1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
32 #include <linux/types.h>
33 #include <linux/if_ether.h>
35 #include "e1000_mac.h"
36 #include "e1000_82575.h"
38 static s32
igb_get_invariants_82575(struct e1000_hw
*);
39 static s32
igb_acquire_phy_82575(struct e1000_hw
*);
40 static void igb_release_phy_82575(struct e1000_hw
*);
41 static s32
igb_acquire_nvm_82575(struct e1000_hw
*);
42 static void igb_release_nvm_82575(struct e1000_hw
*);
43 static s32
igb_check_for_link_82575(struct e1000_hw
*);
44 static s32
igb_get_cfg_done_82575(struct e1000_hw
*);
45 static s32
igb_init_hw_82575(struct e1000_hw
*);
46 static s32
igb_phy_hw_reset_sgmii_82575(struct e1000_hw
*);
47 static s32
igb_read_phy_reg_sgmii_82575(struct e1000_hw
*, u32
, u16
*);
48 static s32
igb_read_phy_reg_82580(struct e1000_hw
*, u32
, u16
*);
49 static s32
igb_write_phy_reg_82580(struct e1000_hw
*, u32
, u16
);
50 static s32
igb_reset_hw_82575(struct e1000_hw
*);
51 static s32
igb_reset_hw_82580(struct e1000_hw
*);
52 static s32
igb_set_d0_lplu_state_82575(struct e1000_hw
*, bool);
53 static s32
igb_setup_copper_link_82575(struct e1000_hw
*);
54 static s32
igb_setup_serdes_link_82575(struct e1000_hw
*);
55 static s32
igb_write_phy_reg_sgmii_82575(struct e1000_hw
*, u32
, u16
);
56 static void igb_clear_hw_cntrs_82575(struct e1000_hw
*);
57 static s32
igb_acquire_swfw_sync_82575(struct e1000_hw
*, u16
);
58 static s32
igb_get_pcs_speed_and_duplex_82575(struct e1000_hw
*, u16
*,
60 static s32
igb_get_phy_id_82575(struct e1000_hw
*);
61 static void igb_release_swfw_sync_82575(struct e1000_hw
*, u16
);
62 static bool igb_sgmii_active_82575(struct e1000_hw
*);
63 static s32
igb_reset_init_script_82575(struct e1000_hw
*);
64 static s32
igb_read_mac_addr_82575(struct e1000_hw
*);
65 static s32
igb_set_pcie_completion_timeout(struct e1000_hw
*hw
);
67 static const u16 e1000_82580_rxpbs_table
[] =
68 { 36, 72, 144, 1, 2, 4, 8, 16,
70 #define E1000_82580_RXPBS_TABLE_SIZE \
71 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
73 static s32
igb_get_invariants_82575(struct e1000_hw
*hw
)
75 struct e1000_phy_info
*phy
= &hw
->phy
;
76 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
77 struct e1000_mac_info
*mac
= &hw
->mac
;
78 struct e1000_dev_spec_82575
* dev_spec
= &hw
->dev_spec
._82575
;
84 switch (hw
->device_id
) {
85 case E1000_DEV_ID_82575EB_COPPER
:
86 case E1000_DEV_ID_82575EB_FIBER_SERDES
:
87 case E1000_DEV_ID_82575GB_QUAD_COPPER
:
88 mac
->type
= e1000_82575
;
90 case E1000_DEV_ID_82576
:
91 case E1000_DEV_ID_82576_NS
:
92 case E1000_DEV_ID_82576_NS_SERDES
:
93 case E1000_DEV_ID_82576_FIBER
:
94 case E1000_DEV_ID_82576_SERDES
:
95 case E1000_DEV_ID_82576_QUAD_COPPER
:
96 case E1000_DEV_ID_82576_QUAD_COPPER_ET2
:
97 case E1000_DEV_ID_82576_SERDES_QUAD
:
98 mac
->type
= e1000_82576
;
100 case E1000_DEV_ID_82580_COPPER
:
101 case E1000_DEV_ID_82580_FIBER
:
102 case E1000_DEV_ID_82580_SERDES
:
103 case E1000_DEV_ID_82580_SGMII
:
104 case E1000_DEV_ID_82580_COPPER_DUAL
:
105 mac
->type
= e1000_82580
;
107 case E1000_DEV_ID_I350_COPPER
:
108 case E1000_DEV_ID_I350_FIBER
:
109 case E1000_DEV_ID_I350_SERDES
:
110 case E1000_DEV_ID_I350_SGMII
:
111 mac
->type
= e1000_i350
;
114 return -E1000_ERR_MAC_INIT
;
120 * The 82575 uses bits 22:23 for link mode. The mode can be changed
121 * based on the EEPROM. We cannot rely upon device ID. There
122 * is no distinguishable difference between fiber and internal
123 * SerDes mode on the 82575. There can be an external PHY attached
124 * on the SGMII interface. For this, we'll set sgmii_active to true.
126 phy
->media_type
= e1000_media_type_copper
;
127 dev_spec
->sgmii_active
= false;
129 ctrl_ext
= rd32(E1000_CTRL_EXT
);
130 switch (ctrl_ext
& E1000_CTRL_EXT_LINK_MODE_MASK
) {
131 case E1000_CTRL_EXT_LINK_MODE_SGMII
:
132 dev_spec
->sgmii_active
= true;
133 ctrl_ext
|= E1000_CTRL_I2C_ENA
;
135 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX
:
136 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES
:
137 hw
->phy
.media_type
= e1000_media_type_internal_serdes
;
138 ctrl_ext
|= E1000_CTRL_I2C_ENA
;
141 ctrl_ext
&= ~E1000_CTRL_I2C_ENA
;
145 wr32(E1000_CTRL_EXT
, ctrl_ext
);
148 * if using i2c make certain the MDICNFG register is cleared to prevent
149 * communications from being misrouted to the mdic registers
151 if ((ctrl_ext
& E1000_CTRL_I2C_ENA
) && (hw
->mac
.type
== e1000_82580
))
152 wr32(E1000_MDICNFG
, 0);
154 /* Set mta register count */
155 mac
->mta_reg_count
= 128;
156 /* Set rar entry count */
157 mac
->rar_entry_count
= E1000_RAR_ENTRIES_82575
;
158 if (mac
->type
== e1000_82576
)
159 mac
->rar_entry_count
= E1000_RAR_ENTRIES_82576
;
160 if (mac
->type
== e1000_82580
)
161 mac
->rar_entry_count
= E1000_RAR_ENTRIES_82580
;
162 if (mac
->type
== e1000_i350
)
163 mac
->rar_entry_count
= E1000_RAR_ENTRIES_I350
;
165 if (mac
->type
>= e1000_82580
)
166 mac
->ops
.reset_hw
= igb_reset_hw_82580
;
168 mac
->ops
.reset_hw
= igb_reset_hw_82575
;
169 /* Set if part includes ASF firmware */
170 mac
->asf_firmware_present
= true;
171 /* Set if manageability features are enabled. */
172 mac
->arc_subsystem_valid
=
173 (rd32(E1000_FWSM
) & E1000_FWSM_MODE_MASK
)
176 /* physical interface link setup */
177 mac
->ops
.setup_physical_interface
=
178 (hw
->phy
.media_type
== e1000_media_type_copper
)
179 ? igb_setup_copper_link_82575
180 : igb_setup_serdes_link_82575
;
182 /* NVM initialization */
183 eecd
= rd32(E1000_EECD
);
185 nvm
->opcode_bits
= 8;
187 switch (nvm
->override
) {
188 case e1000_nvm_override_spi_large
:
190 nvm
->address_bits
= 16;
192 case e1000_nvm_override_spi_small
:
194 nvm
->address_bits
= 8;
197 nvm
->page_size
= eecd
& E1000_EECD_ADDR_BITS
? 32 : 8;
198 nvm
->address_bits
= eecd
& E1000_EECD_ADDR_BITS
? 16 : 8;
202 nvm
->type
= e1000_nvm_eeprom_spi
;
204 size
= (u16
)((eecd
& E1000_EECD_SIZE_EX_MASK
) >>
205 E1000_EECD_SIZE_EX_SHIFT
);
208 * Added to a constant, "size" becomes the left-shift value
209 * for setting word_size.
211 size
+= NVM_WORD_SIZE_BASE_SHIFT
;
213 /* EEPROM access above 16k is unsupported */
216 nvm
->word_size
= 1 << size
;
218 /* if 82576 then initialize mailbox parameters */
219 if (mac
->type
== e1000_82576
)
220 igb_init_mbx_params_pf(hw
);
222 /* setup PHY parameters */
223 if (phy
->media_type
!= e1000_media_type_copper
) {
224 phy
->type
= e1000_phy_none
;
228 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
229 phy
->reset_delay_us
= 100;
231 /* PHY function pointers */
232 if (igb_sgmii_active_82575(hw
)) {
233 phy
->ops
.reset
= igb_phy_hw_reset_sgmii_82575
;
234 phy
->ops
.read_reg
= igb_read_phy_reg_sgmii_82575
;
235 phy
->ops
.write_reg
= igb_write_phy_reg_sgmii_82575
;
236 } else if (hw
->mac
.type
>= e1000_82580
) {
237 phy
->ops
.reset
= igb_phy_hw_reset
;
238 phy
->ops
.read_reg
= igb_read_phy_reg_82580
;
239 phy
->ops
.write_reg
= igb_write_phy_reg_82580
;
241 phy
->ops
.reset
= igb_phy_hw_reset
;
242 phy
->ops
.read_reg
= igb_read_phy_reg_igp
;
243 phy
->ops
.write_reg
= igb_write_phy_reg_igp
;
247 hw
->bus
.func
= (rd32(E1000_STATUS
) & E1000_STATUS_FUNC_MASK
) >>
248 E1000_STATUS_FUNC_SHIFT
;
250 /* Set phy->phy_addr and phy->id. */
251 ret_val
= igb_get_phy_id_82575(hw
);
255 /* Verify phy id and set remaining function pointers */
257 case M88E1111_I_PHY_ID
:
258 phy
->type
= e1000_phy_m88
;
259 phy
->ops
.get_phy_info
= igb_get_phy_info_m88
;
260 phy
->ops
.get_cable_length
= igb_get_cable_length_m88
;
261 phy
->ops
.force_speed_duplex
= igb_phy_force_speed_duplex_m88
;
263 case IGP03E1000_E_PHY_ID
:
264 phy
->type
= e1000_phy_igp_3
;
265 phy
->ops
.get_phy_info
= igb_get_phy_info_igp
;
266 phy
->ops
.get_cable_length
= igb_get_cable_length_igp_2
;
267 phy
->ops
.force_speed_duplex
= igb_phy_force_speed_duplex_igp
;
268 phy
->ops
.set_d0_lplu_state
= igb_set_d0_lplu_state_82575
;
269 phy
->ops
.set_d3_lplu_state
= igb_set_d3_lplu_state
;
271 case I82580_I_PHY_ID
:
273 phy
->type
= e1000_phy_82580
;
274 phy
->ops
.force_speed_duplex
= igb_phy_force_speed_duplex_82580
;
275 phy
->ops
.get_cable_length
= igb_get_cable_length_82580
;
276 phy
->ops
.get_phy_info
= igb_get_phy_info_82580
;
279 return -E1000_ERR_PHY
;
286 * igb_acquire_phy_82575 - Acquire rights to access PHY
287 * @hw: pointer to the HW structure
289 * Acquire access rights to the correct PHY. This is a
290 * function pointer entry point called by the api module.
292 static s32
igb_acquire_phy_82575(struct e1000_hw
*hw
)
294 u16 mask
= E1000_SWFW_PHY0_SM
;
296 if (hw
->bus
.func
== E1000_FUNC_1
)
297 mask
= E1000_SWFW_PHY1_SM
;
299 return igb_acquire_swfw_sync_82575(hw
, mask
);
303 * igb_release_phy_82575 - Release rights to access PHY
304 * @hw: pointer to the HW structure
306 * A wrapper to release access rights to the correct PHY. This is a
307 * function pointer entry point called by the api module.
309 static void igb_release_phy_82575(struct e1000_hw
*hw
)
311 u16 mask
= E1000_SWFW_PHY0_SM
;
313 if (hw
->bus
.func
== E1000_FUNC_1
)
314 mask
= E1000_SWFW_PHY1_SM
;
316 igb_release_swfw_sync_82575(hw
, mask
);
320 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
321 * @hw: pointer to the HW structure
322 * @offset: register offset to be read
323 * @data: pointer to the read data
325 * Reads the PHY register at offset using the serial gigabit media independent
326 * interface and stores the retrieved information in data.
328 static s32
igb_read_phy_reg_sgmii_82575(struct e1000_hw
*hw
, u32 offset
,
331 s32 ret_val
= -E1000_ERR_PARAM
;
333 if (offset
> E1000_MAX_SGMII_PHY_REG_ADDR
) {
334 hw_dbg("PHY Address %u is out of range\n", offset
);
338 ret_val
= hw
->phy
.ops
.acquire(hw
);
342 ret_val
= igb_read_phy_reg_i2c(hw
, offset
, data
);
344 hw
->phy
.ops
.release(hw
);
351 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
352 * @hw: pointer to the HW structure
353 * @offset: register offset to write to
354 * @data: data to write at register offset
356 * Writes the data to PHY register at the offset using the serial gigabit
357 * media independent interface.
359 static s32
igb_write_phy_reg_sgmii_82575(struct e1000_hw
*hw
, u32 offset
,
362 s32 ret_val
= -E1000_ERR_PARAM
;
365 if (offset
> E1000_MAX_SGMII_PHY_REG_ADDR
) {
366 hw_dbg("PHY Address %d is out of range\n", offset
);
370 ret_val
= hw
->phy
.ops
.acquire(hw
);
374 ret_val
= igb_write_phy_reg_i2c(hw
, offset
, data
);
376 hw
->phy
.ops
.release(hw
);
383 * igb_get_phy_id_82575 - Retrieve PHY addr and id
384 * @hw: pointer to the HW structure
386 * Retrieves the PHY address and ID for both PHY's which do and do not use
389 static s32
igb_get_phy_id_82575(struct e1000_hw
*hw
)
391 struct e1000_phy_info
*phy
= &hw
->phy
;
397 * For SGMII PHYs, we try the list of possible addresses until
398 * we find one that works. For non-SGMII PHYs
399 * (e.g. integrated copper PHYs), an address of 1 should
400 * work. The result of this function should mean phy->phy_addr
401 * and phy->id are set correctly.
403 if (!(igb_sgmii_active_82575(hw
))) {
405 ret_val
= igb_get_phy_id(hw
);
409 /* Power on sgmii phy if it is disabled */
410 ctrl_ext
= rd32(E1000_CTRL_EXT
);
411 wr32(E1000_CTRL_EXT
, ctrl_ext
& ~E1000_CTRL_EXT_SDP3_DATA
);
416 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
417 * Therefore, we need to test 1-7
419 for (phy
->addr
= 1; phy
->addr
< 8; phy
->addr
++) {
420 ret_val
= igb_read_phy_reg_sgmii_82575(hw
, PHY_ID1
, &phy_id
);
422 hw_dbg("Vendor ID 0x%08X read at address %u\n",
425 * At the time of this writing, The M88 part is
426 * the only supported SGMII PHY product.
428 if (phy_id
== M88_VENDOR
)
431 hw_dbg("PHY address %u was unreadable\n", phy
->addr
);
435 /* A valid PHY type couldn't be found. */
436 if (phy
->addr
== 8) {
438 ret_val
= -E1000_ERR_PHY
;
441 ret_val
= igb_get_phy_id(hw
);
444 /* restore previous sfp cage power state */
445 wr32(E1000_CTRL_EXT
, ctrl_ext
);
452 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
453 * @hw: pointer to the HW structure
455 * Resets the PHY using the serial gigabit media independent interface.
457 static s32
igb_phy_hw_reset_sgmii_82575(struct e1000_hw
*hw
)
462 * This isn't a true "hard" reset, but is the only reset
463 * available to us at this time.
466 hw_dbg("Soft resetting SGMII attached PHY...\n");
469 * SFP documentation requires the following to configure the SPF module
470 * to work on SGMII. No further documentation is given.
472 ret_val
= hw
->phy
.ops
.write_reg(hw
, 0x1B, 0x8084);
476 ret_val
= igb_phy_sw_reset(hw
);
483 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
484 * @hw: pointer to the HW structure
485 * @active: true to enable LPLU, false to disable
487 * Sets the LPLU D0 state according to the active flag. When
488 * activating LPLU this function also disables smart speed
489 * and vice versa. LPLU will not be activated unless the
490 * device autonegotiation advertisement meets standards of
491 * either 10 or 10/100 or 10/100/1000 at all duplexes.
492 * This is a function pointer entry point only called by
493 * PHY setup routines.
495 static s32
igb_set_d0_lplu_state_82575(struct e1000_hw
*hw
, bool active
)
497 struct e1000_phy_info
*phy
= &hw
->phy
;
501 ret_val
= phy
->ops
.read_reg(hw
, IGP02E1000_PHY_POWER_MGMT
, &data
);
506 data
|= IGP02E1000_PM_D0_LPLU
;
507 ret_val
= phy
->ops
.write_reg(hw
, IGP02E1000_PHY_POWER_MGMT
,
512 /* When LPLU is enabled, we should disable SmartSpeed */
513 ret_val
= phy
->ops
.read_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
515 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
516 ret_val
= phy
->ops
.write_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
521 data
&= ~IGP02E1000_PM_D0_LPLU
;
522 ret_val
= phy
->ops
.write_reg(hw
, IGP02E1000_PHY_POWER_MGMT
,
525 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
526 * during Dx states where the power conservation is most
527 * important. During driver activity we should enable
528 * SmartSpeed, so performance is maintained.
530 if (phy
->smart_speed
== e1000_smart_speed_on
) {
531 ret_val
= phy
->ops
.read_reg(hw
,
532 IGP01E1000_PHY_PORT_CONFIG
, &data
);
536 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
537 ret_val
= phy
->ops
.write_reg(hw
,
538 IGP01E1000_PHY_PORT_CONFIG
, data
);
541 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
542 ret_val
= phy
->ops
.read_reg(hw
,
543 IGP01E1000_PHY_PORT_CONFIG
, &data
);
547 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
548 ret_val
= phy
->ops
.write_reg(hw
,
549 IGP01E1000_PHY_PORT_CONFIG
, data
);
560 * igb_acquire_nvm_82575 - Request for access to EEPROM
561 * @hw: pointer to the HW structure
563 * Acquire the necessary semaphores for exclusive access to the EEPROM.
564 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
565 * Return successful if access grant bit set, else clear the request for
566 * EEPROM access and return -E1000_ERR_NVM (-1).
568 static s32
igb_acquire_nvm_82575(struct e1000_hw
*hw
)
572 ret_val
= igb_acquire_swfw_sync_82575(hw
, E1000_SWFW_EEP_SM
);
576 ret_val
= igb_acquire_nvm(hw
);
579 igb_release_swfw_sync_82575(hw
, E1000_SWFW_EEP_SM
);
586 * igb_release_nvm_82575 - Release exclusive access to EEPROM
587 * @hw: pointer to the HW structure
589 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
590 * then release the semaphores acquired.
592 static void igb_release_nvm_82575(struct e1000_hw
*hw
)
595 igb_release_swfw_sync_82575(hw
, E1000_SWFW_EEP_SM
);
599 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
600 * @hw: pointer to the HW structure
601 * @mask: specifies which semaphore to acquire
603 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
604 * will also specify which port we're acquiring the lock for.
606 static s32
igb_acquire_swfw_sync_82575(struct e1000_hw
*hw
, u16 mask
)
610 u32 fwmask
= mask
<< 16;
612 s32 i
= 0, timeout
= 200; /* FIXME: find real value to use here */
614 while (i
< timeout
) {
615 if (igb_get_hw_semaphore(hw
)) {
616 ret_val
= -E1000_ERR_SWFW_SYNC
;
620 swfw_sync
= rd32(E1000_SW_FW_SYNC
);
621 if (!(swfw_sync
& (fwmask
| swmask
)))
625 * Firmware currently using resource (fwmask)
626 * or other software thread using resource (swmask)
628 igb_put_hw_semaphore(hw
);
634 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
635 ret_val
= -E1000_ERR_SWFW_SYNC
;
640 wr32(E1000_SW_FW_SYNC
, swfw_sync
);
642 igb_put_hw_semaphore(hw
);
649 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
650 * @hw: pointer to the HW structure
651 * @mask: specifies which semaphore to acquire
653 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
654 * will also specify which port we're releasing the lock for.
656 static void igb_release_swfw_sync_82575(struct e1000_hw
*hw
, u16 mask
)
660 while (igb_get_hw_semaphore(hw
) != 0);
663 swfw_sync
= rd32(E1000_SW_FW_SYNC
);
665 wr32(E1000_SW_FW_SYNC
, swfw_sync
);
667 igb_put_hw_semaphore(hw
);
671 * igb_get_cfg_done_82575 - Read config done bit
672 * @hw: pointer to the HW structure
674 * Read the management control register for the config done bit for
675 * completion status. NOTE: silicon which is EEPROM-less will fail trying
676 * to read the config done bit, so an error is *ONLY* logged and returns
677 * 0. If we were to return with error, EEPROM-less silicon
678 * would not be able to be reset or change link.
680 static s32
igb_get_cfg_done_82575(struct e1000_hw
*hw
)
682 s32 timeout
= PHY_CFG_TIMEOUT
;
684 u32 mask
= E1000_NVM_CFG_DONE_PORT_0
;
686 if (hw
->bus
.func
== 1)
687 mask
= E1000_NVM_CFG_DONE_PORT_1
;
688 else if (hw
->bus
.func
== E1000_FUNC_2
)
689 mask
= E1000_NVM_CFG_DONE_PORT_2
;
690 else if (hw
->bus
.func
== E1000_FUNC_3
)
691 mask
= E1000_NVM_CFG_DONE_PORT_3
;
694 if (rd32(E1000_EEMNGCTL
) & mask
)
700 hw_dbg("MNG configuration cycle has not completed.\n");
702 /* If EEPROM is not marked present, init the PHY manually */
703 if (((rd32(E1000_EECD
) & E1000_EECD_PRES
) == 0) &&
704 (hw
->phy
.type
== e1000_phy_igp_3
))
705 igb_phy_init_script_igp3(hw
);
711 * igb_check_for_link_82575 - Check for link
712 * @hw: pointer to the HW structure
714 * If sgmii is enabled, then use the pcs register to determine link, otherwise
715 * use the generic interface for determining link.
717 static s32
igb_check_for_link_82575(struct e1000_hw
*hw
)
722 if (hw
->phy
.media_type
!= e1000_media_type_copper
) {
723 ret_val
= igb_get_pcs_speed_and_duplex_82575(hw
, &speed
,
726 * Use this flag to determine if link needs to be checked or
727 * not. If we have link clear the flag so that we do not
728 * continue to check for link.
730 hw
->mac
.get_link_status
= !hw
->mac
.serdes_has_link
;
732 ret_val
= igb_check_for_copper_link(hw
);
739 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
740 * @hw: pointer to the HW structure
742 void igb_power_up_serdes_link_82575(struct e1000_hw
*hw
)
747 if ((hw
->phy
.media_type
!= e1000_media_type_internal_serdes
) &&
748 !igb_sgmii_active_82575(hw
))
751 /* Enable PCS to turn on link */
752 reg
= rd32(E1000_PCS_CFG0
);
753 reg
|= E1000_PCS_CFG_PCS_EN
;
754 wr32(E1000_PCS_CFG0
, reg
);
756 /* Power up the laser */
757 reg
= rd32(E1000_CTRL_EXT
);
758 reg
&= ~E1000_CTRL_EXT_SDP3_DATA
;
759 wr32(E1000_CTRL_EXT
, reg
);
761 /* flush the write to verify completion */
767 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
768 * @hw: pointer to the HW structure
769 * @speed: stores the current speed
770 * @duplex: stores the current duplex
772 * Using the physical coding sub-layer (PCS), retrieve the current speed and
773 * duplex, then store the values in the pointers provided.
775 static s32
igb_get_pcs_speed_and_duplex_82575(struct e1000_hw
*hw
, u16
*speed
,
778 struct e1000_mac_info
*mac
= &hw
->mac
;
781 /* Set up defaults for the return values of this function */
782 mac
->serdes_has_link
= false;
787 * Read the PCS Status register for link state. For non-copper mode,
788 * the status register is not accurate. The PCS status register is
791 pcs
= rd32(E1000_PCS_LSTAT
);
794 * The link up bit determines when link is up on autoneg. The sync ok
795 * gets set once both sides sync up and agree upon link. Stable link
796 * can be determined by checking for both link up and link sync ok
798 if ((pcs
& E1000_PCS_LSTS_LINK_OK
) && (pcs
& E1000_PCS_LSTS_SYNK_OK
)) {
799 mac
->serdes_has_link
= true;
801 /* Detect and store PCS speed */
802 if (pcs
& E1000_PCS_LSTS_SPEED_1000
) {
804 } else if (pcs
& E1000_PCS_LSTS_SPEED_100
) {
810 /* Detect and store PCS duplex */
811 if (pcs
& E1000_PCS_LSTS_DUPLEX_FULL
) {
812 *duplex
= FULL_DUPLEX
;
814 *duplex
= HALF_DUPLEX
;
822 * igb_shutdown_serdes_link_82575 - Remove link during power down
823 * @hw: pointer to the HW structure
825 * In the case of fiber serdes, shut down optics and PCS on driver unload
826 * when management pass thru is not enabled.
828 void igb_shutdown_serdes_link_82575(struct e1000_hw
*hw
)
832 if (hw
->phy
.media_type
!= e1000_media_type_internal_serdes
&&
833 igb_sgmii_active_82575(hw
))
836 if (!igb_enable_mng_pass_thru(hw
)) {
837 /* Disable PCS to turn off link */
838 reg
= rd32(E1000_PCS_CFG0
);
839 reg
&= ~E1000_PCS_CFG_PCS_EN
;
840 wr32(E1000_PCS_CFG0
, reg
);
842 /* shutdown the laser */
843 reg
= rd32(E1000_CTRL_EXT
);
844 reg
|= E1000_CTRL_EXT_SDP3_DATA
;
845 wr32(E1000_CTRL_EXT
, reg
);
847 /* flush the write to verify completion */
854 * igb_reset_hw_82575 - Reset hardware
855 * @hw: pointer to the HW structure
857 * This resets the hardware into a known state. This is a
858 * function pointer entry point called by the api module.
860 static s32
igb_reset_hw_82575(struct e1000_hw
*hw
)
866 * Prevent the PCI-E bus from sticking if there is no TLP connection
867 * on the last TLP read/write transaction when MAC is reset.
869 ret_val
= igb_disable_pcie_master(hw
);
871 hw_dbg("PCI-E Master disable polling has failed.\n");
873 /* set the completion timeout for interface */
874 ret_val
= igb_set_pcie_completion_timeout(hw
);
876 hw_dbg("PCI-E Set completion timeout has failed.\n");
879 hw_dbg("Masking off all interrupts\n");
880 wr32(E1000_IMC
, 0xffffffff);
883 wr32(E1000_TCTL
, E1000_TCTL_PSP
);
888 ctrl
= rd32(E1000_CTRL
);
890 hw_dbg("Issuing a global reset to MAC\n");
891 wr32(E1000_CTRL
, ctrl
| E1000_CTRL_RST
);
893 ret_val
= igb_get_auto_rd_done(hw
);
896 * When auto config read does not complete, do not
897 * return with an error. This can happen in situations
898 * where there is no eeprom and prevents getting link.
900 hw_dbg("Auto Read Done did not complete\n");
903 /* If EEPROM is not present, run manual init scripts */
904 if ((rd32(E1000_EECD
) & E1000_EECD_PRES
) == 0)
905 igb_reset_init_script_82575(hw
);
907 /* Clear any pending interrupt events. */
908 wr32(E1000_IMC
, 0xffffffff);
909 icr
= rd32(E1000_ICR
);
911 /* Install any alternate MAC address into RAR0 */
912 ret_val
= igb_check_alt_mac_addr(hw
);
918 * igb_init_hw_82575 - Initialize hardware
919 * @hw: pointer to the HW structure
921 * This inits the hardware readying it for operation.
923 static s32
igb_init_hw_82575(struct e1000_hw
*hw
)
925 struct e1000_mac_info
*mac
= &hw
->mac
;
927 u16 i
, rar_count
= mac
->rar_entry_count
;
929 /* Initialize identification LED */
930 ret_val
= igb_id_led_init(hw
);
932 hw_dbg("Error initializing identification LED\n");
933 /* This is not fatal and we should not stop init due to this */
936 /* Disabling VLAN filtering */
937 hw_dbg("Initializing the IEEE VLAN\n");
940 /* Setup the receive address */
941 igb_init_rx_addrs(hw
, rar_count
);
943 /* Zero out the Multicast HASH table */
944 hw_dbg("Zeroing the MTA\n");
945 for (i
= 0; i
< mac
->mta_reg_count
; i
++)
946 array_wr32(E1000_MTA
, i
, 0);
948 /* Zero out the Unicast HASH table */
949 hw_dbg("Zeroing the UTA\n");
950 for (i
= 0; i
< mac
->uta_reg_count
; i
++)
951 array_wr32(E1000_UTA
, i
, 0);
953 /* Setup link and flow control */
954 ret_val
= igb_setup_link(hw
);
957 * Clear all of the statistics registers (clear on read). It is
958 * important that we do this after we have tried to establish link
959 * because the symbol error count will increment wildly if there
962 igb_clear_hw_cntrs_82575(hw
);
968 * igb_setup_copper_link_82575 - Configure copper link settings
969 * @hw: pointer to the HW structure
971 * Configures the link for auto-neg or forced speed and duplex. Then we check
972 * for link, once link is established calls to configure collision distance
973 * and flow control are called.
975 static s32
igb_setup_copper_link_82575(struct e1000_hw
*hw
)
980 ctrl
= rd32(E1000_CTRL
);
981 ctrl
|= E1000_CTRL_SLU
;
982 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
983 wr32(E1000_CTRL
, ctrl
);
985 ret_val
= igb_setup_serdes_link_82575(hw
);
989 if (igb_sgmii_active_82575(hw
) && !hw
->phy
.reset_disable
) {
990 /* allow time for SFP cage time to power up phy */
993 ret_val
= hw
->phy
.ops
.reset(hw
);
995 hw_dbg("Error resetting the PHY.\n");
999 switch (hw
->phy
.type
) {
1001 ret_val
= igb_copper_link_setup_m88(hw
);
1003 case e1000_phy_igp_3
:
1004 ret_val
= igb_copper_link_setup_igp(hw
);
1006 case e1000_phy_82580
:
1007 ret_val
= igb_copper_link_setup_82580(hw
);
1010 ret_val
= -E1000_ERR_PHY
;
1017 ret_val
= igb_setup_copper_link(hw
);
1023 * igb_setup_serdes_link_82575 - Setup link for serdes
1024 * @hw: pointer to the HW structure
1026 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1027 * used on copper connections where the serialized gigabit media independent
1028 * interface (sgmii), or serdes fiber is being used. Configures the link
1029 * for auto-negotiation or forces speed/duplex.
1031 static s32
igb_setup_serdes_link_82575(struct e1000_hw
*hw
)
1033 u32 ctrl_ext
, ctrl_reg
, reg
;
1036 if ((hw
->phy
.media_type
!= e1000_media_type_internal_serdes
) &&
1037 !igb_sgmii_active_82575(hw
))
1041 * On the 82575, SerDes loopback mode persists until it is
1042 * explicitly turned off or a power cycle is performed. A read to
1043 * the register does not indicate its status. Therefore, we ensure
1044 * loopback mode is disabled during initialization.
1046 wr32(E1000_SCTL
, E1000_SCTL_DISABLE_SERDES_LOOPBACK
);
1048 /* power on the sfp cage if present */
1049 ctrl_ext
= rd32(E1000_CTRL_EXT
);
1050 ctrl_ext
&= ~E1000_CTRL_EXT_SDP3_DATA
;
1051 wr32(E1000_CTRL_EXT
, ctrl_ext
);
1053 ctrl_reg
= rd32(E1000_CTRL
);
1054 ctrl_reg
|= E1000_CTRL_SLU
;
1056 if (hw
->mac
.type
== e1000_82575
|| hw
->mac
.type
== e1000_82576
) {
1057 /* set both sw defined pins */
1058 ctrl_reg
|= E1000_CTRL_SWDPIN0
| E1000_CTRL_SWDPIN1
;
1060 /* Set switch control to serdes energy detect */
1061 reg
= rd32(E1000_CONNSW
);
1062 reg
|= E1000_CONNSW_ENRGSRC
;
1063 wr32(E1000_CONNSW
, reg
);
1066 reg
= rd32(E1000_PCS_LCTL
);
1068 /* default pcs_autoneg to the same setting as mac autoneg */
1069 pcs_autoneg
= hw
->mac
.autoneg
;
1071 switch (ctrl_ext
& E1000_CTRL_EXT_LINK_MODE_MASK
) {
1072 case E1000_CTRL_EXT_LINK_MODE_SGMII
:
1073 /* sgmii mode lets the phy handle forcing speed/duplex */
1075 /* autoneg time out should be disabled for SGMII mode */
1076 reg
&= ~(E1000_PCS_LCTL_AN_TIMEOUT
);
1078 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX
:
1079 /* disable PCS autoneg and support parallel detect only */
1080 pcs_autoneg
= false;
1083 * non-SGMII modes only supports a speed of 1000/Full for the
1084 * link so it is best to just force the MAC and let the pcs
1085 * link either autoneg or be forced to 1000/Full
1087 ctrl_reg
|= E1000_CTRL_SPD_1000
| E1000_CTRL_FRCSPD
|
1088 E1000_CTRL_FD
| E1000_CTRL_FRCDPX
;
1090 /* set speed of 1000/Full if speed/duplex is forced */
1091 reg
|= E1000_PCS_LCTL_FSV_1000
| E1000_PCS_LCTL_FDV_FULL
;
1095 wr32(E1000_CTRL
, ctrl_reg
);
1098 * New SerDes mode allows for forcing speed or autonegotiating speed
1099 * at 1gb. Autoneg should be default set by most drivers. This is the
1100 * mode that will be compatible with older link partners and switches.
1101 * However, both are supported by the hardware and some drivers/tools.
1103 reg
&= ~(E1000_PCS_LCTL_AN_ENABLE
| E1000_PCS_LCTL_FLV_LINK_UP
|
1104 E1000_PCS_LCTL_FSD
| E1000_PCS_LCTL_FORCE_LINK
);
1107 * We force flow control to prevent the CTRL register values from being
1108 * overwritten by the autonegotiated flow control values
1110 reg
|= E1000_PCS_LCTL_FORCE_FCTRL
;
1113 /* Set PCS register for autoneg */
1114 reg
|= E1000_PCS_LCTL_AN_ENABLE
| /* Enable Autoneg */
1115 E1000_PCS_LCTL_AN_RESTART
; /* Restart autoneg */
1116 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg
);
1118 /* Set PCS register for forced link */
1119 reg
|= E1000_PCS_LCTL_FSD
; /* Force Speed */
1121 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg
);
1124 wr32(E1000_PCS_LCTL
, reg
);
1126 if (!igb_sgmii_active_82575(hw
))
1127 igb_force_mac_fc(hw
);
1133 * igb_sgmii_active_82575 - Return sgmii state
1134 * @hw: pointer to the HW structure
1136 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1137 * which can be enabled for use in the embedded applications. Simply
1138 * return the current state of the sgmii interface.
1140 static bool igb_sgmii_active_82575(struct e1000_hw
*hw
)
1142 struct e1000_dev_spec_82575
*dev_spec
= &hw
->dev_spec
._82575
;
1143 return dev_spec
->sgmii_active
;
1147 * igb_reset_init_script_82575 - Inits HW defaults after reset
1148 * @hw: pointer to the HW structure
1150 * Inits recommended HW defaults after a reset when there is no EEPROM
1151 * detected. This is only for the 82575.
1153 static s32
igb_reset_init_script_82575(struct e1000_hw
*hw
)
1155 if (hw
->mac
.type
== e1000_82575
) {
1156 hw_dbg("Running reset init script for 82575\n");
1157 /* SerDes configuration via SERDESCTRL */
1158 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x00, 0x0C);
1159 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x01, 0x78);
1160 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x1B, 0x23);
1161 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x23, 0x15);
1163 /* CCM configuration via CCMCTL register */
1164 igb_write_8bit_ctrl_reg(hw
, E1000_CCMCTL
, 0x14, 0x00);
1165 igb_write_8bit_ctrl_reg(hw
, E1000_CCMCTL
, 0x10, 0x00);
1167 /* PCIe lanes configuration */
1168 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x00, 0xEC);
1169 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x61, 0xDF);
1170 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x34, 0x05);
1171 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x2F, 0x81);
1173 /* PCIe PLL Configuration */
1174 igb_write_8bit_ctrl_reg(hw
, E1000_SCCTL
, 0x02, 0x47);
1175 igb_write_8bit_ctrl_reg(hw
, E1000_SCCTL
, 0x14, 0x00);
1176 igb_write_8bit_ctrl_reg(hw
, E1000_SCCTL
, 0x10, 0x00);
1183 * igb_read_mac_addr_82575 - Read device MAC address
1184 * @hw: pointer to the HW structure
1186 static s32
igb_read_mac_addr_82575(struct e1000_hw
*hw
)
1191 * If there's an alternate MAC address place it in RAR0
1192 * so that it will override the Si installed default perm
1195 ret_val
= igb_check_alt_mac_addr(hw
);
1199 ret_val
= igb_read_mac_addr(hw
);
1206 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1207 * @hw: pointer to the HW structure
1209 * In the case of a PHY power down to save power, or to turn off link during a
1210 * driver unload, or wake on lan is not enabled, remove the link.
1212 void igb_power_down_phy_copper_82575(struct e1000_hw
*hw
)
1214 /* If the management interface is not enabled, then power down */
1215 if (!(igb_enable_mng_pass_thru(hw
) || igb_check_reset_block(hw
)))
1216 igb_power_down_phy_copper(hw
);
1220 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1221 * @hw: pointer to the HW structure
1223 * Clears the hardware counters by reading the counter registers.
1225 static void igb_clear_hw_cntrs_82575(struct e1000_hw
*hw
)
1227 igb_clear_hw_cntrs_base(hw
);
1233 rd32(E1000_PRC1023
);
1234 rd32(E1000_PRC1522
);
1239 rd32(E1000_PTC1023
);
1240 rd32(E1000_PTC1522
);
1242 rd32(E1000_ALGNERRC
);
1245 rd32(E1000_CEXTERR
);
1256 rd32(E1000_ICRXPTC
);
1257 rd32(E1000_ICRXATC
);
1258 rd32(E1000_ICTXPTC
);
1259 rd32(E1000_ICTXATC
);
1260 rd32(E1000_ICTXQEC
);
1261 rd32(E1000_ICTXQMTC
);
1262 rd32(E1000_ICRXDMTC
);
1269 rd32(E1000_HTCBDPC
);
1274 rd32(E1000_LENERRS
);
1276 /* This register should not be read in copper configurations */
1277 if (hw
->phy
.media_type
== e1000_media_type_internal_serdes
||
1278 igb_sgmii_active_82575(hw
))
1283 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1284 * @hw: pointer to the HW structure
1286 * After rx enable if managability is enabled then there is likely some
1287 * bad data at the start of the fifo and possibly in the DMA fifo. This
1288 * function clears the fifos and flushes any packets that came in as rx was
1291 void igb_rx_fifo_flush_82575(struct e1000_hw
*hw
)
1293 u32 rctl
, rlpml
, rxdctl
[4], rfctl
, temp_rctl
, rx_enabled
;
1296 if (hw
->mac
.type
!= e1000_82575
||
1297 !(rd32(E1000_MANC
) & E1000_MANC_RCV_TCO_EN
))
1300 /* Disable all RX queues */
1301 for (i
= 0; i
< 4; i
++) {
1302 rxdctl
[i
] = rd32(E1000_RXDCTL(i
));
1303 wr32(E1000_RXDCTL(i
),
1304 rxdctl
[i
] & ~E1000_RXDCTL_QUEUE_ENABLE
);
1306 /* Poll all queues to verify they have shut down */
1307 for (ms_wait
= 0; ms_wait
< 10; ms_wait
++) {
1310 for (i
= 0; i
< 4; i
++)
1311 rx_enabled
|= rd32(E1000_RXDCTL(i
));
1312 if (!(rx_enabled
& E1000_RXDCTL_QUEUE_ENABLE
))
1317 hw_dbg("Queue disable timed out after 10ms\n");
1319 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1320 * incoming packets are rejected. Set enable and wait 2ms so that
1321 * any packet that was coming in as RCTL.EN was set is flushed
1323 rfctl
= rd32(E1000_RFCTL
);
1324 wr32(E1000_RFCTL
, rfctl
& ~E1000_RFCTL_LEF
);
1326 rlpml
= rd32(E1000_RLPML
);
1327 wr32(E1000_RLPML
, 0);
1329 rctl
= rd32(E1000_RCTL
);
1330 temp_rctl
= rctl
& ~(E1000_RCTL_EN
| E1000_RCTL_SBP
);
1331 temp_rctl
|= E1000_RCTL_LPE
;
1333 wr32(E1000_RCTL
, temp_rctl
);
1334 wr32(E1000_RCTL
, temp_rctl
| E1000_RCTL_EN
);
1338 /* Enable RX queues that were previously enabled and restore our
1341 for (i
= 0; i
< 4; i
++)
1342 wr32(E1000_RXDCTL(i
), rxdctl
[i
]);
1343 wr32(E1000_RCTL
, rctl
);
1346 wr32(E1000_RLPML
, rlpml
);
1347 wr32(E1000_RFCTL
, rfctl
);
1349 /* Flush receive errors generated by workaround */
1356 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1357 * @hw: pointer to the HW structure
1359 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1360 * however the hardware default for these parts is 500us to 1ms which is less
1361 * than the 10ms recommended by the pci-e spec. To address this we need to
1362 * increase the value to either 10ms to 200ms for capability version 1 config,
1363 * or 16ms to 55ms for version 2.
1365 static s32
igb_set_pcie_completion_timeout(struct e1000_hw
*hw
)
1367 u32 gcr
= rd32(E1000_GCR
);
1371 /* only take action if timeout value is defaulted to 0 */
1372 if (gcr
& E1000_GCR_CMPL_TMOUT_MASK
)
1376 * if capababilities version is type 1 we can write the
1377 * timeout of 10ms to 200ms through the GCR register
1379 if (!(gcr
& E1000_GCR_CAP_VER2
)) {
1380 gcr
|= E1000_GCR_CMPL_TMOUT_10ms
;
1385 * for version 2 capabilities we need to write the config space
1386 * directly in order to set the completion timeout value for
1389 ret_val
= igb_read_pcie_cap_reg(hw
, PCIE_DEVICE_CONTROL2
,
1394 pcie_devctl2
|= PCIE_DEVICE_CONTROL2_16ms
;
1396 ret_val
= igb_write_pcie_cap_reg(hw
, PCIE_DEVICE_CONTROL2
,
1399 /* disable completion timeout resend */
1400 gcr
&= ~E1000_GCR_CMPL_TMOUT_RESEND
;
1402 wr32(E1000_GCR
, gcr
);
1407 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
1408 * @hw: pointer to the hardware struct
1409 * @enable: state to enter, either enabled or disabled
1411 * enables/disables L2 switch loopback functionality.
1413 void igb_vmdq_set_loopback_pf(struct e1000_hw
*hw
, bool enable
)
1415 u32 dtxswc
= rd32(E1000_DTXSWC
);
1418 dtxswc
|= E1000_DTXSWC_VMDQ_LOOPBACK_EN
;
1420 dtxswc
&= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN
;
1422 wr32(E1000_DTXSWC
, dtxswc
);
1426 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
1427 * @hw: pointer to the hardware struct
1428 * @enable: state to enter, either enabled or disabled
1430 * enables/disables replication of packets across multiple pools.
1432 void igb_vmdq_set_replication_pf(struct e1000_hw
*hw
, bool enable
)
1434 u32 vt_ctl
= rd32(E1000_VT_CTL
);
1437 vt_ctl
|= E1000_VT_CTL_VM_REPL_EN
;
1439 vt_ctl
&= ~E1000_VT_CTL_VM_REPL_EN
;
1441 wr32(E1000_VT_CTL
, vt_ctl
);
1445 * igb_read_phy_reg_82580 - Read 82580 MDI control register
1446 * @hw: pointer to the HW structure
1447 * @offset: register offset to be read
1448 * @data: pointer to the read data
1450 * Reads the MDI control register in the PHY at offset and stores the
1451 * information read to data.
1453 static s32
igb_read_phy_reg_82580(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
1458 ret_val
= hw
->phy
.ops
.acquire(hw
);
1462 ret_val
= igb_read_phy_reg_mdic(hw
, offset
, data
);
1464 hw
->phy
.ops
.release(hw
);
1471 * igb_write_phy_reg_82580 - Write 82580 MDI control register
1472 * @hw: pointer to the HW structure
1473 * @offset: register offset to write to
1474 * @data: data to write to register at offset
1476 * Writes data to MDI control register in the PHY at offset.
1478 static s32
igb_write_phy_reg_82580(struct e1000_hw
*hw
, u32 offset
, u16 data
)
1483 ret_val
= hw
->phy
.ops
.acquire(hw
);
1487 ret_val
= igb_write_phy_reg_mdic(hw
, offset
, data
);
1489 hw
->phy
.ops
.release(hw
);
1496 * igb_reset_hw_82580 - Reset hardware
1497 * @hw: pointer to the HW structure
1499 * This resets function or entire device (all ports, etc.)
1502 static s32
igb_reset_hw_82580(struct e1000_hw
*hw
)
1505 /* BH SW mailbox bit in SW_FW_SYNC */
1506 u16 swmbsw_mask
= E1000_SW_SYNCH_MB
;
1508 bool global_device_reset
= hw
->dev_spec
._82575
.global_device_reset
;
1511 hw
->dev_spec
._82575
.global_device_reset
= false;
1513 /* Get current control state. */
1514 ctrl
= rd32(E1000_CTRL
);
1517 * Prevent the PCI-E bus from sticking if there is no TLP connection
1518 * on the last TLP read/write transaction when MAC is reset.
1520 ret_val
= igb_disable_pcie_master(hw
);
1522 hw_dbg("PCI-E Master disable polling has failed.\n");
1524 hw_dbg("Masking off all interrupts\n");
1525 wr32(E1000_IMC
, 0xffffffff);
1526 wr32(E1000_RCTL
, 0);
1527 wr32(E1000_TCTL
, E1000_TCTL_PSP
);
1532 /* Determine whether or not a global dev reset is requested */
1533 if (global_device_reset
&&
1534 igb_acquire_swfw_sync_82575(hw
, swmbsw_mask
))
1535 global_device_reset
= false;
1537 if (global_device_reset
&&
1538 !(rd32(E1000_STATUS
) & E1000_STAT_DEV_RST_SET
))
1539 ctrl
|= E1000_CTRL_DEV_RST
;
1541 ctrl
|= E1000_CTRL_RST
;
1543 wr32(E1000_CTRL
, ctrl
);
1545 /* Add delay to insure DEV_RST has time to complete */
1546 if (global_device_reset
)
1549 ret_val
= igb_get_auto_rd_done(hw
);
1552 * When auto config read does not complete, do not
1553 * return with an error. This can happen in situations
1554 * where there is no eeprom and prevents getting link.
1556 hw_dbg("Auto Read Done did not complete\n");
1559 /* If EEPROM is not present, run manual init scripts */
1560 if ((rd32(E1000_EECD
) & E1000_EECD_PRES
) == 0)
1561 igb_reset_init_script_82575(hw
);
1563 /* clear global device reset status bit */
1564 wr32(E1000_STATUS
, E1000_STAT_DEV_RST_SET
);
1566 /* Clear any pending interrupt events. */
1567 wr32(E1000_IMC
, 0xffffffff);
1568 icr
= rd32(E1000_ICR
);
1570 /* Install any alternate MAC address into RAR0 */
1571 ret_val
= igb_check_alt_mac_addr(hw
);
1573 /* Release semaphore */
1574 if (global_device_reset
)
1575 igb_release_swfw_sync_82575(hw
, swmbsw_mask
);
1581 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
1582 * @data: data received by reading RXPBS register
1584 * The 82580 uses a table based approach for packet buffer allocation sizes.
1585 * This function converts the retrieved value into the correct table value
1586 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
1587 * 0x0 36 72 144 1 2 4 8 16
1588 * 0x8 35 70 140 rsv rsv rsv rsv rsv
1590 u16
igb_rxpbs_adjust_82580(u32 data
)
1594 if (data
< E1000_82580_RXPBS_TABLE_SIZE
)
1595 ret_val
= e1000_82580_rxpbs_table
[data
];
1600 static struct e1000_mac_operations e1000_mac_ops_82575
= {
1601 .init_hw
= igb_init_hw_82575
,
1602 .check_for_link
= igb_check_for_link_82575
,
1603 .rar_set
= igb_rar_set
,
1604 .read_mac_addr
= igb_read_mac_addr_82575
,
1605 .get_speed_and_duplex
= igb_get_speed_and_duplex_copper
,
1608 static struct e1000_phy_operations e1000_phy_ops_82575
= {
1609 .acquire
= igb_acquire_phy_82575
,
1610 .get_cfg_done
= igb_get_cfg_done_82575
,
1611 .release
= igb_release_phy_82575
,
1614 static struct e1000_nvm_operations e1000_nvm_ops_82575
= {
1615 .acquire
= igb_acquire_nvm_82575
,
1616 .read
= igb_read_nvm_eerd
,
1617 .release
= igb_release_nvm_82575
,
1618 .write
= igb_write_nvm_spi
,
1621 const struct e1000_info e1000_82575_info
= {
1622 .get_invariants
= igb_get_invariants_82575
,
1623 .mac_ops
= &e1000_mac_ops_82575
,
1624 .phy_ops
= &e1000_phy_ops_82575
,
1625 .nvm_ops
= &e1000_nvm_ops_82575
,