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Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[deliverable/linux.git] / drivers / net / igb / e1000_82575.c
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 - 2008 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 /* e1000_82575
29 * e1000_82576
30 */
31
32 #include <linux/types.h>
33 #include <linux/slab.h>
34
35 #include "e1000_mac.h"
36 #include "e1000_82575.h"
37
38 static s32 igb_get_invariants_82575(struct e1000_hw *);
39 static s32 igb_acquire_phy_82575(struct e1000_hw *);
40 static void igb_release_phy_82575(struct e1000_hw *);
41 static s32 igb_acquire_nvm_82575(struct e1000_hw *);
42 static void igb_release_nvm_82575(struct e1000_hw *);
43 static s32 igb_check_for_link_82575(struct e1000_hw *);
44 static s32 igb_get_cfg_done_82575(struct e1000_hw *);
45 static s32 igb_init_hw_82575(struct e1000_hw *);
46 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
47 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
48 static void igb_rar_set_82575(struct e1000_hw *, u8 *, u32);
49 static s32 igb_reset_hw_82575(struct e1000_hw *);
50 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
51 static s32 igb_setup_copper_link_82575(struct e1000_hw *);
52 static s32 igb_setup_fiber_serdes_link_82575(struct e1000_hw *);
53 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
54 static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
55 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
56 static s32 igb_configure_pcs_link_82575(struct e1000_hw *);
57 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
58 u16 *);
59 static s32 igb_get_phy_id_82575(struct e1000_hw *);
60 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
61 static bool igb_sgmii_active_82575(struct e1000_hw *);
62 static s32 igb_reset_init_script_82575(struct e1000_hw *);
63 static s32 igb_read_mac_addr_82575(struct e1000_hw *);
64
65
66 struct e1000_dev_spec_82575 {
67 bool sgmii_active;
68 };
69
70 static s32 igb_get_invariants_82575(struct e1000_hw *hw)
71 {
72 struct e1000_phy_info *phy = &hw->phy;
73 struct e1000_nvm_info *nvm = &hw->nvm;
74 struct e1000_mac_info *mac = &hw->mac;
75 struct e1000_dev_spec_82575 *dev_spec;
76 u32 eecd;
77 s32 ret_val;
78 u16 size;
79 u32 ctrl_ext = 0;
80
81 switch (hw->device_id) {
82 case E1000_DEV_ID_82575EB_COPPER:
83 case E1000_DEV_ID_82575EB_FIBER_SERDES:
84 case E1000_DEV_ID_82575GB_QUAD_COPPER:
85 mac->type = e1000_82575;
86 break;
87 default:
88 return -E1000_ERR_MAC_INIT;
89 break;
90 }
91
92 /* MAC initialization */
93 hw->dev_spec_size = sizeof(struct e1000_dev_spec_82575);
94
95 /* Device-specific structure allocation */
96 hw->dev_spec = kzalloc(hw->dev_spec_size, GFP_KERNEL);
97
98 if (!hw->dev_spec)
99 return -ENOMEM;
100
101 dev_spec = (struct e1000_dev_spec_82575 *)hw->dev_spec;
102
103 /* Set media type */
104 /*
105 * The 82575 uses bits 22:23 for link mode. The mode can be changed
106 * based on the EEPROM. We cannot rely upon device ID. There
107 * is no distinguishable difference between fiber and internal
108 * SerDes mode on the 82575. There can be an external PHY attached
109 * on the SGMII interface. For this, we'll set sgmii_active to true.
110 */
111 phy->media_type = e1000_media_type_copper;
112 dev_spec->sgmii_active = false;
113
114 ctrl_ext = rd32(E1000_CTRL_EXT);
115 if ((ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) ==
116 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES) {
117 hw->phy.media_type = e1000_media_type_internal_serdes;
118 ctrl_ext |= E1000_CTRL_I2C_ENA;
119 } else if (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII) {
120 dev_spec->sgmii_active = true;
121 ctrl_ext |= E1000_CTRL_I2C_ENA;
122 } else {
123 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
124 }
125 wr32(E1000_CTRL_EXT, ctrl_ext);
126
127 /* Set mta register count */
128 mac->mta_reg_count = 128;
129 /* Set rar entry count */
130 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
131 /* Set if part includes ASF firmware */
132 mac->asf_firmware_present = true;
133 /* Set if manageability features are enabled. */
134 mac->arc_subsystem_valid =
135 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
136 ? true : false;
137
138 /* physical interface link setup */
139 mac->ops.setup_physical_interface =
140 (hw->phy.media_type == e1000_media_type_copper)
141 ? igb_setup_copper_link_82575
142 : igb_setup_fiber_serdes_link_82575;
143
144 /* NVM initialization */
145 eecd = rd32(E1000_EECD);
146
147 nvm->opcode_bits = 8;
148 nvm->delay_usec = 1;
149 switch (nvm->override) {
150 case e1000_nvm_override_spi_large:
151 nvm->page_size = 32;
152 nvm->address_bits = 16;
153 break;
154 case e1000_nvm_override_spi_small:
155 nvm->page_size = 8;
156 nvm->address_bits = 8;
157 break;
158 default:
159 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
160 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
161 break;
162 }
163
164 nvm->type = e1000_nvm_eeprom_spi;
165
166 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
167 E1000_EECD_SIZE_EX_SHIFT);
168
169 /*
170 * Added to a constant, "size" becomes the left-shift value
171 * for setting word_size.
172 */
173 size += NVM_WORD_SIZE_BASE_SHIFT;
174
175 /* EEPROM access above 16k is unsupported */
176 if (size > 14)
177 size = 14;
178 nvm->word_size = 1 << size;
179
180 /* setup PHY parameters */
181 if (phy->media_type != e1000_media_type_copper) {
182 phy->type = e1000_phy_none;
183 return 0;
184 }
185
186 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
187 phy->reset_delay_us = 100;
188
189 /* PHY function pointers */
190 if (igb_sgmii_active_82575(hw)) {
191 phy->ops.reset_phy = igb_phy_hw_reset_sgmii_82575;
192 phy->ops.read_phy_reg = igb_read_phy_reg_sgmii_82575;
193 phy->ops.write_phy_reg = igb_write_phy_reg_sgmii_82575;
194 } else {
195 phy->ops.reset_phy = igb_phy_hw_reset;
196 phy->ops.read_phy_reg = igb_read_phy_reg_igp;
197 phy->ops.write_phy_reg = igb_write_phy_reg_igp;
198 }
199
200 /* Set phy->phy_addr and phy->id. */
201 ret_val = igb_get_phy_id_82575(hw);
202 if (ret_val)
203 return ret_val;
204
205 /* Verify phy id and set remaining function pointers */
206 switch (phy->id) {
207 case M88E1111_I_PHY_ID:
208 phy->type = e1000_phy_m88;
209 phy->ops.get_phy_info = igb_get_phy_info_m88;
210 phy->ops.get_cable_length = igb_get_cable_length_m88;
211 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
212 break;
213 case IGP03E1000_E_PHY_ID:
214 phy->type = e1000_phy_igp_3;
215 phy->ops.get_phy_info = igb_get_phy_info_igp;
216 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
217 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
218 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
219 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
220 break;
221 default:
222 return -E1000_ERR_PHY;
223 }
224
225 return 0;
226 }
227
228 /**
229 * igb_acquire_phy_82575 - Acquire rights to access PHY
230 * @hw: pointer to the HW structure
231 *
232 * Acquire access rights to the correct PHY. This is a
233 * function pointer entry point called by the api module.
234 **/
235 static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
236 {
237 u16 mask;
238
239 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
240
241 return igb_acquire_swfw_sync_82575(hw, mask);
242 }
243
244 /**
245 * igb_release_phy_82575 - Release rights to access PHY
246 * @hw: pointer to the HW structure
247 *
248 * A wrapper to release access rights to the correct PHY. This is a
249 * function pointer entry point called by the api module.
250 **/
251 static void igb_release_phy_82575(struct e1000_hw *hw)
252 {
253 u16 mask;
254
255 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
256 igb_release_swfw_sync_82575(hw, mask);
257 }
258
259 /**
260 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
261 * @hw: pointer to the HW structure
262 * @offset: register offset to be read
263 * @data: pointer to the read data
264 *
265 * Reads the PHY register at offset using the serial gigabit media independent
266 * interface and stores the retrieved information in data.
267 **/
268 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
269 u16 *data)
270 {
271 struct e1000_phy_info *phy = &hw->phy;
272 u32 i, i2ccmd = 0;
273
274 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
275 hw_dbg("PHY Address %u is out of range\n", offset);
276 return -E1000_ERR_PARAM;
277 }
278
279 /*
280 * Set up Op-code, Phy Address, and register address in the I2CCMD
281 * register. The MAC will take care of interfacing with the
282 * PHY to retrieve the desired data.
283 */
284 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
285 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
286 (E1000_I2CCMD_OPCODE_READ));
287
288 wr32(E1000_I2CCMD, i2ccmd);
289
290 /* Poll the ready bit to see if the I2C read completed */
291 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
292 udelay(50);
293 i2ccmd = rd32(E1000_I2CCMD);
294 if (i2ccmd & E1000_I2CCMD_READY)
295 break;
296 }
297 if (!(i2ccmd & E1000_I2CCMD_READY)) {
298 hw_dbg("I2CCMD Read did not complete\n");
299 return -E1000_ERR_PHY;
300 }
301 if (i2ccmd & E1000_I2CCMD_ERROR) {
302 hw_dbg("I2CCMD Error bit set\n");
303 return -E1000_ERR_PHY;
304 }
305
306 /* Need to byte-swap the 16-bit value. */
307 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
308
309 return 0;
310 }
311
312 /**
313 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
314 * @hw: pointer to the HW structure
315 * @offset: register offset to write to
316 * @data: data to write at register offset
317 *
318 * Writes the data to PHY register at the offset using the serial gigabit
319 * media independent interface.
320 **/
321 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
322 u16 data)
323 {
324 struct e1000_phy_info *phy = &hw->phy;
325 u32 i, i2ccmd = 0;
326 u16 phy_data_swapped;
327
328 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
329 hw_dbg("PHY Address %d is out of range\n", offset);
330 return -E1000_ERR_PARAM;
331 }
332
333 /* Swap the data bytes for the I2C interface */
334 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
335
336 /*
337 * Set up Op-code, Phy Address, and register address in the I2CCMD
338 * register. The MAC will take care of interfacing with the
339 * PHY to retrieve the desired data.
340 */
341 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
342 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
343 E1000_I2CCMD_OPCODE_WRITE |
344 phy_data_swapped);
345
346 wr32(E1000_I2CCMD, i2ccmd);
347
348 /* Poll the ready bit to see if the I2C read completed */
349 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
350 udelay(50);
351 i2ccmd = rd32(E1000_I2CCMD);
352 if (i2ccmd & E1000_I2CCMD_READY)
353 break;
354 }
355 if (!(i2ccmd & E1000_I2CCMD_READY)) {
356 hw_dbg("I2CCMD Write did not complete\n");
357 return -E1000_ERR_PHY;
358 }
359 if (i2ccmd & E1000_I2CCMD_ERROR) {
360 hw_dbg("I2CCMD Error bit set\n");
361 return -E1000_ERR_PHY;
362 }
363
364 return 0;
365 }
366
367 /**
368 * igb_get_phy_id_82575 - Retrieve PHY addr and id
369 * @hw: pointer to the HW structure
370 *
371 * Retrieves the PHY address and ID for both PHY's which do and do not use
372 * sgmi interface.
373 **/
374 static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
375 {
376 struct e1000_phy_info *phy = &hw->phy;
377 s32 ret_val = 0;
378 u16 phy_id;
379
380 /*
381 * For SGMII PHYs, we try the list of possible addresses until
382 * we find one that works. For non-SGMII PHYs
383 * (e.g. integrated copper PHYs), an address of 1 should
384 * work. The result of this function should mean phy->phy_addr
385 * and phy->id are set correctly.
386 */
387 if (!(igb_sgmii_active_82575(hw))) {
388 phy->addr = 1;
389 ret_val = igb_get_phy_id(hw);
390 goto out;
391 }
392
393 /*
394 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
395 * Therefore, we need to test 1-7
396 */
397 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
398 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
399 if (ret_val == 0) {
400 hw_dbg("Vendor ID 0x%08X read at address %u\n",
401 phy_id, phy->addr);
402 /*
403 * At the time of this writing, The M88 part is
404 * the only supported SGMII PHY product.
405 */
406 if (phy_id == M88_VENDOR)
407 break;
408 } else {
409 hw_dbg("PHY address %u was unreadable\n", phy->addr);
410 }
411 }
412
413 /* A valid PHY type couldn't be found. */
414 if (phy->addr == 8) {
415 phy->addr = 0;
416 ret_val = -E1000_ERR_PHY;
417 goto out;
418 }
419
420 ret_val = igb_get_phy_id(hw);
421
422 out:
423 return ret_val;
424 }
425
426 /**
427 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
428 * @hw: pointer to the HW structure
429 *
430 * Resets the PHY using the serial gigabit media independent interface.
431 **/
432 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
433 {
434 s32 ret_val;
435
436 /*
437 * This isn't a true "hard" reset, but is the only reset
438 * available to us at this time.
439 */
440
441 hw_dbg("Soft resetting SGMII attached PHY...\n");
442
443 /*
444 * SFP documentation requires the following to configure the SPF module
445 * to work on SGMII. No further documentation is given.
446 */
447 ret_val = hw->phy.ops.write_phy_reg(hw, 0x1B, 0x8084);
448 if (ret_val)
449 goto out;
450
451 ret_val = igb_phy_sw_reset(hw);
452
453 out:
454 return ret_val;
455 }
456
457 /**
458 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
459 * @hw: pointer to the HW structure
460 * @active: true to enable LPLU, false to disable
461 *
462 * Sets the LPLU D0 state according to the active flag. When
463 * activating LPLU this function also disables smart speed
464 * and vice versa. LPLU will not be activated unless the
465 * device autonegotiation advertisement meets standards of
466 * either 10 or 10/100 or 10/100/1000 at all duplexes.
467 * This is a function pointer entry point only called by
468 * PHY setup routines.
469 **/
470 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
471 {
472 struct e1000_phy_info *phy = &hw->phy;
473 s32 ret_val;
474 u16 data;
475
476 ret_val = phy->ops.read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
477 if (ret_val)
478 goto out;
479
480 if (active) {
481 data |= IGP02E1000_PM_D0_LPLU;
482 ret_val = phy->ops.write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
483 data);
484 if (ret_val)
485 goto out;
486
487 /* When LPLU is enabled, we should disable SmartSpeed */
488 ret_val = phy->ops.read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
489 &data);
490 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
491 ret_val = phy->ops.write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
492 data);
493 if (ret_val)
494 goto out;
495 } else {
496 data &= ~IGP02E1000_PM_D0_LPLU;
497 ret_val = phy->ops.write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
498 data);
499 /*
500 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
501 * during Dx states where the power conservation is most
502 * important. During driver activity we should enable
503 * SmartSpeed, so performance is maintained.
504 */
505 if (phy->smart_speed == e1000_smart_speed_on) {
506 ret_val = phy->ops.read_phy_reg(hw,
507 IGP01E1000_PHY_PORT_CONFIG, &data);
508 if (ret_val)
509 goto out;
510
511 data |= IGP01E1000_PSCFR_SMART_SPEED;
512 ret_val = phy->ops.write_phy_reg(hw,
513 IGP01E1000_PHY_PORT_CONFIG, data);
514 if (ret_val)
515 goto out;
516 } else if (phy->smart_speed == e1000_smart_speed_off) {
517 ret_val = phy->ops.read_phy_reg(hw,
518 IGP01E1000_PHY_PORT_CONFIG, &data);
519 if (ret_val)
520 goto out;
521
522 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
523 ret_val = phy->ops.write_phy_reg(hw,
524 IGP01E1000_PHY_PORT_CONFIG, data);
525 if (ret_val)
526 goto out;
527 }
528 }
529
530 out:
531 return ret_val;
532 }
533
534 /**
535 * igb_acquire_nvm_82575 - Request for access to EEPROM
536 * @hw: pointer to the HW structure
537 *
538 * Acquire the necessary semaphores for exclusive access to the EEPROM.
539 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
540 * Return successful if access grant bit set, else clear the request for
541 * EEPROM access and return -E1000_ERR_NVM (-1).
542 **/
543 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
544 {
545 s32 ret_val;
546
547 ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
548 if (ret_val)
549 goto out;
550
551 ret_val = igb_acquire_nvm(hw);
552
553 if (ret_val)
554 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
555
556 out:
557 return ret_val;
558 }
559
560 /**
561 * igb_release_nvm_82575 - Release exclusive access to EEPROM
562 * @hw: pointer to the HW structure
563 *
564 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
565 * then release the semaphores acquired.
566 **/
567 static void igb_release_nvm_82575(struct e1000_hw *hw)
568 {
569 igb_release_nvm(hw);
570 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
571 }
572
573 /**
574 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
575 * @hw: pointer to the HW structure
576 * @mask: specifies which semaphore to acquire
577 *
578 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
579 * will also specify which port we're acquiring the lock for.
580 **/
581 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
582 {
583 u32 swfw_sync;
584 u32 swmask = mask;
585 u32 fwmask = mask << 16;
586 s32 ret_val = 0;
587 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
588
589 while (i < timeout) {
590 if (igb_get_hw_semaphore(hw)) {
591 ret_val = -E1000_ERR_SWFW_SYNC;
592 goto out;
593 }
594
595 swfw_sync = rd32(E1000_SW_FW_SYNC);
596 if (!(swfw_sync & (fwmask | swmask)))
597 break;
598
599 /*
600 * Firmware currently using resource (fwmask)
601 * or other software thread using resource (swmask)
602 */
603 igb_put_hw_semaphore(hw);
604 mdelay(5);
605 i++;
606 }
607
608 if (i == timeout) {
609 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
610 ret_val = -E1000_ERR_SWFW_SYNC;
611 goto out;
612 }
613
614 swfw_sync |= swmask;
615 wr32(E1000_SW_FW_SYNC, swfw_sync);
616
617 igb_put_hw_semaphore(hw);
618
619 out:
620 return ret_val;
621 }
622
623 /**
624 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
625 * @hw: pointer to the HW structure
626 * @mask: specifies which semaphore to acquire
627 *
628 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
629 * will also specify which port we're releasing the lock for.
630 **/
631 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
632 {
633 u32 swfw_sync;
634
635 while (igb_get_hw_semaphore(hw) != 0);
636 /* Empty */
637
638 swfw_sync = rd32(E1000_SW_FW_SYNC);
639 swfw_sync &= ~mask;
640 wr32(E1000_SW_FW_SYNC, swfw_sync);
641
642 igb_put_hw_semaphore(hw);
643 }
644
645 /**
646 * igb_get_cfg_done_82575 - Read config done bit
647 * @hw: pointer to the HW structure
648 *
649 * Read the management control register for the config done bit for
650 * completion status. NOTE: silicon which is EEPROM-less will fail trying
651 * to read the config done bit, so an error is *ONLY* logged and returns
652 * 0. If we were to return with error, EEPROM-less silicon
653 * would not be able to be reset or change link.
654 **/
655 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
656 {
657 s32 timeout = PHY_CFG_TIMEOUT;
658 s32 ret_val = 0;
659 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
660
661 if (hw->bus.func == 1)
662 mask = E1000_NVM_CFG_DONE_PORT_1;
663
664 while (timeout) {
665 if (rd32(E1000_EEMNGCTL) & mask)
666 break;
667 msleep(1);
668 timeout--;
669 }
670 if (!timeout)
671 hw_dbg("MNG configuration cycle has not completed.\n");
672
673 /* If EEPROM is not marked present, init the PHY manually */
674 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
675 (hw->phy.type == e1000_phy_igp_3))
676 igb_phy_init_script_igp3(hw);
677
678 return ret_val;
679 }
680
681 /**
682 * igb_check_for_link_82575 - Check for link
683 * @hw: pointer to the HW structure
684 *
685 * If sgmii is enabled, then use the pcs register to determine link, otherwise
686 * use the generic interface for determining link.
687 **/
688 static s32 igb_check_for_link_82575(struct e1000_hw *hw)
689 {
690 s32 ret_val;
691 u16 speed, duplex;
692
693 /* SGMII link check is done through the PCS register. */
694 if ((hw->phy.media_type != e1000_media_type_copper) ||
695 (igb_sgmii_active_82575(hw)))
696 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
697 &duplex);
698 else
699 ret_val = igb_check_for_copper_link(hw);
700
701 return ret_val;
702 }
703
704 /**
705 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
706 * @hw: pointer to the HW structure
707 * @speed: stores the current speed
708 * @duplex: stores the current duplex
709 *
710 * Using the physical coding sub-layer (PCS), retrieve the current speed and
711 * duplex, then store the values in the pointers provided.
712 **/
713 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
714 u16 *duplex)
715 {
716 struct e1000_mac_info *mac = &hw->mac;
717 u32 pcs;
718
719 /* Set up defaults for the return values of this function */
720 mac->serdes_has_link = false;
721 *speed = 0;
722 *duplex = 0;
723
724 /*
725 * Read the PCS Status register for link state. For non-copper mode,
726 * the status register is not accurate. The PCS status register is
727 * used instead.
728 */
729 pcs = rd32(E1000_PCS_LSTAT);
730
731 /*
732 * The link up bit determines when link is up on autoneg. The sync ok
733 * gets set once both sides sync up and agree upon link. Stable link
734 * can be determined by checking for both link up and link sync ok
735 */
736 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
737 mac->serdes_has_link = true;
738
739 /* Detect and store PCS speed */
740 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
741 *speed = SPEED_1000;
742 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
743 *speed = SPEED_100;
744 } else {
745 *speed = SPEED_10;
746 }
747
748 /* Detect and store PCS duplex */
749 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
750 *duplex = FULL_DUPLEX;
751 } else {
752 *duplex = HALF_DUPLEX;
753 }
754 }
755
756 return 0;
757 }
758
759 /**
760 * igb_rar_set_82575 - Set receive address register
761 * @hw: pointer to the HW structure
762 * @addr: pointer to the receive address
763 * @index: receive address array register
764 *
765 * Sets the receive address array register at index to the address passed
766 * in by addr.
767 **/
768 static void igb_rar_set_82575(struct e1000_hw *hw, u8 *addr, u32 index)
769 {
770 if (index < E1000_RAR_ENTRIES_82575)
771 igb_rar_set(hw, addr, index);
772
773 return;
774 }
775
776 /**
777 * igb_reset_hw_82575 - Reset hardware
778 * @hw: pointer to the HW structure
779 *
780 * This resets the hardware into a known state. This is a
781 * function pointer entry point called by the api module.
782 **/
783 static s32 igb_reset_hw_82575(struct e1000_hw *hw)
784 {
785 u32 ctrl, icr;
786 s32 ret_val;
787
788 /*
789 * Prevent the PCI-E bus from sticking if there is no TLP connection
790 * on the last TLP read/write transaction when MAC is reset.
791 */
792 ret_val = igb_disable_pcie_master(hw);
793 if (ret_val)
794 hw_dbg("PCI-E Master disable polling has failed.\n");
795
796 hw_dbg("Masking off all interrupts\n");
797 wr32(E1000_IMC, 0xffffffff);
798
799 wr32(E1000_RCTL, 0);
800 wr32(E1000_TCTL, E1000_TCTL_PSP);
801 wrfl();
802
803 msleep(10);
804
805 ctrl = rd32(E1000_CTRL);
806
807 hw_dbg("Issuing a global reset to MAC\n");
808 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
809
810 ret_val = igb_get_auto_rd_done(hw);
811 if (ret_val) {
812 /*
813 * When auto config read does not complete, do not
814 * return with an error. This can happen in situations
815 * where there is no eeprom and prevents getting link.
816 */
817 hw_dbg("Auto Read Done did not complete\n");
818 }
819
820 /* If EEPROM is not present, run manual init scripts */
821 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
822 igb_reset_init_script_82575(hw);
823
824 /* Clear any pending interrupt events. */
825 wr32(E1000_IMC, 0xffffffff);
826 icr = rd32(E1000_ICR);
827
828 igb_check_alt_mac_addr(hw);
829
830 return ret_val;
831 }
832
833 /**
834 * igb_init_hw_82575 - Initialize hardware
835 * @hw: pointer to the HW structure
836 *
837 * This inits the hardware readying it for operation.
838 **/
839 static s32 igb_init_hw_82575(struct e1000_hw *hw)
840 {
841 struct e1000_mac_info *mac = &hw->mac;
842 s32 ret_val;
843 u16 i, rar_count = mac->rar_entry_count;
844
845 /* Initialize identification LED */
846 ret_val = igb_id_led_init(hw);
847 if (ret_val) {
848 hw_dbg("Error initializing identification LED\n");
849 /* This is not fatal and we should not stop init due to this */
850 }
851
852 /* Disabling VLAN filtering */
853 hw_dbg("Initializing the IEEE VLAN\n");
854 igb_clear_vfta(hw);
855
856 /* Setup the receive address */
857 igb_init_rx_addrs(hw, rar_count);
858 /* Zero out the Multicast HASH table */
859 hw_dbg("Zeroing the MTA\n");
860 for (i = 0; i < mac->mta_reg_count; i++)
861 array_wr32(E1000_MTA, i, 0);
862
863 /* Setup link and flow control */
864 ret_val = igb_setup_link(hw);
865
866 /*
867 * Clear all of the statistics registers (clear on read). It is
868 * important that we do this after we have tried to establish link
869 * because the symbol error count will increment wildly if there
870 * is no link.
871 */
872 igb_clear_hw_cntrs_82575(hw);
873
874 return ret_val;
875 }
876
877 /**
878 * igb_setup_copper_link_82575 - Configure copper link settings
879 * @hw: pointer to the HW structure
880 *
881 * Configures the link for auto-neg or forced speed and duplex. Then we check
882 * for link, once link is established calls to configure collision distance
883 * and flow control are called.
884 **/
885 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
886 {
887 u32 ctrl, led_ctrl;
888 s32 ret_val;
889 bool link;
890
891 ctrl = rd32(E1000_CTRL);
892 ctrl |= E1000_CTRL_SLU;
893 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
894 wr32(E1000_CTRL, ctrl);
895
896 switch (hw->phy.type) {
897 case e1000_phy_m88:
898 ret_val = igb_copper_link_setup_m88(hw);
899 break;
900 case e1000_phy_igp_3:
901 ret_val = igb_copper_link_setup_igp(hw);
902 /* Setup activity LED */
903 led_ctrl = rd32(E1000_LEDCTL);
904 led_ctrl &= IGP_ACTIVITY_LED_MASK;
905 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
906 wr32(E1000_LEDCTL, led_ctrl);
907 break;
908 default:
909 ret_val = -E1000_ERR_PHY;
910 break;
911 }
912
913 if (ret_val)
914 goto out;
915
916 if (hw->mac.autoneg) {
917 /*
918 * Setup autoneg and flow control advertisement
919 * and perform autonegotiation.
920 */
921 ret_val = igb_copper_link_autoneg(hw);
922 if (ret_val)
923 goto out;
924 } else {
925 /*
926 * PHY will be set to 10H, 10F, 100H or 100F
927 * depending on user settings.
928 */
929 hw_dbg("Forcing Speed and Duplex\n");
930 ret_val = igb_phy_force_speed_duplex(hw);
931 if (ret_val) {
932 hw_dbg("Error Forcing Speed and Duplex\n");
933 goto out;
934 }
935 }
936
937 ret_val = igb_configure_pcs_link_82575(hw);
938 if (ret_val)
939 goto out;
940
941 /*
942 * Check link status. Wait up to 100 microseconds for link to become
943 * valid.
944 */
945 ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link);
946 if (ret_val)
947 goto out;
948
949 if (link) {
950 hw_dbg("Valid link established!!!\n");
951 /* Config the MAC and PHY after link is up */
952 igb_config_collision_dist(hw);
953 ret_val = igb_config_fc_after_link_up(hw);
954 } else {
955 hw_dbg("Unable to establish link!!!\n");
956 }
957
958 out:
959 return ret_val;
960 }
961
962 /**
963 * igb_setup_fiber_serdes_link_82575 - Setup link for fiber/serdes
964 * @hw: pointer to the HW structure
965 *
966 * Configures speed and duplex for fiber and serdes links.
967 **/
968 static s32 igb_setup_fiber_serdes_link_82575(struct e1000_hw *hw)
969 {
970 u32 reg;
971
972 /*
973 * On the 82575, SerDes loopback mode persists until it is
974 * explicitly turned off or a power cycle is performed. A read to
975 * the register does not indicate its status. Therefore, we ensure
976 * loopback mode is disabled during initialization.
977 */
978 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
979
980 /* Force link up, set 1gb, set both sw defined pins */
981 reg = rd32(E1000_CTRL);
982 reg |= E1000_CTRL_SLU |
983 E1000_CTRL_SPD_1000 |
984 E1000_CTRL_FRCSPD |
985 E1000_CTRL_SWDPIN0 |
986 E1000_CTRL_SWDPIN1;
987 wr32(E1000_CTRL, reg);
988
989 /* Set switch control to serdes energy detect */
990 reg = rd32(E1000_CONNSW);
991 reg |= E1000_CONNSW_ENRGSRC;
992 wr32(E1000_CONNSW, reg);
993
994 /*
995 * New SerDes mode allows for forcing speed or autonegotiating speed
996 * at 1gb. Autoneg should be default set by most drivers. This is the
997 * mode that will be compatible with older link partners and switches.
998 * However, both are supported by the hardware and some drivers/tools.
999 */
1000 reg = rd32(E1000_PCS_LCTL);
1001
1002 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1003 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1004
1005 if (hw->mac.autoneg) {
1006 /* Set PCS register for autoneg */
1007 reg |= E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1008 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1009 E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1010 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1011 hw_dbg("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg);
1012 } else {
1013 /* Set PCS register for forced speed */
1014 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1015 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1016 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1017 E1000_PCS_LCTL_FSD | /* Force Speed */
1018 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1019 hw_dbg("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg);
1020 }
1021 wr32(E1000_PCS_LCTL, reg);
1022
1023 return 0;
1024 }
1025
1026 /**
1027 * igb_configure_pcs_link_82575 - Configure PCS link
1028 * @hw: pointer to the HW structure
1029 *
1030 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1031 * only used on copper connections where the serialized gigabit media
1032 * independent interface (sgmii) is being used. Configures the link
1033 * for auto-negotiation or forces speed/duplex.
1034 **/
1035 static s32 igb_configure_pcs_link_82575(struct e1000_hw *hw)
1036 {
1037 struct e1000_mac_info *mac = &hw->mac;
1038 u32 reg = 0;
1039
1040 if (hw->phy.media_type != e1000_media_type_copper ||
1041 !(igb_sgmii_active_82575(hw)))
1042 goto out;
1043
1044 /* For SGMII, we need to issue a PCS autoneg restart */
1045 reg = rd32(E1000_PCS_LCTL);
1046
1047 /* AN time out should be disabled for SGMII mode */
1048 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1049
1050 if (mac->autoneg) {
1051 /* Make sure forced speed and force link are not set */
1052 reg &= ~(E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1053
1054 /*
1055 * The PHY should be setup prior to calling this function.
1056 * All we need to do is restart autoneg and enable autoneg.
1057 */
1058 reg |= E1000_PCS_LCTL_AN_RESTART | E1000_PCS_LCTL_AN_ENABLE;
1059 } else {
1060 /* Set PCS register for forced speed */
1061
1062 /* Turn off bits for full duplex, speed, and autoneg */
1063 reg &= ~(E1000_PCS_LCTL_FSV_1000 |
1064 E1000_PCS_LCTL_FSV_100 |
1065 E1000_PCS_LCTL_FDV_FULL |
1066 E1000_PCS_LCTL_AN_ENABLE);
1067
1068 /* Check for duplex first */
1069 if (mac->forced_speed_duplex & E1000_ALL_FULL_DUPLEX)
1070 reg |= E1000_PCS_LCTL_FDV_FULL;
1071
1072 /* Now set speed */
1073 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED)
1074 reg |= E1000_PCS_LCTL_FSV_100;
1075
1076 /* Force speed and force link */
1077 reg |= E1000_PCS_LCTL_FSD |
1078 E1000_PCS_LCTL_FORCE_LINK |
1079 E1000_PCS_LCTL_FLV_LINK_UP;
1080
1081 hw_dbg("Wrote 0x%08X to PCS_LCTL to configure forced link\n",
1082 reg);
1083 }
1084 wr32(E1000_PCS_LCTL, reg);
1085
1086 out:
1087 return 0;
1088 }
1089
1090 /**
1091 * igb_sgmii_active_82575 - Return sgmii state
1092 * @hw: pointer to the HW structure
1093 *
1094 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1095 * which can be enabled for use in the embedded applications. Simply
1096 * return the current state of the sgmii interface.
1097 **/
1098 static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1099 {
1100 struct e1000_dev_spec_82575 *dev_spec;
1101 bool ret_val;
1102
1103 if (hw->mac.type != e1000_82575) {
1104 ret_val = false;
1105 goto out;
1106 }
1107
1108 dev_spec = (struct e1000_dev_spec_82575 *)hw->dev_spec;
1109
1110 ret_val = dev_spec->sgmii_active;
1111
1112 out:
1113 return ret_val;
1114 }
1115
1116 /**
1117 * igb_reset_init_script_82575 - Inits HW defaults after reset
1118 * @hw: pointer to the HW structure
1119 *
1120 * Inits recommended HW defaults after a reset when there is no EEPROM
1121 * detected. This is only for the 82575.
1122 **/
1123 static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1124 {
1125 if (hw->mac.type == e1000_82575) {
1126 hw_dbg("Running reset init script for 82575\n");
1127 /* SerDes configuration via SERDESCTRL */
1128 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1129 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1130 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1131 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1132
1133 /* CCM configuration via CCMCTL register */
1134 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1135 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1136
1137 /* PCIe lanes configuration */
1138 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1139 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1140 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1141 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1142
1143 /* PCIe PLL Configuration */
1144 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1145 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1146 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1147 }
1148
1149 return 0;
1150 }
1151
1152 /**
1153 * igb_read_mac_addr_82575 - Read device MAC address
1154 * @hw: pointer to the HW structure
1155 **/
1156 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1157 {
1158 s32 ret_val = 0;
1159
1160 if (igb_check_alt_mac_addr(hw))
1161 ret_val = igb_read_mac_addr(hw);
1162
1163 return ret_val;
1164 }
1165
1166 /**
1167 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1168 * @hw: pointer to the HW structure
1169 *
1170 * Clears the hardware counters by reading the counter registers.
1171 **/
1172 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1173 {
1174 u32 temp;
1175
1176 igb_clear_hw_cntrs_base(hw);
1177
1178 temp = rd32(E1000_PRC64);
1179 temp = rd32(E1000_PRC127);
1180 temp = rd32(E1000_PRC255);
1181 temp = rd32(E1000_PRC511);
1182 temp = rd32(E1000_PRC1023);
1183 temp = rd32(E1000_PRC1522);
1184 temp = rd32(E1000_PTC64);
1185 temp = rd32(E1000_PTC127);
1186 temp = rd32(E1000_PTC255);
1187 temp = rd32(E1000_PTC511);
1188 temp = rd32(E1000_PTC1023);
1189 temp = rd32(E1000_PTC1522);
1190
1191 temp = rd32(E1000_ALGNERRC);
1192 temp = rd32(E1000_RXERRC);
1193 temp = rd32(E1000_TNCRS);
1194 temp = rd32(E1000_CEXTERR);
1195 temp = rd32(E1000_TSCTC);
1196 temp = rd32(E1000_TSCTFC);
1197
1198 temp = rd32(E1000_MGTPRC);
1199 temp = rd32(E1000_MGTPDC);
1200 temp = rd32(E1000_MGTPTC);
1201
1202 temp = rd32(E1000_IAC);
1203 temp = rd32(E1000_ICRXOC);
1204
1205 temp = rd32(E1000_ICRXPTC);
1206 temp = rd32(E1000_ICRXATC);
1207 temp = rd32(E1000_ICTXPTC);
1208 temp = rd32(E1000_ICTXATC);
1209 temp = rd32(E1000_ICTXQEC);
1210 temp = rd32(E1000_ICTXQMTC);
1211 temp = rd32(E1000_ICRXDMTC);
1212
1213 temp = rd32(E1000_CBTMPC);
1214 temp = rd32(E1000_HTDPMC);
1215 temp = rd32(E1000_CBRMPC);
1216 temp = rd32(E1000_RPTHC);
1217 temp = rd32(E1000_HGPTC);
1218 temp = rd32(E1000_HTCBDPC);
1219 temp = rd32(E1000_HGORCL);
1220 temp = rd32(E1000_HGORCH);
1221 temp = rd32(E1000_HGOTCL);
1222 temp = rd32(E1000_HGOTCH);
1223 temp = rd32(E1000_LENERRS);
1224
1225 /* This register should not be read in copper configurations */
1226 if (hw->phy.media_type == e1000_media_type_internal_serdes)
1227 temp = rd32(E1000_SCVPC);
1228 }
1229
1230 /**
1231 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1232 * @hw: pointer to the HW structure
1233 *
1234 * After rx enable if managability is enabled then there is likely some
1235 * bad data at the start of the fifo and possibly in the DMA fifo. This
1236 * function clears the fifos and flushes any packets that came in as rx was
1237 * being enabled.
1238 **/
1239 void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1240 {
1241 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1242 int i, ms_wait;
1243
1244 if (hw->mac.type != e1000_82575 ||
1245 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1246 return;
1247
1248 /* Disable all RX queues */
1249 for (i = 0; i < 4; i++) {
1250 rxdctl[i] = rd32(E1000_RXDCTL(i));
1251 wr32(E1000_RXDCTL(i),
1252 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1253 }
1254 /* Poll all queues to verify they have shut down */
1255 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1256 msleep(1);
1257 rx_enabled = 0;
1258 for (i = 0; i < 4; i++)
1259 rx_enabled |= rd32(E1000_RXDCTL(i));
1260 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1261 break;
1262 }
1263
1264 if (ms_wait == 10)
1265 hw_dbg("Queue disable timed out after 10ms\n");
1266
1267 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1268 * incoming packets are rejected. Set enable and wait 2ms so that
1269 * any packet that was coming in as RCTL.EN was set is flushed
1270 */
1271 rfctl = rd32(E1000_RFCTL);
1272 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1273
1274 rlpml = rd32(E1000_RLPML);
1275 wr32(E1000_RLPML, 0);
1276
1277 rctl = rd32(E1000_RCTL);
1278 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1279 temp_rctl |= E1000_RCTL_LPE;
1280
1281 wr32(E1000_RCTL, temp_rctl);
1282 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1283 wrfl();
1284 msleep(2);
1285
1286 /* Enable RX queues that were previously enabled and restore our
1287 * previous state
1288 */
1289 for (i = 0; i < 4; i++)
1290 wr32(E1000_RXDCTL(i), rxdctl[i]);
1291 wr32(E1000_RCTL, rctl);
1292 wrfl();
1293
1294 wr32(E1000_RLPML, rlpml);
1295 wr32(E1000_RFCTL, rfctl);
1296
1297 /* Flush receive errors generated by workaround */
1298 rd32(E1000_ROC);
1299 rd32(E1000_RNBC);
1300 rd32(E1000_MPC);
1301 }
1302
1303 static struct e1000_mac_operations e1000_mac_ops_82575 = {
1304 .reset_hw = igb_reset_hw_82575,
1305 .init_hw = igb_init_hw_82575,
1306 .check_for_link = igb_check_for_link_82575,
1307 .rar_set = igb_rar_set_82575,
1308 .read_mac_addr = igb_read_mac_addr_82575,
1309 .get_speed_and_duplex = igb_get_speed_and_duplex_copper,
1310 };
1311
1312 static struct e1000_phy_operations e1000_phy_ops_82575 = {
1313 .acquire_phy = igb_acquire_phy_82575,
1314 .get_cfg_done = igb_get_cfg_done_82575,
1315 .release_phy = igb_release_phy_82575,
1316 };
1317
1318 static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
1319 .acquire_nvm = igb_acquire_nvm_82575,
1320 .read_nvm = igb_read_nvm_eerd,
1321 .release_nvm = igb_release_nvm_82575,
1322 .write_nvm = igb_write_nvm_spi,
1323 };
1324
1325 const struct e1000_info e1000_82575_info = {
1326 .get_invariants = igb_get_invariants_82575,
1327 .mac_ops = &e1000_mac_ops_82575,
1328 .phy_ops = &e1000_phy_ops_82575,
1329 .nvm_ops = &e1000_nvm_ops_82575,
1330 };
1331
Linux kernel - Deliverables
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