projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'for-linus' of git://gitserver.sunplusct.com/linux-2.6-score
[deliverable/linux.git] / drivers / net / igb / e1000_82575.c
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 /* e1000_82575
29 * e1000_82576
30 */
31
32 #include <linux/types.h>
33 #include <linux/slab.h>
34 #include <linux/if_ether.h>
35
36 #include "e1000_mac.h"
37 #include "e1000_82575.h"
38
39 static s32 igb_get_invariants_82575(struct e1000_hw *);
40 static s32 igb_acquire_phy_82575(struct e1000_hw *);
41 static void igb_release_phy_82575(struct e1000_hw *);
42 static s32 igb_acquire_nvm_82575(struct e1000_hw *);
43 static void igb_release_nvm_82575(struct e1000_hw *);
44 static s32 igb_check_for_link_82575(struct e1000_hw *);
45 static s32 igb_get_cfg_done_82575(struct e1000_hw *);
46 static s32 igb_init_hw_82575(struct e1000_hw *);
47 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
48 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
49 static s32 igb_reset_hw_82575(struct e1000_hw *);
50 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
51 static s32 igb_setup_copper_link_82575(struct e1000_hw *);
52 static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
53 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
54 static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
55 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
56 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
57 u16 *);
58 static s32 igb_get_phy_id_82575(struct e1000_hw *);
59 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
60 static bool igb_sgmii_active_82575(struct e1000_hw *);
61 static s32 igb_reset_init_script_82575(struct e1000_hw *);
62 static s32 igb_read_mac_addr_82575(struct e1000_hw *);
63 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
64
65 static s32 igb_get_invariants_82575(struct e1000_hw *hw)
66 {
67 struct e1000_phy_info *phy = &hw->phy;
68 struct e1000_nvm_info *nvm = &hw->nvm;
69 struct e1000_mac_info *mac = &hw->mac;
70 struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
71 u32 eecd;
72 s32 ret_val;
73 u16 size;
74 u32 ctrl_ext = 0;
75
76 switch (hw->device_id) {
77 case E1000_DEV_ID_82575EB_COPPER:
78 case E1000_DEV_ID_82575EB_FIBER_SERDES:
79 case E1000_DEV_ID_82575GB_QUAD_COPPER:
80 mac->type = e1000_82575;
81 break;
82 case E1000_DEV_ID_82576:
83 case E1000_DEV_ID_82576_NS:
84 case E1000_DEV_ID_82576_FIBER:
85 case E1000_DEV_ID_82576_SERDES:
86 case E1000_DEV_ID_82576_QUAD_COPPER:
87 case E1000_DEV_ID_82576_SERDES_QUAD:
88 mac->type = e1000_82576;
89 break;
90 default:
91 return -E1000_ERR_MAC_INIT;
92 break;
93 }
94
95 /* Set media type */
96 /*
97 * The 82575 uses bits 22:23 for link mode. The mode can be changed
98 * based on the EEPROM. We cannot rely upon device ID. There
99 * is no distinguishable difference between fiber and internal
100 * SerDes mode on the 82575. There can be an external PHY attached
101 * on the SGMII interface. For this, we'll set sgmii_active to true.
102 */
103 phy->media_type = e1000_media_type_copper;
104 dev_spec->sgmii_active = false;
105
106 ctrl_ext = rd32(E1000_CTRL_EXT);
107 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
108 case E1000_CTRL_EXT_LINK_MODE_SGMII:
109 dev_spec->sgmii_active = true;
110 ctrl_ext |= E1000_CTRL_I2C_ENA;
111 break;
112 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
113 hw->phy.media_type = e1000_media_type_internal_serdes;
114 ctrl_ext |= E1000_CTRL_I2C_ENA;
115 break;
116 default:
117 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
118 break;
119 }
120
121 wr32(E1000_CTRL_EXT, ctrl_ext);
122
123 /* Set mta register count */
124 mac->mta_reg_count = 128;
125 /* Set rar entry count */
126 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
127 if (mac->type == e1000_82576)
128 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
129 /* Set if part includes ASF firmware */
130 mac->asf_firmware_present = true;
131 /* Set if manageability features are enabled. */
132 mac->arc_subsystem_valid =
133 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
134 ? true : false;
135
136 /* physical interface link setup */
137 mac->ops.setup_physical_interface =
138 (hw->phy.media_type == e1000_media_type_copper)
139 ? igb_setup_copper_link_82575
140 : igb_setup_serdes_link_82575;
141
142 /* NVM initialization */
143 eecd = rd32(E1000_EECD);
144
145 nvm->opcode_bits = 8;
146 nvm->delay_usec = 1;
147 switch (nvm->override) {
148 case e1000_nvm_override_spi_large:
149 nvm->page_size = 32;
150 nvm->address_bits = 16;
151 break;
152 case e1000_nvm_override_spi_small:
153 nvm->page_size = 8;
154 nvm->address_bits = 8;
155 break;
156 default:
157 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
158 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
159 break;
160 }
161
162 nvm->type = e1000_nvm_eeprom_spi;
163
164 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
165 E1000_EECD_SIZE_EX_SHIFT);
166
167 /*
168 * Added to a constant, "size" becomes the left-shift value
169 * for setting word_size.
170 */
171 size += NVM_WORD_SIZE_BASE_SHIFT;
172
173 /* EEPROM access above 16k is unsupported */
174 if (size > 14)
175 size = 14;
176 nvm->word_size = 1 << size;
177
178 /* if 82576 then initialize mailbox parameters */
179 if (mac->type == e1000_82576)
180 igb_init_mbx_params_pf(hw);
181
182 /* setup PHY parameters */
183 if (phy->media_type != e1000_media_type_copper) {
184 phy->type = e1000_phy_none;
185 return 0;
186 }
187
188 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
189 phy->reset_delay_us = 100;
190
191 /* PHY function pointers */
192 if (igb_sgmii_active_82575(hw)) {
193 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
194 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
195 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
196 } else {
197 phy->ops.reset = igb_phy_hw_reset;
198 phy->ops.read_reg = igb_read_phy_reg_igp;
199 phy->ops.write_reg = igb_write_phy_reg_igp;
200 }
201
202 /* set lan id */
203 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
204 E1000_STATUS_FUNC_SHIFT;
205
206 /* Set phy->phy_addr and phy->id. */
207 ret_val = igb_get_phy_id_82575(hw);
208 if (ret_val)
209 return ret_val;
210
211 /* Verify phy id and set remaining function pointers */
212 switch (phy->id) {
213 case M88E1111_I_PHY_ID:
214 phy->type = e1000_phy_m88;
215 phy->ops.get_phy_info = igb_get_phy_info_m88;
216 phy->ops.get_cable_length = igb_get_cable_length_m88;
217 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
218 break;
219 case IGP03E1000_E_PHY_ID:
220 phy->type = e1000_phy_igp_3;
221 phy->ops.get_phy_info = igb_get_phy_info_igp;
222 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
223 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
224 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
225 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
226 break;
227 default:
228 return -E1000_ERR_PHY;
229 }
230
231 return 0;
232 }
233
234 /**
235 * igb_acquire_phy_82575 - Acquire rights to access PHY
236 * @hw: pointer to the HW structure
237 *
238 * Acquire access rights to the correct PHY. This is a
239 * function pointer entry point called by the api module.
240 **/
241 static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
242 {
243 u16 mask;
244
245 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
246
247 return igb_acquire_swfw_sync_82575(hw, mask);
248 }
249
250 /**
251 * igb_release_phy_82575 - Release rights to access PHY
252 * @hw: pointer to the HW structure
253 *
254 * A wrapper to release access rights to the correct PHY. This is a
255 * function pointer entry point called by the api module.
256 **/
257 static void igb_release_phy_82575(struct e1000_hw *hw)
258 {
259 u16 mask;
260
261 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
262 igb_release_swfw_sync_82575(hw, mask);
263 }
264
265 /**
266 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
267 * @hw: pointer to the HW structure
268 * @offset: register offset to be read
269 * @data: pointer to the read data
270 *
271 * Reads the PHY register at offset using the serial gigabit media independent
272 * interface and stores the retrieved information in data.
273 **/
274 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
275 u16 *data)
276 {
277 struct e1000_phy_info *phy = &hw->phy;
278 u32 i, i2ccmd = 0;
279
280 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
281 hw_dbg("PHY Address %u is out of range\n", offset);
282 return -E1000_ERR_PARAM;
283 }
284
285 /*
286 * Set up Op-code, Phy Address, and register address in the I2CCMD
287 * register. The MAC will take care of interfacing with the
288 * PHY to retrieve the desired data.
289 */
290 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
291 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
292 (E1000_I2CCMD_OPCODE_READ));
293
294 wr32(E1000_I2CCMD, i2ccmd);
295
296 /* Poll the ready bit to see if the I2C read completed */
297 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
298 udelay(50);
299 i2ccmd = rd32(E1000_I2CCMD);
300 if (i2ccmd & E1000_I2CCMD_READY)
301 break;
302 }
303 if (!(i2ccmd & E1000_I2CCMD_READY)) {
304 hw_dbg("I2CCMD Read did not complete\n");
305 return -E1000_ERR_PHY;
306 }
307 if (i2ccmd & E1000_I2CCMD_ERROR) {
308 hw_dbg("I2CCMD Error bit set\n");
309 return -E1000_ERR_PHY;
310 }
311
312 /* Need to byte-swap the 16-bit value. */
313 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
314
315 return 0;
316 }
317
318 /**
319 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
320 * @hw: pointer to the HW structure
321 * @offset: register offset to write to
322 * @data: data to write at register offset
323 *
324 * Writes the data to PHY register at the offset using the serial gigabit
325 * media independent interface.
326 **/
327 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
328 u16 data)
329 {
330 struct e1000_phy_info *phy = &hw->phy;
331 u32 i, i2ccmd = 0;
332 u16 phy_data_swapped;
333
334 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
335 hw_dbg("PHY Address %d is out of range\n", offset);
336 return -E1000_ERR_PARAM;
337 }
338
339 /* Swap the data bytes for the I2C interface */
340 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
341
342 /*
343 * Set up Op-code, Phy Address, and register address in the I2CCMD
344 * register. The MAC will take care of interfacing with the
345 * PHY to retrieve the desired data.
346 */
347 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
348 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
349 E1000_I2CCMD_OPCODE_WRITE |
350 phy_data_swapped);
351
352 wr32(E1000_I2CCMD, i2ccmd);
353
354 /* Poll the ready bit to see if the I2C read completed */
355 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
356 udelay(50);
357 i2ccmd = rd32(E1000_I2CCMD);
358 if (i2ccmd & E1000_I2CCMD_READY)
359 break;
360 }
361 if (!(i2ccmd & E1000_I2CCMD_READY)) {
362 hw_dbg("I2CCMD Write did not complete\n");
363 return -E1000_ERR_PHY;
364 }
365 if (i2ccmd & E1000_I2CCMD_ERROR) {
366 hw_dbg("I2CCMD Error bit set\n");
367 return -E1000_ERR_PHY;
368 }
369
370 return 0;
371 }
372
373 /**
374 * igb_get_phy_id_82575 - Retrieve PHY addr and id
375 * @hw: pointer to the HW structure
376 *
377 * Retrieves the PHY address and ID for both PHY's which do and do not use
378 * sgmi interface.
379 **/
380 static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
381 {
382 struct e1000_phy_info *phy = &hw->phy;
383 s32 ret_val = 0;
384 u16 phy_id;
385 u32 ctrl_ext;
386
387 /*
388 * For SGMII PHYs, we try the list of possible addresses until
389 * we find one that works. For non-SGMII PHYs
390 * (e.g. integrated copper PHYs), an address of 1 should
391 * work. The result of this function should mean phy->phy_addr
392 * and phy->id are set correctly.
393 */
394 if (!(igb_sgmii_active_82575(hw))) {
395 phy->addr = 1;
396 ret_val = igb_get_phy_id(hw);
397 goto out;
398 }
399
400 /* Power on sgmii phy if it is disabled */
401 ctrl_ext = rd32(E1000_CTRL_EXT);
402 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
403 wrfl();
404 msleep(300);
405
406 /*
407 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
408 * Therefore, we need to test 1-7
409 */
410 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
411 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
412 if (ret_val == 0) {
413 hw_dbg("Vendor ID 0x%08X read at address %u\n",
414 phy_id, phy->addr);
415 /*
416 * At the time of this writing, The M88 part is
417 * the only supported SGMII PHY product.
418 */
419 if (phy_id == M88_VENDOR)
420 break;
421 } else {
422 hw_dbg("PHY address %u was unreadable\n", phy->addr);
423 }
424 }
425
426 /* A valid PHY type couldn't be found. */
427 if (phy->addr == 8) {
428 phy->addr = 0;
429 ret_val = -E1000_ERR_PHY;
430 goto out;
431 } else {
432 ret_val = igb_get_phy_id(hw);
433 }
434
435 /* restore previous sfp cage power state */
436 wr32(E1000_CTRL_EXT, ctrl_ext);
437
438 out:
439 return ret_val;
440 }
441
442 /**
443 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
444 * @hw: pointer to the HW structure
445 *
446 * Resets the PHY using the serial gigabit media independent interface.
447 **/
448 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
449 {
450 s32 ret_val;
451
452 /*
453 * This isn't a true "hard" reset, but is the only reset
454 * available to us at this time.
455 */
456
457 hw_dbg("Soft resetting SGMII attached PHY...\n");
458
459 /*
460 * SFP documentation requires the following to configure the SPF module
461 * to work on SGMII. No further documentation is given.
462 */
463 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
464 if (ret_val)
465 goto out;
466
467 ret_val = igb_phy_sw_reset(hw);
468
469 out:
470 return ret_val;
471 }
472
473 /**
474 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
475 * @hw: pointer to the HW structure
476 * @active: true to enable LPLU, false to disable
477 *
478 * Sets the LPLU D0 state according to the active flag. When
479 * activating LPLU this function also disables smart speed
480 * and vice versa. LPLU will not be activated unless the
481 * device autonegotiation advertisement meets standards of
482 * either 10 or 10/100 or 10/100/1000 at all duplexes.
483 * This is a function pointer entry point only called by
484 * PHY setup routines.
485 **/
486 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
487 {
488 struct e1000_phy_info *phy = &hw->phy;
489 s32 ret_val;
490 u16 data;
491
492 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
493 if (ret_val)
494 goto out;
495
496 if (active) {
497 data |= IGP02E1000_PM_D0_LPLU;
498 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
499 data);
500 if (ret_val)
501 goto out;
502
503 /* When LPLU is enabled, we should disable SmartSpeed */
504 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
505 &data);
506 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
507 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
508 data);
509 if (ret_val)
510 goto out;
511 } else {
512 data &= ~IGP02E1000_PM_D0_LPLU;
513 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
514 data);
515 /*
516 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
517 * during Dx states where the power conservation is most
518 * important. During driver activity we should enable
519 * SmartSpeed, so performance is maintained.
520 */
521 if (phy->smart_speed == e1000_smart_speed_on) {
522 ret_val = phy->ops.read_reg(hw,
523 IGP01E1000_PHY_PORT_CONFIG, &data);
524 if (ret_val)
525 goto out;
526
527 data |= IGP01E1000_PSCFR_SMART_SPEED;
528 ret_val = phy->ops.write_reg(hw,
529 IGP01E1000_PHY_PORT_CONFIG, data);
530 if (ret_val)
531 goto out;
532 } else if (phy->smart_speed == e1000_smart_speed_off) {
533 ret_val = phy->ops.read_reg(hw,
534 IGP01E1000_PHY_PORT_CONFIG, &data);
535 if (ret_val)
536 goto out;
537
538 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
539 ret_val = phy->ops.write_reg(hw,
540 IGP01E1000_PHY_PORT_CONFIG, data);
541 if (ret_val)
542 goto out;
543 }
544 }
545
546 out:
547 return ret_val;
548 }
549
550 /**
551 * igb_acquire_nvm_82575 - Request for access to EEPROM
552 * @hw: pointer to the HW structure
553 *
554 * Acquire the necessary semaphores for exclusive access to the EEPROM.
555 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
556 * Return successful if access grant bit set, else clear the request for
557 * EEPROM access and return -E1000_ERR_NVM (-1).
558 **/
559 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
560 {
561 s32 ret_val;
562
563 ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
564 if (ret_val)
565 goto out;
566
567 ret_val = igb_acquire_nvm(hw);
568
569 if (ret_val)
570 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
571
572 out:
573 return ret_val;
574 }
575
576 /**
577 * igb_release_nvm_82575 - Release exclusive access to EEPROM
578 * @hw: pointer to the HW structure
579 *
580 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
581 * then release the semaphores acquired.
582 **/
583 static void igb_release_nvm_82575(struct e1000_hw *hw)
584 {
585 igb_release_nvm(hw);
586 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
587 }
588
589 /**
590 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
591 * @hw: pointer to the HW structure
592 * @mask: specifies which semaphore to acquire
593 *
594 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
595 * will also specify which port we're acquiring the lock for.
596 **/
597 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
598 {
599 u32 swfw_sync;
600 u32 swmask = mask;
601 u32 fwmask = mask << 16;
602 s32 ret_val = 0;
603 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
604
605 while (i < timeout) {
606 if (igb_get_hw_semaphore(hw)) {
607 ret_val = -E1000_ERR_SWFW_SYNC;
608 goto out;
609 }
610
611 swfw_sync = rd32(E1000_SW_FW_SYNC);
612 if (!(swfw_sync & (fwmask | swmask)))
613 break;
614
615 /*
616 * Firmware currently using resource (fwmask)
617 * or other software thread using resource (swmask)
618 */
619 igb_put_hw_semaphore(hw);
620 mdelay(5);
621 i++;
622 }
623
624 if (i == timeout) {
625 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
626 ret_val = -E1000_ERR_SWFW_SYNC;
627 goto out;
628 }
629
630 swfw_sync |= swmask;
631 wr32(E1000_SW_FW_SYNC, swfw_sync);
632
633 igb_put_hw_semaphore(hw);
634
635 out:
636 return ret_val;
637 }
638
639 /**
640 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
641 * @hw: pointer to the HW structure
642 * @mask: specifies which semaphore to acquire
643 *
644 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
645 * will also specify which port we're releasing the lock for.
646 **/
647 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
648 {
649 u32 swfw_sync;
650
651 while (igb_get_hw_semaphore(hw) != 0);
652 /* Empty */
653
654 swfw_sync = rd32(E1000_SW_FW_SYNC);
655 swfw_sync &= ~mask;
656 wr32(E1000_SW_FW_SYNC, swfw_sync);
657
658 igb_put_hw_semaphore(hw);
659 }
660
661 /**
662 * igb_get_cfg_done_82575 - Read config done bit
663 * @hw: pointer to the HW structure
664 *
665 * Read the management control register for the config done bit for
666 * completion status. NOTE: silicon which is EEPROM-less will fail trying
667 * to read the config done bit, so an error is *ONLY* logged and returns
668 * 0. If we were to return with error, EEPROM-less silicon
669 * would not be able to be reset or change link.
670 **/
671 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
672 {
673 s32 timeout = PHY_CFG_TIMEOUT;
674 s32 ret_val = 0;
675 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
676
677 if (hw->bus.func == 1)
678 mask = E1000_NVM_CFG_DONE_PORT_1;
679
680 while (timeout) {
681 if (rd32(E1000_EEMNGCTL) & mask)
682 break;
683 msleep(1);
684 timeout--;
685 }
686 if (!timeout)
687 hw_dbg("MNG configuration cycle has not completed.\n");
688
689 /* If EEPROM is not marked present, init the PHY manually */
690 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
691 (hw->phy.type == e1000_phy_igp_3))
692 igb_phy_init_script_igp3(hw);
693
694 return ret_val;
695 }
696
697 /**
698 * igb_check_for_link_82575 - Check for link
699 * @hw: pointer to the HW structure
700 *
701 * If sgmii is enabled, then use the pcs register to determine link, otherwise
702 * use the generic interface for determining link.
703 **/
704 static s32 igb_check_for_link_82575(struct e1000_hw *hw)
705 {
706 s32 ret_val;
707 u16 speed, duplex;
708
709 /* SGMII link check is done through the PCS register. */
710 if ((hw->phy.media_type != e1000_media_type_copper) ||
711 (igb_sgmii_active_82575(hw))) {
712 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
713 &duplex);
714 /*
715 * Use this flag to determine if link needs to be checked or
716 * not. If we have link clear the flag so that we do not
717 * continue to check for link.
718 */
719 hw->mac.get_link_status = !hw->mac.serdes_has_link;
720 } else {
721 ret_val = igb_check_for_copper_link(hw);
722 }
723
724 return ret_val;
725 }
726 /**
727 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
728 * @hw: pointer to the HW structure
729 * @speed: stores the current speed
730 * @duplex: stores the current duplex
731 *
732 * Using the physical coding sub-layer (PCS), retrieve the current speed and
733 * duplex, then store the values in the pointers provided.
734 **/
735 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
736 u16 *duplex)
737 {
738 struct e1000_mac_info *mac = &hw->mac;
739 u32 pcs;
740
741 /* Set up defaults for the return values of this function */
742 mac->serdes_has_link = false;
743 *speed = 0;
744 *duplex = 0;
745
746 /*
747 * Read the PCS Status register for link state. For non-copper mode,
748 * the status register is not accurate. The PCS status register is
749 * used instead.
750 */
751 pcs = rd32(E1000_PCS_LSTAT);
752
753 /*
754 * The link up bit determines when link is up on autoneg. The sync ok
755 * gets set once both sides sync up and agree upon link. Stable link
756 * can be determined by checking for both link up and link sync ok
757 */
758 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
759 mac->serdes_has_link = true;
760
761 /* Detect and store PCS speed */
762 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
763 *speed = SPEED_1000;
764 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
765 *speed = SPEED_100;
766 } else {
767 *speed = SPEED_10;
768 }
769
770 /* Detect and store PCS duplex */
771 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
772 *duplex = FULL_DUPLEX;
773 } else {
774 *duplex = HALF_DUPLEX;
775 }
776 }
777
778 return 0;
779 }
780
781 /**
782 * igb_shutdown_serdes_link_82575 - Remove link during power down
783 * @hw: pointer to the HW structure
784 *
785 * In the case of fiber serdes, shut down optics and PCS on driver unload
786 * when management pass thru is not enabled.
787 **/
788 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
789 {
790 u32 reg;
791
792 if (hw->phy.media_type != e1000_media_type_internal_serdes ||
793 igb_sgmii_active_82575(hw))
794 return;
795
796 /* if the management interface is not enabled, then power down */
797 if (!igb_enable_mng_pass_thru(hw)) {
798 /* Disable PCS to turn off link */
799 reg = rd32(E1000_PCS_CFG0);
800 reg &= ~E1000_PCS_CFG_PCS_EN;
801 wr32(E1000_PCS_CFG0, reg);
802
803 /* shutdown the laser */
804 reg = rd32(E1000_CTRL_EXT);
805 reg |= E1000_CTRL_EXT_SDP3_DATA;
806 wr32(E1000_CTRL_EXT, reg);
807
808 /* flush the write to verify completion */
809 wrfl();
810 msleep(1);
811 }
812
813 return;
814 }
815
816 /**
817 * igb_reset_hw_82575 - Reset hardware
818 * @hw: pointer to the HW structure
819 *
820 * This resets the hardware into a known state. This is a
821 * function pointer entry point called by the api module.
822 **/
823 static s32 igb_reset_hw_82575(struct e1000_hw *hw)
824 {
825 u32 ctrl, icr;
826 s32 ret_val;
827
828 /*
829 * Prevent the PCI-E bus from sticking if there is no TLP connection
830 * on the last TLP read/write transaction when MAC is reset.
831 */
832 ret_val = igb_disable_pcie_master(hw);
833 if (ret_val)
834 hw_dbg("PCI-E Master disable polling has failed.\n");
835
836 /* set the completion timeout for interface */
837 ret_val = igb_set_pcie_completion_timeout(hw);
838 if (ret_val) {
839 hw_dbg("PCI-E Set completion timeout has failed.\n");
840 }
841
842 hw_dbg("Masking off all interrupts\n");
843 wr32(E1000_IMC, 0xffffffff);
844
845 wr32(E1000_RCTL, 0);
846 wr32(E1000_TCTL, E1000_TCTL_PSP);
847 wrfl();
848
849 msleep(10);
850
851 ctrl = rd32(E1000_CTRL);
852
853 hw_dbg("Issuing a global reset to MAC\n");
854 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
855
856 ret_val = igb_get_auto_rd_done(hw);
857 if (ret_val) {
858 /*
859 * When auto config read does not complete, do not
860 * return with an error. This can happen in situations
861 * where there is no eeprom and prevents getting link.
862 */
863 hw_dbg("Auto Read Done did not complete\n");
864 }
865
866 /* If EEPROM is not present, run manual init scripts */
867 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
868 igb_reset_init_script_82575(hw);
869
870 /* Clear any pending interrupt events. */
871 wr32(E1000_IMC, 0xffffffff);
872 icr = rd32(E1000_ICR);
873
874 /* Install any alternate MAC address into RAR0 */
875 ret_val = igb_check_alt_mac_addr(hw);
876
877 return ret_val;
878 }
879
880 /**
881 * igb_init_hw_82575 - Initialize hardware
882 * @hw: pointer to the HW structure
883 *
884 * This inits the hardware readying it for operation.
885 **/
886 static s32 igb_init_hw_82575(struct e1000_hw *hw)
887 {
888 struct e1000_mac_info *mac = &hw->mac;
889 s32 ret_val;
890 u16 i, rar_count = mac->rar_entry_count;
891
892 /* Initialize identification LED */
893 ret_val = igb_id_led_init(hw);
894 if (ret_val) {
895 hw_dbg("Error initializing identification LED\n");
896 /* This is not fatal and we should not stop init due to this */
897 }
898
899 /* Disabling VLAN filtering */
900 hw_dbg("Initializing the IEEE VLAN\n");
901 igb_clear_vfta(hw);
902
903 /* Setup the receive address */
904 igb_init_rx_addrs(hw, rar_count);
905
906 /* Zero out the Multicast HASH table */
907 hw_dbg("Zeroing the MTA\n");
908 for (i = 0; i < mac->mta_reg_count; i++)
909 array_wr32(E1000_MTA, i, 0);
910
911 /* Setup link and flow control */
912 ret_val = igb_setup_link(hw);
913
914 /*
915 * Clear all of the statistics registers (clear on read). It is
916 * important that we do this after we have tried to establish link
917 * because the symbol error count will increment wildly if there
918 * is no link.
919 */
920 igb_clear_hw_cntrs_82575(hw);
921
922 return ret_val;
923 }
924
925 /**
926 * igb_setup_copper_link_82575 - Configure copper link settings
927 * @hw: pointer to the HW structure
928 *
929 * Configures the link for auto-neg or forced speed and duplex. Then we check
930 * for link, once link is established calls to configure collision distance
931 * and flow control are called.
932 **/
933 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
934 {
935 u32 ctrl;
936 s32 ret_val;
937 bool link;
938
939 ctrl = rd32(E1000_CTRL);
940 ctrl |= E1000_CTRL_SLU;
941 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
942 wr32(E1000_CTRL, ctrl);
943
944 ret_val = igb_setup_serdes_link_82575(hw);
945 if (ret_val)
946 goto out;
947
948 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
949 ret_val = hw->phy.ops.reset(hw);
950 if (ret_val) {
951 hw_dbg("Error resetting the PHY.\n");
952 goto out;
953 }
954 }
955 switch (hw->phy.type) {
956 case e1000_phy_m88:
957 ret_val = igb_copper_link_setup_m88(hw);
958 break;
959 case e1000_phy_igp_3:
960 ret_val = igb_copper_link_setup_igp(hw);
961 break;
962 default:
963 ret_val = -E1000_ERR_PHY;
964 break;
965 }
966
967 if (ret_val)
968 goto out;
969
970 if (hw->mac.autoneg) {
971 /*
972 * Setup autoneg and flow control advertisement
973 * and perform autonegotiation.
974 */
975 ret_val = igb_copper_link_autoneg(hw);
976 if (ret_val)
977 goto out;
978 } else {
979 /*
980 * PHY will be set to 10H, 10F, 100H or 100F
981 * depending on user settings.
982 */
983 hw_dbg("Forcing Speed and Duplex\n");
984 ret_val = hw->phy.ops.force_speed_duplex(hw);
985 if (ret_val) {
986 hw_dbg("Error Forcing Speed and Duplex\n");
987 goto out;
988 }
989 }
990
991 /*
992 * Check link status. Wait up to 100 microseconds for link to become
993 * valid.
994 */
995 ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link);
996 if (ret_val)
997 goto out;
998
999 if (link) {
1000 hw_dbg("Valid link established!!!\n");
1001 /* Config the MAC and PHY after link is up */
1002 igb_config_collision_dist(hw);
1003 ret_val = igb_config_fc_after_link_up(hw);
1004 } else {
1005 hw_dbg("Unable to establish link!!!\n");
1006 }
1007
1008 out:
1009 return ret_val;
1010 }
1011
1012 /**
1013 * igb_setup_serdes_link_82575 - Setup link for fiber/serdes
1014 * @hw: pointer to the HW structure
1015 *
1016 * Configures speed and duplex for fiber and serdes links.
1017 **/
1018 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
1019 {
1020 u32 ctrl_reg, reg;
1021
1022 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1023 !igb_sgmii_active_82575(hw))
1024 return 0;
1025
1026 /*
1027 * On the 82575, SerDes loopback mode persists until it is
1028 * explicitly turned off or a power cycle is performed. A read to
1029 * the register does not indicate its status. Therefore, we ensure
1030 * loopback mode is disabled during initialization.
1031 */
1032 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1033
1034 /* power on the sfp cage if present */
1035 reg = rd32(E1000_CTRL_EXT);
1036 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1037 wr32(E1000_CTRL_EXT, reg);
1038
1039 ctrl_reg = rd32(E1000_CTRL);
1040 ctrl_reg |= E1000_CTRL_SLU;
1041
1042 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1043 /* set both sw defined pins */
1044 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1045
1046 /* Set switch control to serdes energy detect */
1047 reg = rd32(E1000_CONNSW);
1048 reg |= E1000_CONNSW_ENRGSRC;
1049 wr32(E1000_CONNSW, reg);
1050 }
1051
1052 reg = rd32(E1000_PCS_LCTL);
1053
1054 if (igb_sgmii_active_82575(hw)) {
1055 /* allow time for SFP cage to power up phy */
1056 msleep(300);
1057
1058 /* AN time out should be disabled for SGMII mode */
1059 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1060 } else {
1061 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1062 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1063 }
1064
1065 wr32(E1000_CTRL, ctrl_reg);
1066
1067 /*
1068 * New SerDes mode allows for forcing speed or autonegotiating speed
1069 * at 1gb. Autoneg should be default set by most drivers. This is the
1070 * mode that will be compatible with older link partners and switches.
1071 * However, both are supported by the hardware and some drivers/tools.
1072 */
1073
1074 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1075 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1076
1077 /*
1078 * We force flow control to prevent the CTRL register values from being
1079 * overwritten by the autonegotiated flow control values
1080 */
1081 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1082
1083 /*
1084 * we always set sgmii to autoneg since it is the phy that will be
1085 * forcing the link and the serdes is just a go-between
1086 */
1087 if (hw->mac.autoneg || igb_sgmii_active_82575(hw)) {
1088 /* Set PCS register for autoneg */
1089 reg |= E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1090 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1091 E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1092 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1093 hw_dbg("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg);
1094 } else {
1095 /* Set PCS register for forced speed */
1096 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1097 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1098 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1099 E1000_PCS_LCTL_FSD | /* Force Speed */
1100 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1101 hw_dbg("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg);
1102 }
1103
1104 wr32(E1000_PCS_LCTL, reg);
1105
1106 if (!igb_sgmii_active_82575(hw))
1107 igb_force_mac_fc(hw);
1108
1109 return 0;
1110 }
1111
1112 /**
1113 * igb_sgmii_active_82575 - Return sgmii state
1114 * @hw: pointer to the HW structure
1115 *
1116 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1117 * which can be enabled for use in the embedded applications. Simply
1118 * return the current state of the sgmii interface.
1119 **/
1120 static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1121 {
1122 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1123 return dev_spec->sgmii_active;
1124 }
1125
1126 /**
1127 * igb_reset_init_script_82575 - Inits HW defaults after reset
1128 * @hw: pointer to the HW structure
1129 *
1130 * Inits recommended HW defaults after a reset when there is no EEPROM
1131 * detected. This is only for the 82575.
1132 **/
1133 static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1134 {
1135 if (hw->mac.type == e1000_82575) {
1136 hw_dbg("Running reset init script for 82575\n");
1137 /* SerDes configuration via SERDESCTRL */
1138 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1139 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1140 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1141 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1142
1143 /* CCM configuration via CCMCTL register */
1144 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1145 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1146
1147 /* PCIe lanes configuration */
1148 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1149 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1150 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1151 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1152
1153 /* PCIe PLL Configuration */
1154 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1155 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1156 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1157 }
1158
1159 return 0;
1160 }
1161
1162 /**
1163 * igb_read_mac_addr_82575 - Read device MAC address
1164 * @hw: pointer to the HW structure
1165 **/
1166 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1167 {
1168 s32 ret_val = 0;
1169
1170 if (igb_check_alt_mac_addr(hw))
1171 ret_val = igb_read_mac_addr(hw);
1172
1173 return ret_val;
1174 }
1175
1176 /**
1177 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1178 * @hw: pointer to the HW structure
1179 *
1180 * Clears the hardware counters by reading the counter registers.
1181 **/
1182 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1183 {
1184 u32 temp;
1185
1186 igb_clear_hw_cntrs_base(hw);
1187
1188 temp = rd32(E1000_PRC64);
1189 temp = rd32(E1000_PRC127);
1190 temp = rd32(E1000_PRC255);
1191 temp = rd32(E1000_PRC511);
1192 temp = rd32(E1000_PRC1023);
1193 temp = rd32(E1000_PRC1522);
1194 temp = rd32(E1000_PTC64);
1195 temp = rd32(E1000_PTC127);
1196 temp = rd32(E1000_PTC255);
1197 temp = rd32(E1000_PTC511);
1198 temp = rd32(E1000_PTC1023);
1199 temp = rd32(E1000_PTC1522);
1200
1201 temp = rd32(E1000_ALGNERRC);
1202 temp = rd32(E1000_RXERRC);
1203 temp = rd32(E1000_TNCRS);
1204 temp = rd32(E1000_CEXTERR);
1205 temp = rd32(E1000_TSCTC);
1206 temp = rd32(E1000_TSCTFC);
1207
1208 temp = rd32(E1000_MGTPRC);
1209 temp = rd32(E1000_MGTPDC);
1210 temp = rd32(E1000_MGTPTC);
1211
1212 temp = rd32(E1000_IAC);
1213 temp = rd32(E1000_ICRXOC);
1214
1215 temp = rd32(E1000_ICRXPTC);
1216 temp = rd32(E1000_ICRXATC);
1217 temp = rd32(E1000_ICTXPTC);
1218 temp = rd32(E1000_ICTXATC);
1219 temp = rd32(E1000_ICTXQEC);
1220 temp = rd32(E1000_ICTXQMTC);
1221 temp = rd32(E1000_ICRXDMTC);
1222
1223 temp = rd32(E1000_CBTMPC);
1224 temp = rd32(E1000_HTDPMC);
1225 temp = rd32(E1000_CBRMPC);
1226 temp = rd32(E1000_RPTHC);
1227 temp = rd32(E1000_HGPTC);
1228 temp = rd32(E1000_HTCBDPC);
1229 temp = rd32(E1000_HGORCL);
1230 temp = rd32(E1000_HGORCH);
1231 temp = rd32(E1000_HGOTCL);
1232 temp = rd32(E1000_HGOTCH);
1233 temp = rd32(E1000_LENERRS);
1234
1235 /* This register should not be read in copper configurations */
1236 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1237 igb_sgmii_active_82575(hw))
1238 temp = rd32(E1000_SCVPC);
1239 }
1240
1241 /**
1242 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1243 * @hw: pointer to the HW structure
1244 *
1245 * After rx enable if managability is enabled then there is likely some
1246 * bad data at the start of the fifo and possibly in the DMA fifo. This
1247 * function clears the fifos and flushes any packets that came in as rx was
1248 * being enabled.
1249 **/
1250 void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1251 {
1252 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1253 int i, ms_wait;
1254
1255 if (hw->mac.type != e1000_82575 ||
1256 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1257 return;
1258
1259 /* Disable all RX queues */
1260 for (i = 0; i < 4; i++) {
1261 rxdctl[i] = rd32(E1000_RXDCTL(i));
1262 wr32(E1000_RXDCTL(i),
1263 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1264 }
1265 /* Poll all queues to verify they have shut down */
1266 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1267 msleep(1);
1268 rx_enabled = 0;
1269 for (i = 0; i < 4; i++)
1270 rx_enabled |= rd32(E1000_RXDCTL(i));
1271 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1272 break;
1273 }
1274
1275 if (ms_wait == 10)
1276 hw_dbg("Queue disable timed out after 10ms\n");
1277
1278 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1279 * incoming packets are rejected. Set enable and wait 2ms so that
1280 * any packet that was coming in as RCTL.EN was set is flushed
1281 */
1282 rfctl = rd32(E1000_RFCTL);
1283 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1284
1285 rlpml = rd32(E1000_RLPML);
1286 wr32(E1000_RLPML, 0);
1287
1288 rctl = rd32(E1000_RCTL);
1289 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1290 temp_rctl |= E1000_RCTL_LPE;
1291
1292 wr32(E1000_RCTL, temp_rctl);
1293 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1294 wrfl();
1295 msleep(2);
1296
1297 /* Enable RX queues that were previously enabled and restore our
1298 * previous state
1299 */
1300 for (i = 0; i < 4; i++)
1301 wr32(E1000_RXDCTL(i), rxdctl[i]);
1302 wr32(E1000_RCTL, rctl);
1303 wrfl();
1304
1305 wr32(E1000_RLPML, rlpml);
1306 wr32(E1000_RFCTL, rfctl);
1307
1308 /* Flush receive errors generated by workaround */
1309 rd32(E1000_ROC);
1310 rd32(E1000_RNBC);
1311 rd32(E1000_MPC);
1312 }
1313
1314 /**
1315 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1316 * @hw: pointer to the HW structure
1317 *
1318 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1319 * however the hardware default for these parts is 500us to 1ms which is less
1320 * than the 10ms recommended by the pci-e spec. To address this we need to
1321 * increase the value to either 10ms to 200ms for capability version 1 config,
1322 * or 16ms to 55ms for version 2.
1323 **/
1324 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1325 {
1326 u32 gcr = rd32(E1000_GCR);
1327 s32 ret_val = 0;
1328 u16 pcie_devctl2;
1329
1330 /* only take action if timeout value is defaulted to 0 */
1331 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1332 goto out;
1333
1334 /*
1335 * if capababilities version is type 1 we can write the
1336 * timeout of 10ms to 200ms through the GCR register
1337 */
1338 if (!(gcr & E1000_GCR_CAP_VER2)) {
1339 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
1340 goto out;
1341 }
1342
1343 /*
1344 * for version 2 capabilities we need to write the config space
1345 * directly in order to set the completion timeout value for
1346 * 16ms to 55ms
1347 */
1348 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1349 &pcie_devctl2);
1350 if (ret_val)
1351 goto out;
1352
1353 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
1354
1355 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1356 &pcie_devctl2);
1357 out:
1358 /* disable completion timeout resend */
1359 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
1360
1361 wr32(E1000_GCR, gcr);
1362 return ret_val;
1363 }
1364
1365 /**
1366 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
1367 * @hw: pointer to the hardware struct
1368 * @enable: state to enter, either enabled or disabled
1369 *
1370 * enables/disables L2 switch loopback functionality.
1371 **/
1372 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
1373 {
1374 u32 dtxswc = rd32(E1000_DTXSWC);
1375
1376 if (enable)
1377 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1378 else
1379 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1380
1381 wr32(E1000_DTXSWC, dtxswc);
1382 }
1383
1384 /**
1385 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
1386 * @hw: pointer to the hardware struct
1387 * @enable: state to enter, either enabled or disabled
1388 *
1389 * enables/disables replication of packets across multiple pools.
1390 **/
1391 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
1392 {
1393 u32 vt_ctl = rd32(E1000_VT_CTL);
1394
1395 if (enable)
1396 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
1397 else
1398 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
1399
1400 wr32(E1000_VT_CTL, vt_ctl);
1401 }
1402
1403 static struct e1000_mac_operations e1000_mac_ops_82575 = {
1404 .reset_hw = igb_reset_hw_82575,
1405 .init_hw = igb_init_hw_82575,
1406 .check_for_link = igb_check_for_link_82575,
1407 .rar_set = igb_rar_set,
1408 .read_mac_addr = igb_read_mac_addr_82575,
1409 .get_speed_and_duplex = igb_get_speed_and_duplex_copper,
1410 };
1411
1412 static struct e1000_phy_operations e1000_phy_ops_82575 = {
1413 .acquire = igb_acquire_phy_82575,
1414 .get_cfg_done = igb_get_cfg_done_82575,
1415 .release = igb_release_phy_82575,
1416 };
1417
1418 static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
1419 .acquire = igb_acquire_nvm_82575,
1420 .read = igb_read_nvm_eerd,
1421 .release = igb_release_nvm_82575,
1422 .write = igb_write_nvm_spi,
1423 };
1424
1425 const struct e1000_info e1000_82575_info = {
1426 .get_invariants = igb_get_invariants_82575,
1427 .mac_ops = &e1000_mac_ops_82575,
1428 .phy_ops = &e1000_phy_ops_82575,
1429 .nvm_ops = &e1000_nvm_ops_82575,
1430 };
1431
Linux kernel - Deliverables
This page took 0.269612 seconds and 6 git commands to generate.