projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'timers-timekeeping-for-linus' of git://git.kernel.org/pub/scm/linux...
[deliverable/linux.git] / drivers / net / igb / e1000_82575.c
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 /* e1000_82575
29 * e1000_82576
30 */
31
32 #include <linux/types.h>
33 #include <linux/if_ether.h>
34
35 #include "e1000_mac.h"
36 #include "e1000_82575.h"
37
38 static s32 igb_get_invariants_82575(struct e1000_hw *);
39 static s32 igb_acquire_phy_82575(struct e1000_hw *);
40 static void igb_release_phy_82575(struct e1000_hw *);
41 static s32 igb_acquire_nvm_82575(struct e1000_hw *);
42 static void igb_release_nvm_82575(struct e1000_hw *);
43 static s32 igb_check_for_link_82575(struct e1000_hw *);
44 static s32 igb_get_cfg_done_82575(struct e1000_hw *);
45 static s32 igb_init_hw_82575(struct e1000_hw *);
46 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
47 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
48 static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
49 static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
50 static s32 igb_reset_hw_82575(struct e1000_hw *);
51 static s32 igb_reset_hw_82580(struct e1000_hw *);
52 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
53 static s32 igb_setup_copper_link_82575(struct e1000_hw *);
54 static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
55 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
56 static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
57 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
58 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
59 u16 *);
60 static s32 igb_get_phy_id_82575(struct e1000_hw *);
61 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
62 static bool igb_sgmii_active_82575(struct e1000_hw *);
63 static s32 igb_reset_init_script_82575(struct e1000_hw *);
64 static s32 igb_read_mac_addr_82575(struct e1000_hw *);
65 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
66 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw);
67
68 static const u16 e1000_82580_rxpbs_table[] =
69 { 36, 72, 144, 1, 2, 4, 8, 16,
70 35, 70, 140 };
71 #define E1000_82580_RXPBS_TABLE_SIZE \
72 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
73
74 /**
75 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
76 * @hw: pointer to the HW structure
77 *
78 * Called to determine if the I2C pins are being used for I2C or as an
79 * external MDIO interface since the two options are mutually exclusive.
80 **/
81 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
82 {
83 u32 reg = 0;
84 bool ext_mdio = false;
85
86 switch (hw->mac.type) {
87 case e1000_82575:
88 case e1000_82576:
89 reg = rd32(E1000_MDIC);
90 ext_mdio = !!(reg & E1000_MDIC_DEST);
91 break;
92 case e1000_82580:
93 case e1000_i350:
94 reg = rd32(E1000_MDICNFG);
95 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
96 break;
97 default:
98 break;
99 }
100 return ext_mdio;
101 }
102
103 static s32 igb_get_invariants_82575(struct e1000_hw *hw)
104 {
105 struct e1000_phy_info *phy = &hw->phy;
106 struct e1000_nvm_info *nvm = &hw->nvm;
107 struct e1000_mac_info *mac = &hw->mac;
108 struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
109 u32 eecd;
110 s32 ret_val;
111 u16 size;
112 u32 ctrl_ext = 0;
113
114 switch (hw->device_id) {
115 case E1000_DEV_ID_82575EB_COPPER:
116 case E1000_DEV_ID_82575EB_FIBER_SERDES:
117 case E1000_DEV_ID_82575GB_QUAD_COPPER:
118 mac->type = e1000_82575;
119 break;
120 case E1000_DEV_ID_82576:
121 case E1000_DEV_ID_82576_NS:
122 case E1000_DEV_ID_82576_NS_SERDES:
123 case E1000_DEV_ID_82576_FIBER:
124 case E1000_DEV_ID_82576_SERDES:
125 case E1000_DEV_ID_82576_QUAD_COPPER:
126 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
127 case E1000_DEV_ID_82576_SERDES_QUAD:
128 mac->type = e1000_82576;
129 break;
130 case E1000_DEV_ID_82580_COPPER:
131 case E1000_DEV_ID_82580_FIBER:
132 case E1000_DEV_ID_82580_SERDES:
133 case E1000_DEV_ID_82580_SGMII:
134 case E1000_DEV_ID_82580_COPPER_DUAL:
135 mac->type = e1000_82580;
136 break;
137 case E1000_DEV_ID_I350_COPPER:
138 case E1000_DEV_ID_I350_FIBER:
139 case E1000_DEV_ID_I350_SERDES:
140 case E1000_DEV_ID_I350_SGMII:
141 mac->type = e1000_i350;
142 break;
143 default:
144 return -E1000_ERR_MAC_INIT;
145 break;
146 }
147
148 /* Set media type */
149 /*
150 * The 82575 uses bits 22:23 for link mode. The mode can be changed
151 * based on the EEPROM. We cannot rely upon device ID. There
152 * is no distinguishable difference between fiber and internal
153 * SerDes mode on the 82575. There can be an external PHY attached
154 * on the SGMII interface. For this, we'll set sgmii_active to true.
155 */
156 phy->media_type = e1000_media_type_copper;
157 dev_spec->sgmii_active = false;
158
159 ctrl_ext = rd32(E1000_CTRL_EXT);
160 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
161 case E1000_CTRL_EXT_LINK_MODE_SGMII:
162 dev_spec->sgmii_active = true;
163 break;
164 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
165 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
166 hw->phy.media_type = e1000_media_type_internal_serdes;
167 break;
168 default:
169 break;
170 }
171
172 /* Set mta register count */
173 mac->mta_reg_count = 128;
174 /* Set rar entry count */
175 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
176 if (mac->type == e1000_82576)
177 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
178 if (mac->type == e1000_82580)
179 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
180 if (mac->type == e1000_i350)
181 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
182 /* reset */
183 if (mac->type >= e1000_82580)
184 mac->ops.reset_hw = igb_reset_hw_82580;
185 else
186 mac->ops.reset_hw = igb_reset_hw_82575;
187 /* Set if part includes ASF firmware */
188 mac->asf_firmware_present = true;
189 /* Set if manageability features are enabled. */
190 mac->arc_subsystem_valid =
191 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
192 ? true : false;
193
194 /* physical interface link setup */
195 mac->ops.setup_physical_interface =
196 (hw->phy.media_type == e1000_media_type_copper)
197 ? igb_setup_copper_link_82575
198 : igb_setup_serdes_link_82575;
199
200 /* NVM initialization */
201 eecd = rd32(E1000_EECD);
202
203 nvm->opcode_bits = 8;
204 nvm->delay_usec = 1;
205 switch (nvm->override) {
206 case e1000_nvm_override_spi_large:
207 nvm->page_size = 32;
208 nvm->address_bits = 16;
209 break;
210 case e1000_nvm_override_spi_small:
211 nvm->page_size = 8;
212 nvm->address_bits = 8;
213 break;
214 default:
215 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
216 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
217 break;
218 }
219
220 nvm->type = e1000_nvm_eeprom_spi;
221
222 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
223 E1000_EECD_SIZE_EX_SHIFT);
224
225 /*
226 * Added to a constant, "size" becomes the left-shift value
227 * for setting word_size.
228 */
229 size += NVM_WORD_SIZE_BASE_SHIFT;
230
231 /* EEPROM access above 16k is unsupported */
232 if (size > 14)
233 size = 14;
234 nvm->word_size = 1 << size;
235
236 /* if 82576 then initialize mailbox parameters */
237 if (mac->type == e1000_82576)
238 igb_init_mbx_params_pf(hw);
239
240 /* setup PHY parameters */
241 if (phy->media_type != e1000_media_type_copper) {
242 phy->type = e1000_phy_none;
243 return 0;
244 }
245
246 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
247 phy->reset_delay_us = 100;
248
249 ctrl_ext = rd32(E1000_CTRL_EXT);
250
251 /* PHY function pointers */
252 if (igb_sgmii_active_82575(hw)) {
253 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
254 ctrl_ext |= E1000_CTRL_I2C_ENA;
255 } else {
256 phy->ops.reset = igb_phy_hw_reset;
257 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
258 }
259
260 wr32(E1000_CTRL_EXT, ctrl_ext);
261 igb_reset_mdicnfg_82580(hw);
262
263 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
264 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
265 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
266 } else if (hw->mac.type >= e1000_82580) {
267 phy->ops.read_reg = igb_read_phy_reg_82580;
268 phy->ops.write_reg = igb_write_phy_reg_82580;
269 } else {
270 phy->ops.read_reg = igb_read_phy_reg_igp;
271 phy->ops.write_reg = igb_write_phy_reg_igp;
272 }
273
274 /* set lan id */
275 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
276 E1000_STATUS_FUNC_SHIFT;
277
278 /* Set phy->phy_addr and phy->id. */
279 ret_val = igb_get_phy_id_82575(hw);
280 if (ret_val)
281 return ret_val;
282
283 /* Verify phy id and set remaining function pointers */
284 switch (phy->id) {
285 case M88E1111_I_PHY_ID:
286 phy->type = e1000_phy_m88;
287 phy->ops.get_phy_info = igb_get_phy_info_m88;
288 phy->ops.get_cable_length = igb_get_cable_length_m88;
289 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
290 break;
291 case IGP03E1000_E_PHY_ID:
292 phy->type = e1000_phy_igp_3;
293 phy->ops.get_phy_info = igb_get_phy_info_igp;
294 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
295 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
296 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
297 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
298 break;
299 case I82580_I_PHY_ID:
300 case I350_I_PHY_ID:
301 phy->type = e1000_phy_82580;
302 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_82580;
303 phy->ops.get_cable_length = igb_get_cable_length_82580;
304 phy->ops.get_phy_info = igb_get_phy_info_82580;
305 break;
306 default:
307 return -E1000_ERR_PHY;
308 }
309
310 return 0;
311 }
312
313 /**
314 * igb_acquire_phy_82575 - Acquire rights to access PHY
315 * @hw: pointer to the HW structure
316 *
317 * Acquire access rights to the correct PHY. This is a
318 * function pointer entry point called by the api module.
319 **/
320 static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
321 {
322 u16 mask = E1000_SWFW_PHY0_SM;
323
324 if (hw->bus.func == E1000_FUNC_1)
325 mask = E1000_SWFW_PHY1_SM;
326 else if (hw->bus.func == E1000_FUNC_2)
327 mask = E1000_SWFW_PHY2_SM;
328 else if (hw->bus.func == E1000_FUNC_3)
329 mask = E1000_SWFW_PHY3_SM;
330
331 return igb_acquire_swfw_sync_82575(hw, mask);
332 }
333
334 /**
335 * igb_release_phy_82575 - Release rights to access PHY
336 * @hw: pointer to the HW structure
337 *
338 * A wrapper to release access rights to the correct PHY. This is a
339 * function pointer entry point called by the api module.
340 **/
341 static void igb_release_phy_82575(struct e1000_hw *hw)
342 {
343 u16 mask = E1000_SWFW_PHY0_SM;
344
345 if (hw->bus.func == E1000_FUNC_1)
346 mask = E1000_SWFW_PHY1_SM;
347 else if (hw->bus.func == E1000_FUNC_2)
348 mask = E1000_SWFW_PHY2_SM;
349 else if (hw->bus.func == E1000_FUNC_3)
350 mask = E1000_SWFW_PHY3_SM;
351
352 igb_release_swfw_sync_82575(hw, mask);
353 }
354
355 /**
356 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
357 * @hw: pointer to the HW structure
358 * @offset: register offset to be read
359 * @data: pointer to the read data
360 *
361 * Reads the PHY register at offset using the serial gigabit media independent
362 * interface and stores the retrieved information in data.
363 **/
364 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
365 u16 *data)
366 {
367 s32 ret_val = -E1000_ERR_PARAM;
368
369 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
370 hw_dbg("PHY Address %u is out of range\n", offset);
371 goto out;
372 }
373
374 ret_val = hw->phy.ops.acquire(hw);
375 if (ret_val)
376 goto out;
377
378 ret_val = igb_read_phy_reg_i2c(hw, offset, data);
379
380 hw->phy.ops.release(hw);
381
382 out:
383 return ret_val;
384 }
385
386 /**
387 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
388 * @hw: pointer to the HW structure
389 * @offset: register offset to write to
390 * @data: data to write at register offset
391 *
392 * Writes the data to PHY register at the offset using the serial gigabit
393 * media independent interface.
394 **/
395 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
396 u16 data)
397 {
398 s32 ret_val = -E1000_ERR_PARAM;
399
400
401 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
402 hw_dbg("PHY Address %d is out of range\n", offset);
403 goto out;
404 }
405
406 ret_val = hw->phy.ops.acquire(hw);
407 if (ret_val)
408 goto out;
409
410 ret_val = igb_write_phy_reg_i2c(hw, offset, data);
411
412 hw->phy.ops.release(hw);
413
414 out:
415 return ret_val;
416 }
417
418 /**
419 * igb_get_phy_id_82575 - Retrieve PHY addr and id
420 * @hw: pointer to the HW structure
421 *
422 * Retrieves the PHY address and ID for both PHY's which do and do not use
423 * sgmi interface.
424 **/
425 static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
426 {
427 struct e1000_phy_info *phy = &hw->phy;
428 s32 ret_val = 0;
429 u16 phy_id;
430 u32 ctrl_ext;
431 u32 mdic;
432
433 /*
434 * For SGMII PHYs, we try the list of possible addresses until
435 * we find one that works. For non-SGMII PHYs
436 * (e.g. integrated copper PHYs), an address of 1 should
437 * work. The result of this function should mean phy->phy_addr
438 * and phy->id are set correctly.
439 */
440 if (!(igb_sgmii_active_82575(hw))) {
441 phy->addr = 1;
442 ret_val = igb_get_phy_id(hw);
443 goto out;
444 }
445
446 if (igb_sgmii_uses_mdio_82575(hw)) {
447 switch (hw->mac.type) {
448 case e1000_82575:
449 case e1000_82576:
450 mdic = rd32(E1000_MDIC);
451 mdic &= E1000_MDIC_PHY_MASK;
452 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
453 break;
454 case e1000_82580:
455 case e1000_i350:
456 mdic = rd32(E1000_MDICNFG);
457 mdic &= E1000_MDICNFG_PHY_MASK;
458 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
459 break;
460 default:
461 ret_val = -E1000_ERR_PHY;
462 goto out;
463 break;
464 }
465 ret_val = igb_get_phy_id(hw);
466 goto out;
467 }
468
469 /* Power on sgmii phy if it is disabled */
470 ctrl_ext = rd32(E1000_CTRL_EXT);
471 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
472 wrfl();
473 msleep(300);
474
475 /*
476 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
477 * Therefore, we need to test 1-7
478 */
479 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
480 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
481 if (ret_val == 0) {
482 hw_dbg("Vendor ID 0x%08X read at address %u\n",
483 phy_id, phy->addr);
484 /*
485 * At the time of this writing, The M88 part is
486 * the only supported SGMII PHY product.
487 */
488 if (phy_id == M88_VENDOR)
489 break;
490 } else {
491 hw_dbg("PHY address %u was unreadable\n", phy->addr);
492 }
493 }
494
495 /* A valid PHY type couldn't be found. */
496 if (phy->addr == 8) {
497 phy->addr = 0;
498 ret_val = -E1000_ERR_PHY;
499 goto out;
500 } else {
501 ret_val = igb_get_phy_id(hw);
502 }
503
504 /* restore previous sfp cage power state */
505 wr32(E1000_CTRL_EXT, ctrl_ext);
506
507 out:
508 return ret_val;
509 }
510
511 /**
512 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
513 * @hw: pointer to the HW structure
514 *
515 * Resets the PHY using the serial gigabit media independent interface.
516 **/
517 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
518 {
519 s32 ret_val;
520
521 /*
522 * This isn't a true "hard" reset, but is the only reset
523 * available to us at this time.
524 */
525
526 hw_dbg("Soft resetting SGMII attached PHY...\n");
527
528 /*
529 * SFP documentation requires the following to configure the SPF module
530 * to work on SGMII. No further documentation is given.
531 */
532 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
533 if (ret_val)
534 goto out;
535
536 ret_val = igb_phy_sw_reset(hw);
537
538 out:
539 return ret_val;
540 }
541
542 /**
543 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
544 * @hw: pointer to the HW structure
545 * @active: true to enable LPLU, false to disable
546 *
547 * Sets the LPLU D0 state according to the active flag. When
548 * activating LPLU this function also disables smart speed
549 * and vice versa. LPLU will not be activated unless the
550 * device autonegotiation advertisement meets standards of
551 * either 10 or 10/100 or 10/100/1000 at all duplexes.
552 * This is a function pointer entry point only called by
553 * PHY setup routines.
554 **/
555 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
556 {
557 struct e1000_phy_info *phy = &hw->phy;
558 s32 ret_val;
559 u16 data;
560
561 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
562 if (ret_val)
563 goto out;
564
565 if (active) {
566 data |= IGP02E1000_PM_D0_LPLU;
567 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
568 data);
569 if (ret_val)
570 goto out;
571
572 /* When LPLU is enabled, we should disable SmartSpeed */
573 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
574 &data);
575 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
576 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
577 data);
578 if (ret_val)
579 goto out;
580 } else {
581 data &= ~IGP02E1000_PM_D0_LPLU;
582 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
583 data);
584 /*
585 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
586 * during Dx states where the power conservation is most
587 * important. During driver activity we should enable
588 * SmartSpeed, so performance is maintained.
589 */
590 if (phy->smart_speed == e1000_smart_speed_on) {
591 ret_val = phy->ops.read_reg(hw,
592 IGP01E1000_PHY_PORT_CONFIG, &data);
593 if (ret_val)
594 goto out;
595
596 data |= IGP01E1000_PSCFR_SMART_SPEED;
597 ret_val = phy->ops.write_reg(hw,
598 IGP01E1000_PHY_PORT_CONFIG, data);
599 if (ret_val)
600 goto out;
601 } else if (phy->smart_speed == e1000_smart_speed_off) {
602 ret_val = phy->ops.read_reg(hw,
603 IGP01E1000_PHY_PORT_CONFIG, &data);
604 if (ret_val)
605 goto out;
606
607 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
608 ret_val = phy->ops.write_reg(hw,
609 IGP01E1000_PHY_PORT_CONFIG, data);
610 if (ret_val)
611 goto out;
612 }
613 }
614
615 out:
616 return ret_val;
617 }
618
619 /**
620 * igb_acquire_nvm_82575 - Request for access to EEPROM
621 * @hw: pointer to the HW structure
622 *
623 * Acquire the necessary semaphores for exclusive access to the EEPROM.
624 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
625 * Return successful if access grant bit set, else clear the request for
626 * EEPROM access and return -E1000_ERR_NVM (-1).
627 **/
628 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
629 {
630 s32 ret_val;
631
632 ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
633 if (ret_val)
634 goto out;
635
636 ret_val = igb_acquire_nvm(hw);
637
638 if (ret_val)
639 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
640
641 out:
642 return ret_val;
643 }
644
645 /**
646 * igb_release_nvm_82575 - Release exclusive access to EEPROM
647 * @hw: pointer to the HW structure
648 *
649 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
650 * then release the semaphores acquired.
651 **/
652 static void igb_release_nvm_82575(struct e1000_hw *hw)
653 {
654 igb_release_nvm(hw);
655 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
656 }
657
658 /**
659 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
660 * @hw: pointer to the HW structure
661 * @mask: specifies which semaphore to acquire
662 *
663 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
664 * will also specify which port we're acquiring the lock for.
665 **/
666 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
667 {
668 u32 swfw_sync;
669 u32 swmask = mask;
670 u32 fwmask = mask << 16;
671 s32 ret_val = 0;
672 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
673
674 while (i < timeout) {
675 if (igb_get_hw_semaphore(hw)) {
676 ret_val = -E1000_ERR_SWFW_SYNC;
677 goto out;
678 }
679
680 swfw_sync = rd32(E1000_SW_FW_SYNC);
681 if (!(swfw_sync & (fwmask | swmask)))
682 break;
683
684 /*
685 * Firmware currently using resource (fwmask)
686 * or other software thread using resource (swmask)
687 */
688 igb_put_hw_semaphore(hw);
689 mdelay(5);
690 i++;
691 }
692
693 if (i == timeout) {
694 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
695 ret_val = -E1000_ERR_SWFW_SYNC;
696 goto out;
697 }
698
699 swfw_sync |= swmask;
700 wr32(E1000_SW_FW_SYNC, swfw_sync);
701
702 igb_put_hw_semaphore(hw);
703
704 out:
705 return ret_val;
706 }
707
708 /**
709 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
710 * @hw: pointer to the HW structure
711 * @mask: specifies which semaphore to acquire
712 *
713 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
714 * will also specify which port we're releasing the lock for.
715 **/
716 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
717 {
718 u32 swfw_sync;
719
720 while (igb_get_hw_semaphore(hw) != 0);
721 /* Empty */
722
723 swfw_sync = rd32(E1000_SW_FW_SYNC);
724 swfw_sync &= ~mask;
725 wr32(E1000_SW_FW_SYNC, swfw_sync);
726
727 igb_put_hw_semaphore(hw);
728 }
729
730 /**
731 * igb_get_cfg_done_82575 - Read config done bit
732 * @hw: pointer to the HW structure
733 *
734 * Read the management control register for the config done bit for
735 * completion status. NOTE: silicon which is EEPROM-less will fail trying
736 * to read the config done bit, so an error is *ONLY* logged and returns
737 * 0. If we were to return with error, EEPROM-less silicon
738 * would not be able to be reset or change link.
739 **/
740 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
741 {
742 s32 timeout = PHY_CFG_TIMEOUT;
743 s32 ret_val = 0;
744 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
745
746 if (hw->bus.func == 1)
747 mask = E1000_NVM_CFG_DONE_PORT_1;
748 else if (hw->bus.func == E1000_FUNC_2)
749 mask = E1000_NVM_CFG_DONE_PORT_2;
750 else if (hw->bus.func == E1000_FUNC_3)
751 mask = E1000_NVM_CFG_DONE_PORT_3;
752
753 while (timeout) {
754 if (rd32(E1000_EEMNGCTL) & mask)
755 break;
756 msleep(1);
757 timeout--;
758 }
759 if (!timeout)
760 hw_dbg("MNG configuration cycle has not completed.\n");
761
762 /* If EEPROM is not marked present, init the PHY manually */
763 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
764 (hw->phy.type == e1000_phy_igp_3))
765 igb_phy_init_script_igp3(hw);
766
767 return ret_val;
768 }
769
770 /**
771 * igb_check_for_link_82575 - Check for link
772 * @hw: pointer to the HW structure
773 *
774 * If sgmii is enabled, then use the pcs register to determine link, otherwise
775 * use the generic interface for determining link.
776 **/
777 static s32 igb_check_for_link_82575(struct e1000_hw *hw)
778 {
779 s32 ret_val;
780 u16 speed, duplex;
781
782 if (hw->phy.media_type != e1000_media_type_copper) {
783 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
784 &duplex);
785 /*
786 * Use this flag to determine if link needs to be checked or
787 * not. If we have link clear the flag so that we do not
788 * continue to check for link.
789 */
790 hw->mac.get_link_status = !hw->mac.serdes_has_link;
791 } else {
792 ret_val = igb_check_for_copper_link(hw);
793 }
794
795 return ret_val;
796 }
797
798 /**
799 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
800 * @hw: pointer to the HW structure
801 **/
802 void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
803 {
804 u32 reg;
805
806
807 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
808 !igb_sgmii_active_82575(hw))
809 return;
810
811 /* Enable PCS to turn on link */
812 reg = rd32(E1000_PCS_CFG0);
813 reg |= E1000_PCS_CFG_PCS_EN;
814 wr32(E1000_PCS_CFG0, reg);
815
816 /* Power up the laser */
817 reg = rd32(E1000_CTRL_EXT);
818 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
819 wr32(E1000_CTRL_EXT, reg);
820
821 /* flush the write to verify completion */
822 wrfl();
823 msleep(1);
824 }
825
826 /**
827 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
828 * @hw: pointer to the HW structure
829 * @speed: stores the current speed
830 * @duplex: stores the current duplex
831 *
832 * Using the physical coding sub-layer (PCS), retrieve the current speed and
833 * duplex, then store the values in the pointers provided.
834 **/
835 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
836 u16 *duplex)
837 {
838 struct e1000_mac_info *mac = &hw->mac;
839 u32 pcs;
840
841 /* Set up defaults for the return values of this function */
842 mac->serdes_has_link = false;
843 *speed = 0;
844 *duplex = 0;
845
846 /*
847 * Read the PCS Status register for link state. For non-copper mode,
848 * the status register is not accurate. The PCS status register is
849 * used instead.
850 */
851 pcs = rd32(E1000_PCS_LSTAT);
852
853 /*
854 * The link up bit determines when link is up on autoneg. The sync ok
855 * gets set once both sides sync up and agree upon link. Stable link
856 * can be determined by checking for both link up and link sync ok
857 */
858 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
859 mac->serdes_has_link = true;
860
861 /* Detect and store PCS speed */
862 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
863 *speed = SPEED_1000;
864 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
865 *speed = SPEED_100;
866 } else {
867 *speed = SPEED_10;
868 }
869
870 /* Detect and store PCS duplex */
871 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
872 *duplex = FULL_DUPLEX;
873 } else {
874 *duplex = HALF_DUPLEX;
875 }
876 }
877
878 return 0;
879 }
880
881 /**
882 * igb_shutdown_serdes_link_82575 - Remove link during power down
883 * @hw: pointer to the HW structure
884 *
885 * In the case of fiber serdes, shut down optics and PCS on driver unload
886 * when management pass thru is not enabled.
887 **/
888 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
889 {
890 u32 reg;
891
892 if (hw->phy.media_type != e1000_media_type_internal_serdes &&
893 igb_sgmii_active_82575(hw))
894 return;
895
896 if (!igb_enable_mng_pass_thru(hw)) {
897 /* Disable PCS to turn off link */
898 reg = rd32(E1000_PCS_CFG0);
899 reg &= ~E1000_PCS_CFG_PCS_EN;
900 wr32(E1000_PCS_CFG0, reg);
901
902 /* shutdown the laser */
903 reg = rd32(E1000_CTRL_EXT);
904 reg |= E1000_CTRL_EXT_SDP3_DATA;
905 wr32(E1000_CTRL_EXT, reg);
906
907 /* flush the write to verify completion */
908 wrfl();
909 msleep(1);
910 }
911 }
912
913 /**
914 * igb_reset_hw_82575 - Reset hardware
915 * @hw: pointer to the HW structure
916 *
917 * This resets the hardware into a known state. This is a
918 * function pointer entry point called by the api module.
919 **/
920 static s32 igb_reset_hw_82575(struct e1000_hw *hw)
921 {
922 u32 ctrl, icr;
923 s32 ret_val;
924
925 /*
926 * Prevent the PCI-E bus from sticking if there is no TLP connection
927 * on the last TLP read/write transaction when MAC is reset.
928 */
929 ret_val = igb_disable_pcie_master(hw);
930 if (ret_val)
931 hw_dbg("PCI-E Master disable polling has failed.\n");
932
933 /* set the completion timeout for interface */
934 ret_val = igb_set_pcie_completion_timeout(hw);
935 if (ret_val) {
936 hw_dbg("PCI-E Set completion timeout has failed.\n");
937 }
938
939 hw_dbg("Masking off all interrupts\n");
940 wr32(E1000_IMC, 0xffffffff);
941
942 wr32(E1000_RCTL, 0);
943 wr32(E1000_TCTL, E1000_TCTL_PSP);
944 wrfl();
945
946 msleep(10);
947
948 ctrl = rd32(E1000_CTRL);
949
950 hw_dbg("Issuing a global reset to MAC\n");
951 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
952
953 ret_val = igb_get_auto_rd_done(hw);
954 if (ret_val) {
955 /*
956 * When auto config read does not complete, do not
957 * return with an error. This can happen in situations
958 * where there is no eeprom and prevents getting link.
959 */
960 hw_dbg("Auto Read Done did not complete\n");
961 }
962
963 /* If EEPROM is not present, run manual init scripts */
964 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
965 igb_reset_init_script_82575(hw);
966
967 /* Clear any pending interrupt events. */
968 wr32(E1000_IMC, 0xffffffff);
969 icr = rd32(E1000_ICR);
970
971 /* Install any alternate MAC address into RAR0 */
972 ret_val = igb_check_alt_mac_addr(hw);
973
974 return ret_val;
975 }
976
977 /**
978 * igb_init_hw_82575 - Initialize hardware
979 * @hw: pointer to the HW structure
980 *
981 * This inits the hardware readying it for operation.
982 **/
983 static s32 igb_init_hw_82575(struct e1000_hw *hw)
984 {
985 struct e1000_mac_info *mac = &hw->mac;
986 s32 ret_val;
987 u16 i, rar_count = mac->rar_entry_count;
988
989 /* Initialize identification LED */
990 ret_val = igb_id_led_init(hw);
991 if (ret_val) {
992 hw_dbg("Error initializing identification LED\n");
993 /* This is not fatal and we should not stop init due to this */
994 }
995
996 /* Disabling VLAN filtering */
997 hw_dbg("Initializing the IEEE VLAN\n");
998 igb_clear_vfta(hw);
999
1000 /* Setup the receive address */
1001 igb_init_rx_addrs(hw, rar_count);
1002
1003 /* Zero out the Multicast HASH table */
1004 hw_dbg("Zeroing the MTA\n");
1005 for (i = 0; i < mac->mta_reg_count; i++)
1006 array_wr32(E1000_MTA, i, 0);
1007
1008 /* Zero out the Unicast HASH table */
1009 hw_dbg("Zeroing the UTA\n");
1010 for (i = 0; i < mac->uta_reg_count; i++)
1011 array_wr32(E1000_UTA, i, 0);
1012
1013 /* Setup link and flow control */
1014 ret_val = igb_setup_link(hw);
1015
1016 /*
1017 * Clear all of the statistics registers (clear on read). It is
1018 * important that we do this after we have tried to establish link
1019 * because the symbol error count will increment wildly if there
1020 * is no link.
1021 */
1022 igb_clear_hw_cntrs_82575(hw);
1023
1024 return ret_val;
1025 }
1026
1027 /**
1028 * igb_setup_copper_link_82575 - Configure copper link settings
1029 * @hw: pointer to the HW structure
1030 *
1031 * Configures the link for auto-neg or forced speed and duplex. Then we check
1032 * for link, once link is established calls to configure collision distance
1033 * and flow control are called.
1034 **/
1035 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1036 {
1037 u32 ctrl;
1038 s32 ret_val;
1039
1040 ctrl = rd32(E1000_CTRL);
1041 ctrl |= E1000_CTRL_SLU;
1042 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1043 wr32(E1000_CTRL, ctrl);
1044
1045 ret_val = igb_setup_serdes_link_82575(hw);
1046 if (ret_val)
1047 goto out;
1048
1049 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1050 /* allow time for SFP cage time to power up phy */
1051 msleep(300);
1052
1053 ret_val = hw->phy.ops.reset(hw);
1054 if (ret_val) {
1055 hw_dbg("Error resetting the PHY.\n");
1056 goto out;
1057 }
1058 }
1059 switch (hw->phy.type) {
1060 case e1000_phy_m88:
1061 ret_val = igb_copper_link_setup_m88(hw);
1062 break;
1063 case e1000_phy_igp_3:
1064 ret_val = igb_copper_link_setup_igp(hw);
1065 break;
1066 case e1000_phy_82580:
1067 ret_val = igb_copper_link_setup_82580(hw);
1068 break;
1069 default:
1070 ret_val = -E1000_ERR_PHY;
1071 break;
1072 }
1073
1074 if (ret_val)
1075 goto out;
1076
1077 ret_val = igb_setup_copper_link(hw);
1078 out:
1079 return ret_val;
1080 }
1081
1082 /**
1083 * igb_setup_serdes_link_82575 - Setup link for serdes
1084 * @hw: pointer to the HW structure
1085 *
1086 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1087 * used on copper connections where the serialized gigabit media independent
1088 * interface (sgmii), or serdes fiber is being used. Configures the link
1089 * for auto-negotiation or forces speed/duplex.
1090 **/
1091 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
1092 {
1093 u32 ctrl_ext, ctrl_reg, reg;
1094 bool pcs_autoneg;
1095
1096 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1097 !igb_sgmii_active_82575(hw))
1098 return 0;
1099
1100 /*
1101 * On the 82575, SerDes loopback mode persists until it is
1102 * explicitly turned off or a power cycle is performed. A read to
1103 * the register does not indicate its status. Therefore, we ensure
1104 * loopback mode is disabled during initialization.
1105 */
1106 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1107
1108 /* power on the sfp cage if present */
1109 ctrl_ext = rd32(E1000_CTRL_EXT);
1110 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1111 wr32(E1000_CTRL_EXT, ctrl_ext);
1112
1113 ctrl_reg = rd32(E1000_CTRL);
1114 ctrl_reg |= E1000_CTRL_SLU;
1115
1116 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1117 /* set both sw defined pins */
1118 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1119
1120 /* Set switch control to serdes energy detect */
1121 reg = rd32(E1000_CONNSW);
1122 reg |= E1000_CONNSW_ENRGSRC;
1123 wr32(E1000_CONNSW, reg);
1124 }
1125
1126 reg = rd32(E1000_PCS_LCTL);
1127
1128 /* default pcs_autoneg to the same setting as mac autoneg */
1129 pcs_autoneg = hw->mac.autoneg;
1130
1131 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1132 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1133 /* sgmii mode lets the phy handle forcing speed/duplex */
1134 pcs_autoneg = true;
1135 /* autoneg time out should be disabled for SGMII mode */
1136 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1137 break;
1138 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1139 /* disable PCS autoneg and support parallel detect only */
1140 pcs_autoneg = false;
1141 default:
1142 /*
1143 * non-SGMII modes only supports a speed of 1000/Full for the
1144 * link so it is best to just force the MAC and let the pcs
1145 * link either autoneg or be forced to 1000/Full
1146 */
1147 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1148 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1149
1150 /* set speed of 1000/Full if speed/duplex is forced */
1151 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1152 break;
1153 }
1154
1155 wr32(E1000_CTRL, ctrl_reg);
1156
1157 /*
1158 * New SerDes mode allows for forcing speed or autonegotiating speed
1159 * at 1gb. Autoneg should be default set by most drivers. This is the
1160 * mode that will be compatible with older link partners and switches.
1161 * However, both are supported by the hardware and some drivers/tools.
1162 */
1163 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1164 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1165
1166 /*
1167 * We force flow control to prevent the CTRL register values from being
1168 * overwritten by the autonegotiated flow control values
1169 */
1170 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1171
1172 if (pcs_autoneg) {
1173 /* Set PCS register for autoneg */
1174 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1175 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1176 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1177 } else {
1178 /* Set PCS register for forced link */
1179 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1180
1181 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1182 }
1183
1184 wr32(E1000_PCS_LCTL, reg);
1185
1186 if (!igb_sgmii_active_82575(hw))
1187 igb_force_mac_fc(hw);
1188
1189 return 0;
1190 }
1191
1192 /**
1193 * igb_sgmii_active_82575 - Return sgmii state
1194 * @hw: pointer to the HW structure
1195 *
1196 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1197 * which can be enabled for use in the embedded applications. Simply
1198 * return the current state of the sgmii interface.
1199 **/
1200 static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1201 {
1202 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1203 return dev_spec->sgmii_active;
1204 }
1205
1206 /**
1207 * igb_reset_init_script_82575 - Inits HW defaults after reset
1208 * @hw: pointer to the HW structure
1209 *
1210 * Inits recommended HW defaults after a reset when there is no EEPROM
1211 * detected. This is only for the 82575.
1212 **/
1213 static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1214 {
1215 if (hw->mac.type == e1000_82575) {
1216 hw_dbg("Running reset init script for 82575\n");
1217 /* SerDes configuration via SERDESCTRL */
1218 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1219 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1220 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1221 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1222
1223 /* CCM configuration via CCMCTL register */
1224 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1225 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1226
1227 /* PCIe lanes configuration */
1228 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1229 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1230 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1231 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1232
1233 /* PCIe PLL Configuration */
1234 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1235 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1236 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1237 }
1238
1239 return 0;
1240 }
1241
1242 /**
1243 * igb_read_mac_addr_82575 - Read device MAC address
1244 * @hw: pointer to the HW structure
1245 **/
1246 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1247 {
1248 s32 ret_val = 0;
1249
1250 /*
1251 * If there's an alternate MAC address place it in RAR0
1252 * so that it will override the Si installed default perm
1253 * address.
1254 */
1255 ret_val = igb_check_alt_mac_addr(hw);
1256 if (ret_val)
1257 goto out;
1258
1259 ret_val = igb_read_mac_addr(hw);
1260
1261 out:
1262 return ret_val;
1263 }
1264
1265 /**
1266 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1267 * @hw: pointer to the HW structure
1268 *
1269 * In the case of a PHY power down to save power, or to turn off link during a
1270 * driver unload, or wake on lan is not enabled, remove the link.
1271 **/
1272 void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1273 {
1274 /* If the management interface is not enabled, then power down */
1275 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1276 igb_power_down_phy_copper(hw);
1277 }
1278
1279 /**
1280 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1281 * @hw: pointer to the HW structure
1282 *
1283 * Clears the hardware counters by reading the counter registers.
1284 **/
1285 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1286 {
1287 igb_clear_hw_cntrs_base(hw);
1288
1289 rd32(E1000_PRC64);
1290 rd32(E1000_PRC127);
1291 rd32(E1000_PRC255);
1292 rd32(E1000_PRC511);
1293 rd32(E1000_PRC1023);
1294 rd32(E1000_PRC1522);
1295 rd32(E1000_PTC64);
1296 rd32(E1000_PTC127);
1297 rd32(E1000_PTC255);
1298 rd32(E1000_PTC511);
1299 rd32(E1000_PTC1023);
1300 rd32(E1000_PTC1522);
1301
1302 rd32(E1000_ALGNERRC);
1303 rd32(E1000_RXERRC);
1304 rd32(E1000_TNCRS);
1305 rd32(E1000_CEXTERR);
1306 rd32(E1000_TSCTC);
1307 rd32(E1000_TSCTFC);
1308
1309 rd32(E1000_MGTPRC);
1310 rd32(E1000_MGTPDC);
1311 rd32(E1000_MGTPTC);
1312
1313 rd32(E1000_IAC);
1314 rd32(E1000_ICRXOC);
1315
1316 rd32(E1000_ICRXPTC);
1317 rd32(E1000_ICRXATC);
1318 rd32(E1000_ICTXPTC);
1319 rd32(E1000_ICTXATC);
1320 rd32(E1000_ICTXQEC);
1321 rd32(E1000_ICTXQMTC);
1322 rd32(E1000_ICRXDMTC);
1323
1324 rd32(E1000_CBTMPC);
1325 rd32(E1000_HTDPMC);
1326 rd32(E1000_CBRMPC);
1327 rd32(E1000_RPTHC);
1328 rd32(E1000_HGPTC);
1329 rd32(E1000_HTCBDPC);
1330 rd32(E1000_HGORCL);
1331 rd32(E1000_HGORCH);
1332 rd32(E1000_HGOTCL);
1333 rd32(E1000_HGOTCH);
1334 rd32(E1000_LENERRS);
1335
1336 /* This register should not be read in copper configurations */
1337 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1338 igb_sgmii_active_82575(hw))
1339 rd32(E1000_SCVPC);
1340 }
1341
1342 /**
1343 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1344 * @hw: pointer to the HW structure
1345 *
1346 * After rx enable if managability is enabled then there is likely some
1347 * bad data at the start of the fifo and possibly in the DMA fifo. This
1348 * function clears the fifos and flushes any packets that came in as rx was
1349 * being enabled.
1350 **/
1351 void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1352 {
1353 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1354 int i, ms_wait;
1355
1356 if (hw->mac.type != e1000_82575 ||
1357 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1358 return;
1359
1360 /* Disable all RX queues */
1361 for (i = 0; i < 4; i++) {
1362 rxdctl[i] = rd32(E1000_RXDCTL(i));
1363 wr32(E1000_RXDCTL(i),
1364 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1365 }
1366 /* Poll all queues to verify they have shut down */
1367 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1368 msleep(1);
1369 rx_enabled = 0;
1370 for (i = 0; i < 4; i++)
1371 rx_enabled |= rd32(E1000_RXDCTL(i));
1372 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1373 break;
1374 }
1375
1376 if (ms_wait == 10)
1377 hw_dbg("Queue disable timed out after 10ms\n");
1378
1379 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1380 * incoming packets are rejected. Set enable and wait 2ms so that
1381 * any packet that was coming in as RCTL.EN was set is flushed
1382 */
1383 rfctl = rd32(E1000_RFCTL);
1384 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1385
1386 rlpml = rd32(E1000_RLPML);
1387 wr32(E1000_RLPML, 0);
1388
1389 rctl = rd32(E1000_RCTL);
1390 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1391 temp_rctl |= E1000_RCTL_LPE;
1392
1393 wr32(E1000_RCTL, temp_rctl);
1394 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1395 wrfl();
1396 msleep(2);
1397
1398 /* Enable RX queues that were previously enabled and restore our
1399 * previous state
1400 */
1401 for (i = 0; i < 4; i++)
1402 wr32(E1000_RXDCTL(i), rxdctl[i]);
1403 wr32(E1000_RCTL, rctl);
1404 wrfl();
1405
1406 wr32(E1000_RLPML, rlpml);
1407 wr32(E1000_RFCTL, rfctl);
1408
1409 /* Flush receive errors generated by workaround */
1410 rd32(E1000_ROC);
1411 rd32(E1000_RNBC);
1412 rd32(E1000_MPC);
1413 }
1414
1415 /**
1416 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1417 * @hw: pointer to the HW structure
1418 *
1419 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1420 * however the hardware default for these parts is 500us to 1ms which is less
1421 * than the 10ms recommended by the pci-e spec. To address this we need to
1422 * increase the value to either 10ms to 200ms for capability version 1 config,
1423 * or 16ms to 55ms for version 2.
1424 **/
1425 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1426 {
1427 u32 gcr = rd32(E1000_GCR);
1428 s32 ret_val = 0;
1429 u16 pcie_devctl2;
1430
1431 /* only take action if timeout value is defaulted to 0 */
1432 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1433 goto out;
1434
1435 /*
1436 * if capababilities version is type 1 we can write the
1437 * timeout of 10ms to 200ms through the GCR register
1438 */
1439 if (!(gcr & E1000_GCR_CAP_VER2)) {
1440 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
1441 goto out;
1442 }
1443
1444 /*
1445 * for version 2 capabilities we need to write the config space
1446 * directly in order to set the completion timeout value for
1447 * 16ms to 55ms
1448 */
1449 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1450 &pcie_devctl2);
1451 if (ret_val)
1452 goto out;
1453
1454 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
1455
1456 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1457 &pcie_devctl2);
1458 out:
1459 /* disable completion timeout resend */
1460 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
1461
1462 wr32(E1000_GCR, gcr);
1463 return ret_val;
1464 }
1465
1466 /**
1467 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
1468 * @hw: pointer to the hardware struct
1469 * @enable: state to enter, either enabled or disabled
1470 *
1471 * enables/disables L2 switch loopback functionality.
1472 **/
1473 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
1474 {
1475 u32 dtxswc = rd32(E1000_DTXSWC);
1476
1477 if (enable)
1478 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1479 else
1480 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1481
1482 wr32(E1000_DTXSWC, dtxswc);
1483 }
1484
1485 /**
1486 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
1487 * @hw: pointer to the hardware struct
1488 * @enable: state to enter, either enabled or disabled
1489 *
1490 * enables/disables replication of packets across multiple pools.
1491 **/
1492 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
1493 {
1494 u32 vt_ctl = rd32(E1000_VT_CTL);
1495
1496 if (enable)
1497 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
1498 else
1499 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
1500
1501 wr32(E1000_VT_CTL, vt_ctl);
1502 }
1503
1504 /**
1505 * igb_read_phy_reg_82580 - Read 82580 MDI control register
1506 * @hw: pointer to the HW structure
1507 * @offset: register offset to be read
1508 * @data: pointer to the read data
1509 *
1510 * Reads the MDI control register in the PHY at offset and stores the
1511 * information read to data.
1512 **/
1513 static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
1514 {
1515 s32 ret_val;
1516
1517
1518 ret_val = hw->phy.ops.acquire(hw);
1519 if (ret_val)
1520 goto out;
1521
1522 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
1523
1524 hw->phy.ops.release(hw);
1525
1526 out:
1527 return ret_val;
1528 }
1529
1530 /**
1531 * igb_write_phy_reg_82580 - Write 82580 MDI control register
1532 * @hw: pointer to the HW structure
1533 * @offset: register offset to write to
1534 * @data: data to write to register at offset
1535 *
1536 * Writes data to MDI control register in the PHY at offset.
1537 **/
1538 static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
1539 {
1540 s32 ret_val;
1541
1542
1543 ret_val = hw->phy.ops.acquire(hw);
1544 if (ret_val)
1545 goto out;
1546
1547 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
1548
1549 hw->phy.ops.release(hw);
1550
1551 out:
1552 return ret_val;
1553 }
1554
1555 /**
1556 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
1557 * @hw: pointer to the HW structure
1558 *
1559 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
1560 * the values found in the EEPROM. This addresses an issue in which these
1561 * bits are not restored from EEPROM after reset.
1562 **/
1563 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
1564 {
1565 s32 ret_val = 0;
1566 u32 mdicnfg;
1567 u16 nvm_data;
1568
1569 if (hw->mac.type != e1000_82580)
1570 goto out;
1571 if (!igb_sgmii_active_82575(hw))
1572 goto out;
1573
1574 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
1575 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
1576 &nvm_data);
1577 if (ret_val) {
1578 hw_dbg("NVM Read Error\n");
1579 goto out;
1580 }
1581
1582 mdicnfg = rd32(E1000_MDICNFG);
1583 if (nvm_data & NVM_WORD24_EXT_MDIO)
1584 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
1585 if (nvm_data & NVM_WORD24_COM_MDIO)
1586 mdicnfg |= E1000_MDICNFG_COM_MDIO;
1587 wr32(E1000_MDICNFG, mdicnfg);
1588 out:
1589 return ret_val;
1590 }
1591
1592 /**
1593 * igb_reset_hw_82580 - Reset hardware
1594 * @hw: pointer to the HW structure
1595 *
1596 * This resets function or entire device (all ports, etc.)
1597 * to a known state.
1598 **/
1599 static s32 igb_reset_hw_82580(struct e1000_hw *hw)
1600 {
1601 s32 ret_val = 0;
1602 /* BH SW mailbox bit in SW_FW_SYNC */
1603 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
1604 u32 ctrl, icr;
1605 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
1606
1607
1608 hw->dev_spec._82575.global_device_reset = false;
1609
1610 /* Get current control state. */
1611 ctrl = rd32(E1000_CTRL);
1612
1613 /*
1614 * Prevent the PCI-E bus from sticking if there is no TLP connection
1615 * on the last TLP read/write transaction when MAC is reset.
1616 */
1617 ret_val = igb_disable_pcie_master(hw);
1618 if (ret_val)
1619 hw_dbg("PCI-E Master disable polling has failed.\n");
1620
1621 hw_dbg("Masking off all interrupts\n");
1622 wr32(E1000_IMC, 0xffffffff);
1623 wr32(E1000_RCTL, 0);
1624 wr32(E1000_TCTL, E1000_TCTL_PSP);
1625 wrfl();
1626
1627 msleep(10);
1628
1629 /* Determine whether or not a global dev reset is requested */
1630 if (global_device_reset &&
1631 igb_acquire_swfw_sync_82575(hw, swmbsw_mask))
1632 global_device_reset = false;
1633
1634 if (global_device_reset &&
1635 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
1636 ctrl |= E1000_CTRL_DEV_RST;
1637 else
1638 ctrl |= E1000_CTRL_RST;
1639
1640 wr32(E1000_CTRL, ctrl);
1641
1642 /* Add delay to insure DEV_RST has time to complete */
1643 if (global_device_reset)
1644 msleep(5);
1645
1646 ret_val = igb_get_auto_rd_done(hw);
1647 if (ret_val) {
1648 /*
1649 * When auto config read does not complete, do not
1650 * return with an error. This can happen in situations
1651 * where there is no eeprom and prevents getting link.
1652 */
1653 hw_dbg("Auto Read Done did not complete\n");
1654 }
1655
1656 /* If EEPROM is not present, run manual init scripts */
1657 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1658 igb_reset_init_script_82575(hw);
1659
1660 /* clear global device reset status bit */
1661 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
1662
1663 /* Clear any pending interrupt events. */
1664 wr32(E1000_IMC, 0xffffffff);
1665 icr = rd32(E1000_ICR);
1666
1667 ret_val = igb_reset_mdicnfg_82580(hw);
1668 if (ret_val)
1669 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
1670
1671 /* Install any alternate MAC address into RAR0 */
1672 ret_val = igb_check_alt_mac_addr(hw);
1673
1674 /* Release semaphore */
1675 if (global_device_reset)
1676 igb_release_swfw_sync_82575(hw, swmbsw_mask);
1677
1678 return ret_val;
1679 }
1680
1681 /**
1682 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
1683 * @data: data received by reading RXPBS register
1684 *
1685 * The 82580 uses a table based approach for packet buffer allocation sizes.
1686 * This function converts the retrieved value into the correct table value
1687 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
1688 * 0x0 36 72 144 1 2 4 8 16
1689 * 0x8 35 70 140 rsv rsv rsv rsv rsv
1690 */
1691 u16 igb_rxpbs_adjust_82580(u32 data)
1692 {
1693 u16 ret_val = 0;
1694
1695 if (data < E1000_82580_RXPBS_TABLE_SIZE)
1696 ret_val = e1000_82580_rxpbs_table[data];
1697
1698 return ret_val;
1699 }
1700
1701 static struct e1000_mac_operations e1000_mac_ops_82575 = {
1702 .init_hw = igb_init_hw_82575,
1703 .check_for_link = igb_check_for_link_82575,
1704 .rar_set = igb_rar_set,
1705 .read_mac_addr = igb_read_mac_addr_82575,
1706 .get_speed_and_duplex = igb_get_speed_and_duplex_copper,
1707 };
1708
1709 static struct e1000_phy_operations e1000_phy_ops_82575 = {
1710 .acquire = igb_acquire_phy_82575,
1711 .get_cfg_done = igb_get_cfg_done_82575,
1712 .release = igb_release_phy_82575,
1713 };
1714
1715 static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
1716 .acquire = igb_acquire_nvm_82575,
1717 .read = igb_read_nvm_eerd,
1718 .release = igb_release_nvm_82575,
1719 .write = igb_write_nvm_spi,
1720 };
1721
1722 const struct e1000_info e1000_82575_info = {
1723 .get_invariants = igb_get_invariants_82575,
1724 .mac_ops = &e1000_mac_ops_82575,
1725 .phy_ops = &e1000_phy_ops_82575,
1726 .nvm_ops = &e1000_nvm_ops_82575,
1727 };
1728
Linux kernel - Deliverables
This page took 0.064106 seconds and 6 git commands to generate.