drivers/net/igb/e1000_82575.h

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #ifndef _E1000_82575_H_
  29 #define _E1000_82575_H_
  30
  31 extern void igb_shutdown_serdes_link_82575(struct e1000_hw *hw);
  32 extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw);
  33
  34 #define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \
  35                                      (ID_LED_DEF1_DEF2 <<  8) | \
  36                                      (ID_LED_DEF1_DEF2 <<  4) | \
  37                                      (ID_LED_OFF1_ON2))
  38
  39 #define E1000_RAR_ENTRIES_82575   16
  40 #define E1000_RAR_ENTRIES_82576   24
  41
  42 /* SRRCTL bit definitions */
  43 #define E1000_SRRCTL_BSIZEPKT_SHIFT                     10 /* Shift _right_ */
  44 #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT                 2  /* Shift _left_ */
  45 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF                0x02000000
  46 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS          0x0A000000
  47 #define E1000_SRRCTL_DROP_EN                            0x80000000
  48
  49 #define E1000_MRQC_ENABLE_RSS_4Q            0x00000002
  50 #define E1000_MRQC_ENABLE_VMDQ              0x00000003
  51 #define E1000_MRQC_ENABLE_VMDQ_RSS_2Q       0x00000005
  52 #define E1000_MRQC_RSS_FIELD_IPV4_UDP       0x00400000
  53 #define E1000_MRQC_RSS_FIELD_IPV6_UDP       0x00800000
  54 #define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX    0x01000000
  55
  56 #define E1000_EICR_TX_QUEUE ( \
  57     E1000_EICR_TX_QUEUE0 |    \
  58     E1000_EICR_TX_QUEUE1 |    \
  59     E1000_EICR_TX_QUEUE2 |    \
  60     E1000_EICR_TX_QUEUE3)
  61
  62 #define E1000_EICR_RX_QUEUE ( \
  63     E1000_EICR_RX_QUEUE0 |    \
  64     E1000_EICR_RX_QUEUE1 |    \
  65     E1000_EICR_RX_QUEUE2 |    \
  66     E1000_EICR_RX_QUEUE3)
  67
  68 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
  69 #define E1000_IMIREXT_SIZE_BP     0x00001000  /* Packet size bypass */
  70 #define E1000_IMIREXT_CTRL_BP     0x00080000  /* Bypass check of ctrl bits */
  71
  72 /* Receive Descriptor - Advanced */
  73 union e1000_adv_rx_desc {
  74         struct {
  75                 __le64 pkt_addr;             /* Packet buffer address */
  76                 __le64 hdr_addr;             /* Header buffer address */
  77         } read;
  78         struct {
  79                 struct {
  80                         struct {
  81                                 __le16 pkt_info;   /* RSS type, Packet type */
  82                                 __le16 hdr_info;   /* Split Header,
  83                                                     * header buffer length */
  84                         } lo_dword;
  85                         union {
  86                                 __le32 rss;          /* RSS Hash */
  87                                 struct {
  88                                         __le16 ip_id;    /* IP id */
  89                                         __le16 csum;     /* Packet Checksum */
  90                                 } csum_ip;
  91                         } hi_dword;
  92                 } lower;
  93                 struct {
  94                         __le32 status_error;     /* ext status/error */
  95                         __le16 length;           /* Packet length */
  96                         __le16 vlan;             /* VLAN tag */
  97                 } upper;
  98         } wb;  /* writeback */
  99 };
 100
 101 #define E1000_RXDADV_HDRBUFLEN_MASK      0x7FE0
 102 #define E1000_RXDADV_HDRBUFLEN_SHIFT     5
 103 #define E1000_RXDADV_STAT_TS             0x10000 /* Pkt was time stamped */
 104
 105 /* Transmit Descriptor - Advanced */
 106 union e1000_adv_tx_desc {
 107         struct {
 108                 __le64 buffer_addr;    /* Address of descriptor's data buf */
 109                 __le32 cmd_type_len;
 110                 __le32 olinfo_status;
 111         } read;
 112         struct {
 113                 __le64 rsvd;       /* Reserved */
 114                 __le32 nxtseq_seed;
 115                 __le32 status;
 116         } wb;
 117 };
 118
 119 /* Adv Transmit Descriptor Config Masks */
 120 #define E1000_ADVTXD_MAC_TSTAMP   0x00080000 /* IEEE1588 Timestamp packet */
 121 #define E1000_ADVTXD_DTYP_CTXT    0x00200000 /* Advanced Context Descriptor */
 122 #define E1000_ADVTXD_DTYP_DATA    0x00300000 /* Advanced Data Descriptor */
 123 #define E1000_ADVTXD_DCMD_IFCS    0x02000000 /* Insert FCS (Ethernet CRC) */
 124 #define E1000_ADVTXD_DCMD_DEXT    0x20000000 /* Descriptor extension (1=Adv) */
 125 #define E1000_ADVTXD_DCMD_VLE     0x40000000 /* VLAN pkt enable */
 126 #define E1000_ADVTXD_DCMD_TSE     0x80000000 /* TCP Seg enable */
 127 #define E1000_ADVTXD_PAYLEN_SHIFT    14 /* Adv desc PAYLEN shift */
 128
 129 /* Context descriptors */
 130 struct e1000_adv_tx_context_desc {
 131         __le32 vlan_macip_lens;
 132         __le32 seqnum_seed;
 133         __le32 type_tucmd_mlhl;
 134         __le32 mss_l4len_idx;
 135 };
 136
 137 #define E1000_ADVTXD_MACLEN_SHIFT    9  /* Adv ctxt desc mac len shift */
 138 #define E1000_ADVTXD_TUCMD_IPV4    0x00000400  /* IP Packet Type: 1=IPv4 */
 139 #define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800  /* L4 Packet TYPE of TCP */
 140 #define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 packet TYPE of SCTP */
 141 /* IPSec Encrypt Enable for ESP */
 142 #define E1000_ADVTXD_L4LEN_SHIFT     8  /* Adv ctxt L4LEN shift */
 143 #define E1000_ADVTXD_MSS_SHIFT      16  /* Adv ctxt MSS shift */
 144 /* Adv ctxt IPSec SA IDX mask */
 145 /* Adv ctxt IPSec ESP len mask */
 146
 147 /* Additional Transmit Descriptor Control definitions */
 148 #define E1000_TXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Tx Queue */
 149 /* Tx Queue Arbitration Priority 0=low, 1=high */
 150
 151 /* Additional Receive Descriptor Control definitions */
 152 #define E1000_RXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Rx Queue */
 153
 154 /* Direct Cache Access (DCA) definitions */
 155 #define E1000_DCA_CTRL_DCA_MODE_DISABLE 0x01 /* DCA Disable */
 156 #define E1000_DCA_CTRL_DCA_MODE_CB2     0x02 /* DCA Mode CB2 */
 157
 158 #define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
 159 #define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
 160 #define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
 161 #define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
 162
 163 #define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
 164 #define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
 165 #define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
 166
 167 /* Additional DCA related definitions, note change in position of CPUID */
 168 #define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
 169 #define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
 170 #define E1000_DCA_TXCTRL_CPUID_SHIFT 24 /* Tx CPUID now in the last byte */
 171 #define E1000_DCA_RXCTRL_CPUID_SHIFT 24 /* Rx CPUID now in the last byte */
 172
 173 /* ETQF register bit definitions */
 174 #define E1000_ETQF_FILTER_ENABLE   (1 << 26)
 175 #define E1000_ETQF_1588            (1 << 30)
 176
 177 /* FTQF register bit definitions */
 178 #define E1000_FTQF_VF_BP               0x00008000
 179 #define E1000_FTQF_1588_TIME_STAMP     0x08000000
 180 #define E1000_FTQF_MASK                0xF0000000
 181 #define E1000_FTQF_MASK_PROTO_BP       0x10000000
 182 #define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000
 183
 184 #define E1000_NVM_APME_82575          0x0400
 185 #define MAX_NUM_VFS                   8
 186
 187 #define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31)  /* global VF LB enable */
 188
 189 /* Easy defines for setting default pool, would normally be left a zero */
 190 #define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7
 191 #define E1000_VT_CTL_DEFAULT_POOL_MASK  (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)
 192
 193 /* Other useful VMD_CTL register defines */
 194 #define E1000_VT_CTL_IGNORE_MAC         (1 << 28)
 195 #define E1000_VT_CTL_DISABLE_DEF_POOL   (1 << 29)
 196 #define E1000_VT_CTL_VM_REPL_EN         (1 << 30)
 197
 198 /* Per VM Offload register setup */
 199 #define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */
 200 #define E1000_VMOLR_LPE        0x00010000 /* Accept Long packet */
 201 #define E1000_VMOLR_RSSE       0x00020000 /* Enable RSS */
 202 #define E1000_VMOLR_AUPE       0x01000000 /* Accept untagged packets */
 203 #define E1000_VMOLR_ROMPE      0x02000000 /* Accept overflow multicast */
 204 #define E1000_VMOLR_ROPE       0x04000000 /* Accept overflow unicast */
 205 #define E1000_VMOLR_BAM        0x08000000 /* Accept Broadcast packets */
 206 #define E1000_VMOLR_MPME       0x10000000 /* Multicast promiscuous mode */
 207 #define E1000_VMOLR_STRVLAN    0x40000000 /* Vlan stripping enable */
 208 #define E1000_VMOLR_STRCRC     0x80000000 /* CRC stripping enable */
 209
 210 #define E1000_VLVF_ARRAY_SIZE     32
 211 #define E1000_VLVF_VLANID_MASK    0x00000FFF
 212 #define E1000_VLVF_POOLSEL_SHIFT  12
 213 #define E1000_VLVF_POOLSEL_MASK   (0xFF << E1000_VLVF_POOLSEL_SHIFT)
 214 #define E1000_VLVF_LVLAN          0x00100000
 215 #define E1000_VLVF_VLANID_ENABLE  0x80000000
 216
 217 #define E1000_IOVCTL 0x05BBC
 218 #define E1000_IOVCTL_REUSE_VFQ 0x00000001
 219
 220 #define E1000_RPLOLR_STRVLAN   0x40000000
 221 #define E1000_RPLOLR_STRCRC    0x80000000
 222
 223 #define E1000_DTXCTL_8023LL     0x0004
 224 #define E1000_DTXCTL_VLAN_ADDED 0x0008
 225 #define E1000_DTXCTL_OOS_ENABLE 0x0010
 226 #define E1000_DTXCTL_MDP_EN     0x0020
 227 #define E1000_DTXCTL_SPOOF_INT  0x0040
 228
 229 #define ALL_QUEUES   0xFFFF
 230
 231 void igb_vmdq_set_loopback_pf(struct e1000_hw *, bool);
 232 void igb_vmdq_set_replication_pf(struct e1000_hw *, bool);
 233
 234 #endif