drivers/net/igb/e1000_hw.h

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #ifndef _E1000_HW_H_
  29 #define _E1000_HW_H_
  30
  31 #include <linux/types.h>
  32 #include <linux/delay.h>
  33 #include <linux/io.h>
  34
  35 #include "e1000_regs.h"
  36 #include "e1000_defines.h"
  37
  38 struct e1000_hw;
  39
  40 #define E1000_DEV_ID_82576                    0x10C9
  41 #define E1000_DEV_ID_82576_FIBER              0x10E6
  42 #define E1000_DEV_ID_82576_SERDES             0x10E7
  43 #define E1000_DEV_ID_82576_QUAD_COPPER        0x10E8
  44 #define E1000_DEV_ID_82576_NS                 0x150A
  45 #define E1000_DEV_ID_82576_NS_SERDES          0x1518
  46 #define E1000_DEV_ID_82576_SERDES_QUAD        0x150D
  47 #define E1000_DEV_ID_82575EB_COPPER           0x10A7
  48 #define E1000_DEV_ID_82575EB_FIBER_SERDES     0x10A9
  49 #define E1000_DEV_ID_82575GB_QUAD_COPPER      0x10D6
  50
  51 #define E1000_REVISION_2 2
  52 #define E1000_REVISION_4 4
  53
  54 #define E1000_FUNC_0     0
  55 #define E1000_FUNC_1     1
  56
  57 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
  58
  59 enum e1000_mac_type {
  60         e1000_undefined = 0,
  61         e1000_82575,
  62         e1000_82576,
  63         e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
  64 };
  65
  66 enum e1000_media_type {
  67         e1000_media_type_unknown = 0,
  68         e1000_media_type_copper = 1,
  69         e1000_media_type_internal_serdes = 2,
  70         e1000_num_media_types
  71 };
  72
  73 enum e1000_nvm_type {
  74         e1000_nvm_unknown = 0,
  75         e1000_nvm_none,
  76         e1000_nvm_eeprom_spi,
  77         e1000_nvm_eeprom_microwire,
  78         e1000_nvm_flash_hw,
  79         e1000_nvm_flash_sw
  80 };
  81
  82 enum e1000_nvm_override {
  83         e1000_nvm_override_none = 0,
  84         e1000_nvm_override_spi_small,
  85         e1000_nvm_override_spi_large,
  86         e1000_nvm_override_microwire_small,
  87         e1000_nvm_override_microwire_large
  88 };
  89
  90 enum e1000_phy_type {
  91         e1000_phy_unknown = 0,
  92         e1000_phy_none,
  93         e1000_phy_m88,
  94         e1000_phy_igp,
  95         e1000_phy_igp_2,
  96         e1000_phy_gg82563,
  97         e1000_phy_igp_3,
  98         e1000_phy_ife,
  99 };
 100
 101 enum e1000_bus_type {
 102         e1000_bus_type_unknown = 0,
 103         e1000_bus_type_pci,
 104         e1000_bus_type_pcix,
 105         e1000_bus_type_pci_express,
 106         e1000_bus_type_reserved
 107 };
 108
 109 enum e1000_bus_speed {
 110         e1000_bus_speed_unknown = 0,
 111         e1000_bus_speed_33,
 112         e1000_bus_speed_66,
 113         e1000_bus_speed_100,
 114         e1000_bus_speed_120,
 115         e1000_bus_speed_133,
 116         e1000_bus_speed_2500,
 117         e1000_bus_speed_5000,
 118         e1000_bus_speed_reserved
 119 };
 120
 121 enum e1000_bus_width {
 122         e1000_bus_width_unknown = 0,
 123         e1000_bus_width_pcie_x1,
 124         e1000_bus_width_pcie_x2,
 125         e1000_bus_width_pcie_x4 = 4,
 126         e1000_bus_width_pcie_x8 = 8,
 127         e1000_bus_width_32,
 128         e1000_bus_width_64,
 129         e1000_bus_width_reserved
 130 };
 131
 132 enum e1000_1000t_rx_status {
 133         e1000_1000t_rx_status_not_ok = 0,
 134         e1000_1000t_rx_status_ok,
 135         e1000_1000t_rx_status_undefined = 0xFF
 136 };
 137
 138 enum e1000_rev_polarity {
 139         e1000_rev_polarity_normal = 0,
 140         e1000_rev_polarity_reversed,
 141         e1000_rev_polarity_undefined = 0xFF
 142 };
 143
 144 enum e1000_fc_mode {
 145         e1000_fc_none = 0,
 146         e1000_fc_rx_pause,
 147         e1000_fc_tx_pause,
 148         e1000_fc_full,
 149         e1000_fc_default = 0xFF
 150 };
 151
 152 /* Statistics counters collected by the MAC */
 153 struct e1000_hw_stats {
 154         u64 crcerrs;
 155         u64 algnerrc;
 156         u64 symerrs;
 157         u64 rxerrc;
 158         u64 mpc;
 159         u64 scc;
 160         u64 ecol;
 161         u64 mcc;
 162         u64 latecol;
 163         u64 colc;
 164         u64 dc;
 165         u64 tncrs;
 166         u64 sec;
 167         u64 cexterr;
 168         u64 rlec;
 169         u64 xonrxc;
 170         u64 xontxc;
 171         u64 xoffrxc;
 172         u64 xofftxc;
 173         u64 fcruc;
 174         u64 prc64;
 175         u64 prc127;
 176         u64 prc255;
 177         u64 prc511;
 178         u64 prc1023;
 179         u64 prc1522;
 180         u64 gprc;
 181         u64 bprc;
 182         u64 mprc;
 183         u64 gptc;
 184         u64 gorc;
 185         u64 gotc;
 186         u64 rnbc;
 187         u64 ruc;
 188         u64 rfc;
 189         u64 roc;
 190         u64 rjc;
 191         u64 mgprc;
 192         u64 mgpdc;
 193         u64 mgptc;
 194         u64 tor;
 195         u64 tot;
 196         u64 tpr;
 197         u64 tpt;
 198         u64 ptc64;
 199         u64 ptc127;
 200         u64 ptc255;
 201         u64 ptc511;
 202         u64 ptc1023;
 203         u64 ptc1522;
 204         u64 mptc;
 205         u64 bptc;
 206         u64 tsctc;
 207         u64 tsctfc;
 208         u64 iac;
 209         u64 icrxptc;
 210         u64 icrxatc;
 211         u64 ictxptc;
 212         u64 ictxatc;
 213         u64 ictxqec;
 214         u64 ictxqmtc;
 215         u64 icrxdmtc;
 216         u64 icrxoc;
 217         u64 cbtmpc;
 218         u64 htdpmc;
 219         u64 cbrdpc;
 220         u64 cbrmpc;
 221         u64 rpthc;
 222         u64 hgptc;
 223         u64 htcbdpc;
 224         u64 hgorc;
 225         u64 hgotc;
 226         u64 lenerrs;
 227         u64 scvpc;
 228         u64 hrmpc;
 229         u64 doosync;
 230 };
 231
 232 struct e1000_phy_stats {
 233         u32 idle_errors;
 234         u32 receive_errors;
 235 };
 236
 237 struct e1000_host_mng_dhcp_cookie {
 238         u32 signature;
 239         u8  status;
 240         u8  reserved0;
 241         u16 vlan_id;
 242         u32 reserved1;
 243         u16 reserved2;
 244         u8  reserved3;
 245         u8  checksum;
 246 };
 247
 248 /* Host Interface "Rev 1" */
 249 struct e1000_host_command_header {
 250         u8 command_id;
 251         u8 command_length;
 252         u8 command_options;
 253         u8 checksum;
 254 };
 255
 256 #define E1000_HI_MAX_DATA_LENGTH     252
 257 struct e1000_host_command_info {
 258         struct e1000_host_command_header command_header;
 259         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 260 };
 261
 262 /* Host Interface "Rev 2" */
 263 struct e1000_host_mng_command_header {
 264         u8  command_id;
 265         u8  checksum;
 266         u16 reserved1;
 267         u16 reserved2;
 268         u16 command_length;
 269 };
 270
 271 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
 272 struct e1000_host_mng_command_info {
 273         struct e1000_host_mng_command_header command_header;
 274         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 275 };
 276
 277 #include "e1000_mac.h"
 278 #include "e1000_phy.h"
 279 #include "e1000_nvm.h"
 280 #include "e1000_mbx.h"
 281
 282 struct e1000_mac_operations {
 283         s32  (*check_for_link)(struct e1000_hw *);
 284         s32  (*reset_hw)(struct e1000_hw *);
 285         s32  (*init_hw)(struct e1000_hw *);
 286         bool (*check_mng_mode)(struct e1000_hw *);
 287         s32  (*setup_physical_interface)(struct e1000_hw *);
 288         void (*rar_set)(struct e1000_hw *, u8 *, u32);
 289         s32  (*read_mac_addr)(struct e1000_hw *);
 290         s32  (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *);
 291 };
 292
 293 struct e1000_phy_operations {
 294         s32  (*acquire)(struct e1000_hw *);
 295         s32  (*check_reset_block)(struct e1000_hw *);
 296         s32  (*force_speed_duplex)(struct e1000_hw *);
 297         s32  (*get_cfg_done)(struct e1000_hw *hw);
 298         s32  (*get_cable_length)(struct e1000_hw *);
 299         s32  (*get_phy_info)(struct e1000_hw *);
 300         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 301         void (*release)(struct e1000_hw *);
 302         s32  (*reset)(struct e1000_hw *);
 303         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 304         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 305         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 306 };
 307
 308 struct e1000_nvm_operations {
 309         s32  (*acquire)(struct e1000_hw *);
 310         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 311         void (*release)(struct e1000_hw *);
 312         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 313 };
 314
 315 struct e1000_info {
 316         s32 (*get_invariants)(struct e1000_hw *);
 317         struct e1000_mac_operations *mac_ops;
 318         struct e1000_phy_operations *phy_ops;
 319         struct e1000_nvm_operations *nvm_ops;
 320 };
 321
 322 extern const struct e1000_info e1000_82575_info;
 323
 324 struct e1000_mac_info {
 325         struct e1000_mac_operations ops;
 326
 327         u8 addr[6];
 328         u8 perm_addr[6];
 329
 330         enum e1000_mac_type type;
 331
 332         u32 collision_delta;
 333         u32 ledctl_default;
 334         u32 ledctl_mode1;
 335         u32 ledctl_mode2;
 336         u32 mc_filter_type;
 337         u32 tx_packet_delta;
 338         u32 txcw;
 339
 340         u16 current_ifs_val;
 341         u16 ifs_max_val;
 342         u16 ifs_min_val;
 343         u16 ifs_ratio;
 344         u16 ifs_step_size;
 345         u16 mta_reg_count;
 346         u16 uta_reg_count;
 347
 348         /* Maximum size of the MTA register table in all supported adapters */
 349         #define MAX_MTA_REG 128
 350         u32 mta_shadow[MAX_MTA_REG];
 351         u16 rar_entry_count;
 352
 353         u8  forced_speed_duplex;
 354
 355         bool adaptive_ifs;
 356         bool arc_subsystem_valid;
 357         bool asf_firmware_present;
 358         bool autoneg;
 359         bool autoneg_failed;
 360         bool disable_hw_init_bits;
 361         bool get_link_status;
 362         bool ifs_params_forced;
 363         bool in_ifs_mode;
 364         bool report_tx_early;
 365         bool serdes_has_link;
 366         bool tx_pkt_filtering;
 367 };
 368
 369 struct e1000_phy_info {
 370         struct e1000_phy_operations ops;
 371
 372         enum e1000_phy_type type;
 373
 374         enum e1000_1000t_rx_status local_rx;
 375         enum e1000_1000t_rx_status remote_rx;
 376         enum e1000_ms_type ms_type;
 377         enum e1000_ms_type original_ms_type;
 378         enum e1000_rev_polarity cable_polarity;
 379         enum e1000_smart_speed smart_speed;
 380
 381         u32 addr;
 382         u32 id;
 383         u32 reset_delay_us; /* in usec */
 384         u32 revision;
 385
 386         enum e1000_media_type media_type;
 387
 388         u16 autoneg_advertised;
 389         u16 autoneg_mask;
 390         u16 cable_length;
 391         u16 max_cable_length;
 392         u16 min_cable_length;
 393
 394         u8 mdix;
 395
 396         bool disable_polarity_correction;
 397         bool is_mdix;
 398         bool polarity_correction;
 399         bool reset_disable;
 400         bool speed_downgraded;
 401         bool autoneg_wait_to_complete;
 402 };
 403
 404 struct e1000_nvm_info {
 405         struct e1000_nvm_operations ops;
 406
 407         enum e1000_nvm_type type;
 408         enum e1000_nvm_override override;
 409
 410         u32 flash_bank_size;
 411         u32 flash_base_addr;
 412
 413         u16 word_size;
 414         u16 delay_usec;
 415         u16 address_bits;
 416         u16 opcode_bits;
 417         u16 page_size;
 418 };
 419
 420 struct e1000_bus_info {
 421         enum e1000_bus_type type;
 422         enum e1000_bus_speed speed;
 423         enum e1000_bus_width width;
 424
 425         u32 snoop;
 426
 427         u16 func;
 428         u16 pci_cmd_word;
 429 };
 430
 431 struct e1000_fc_info {
 432         u32 high_water;     /* Flow control high-water mark */
 433         u32 low_water;      /* Flow control low-water mark */
 434         u16 pause_time;     /* Flow control pause timer */
 435         bool send_xon;      /* Flow control send XON */
 436         bool strict_ieee;   /* Strict IEEE mode */
 437         enum e1000_fc_mode current_mode; /* Type of flow control */
 438         enum e1000_fc_mode requested_mode;
 439 };
 440
 441 struct e1000_mbx_operations {
 442         s32 (*init_params)(struct e1000_hw *hw);
 443         s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
 444         s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
 445         s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
 446         s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
 447         s32 (*check_for_msg)(struct e1000_hw *, u16);
 448         s32 (*check_for_ack)(struct e1000_hw *, u16);
 449         s32 (*check_for_rst)(struct e1000_hw *, u16);
 450 };
 451
 452 struct e1000_mbx_stats {
 453         u32 msgs_tx;
 454         u32 msgs_rx;
 455
 456         u32 acks;
 457         u32 reqs;
 458         u32 rsts;
 459 };
 460
 461 struct e1000_mbx_info {
 462         struct e1000_mbx_operations ops;
 463         struct e1000_mbx_stats stats;
 464         u32 timeout;
 465         u32 usec_delay;
 466         u16 size;
 467 };
 468
 469 struct e1000_dev_spec_82575 {
 470         bool sgmii_active;
 471 };
 472
 473 struct e1000_hw {
 474         void *back;
 475
 476         u8 __iomem *hw_addr;
 477         u8 __iomem *flash_address;
 478         unsigned long io_base;
 479
 480         struct e1000_mac_info  mac;
 481         struct e1000_fc_info   fc;
 482         struct e1000_phy_info  phy;
 483         struct e1000_nvm_info  nvm;
 484         struct e1000_bus_info  bus;
 485         struct e1000_mbx_info mbx;
 486         struct e1000_host_mng_dhcp_cookie mng_cookie;
 487
 488         union {
 489                 struct e1000_dev_spec_82575     _82575;
 490         } dev_spec;
 491
 492         u16 device_id;
 493         u16 subsystem_vendor_id;
 494         u16 subsystem_device_id;
 495         u16 vendor_id;
 496
 497         u8  revision_id;
 498 };
 499
 500 #ifdef DEBUG
 501 extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
 502 #define hw_dbg(format, arg...) \
 503         printk(KERN_DEBUG "%s: " format, igb_get_hw_dev_name(hw), ##arg)
 504 #else
 505 #define hw_dbg(format, arg...)
 506 #endif
 507 #endif
 508 /* These functions must be implemented by drivers */
 509 s32  igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 510 s32  igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);