1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/if_ether.h>
29 #include <linux/delay.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
33 #include "e1000_mac.h"
37 static s32
igb_set_default_fc(struct e1000_hw
*hw
);
38 static s32
igb_set_fc_watermarks(struct e1000_hw
*hw
);
41 * igb_remove_device - Free device specific structure
42 * @hw: pointer to the HW structure
44 * If a device specific structure was allocated, this function will
47 void igb_remove_device(struct e1000_hw
*hw
)
49 /* Freeing the dev_spec member of e1000_hw structure */
53 static void igb_read_pci_cfg(struct e1000_hw
*hw
, u32 reg
, u16
*value
)
55 struct igb_adapter
*adapter
= hw
->back
;
57 pci_read_config_word(adapter
->pdev
, reg
, value
);
60 static s32
igb_read_pcie_cap_reg(struct e1000_hw
*hw
, u32 reg
, u16
*value
)
62 struct igb_adapter
*adapter
= hw
->back
;
65 cap_offset
= pci_find_capability(adapter
->pdev
, PCI_CAP_ID_EXP
);
67 return -E1000_ERR_CONFIG
;
69 pci_read_config_word(adapter
->pdev
, cap_offset
+ reg
, value
);
75 * igb_get_bus_info_pcie - Get PCIe bus information
76 * @hw: pointer to the HW structure
78 * Determines and stores the system bus information for a particular
79 * network interface. The following bus information is determined and stored:
80 * bus speed, bus width, type (PCIe), and PCIe function.
82 s32
igb_get_bus_info_pcie(struct e1000_hw
*hw
)
84 struct e1000_bus_info
*bus
= &hw
->bus
;
89 bus
->type
= e1000_bus_type_pci_express
;
90 bus
->speed
= e1000_bus_speed_2500
;
92 ret_val
= igb_read_pcie_cap_reg(hw
,
96 bus
->width
= e1000_bus_width_unknown
;
98 bus
->width
= (enum e1000_bus_width
)((pcie_link_status
&
99 PCIE_LINK_WIDTH_MASK
) >>
100 PCIE_LINK_WIDTH_SHIFT
);
102 reg
= rd32(E1000_STATUS
);
103 bus
->func
= (reg
& E1000_STATUS_FUNC_MASK
) >> E1000_STATUS_FUNC_SHIFT
;
109 * igb_clear_vfta - Clear VLAN filter table
110 * @hw: pointer to the HW structure
112 * Clears the register array which contains the VLAN filter table by
113 * setting all the values to 0.
115 void igb_clear_vfta(struct e1000_hw
*hw
)
119 for (offset
= 0; offset
< E1000_VLAN_FILTER_TBL_SIZE
; offset
++) {
120 array_wr32(E1000_VFTA
, offset
, 0);
126 * igb_write_vfta - Write value to VLAN filter table
127 * @hw: pointer to the HW structure
128 * @offset: register offset in VLAN filter table
129 * @value: register value written to VLAN filter table
131 * Writes value at the given offset in the register array which stores
132 * the VLAN filter table.
134 void igb_write_vfta(struct e1000_hw
*hw
, u32 offset
, u32 value
)
136 array_wr32(E1000_VFTA
, offset
, value
);
141 * igb_check_alt_mac_addr - Check for alternate MAC addr
142 * @hw: pointer to the HW structure
144 * Checks the nvm for an alternate MAC address. An alternate MAC address
145 * can be setup by pre-boot software and must be treated like a permanent
146 * address and must override the actual permanent MAC address. If an
147 * alternate MAC address is fopund it is saved in the hw struct and
148 * prgrammed into RAR0 and the cuntion returns success, otherwise the
149 * fucntion returns an error.
151 s32
igb_check_alt_mac_addr(struct e1000_hw
*hw
)
155 u16 offset
, nvm_alt_mac_addr_offset
, nvm_data
;
156 u8 alt_mac_addr
[ETH_ALEN
];
158 ret_val
= hw
->nvm
.ops
.read_nvm(hw
, NVM_ALT_MAC_ADDR_PTR
, 1,
159 &nvm_alt_mac_addr_offset
);
161 hw_dbg("NVM Read Error\n");
165 if (nvm_alt_mac_addr_offset
== 0xFFFF) {
166 ret_val
= -(E1000_NOT_IMPLEMENTED
);
170 if (hw
->bus
.func
== E1000_FUNC_1
)
171 nvm_alt_mac_addr_offset
+= ETH_ALEN
/sizeof(u16
);
173 for (i
= 0; i
< ETH_ALEN
; i
+= 2) {
174 offset
= nvm_alt_mac_addr_offset
+ (i
>> 1);
175 ret_val
= hw
->nvm
.ops
.read_nvm(hw
, offset
, 1, &nvm_data
);
177 hw_dbg("NVM Read Error\n");
181 alt_mac_addr
[i
] = (u8
)(nvm_data
& 0xFF);
182 alt_mac_addr
[i
+ 1] = (u8
)(nvm_data
>> 8);
185 /* if multicast bit is set, the alternate address will not be used */
186 if (alt_mac_addr
[0] & 0x01) {
187 ret_val
= -(E1000_NOT_IMPLEMENTED
);
191 for (i
= 0; i
< ETH_ALEN
; i
++)
192 hw
->mac
.addr
[i
] = hw
->mac
.perm_addr
[i
] = alt_mac_addr
[i
];
194 hw
->mac
.ops
.rar_set(hw
, hw
->mac
.perm_addr
, 0);
201 * igb_rar_set - Set receive address register
202 * @hw: pointer to the HW structure
203 * @addr: pointer to the receive address
204 * @index: receive address array register
206 * Sets the receive address array register at index to the address passed
209 void igb_rar_set(struct e1000_hw
*hw
, u8
*addr
, u32 index
)
211 u32 rar_low
, rar_high
;
214 * HW expects these in little endian so we reverse the byte order
215 * from network order (big endian) to little endian
217 rar_low
= ((u32
) addr
[0] |
218 ((u32
) addr
[1] << 8) |
219 ((u32
) addr
[2] << 16) | ((u32
) addr
[3] << 24));
221 rar_high
= ((u32
) addr
[4] | ((u32
) addr
[5] << 8));
223 if (!hw
->mac
.disable_av
)
224 rar_high
|= E1000_RAH_AV
;
226 wr32(E1000_RAL(index
), rar_low
);
227 wr32(E1000_RAH(index
), rar_high
);
231 * igb_mta_set - Set multicast filter table address
232 * @hw: pointer to the HW structure
233 * @hash_value: determines the MTA register and bit to set
235 * The multicast table address is a register array of 32-bit registers.
236 * The hash_value is used to determine what register the bit is in, the
237 * current value is read, the new bit is OR'd in and the new value is
238 * written back into the register.
240 void igb_mta_set(struct e1000_hw
*hw
, u32 hash_value
)
242 u32 hash_bit
, hash_reg
, mta
;
245 * The MTA is a register array of 32-bit registers. It is
246 * treated like an array of (32*mta_reg_count) bits. We want to
247 * set bit BitArray[hash_value]. So we figure out what register
248 * the bit is in, read it, OR in the new bit, then write
249 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a
250 * mask to bits 31:5 of the hash value which gives us the
251 * register we're modifying. The hash bit within that register
252 * is determined by the lower 5 bits of the hash value.
254 hash_reg
= (hash_value
>> 5) & (hw
->mac
.mta_reg_count
- 1);
255 hash_bit
= hash_value
& 0x1F;
257 mta
= array_rd32(E1000_MTA
, hash_reg
);
259 mta
|= (1 << hash_bit
);
261 array_wr32(E1000_MTA
, hash_reg
, mta
);
266 * igb_hash_mc_addr - Generate a multicast hash value
267 * @hw: pointer to the HW structure
268 * @mc_addr: pointer to a multicast address
270 * Generates a multicast address hash value which is used to determine
271 * the multicast filter table array address and new table value. See
274 u32
igb_hash_mc_addr(struct e1000_hw
*hw
, u8
*mc_addr
)
276 u32 hash_value
, hash_mask
;
279 /* Register count multiplied by bits per register */
280 hash_mask
= (hw
->mac
.mta_reg_count
* 32) - 1;
283 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
284 * where 0xFF would still fall within the hash mask.
286 while (hash_mask
>> bit_shift
!= 0xFF)
290 * The portion of the address that is used for the hash table
291 * is determined by the mc_filter_type setting.
292 * The algorithm is such that there is a total of 8 bits of shifting.
293 * The bit_shift for a mc_filter_type of 0 represents the number of
294 * left-shifts where the MSB of mc_addr[5] would still fall within
295 * the hash_mask. Case 0 does this exactly. Since there are a total
296 * of 8 bits of shifting, then mc_addr[4] will shift right the
297 * remaining number of bits. Thus 8 - bit_shift. The rest of the
298 * cases are a variation of this algorithm...essentially raising the
299 * number of bits to shift mc_addr[5] left, while still keeping the
300 * 8-bit shifting total.
302 * For example, given the following Destination MAC Address and an
303 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
304 * we can see that the bit_shift for case 0 is 4. These are the hash
305 * values resulting from each mc_filter_type...
306 * [0] [1] [2] [3] [4] [5]
310 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
311 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
312 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
313 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
315 switch (hw
->mac
.mc_filter_type
) {
330 hash_value
= hash_mask
& (((mc_addr
[4] >> (8 - bit_shift
)) |
331 (((u16
) mc_addr
[5]) << bit_shift
)));
337 * igb_clear_hw_cntrs_base - Clear base hardware counters
338 * @hw: pointer to the HW structure
340 * Clears the base hardware counters by reading the counter registers.
342 void igb_clear_hw_cntrs_base(struct e1000_hw
*hw
)
346 temp
= rd32(E1000_CRCERRS
);
347 temp
= rd32(E1000_SYMERRS
);
348 temp
= rd32(E1000_MPC
);
349 temp
= rd32(E1000_SCC
);
350 temp
= rd32(E1000_ECOL
);
351 temp
= rd32(E1000_MCC
);
352 temp
= rd32(E1000_LATECOL
);
353 temp
= rd32(E1000_COLC
);
354 temp
= rd32(E1000_DC
);
355 temp
= rd32(E1000_SEC
);
356 temp
= rd32(E1000_RLEC
);
357 temp
= rd32(E1000_XONRXC
);
358 temp
= rd32(E1000_XONTXC
);
359 temp
= rd32(E1000_XOFFRXC
);
360 temp
= rd32(E1000_XOFFTXC
);
361 temp
= rd32(E1000_FCRUC
);
362 temp
= rd32(E1000_GPRC
);
363 temp
= rd32(E1000_BPRC
);
364 temp
= rd32(E1000_MPRC
);
365 temp
= rd32(E1000_GPTC
);
366 temp
= rd32(E1000_GORCL
);
367 temp
= rd32(E1000_GORCH
);
368 temp
= rd32(E1000_GOTCL
);
369 temp
= rd32(E1000_GOTCH
);
370 temp
= rd32(E1000_RNBC
);
371 temp
= rd32(E1000_RUC
);
372 temp
= rd32(E1000_RFC
);
373 temp
= rd32(E1000_ROC
);
374 temp
= rd32(E1000_RJC
);
375 temp
= rd32(E1000_TORL
);
376 temp
= rd32(E1000_TORH
);
377 temp
= rd32(E1000_TOTL
);
378 temp
= rd32(E1000_TOTH
);
379 temp
= rd32(E1000_TPR
);
380 temp
= rd32(E1000_TPT
);
381 temp
= rd32(E1000_MPTC
);
382 temp
= rd32(E1000_BPTC
);
386 * igb_check_for_copper_link - Check for link (Copper)
387 * @hw: pointer to the HW structure
389 * Checks to see of the link status of the hardware has changed. If a
390 * change in link status has been detected, then we read the PHY registers
391 * to get the current speed/duplex if link exists.
393 s32
igb_check_for_copper_link(struct e1000_hw
*hw
)
395 struct e1000_mac_info
*mac
= &hw
->mac
;
400 * We only want to go out to the PHY registers to see if Auto-Neg
401 * has completed and/or if our link status has changed. The
402 * get_link_status flag is set upon receiving a Link Status
403 * Change or Rx Sequence Error interrupt.
405 if (!mac
->get_link_status
) {
411 * First we want to see if the MII Status Register reports
412 * link. If so, then we want to get the current speed/duplex
415 ret_val
= igb_phy_has_link(hw
, 1, 0, &link
);
420 goto out
; /* No link detected */
422 mac
->get_link_status
= false;
425 * Check if there was DownShift, must be checked
426 * immediately after link-up
428 igb_check_downshift(hw
);
431 * If we are forcing speed/duplex, then we simply return since
432 * we have already determined whether we have link or not.
435 ret_val
= -E1000_ERR_CONFIG
;
440 * Auto-Neg is enabled. Auto Speed Detection takes care
441 * of MAC speed/duplex configuration. So we only need to
442 * configure Collision Distance in the MAC.
444 igb_config_collision_dist(hw
);
447 * Configure Flow Control now that Auto-Neg has completed.
448 * First, we need to restore the desired flow control
449 * settings because we may have had to re-autoneg with a
450 * different link partner.
452 ret_val
= igb_config_fc_after_link_up(hw
);
454 hw_dbg("Error configuring flow control\n");
461 * igb_setup_link - Setup flow control and link settings
462 * @hw: pointer to the HW structure
464 * Determines which flow control settings to use, then configures flow
465 * control. Calls the appropriate media-specific link configuration
466 * function. Assuming the adapter has a valid link partner, a valid link
467 * should be established. Assumes the hardware has previously been reset
468 * and the transmitter and receiver are not enabled.
470 s32
igb_setup_link(struct e1000_hw
*hw
)
475 * In the case of the phy reset being blocked, we already have a link.
476 * We do not need to set it up again.
478 if (igb_check_reset_block(hw
))
481 ret_val
= igb_set_default_fc(hw
);
486 * We want to save off the original Flow Control configuration just
487 * in case we get disconnected and then reconnected into a different
488 * hub or switch with different Flow Control capabilities.
490 hw
->fc
.original_type
= hw
->fc
.type
;
492 hw_dbg("After fix-ups FlowControl is now = %x\n", hw
->fc
.type
);
494 /* Call the necessary media_type subroutine to configure the link. */
495 ret_val
= hw
->mac
.ops
.setup_physical_interface(hw
);
500 * Initialize the flow control address, type, and PAUSE timer
501 * registers to their default values. This is done even if flow
502 * control is disabled, because it does not hurt anything to
503 * initialize these registers.
505 hw_dbg("Initializing the Flow Control address, type and timer regs\n");
506 wr32(E1000_FCT
, FLOW_CONTROL_TYPE
);
507 wr32(E1000_FCAH
, FLOW_CONTROL_ADDRESS_HIGH
);
508 wr32(E1000_FCAL
, FLOW_CONTROL_ADDRESS_LOW
);
510 wr32(E1000_FCTTV
, hw
->fc
.pause_time
);
512 ret_val
= igb_set_fc_watermarks(hw
);
519 * igb_config_collision_dist - Configure collision distance
520 * @hw: pointer to the HW structure
522 * Configures the collision distance to the default value and is used
523 * during link setup. Currently no func pointer exists and all
524 * implementations are handled in the generic version of this function.
526 void igb_config_collision_dist(struct e1000_hw
*hw
)
530 tctl
= rd32(E1000_TCTL
);
532 tctl
&= ~E1000_TCTL_COLD
;
533 tctl
|= E1000_COLLISION_DISTANCE
<< E1000_COLD_SHIFT
;
535 wr32(E1000_TCTL
, tctl
);
540 * igb_set_fc_watermarks - Set flow control high/low watermarks
541 * @hw: pointer to the HW structure
543 * Sets the flow control high/low threshold (watermark) registers. If
544 * flow control XON frame transmission is enabled, then set XON frame
545 * tansmission as well.
547 static s32
igb_set_fc_watermarks(struct e1000_hw
*hw
)
550 u32 fcrtl
= 0, fcrth
= 0;
553 * Set the flow control receive threshold registers. Normally,
554 * these registers will be set to a default threshold that may be
555 * adjusted later by the driver's runtime code. However, if the
556 * ability to transmit pause frames is not enabled, then these
557 * registers will be set to 0.
559 if (hw
->fc
.type
& e1000_fc_tx_pause
) {
561 * We need to set up the Receive Threshold high and low water
562 * marks as well as (optionally) enabling the transmission of
565 fcrtl
= hw
->fc
.low_water
;
567 fcrtl
|= E1000_FCRTL_XONE
;
569 fcrth
= hw
->fc
.high_water
;
571 wr32(E1000_FCRTL
, fcrtl
);
572 wr32(E1000_FCRTH
, fcrth
);
578 * igb_set_default_fc - Set flow control default values
579 * @hw: pointer to the HW structure
581 * Read the EEPROM for the default values for flow control and store the
584 static s32
igb_set_default_fc(struct e1000_hw
*hw
)
590 * Read and store word 0x0F of the EEPROM. This word contains bits
591 * that determine the hardware's default PAUSE (flow control) mode,
592 * a bit that determines whether the HW defaults to enabling or
593 * disabling auto-negotiation, and the direction of the
594 * SW defined pins. If there is no SW over-ride of the flow
595 * control setting, then the variable hw->fc will
596 * be initialized based on a value in the EEPROM.
598 ret_val
= hw
->nvm
.ops
.read_nvm(hw
, NVM_INIT_CONTROL2_REG
, 1,
602 hw_dbg("NVM Read Error\n");
606 if ((nvm_data
& NVM_WORD0F_PAUSE_MASK
) == 0)
607 hw
->fc
.type
= e1000_fc_none
;
608 else if ((nvm_data
& NVM_WORD0F_PAUSE_MASK
) ==
610 hw
->fc
.type
= e1000_fc_tx_pause
;
612 hw
->fc
.type
= e1000_fc_full
;
619 * igb_force_mac_fc - Force the MAC's flow control settings
620 * @hw: pointer to the HW structure
622 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
623 * device control register to reflect the adapter settings. TFCE and RFCE
624 * need to be explicitly set by software when a copper PHY is used because
625 * autonegotiation is managed by the PHY rather than the MAC. Software must
626 * also configure these bits when link is forced on a fiber connection.
628 s32
igb_force_mac_fc(struct e1000_hw
*hw
)
633 ctrl
= rd32(E1000_CTRL
);
636 * Because we didn't get link via the internal auto-negotiation
637 * mechanism (we either forced link or we got link via PHY
638 * auto-neg), we have to manually enable/disable transmit an
639 * receive flow control.
641 * The "Case" statement below enables/disable flow control
642 * according to the "hw->fc.type" parameter.
644 * The possible values of the "fc" parameter are:
645 * 0: Flow control is completely disabled
646 * 1: Rx flow control is enabled (we can receive pause
647 * frames but not send pause frames).
648 * 2: Tx flow control is enabled (we can send pause frames
649 * frames but we do not receive pause frames).
650 * 3: Both Rx and TX flow control (symmetric) is enabled.
651 * other: No other values should be possible at this point.
653 hw_dbg("hw->fc.type = %u\n", hw
->fc
.type
);
655 switch (hw
->fc
.type
) {
657 ctrl
&= (~(E1000_CTRL_TFCE
| E1000_CTRL_RFCE
));
659 case e1000_fc_rx_pause
:
660 ctrl
&= (~E1000_CTRL_TFCE
);
661 ctrl
|= E1000_CTRL_RFCE
;
663 case e1000_fc_tx_pause
:
664 ctrl
&= (~E1000_CTRL_RFCE
);
665 ctrl
|= E1000_CTRL_TFCE
;
668 ctrl
|= (E1000_CTRL_TFCE
| E1000_CTRL_RFCE
);
671 hw_dbg("Flow control param set incorrectly\n");
672 ret_val
= -E1000_ERR_CONFIG
;
676 wr32(E1000_CTRL
, ctrl
);
683 * igb_config_fc_after_link_up - Configures flow control after link
684 * @hw: pointer to the HW structure
686 * Checks the status of auto-negotiation after link up to ensure that the
687 * speed and duplex were not forced. If the link needed to be forced, then
688 * flow control needs to be forced also. If auto-negotiation is enabled
689 * and did not fail, then we configure flow control based on our link
692 s32
igb_config_fc_after_link_up(struct e1000_hw
*hw
)
694 struct e1000_mac_info
*mac
= &hw
->mac
;
696 u16 mii_status_reg
, mii_nway_adv_reg
, mii_nway_lp_ability_reg
;
700 * Check for the case where we have fiber media and auto-neg failed
701 * so we had to force link. In this case, we need to force the
702 * configuration of the MAC to match the "fc" parameter.
704 if (mac
->autoneg_failed
) {
705 if (hw
->phy
.media_type
== e1000_media_type_fiber
||
706 hw
->phy
.media_type
== e1000_media_type_internal_serdes
)
707 ret_val
= igb_force_mac_fc(hw
);
709 if (hw
->phy
.media_type
== e1000_media_type_copper
)
710 ret_val
= igb_force_mac_fc(hw
);
714 hw_dbg("Error forcing flow control settings\n");
719 * Check for the case where we have copper media and auto-neg is
720 * enabled. In this case, we need to check and see if Auto-Neg
721 * has completed, and if so, how the PHY and link partner has
722 * flow control configured.
724 if ((hw
->phy
.media_type
== e1000_media_type_copper
) && mac
->autoneg
) {
726 * Read the MII Status Register and check to see if AutoNeg
727 * has completed. We read this twice because this reg has
728 * some "sticky" (latched) bits.
730 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, PHY_STATUS
,
734 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, PHY_STATUS
,
739 if (!(mii_status_reg
& MII_SR_AUTONEG_COMPLETE
)) {
740 hw_dbg("Copper PHY and Auto Neg "
741 "has not completed.\n");
746 * The AutoNeg process has completed, so we now need to
747 * read both the Auto Negotiation Advertisement
748 * Register (Address 4) and the Auto_Negotiation Base
749 * Page Ability Register (Address 5) to determine how
750 * flow control was negotiated.
752 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, PHY_AUTONEG_ADV
,
756 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, PHY_LP_ABILITY
,
757 &mii_nway_lp_ability_reg
);
762 * Two bits in the Auto Negotiation Advertisement Register
763 * (Address 4) and two bits in the Auto Negotiation Base
764 * Page Ability Register (Address 5) determine flow control
765 * for both the PHY and the link partner. The following
766 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
767 * 1999, describes these PAUSE resolution bits and how flow
768 * control is determined based upon these settings.
769 * NOTE: DC = Don't Care
771 * LOCAL DEVICE | LINK PARTNER
772 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
773 *-------|---------|-------|---------|--------------------
774 * 0 | 0 | DC | DC | e1000_fc_none
775 * 0 | 1 | 0 | DC | e1000_fc_none
776 * 0 | 1 | 1 | 0 | e1000_fc_none
777 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
778 * 1 | 0 | 0 | DC | e1000_fc_none
779 * 1 | DC | 1 | DC | e1000_fc_full
780 * 1 | 1 | 0 | 0 | e1000_fc_none
781 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
783 * Are both PAUSE bits set to 1? If so, this implies
784 * Symmetric Flow Control is enabled at both ends. The
785 * ASM_DIR bits are irrelevant per the spec.
787 * For Symmetric Flow Control:
789 * LOCAL DEVICE | LINK PARTNER
790 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
791 *-------|---------|-------|---------|--------------------
792 * 1 | DC | 1 | DC | E1000_fc_full
795 if ((mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
796 (mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
)) {
798 * Now we need to check if the user selected RX ONLY
799 * of pause frames. In this case, we had to advertise
800 * FULL flow control because we could not advertise RX
801 * ONLY. Hence, we must now check to see if we need to
802 * turn OFF the TRANSMISSION of PAUSE frames.
804 if (hw
->fc
.original_type
== e1000_fc_full
) {
805 hw
->fc
.type
= e1000_fc_full
;
806 hw_dbg("Flow Control = FULL.\r\n");
808 hw
->fc
.type
= e1000_fc_rx_pause
;
809 hw_dbg("Flow Control = "
810 "RX PAUSE frames only.\r\n");
814 * For receiving PAUSE frames ONLY.
816 * LOCAL DEVICE | LINK PARTNER
817 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
818 *-------|---------|-------|---------|--------------------
819 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
821 else if (!(mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
822 (mii_nway_adv_reg
& NWAY_AR_ASM_DIR
) &&
823 (mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
) &&
824 (mii_nway_lp_ability_reg
& NWAY_LPAR_ASM_DIR
)) {
825 hw
->fc
.type
= e1000_fc_tx_pause
;
826 hw_dbg("Flow Control = TX PAUSE frames only.\r\n");
829 * For transmitting PAUSE frames ONLY.
831 * LOCAL DEVICE | LINK PARTNER
832 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
833 *-------|---------|-------|---------|--------------------
834 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
836 else if ((mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
837 (mii_nway_adv_reg
& NWAY_AR_ASM_DIR
) &&
838 !(mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
) &&
839 (mii_nway_lp_ability_reg
& NWAY_LPAR_ASM_DIR
)) {
840 hw
->fc
.type
= e1000_fc_rx_pause
;
841 hw_dbg("Flow Control = RX PAUSE frames only.\r\n");
844 * Per the IEEE spec, at this point flow control should be
845 * disabled. However, we want to consider that we could
846 * be connected to a legacy switch that doesn't advertise
847 * desired flow control, but can be forced on the link
848 * partner. So if we advertised no flow control, that is
849 * what we will resolve to. If we advertised some kind of
850 * receive capability (Rx Pause Only or Full Flow Control)
851 * and the link partner advertised none, we will configure
852 * ourselves to enable Rx Flow Control only. We can do
853 * this safely for two reasons: If the link partner really
854 * didn't want flow control enabled, and we enable Rx, no
855 * harm done since we won't be receiving any PAUSE frames
856 * anyway. If the intent on the link partner was to have
857 * flow control enabled, then by us enabling RX only, we
858 * can at least receive pause frames and process them.
859 * This is a good idea because in most cases, since we are
860 * predominantly a server NIC, more times than not we will
861 * be asked to delay transmission of packets than asking
862 * our link partner to pause transmission of frames.
864 else if ((hw
->fc
.original_type
== e1000_fc_none
||
865 hw
->fc
.original_type
== e1000_fc_tx_pause
) ||
866 hw
->fc
.strict_ieee
) {
867 hw
->fc
.type
= e1000_fc_none
;
868 hw_dbg("Flow Control = NONE.\r\n");
870 hw
->fc
.type
= e1000_fc_rx_pause
;
871 hw_dbg("Flow Control = RX PAUSE frames only.\r\n");
875 * Now we need to do one last check... If we auto-
876 * negotiated to HALF DUPLEX, flow control should not be
877 * enabled per IEEE 802.3 spec.
879 ret_val
= hw
->mac
.ops
.get_speed_and_duplex(hw
, &speed
, &duplex
);
881 hw_dbg("Error getting link speed and duplex\n");
885 if (duplex
== HALF_DUPLEX
)
886 hw
->fc
.type
= e1000_fc_none
;
889 * Now we call a subroutine to actually force the MAC
890 * controller to use the correct flow control settings.
892 ret_val
= igb_force_mac_fc(hw
);
894 hw_dbg("Error forcing flow control settings\n");
904 * igb_get_speed_and_duplex_copper - Retreive current speed/duplex
905 * @hw: pointer to the HW structure
906 * @speed: stores the current speed
907 * @duplex: stores the current duplex
909 * Read the status register for the current speed/duplex and store the current
910 * speed and duplex for copper connections.
912 s32
igb_get_speed_and_duplex_copper(struct e1000_hw
*hw
, u16
*speed
,
917 status
= rd32(E1000_STATUS
);
918 if (status
& E1000_STATUS_SPEED_1000
) {
920 hw_dbg("1000 Mbs, ");
921 } else if (status
& E1000_STATUS_SPEED_100
) {
929 if (status
& E1000_STATUS_FD
) {
930 *duplex
= FULL_DUPLEX
;
931 hw_dbg("Full Duplex\n");
933 *duplex
= HALF_DUPLEX
;
934 hw_dbg("Half Duplex\n");
941 * igb_get_hw_semaphore - Acquire hardware semaphore
942 * @hw: pointer to the HW structure
944 * Acquire the HW semaphore to access the PHY or NVM
946 s32
igb_get_hw_semaphore(struct e1000_hw
*hw
)
950 s32 timeout
= hw
->nvm
.word_size
+ 1;
953 /* Get the SW semaphore */
954 while (i
< timeout
) {
955 swsm
= rd32(E1000_SWSM
);
956 if (!(swsm
& E1000_SWSM_SMBI
))
964 hw_dbg("Driver can't access device - SMBI bit is set.\n");
965 ret_val
= -E1000_ERR_NVM
;
969 /* Get the FW semaphore. */
970 for (i
= 0; i
< timeout
; i
++) {
971 swsm
= rd32(E1000_SWSM
);
972 wr32(E1000_SWSM
, swsm
| E1000_SWSM_SWESMBI
);
974 /* Semaphore acquired if bit latched */
975 if (rd32(E1000_SWSM
) & E1000_SWSM_SWESMBI
)
982 /* Release semaphores */
983 igb_put_hw_semaphore(hw
);
984 hw_dbg("Driver can't access the NVM\n");
985 ret_val
= -E1000_ERR_NVM
;
994 * igb_put_hw_semaphore - Release hardware semaphore
995 * @hw: pointer to the HW structure
997 * Release hardware semaphore used to access the PHY or NVM
999 void igb_put_hw_semaphore(struct e1000_hw
*hw
)
1003 swsm
= rd32(E1000_SWSM
);
1005 swsm
&= ~(E1000_SWSM_SMBI
| E1000_SWSM_SWESMBI
);
1007 wr32(E1000_SWSM
, swsm
);
1011 * igb_get_auto_rd_done - Check for auto read completion
1012 * @hw: pointer to the HW structure
1014 * Check EEPROM for Auto Read done bit.
1016 s32
igb_get_auto_rd_done(struct e1000_hw
*hw
)
1022 while (i
< AUTO_READ_DONE_TIMEOUT
) {
1023 if (rd32(E1000_EECD
) & E1000_EECD_AUTO_RD
)
1029 if (i
== AUTO_READ_DONE_TIMEOUT
) {
1030 hw_dbg("Auto read by HW from NVM has not completed.\n");
1031 ret_val
= -E1000_ERR_RESET
;
1040 * igb_valid_led_default - Verify a valid default LED config
1041 * @hw: pointer to the HW structure
1042 * @data: pointer to the NVM (EEPROM)
1044 * Read the EEPROM for the current default LED configuration. If the
1045 * LED configuration is not valid, set to a valid LED configuration.
1047 static s32
igb_valid_led_default(struct e1000_hw
*hw
, u16
*data
)
1051 ret_val
= hw
->nvm
.ops
.read_nvm(hw
, NVM_ID_LED_SETTINGS
, 1, data
);
1053 hw_dbg("NVM Read Error\n");
1057 if (*data
== ID_LED_RESERVED_0000
|| *data
== ID_LED_RESERVED_FFFF
)
1058 *data
= ID_LED_DEFAULT
;
1066 * @hw: pointer to the HW structure
1069 s32
igb_id_led_init(struct e1000_hw
*hw
)
1071 struct e1000_mac_info
*mac
= &hw
->mac
;
1073 const u32 ledctl_mask
= 0x000000FF;
1074 const u32 ledctl_on
= E1000_LEDCTL_MODE_LED_ON
;
1075 const u32 ledctl_off
= E1000_LEDCTL_MODE_LED_OFF
;
1077 const u16 led_mask
= 0x0F;
1079 ret_val
= igb_valid_led_default(hw
, &data
);
1083 mac
->ledctl_default
= rd32(E1000_LEDCTL
);
1084 mac
->ledctl_mode1
= mac
->ledctl_default
;
1085 mac
->ledctl_mode2
= mac
->ledctl_default
;
1087 for (i
= 0; i
< 4; i
++) {
1088 temp
= (data
>> (i
<< 2)) & led_mask
;
1090 case ID_LED_ON1_DEF2
:
1091 case ID_LED_ON1_ON2
:
1092 case ID_LED_ON1_OFF2
:
1093 mac
->ledctl_mode1
&= ~(ledctl_mask
<< (i
<< 3));
1094 mac
->ledctl_mode1
|= ledctl_on
<< (i
<< 3);
1096 case ID_LED_OFF1_DEF2
:
1097 case ID_LED_OFF1_ON2
:
1098 case ID_LED_OFF1_OFF2
:
1099 mac
->ledctl_mode1
&= ~(ledctl_mask
<< (i
<< 3));
1100 mac
->ledctl_mode1
|= ledctl_off
<< (i
<< 3);
1107 case ID_LED_DEF1_ON2
:
1108 case ID_LED_ON1_ON2
:
1109 case ID_LED_OFF1_ON2
:
1110 mac
->ledctl_mode2
&= ~(ledctl_mask
<< (i
<< 3));
1111 mac
->ledctl_mode2
|= ledctl_on
<< (i
<< 3);
1113 case ID_LED_DEF1_OFF2
:
1114 case ID_LED_ON1_OFF2
:
1115 case ID_LED_OFF1_OFF2
:
1116 mac
->ledctl_mode2
&= ~(ledctl_mask
<< (i
<< 3));
1117 mac
->ledctl_mode2
|= ledctl_off
<< (i
<< 3);
1130 * igb_cleanup_led - Set LED config to default operation
1131 * @hw: pointer to the HW structure
1133 * Remove the current LED configuration and set the LED configuration
1134 * to the default value, saved from the EEPROM.
1136 s32
igb_cleanup_led(struct e1000_hw
*hw
)
1138 wr32(E1000_LEDCTL
, hw
->mac
.ledctl_default
);
1143 * igb_blink_led - Blink LED
1144 * @hw: pointer to the HW structure
1146 * Blink the led's which are set to be on.
1148 s32
igb_blink_led(struct e1000_hw
*hw
)
1150 u32 ledctl_blink
= 0;
1153 if (hw
->phy
.media_type
== e1000_media_type_fiber
) {
1154 /* always blink LED0 for PCI-E fiber */
1155 ledctl_blink
= E1000_LEDCTL_LED0_BLINK
|
1156 (E1000_LEDCTL_MODE_LED_ON
<< E1000_LEDCTL_LED0_MODE_SHIFT
);
1159 * set the blink bit for each LED that's "on" (0x0E)
1162 ledctl_blink
= hw
->mac
.ledctl_mode2
;
1163 for (i
= 0; i
< 4; i
++)
1164 if (((hw
->mac
.ledctl_mode2
>> (i
* 8)) & 0xFF) ==
1165 E1000_LEDCTL_MODE_LED_ON
)
1166 ledctl_blink
|= (E1000_LEDCTL_LED0_BLINK
<<
1170 wr32(E1000_LEDCTL
, ledctl_blink
);
1176 * igb_led_off - Turn LED off
1177 * @hw: pointer to the HW structure
1181 s32
igb_led_off(struct e1000_hw
*hw
)
1185 switch (hw
->phy
.media_type
) {
1186 case e1000_media_type_fiber
:
1187 ctrl
= rd32(E1000_CTRL
);
1188 ctrl
|= E1000_CTRL_SWDPIN0
;
1189 ctrl
|= E1000_CTRL_SWDPIO0
;
1190 wr32(E1000_CTRL
, ctrl
);
1192 case e1000_media_type_copper
:
1193 wr32(E1000_LEDCTL
, hw
->mac
.ledctl_mode1
);
1203 * igb_disable_pcie_master - Disables PCI-express master access
1204 * @hw: pointer to the HW structure
1206 * Returns 0 (0) if successful, else returns -10
1207 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not casued
1208 * the master requests to be disabled.
1210 * Disables PCI-Express master access and verifies there are no pending
1213 s32
igb_disable_pcie_master(struct e1000_hw
*hw
)
1216 s32 timeout
= MASTER_DISABLE_TIMEOUT
;
1219 if (hw
->bus
.type
!= e1000_bus_type_pci_express
)
1222 ctrl
= rd32(E1000_CTRL
);
1223 ctrl
|= E1000_CTRL_GIO_MASTER_DISABLE
;
1224 wr32(E1000_CTRL
, ctrl
);
1227 if (!(rd32(E1000_STATUS
) &
1228 E1000_STATUS_GIO_MASTER_ENABLE
))
1235 hw_dbg("Master requests are pending.\n");
1236 ret_val
= -E1000_ERR_MASTER_REQUESTS_PENDING
;
1245 * igb_reset_adaptive - Reset Adaptive Interframe Spacing
1246 * @hw: pointer to the HW structure
1248 * Reset the Adaptive Interframe Spacing throttle to default values.
1250 void igb_reset_adaptive(struct e1000_hw
*hw
)
1252 struct e1000_mac_info
*mac
= &hw
->mac
;
1254 if (!mac
->adaptive_ifs
) {
1255 hw_dbg("Not in Adaptive IFS mode!\n");
1259 if (!mac
->ifs_params_forced
) {
1260 mac
->current_ifs_val
= 0;
1261 mac
->ifs_min_val
= IFS_MIN
;
1262 mac
->ifs_max_val
= IFS_MAX
;
1263 mac
->ifs_step_size
= IFS_STEP
;
1264 mac
->ifs_ratio
= IFS_RATIO
;
1267 mac
->in_ifs_mode
= false;
1274 * igb_update_adaptive - Update Adaptive Interframe Spacing
1275 * @hw: pointer to the HW structure
1277 * Update the Adaptive Interframe Spacing Throttle value based on the
1278 * time between transmitted packets and time between collisions.
1280 void igb_update_adaptive(struct e1000_hw
*hw
)
1282 struct e1000_mac_info
*mac
= &hw
->mac
;
1284 if (!mac
->adaptive_ifs
) {
1285 hw_dbg("Not in Adaptive IFS mode!\n");
1289 if ((mac
->collision_delta
* mac
->ifs_ratio
) > mac
->tx_packet_delta
) {
1290 if (mac
->tx_packet_delta
> MIN_NUM_XMITS
) {
1291 mac
->in_ifs_mode
= true;
1292 if (mac
->current_ifs_val
< mac
->ifs_max_val
) {
1293 if (!mac
->current_ifs_val
)
1294 mac
->current_ifs_val
= mac
->ifs_min_val
;
1296 mac
->current_ifs_val
+=
1299 mac
->current_ifs_val
);
1303 if (mac
->in_ifs_mode
&&
1304 (mac
->tx_packet_delta
<= MIN_NUM_XMITS
)) {
1305 mac
->current_ifs_val
= 0;
1306 mac
->in_ifs_mode
= false;
1315 * igb_validate_mdi_setting - Verify MDI/MDIx settings
1316 * @hw: pointer to the HW structure
1318 * Verify that when not using auto-negotitation that MDI/MDIx is correctly
1319 * set, which is forced to MDI mode only.
1321 s32
igb_validate_mdi_setting(struct e1000_hw
*hw
)
1325 if (!hw
->mac
.autoneg
&& (hw
->phy
.mdix
== 0 || hw
->phy
.mdix
== 3)) {
1326 hw_dbg("Invalid MDI setting detected\n");
1328 ret_val
= -E1000_ERR_CONFIG
;
1337 * igb_write_8bit_ctrl_reg - Write a 8bit CTRL register
1338 * @hw: pointer to the HW structure
1339 * @reg: 32bit register offset such as E1000_SCTL
1340 * @offset: register offset to write to
1341 * @data: data to write at register offset
1343 * Writes an address/data control type register. There are several of these
1344 * and they all have the format address << 8 | data and bit 31 is polled for
1347 s32
igb_write_8bit_ctrl_reg(struct e1000_hw
*hw
, u32 reg
,
1348 u32 offset
, u8 data
)
1350 u32 i
, regvalue
= 0;
1353 /* Set up the address and data */
1354 regvalue
= ((u32
)data
) | (offset
<< E1000_GEN_CTL_ADDRESS_SHIFT
);
1355 wr32(reg
, regvalue
);
1357 /* Poll the ready bit to see if the MDI read completed */
1358 for (i
= 0; i
< E1000_GEN_POLL_TIMEOUT
; i
++) {
1360 regvalue
= rd32(reg
);
1361 if (regvalue
& E1000_GEN_CTL_READY
)
1364 if (!(regvalue
& E1000_GEN_CTL_READY
)) {
1365 hw_dbg("Reg %08x did not indicate ready\n", reg
);
1366 ret_val
= -E1000_ERR_PHY
;
1375 * igb_enable_mng_pass_thru - Enable processing of ARP's
1376 * @hw: pointer to the HW structure
1378 * Verifies the hardware needs to allow ARPs to be processed by the host.
1380 bool igb_enable_mng_pass_thru(struct e1000_hw
*hw
)
1384 bool ret_val
= false;
1386 if (!hw
->mac
.asf_firmware_present
)
1389 manc
= rd32(E1000_MANC
);
1391 if (!(manc
& E1000_MANC_RCV_TCO_EN
) ||
1392 !(manc
& E1000_MANC_EN_MAC_ADDR_FILTER
))
1395 if (hw
->mac
.arc_subsystem_valid
) {
1396 fwsm
= rd32(E1000_FWSM
);
1397 factps
= rd32(E1000_FACTPS
);
1399 if (!(factps
& E1000_FACTPS_MNGCG
) &&
1400 ((fwsm
& E1000_FWSM_MODE_MASK
) ==
1401 (e1000_mng_mode_pt
<< E1000_FWSM_MODE_SHIFT
))) {
1406 if ((manc
& E1000_MANC_SMBUS_EN
) &&
1407 !(manc
& E1000_MANC_ASF_EN
)) {