drivers/net/igb/igb.h

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28
  29 /* Linux PRO/1000 Ethernet Driver main header file */
  30
  31 #ifndef _IGB_H_
  32 #define _IGB_H_
  33
  34 #include "e1000_mac.h"
  35 #include "e1000_82575.h"
  36
  37 #include <linux/clocksource.h>
  38 #include <linux/timecompare.h>
  39 #include <linux/net_tstamp.h>
  40
  41 struct igb_adapter;
  42
  43 /* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
  44 #define IGB_START_ITR 648
  45
  46 /* TX/RX descriptor defines */
  47 #define IGB_DEFAULT_TXD                  256
  48 #define IGB_MIN_TXD                       80
  49 #define IGB_MAX_TXD                     4096
  50
  51 #define IGB_DEFAULT_RXD                  256
  52 #define IGB_MIN_RXD                       80
  53 #define IGB_MAX_RXD                     4096
  54
  55 #define IGB_DEFAULT_ITR                    3 /* dynamic */
  56 #define IGB_MAX_ITR_USECS              10000
  57 #define IGB_MIN_ITR_USECS                 10
  58 #define NON_Q_VECTORS                      1
  59 #define MAX_Q_VECTORS                      8
  60
  61 /* Transmit and receive queues */
  62 #define IGB_MAX_RX_QUEUES     (adapter->vfs_allocated_count ? \
  63                                (adapter->vfs_allocated_count > 6 ? 1 : 2) : 4)
  64 #define IGB_MAX_TX_QUEUES     IGB_MAX_RX_QUEUES
  65 #define IGB_ABS_MAX_TX_QUEUES     4
  66
  67 #define IGB_MAX_VF_MC_ENTRIES              30
  68 #define IGB_MAX_VF_FUNCTIONS               8
  69 #define IGB_MAX_VFTA_ENTRIES               128
  70
  71 struct vf_data_storage {
  72         unsigned char vf_mac_addresses[ETH_ALEN];
  73         u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
  74         u16 num_vf_mc_hashes;
  75         u16 vlans_enabled;
  76         bool clear_to_send;
  77 };
  78
  79 /* RX descriptor control thresholds.
  80  * PTHRESH - MAC will consider prefetch if it has fewer than this number of
  81  *           descriptors available in its onboard memory.
  82  *           Setting this to 0 disables RX descriptor prefetch.
  83  * HTHRESH - MAC will only prefetch if there are at least this many descriptors
  84  *           available in host memory.
  85  *           If PTHRESH is 0, this should also be 0.
  86  * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
  87  *           descriptors until either it has this many to write back, or the
  88  *           ITR timer expires.
  89  */
  90 #define IGB_RX_PTHRESH                    (hw->mac.type <= e1000_82576 ? 16 : 8)
  91 #define IGB_RX_HTHRESH                     8
  92 #define IGB_RX_WTHRESH                     1
  93 #define IGB_TX_PTHRESH                     8
  94 #define IGB_TX_HTHRESH                     1
  95 #define IGB_TX_WTHRESH                     ((hw->mac.type == e1000_82576 && \
  96                                              adapter->msix_entries) ? 0 : 16)
  97
  98 /* this is the size past which hardware will drop packets when setting LPE=0 */
  99 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522
 100
 101 /* Supported Rx Buffer Sizes */
 102 #define IGB_RXBUFFER_128   128    /* Used for packet split */
 103 #define IGB_RXBUFFER_1024  1024
 104 #define IGB_RXBUFFER_2048  2048
 105 #define IGB_RXBUFFER_16384 16384
 106
 107 #define MAX_STD_JUMBO_FRAME_SIZE 9234
 108
 109 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
 110 #define IGB_TX_QUEUE_WAKE       16
 111 /* How many Rx Buffers do we bundle into one write to the hardware ? */
 112 #define IGB_RX_BUFFER_WRITE     16      /* Must be power of 2 */
 113
 114 #define AUTO_ALL_MODES            0
 115 #define IGB_EEPROM_APME         0x0400
 116
 117 #ifndef IGB_MASTER_SLAVE
 118 /* Switch to override PHY master/slave setting */
 119 #define IGB_MASTER_SLAVE        e1000_ms_hw_default
 120 #endif
 121
 122 #define IGB_MNG_VLAN_NONE -1
 123
 124 /* wrapper around a pointer to a socket buffer,
 125  * so a DMA handle can be stored along with the buffer */
 126 struct igb_buffer {
 127         struct sk_buff *skb;
 128         dma_addr_t dma;
 129         union {
 130                 /* TX */
 131                 struct {
 132                         unsigned long time_stamp;
 133                         u16 length;
 134                         u16 next_to_watch;
 135                 };
 136                 /* RX */
 137                 struct {
 138                         struct page *page;
 139                         u64 page_dma;
 140                         unsigned int page_offset;
 141                 };
 142         };
 143 };
 144
 145 struct igb_tx_queue_stats {
 146         u64 packets;
 147         u64 bytes;
 148         u64 restart_queue;
 149 };
 150
 151 struct igb_rx_queue_stats {
 152         u64 packets;
 153         u64 bytes;
 154         u64 drops;
 155         u64 csum_err;
 156         u64 alloc_failed;
 157 };
 158
 159 struct igb_q_vector {
 160         struct igb_adapter *adapter; /* backlink */
 161         struct igb_ring *rx_ring;
 162         struct igb_ring *tx_ring;
 163         struct napi_struct napi;
 164
 165         u32 eims_value;
 166         u16 cpu;
 167
 168         u16 itr_val;
 169         u8 set_itr;
 170         u8 itr_shift;
 171         void __iomem *itr_register;
 172
 173         char name[IFNAMSIZ + 9];
 174 };
 175
 176 struct igb_ring {
 177         struct igb_q_vector *q_vector; /* backlink to q_vector */
 178         struct net_device *netdev;     /* back pointer to net_device */
 179         struct pci_dev *pdev;          /* pci device for dma mapping */
 180         dma_addr_t dma;                /* phys address of the ring */
 181         void *desc;                    /* descriptor ring memory */
 182         unsigned int size;             /* length of desc. ring in bytes */
 183         unsigned int count;            /* number of desc. in the ring */
 184         u16 next_to_use;
 185         u16 next_to_clean;
 186         void __iomem *head;
 187         void __iomem *tail;
 188         struct igb_buffer *buffer_info; /* array of buffer info structs */
 189
 190         u8 queue_index;
 191         u8 reg_idx;
 192
 193         unsigned int total_bytes;
 194         unsigned int total_packets;
 195
 196         u32 flags;
 197
 198         union {
 199                 /* TX */
 200                 struct {
 201                         struct igb_tx_queue_stats tx_stats;
 202                         bool detect_tx_hung;
 203                 };
 204                 /* RX */
 205                 struct {
 206                         struct igb_rx_queue_stats rx_stats;
 207                         u32 rx_buffer_len;
 208                 };
 209         };
 210 };
 211
 212 #define IGB_RING_FLAG_RX_CSUM        0x00000001 /* RX CSUM enabled */
 213 #define IGB_RING_FLAG_RX_SCTP_CSUM   0x00000002 /* SCTP CSUM offload enabled */
 214
 215 #define IGB_RING_FLAG_TX_CTX_IDX     0x00000001 /* HW requires context index */
 216
 217 #define IGB_ADVTXD_DCMD (E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS)
 218
 219 #define E1000_RX_DESC_ADV(R, i)     \
 220         (&(((union e1000_adv_rx_desc *)((R).desc))[i]))
 221 #define E1000_TX_DESC_ADV(R, i)     \
 222         (&(((union e1000_adv_tx_desc *)((R).desc))[i]))
 223 #define E1000_TX_CTXTDESC_ADV(R, i)         \
 224         (&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
 225
 226 /* igb_desc_unused - calculate if we have unused descriptors */
 227 static inline int igb_desc_unused(struct igb_ring *ring)
 228 {
 229         if (ring->next_to_clean > ring->next_to_use)
 230                 return ring->next_to_clean - ring->next_to_use - 1;
 231
 232         return ring->count + ring->next_to_clean - ring->next_to_use - 1;
 233 }
 234
 235 /* board specific private data structure */
 236
 237 struct igb_adapter {
 238         struct timer_list watchdog_timer;
 239         struct timer_list phy_info_timer;
 240         struct vlan_group *vlgrp;
 241         u16 mng_vlan_id;
 242         u32 bd_number;
 243         u32 wol;
 244         u32 en_mng_pt;
 245         u16 link_speed;
 246         u16 link_duplex;
 247         unsigned int total_tx_bytes;
 248         unsigned int total_tx_packets;
 249         unsigned int total_rx_bytes;
 250         unsigned int total_rx_packets;
 251         /* Interrupt Throttle Rate */
 252         u32 itr;
 253         u32 itr_setting;
 254         u16 tx_itr;
 255         u16 rx_itr;
 256
 257         struct work_struct reset_task;
 258         struct work_struct watchdog_task;
 259         bool fc_autoneg;
 260         u8  tx_timeout_factor;
 261         struct timer_list blink_timer;
 262         unsigned long led_status;
 263
 264         /* TX */
 265         struct igb_ring *tx_ring;      /* One per active queue */
 266         unsigned long tx_queue_len;
 267         u32 gotc;
 268         u64 gotc_old;
 269         u64 tpt_old;
 270         u64 colc_old;
 271         u32 tx_timeout_count;
 272
 273         /* RX */
 274         struct igb_ring *rx_ring;      /* One per active queue */
 275         int num_tx_queues;
 276         int num_rx_queues;
 277
 278         u32 gorc;
 279         u64 gorc_old;
 280         u32 max_frame_size;
 281         u32 min_frame_size;
 282
 283         /* OS defined structs */
 284         struct net_device *netdev;
 285         struct pci_dev *pdev;
 286         struct cyclecounter cycles;
 287         struct timecounter clock;
 288         struct timecompare compare;
 289         struct hwtstamp_config hwtstamp_config;
 290
 291         /* structs defined in e1000_hw.h */
 292         struct e1000_hw hw;
 293         struct e1000_hw_stats stats;
 294         struct e1000_phy_info phy_info;
 295         struct e1000_phy_stats phy_stats;
 296
 297         u32 test_icr;
 298         struct igb_ring test_tx_ring;
 299         struct igb_ring test_rx_ring;
 300
 301         int msg_enable;
 302
 303         unsigned int num_q_vectors;
 304         struct igb_q_vector *q_vector[MAX_Q_VECTORS];
 305         struct msix_entry *msix_entries;
 306         u32 eims_enable_mask;
 307         u32 eims_other;
 308
 309         /* to not mess up cache alignment, always add to the bottom */
 310         unsigned long state;
 311         unsigned int flags;
 312         u32 eeprom_wol;
 313
 314         struct igb_ring *multi_tx_table[IGB_ABS_MAX_TX_QUEUES];
 315         unsigned int tx_ring_count;
 316         unsigned int rx_ring_count;
 317         unsigned int vfs_allocated_count;
 318         struct vf_data_storage *vf_data;
 319 };
 320
 321 #define IGB_FLAG_HAS_MSI           (1 << 0)
 322 #define IGB_FLAG_DCA_ENABLED       (1 << 1)
 323 #define IGB_FLAG_QUAD_PORT_A       (1 << 2)
 324
 325 enum e1000_state_t {
 326         __IGB_TESTING,
 327         __IGB_RESETTING,
 328         __IGB_DOWN
 329 };
 330
 331 enum igb_boards {
 332         board_82575,
 333 };
 334
 335 extern char igb_driver_name[];
 336 extern char igb_driver_version[];
 337
 338 extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
 339 extern int igb_up(struct igb_adapter *);
 340 extern void igb_down(struct igb_adapter *);
 341 extern void igb_reinit_locked(struct igb_adapter *);
 342 extern void igb_reset(struct igb_adapter *);
 343 extern int igb_set_spd_dplx(struct igb_adapter *, u16);
 344 extern int igb_setup_tx_resources(struct igb_ring *);
 345 extern int igb_setup_rx_resources(struct igb_ring *);
 346 extern void igb_free_tx_resources(struct igb_ring *);
 347 extern void igb_free_rx_resources(struct igb_ring *);
 348 extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
 349 extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
 350 extern void igb_setup_tctl(struct igb_adapter *);
 351 extern void igb_setup_rctl(struct igb_adapter *);
 352 extern void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
 353 extern void igb_update_stats(struct igb_adapter *);
 354 extern void igb_set_ethtool_ops(struct net_device *);
 355
 356 static inline s32 igb_reset_phy(struct e1000_hw *hw)
 357 {
 358         if (hw->phy.ops.reset)
 359                 return hw->phy.ops.reset(hw);
 360
 361         return 0;
 362 }
 363
 364 static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
 365 {
 366         if (hw->phy.ops.read_reg)
 367                 return hw->phy.ops.read_reg(hw, offset, data);
 368
 369         return 0;
 370 }
 371
 372 static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
 373 {
 374         if (hw->phy.ops.write_reg)
 375                 return hw->phy.ops.write_reg(hw, offset, data);
 376
 377         return 0;
 378 }
 379
 380 static inline s32 igb_get_phy_info(struct e1000_hw *hw)
 381 {
 382         if (hw->phy.ops.get_phy_info)
 383                 return hw->phy.ops.get_phy_info(hw);
 384
 385         return 0;
 386 }
 387
 388 #endif /* _IGB_H_ */