drivers/net/igb/igb.h

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28
  29 /* Linux PRO/1000 Ethernet Driver main header file */
  30
  31 #ifndef _IGB_H_
  32 #define _IGB_H_
  33
  34 #include "e1000_mac.h"
  35 #include "e1000_82575.h"
  36
  37 #include <linux/clocksource.h>
  38 #include <linux/timecompare.h>
  39 #include <linux/net_tstamp.h>
  40
  41 struct igb_adapter;
  42
  43 /* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
  44 #define IGB_START_ITR 648
  45
  46 /* TX/RX descriptor defines */
  47 #define IGB_DEFAULT_TXD                  256
  48 #define IGB_MIN_TXD                       80
  49 #define IGB_MAX_TXD                     4096
  50
  51 #define IGB_DEFAULT_RXD                  256
  52 #define IGB_MIN_RXD                       80
  53 #define IGB_MAX_RXD                     4096
  54
  55 #define IGB_DEFAULT_ITR                    3 /* dynamic */
  56 #define IGB_MAX_ITR_USECS              10000
  57 #define IGB_MIN_ITR_USECS                 10
  58 #define NON_Q_VECTORS                      1
  59 #define MAX_Q_VECTORS                      8
  60
  61 /* Transmit and receive queues */
  62 #define IGB_MAX_RX_QUEUES                  (adapter->vfs_allocated_count ? 2 : \
  63                                            (hw->mac.type > e1000_82575 ? 8 : 4))
  64 #define IGB_ABS_MAX_TX_QUEUES              8
  65 #define IGB_MAX_TX_QUEUES                  IGB_MAX_RX_QUEUES
  66
  67 #define IGB_MAX_VF_MC_ENTRIES              30
  68 #define IGB_MAX_VF_FUNCTIONS               8
  69 #define IGB_MAX_VFTA_ENTRIES               128
  70
  71 struct vf_data_storage {
  72         unsigned char vf_mac_addresses[ETH_ALEN];
  73         u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
  74         u16 num_vf_mc_hashes;
  75         u16 vlans_enabled;
  76         u32 flags;
  77         unsigned long last_nack;
  78         u16 pf_vlan; /* When set, guest VLAN config not allowed. */
  79         u16 pf_qos;
  80 };
  81
  82 #define IGB_VF_FLAG_CTS            0x00000001 /* VF is clear to send data */
  83 #define IGB_VF_FLAG_UNI_PROMISC    0x00000002 /* VF has unicast promisc */
  84 #define IGB_VF_FLAG_MULTI_PROMISC  0x00000004 /* VF has multicast promisc */
  85 #define IGB_VF_FLAG_PF_SET_MAC     0x00000008 /* PF has set MAC address */
  86
  87 /* RX descriptor control thresholds.
  88  * PTHRESH - MAC will consider prefetch if it has fewer than this number of
  89  *           descriptors available in its onboard memory.
  90  *           Setting this to 0 disables RX descriptor prefetch.
  91  * HTHRESH - MAC will only prefetch if there are at least this many descriptors
  92  *           available in host memory.
  93  *           If PTHRESH is 0, this should also be 0.
  94  * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
  95  *           descriptors until either it has this many to write back, or the
  96  *           ITR timer expires.
  97  */
  98 #define IGB_RX_PTHRESH                     8
  99 #define IGB_RX_HTHRESH                     8
 100 #define IGB_RX_WTHRESH                     1
 101 #define IGB_TX_PTHRESH                     8
 102 #define IGB_TX_HTHRESH                     1
 103 #define IGB_TX_WTHRESH                     ((hw->mac.type == e1000_82576 && \
 104                                              adapter->msix_entries) ? 1 : 16)
 105
 106 /* this is the size past which hardware will drop packets when setting LPE=0 */
 107 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522
 108
 109 /* Supported Rx Buffer Sizes */
 110 #define IGB_RXBUFFER_64    64     /* Used for packet split */
 111 #define IGB_RXBUFFER_128   128    /* Used for packet split */
 112 #define IGB_RXBUFFER_1024  1024
 113 #define IGB_RXBUFFER_2048  2048
 114 #define IGB_RXBUFFER_16384 16384
 115
 116 #define MAX_STD_JUMBO_FRAME_SIZE 9234
 117
 118 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
 119 #define IGB_TX_QUEUE_WAKE       16
 120 /* How many Rx Buffers do we bundle into one write to the hardware ? */
 121 #define IGB_RX_BUFFER_WRITE     16      /* Must be power of 2 */
 122
 123 #define AUTO_ALL_MODES            0
 124 #define IGB_EEPROM_APME         0x0400
 125
 126 #ifndef IGB_MASTER_SLAVE
 127 /* Switch to override PHY master/slave setting */
 128 #define IGB_MASTER_SLAVE        e1000_ms_hw_default
 129 #endif
 130
 131 #define IGB_MNG_VLAN_NONE -1
 132
 133 /* wrapper around a pointer to a socket buffer,
 134  * so a DMA handle can be stored along with the buffer */
 135 struct igb_buffer {
 136         struct sk_buff *skb;
 137         dma_addr_t dma;
 138         union {
 139                 /* TX */
 140                 struct {
 141                         unsigned long time_stamp;
 142                         u16 length;
 143                         u16 next_to_watch;
 144                         unsigned int bytecount;
 145                         u16 gso_segs;
 146                         u8 tx_flags;
 147                         u8 mapped_as_page;
 148                 };
 149                 /* RX */
 150                 struct {
 151                         struct page *page;
 152                         dma_addr_t page_dma;
 153                         u16 page_offset;
 154                 };
 155         };
 156 };
 157
 158 struct igb_tx_queue_stats {
 159         u64 packets;
 160         u64 bytes;
 161         u64 restart_queue;
 162         u64 restart_queue2;
 163 };
 164
 165 struct igb_rx_queue_stats {
 166         u64 packets;
 167         u64 bytes;
 168         u64 drops;
 169         u64 csum_err;
 170         u64 alloc_failed;
 171 };
 172
 173 struct igb_q_vector {
 174         struct igb_adapter *adapter; /* backlink */
 175         struct igb_ring *rx_ring;
 176         struct igb_ring *tx_ring;
 177         struct napi_struct napi;
 178
 179         u32 eims_value;
 180         u16 cpu;
 181
 182         u16 itr_val;
 183         u8 set_itr;
 184         void __iomem *itr_register;
 185
 186         char name[IFNAMSIZ + 9];
 187 };
 188
 189 struct igb_ring {
 190         struct igb_q_vector *q_vector; /* backlink to q_vector */
 191         struct net_device *netdev;     /* back pointer to net_device */
 192         struct device *dev;            /* device pointer for dma mapping */
 193         dma_addr_t dma;                /* phys address of the ring */
 194         void *desc;                    /* descriptor ring memory */
 195         unsigned int size;             /* length of desc. ring in bytes */
 196         u16 count;                     /* number of desc. in the ring */
 197         u16 next_to_use;
 198         u16 next_to_clean;
 199         u8 queue_index;
 200         u8 reg_idx;
 201         void __iomem *head;
 202         void __iomem *tail;
 203         struct igb_buffer *buffer_info; /* array of buffer info structs */
 204
 205         unsigned int total_bytes;
 206         unsigned int total_packets;
 207
 208         u32 flags;
 209
 210         union {
 211                 /* TX */
 212                 struct {
 213                         struct igb_tx_queue_stats tx_stats;
 214                         struct u64_stats_sync tx_syncp;
 215                         struct u64_stats_sync tx_syncp2;
 216                         bool detect_tx_hung;
 217                 };
 218                 /* RX */
 219                 struct {
 220                         struct igb_rx_queue_stats rx_stats;
 221                         struct u64_stats_sync rx_syncp;
 222                         u32 rx_buffer_len;
 223                 };
 224         };
 225 };
 226
 227 #define IGB_RING_FLAG_RX_CSUM        0x00000001 /* RX CSUM enabled */
 228 #define IGB_RING_FLAG_RX_SCTP_CSUM   0x00000002 /* SCTP CSUM offload enabled */
 229
 230 #define IGB_RING_FLAG_TX_CTX_IDX     0x00000001 /* HW requires context index */
 231
 232 #define IGB_ADVTXD_DCMD (E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS)
 233
 234 #define E1000_RX_DESC_ADV(R, i)     \
 235         (&(((union e1000_adv_rx_desc *)((R).desc))[i]))
 236 #define E1000_TX_DESC_ADV(R, i)     \
 237         (&(((union e1000_adv_tx_desc *)((R).desc))[i]))
 238 #define E1000_TX_CTXTDESC_ADV(R, i)         \
 239         (&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
 240
 241 /* igb_desc_unused - calculate if we have unused descriptors */
 242 static inline int igb_desc_unused(struct igb_ring *ring)
 243 {
 244         if (ring->next_to_clean > ring->next_to_use)
 245                 return ring->next_to_clean - ring->next_to_use - 1;
 246
 247         return ring->count + ring->next_to_clean - ring->next_to_use - 1;
 248 }
 249
 250 /* board specific private data structure */
 251 struct igb_adapter {
 252         struct timer_list watchdog_timer;
 253         struct timer_list phy_info_timer;
 254         struct vlan_group *vlgrp;
 255         u16 mng_vlan_id;
 256         u32 bd_number;
 257         u32 wol;
 258         u32 en_mng_pt;
 259         u16 link_speed;
 260         u16 link_duplex;
 261
 262         /* Interrupt Throttle Rate */
 263         u32 rx_itr_setting;
 264         u32 tx_itr_setting;
 265         u16 tx_itr;
 266         u16 rx_itr;
 267
 268         struct work_struct reset_task;
 269         struct work_struct watchdog_task;
 270         bool fc_autoneg;
 271         u8  tx_timeout_factor;
 272         struct timer_list blink_timer;
 273         unsigned long led_status;
 274
 275         /* TX */
 276         struct igb_ring *tx_ring[16];
 277         u32 tx_timeout_count;
 278
 279         /* RX */
 280         struct igb_ring *rx_ring[16];
 281         int num_tx_queues;
 282         int num_rx_queues;
 283
 284         u32 max_frame_size;
 285         u32 min_frame_size;
 286
 287         /* OS defined structs */
 288         struct net_device *netdev;
 289         struct pci_dev *pdev;
 290         struct cyclecounter cycles;
 291         struct timecounter clock;
 292         struct timecompare compare;
 293         struct hwtstamp_config hwtstamp_config;
 294
 295         spinlock_t stats64_lock;
 296         struct rtnl_link_stats64 stats64;
 297
 298         /* structs defined in e1000_hw.h */
 299         struct e1000_hw hw;
 300         struct e1000_hw_stats stats;
 301         struct e1000_phy_info phy_info;
 302         struct e1000_phy_stats phy_stats;
 303
 304         u32 test_icr;
 305         struct igb_ring test_tx_ring;
 306         struct igb_ring test_rx_ring;
 307
 308         int msg_enable;
 309
 310         unsigned int num_q_vectors;
 311         struct igb_q_vector *q_vector[MAX_Q_VECTORS];
 312         struct msix_entry *msix_entries;
 313         u32 eims_enable_mask;
 314         u32 eims_other;
 315
 316         /* to not mess up cache alignment, always add to the bottom */
 317         unsigned long state;
 318         unsigned int flags;
 319         u32 eeprom_wol;
 320
 321         struct igb_ring *multi_tx_table[IGB_ABS_MAX_TX_QUEUES];
 322         u16 tx_ring_count;
 323         u16 rx_ring_count;
 324         unsigned int vfs_allocated_count;
 325         struct vf_data_storage *vf_data;
 326         u32 rss_queues;
 327 };
 328
 329 #define IGB_FLAG_HAS_MSI           (1 << 0)
 330 #define IGB_FLAG_DCA_ENABLED       (1 << 1)
 331 #define IGB_FLAG_QUAD_PORT_A       (1 << 2)
 332 #define IGB_FLAG_QUEUE_PAIRS       (1 << 3)
 333
 334 #define IGB_82576_TSYNC_SHIFT 19
 335 #define IGB_82580_TSYNC_SHIFT 24
 336 #define IGB_TS_HDR_LEN        16
 337 enum e1000_state_t {
 338         __IGB_TESTING,
 339         __IGB_RESETTING,
 340         __IGB_DOWN
 341 };
 342
 343 enum igb_boards {
 344         board_82575,
 345 };
 346
 347 extern char igb_driver_name[];
 348 extern char igb_driver_version[];
 349
 350 extern int igb_up(struct igb_adapter *);
 351 extern void igb_down(struct igb_adapter *);
 352 extern void igb_reinit_locked(struct igb_adapter *);
 353 extern void igb_reset(struct igb_adapter *);
 354 extern int igb_set_spd_dplx(struct igb_adapter *, u16);
 355 extern int igb_setup_tx_resources(struct igb_ring *);
 356 extern int igb_setup_rx_resources(struct igb_ring *);
 357 extern void igb_free_tx_resources(struct igb_ring *);
 358 extern void igb_free_rx_resources(struct igb_ring *);
 359 extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
 360 extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
 361 extern void igb_setup_tctl(struct igb_adapter *);
 362 extern void igb_setup_rctl(struct igb_adapter *);
 363 extern netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *, struct igb_ring *);
 364 extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
 365                                            struct igb_buffer *);
 366 extern void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
 367 extern void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *);
 368 extern bool igb_has_link(struct igb_adapter *adapter);
 369 extern void igb_set_ethtool_ops(struct net_device *);
 370 extern void igb_power_up_link(struct igb_adapter *);
 371
 372 static inline s32 igb_reset_phy(struct e1000_hw *hw)
 373 {
 374         if (hw->phy.ops.reset)
 375                 return hw->phy.ops.reset(hw);
 376
 377         return 0;
 378 }
 379
 380 static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
 381 {
 382         if (hw->phy.ops.read_reg)
 383                 return hw->phy.ops.read_reg(hw, offset, data);
 384
 385         return 0;
 386 }
 387
 388 static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
 389 {
 390         if (hw->phy.ops.write_reg)
 391                 return hw->phy.ops.write_reg(hw, offset, data);
 392
 393         return 0;
 394 }
 395
 396 static inline s32 igb_get_phy_info(struct e1000_hw *hw)
 397 {
 398         if (hw->phy.ops.get_phy_info)
 399                 return hw->phy.ops.get_phy_info(hw);
 400
 401         return 0;
 402 }
 403
 404 #endif /* _IGB_H_ */