drivers/net/igb/igb.h

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28
  29 /* Linux PRO/1000 Ethernet Driver main header file */
  30
  31 #ifndef _IGB_H_
  32 #define _IGB_H_
  33
  34 #include "e1000_mac.h"
  35 #include "e1000_82575.h"
  36
  37 #include <linux/clocksource.h>
  38 #include <linux/timecompare.h>
  39 #include <linux/net_tstamp.h>
  40
  41 struct igb_adapter;
  42
  43 /* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
  44 #define IGB_START_ITR 648
  45
  46 /* TX/RX descriptor defines */
  47 #define IGB_DEFAULT_TXD                  256
  48 #define IGB_MIN_TXD                       80
  49 #define IGB_MAX_TXD                     4096
  50
  51 #define IGB_DEFAULT_RXD                  256
  52 #define IGB_MIN_RXD                       80
  53 #define IGB_MAX_RXD                     4096
  54
  55 #define IGB_DEFAULT_ITR                    3 /* dynamic */
  56 #define IGB_MAX_ITR_USECS              10000
  57 #define IGB_MIN_ITR_USECS                 10
  58 #define NON_Q_VECTORS                      1
  59 #define MAX_Q_VECTORS                      8
  60
  61 /* Transmit and receive queues */
  62 #define IGB_MAX_RX_QUEUES     (adapter->vfs_allocated_count ? \
  63                                (adapter->vfs_allocated_count > 6 ? 1 : 2) : 4)
  64 #define IGB_MAX_TX_QUEUES     IGB_MAX_RX_QUEUES
  65 #define IGB_ABS_MAX_TX_QUEUES     4
  66
  67 #define IGB_MAX_VF_MC_ENTRIES              30
  68 #define IGB_MAX_VF_FUNCTIONS               8
  69 #define IGB_MAX_VFTA_ENTRIES               128
  70
  71 struct vf_data_storage {
  72         unsigned char vf_mac_addresses[ETH_ALEN];
  73         u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
  74         u16 num_vf_mc_hashes;
  75         u16 vlans_enabled;
  76         bool clear_to_send;
  77 };
  78
  79 /* RX descriptor control thresholds.
  80  * PTHRESH - MAC will consider prefetch if it has fewer than this number of
  81  *           descriptors available in its onboard memory.
  82  *           Setting this to 0 disables RX descriptor prefetch.
  83  * HTHRESH - MAC will only prefetch if there are at least this many descriptors
  84  *           available in host memory.
  85  *           If PTHRESH is 0, this should also be 0.
  86  * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
  87  *           descriptors until either it has this many to write back, or the
  88  *           ITR timer expires.
  89  */
  90 #define IGB_RX_PTHRESH                    16
  91 #define IGB_RX_HTHRESH                     8
  92 #define IGB_RX_WTHRESH                     1
  93
  94 /* this is the size past which hardware will drop packets when setting LPE=0 */
  95 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522
  96
  97 /* Supported Rx Buffer Sizes */
  98 #define IGB_RXBUFFER_128   128    /* Used for packet split */
  99 #define IGB_RXBUFFER_256   256    /* Used for packet split */
 100 #define IGB_RXBUFFER_512   512
 101 #define IGB_RXBUFFER_1024  1024
 102 #define IGB_RXBUFFER_2048  2048
 103 #define IGB_RXBUFFER_16384 16384
 104
 105 #define MAX_STD_JUMBO_FRAME_SIZE 9234
 106
 107 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
 108 #define IGB_TX_QUEUE_WAKE       16
 109 /* How many Rx Buffers do we bundle into one write to the hardware ? */
 110 #define IGB_RX_BUFFER_WRITE     16      /* Must be power of 2 */
 111
 112 #define AUTO_ALL_MODES            0
 113 #define IGB_EEPROM_APME         0x0400
 114
 115 #ifndef IGB_MASTER_SLAVE
 116 /* Switch to override PHY master/slave setting */
 117 #define IGB_MASTER_SLAVE        e1000_ms_hw_default
 118 #endif
 119
 120 #define IGB_MNG_VLAN_NONE -1
 121
 122 /* wrapper around a pointer to a socket buffer,
 123  * so a DMA handle can be stored along with the buffer */
 124 struct igb_buffer {
 125         struct sk_buff *skb;
 126         dma_addr_t dma;
 127         union {
 128                 /* TX */
 129                 struct {
 130                         unsigned long time_stamp;
 131                         u16 length;
 132                         u16 next_to_watch;
 133                 };
 134                 /* RX */
 135                 struct {
 136                         struct page *page;
 137                         u64 page_dma;
 138                         unsigned int page_offset;
 139                 };
 140         };
 141 };
 142
 143 struct igb_tx_queue_stats {
 144         u64 packets;
 145         u64 bytes;
 146 };
 147
 148 struct igb_rx_queue_stats {
 149         u64 packets;
 150         u64 bytes;
 151         u64 drops;
 152 };
 153
 154 struct igb_q_vector {
 155         struct igb_adapter *adapter; /* backlink */
 156         struct igb_ring *rx_ring;
 157         struct igb_ring *tx_ring;
 158         struct napi_struct napi;
 159
 160         u32 eims_value;
 161         u16 cpu;
 162
 163         u16 itr_val;
 164         u8 set_itr;
 165         u8 itr_shift;
 166         void __iomem *itr_register;
 167
 168         char name[IFNAMSIZ + 9];
 169 };
 170
 171 struct igb_ring {
 172         struct igb_q_vector *q_vector; /* backlink to q_vector */
 173         void *desc;                    /* descriptor ring memory */
 174         dma_addr_t dma;                /* phys address of the ring */
 175         unsigned int size;             /* length of desc. ring in bytes */
 176         unsigned int count;            /* number of desc. in the ring */
 177         u16 next_to_use;
 178         u16 next_to_clean;
 179         u16 head;
 180         u16 tail;
 181         struct igb_buffer *buffer_info; /* array of buffer info structs */
 182
 183         u8 queue_index;
 184         u8 reg_idx;
 185
 186         unsigned int total_bytes;
 187         unsigned int total_packets;
 188
 189         union {
 190                 /* TX */
 191                 struct {
 192                         struct igb_tx_queue_stats tx_stats;
 193                         bool detect_tx_hung;
 194                 };
 195                 /* RX */
 196                 struct {
 197                         struct igb_rx_queue_stats rx_stats;
 198                         u64 rx_queue_drops;
 199                 };
 200         };
 201 };
 202
 203 #define E1000_RX_DESC_ADV(R, i)     \
 204         (&(((union e1000_adv_rx_desc *)((R).desc))[i]))
 205 #define E1000_TX_DESC_ADV(R, i)     \
 206         (&(((union e1000_adv_tx_desc *)((R).desc))[i]))
 207 #define E1000_TX_CTXTDESC_ADV(R, i)         \
 208         (&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
 209
 210 /* board specific private data structure */
 211
 212 struct igb_adapter {
 213         struct timer_list watchdog_timer;
 214         struct timer_list phy_info_timer;
 215         struct vlan_group *vlgrp;
 216         u16 mng_vlan_id;
 217         u32 bd_number;
 218         u32 rx_buffer_len;
 219         u32 wol;
 220         u32 en_mng_pt;
 221         u16 link_speed;
 222         u16 link_duplex;
 223         unsigned int total_tx_bytes;
 224         unsigned int total_tx_packets;
 225         unsigned int total_rx_bytes;
 226         unsigned int total_rx_packets;
 227         /* Interrupt Throttle Rate */
 228         u32 itr;
 229         u32 itr_setting;
 230         u16 tx_itr;
 231         u16 rx_itr;
 232
 233         struct work_struct reset_task;
 234         struct work_struct watchdog_task;
 235         bool fc_autoneg;
 236         u8  tx_timeout_factor;
 237         struct timer_list blink_timer;
 238         unsigned long led_status;
 239
 240         /* TX */
 241         struct igb_ring *tx_ring;      /* One per active queue */
 242         unsigned int restart_queue;
 243         unsigned long tx_queue_len;
 244         u32 txd_cmd;
 245         u32 gotc;
 246         u64 gotc_old;
 247         u64 tpt_old;
 248         u64 colc_old;
 249         u32 tx_timeout_count;
 250
 251         /* RX */
 252         struct igb_ring *rx_ring;      /* One per active queue */
 253         int num_tx_queues;
 254         int num_rx_queues;
 255
 256         u64 hw_csum_err;
 257         u64 hw_csum_good;
 258         u32 alloc_rx_buff_failed;
 259         u32 gorc;
 260         u64 gorc_old;
 261         u16 rx_ps_hdr_size;
 262         u32 max_frame_size;
 263         u32 min_frame_size;
 264
 265         /* OS defined structs */
 266         struct net_device *netdev;
 267         struct pci_dev *pdev;
 268         struct cyclecounter cycles;
 269         struct timecounter clock;
 270         struct timecompare compare;
 271         struct hwtstamp_config hwtstamp_config;
 272
 273         /* structs defined in e1000_hw.h */
 274         struct e1000_hw hw;
 275         struct e1000_hw_stats stats;
 276         struct e1000_phy_info phy_info;
 277         struct e1000_phy_stats phy_stats;
 278
 279         u32 test_icr;
 280         struct igb_ring test_tx_ring;
 281         struct igb_ring test_rx_ring;
 282
 283         int msg_enable;
 284
 285         unsigned int num_q_vectors;
 286         struct igb_q_vector *q_vector[MAX_Q_VECTORS];
 287         struct msix_entry *msix_entries;
 288         u32 eims_enable_mask;
 289         u32 eims_other;
 290
 291         /* to not mess up cache alignment, always add to the bottom */
 292         unsigned long state;
 293         unsigned int flags;
 294         u32 eeprom_wol;
 295
 296         struct igb_ring *multi_tx_table[IGB_ABS_MAX_TX_QUEUES];
 297         unsigned int tx_ring_count;
 298         unsigned int rx_ring_count;
 299         unsigned int vfs_allocated_count;
 300         struct vf_data_storage *vf_data;
 301 };
 302
 303 #define IGB_FLAG_HAS_MSI           (1 << 0)
 304 #define IGB_FLAG_DCA_ENABLED       (1 << 1)
 305 #define IGB_FLAG_QUAD_PORT_A       (1 << 2)
 306 #define IGB_FLAG_NEED_CTX_IDX      (1 << 3)
 307 #define IGB_FLAG_RX_CSUM_DISABLED  (1 << 4)
 308
 309 enum e1000_state_t {
 310         __IGB_TESTING,
 311         __IGB_RESETTING,
 312         __IGB_DOWN
 313 };
 314
 315 enum igb_boards {
 316         board_82575,
 317 };
 318
 319 extern char igb_driver_name[];
 320 extern char igb_driver_version[];
 321
 322 extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
 323 extern int igb_up(struct igb_adapter *);
 324 extern void igb_down(struct igb_adapter *);
 325 extern void igb_reinit_locked(struct igb_adapter *);
 326 extern void igb_reset(struct igb_adapter *);
 327 extern int igb_set_spd_dplx(struct igb_adapter *, u16);
 328 extern int igb_setup_tx_resources(struct igb_adapter *, struct igb_ring *);
 329 extern int igb_setup_rx_resources(struct igb_adapter *, struct igb_ring *);
 330 extern void igb_free_tx_resources(struct igb_ring *);
 331 extern void igb_free_rx_resources(struct igb_ring *);
 332 extern void igb_update_stats(struct igb_adapter *);
 333 extern void igb_set_ethtool_ops(struct net_device *);
 334
 335 static inline s32 igb_reset_phy(struct e1000_hw *hw)
 336 {
 337         if (hw->phy.ops.reset)
 338                 return hw->phy.ops.reset(hw);
 339
 340         return 0;
 341 }
 342
 343 static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
 344 {
 345         if (hw->phy.ops.read_reg)
 346                 return hw->phy.ops.read_reg(hw, offset, data);
 347
 348         return 0;
 349 }
 350
 351 static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
 352 {
 353         if (hw->phy.ops.write_reg)
 354                 return hw->phy.ops.write_reg(hw, offset, data);
 355
 356         return 0;
 357 }
 358
 359 static inline s32 igb_get_phy_info(struct e1000_hw *hw)
 360 {
 361         if (hw->phy.ops.get_phy_info)
 362                 return hw->phy.ops.get_phy_info(hw);
 363
 364         return 0;
 365 }
 366
 367 #endif /* _IGB_H_ */