drivers/net/igb/igb.h

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28
  29 /* Linux PRO/1000 Ethernet Driver main header file */
  30
  31 #ifndef _IGB_H_
  32 #define _IGB_H_
  33
  34 #include "e1000_mac.h"
  35 #include "e1000_82575.h"
  36
  37 #include <linux/clocksource.h>
  38 #include <linux/timecompare.h>
  39 #include <linux/net_tstamp.h>
  40
  41 struct igb_adapter;
  42
  43 /* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
  44 #define IGB_START_ITR 648
  45
  46 /* TX/RX descriptor defines */
  47 #define IGB_DEFAULT_TXD                  256
  48 #define IGB_MIN_TXD                       80
  49 #define IGB_MAX_TXD                     4096
  50
  51 #define IGB_DEFAULT_RXD                  256
  52 #define IGB_MIN_RXD                       80
  53 #define IGB_MAX_RXD                     4096
  54
  55 #define IGB_DEFAULT_ITR                    3 /* dynamic */
  56 #define IGB_MAX_ITR_USECS              10000
  57 #define IGB_MIN_ITR_USECS                 10
  58
  59 /* Transmit and receive queues */
  60 #define IGB_MAX_RX_QUEUES     (adapter->vfs_allocated_count ? \
  61                                (adapter->vfs_allocated_count > 6 ? 1 : 2) : 4)
  62 #define IGB_MAX_TX_QUEUES     IGB_MAX_RX_QUEUES
  63 #define IGB_ABS_MAX_TX_QUEUES     4
  64
  65 #define IGB_MAX_VF_MC_ENTRIES              30
  66 #define IGB_MAX_VF_FUNCTIONS               8
  67 #define IGB_MAX_VFTA_ENTRIES               128
  68
  69 struct vf_data_storage {
  70         unsigned char vf_mac_addresses[ETH_ALEN];
  71         u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
  72         u16 num_vf_mc_hashes;
  73         u16 vlans_enabled;
  74         bool clear_to_send;
  75 };
  76
  77 /* RX descriptor control thresholds.
  78  * PTHRESH - MAC will consider prefetch if it has fewer than this number of
  79  *           descriptors available in its onboard memory.
  80  *           Setting this to 0 disables RX descriptor prefetch.
  81  * HTHRESH - MAC will only prefetch if there are at least this many descriptors
  82  *           available in host memory.
  83  *           If PTHRESH is 0, this should also be 0.
  84  * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
  85  *           descriptors until either it has this many to write back, or the
  86  *           ITR timer expires.
  87  */
  88 #define IGB_RX_PTHRESH                    16
  89 #define IGB_RX_HTHRESH                     8
  90 #define IGB_RX_WTHRESH                     1
  91
  92 /* this is the size past which hardware will drop packets when setting LPE=0 */
  93 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522
  94
  95 /* Supported Rx Buffer Sizes */
  96 #define IGB_RXBUFFER_128   128    /* Used for packet split */
  97 #define IGB_RXBUFFER_256   256    /* Used for packet split */
  98 #define IGB_RXBUFFER_512   512
  99 #define IGB_RXBUFFER_1024  1024
 100 #define IGB_RXBUFFER_2048  2048
 101 #define IGB_RXBUFFER_16384 16384
 102
 103 #define MAX_STD_JUMBO_FRAME_SIZE 9234
 104
 105 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
 106 #define IGB_TX_QUEUE_WAKE       16
 107 /* How many Rx Buffers do we bundle into one write to the hardware ? */
 108 #define IGB_RX_BUFFER_WRITE     16      /* Must be power of 2 */
 109
 110 #define AUTO_ALL_MODES            0
 111 #define IGB_EEPROM_APME         0x0400
 112
 113 #ifndef IGB_MASTER_SLAVE
 114 /* Switch to override PHY master/slave setting */
 115 #define IGB_MASTER_SLAVE        e1000_ms_hw_default
 116 #endif
 117
 118 #define IGB_MNG_VLAN_NONE -1
 119
 120 /* wrapper around a pointer to a socket buffer,
 121  * so a DMA handle can be stored along with the buffer */
 122 struct igb_buffer {
 123         struct sk_buff *skb;
 124         dma_addr_t dma;
 125         union {
 126                 /* TX */
 127                 struct {
 128                         unsigned long time_stamp;
 129                         u16 length;
 130                         u16 next_to_watch;
 131                 };
 132                 /* RX */
 133                 struct {
 134                         struct page *page;
 135                         u64 page_dma;
 136                         unsigned int page_offset;
 137                 };
 138         };
 139 };
 140
 141 struct igb_tx_queue_stats {
 142         u64 packets;
 143         u64 bytes;
 144 };
 145
 146 struct igb_rx_queue_stats {
 147         u64 packets;
 148         u64 bytes;
 149         u64 drops;
 150 };
 151
 152 struct igb_ring {
 153         struct igb_adapter *adapter; /* backlink */
 154         void *desc;                  /* descriptor ring memory */
 155         dma_addr_t dma;              /* phys address of the ring */
 156         unsigned int size;           /* length of desc. ring in bytes */
 157         unsigned int count;          /* number of desc. in the ring */
 158         u16 next_to_use;
 159         u16 next_to_clean;
 160         u16 head;
 161         u16 tail;
 162         struct igb_buffer *buffer_info; /* array of buffer info structs */
 163
 164         u32 eims_value;
 165         u32 itr_val;
 166         u16 itr_register;
 167         u16 cpu;
 168
 169         u16 queue_index;
 170         u16 reg_idx;
 171         unsigned int total_bytes;
 172         unsigned int total_packets;
 173
 174         union {
 175                 /* TX */
 176                 struct {
 177                         struct igb_tx_queue_stats tx_stats;
 178                         bool detect_tx_hung;
 179                 };
 180                 /* RX */
 181                 struct {
 182                         struct igb_rx_queue_stats rx_stats;
 183                         u64 rx_queue_drops;
 184                         struct napi_struct napi;
 185                         int set_itr;
 186                         struct igb_ring *buddy;
 187                 };
 188         };
 189
 190         char name[IFNAMSIZ + 5];
 191 };
 192
 193 #define E1000_RX_DESC_ADV(R, i)     \
 194         (&(((union e1000_adv_rx_desc *)((R).desc))[i]))
 195 #define E1000_TX_DESC_ADV(R, i)     \
 196         (&(((union e1000_adv_tx_desc *)((R).desc))[i]))
 197 #define E1000_TX_CTXTDESC_ADV(R, i)         \
 198         (&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
 199
 200 /* board specific private data structure */
 201
 202 struct igb_adapter {
 203         struct timer_list watchdog_timer;
 204         struct timer_list phy_info_timer;
 205         struct vlan_group *vlgrp;
 206         u16 mng_vlan_id;
 207         u32 bd_number;
 208         u32 rx_buffer_len;
 209         u32 wol;
 210         u32 en_mng_pt;
 211         u16 link_speed;
 212         u16 link_duplex;
 213         unsigned int total_tx_bytes;
 214         unsigned int total_tx_packets;
 215         unsigned int total_rx_bytes;
 216         unsigned int total_rx_packets;
 217         /* Interrupt Throttle Rate */
 218         u32 itr;
 219         u32 itr_setting;
 220         u16 tx_itr;
 221         u16 rx_itr;
 222
 223         struct work_struct reset_task;
 224         struct work_struct watchdog_task;
 225         bool fc_autoneg;
 226         u8  tx_timeout_factor;
 227         struct timer_list blink_timer;
 228         unsigned long led_status;
 229
 230         /* TX */
 231         struct igb_ring *tx_ring;      /* One per active queue */
 232         unsigned int restart_queue;
 233         unsigned long tx_queue_len;
 234         u32 txd_cmd;
 235         u32 gotc;
 236         u64 gotc_old;
 237         u64 tpt_old;
 238         u64 colc_old;
 239         u32 tx_timeout_count;
 240
 241         /* RX */
 242         struct igb_ring *rx_ring;      /* One per active queue */
 243         int num_tx_queues;
 244         int num_rx_queues;
 245
 246         u64 hw_csum_err;
 247         u64 hw_csum_good;
 248         u32 alloc_rx_buff_failed;
 249         u32 gorc;
 250         u64 gorc_old;
 251         u16 rx_ps_hdr_size;
 252         u32 max_frame_size;
 253         u32 min_frame_size;
 254
 255         /* OS defined structs */
 256         struct net_device *netdev;
 257         struct napi_struct napi;
 258         struct pci_dev *pdev;
 259         struct net_device_stats net_stats;
 260         struct cyclecounter cycles;
 261         struct timecounter clock;
 262         struct timecompare compare;
 263         struct hwtstamp_config hwtstamp_config;
 264
 265         /* structs defined in e1000_hw.h */
 266         struct e1000_hw hw;
 267         struct e1000_hw_stats stats;
 268         struct e1000_phy_info phy_info;
 269         struct e1000_phy_stats phy_stats;
 270
 271         u32 test_icr;
 272         struct igb_ring test_tx_ring;
 273         struct igb_ring test_rx_ring;
 274
 275         int msg_enable;
 276         struct msix_entry *msix_entries;
 277         u32 eims_enable_mask;
 278         u32 eims_other;
 279
 280         /* to not mess up cache alignment, always add to the bottom */
 281         unsigned long state;
 282         unsigned int flags;
 283         u32 eeprom_wol;
 284
 285         struct igb_ring *multi_tx_table[IGB_ABS_MAX_TX_QUEUES];
 286         unsigned int tx_ring_count;
 287         unsigned int rx_ring_count;
 288         unsigned int vfs_allocated_count;
 289         struct vf_data_storage *vf_data;
 290 };
 291
 292 #define IGB_FLAG_HAS_MSI           (1 << 0)
 293 #define IGB_FLAG_DCA_ENABLED       (1 << 1)
 294 #define IGB_FLAG_QUAD_PORT_A       (1 << 2)
 295 #define IGB_FLAG_NEED_CTX_IDX      (1 << 3)
 296 #define IGB_FLAG_RX_CSUM_DISABLED  (1 << 4)
 297
 298 enum e1000_state_t {
 299         __IGB_TESTING,
 300         __IGB_RESETTING,
 301         __IGB_DOWN
 302 };
 303
 304 enum igb_boards {
 305         board_82575,
 306 };
 307
 308 extern char igb_driver_name[];
 309 extern char igb_driver_version[];
 310
 311 extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
 312 extern int igb_up(struct igb_adapter *);
 313 extern void igb_down(struct igb_adapter *);
 314 extern void igb_reinit_locked(struct igb_adapter *);
 315 extern void igb_reset(struct igb_adapter *);
 316 extern int igb_set_spd_dplx(struct igb_adapter *, u16);
 317 extern int igb_setup_tx_resources(struct igb_adapter *, struct igb_ring *);
 318 extern int igb_setup_rx_resources(struct igb_adapter *, struct igb_ring *);
 319 extern void igb_free_tx_resources(struct igb_ring *);
 320 extern void igb_free_rx_resources(struct igb_ring *);
 321 extern void igb_update_stats(struct igb_adapter *);
 322 extern void igb_set_ethtool_ops(struct net_device *);
 323
 324 static inline s32 igb_reset_phy(struct e1000_hw *hw)
 325 {
 326         if (hw->phy.ops.reset)
 327                 return hw->phy.ops.reset(hw);
 328
 329         return 0;
 330 }
 331
 332 static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
 333 {
 334         if (hw->phy.ops.read_reg)
 335                 return hw->phy.ops.read_reg(hw, offset, data);
 336
 337         return 0;
 338 }
 339
 340 static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
 341 {
 342         if (hw->phy.ops.write_reg)
 343                 return hw->phy.ops.write_reg(hw, offset, data);
 344
 345         return 0;
 346 }
 347
 348 static inline s32 igb_get_phy_info(struct e1000_hw *hw)
 349 {
 350         if (hw->phy.ops.get_phy_info)
 351                 return hw->phy.ops.get_phy_info(hw);
 352
 353         return 0;
 354 }
 355
 356 #endif /* _IGB_H_ */