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igb: Power down link when interface is down
[deliverable/linux.git] / drivers / net / igb / igb_ethtool.c
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 /* ethtool support for igb */
29
30 #include <linux/vmalloc.h>
31 #include <linux/netdevice.h>
32 #include <linux/pci.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
35 #include <linux/if_ether.h>
36 #include <linux/ethtool.h>
37 #include <linux/sched.h>
38
39 #include "igb.h"
40
41 struct igb_stats {
42 char stat_string[ETH_GSTRING_LEN];
43 int sizeof_stat;
44 int stat_offset;
45 };
46
47 #define IGB_STAT(_name, _stat) { \
48 .stat_string = _name, \
49 .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \
50 .stat_offset = offsetof(struct igb_adapter, _stat) \
51 }
52 static const struct igb_stats igb_gstrings_stats[] = {
53 IGB_STAT("rx_packets", stats.gprc),
54 IGB_STAT("tx_packets", stats.gptc),
55 IGB_STAT("rx_bytes", stats.gorc),
56 IGB_STAT("tx_bytes", stats.gotc),
57 IGB_STAT("rx_broadcast", stats.bprc),
58 IGB_STAT("tx_broadcast", stats.bptc),
59 IGB_STAT("rx_multicast", stats.mprc),
60 IGB_STAT("tx_multicast", stats.mptc),
61 IGB_STAT("multicast", stats.mprc),
62 IGB_STAT("collisions", stats.colc),
63 IGB_STAT("rx_crc_errors", stats.crcerrs),
64 IGB_STAT("rx_no_buffer_count", stats.rnbc),
65 IGB_STAT("rx_missed_errors", stats.mpc),
66 IGB_STAT("tx_aborted_errors", stats.ecol),
67 IGB_STAT("tx_carrier_errors", stats.tncrs),
68 IGB_STAT("tx_window_errors", stats.latecol),
69 IGB_STAT("tx_abort_late_coll", stats.latecol),
70 IGB_STAT("tx_deferred_ok", stats.dc),
71 IGB_STAT("tx_single_coll_ok", stats.scc),
72 IGB_STAT("tx_multi_coll_ok", stats.mcc),
73 IGB_STAT("tx_timeout_count", tx_timeout_count),
74 IGB_STAT("rx_long_length_errors", stats.roc),
75 IGB_STAT("rx_short_length_errors", stats.ruc),
76 IGB_STAT("rx_align_errors", stats.algnerrc),
77 IGB_STAT("tx_tcp_seg_good", stats.tsctc),
78 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc),
79 IGB_STAT("rx_flow_control_xon", stats.xonrxc),
80 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc),
81 IGB_STAT("tx_flow_control_xon", stats.xontxc),
82 IGB_STAT("tx_flow_control_xoff", stats.xofftxc),
83 IGB_STAT("rx_long_byte_count", stats.gorc),
84 IGB_STAT("tx_dma_out_of_sync", stats.doosync),
85 IGB_STAT("tx_smbus", stats.mgptc),
86 IGB_STAT("rx_smbus", stats.mgprc),
87 IGB_STAT("dropped_smbus", stats.mgpdc),
88 };
89
90 #define IGB_NETDEV_STAT(_net_stat) { \
91 .stat_string = __stringify(_net_stat), \
92 .sizeof_stat = FIELD_SIZEOF(struct net_device_stats, _net_stat), \
93 .stat_offset = offsetof(struct net_device_stats, _net_stat) \
94 }
95 static const struct igb_stats igb_gstrings_net_stats[] = {
96 IGB_NETDEV_STAT(rx_errors),
97 IGB_NETDEV_STAT(tx_errors),
98 IGB_NETDEV_STAT(tx_dropped),
99 IGB_NETDEV_STAT(rx_length_errors),
100 IGB_NETDEV_STAT(rx_over_errors),
101 IGB_NETDEV_STAT(rx_frame_errors),
102 IGB_NETDEV_STAT(rx_fifo_errors),
103 IGB_NETDEV_STAT(tx_fifo_errors),
104 IGB_NETDEV_STAT(tx_heartbeat_errors)
105 };
106
107 #define IGB_GLOBAL_STATS_LEN \
108 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats))
109 #define IGB_NETDEV_STATS_LEN \
110 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats))
111 #define IGB_RX_QUEUE_STATS_LEN \
112 (sizeof(struct igb_rx_queue_stats) / sizeof(u64))
113 #define IGB_TX_QUEUE_STATS_LEN \
114 (sizeof(struct igb_tx_queue_stats) / sizeof(u64))
115 #define IGB_QUEUE_STATS_LEN \
116 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \
117 IGB_RX_QUEUE_STATS_LEN) + \
118 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \
119 IGB_TX_QUEUE_STATS_LEN))
120 #define IGB_STATS_LEN \
121 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN)
122
123 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
124 "Register test (offline)", "Eeprom test (offline)",
125 "Interrupt test (offline)", "Loopback test (offline)",
126 "Link test (on/offline)"
127 };
128 #define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN)
129
130 static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
131 {
132 struct igb_adapter *adapter = netdev_priv(netdev);
133 struct e1000_hw *hw = &adapter->hw;
134 u32 status;
135
136 if (hw->phy.media_type == e1000_media_type_copper) {
137
138 ecmd->supported = (SUPPORTED_10baseT_Half |
139 SUPPORTED_10baseT_Full |
140 SUPPORTED_100baseT_Half |
141 SUPPORTED_100baseT_Full |
142 SUPPORTED_1000baseT_Full|
143 SUPPORTED_Autoneg |
144 SUPPORTED_TP);
145 ecmd->advertising = ADVERTISED_TP;
146
147 if (hw->mac.autoneg == 1) {
148 ecmd->advertising |= ADVERTISED_Autoneg;
149 /* the e1000 autoneg seems to match ethtool nicely */
150 ecmd->advertising |= hw->phy.autoneg_advertised;
151 }
152
153 ecmd->port = PORT_TP;
154 ecmd->phy_address = hw->phy.addr;
155 } else {
156 ecmd->supported = (SUPPORTED_1000baseT_Full |
157 SUPPORTED_FIBRE |
158 SUPPORTED_Autoneg);
159
160 ecmd->advertising = (ADVERTISED_1000baseT_Full |
161 ADVERTISED_FIBRE |
162 ADVERTISED_Autoneg);
163
164 ecmd->port = PORT_FIBRE;
165 }
166
167 ecmd->transceiver = XCVR_INTERNAL;
168
169 status = rd32(E1000_STATUS);
170
171 if (status & E1000_STATUS_LU) {
172
173 if ((status & E1000_STATUS_SPEED_1000) ||
174 hw->phy.media_type != e1000_media_type_copper)
175 ecmd->speed = SPEED_1000;
176 else if (status & E1000_STATUS_SPEED_100)
177 ecmd->speed = SPEED_100;
178 else
179 ecmd->speed = SPEED_10;
180
181 if ((status & E1000_STATUS_FD) ||
182 hw->phy.media_type != e1000_media_type_copper)
183 ecmd->duplex = DUPLEX_FULL;
184 else
185 ecmd->duplex = DUPLEX_HALF;
186 } else {
187 ecmd->speed = -1;
188 ecmd->duplex = -1;
189 }
190
191 ecmd->autoneg = hw->mac.autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
192 return 0;
193 }
194
195 static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
196 {
197 struct igb_adapter *adapter = netdev_priv(netdev);
198 struct e1000_hw *hw = &adapter->hw;
199
200 /* When SoL/IDER sessions are active, autoneg/speed/duplex
201 * cannot be changed */
202 if (igb_check_reset_block(hw)) {
203 dev_err(&adapter->pdev->dev, "Cannot change link "
204 "characteristics when SoL/IDER is active.\n");
205 return -EINVAL;
206 }
207
208 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
209 msleep(1);
210
211 if (ecmd->autoneg == AUTONEG_ENABLE) {
212 hw->mac.autoneg = 1;
213 hw->phy.autoneg_advertised = ecmd->advertising |
214 ADVERTISED_TP |
215 ADVERTISED_Autoneg;
216 ecmd->advertising = hw->phy.autoneg_advertised;
217 if (adapter->fc_autoneg)
218 hw->fc.requested_mode = e1000_fc_default;
219 } else {
220 if (igb_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
221 clear_bit(__IGB_RESETTING, &adapter->state);
222 return -EINVAL;
223 }
224 }
225
226 /* reset the link */
227 if (netif_running(adapter->netdev)) {
228 igb_down(adapter);
229 igb_up(adapter);
230 } else
231 igb_reset(adapter);
232
233 clear_bit(__IGB_RESETTING, &adapter->state);
234 return 0;
235 }
236
237 static u32 igb_get_link(struct net_device *netdev)
238 {
239 struct igb_adapter *adapter = netdev_priv(netdev);
240 struct e1000_mac_info *mac = &adapter->hw.mac;
241
242 /*
243 * If the link is not reported up to netdev, interrupts are disabled,
244 * and so the physical link state may have changed since we last
245 * looked. Set get_link_status to make sure that the true link
246 * state is interrogated, rather than pulling a cached and possibly
247 * stale link state from the driver.
248 */
249 if (!netif_carrier_ok(netdev))
250 mac->get_link_status = 1;
251
252 return igb_has_link(adapter);
253 }
254
255 static void igb_get_pauseparam(struct net_device *netdev,
256 struct ethtool_pauseparam *pause)
257 {
258 struct igb_adapter *adapter = netdev_priv(netdev);
259 struct e1000_hw *hw = &adapter->hw;
260
261 pause->autoneg =
262 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
263
264 if (hw->fc.current_mode == e1000_fc_rx_pause)
265 pause->rx_pause = 1;
266 else if (hw->fc.current_mode == e1000_fc_tx_pause)
267 pause->tx_pause = 1;
268 else if (hw->fc.current_mode == e1000_fc_full) {
269 pause->rx_pause = 1;
270 pause->tx_pause = 1;
271 }
272 }
273
274 static int igb_set_pauseparam(struct net_device *netdev,
275 struct ethtool_pauseparam *pause)
276 {
277 struct igb_adapter *adapter = netdev_priv(netdev);
278 struct e1000_hw *hw = &adapter->hw;
279 int retval = 0;
280
281 adapter->fc_autoneg = pause->autoneg;
282
283 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
284 msleep(1);
285
286 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
287 hw->fc.requested_mode = e1000_fc_default;
288 if (netif_running(adapter->netdev)) {
289 igb_down(adapter);
290 igb_up(adapter);
291 } else {
292 igb_reset(adapter);
293 }
294 } else {
295 if (pause->rx_pause && pause->tx_pause)
296 hw->fc.requested_mode = e1000_fc_full;
297 else if (pause->rx_pause && !pause->tx_pause)
298 hw->fc.requested_mode = e1000_fc_rx_pause;
299 else if (!pause->rx_pause && pause->tx_pause)
300 hw->fc.requested_mode = e1000_fc_tx_pause;
301 else if (!pause->rx_pause && !pause->tx_pause)
302 hw->fc.requested_mode = e1000_fc_none;
303
304 hw->fc.current_mode = hw->fc.requested_mode;
305
306 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
307 igb_force_mac_fc(hw) : igb_setup_link(hw));
308 }
309
310 clear_bit(__IGB_RESETTING, &adapter->state);
311 return retval;
312 }
313
314 static u32 igb_get_rx_csum(struct net_device *netdev)
315 {
316 struct igb_adapter *adapter = netdev_priv(netdev);
317 return !!(adapter->rx_ring[0].flags & IGB_RING_FLAG_RX_CSUM);
318 }
319
320 static int igb_set_rx_csum(struct net_device *netdev, u32 data)
321 {
322 struct igb_adapter *adapter = netdev_priv(netdev);
323 int i;
324
325 for (i = 0; i < adapter->num_rx_queues; i++) {
326 if (data)
327 adapter->rx_ring[i].flags |= IGB_RING_FLAG_RX_CSUM;
328 else
329 adapter->rx_ring[i].flags &= ~IGB_RING_FLAG_RX_CSUM;
330 }
331
332 return 0;
333 }
334
335 static u32 igb_get_tx_csum(struct net_device *netdev)
336 {
337 return (netdev->features & NETIF_F_IP_CSUM) != 0;
338 }
339
340 static int igb_set_tx_csum(struct net_device *netdev, u32 data)
341 {
342 struct igb_adapter *adapter = netdev_priv(netdev);
343
344 if (data) {
345 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
346 if (adapter->hw.mac.type >= e1000_82576)
347 netdev->features |= NETIF_F_SCTP_CSUM;
348 } else {
349 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
350 NETIF_F_SCTP_CSUM);
351 }
352
353 return 0;
354 }
355
356 static int igb_set_tso(struct net_device *netdev, u32 data)
357 {
358 struct igb_adapter *adapter = netdev_priv(netdev);
359
360 if (data) {
361 netdev->features |= NETIF_F_TSO;
362 netdev->features |= NETIF_F_TSO6;
363 } else {
364 netdev->features &= ~NETIF_F_TSO;
365 netdev->features &= ~NETIF_F_TSO6;
366 }
367
368 dev_info(&adapter->pdev->dev, "TSO is %s\n",
369 data ? "Enabled" : "Disabled");
370 return 0;
371 }
372
373 static u32 igb_get_msglevel(struct net_device *netdev)
374 {
375 struct igb_adapter *adapter = netdev_priv(netdev);
376 return adapter->msg_enable;
377 }
378
379 static void igb_set_msglevel(struct net_device *netdev, u32 data)
380 {
381 struct igb_adapter *adapter = netdev_priv(netdev);
382 adapter->msg_enable = data;
383 }
384
385 static int igb_get_regs_len(struct net_device *netdev)
386 {
387 #define IGB_REGS_LEN 551
388 return IGB_REGS_LEN * sizeof(u32);
389 }
390
391 static void igb_get_regs(struct net_device *netdev,
392 struct ethtool_regs *regs, void *p)
393 {
394 struct igb_adapter *adapter = netdev_priv(netdev);
395 struct e1000_hw *hw = &adapter->hw;
396 u32 *regs_buff = p;
397 u8 i;
398
399 memset(p, 0, IGB_REGS_LEN * sizeof(u32));
400
401 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
402
403 /* General Registers */
404 regs_buff[0] = rd32(E1000_CTRL);
405 regs_buff[1] = rd32(E1000_STATUS);
406 regs_buff[2] = rd32(E1000_CTRL_EXT);
407 regs_buff[3] = rd32(E1000_MDIC);
408 regs_buff[4] = rd32(E1000_SCTL);
409 regs_buff[5] = rd32(E1000_CONNSW);
410 regs_buff[6] = rd32(E1000_VET);
411 regs_buff[7] = rd32(E1000_LEDCTL);
412 regs_buff[8] = rd32(E1000_PBA);
413 regs_buff[9] = rd32(E1000_PBS);
414 regs_buff[10] = rd32(E1000_FRTIMER);
415 regs_buff[11] = rd32(E1000_TCPTIMER);
416
417 /* NVM Register */
418 regs_buff[12] = rd32(E1000_EECD);
419
420 /* Interrupt */
421 /* Reading EICS for EICR because they read the
422 * same but EICS does not clear on read */
423 regs_buff[13] = rd32(E1000_EICS);
424 regs_buff[14] = rd32(E1000_EICS);
425 regs_buff[15] = rd32(E1000_EIMS);
426 regs_buff[16] = rd32(E1000_EIMC);
427 regs_buff[17] = rd32(E1000_EIAC);
428 regs_buff[18] = rd32(E1000_EIAM);
429 /* Reading ICS for ICR because they read the
430 * same but ICS does not clear on read */
431 regs_buff[19] = rd32(E1000_ICS);
432 regs_buff[20] = rd32(E1000_ICS);
433 regs_buff[21] = rd32(E1000_IMS);
434 regs_buff[22] = rd32(E1000_IMC);
435 regs_buff[23] = rd32(E1000_IAC);
436 regs_buff[24] = rd32(E1000_IAM);
437 regs_buff[25] = rd32(E1000_IMIRVP);
438
439 /* Flow Control */
440 regs_buff[26] = rd32(E1000_FCAL);
441 regs_buff[27] = rd32(E1000_FCAH);
442 regs_buff[28] = rd32(E1000_FCTTV);
443 regs_buff[29] = rd32(E1000_FCRTL);
444 regs_buff[30] = rd32(E1000_FCRTH);
445 regs_buff[31] = rd32(E1000_FCRTV);
446
447 /* Receive */
448 regs_buff[32] = rd32(E1000_RCTL);
449 regs_buff[33] = rd32(E1000_RXCSUM);
450 regs_buff[34] = rd32(E1000_RLPML);
451 regs_buff[35] = rd32(E1000_RFCTL);
452 regs_buff[36] = rd32(E1000_MRQC);
453 regs_buff[37] = rd32(E1000_VT_CTL);
454
455 /* Transmit */
456 regs_buff[38] = rd32(E1000_TCTL);
457 regs_buff[39] = rd32(E1000_TCTL_EXT);
458 regs_buff[40] = rd32(E1000_TIPG);
459 regs_buff[41] = rd32(E1000_DTXCTL);
460
461 /* Wake Up */
462 regs_buff[42] = rd32(E1000_WUC);
463 regs_buff[43] = rd32(E1000_WUFC);
464 regs_buff[44] = rd32(E1000_WUS);
465 regs_buff[45] = rd32(E1000_IPAV);
466 regs_buff[46] = rd32(E1000_WUPL);
467
468 /* MAC */
469 regs_buff[47] = rd32(E1000_PCS_CFG0);
470 regs_buff[48] = rd32(E1000_PCS_LCTL);
471 regs_buff[49] = rd32(E1000_PCS_LSTAT);
472 regs_buff[50] = rd32(E1000_PCS_ANADV);
473 regs_buff[51] = rd32(E1000_PCS_LPAB);
474 regs_buff[52] = rd32(E1000_PCS_NPTX);
475 regs_buff[53] = rd32(E1000_PCS_LPABNP);
476
477 /* Statistics */
478 regs_buff[54] = adapter->stats.crcerrs;
479 regs_buff[55] = adapter->stats.algnerrc;
480 regs_buff[56] = adapter->stats.symerrs;
481 regs_buff[57] = adapter->stats.rxerrc;
482 regs_buff[58] = adapter->stats.mpc;
483 regs_buff[59] = adapter->stats.scc;
484 regs_buff[60] = adapter->stats.ecol;
485 regs_buff[61] = adapter->stats.mcc;
486 regs_buff[62] = adapter->stats.latecol;
487 regs_buff[63] = adapter->stats.colc;
488 regs_buff[64] = adapter->stats.dc;
489 regs_buff[65] = adapter->stats.tncrs;
490 regs_buff[66] = adapter->stats.sec;
491 regs_buff[67] = adapter->stats.htdpmc;
492 regs_buff[68] = adapter->stats.rlec;
493 regs_buff[69] = adapter->stats.xonrxc;
494 regs_buff[70] = adapter->stats.xontxc;
495 regs_buff[71] = adapter->stats.xoffrxc;
496 regs_buff[72] = adapter->stats.xofftxc;
497 regs_buff[73] = adapter->stats.fcruc;
498 regs_buff[74] = adapter->stats.prc64;
499 regs_buff[75] = adapter->stats.prc127;
500 regs_buff[76] = adapter->stats.prc255;
501 regs_buff[77] = adapter->stats.prc511;
502 regs_buff[78] = adapter->stats.prc1023;
503 regs_buff[79] = adapter->stats.prc1522;
504 regs_buff[80] = adapter->stats.gprc;
505 regs_buff[81] = adapter->stats.bprc;
506 regs_buff[82] = adapter->stats.mprc;
507 regs_buff[83] = adapter->stats.gptc;
508 regs_buff[84] = adapter->stats.gorc;
509 regs_buff[86] = adapter->stats.gotc;
510 regs_buff[88] = adapter->stats.rnbc;
511 regs_buff[89] = adapter->stats.ruc;
512 regs_buff[90] = adapter->stats.rfc;
513 regs_buff[91] = adapter->stats.roc;
514 regs_buff[92] = adapter->stats.rjc;
515 regs_buff[93] = adapter->stats.mgprc;
516 regs_buff[94] = adapter->stats.mgpdc;
517 regs_buff[95] = adapter->stats.mgptc;
518 regs_buff[96] = adapter->stats.tor;
519 regs_buff[98] = adapter->stats.tot;
520 regs_buff[100] = adapter->stats.tpr;
521 regs_buff[101] = adapter->stats.tpt;
522 regs_buff[102] = adapter->stats.ptc64;
523 regs_buff[103] = adapter->stats.ptc127;
524 regs_buff[104] = adapter->stats.ptc255;
525 regs_buff[105] = adapter->stats.ptc511;
526 regs_buff[106] = adapter->stats.ptc1023;
527 regs_buff[107] = adapter->stats.ptc1522;
528 regs_buff[108] = adapter->stats.mptc;
529 regs_buff[109] = adapter->stats.bptc;
530 regs_buff[110] = adapter->stats.tsctc;
531 regs_buff[111] = adapter->stats.iac;
532 regs_buff[112] = adapter->stats.rpthc;
533 regs_buff[113] = adapter->stats.hgptc;
534 regs_buff[114] = adapter->stats.hgorc;
535 regs_buff[116] = adapter->stats.hgotc;
536 regs_buff[118] = adapter->stats.lenerrs;
537 regs_buff[119] = adapter->stats.scvpc;
538 regs_buff[120] = adapter->stats.hrmpc;
539
540 for (i = 0; i < 4; i++)
541 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
542 for (i = 0; i < 4; i++)
543 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i));
544 for (i = 0; i < 4; i++)
545 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
546 for (i = 0; i < 4; i++)
547 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
548 for (i = 0; i < 4; i++)
549 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
550 for (i = 0; i < 4; i++)
551 regs_buff[141 + i] = rd32(E1000_RDH(i));
552 for (i = 0; i < 4; i++)
553 regs_buff[145 + i] = rd32(E1000_RDT(i));
554 for (i = 0; i < 4; i++)
555 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
556
557 for (i = 0; i < 10; i++)
558 regs_buff[153 + i] = rd32(E1000_EITR(i));
559 for (i = 0; i < 8; i++)
560 regs_buff[163 + i] = rd32(E1000_IMIR(i));
561 for (i = 0; i < 8; i++)
562 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
563 for (i = 0; i < 16; i++)
564 regs_buff[179 + i] = rd32(E1000_RAL(i));
565 for (i = 0; i < 16; i++)
566 regs_buff[195 + i] = rd32(E1000_RAH(i));
567
568 for (i = 0; i < 4; i++)
569 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
570 for (i = 0; i < 4; i++)
571 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
572 for (i = 0; i < 4; i++)
573 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
574 for (i = 0; i < 4; i++)
575 regs_buff[223 + i] = rd32(E1000_TDH(i));
576 for (i = 0; i < 4; i++)
577 regs_buff[227 + i] = rd32(E1000_TDT(i));
578 for (i = 0; i < 4; i++)
579 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
580 for (i = 0; i < 4; i++)
581 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
582 for (i = 0; i < 4; i++)
583 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
584 for (i = 0; i < 4; i++)
585 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
586
587 for (i = 0; i < 4; i++)
588 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
589 for (i = 0; i < 4; i++)
590 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
591 for (i = 0; i < 32; i++)
592 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
593 for (i = 0; i < 128; i++)
594 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
595 for (i = 0; i < 128; i++)
596 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
597 for (i = 0; i < 4; i++)
598 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
599
600 regs_buff[547] = rd32(E1000_TDFH);
601 regs_buff[548] = rd32(E1000_TDFT);
602 regs_buff[549] = rd32(E1000_TDFHS);
603 regs_buff[550] = rd32(E1000_TDFPC);
604
605 }
606
607 static int igb_get_eeprom_len(struct net_device *netdev)
608 {
609 struct igb_adapter *adapter = netdev_priv(netdev);
610 return adapter->hw.nvm.word_size * 2;
611 }
612
613 static int igb_get_eeprom(struct net_device *netdev,
614 struct ethtool_eeprom *eeprom, u8 *bytes)
615 {
616 struct igb_adapter *adapter = netdev_priv(netdev);
617 struct e1000_hw *hw = &adapter->hw;
618 u16 *eeprom_buff;
619 int first_word, last_word;
620 int ret_val = 0;
621 u16 i;
622
623 if (eeprom->len == 0)
624 return -EINVAL;
625
626 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
627
628 first_word = eeprom->offset >> 1;
629 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
630
631 eeprom_buff = kmalloc(sizeof(u16) *
632 (last_word - first_word + 1), GFP_KERNEL);
633 if (!eeprom_buff)
634 return -ENOMEM;
635
636 if (hw->nvm.type == e1000_nvm_eeprom_spi)
637 ret_val = hw->nvm.ops.read(hw, first_word,
638 last_word - first_word + 1,
639 eeprom_buff);
640 else {
641 for (i = 0; i < last_word - first_word + 1; i++) {
642 ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
643 &eeprom_buff[i]);
644 if (ret_val)
645 break;
646 }
647 }
648
649 /* Device's eeprom is always little-endian, word addressable */
650 for (i = 0; i < last_word - first_word + 1; i++)
651 le16_to_cpus(&eeprom_buff[i]);
652
653 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
654 eeprom->len);
655 kfree(eeprom_buff);
656
657 return ret_val;
658 }
659
660 static int igb_set_eeprom(struct net_device *netdev,
661 struct ethtool_eeprom *eeprom, u8 *bytes)
662 {
663 struct igb_adapter *adapter = netdev_priv(netdev);
664 struct e1000_hw *hw = &adapter->hw;
665 u16 *eeprom_buff;
666 void *ptr;
667 int max_len, first_word, last_word, ret_val = 0;
668 u16 i;
669
670 if (eeprom->len == 0)
671 return -EOPNOTSUPP;
672
673 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
674 return -EFAULT;
675
676 max_len = hw->nvm.word_size * 2;
677
678 first_word = eeprom->offset >> 1;
679 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
680 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
681 if (!eeprom_buff)
682 return -ENOMEM;
683
684 ptr = (void *)eeprom_buff;
685
686 if (eeprom->offset & 1) {
687 /* need read/modify/write of first changed EEPROM word */
688 /* only the second byte of the word is being modified */
689 ret_val = hw->nvm.ops.read(hw, first_word, 1,
690 &eeprom_buff[0]);
691 ptr++;
692 }
693 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
694 /* need read/modify/write of last changed EEPROM word */
695 /* only the first byte of the word is being modified */
696 ret_val = hw->nvm.ops.read(hw, last_word, 1,
697 &eeprom_buff[last_word - first_word]);
698 }
699
700 /* Device's eeprom is always little-endian, word addressable */
701 for (i = 0; i < last_word - first_word + 1; i++)
702 le16_to_cpus(&eeprom_buff[i]);
703
704 memcpy(ptr, bytes, eeprom->len);
705
706 for (i = 0; i < last_word - first_word + 1; i++)
707 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
708
709 ret_val = hw->nvm.ops.write(hw, first_word,
710 last_word - first_word + 1, eeprom_buff);
711
712 /* Update the checksum over the first part of the EEPROM if needed
713 * and flush shadow RAM for 82573 controllers */
714 if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
715 igb_update_nvm_checksum(hw);
716
717 kfree(eeprom_buff);
718 return ret_val;
719 }
720
721 static void igb_get_drvinfo(struct net_device *netdev,
722 struct ethtool_drvinfo *drvinfo)
723 {
724 struct igb_adapter *adapter = netdev_priv(netdev);
725 char firmware_version[32];
726 u16 eeprom_data;
727
728 strncpy(drvinfo->driver, igb_driver_name, 32);
729 strncpy(drvinfo->version, igb_driver_version, 32);
730
731 /* EEPROM image version # is reported as firmware version # for
732 * 82575 controllers */
733 adapter->hw.nvm.ops.read(&adapter->hw, 5, 1, &eeprom_data);
734 sprintf(firmware_version, "%d.%d-%d",
735 (eeprom_data & 0xF000) >> 12,
736 (eeprom_data & 0x0FF0) >> 4,
737 eeprom_data & 0x000F);
738
739 strncpy(drvinfo->fw_version, firmware_version, 32);
740 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
741 drvinfo->n_stats = IGB_STATS_LEN;
742 drvinfo->testinfo_len = IGB_TEST_LEN;
743 drvinfo->regdump_len = igb_get_regs_len(netdev);
744 drvinfo->eedump_len = igb_get_eeprom_len(netdev);
745 }
746
747 static void igb_get_ringparam(struct net_device *netdev,
748 struct ethtool_ringparam *ring)
749 {
750 struct igb_adapter *adapter = netdev_priv(netdev);
751
752 ring->rx_max_pending = IGB_MAX_RXD;
753 ring->tx_max_pending = IGB_MAX_TXD;
754 ring->rx_mini_max_pending = 0;
755 ring->rx_jumbo_max_pending = 0;
756 ring->rx_pending = adapter->rx_ring_count;
757 ring->tx_pending = adapter->tx_ring_count;
758 ring->rx_mini_pending = 0;
759 ring->rx_jumbo_pending = 0;
760 }
761
762 static int igb_set_ringparam(struct net_device *netdev,
763 struct ethtool_ringparam *ring)
764 {
765 struct igb_adapter *adapter = netdev_priv(netdev);
766 struct igb_ring *temp_ring;
767 int i, err = 0;
768 u16 new_rx_count, new_tx_count;
769
770 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
771 return -EINVAL;
772
773 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD);
774 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD);
775 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
776
777 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD);
778 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD);
779 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
780
781 if ((new_tx_count == adapter->tx_ring_count) &&
782 (new_rx_count == adapter->rx_ring_count)) {
783 /* nothing to do */
784 return 0;
785 }
786
787 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
788 msleep(1);
789
790 if (!netif_running(adapter->netdev)) {
791 for (i = 0; i < adapter->num_tx_queues; i++)
792 adapter->tx_ring[i].count = new_tx_count;
793 for (i = 0; i < adapter->num_rx_queues; i++)
794 adapter->rx_ring[i].count = new_rx_count;
795 adapter->tx_ring_count = new_tx_count;
796 adapter->rx_ring_count = new_rx_count;
797 goto clear_reset;
798 }
799
800 if (adapter->num_tx_queues > adapter->num_rx_queues)
801 temp_ring = vmalloc(adapter->num_tx_queues * sizeof(struct igb_ring));
802 else
803 temp_ring = vmalloc(adapter->num_rx_queues * sizeof(struct igb_ring));
804
805 if (!temp_ring) {
806 err = -ENOMEM;
807 goto clear_reset;
808 }
809
810 igb_down(adapter);
811
812 /*
813 * We can't just free everything and then setup again,
814 * because the ISRs in MSI-X mode get passed pointers
815 * to the tx and rx ring structs.
816 */
817 if (new_tx_count != adapter->tx_ring_count) {
818 memcpy(temp_ring, adapter->tx_ring,
819 adapter->num_tx_queues * sizeof(struct igb_ring));
820
821 for (i = 0; i < adapter->num_tx_queues; i++) {
822 temp_ring[i].count = new_tx_count;
823 err = igb_setup_tx_resources(&temp_ring[i]);
824 if (err) {
825 while (i) {
826 i--;
827 igb_free_tx_resources(&temp_ring[i]);
828 }
829 goto err_setup;
830 }
831 }
832
833 for (i = 0; i < adapter->num_tx_queues; i++)
834 igb_free_tx_resources(&adapter->tx_ring[i]);
835
836 memcpy(adapter->tx_ring, temp_ring,
837 adapter->num_tx_queues * sizeof(struct igb_ring));
838
839 adapter->tx_ring_count = new_tx_count;
840 }
841
842 if (new_rx_count != adapter->rx_ring->count) {
843 memcpy(temp_ring, adapter->rx_ring,
844 adapter->num_rx_queues * sizeof(struct igb_ring));
845
846 for (i = 0; i < adapter->num_rx_queues; i++) {
847 temp_ring[i].count = new_rx_count;
848 err = igb_setup_rx_resources(&temp_ring[i]);
849 if (err) {
850 while (i) {
851 i--;
852 igb_free_rx_resources(&temp_ring[i]);
853 }
854 goto err_setup;
855 }
856
857 }
858
859 for (i = 0; i < adapter->num_rx_queues; i++)
860 igb_free_rx_resources(&adapter->rx_ring[i]);
861
862 memcpy(adapter->rx_ring, temp_ring,
863 adapter->num_rx_queues * sizeof(struct igb_ring));
864
865 adapter->rx_ring_count = new_rx_count;
866 }
867 err_setup:
868 igb_up(adapter);
869 vfree(temp_ring);
870 clear_reset:
871 clear_bit(__IGB_RESETTING, &adapter->state);
872 return err;
873 }
874
875 /* ethtool register test data */
876 struct igb_reg_test {
877 u16 reg;
878 u16 reg_offset;
879 u16 array_len;
880 u16 test_type;
881 u32 mask;
882 u32 write;
883 };
884
885 /* In the hardware, registers are laid out either singly, in arrays
886 * spaced 0x100 bytes apart, or in contiguous tables. We assume
887 * most tests take place on arrays or single registers (handled
888 * as a single-element array) and special-case the tables.
889 * Table tests are always pattern tests.
890 *
891 * We also make provision for some required setup steps by specifying
892 * registers to be written without any read-back testing.
893 */
894
895 #define PATTERN_TEST 1
896 #define SET_READ_TEST 2
897 #define WRITE_NO_TEST 3
898 #define TABLE32_TEST 4
899 #define TABLE64_TEST_LO 5
900 #define TABLE64_TEST_HI 6
901
902 /* 82580 reg test */
903 static struct igb_reg_test reg_test_82580[] = {
904 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
905 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
906 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
907 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
908 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
909 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
910 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
911 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
912 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
913 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
914 /* RDH is read-only for 82580, only test RDT. */
915 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
916 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
917 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
918 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
919 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
920 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
921 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
922 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
923 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
924 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
925 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
926 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
927 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
928 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
929 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
930 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
931 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
932 { E1000_RA, 0, 16, TABLE64_TEST_LO,
933 0xFFFFFFFF, 0xFFFFFFFF },
934 { E1000_RA, 0, 16, TABLE64_TEST_HI,
935 0x83FFFFFF, 0xFFFFFFFF },
936 { E1000_RA2, 0, 8, TABLE64_TEST_LO,
937 0xFFFFFFFF, 0xFFFFFFFF },
938 { E1000_RA2, 0, 8, TABLE64_TEST_HI,
939 0x83FFFFFF, 0xFFFFFFFF },
940 { E1000_MTA, 0, 128, TABLE32_TEST,
941 0xFFFFFFFF, 0xFFFFFFFF },
942 { 0, 0, 0, 0 }
943 };
944
945 /* 82576 reg test */
946 static struct igb_reg_test reg_test_82576[] = {
947 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
948 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
949 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
950 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
951 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
952 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
953 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
954 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
955 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
956 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
957 /* Enable all RX queues before testing. */
958 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
959 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
960 /* RDH is read-only for 82576, only test RDT. */
961 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
962 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
963 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
964 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 },
965 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
966 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
967 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
968 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
969 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
970 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
971 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
972 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
973 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
974 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
975 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
976 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
977 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
978 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
979 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
980 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
981 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
982 { E1000_MTA, 0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
983 { 0, 0, 0, 0 }
984 };
985
986 /* 82575 register test */
987 static struct igb_reg_test reg_test_82575[] = {
988 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
989 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
990 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
991 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
992 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
993 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
994 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
995 /* Enable all four RX queues before testing. */
996 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
997 /* RDH is read-only for 82575, only test RDT. */
998 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
999 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1000 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1001 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1002 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1003 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1004 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1005 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1006 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1007 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
1008 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
1009 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1010 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
1011 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1012 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
1013 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1014 { 0, 0, 0, 0 }
1015 };
1016
1017 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
1018 int reg, u32 mask, u32 write)
1019 {
1020 struct e1000_hw *hw = &adapter->hw;
1021 u32 pat, val;
1022 static const u32 _test[] =
1023 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1024 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
1025 wr32(reg, (_test[pat] & write));
1026 val = rd32(reg);
1027 if (val != (_test[pat] & write & mask)) {
1028 dev_err(&adapter->pdev->dev, "pattern test reg %04X "
1029 "failed: got 0x%08X expected 0x%08X\n",
1030 reg, val, (_test[pat] & write & mask));
1031 *data = reg;
1032 return 1;
1033 }
1034 }
1035
1036 return 0;
1037 }
1038
1039 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
1040 int reg, u32 mask, u32 write)
1041 {
1042 struct e1000_hw *hw = &adapter->hw;
1043 u32 val;
1044 wr32(reg, write & mask);
1045 val = rd32(reg);
1046 if ((write & mask) != (val & mask)) {
1047 dev_err(&adapter->pdev->dev, "set/check reg %04X test failed:"
1048 " got 0x%08X expected 0x%08X\n", reg,
1049 (val & mask), (write & mask));
1050 *data = reg;
1051 return 1;
1052 }
1053
1054 return 0;
1055 }
1056
1057 #define REG_PATTERN_TEST(reg, mask, write) \
1058 do { \
1059 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1060 return 1; \
1061 } while (0)
1062
1063 #define REG_SET_AND_CHECK(reg, mask, write) \
1064 do { \
1065 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1066 return 1; \
1067 } while (0)
1068
1069 static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
1070 {
1071 struct e1000_hw *hw = &adapter->hw;
1072 struct igb_reg_test *test;
1073 u32 value, before, after;
1074 u32 i, toggle;
1075
1076 switch (adapter->hw.mac.type) {
1077 case e1000_82580:
1078 test = reg_test_82580;
1079 toggle = 0x7FEFF3FF;
1080 break;
1081 case e1000_82576:
1082 test = reg_test_82576;
1083 toggle = 0x7FFFF3FF;
1084 break;
1085 default:
1086 test = reg_test_82575;
1087 toggle = 0x7FFFF3FF;
1088 break;
1089 }
1090
1091 /* Because the status register is such a special case,
1092 * we handle it separately from the rest of the register
1093 * tests. Some bits are read-only, some toggle, and some
1094 * are writable on newer MACs.
1095 */
1096 before = rd32(E1000_STATUS);
1097 value = (rd32(E1000_STATUS) & toggle);
1098 wr32(E1000_STATUS, toggle);
1099 after = rd32(E1000_STATUS) & toggle;
1100 if (value != after) {
1101 dev_err(&adapter->pdev->dev, "failed STATUS register test "
1102 "got: 0x%08X expected: 0x%08X\n", after, value);
1103 *data = 1;
1104 return 1;
1105 }
1106 /* restore previous status */
1107 wr32(E1000_STATUS, before);
1108
1109 /* Perform the remainder of the register test, looping through
1110 * the test table until we either fail or reach the null entry.
1111 */
1112 while (test->reg) {
1113 for (i = 0; i < test->array_len; i++) {
1114 switch (test->test_type) {
1115 case PATTERN_TEST:
1116 REG_PATTERN_TEST(test->reg +
1117 (i * test->reg_offset),
1118 test->mask,
1119 test->write);
1120 break;
1121 case SET_READ_TEST:
1122 REG_SET_AND_CHECK(test->reg +
1123 (i * test->reg_offset),
1124 test->mask,
1125 test->write);
1126 break;
1127 case WRITE_NO_TEST:
1128 writel(test->write,
1129 (adapter->hw.hw_addr + test->reg)
1130 + (i * test->reg_offset));
1131 break;
1132 case TABLE32_TEST:
1133 REG_PATTERN_TEST(test->reg + (i * 4),
1134 test->mask,
1135 test->write);
1136 break;
1137 case TABLE64_TEST_LO:
1138 REG_PATTERN_TEST(test->reg + (i * 8),
1139 test->mask,
1140 test->write);
1141 break;
1142 case TABLE64_TEST_HI:
1143 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1144 test->mask,
1145 test->write);
1146 break;
1147 }
1148 }
1149 test++;
1150 }
1151
1152 *data = 0;
1153 return 0;
1154 }
1155
1156 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1157 {
1158 u16 temp;
1159 u16 checksum = 0;
1160 u16 i;
1161
1162 *data = 0;
1163 /* Read and add up the contents of the EEPROM */
1164 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1165 if ((adapter->hw.nvm.ops.read(&adapter->hw, i, 1, &temp)) < 0) {
1166 *data = 1;
1167 break;
1168 }
1169 checksum += temp;
1170 }
1171
1172 /* If Checksum is not Correct return error else test passed */
1173 if ((checksum != (u16) NVM_SUM) && !(*data))
1174 *data = 2;
1175
1176 return *data;
1177 }
1178
1179 static irqreturn_t igb_test_intr(int irq, void *data)
1180 {
1181 struct igb_adapter *adapter = (struct igb_adapter *) data;
1182 struct e1000_hw *hw = &adapter->hw;
1183
1184 adapter->test_icr |= rd32(E1000_ICR);
1185
1186 return IRQ_HANDLED;
1187 }
1188
1189 static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1190 {
1191 struct e1000_hw *hw = &adapter->hw;
1192 struct net_device *netdev = adapter->netdev;
1193 u32 mask, ics_mask, i = 0, shared_int = true;
1194 u32 irq = adapter->pdev->irq;
1195
1196 *data = 0;
1197
1198 /* Hook up test interrupt handler just for this test */
1199 if (adapter->msix_entries) {
1200 if (request_irq(adapter->msix_entries[0].vector,
1201 igb_test_intr, 0, netdev->name, adapter)) {
1202 *data = 1;
1203 return -1;
1204 }
1205 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
1206 shared_int = false;
1207 if (request_irq(irq,
1208 igb_test_intr, 0, netdev->name, adapter)) {
1209 *data = 1;
1210 return -1;
1211 }
1212 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED,
1213 netdev->name, adapter)) {
1214 shared_int = false;
1215 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED,
1216 netdev->name, adapter)) {
1217 *data = 1;
1218 return -1;
1219 }
1220 dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1221 (shared_int ? "shared" : "unshared"));
1222
1223 /* Disable all the interrupts */
1224 wr32(E1000_IMC, ~0);
1225 msleep(10);
1226
1227 /* Define all writable bits for ICS */
1228 switch (hw->mac.type) {
1229 case e1000_82575:
1230 ics_mask = 0x37F47EDD;
1231 break;
1232 case e1000_82576:
1233 ics_mask = 0x77D4FBFD;
1234 break;
1235 case e1000_82580:
1236 ics_mask = 0x77DCFED5;
1237 break;
1238 default:
1239 ics_mask = 0x7FFFFFFF;
1240 break;
1241 }
1242
1243 /* Test each interrupt */
1244 for (; i < 31; i++) {
1245 /* Interrupt to test */
1246 mask = 1 << i;
1247
1248 if (!(mask & ics_mask))
1249 continue;
1250
1251 if (!shared_int) {
1252 /* Disable the interrupt to be reported in
1253 * the cause register and then force the same
1254 * interrupt and see if one gets posted. If
1255 * an interrupt was posted to the bus, the
1256 * test failed.
1257 */
1258 adapter->test_icr = 0;
1259
1260 /* Flush any pending interrupts */
1261 wr32(E1000_ICR, ~0);
1262
1263 wr32(E1000_IMC, mask);
1264 wr32(E1000_ICS, mask);
1265 msleep(10);
1266
1267 if (adapter->test_icr & mask) {
1268 *data = 3;
1269 break;
1270 }
1271 }
1272
1273 /* Enable the interrupt to be reported in
1274 * the cause register and then force the same
1275 * interrupt and see if one gets posted. If
1276 * an interrupt was not posted to the bus, the
1277 * test failed.
1278 */
1279 adapter->test_icr = 0;
1280
1281 /* Flush any pending interrupts */
1282 wr32(E1000_ICR, ~0);
1283
1284 wr32(E1000_IMS, mask);
1285 wr32(E1000_ICS, mask);
1286 msleep(10);
1287
1288 if (!(adapter->test_icr & mask)) {
1289 *data = 4;
1290 break;
1291 }
1292
1293 if (!shared_int) {
1294 /* Disable the other interrupts to be reported in
1295 * the cause register and then force the other
1296 * interrupts and see if any get posted. If
1297 * an interrupt was posted to the bus, the
1298 * test failed.
1299 */
1300 adapter->test_icr = 0;
1301
1302 /* Flush any pending interrupts */
1303 wr32(E1000_ICR, ~0);
1304
1305 wr32(E1000_IMC, ~mask);
1306 wr32(E1000_ICS, ~mask);
1307 msleep(10);
1308
1309 if (adapter->test_icr & mask) {
1310 *data = 5;
1311 break;
1312 }
1313 }
1314 }
1315
1316 /* Disable all the interrupts */
1317 wr32(E1000_IMC, ~0);
1318 msleep(10);
1319
1320 /* Unhook test interrupt handler */
1321 if (adapter->msix_entries)
1322 free_irq(adapter->msix_entries[0].vector, adapter);
1323 else
1324 free_irq(irq, adapter);
1325
1326 return *data;
1327 }
1328
1329 static void igb_free_desc_rings(struct igb_adapter *adapter)
1330 {
1331 igb_free_tx_resources(&adapter->test_tx_ring);
1332 igb_free_rx_resources(&adapter->test_rx_ring);
1333 }
1334
1335 static int igb_setup_desc_rings(struct igb_adapter *adapter)
1336 {
1337 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1338 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1339 struct e1000_hw *hw = &adapter->hw;
1340 int ret_val;
1341
1342 /* Setup Tx descriptor ring and Tx buffers */
1343 tx_ring->count = IGB_DEFAULT_TXD;
1344 tx_ring->pdev = adapter->pdev;
1345 tx_ring->netdev = adapter->netdev;
1346 tx_ring->reg_idx = adapter->vfs_allocated_count;
1347
1348 if (igb_setup_tx_resources(tx_ring)) {
1349 ret_val = 1;
1350 goto err_nomem;
1351 }
1352
1353 igb_setup_tctl(adapter);
1354 igb_configure_tx_ring(adapter, tx_ring);
1355
1356 /* Setup Rx descriptor ring and Rx buffers */
1357 rx_ring->count = IGB_DEFAULT_RXD;
1358 rx_ring->pdev = adapter->pdev;
1359 rx_ring->netdev = adapter->netdev;
1360 rx_ring->rx_buffer_len = IGB_RXBUFFER_2048;
1361 rx_ring->reg_idx = adapter->vfs_allocated_count;
1362
1363 if (igb_setup_rx_resources(rx_ring)) {
1364 ret_val = 3;
1365 goto err_nomem;
1366 }
1367
1368 /* set the default queue to queue 0 of PF */
1369 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3);
1370
1371 /* enable receive ring */
1372 igb_setup_rctl(adapter);
1373 igb_configure_rx_ring(adapter, rx_ring);
1374
1375 igb_alloc_rx_buffers_adv(rx_ring, igb_desc_unused(rx_ring));
1376
1377 return 0;
1378
1379 err_nomem:
1380 igb_free_desc_rings(adapter);
1381 return ret_val;
1382 }
1383
1384 static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1385 {
1386 struct e1000_hw *hw = &adapter->hw;
1387
1388 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1389 igb_write_phy_reg(hw, 29, 0x001F);
1390 igb_write_phy_reg(hw, 30, 0x8FFC);
1391 igb_write_phy_reg(hw, 29, 0x001A);
1392 igb_write_phy_reg(hw, 30, 0x8FF0);
1393 }
1394
1395 static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1396 {
1397 struct e1000_hw *hw = &adapter->hw;
1398 u32 ctrl_reg = 0;
1399
1400 hw->mac.autoneg = false;
1401
1402 if (hw->phy.type == e1000_phy_m88) {
1403 /* Auto-MDI/MDIX Off */
1404 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1405 /* reset to update Auto-MDI/MDIX */
1406 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1407 /* autoneg off */
1408 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1409 } else if (hw->phy.type == e1000_phy_82580) {
1410 /* enable MII loopback */
1411 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041);
1412 }
1413
1414 ctrl_reg = rd32(E1000_CTRL);
1415
1416 /* force 1000, set loopback */
1417 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1418
1419 /* Now set up the MAC to the same speed/duplex as the PHY. */
1420 ctrl_reg = rd32(E1000_CTRL);
1421 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1422 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1423 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1424 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1425 E1000_CTRL_FD | /* Force Duplex to FULL */
1426 E1000_CTRL_SLU); /* Set link up enable bit */
1427
1428 if (hw->phy.type == e1000_phy_m88)
1429 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1430
1431 wr32(E1000_CTRL, ctrl_reg);
1432
1433 /* Disable the receiver on the PHY so when a cable is plugged in, the
1434 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1435 */
1436 if (hw->phy.type == e1000_phy_m88)
1437 igb_phy_disable_receiver(adapter);
1438
1439 udelay(500);
1440
1441 return 0;
1442 }
1443
1444 static int igb_set_phy_loopback(struct igb_adapter *adapter)
1445 {
1446 return igb_integrated_phy_loopback(adapter);
1447 }
1448
1449 static int igb_setup_loopback_test(struct igb_adapter *adapter)
1450 {
1451 struct e1000_hw *hw = &adapter->hw;
1452 u32 reg;
1453
1454 reg = rd32(E1000_CTRL_EXT);
1455
1456 /* use CTRL_EXT to identify link type as SGMII can appear as copper */
1457 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) {
1458 reg = rd32(E1000_RCTL);
1459 reg |= E1000_RCTL_LBM_TCVR;
1460 wr32(E1000_RCTL, reg);
1461
1462 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1463
1464 reg = rd32(E1000_CTRL);
1465 reg &= ~(E1000_CTRL_RFCE |
1466 E1000_CTRL_TFCE |
1467 E1000_CTRL_LRST);
1468 reg |= E1000_CTRL_SLU |
1469 E1000_CTRL_FD;
1470 wr32(E1000_CTRL, reg);
1471
1472 /* Unset switch control to serdes energy detect */
1473 reg = rd32(E1000_CONNSW);
1474 reg &= ~E1000_CONNSW_ENRGSRC;
1475 wr32(E1000_CONNSW, reg);
1476
1477 /* Set PCS register for forced speed */
1478 reg = rd32(E1000_PCS_LCTL);
1479 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/
1480 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1481 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1482 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1483 E1000_PCS_LCTL_FSD | /* Force Speed */
1484 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1485 wr32(E1000_PCS_LCTL, reg);
1486
1487 return 0;
1488 }
1489
1490 return igb_set_phy_loopback(adapter);
1491 }
1492
1493 static void igb_loopback_cleanup(struct igb_adapter *adapter)
1494 {
1495 struct e1000_hw *hw = &adapter->hw;
1496 u32 rctl;
1497 u16 phy_reg;
1498
1499 rctl = rd32(E1000_RCTL);
1500 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1501 wr32(E1000_RCTL, rctl);
1502
1503 hw->mac.autoneg = true;
1504 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
1505 if (phy_reg & MII_CR_LOOPBACK) {
1506 phy_reg &= ~MII_CR_LOOPBACK;
1507 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
1508 igb_phy_sw_reset(hw);
1509 }
1510 }
1511
1512 static void igb_create_lbtest_frame(struct sk_buff *skb,
1513 unsigned int frame_size)
1514 {
1515 memset(skb->data, 0xFF, frame_size);
1516 frame_size /= 2;
1517 memset(&skb->data[frame_size], 0xAA, frame_size - 1);
1518 memset(&skb->data[frame_size + 10], 0xBE, 1);
1519 memset(&skb->data[frame_size + 12], 0xAF, 1);
1520 }
1521
1522 static int igb_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
1523 {
1524 frame_size /= 2;
1525 if (*(skb->data + 3) == 0xFF) {
1526 if ((*(skb->data + frame_size + 10) == 0xBE) &&
1527 (*(skb->data + frame_size + 12) == 0xAF)) {
1528 return 0;
1529 }
1530 }
1531 return 13;
1532 }
1533
1534 static int igb_clean_test_rings(struct igb_ring *rx_ring,
1535 struct igb_ring *tx_ring,
1536 unsigned int size)
1537 {
1538 union e1000_adv_rx_desc *rx_desc;
1539 struct igb_buffer *buffer_info;
1540 int rx_ntc, tx_ntc, count = 0;
1541 u32 staterr;
1542
1543 /* initialize next to clean and descriptor values */
1544 rx_ntc = rx_ring->next_to_clean;
1545 tx_ntc = tx_ring->next_to_clean;
1546 rx_desc = E1000_RX_DESC_ADV(*rx_ring, rx_ntc);
1547 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1548
1549 while (staterr & E1000_RXD_STAT_DD) {
1550 /* check rx buffer */
1551 buffer_info = &rx_ring->buffer_info[rx_ntc];
1552
1553 /* unmap rx buffer, will be remapped by alloc_rx_buffers */
1554 pci_unmap_single(rx_ring->pdev,
1555 buffer_info->dma,
1556 rx_ring->rx_buffer_len,
1557 PCI_DMA_FROMDEVICE);
1558 buffer_info->dma = 0;
1559
1560 /* verify contents of skb */
1561 if (!igb_check_lbtest_frame(buffer_info->skb, size))
1562 count++;
1563
1564 /* unmap buffer on tx side */
1565 buffer_info = &tx_ring->buffer_info[tx_ntc];
1566 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
1567
1568 /* increment rx/tx next to clean counters */
1569 rx_ntc++;
1570 if (rx_ntc == rx_ring->count)
1571 rx_ntc = 0;
1572 tx_ntc++;
1573 if (tx_ntc == tx_ring->count)
1574 tx_ntc = 0;
1575
1576 /* fetch next descriptor */
1577 rx_desc = E1000_RX_DESC_ADV(*rx_ring, rx_ntc);
1578 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1579 }
1580
1581 /* re-map buffers to ring, store next to clean values */
1582 igb_alloc_rx_buffers_adv(rx_ring, count);
1583 rx_ring->next_to_clean = rx_ntc;
1584 tx_ring->next_to_clean = tx_ntc;
1585
1586 return count;
1587 }
1588
1589 static int igb_run_loopback_test(struct igb_adapter *adapter)
1590 {
1591 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1592 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1593 int i, j, lc, good_cnt, ret_val = 0;
1594 unsigned int size = 1024;
1595 netdev_tx_t tx_ret_val;
1596 struct sk_buff *skb;
1597
1598 /* allocate test skb */
1599 skb = alloc_skb(size, GFP_KERNEL);
1600 if (!skb)
1601 return 11;
1602
1603 /* place data into test skb */
1604 igb_create_lbtest_frame(skb, size);
1605 skb_put(skb, size);
1606
1607 /*
1608 * Calculate the loop count based on the largest descriptor ring
1609 * The idea is to wrap the largest ring a number of times using 64
1610 * send/receive pairs during each loop
1611 */
1612
1613 if (rx_ring->count <= tx_ring->count)
1614 lc = ((tx_ring->count / 64) * 2) + 1;
1615 else
1616 lc = ((rx_ring->count / 64) * 2) + 1;
1617
1618 for (j = 0; j <= lc; j++) { /* loop count loop */
1619 /* reset count of good packets */
1620 good_cnt = 0;
1621
1622 /* place 64 packets on the transmit queue*/
1623 for (i = 0; i < 64; i++) {
1624 skb_get(skb);
1625 tx_ret_val = igb_xmit_frame_ring_adv(skb, tx_ring);
1626 if (tx_ret_val == NETDEV_TX_OK)
1627 good_cnt++;
1628 }
1629
1630 if (good_cnt != 64) {
1631 ret_val = 12;
1632 break;
1633 }
1634
1635 /* allow 200 milliseconds for packets to go from tx to rx */
1636 msleep(200);
1637
1638 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size);
1639 if (good_cnt != 64) {
1640 ret_val = 13;
1641 break;
1642 }
1643 } /* end loop count loop */
1644
1645 /* free the original skb */
1646 kfree_skb(skb);
1647
1648 return ret_val;
1649 }
1650
1651 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1652 {
1653 /* PHY loopback cannot be performed if SoL/IDER
1654 * sessions are active */
1655 if (igb_check_reset_block(&adapter->hw)) {
1656 dev_err(&adapter->pdev->dev,
1657 "Cannot do PHY loopback test "
1658 "when SoL/IDER is active.\n");
1659 *data = 0;
1660 goto out;
1661 }
1662 *data = igb_setup_desc_rings(adapter);
1663 if (*data)
1664 goto out;
1665 *data = igb_setup_loopback_test(adapter);
1666 if (*data)
1667 goto err_loopback;
1668 *data = igb_run_loopback_test(adapter);
1669 igb_loopback_cleanup(adapter);
1670
1671 err_loopback:
1672 igb_free_desc_rings(adapter);
1673 out:
1674 return *data;
1675 }
1676
1677 static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1678 {
1679 struct e1000_hw *hw = &adapter->hw;
1680 *data = 0;
1681 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1682 int i = 0;
1683 hw->mac.serdes_has_link = false;
1684
1685 /* On some blade server designs, link establishment
1686 * could take as long as 2-3 minutes */
1687 do {
1688 hw->mac.ops.check_for_link(&adapter->hw);
1689 if (hw->mac.serdes_has_link)
1690 return *data;
1691 msleep(20);
1692 } while (i++ < 3750);
1693
1694 *data = 1;
1695 } else {
1696 hw->mac.ops.check_for_link(&adapter->hw);
1697 if (hw->mac.autoneg)
1698 msleep(4000);
1699
1700 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU))
1701 *data = 1;
1702 }
1703 return *data;
1704 }
1705
1706 static void igb_diag_test(struct net_device *netdev,
1707 struct ethtool_test *eth_test, u64 *data)
1708 {
1709 struct igb_adapter *adapter = netdev_priv(netdev);
1710 u16 autoneg_advertised;
1711 u8 forced_speed_duplex, autoneg;
1712 bool if_running = netif_running(netdev);
1713
1714 set_bit(__IGB_TESTING, &adapter->state);
1715 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1716 /* Offline tests */
1717
1718 /* save speed, duplex, autoneg settings */
1719 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1720 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1721 autoneg = adapter->hw.mac.autoneg;
1722
1723 dev_info(&adapter->pdev->dev, "offline testing starting\n");
1724
1725 /* power up link for link test */
1726 igb_power_up_link(adapter);
1727
1728 /* Link test performed before hardware reset so autoneg doesn't
1729 * interfere with test result */
1730 if (igb_link_test(adapter, &data[4]))
1731 eth_test->flags |= ETH_TEST_FL_FAILED;
1732
1733 if (if_running)
1734 /* indicate we're in test mode */
1735 dev_close(netdev);
1736 else
1737 igb_reset(adapter);
1738
1739 if (igb_reg_test(adapter, &data[0]))
1740 eth_test->flags |= ETH_TEST_FL_FAILED;
1741
1742 igb_reset(adapter);
1743 if (igb_eeprom_test(adapter, &data[1]))
1744 eth_test->flags |= ETH_TEST_FL_FAILED;
1745
1746 igb_reset(adapter);
1747 if (igb_intr_test(adapter, &data[2]))
1748 eth_test->flags |= ETH_TEST_FL_FAILED;
1749
1750 igb_reset(adapter);
1751 /* power up link for loopback test */
1752 igb_power_up_link(adapter);
1753 if (igb_loopback_test(adapter, &data[3]))
1754 eth_test->flags |= ETH_TEST_FL_FAILED;
1755
1756 /* restore speed, duplex, autoneg settings */
1757 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
1758 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
1759 adapter->hw.mac.autoneg = autoneg;
1760
1761 /* force this routine to wait until autoneg complete/timeout */
1762 adapter->hw.phy.autoneg_wait_to_complete = true;
1763 igb_reset(adapter);
1764 adapter->hw.phy.autoneg_wait_to_complete = false;
1765
1766 clear_bit(__IGB_TESTING, &adapter->state);
1767 if (if_running)
1768 dev_open(netdev);
1769 } else {
1770 dev_info(&adapter->pdev->dev, "online testing starting\n");
1771
1772 /* PHY is powered down when interface is down */
1773 if (!netif_carrier_ok(netdev)) {
1774 data[4] = 0;
1775 } else {
1776 if (igb_link_test(adapter, &data[4]))
1777 eth_test->flags |= ETH_TEST_FL_FAILED;
1778 }
1779
1780 /* Online tests aren't run; pass by default */
1781 data[0] = 0;
1782 data[1] = 0;
1783 data[2] = 0;
1784 data[3] = 0;
1785
1786 clear_bit(__IGB_TESTING, &adapter->state);
1787 }
1788 msleep_interruptible(4 * 1000);
1789 }
1790
1791 static int igb_wol_exclusion(struct igb_adapter *adapter,
1792 struct ethtool_wolinfo *wol)
1793 {
1794 struct e1000_hw *hw = &adapter->hw;
1795 int retval = 1; /* fail by default */
1796
1797 switch (hw->device_id) {
1798 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1799 /* WoL not supported */
1800 wol->supported = 0;
1801 break;
1802 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1803 case E1000_DEV_ID_82576_FIBER:
1804 case E1000_DEV_ID_82576_SERDES:
1805 /* Wake events not supported on port B */
1806 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) {
1807 wol->supported = 0;
1808 break;
1809 }
1810 /* return success for non excluded adapter ports */
1811 retval = 0;
1812 break;
1813 case E1000_DEV_ID_82576_QUAD_COPPER:
1814 /* quad port adapters only support WoL on port A */
1815 if (!(adapter->flags & IGB_FLAG_QUAD_PORT_A)) {
1816 wol->supported = 0;
1817 break;
1818 }
1819 /* return success for non excluded adapter ports */
1820 retval = 0;
1821 break;
1822 default:
1823 /* dual port cards only support WoL on port A from now on
1824 * unless it was enabled in the eeprom for port B
1825 * so exclude FUNC_1 ports from having WoL enabled */
1826 if ((rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) &&
1827 !adapter->eeprom_wol) {
1828 wol->supported = 0;
1829 break;
1830 }
1831
1832 retval = 0;
1833 }
1834
1835 return retval;
1836 }
1837
1838 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1839 {
1840 struct igb_adapter *adapter = netdev_priv(netdev);
1841
1842 wol->supported = WAKE_UCAST | WAKE_MCAST |
1843 WAKE_BCAST | WAKE_MAGIC |
1844 WAKE_PHY;
1845 wol->wolopts = 0;
1846
1847 /* this function will set ->supported = 0 and return 1 if wol is not
1848 * supported by this hardware */
1849 if (igb_wol_exclusion(adapter, wol) ||
1850 !device_can_wakeup(&adapter->pdev->dev))
1851 return;
1852
1853 /* apply any specific unsupported masks here */
1854 switch (adapter->hw.device_id) {
1855 default:
1856 break;
1857 }
1858
1859 if (adapter->wol & E1000_WUFC_EX)
1860 wol->wolopts |= WAKE_UCAST;
1861 if (adapter->wol & E1000_WUFC_MC)
1862 wol->wolopts |= WAKE_MCAST;
1863 if (adapter->wol & E1000_WUFC_BC)
1864 wol->wolopts |= WAKE_BCAST;
1865 if (adapter->wol & E1000_WUFC_MAG)
1866 wol->wolopts |= WAKE_MAGIC;
1867 if (adapter->wol & E1000_WUFC_LNKC)
1868 wol->wolopts |= WAKE_PHY;
1869 }
1870
1871 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1872 {
1873 struct igb_adapter *adapter = netdev_priv(netdev);
1874
1875 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
1876 return -EOPNOTSUPP;
1877
1878 if (igb_wol_exclusion(adapter, wol) ||
1879 !device_can_wakeup(&adapter->pdev->dev))
1880 return wol->wolopts ? -EOPNOTSUPP : 0;
1881
1882 /* these settings will always override what we currently have */
1883 adapter->wol = 0;
1884
1885 if (wol->wolopts & WAKE_UCAST)
1886 adapter->wol |= E1000_WUFC_EX;
1887 if (wol->wolopts & WAKE_MCAST)
1888 adapter->wol |= E1000_WUFC_MC;
1889 if (wol->wolopts & WAKE_BCAST)
1890 adapter->wol |= E1000_WUFC_BC;
1891 if (wol->wolopts & WAKE_MAGIC)
1892 adapter->wol |= E1000_WUFC_MAG;
1893 if (wol->wolopts & WAKE_PHY)
1894 adapter->wol |= E1000_WUFC_LNKC;
1895 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1896
1897 return 0;
1898 }
1899
1900 /* bit defines for adapter->led_status */
1901 #define IGB_LED_ON 0
1902
1903 static int igb_phys_id(struct net_device *netdev, u32 data)
1904 {
1905 struct igb_adapter *adapter = netdev_priv(netdev);
1906 struct e1000_hw *hw = &adapter->hw;
1907 unsigned long timeout;
1908
1909 timeout = data * 1000;
1910
1911 /*
1912 * msleep_interruptable only accepts unsigned int so we are limited
1913 * in how long a duration we can wait
1914 */
1915 if (!timeout || timeout > UINT_MAX)
1916 timeout = UINT_MAX;
1917
1918 igb_blink_led(hw);
1919 msleep_interruptible(timeout);
1920
1921 igb_led_off(hw);
1922 clear_bit(IGB_LED_ON, &adapter->led_status);
1923 igb_cleanup_led(hw);
1924
1925 return 0;
1926 }
1927
1928 static int igb_set_coalesce(struct net_device *netdev,
1929 struct ethtool_coalesce *ec)
1930 {
1931 struct igb_adapter *adapter = netdev_priv(netdev);
1932 int i;
1933
1934 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1935 ((ec->rx_coalesce_usecs > 3) &&
1936 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
1937 (ec->rx_coalesce_usecs == 2))
1938 return -EINVAL;
1939
1940 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1941 ((ec->tx_coalesce_usecs > 3) &&
1942 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
1943 (ec->tx_coalesce_usecs == 2))
1944 return -EINVAL;
1945
1946 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs)
1947 return -EINVAL;
1948
1949 /* convert to rate of irq's per second */
1950 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3)
1951 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
1952 else
1953 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
1954
1955 /* convert to rate of irq's per second */
1956 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS)
1957 adapter->tx_itr_setting = adapter->rx_itr_setting;
1958 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3)
1959 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
1960 else
1961 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
1962
1963 for (i = 0; i < adapter->num_q_vectors; i++) {
1964 struct igb_q_vector *q_vector = adapter->q_vector[i];
1965 if (q_vector->rx_ring)
1966 q_vector->itr_val = adapter->rx_itr_setting;
1967 else
1968 q_vector->itr_val = adapter->tx_itr_setting;
1969 if (q_vector->itr_val && q_vector->itr_val <= 3)
1970 q_vector->itr_val = IGB_START_ITR;
1971 q_vector->set_itr = 1;
1972 }
1973
1974 return 0;
1975 }
1976
1977 static int igb_get_coalesce(struct net_device *netdev,
1978 struct ethtool_coalesce *ec)
1979 {
1980 struct igb_adapter *adapter = netdev_priv(netdev);
1981
1982 if (adapter->rx_itr_setting <= 3)
1983 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
1984 else
1985 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
1986
1987 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) {
1988 if (adapter->tx_itr_setting <= 3)
1989 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
1990 else
1991 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
1992 }
1993
1994 return 0;
1995 }
1996
1997 static int igb_nway_reset(struct net_device *netdev)
1998 {
1999 struct igb_adapter *adapter = netdev_priv(netdev);
2000 if (netif_running(netdev))
2001 igb_reinit_locked(adapter);
2002 return 0;
2003 }
2004
2005 static int igb_get_sset_count(struct net_device *netdev, int sset)
2006 {
2007 switch (sset) {
2008 case ETH_SS_STATS:
2009 return IGB_STATS_LEN;
2010 case ETH_SS_TEST:
2011 return IGB_TEST_LEN;
2012 default:
2013 return -ENOTSUPP;
2014 }
2015 }
2016
2017 static void igb_get_ethtool_stats(struct net_device *netdev,
2018 struct ethtool_stats *stats, u64 *data)
2019 {
2020 struct igb_adapter *adapter = netdev_priv(netdev);
2021 struct net_device_stats *net_stats = &netdev->stats;
2022 u64 *queue_stat;
2023 int i, j, k;
2024 char *p;
2025
2026 igb_update_stats(adapter);
2027
2028 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2029 p = (char *)adapter + igb_gstrings_stats[i].stat_offset;
2030 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
2031 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2032 }
2033 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) {
2034 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset;
2035 data[i] = (igb_gstrings_net_stats[j].sizeof_stat ==
2036 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2037 }
2038 for (j = 0; j < adapter->num_tx_queues; j++) {
2039 queue_stat = (u64 *)&adapter->tx_ring[j].tx_stats;
2040 for (k = 0; k < IGB_TX_QUEUE_STATS_LEN; k++, i++)
2041 data[i] = queue_stat[k];
2042 }
2043 for (j = 0; j < adapter->num_rx_queues; j++) {
2044 queue_stat = (u64 *)&adapter->rx_ring[j].rx_stats;
2045 for (k = 0; k < IGB_RX_QUEUE_STATS_LEN; k++, i++)
2046 data[i] = queue_stat[k];
2047 }
2048 }
2049
2050 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2051 {
2052 struct igb_adapter *adapter = netdev_priv(netdev);
2053 u8 *p = data;
2054 int i;
2055
2056 switch (stringset) {
2057 case ETH_SS_TEST:
2058 memcpy(data, *igb_gstrings_test,
2059 IGB_TEST_LEN*ETH_GSTRING_LEN);
2060 break;
2061 case ETH_SS_STATS:
2062 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2063 memcpy(p, igb_gstrings_stats[i].stat_string,
2064 ETH_GSTRING_LEN);
2065 p += ETH_GSTRING_LEN;
2066 }
2067 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) {
2068 memcpy(p, igb_gstrings_net_stats[i].stat_string,
2069 ETH_GSTRING_LEN);
2070 p += ETH_GSTRING_LEN;
2071 }
2072 for (i = 0; i < adapter->num_tx_queues; i++) {
2073 sprintf(p, "tx_queue_%u_packets", i);
2074 p += ETH_GSTRING_LEN;
2075 sprintf(p, "tx_queue_%u_bytes", i);
2076 p += ETH_GSTRING_LEN;
2077 sprintf(p, "tx_queue_%u_restart", i);
2078 p += ETH_GSTRING_LEN;
2079 }
2080 for (i = 0; i < adapter->num_rx_queues; i++) {
2081 sprintf(p, "rx_queue_%u_packets", i);
2082 p += ETH_GSTRING_LEN;
2083 sprintf(p, "rx_queue_%u_bytes", i);
2084 p += ETH_GSTRING_LEN;
2085 sprintf(p, "rx_queue_%u_drops", i);
2086 p += ETH_GSTRING_LEN;
2087 sprintf(p, "rx_queue_%u_csum_err", i);
2088 p += ETH_GSTRING_LEN;
2089 sprintf(p, "rx_queue_%u_alloc_failed", i);
2090 p += ETH_GSTRING_LEN;
2091 }
2092 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2093 break;
2094 }
2095 }
2096
2097 static const struct ethtool_ops igb_ethtool_ops = {
2098 .get_settings = igb_get_settings,
2099 .set_settings = igb_set_settings,
2100 .get_drvinfo = igb_get_drvinfo,
2101 .get_regs_len = igb_get_regs_len,
2102 .get_regs = igb_get_regs,
2103 .get_wol = igb_get_wol,
2104 .set_wol = igb_set_wol,
2105 .get_msglevel = igb_get_msglevel,
2106 .set_msglevel = igb_set_msglevel,
2107 .nway_reset = igb_nway_reset,
2108 .get_link = igb_get_link,
2109 .get_eeprom_len = igb_get_eeprom_len,
2110 .get_eeprom = igb_get_eeprom,
2111 .set_eeprom = igb_set_eeprom,
2112 .get_ringparam = igb_get_ringparam,
2113 .set_ringparam = igb_set_ringparam,
2114 .get_pauseparam = igb_get_pauseparam,
2115 .set_pauseparam = igb_set_pauseparam,
2116 .get_rx_csum = igb_get_rx_csum,
2117 .set_rx_csum = igb_set_rx_csum,
2118 .get_tx_csum = igb_get_tx_csum,
2119 .set_tx_csum = igb_set_tx_csum,
2120 .get_sg = ethtool_op_get_sg,
2121 .set_sg = ethtool_op_set_sg,
2122 .get_tso = ethtool_op_get_tso,
2123 .set_tso = igb_set_tso,
2124 .self_test = igb_diag_test,
2125 .get_strings = igb_get_strings,
2126 .phys_id = igb_phys_id,
2127 .get_sset_count = igb_get_sset_count,
2128 .get_ethtool_stats = igb_get_ethtool_stats,
2129 .get_coalesce = igb_get_coalesce,
2130 .set_coalesce = igb_set_coalesce,
2131 };
2132
2133 void igb_set_ethtool_ops(struct net_device *netdev)
2134 {
2135 SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);
2136 }
Linux kernel - Deliverables
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