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headers: remove sched.h from interrupt.h
[deliverable/linux.git] / drivers / net / igb / igb_ethtool.c
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 /* ethtool support for igb */
29
30 #include <linux/vmalloc.h>
31 #include <linux/netdevice.h>
32 #include <linux/pci.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
35 #include <linux/if_ether.h>
36 #include <linux/ethtool.h>
37 #include <linux/sched.h>
38
39 #include "igb.h"
40
41 struct igb_stats {
42 char stat_string[ETH_GSTRING_LEN];
43 int sizeof_stat;
44 int stat_offset;
45 };
46
47 #define IGB_STAT(m) FIELD_SIZEOF(struct igb_adapter, m), \
48 offsetof(struct igb_adapter, m)
49 static const struct igb_stats igb_gstrings_stats[] = {
50 { "rx_packets", IGB_STAT(stats.gprc) },
51 { "tx_packets", IGB_STAT(stats.gptc) },
52 { "rx_bytes", IGB_STAT(stats.gorc) },
53 { "tx_bytes", IGB_STAT(stats.gotc) },
54 { "rx_broadcast", IGB_STAT(stats.bprc) },
55 { "tx_broadcast", IGB_STAT(stats.bptc) },
56 { "rx_multicast", IGB_STAT(stats.mprc) },
57 { "tx_multicast", IGB_STAT(stats.mptc) },
58 { "rx_errors", IGB_STAT(net_stats.rx_errors) },
59 { "tx_errors", IGB_STAT(net_stats.tx_errors) },
60 { "tx_dropped", IGB_STAT(net_stats.tx_dropped) },
61 { "multicast", IGB_STAT(stats.mprc) },
62 { "collisions", IGB_STAT(stats.colc) },
63 { "rx_length_errors", IGB_STAT(net_stats.rx_length_errors) },
64 { "rx_over_errors", IGB_STAT(net_stats.rx_over_errors) },
65 { "rx_crc_errors", IGB_STAT(stats.crcerrs) },
66 { "rx_frame_errors", IGB_STAT(net_stats.rx_frame_errors) },
67 { "rx_no_buffer_count", IGB_STAT(stats.rnbc) },
68 { "rx_queue_drop_packet_count", IGB_STAT(net_stats.rx_fifo_errors) },
69 { "rx_missed_errors", IGB_STAT(stats.mpc) },
70 { "tx_aborted_errors", IGB_STAT(stats.ecol) },
71 { "tx_carrier_errors", IGB_STAT(stats.tncrs) },
72 { "tx_fifo_errors", IGB_STAT(net_stats.tx_fifo_errors) },
73 { "tx_heartbeat_errors", IGB_STAT(net_stats.tx_heartbeat_errors) },
74 { "tx_window_errors", IGB_STAT(stats.latecol) },
75 { "tx_abort_late_coll", IGB_STAT(stats.latecol) },
76 { "tx_deferred_ok", IGB_STAT(stats.dc) },
77 { "tx_single_coll_ok", IGB_STAT(stats.scc) },
78 { "tx_multi_coll_ok", IGB_STAT(stats.mcc) },
79 { "tx_timeout_count", IGB_STAT(tx_timeout_count) },
80 { "tx_restart_queue", IGB_STAT(restart_queue) },
81 { "rx_long_length_errors", IGB_STAT(stats.roc) },
82 { "rx_short_length_errors", IGB_STAT(stats.ruc) },
83 { "rx_align_errors", IGB_STAT(stats.algnerrc) },
84 { "tx_tcp_seg_good", IGB_STAT(stats.tsctc) },
85 { "tx_tcp_seg_failed", IGB_STAT(stats.tsctfc) },
86 { "rx_flow_control_xon", IGB_STAT(stats.xonrxc) },
87 { "rx_flow_control_xoff", IGB_STAT(stats.xoffrxc) },
88 { "tx_flow_control_xon", IGB_STAT(stats.xontxc) },
89 { "tx_flow_control_xoff", IGB_STAT(stats.xofftxc) },
90 { "rx_long_byte_count", IGB_STAT(stats.gorc) },
91 { "rx_csum_offload_good", IGB_STAT(hw_csum_good) },
92 { "rx_csum_offload_errors", IGB_STAT(hw_csum_err) },
93 { "tx_dma_out_of_sync", IGB_STAT(stats.doosync) },
94 { "alloc_rx_buff_failed", IGB_STAT(alloc_rx_buff_failed) },
95 { "tx_smbus", IGB_STAT(stats.mgptc) },
96 { "rx_smbus", IGB_STAT(stats.mgprc) },
97 { "dropped_smbus", IGB_STAT(stats.mgpdc) },
98 };
99
100 #define IGB_QUEUE_STATS_LEN \
101 (((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues)* \
102 (sizeof(struct igb_rx_queue_stats) / sizeof(u64))) + \
103 ((((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues) * \
104 (sizeof(struct igb_tx_queue_stats) / sizeof(u64))))
105 #define IGB_GLOBAL_STATS_LEN \
106 sizeof(igb_gstrings_stats) / sizeof(struct igb_stats)
107 #define IGB_STATS_LEN (IGB_GLOBAL_STATS_LEN + IGB_QUEUE_STATS_LEN)
108 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
109 "Register test (offline)", "Eeprom test (offline)",
110 "Interrupt test (offline)", "Loopback test (offline)",
111 "Link test (on/offline)"
112 };
113 #define IGB_TEST_LEN sizeof(igb_gstrings_test) / ETH_GSTRING_LEN
114
115 static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
116 {
117 struct igb_adapter *adapter = netdev_priv(netdev);
118 struct e1000_hw *hw = &adapter->hw;
119
120 if (hw->phy.media_type == e1000_media_type_copper) {
121
122 ecmd->supported = (SUPPORTED_10baseT_Half |
123 SUPPORTED_10baseT_Full |
124 SUPPORTED_100baseT_Half |
125 SUPPORTED_100baseT_Full |
126 SUPPORTED_1000baseT_Full|
127 SUPPORTED_Autoneg |
128 SUPPORTED_TP);
129 ecmd->advertising = ADVERTISED_TP;
130
131 if (hw->mac.autoneg == 1) {
132 ecmd->advertising |= ADVERTISED_Autoneg;
133 /* the e1000 autoneg seems to match ethtool nicely */
134 ecmd->advertising |= hw->phy.autoneg_advertised;
135 }
136
137 ecmd->port = PORT_TP;
138 ecmd->phy_address = hw->phy.addr;
139 } else {
140 ecmd->supported = (SUPPORTED_1000baseT_Full |
141 SUPPORTED_FIBRE |
142 SUPPORTED_Autoneg);
143
144 ecmd->advertising = (ADVERTISED_1000baseT_Full |
145 ADVERTISED_FIBRE |
146 ADVERTISED_Autoneg);
147
148 ecmd->port = PORT_FIBRE;
149 }
150
151 ecmd->transceiver = XCVR_INTERNAL;
152
153 if (rd32(E1000_STATUS) & E1000_STATUS_LU) {
154
155 adapter->hw.mac.ops.get_speed_and_duplex(hw,
156 &adapter->link_speed,
157 &adapter->link_duplex);
158 ecmd->speed = adapter->link_speed;
159
160 /* unfortunately FULL_DUPLEX != DUPLEX_FULL
161 * and HALF_DUPLEX != DUPLEX_HALF */
162
163 if (adapter->link_duplex == FULL_DUPLEX)
164 ecmd->duplex = DUPLEX_FULL;
165 else
166 ecmd->duplex = DUPLEX_HALF;
167 } else {
168 ecmd->speed = -1;
169 ecmd->duplex = -1;
170 }
171
172 ecmd->autoneg = hw->mac.autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
173 return 0;
174 }
175
176 static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
177 {
178 struct igb_adapter *adapter = netdev_priv(netdev);
179 struct e1000_hw *hw = &adapter->hw;
180
181 /* When SoL/IDER sessions are active, autoneg/speed/duplex
182 * cannot be changed */
183 if (igb_check_reset_block(hw)) {
184 dev_err(&adapter->pdev->dev, "Cannot change link "
185 "characteristics when SoL/IDER is active.\n");
186 return -EINVAL;
187 }
188
189 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
190 msleep(1);
191
192 if (ecmd->autoneg == AUTONEG_ENABLE) {
193 hw->mac.autoneg = 1;
194 hw->phy.autoneg_advertised = ecmd->advertising |
195 ADVERTISED_TP |
196 ADVERTISED_Autoneg;
197 ecmd->advertising = hw->phy.autoneg_advertised;
198 if (adapter->fc_autoneg)
199 hw->fc.requested_mode = e1000_fc_default;
200 } else {
201 if (igb_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
202 clear_bit(__IGB_RESETTING, &adapter->state);
203 return -EINVAL;
204 }
205 }
206
207 /* reset the link */
208 if (netif_running(adapter->netdev)) {
209 igb_down(adapter);
210 igb_up(adapter);
211 } else
212 igb_reset(adapter);
213
214 clear_bit(__IGB_RESETTING, &adapter->state);
215 return 0;
216 }
217
218 static void igb_get_pauseparam(struct net_device *netdev,
219 struct ethtool_pauseparam *pause)
220 {
221 struct igb_adapter *adapter = netdev_priv(netdev);
222 struct e1000_hw *hw = &adapter->hw;
223
224 pause->autoneg =
225 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
226
227 if (hw->fc.current_mode == e1000_fc_rx_pause)
228 pause->rx_pause = 1;
229 else if (hw->fc.current_mode == e1000_fc_tx_pause)
230 pause->tx_pause = 1;
231 else if (hw->fc.current_mode == e1000_fc_full) {
232 pause->rx_pause = 1;
233 pause->tx_pause = 1;
234 }
235 }
236
237 static int igb_set_pauseparam(struct net_device *netdev,
238 struct ethtool_pauseparam *pause)
239 {
240 struct igb_adapter *adapter = netdev_priv(netdev);
241 struct e1000_hw *hw = &adapter->hw;
242 int retval = 0;
243
244 adapter->fc_autoneg = pause->autoneg;
245
246 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
247 msleep(1);
248
249 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
250 hw->fc.requested_mode = e1000_fc_default;
251 if (netif_running(adapter->netdev)) {
252 igb_down(adapter);
253 igb_up(adapter);
254 } else
255 igb_reset(adapter);
256 } else {
257 if (pause->rx_pause && pause->tx_pause)
258 hw->fc.requested_mode = e1000_fc_full;
259 else if (pause->rx_pause && !pause->tx_pause)
260 hw->fc.requested_mode = e1000_fc_rx_pause;
261 else if (!pause->rx_pause && pause->tx_pause)
262 hw->fc.requested_mode = e1000_fc_tx_pause;
263 else if (!pause->rx_pause && !pause->tx_pause)
264 hw->fc.requested_mode = e1000_fc_none;
265
266 hw->fc.current_mode = hw->fc.requested_mode;
267
268 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
269 igb_force_mac_fc(hw) : igb_setup_link(hw));
270 }
271
272 clear_bit(__IGB_RESETTING, &adapter->state);
273 return retval;
274 }
275
276 static u32 igb_get_rx_csum(struct net_device *netdev)
277 {
278 struct igb_adapter *adapter = netdev_priv(netdev);
279 return !(adapter->flags & IGB_FLAG_RX_CSUM_DISABLED);
280 }
281
282 static int igb_set_rx_csum(struct net_device *netdev, u32 data)
283 {
284 struct igb_adapter *adapter = netdev_priv(netdev);
285
286 if (data)
287 adapter->flags &= ~IGB_FLAG_RX_CSUM_DISABLED;
288 else
289 adapter->flags |= IGB_FLAG_RX_CSUM_DISABLED;
290
291 return 0;
292 }
293
294 static u32 igb_get_tx_csum(struct net_device *netdev)
295 {
296 return (netdev->features & NETIF_F_IP_CSUM) != 0;
297 }
298
299 static int igb_set_tx_csum(struct net_device *netdev, u32 data)
300 {
301 struct igb_adapter *adapter = netdev_priv(netdev);
302
303 if (data) {
304 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
305 if (adapter->hw.mac.type == e1000_82576)
306 netdev->features |= NETIF_F_SCTP_CSUM;
307 } else {
308 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
309 NETIF_F_SCTP_CSUM);
310 }
311
312 return 0;
313 }
314
315 static int igb_set_tso(struct net_device *netdev, u32 data)
316 {
317 struct igb_adapter *adapter = netdev_priv(netdev);
318
319 if (data) {
320 netdev->features |= NETIF_F_TSO;
321 netdev->features |= NETIF_F_TSO6;
322 } else {
323 netdev->features &= ~NETIF_F_TSO;
324 netdev->features &= ~NETIF_F_TSO6;
325 }
326
327 dev_info(&adapter->pdev->dev, "TSO is %s\n",
328 data ? "Enabled" : "Disabled");
329 return 0;
330 }
331
332 static u32 igb_get_msglevel(struct net_device *netdev)
333 {
334 struct igb_adapter *adapter = netdev_priv(netdev);
335 return adapter->msg_enable;
336 }
337
338 static void igb_set_msglevel(struct net_device *netdev, u32 data)
339 {
340 struct igb_adapter *adapter = netdev_priv(netdev);
341 adapter->msg_enable = data;
342 }
343
344 static int igb_get_regs_len(struct net_device *netdev)
345 {
346 #define IGB_REGS_LEN 551
347 return IGB_REGS_LEN * sizeof(u32);
348 }
349
350 static void igb_get_regs(struct net_device *netdev,
351 struct ethtool_regs *regs, void *p)
352 {
353 struct igb_adapter *adapter = netdev_priv(netdev);
354 struct e1000_hw *hw = &adapter->hw;
355 u32 *regs_buff = p;
356 u8 i;
357
358 memset(p, 0, IGB_REGS_LEN * sizeof(u32));
359
360 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
361
362 /* General Registers */
363 regs_buff[0] = rd32(E1000_CTRL);
364 regs_buff[1] = rd32(E1000_STATUS);
365 regs_buff[2] = rd32(E1000_CTRL_EXT);
366 regs_buff[3] = rd32(E1000_MDIC);
367 regs_buff[4] = rd32(E1000_SCTL);
368 regs_buff[5] = rd32(E1000_CONNSW);
369 regs_buff[6] = rd32(E1000_VET);
370 regs_buff[7] = rd32(E1000_LEDCTL);
371 regs_buff[8] = rd32(E1000_PBA);
372 regs_buff[9] = rd32(E1000_PBS);
373 regs_buff[10] = rd32(E1000_FRTIMER);
374 regs_buff[11] = rd32(E1000_TCPTIMER);
375
376 /* NVM Register */
377 regs_buff[12] = rd32(E1000_EECD);
378
379 /* Interrupt */
380 /* Reading EICS for EICR because they read the
381 * same but EICS does not clear on read */
382 regs_buff[13] = rd32(E1000_EICS);
383 regs_buff[14] = rd32(E1000_EICS);
384 regs_buff[15] = rd32(E1000_EIMS);
385 regs_buff[16] = rd32(E1000_EIMC);
386 regs_buff[17] = rd32(E1000_EIAC);
387 regs_buff[18] = rd32(E1000_EIAM);
388 /* Reading ICS for ICR because they read the
389 * same but ICS does not clear on read */
390 regs_buff[19] = rd32(E1000_ICS);
391 regs_buff[20] = rd32(E1000_ICS);
392 regs_buff[21] = rd32(E1000_IMS);
393 regs_buff[22] = rd32(E1000_IMC);
394 regs_buff[23] = rd32(E1000_IAC);
395 regs_buff[24] = rd32(E1000_IAM);
396 regs_buff[25] = rd32(E1000_IMIRVP);
397
398 /* Flow Control */
399 regs_buff[26] = rd32(E1000_FCAL);
400 regs_buff[27] = rd32(E1000_FCAH);
401 regs_buff[28] = rd32(E1000_FCTTV);
402 regs_buff[29] = rd32(E1000_FCRTL);
403 regs_buff[30] = rd32(E1000_FCRTH);
404 regs_buff[31] = rd32(E1000_FCRTV);
405
406 /* Receive */
407 regs_buff[32] = rd32(E1000_RCTL);
408 regs_buff[33] = rd32(E1000_RXCSUM);
409 regs_buff[34] = rd32(E1000_RLPML);
410 regs_buff[35] = rd32(E1000_RFCTL);
411 regs_buff[36] = rd32(E1000_MRQC);
412 regs_buff[37] = rd32(E1000_VT_CTL);
413
414 /* Transmit */
415 regs_buff[38] = rd32(E1000_TCTL);
416 regs_buff[39] = rd32(E1000_TCTL_EXT);
417 regs_buff[40] = rd32(E1000_TIPG);
418 regs_buff[41] = rd32(E1000_DTXCTL);
419
420 /* Wake Up */
421 regs_buff[42] = rd32(E1000_WUC);
422 regs_buff[43] = rd32(E1000_WUFC);
423 regs_buff[44] = rd32(E1000_WUS);
424 regs_buff[45] = rd32(E1000_IPAV);
425 regs_buff[46] = rd32(E1000_WUPL);
426
427 /* MAC */
428 regs_buff[47] = rd32(E1000_PCS_CFG0);
429 regs_buff[48] = rd32(E1000_PCS_LCTL);
430 regs_buff[49] = rd32(E1000_PCS_LSTAT);
431 regs_buff[50] = rd32(E1000_PCS_ANADV);
432 regs_buff[51] = rd32(E1000_PCS_LPAB);
433 regs_buff[52] = rd32(E1000_PCS_NPTX);
434 regs_buff[53] = rd32(E1000_PCS_LPABNP);
435
436 /* Statistics */
437 regs_buff[54] = adapter->stats.crcerrs;
438 regs_buff[55] = adapter->stats.algnerrc;
439 regs_buff[56] = adapter->stats.symerrs;
440 regs_buff[57] = adapter->stats.rxerrc;
441 regs_buff[58] = adapter->stats.mpc;
442 regs_buff[59] = adapter->stats.scc;
443 regs_buff[60] = adapter->stats.ecol;
444 regs_buff[61] = adapter->stats.mcc;
445 regs_buff[62] = adapter->stats.latecol;
446 regs_buff[63] = adapter->stats.colc;
447 regs_buff[64] = adapter->stats.dc;
448 regs_buff[65] = adapter->stats.tncrs;
449 regs_buff[66] = adapter->stats.sec;
450 regs_buff[67] = adapter->stats.htdpmc;
451 regs_buff[68] = adapter->stats.rlec;
452 regs_buff[69] = adapter->stats.xonrxc;
453 regs_buff[70] = adapter->stats.xontxc;
454 regs_buff[71] = adapter->stats.xoffrxc;
455 regs_buff[72] = adapter->stats.xofftxc;
456 regs_buff[73] = adapter->stats.fcruc;
457 regs_buff[74] = adapter->stats.prc64;
458 regs_buff[75] = adapter->stats.prc127;
459 regs_buff[76] = adapter->stats.prc255;
460 regs_buff[77] = adapter->stats.prc511;
461 regs_buff[78] = adapter->stats.prc1023;
462 regs_buff[79] = adapter->stats.prc1522;
463 regs_buff[80] = adapter->stats.gprc;
464 regs_buff[81] = adapter->stats.bprc;
465 regs_buff[82] = adapter->stats.mprc;
466 regs_buff[83] = adapter->stats.gptc;
467 regs_buff[84] = adapter->stats.gorc;
468 regs_buff[86] = adapter->stats.gotc;
469 regs_buff[88] = adapter->stats.rnbc;
470 regs_buff[89] = adapter->stats.ruc;
471 regs_buff[90] = adapter->stats.rfc;
472 regs_buff[91] = adapter->stats.roc;
473 regs_buff[92] = adapter->stats.rjc;
474 regs_buff[93] = adapter->stats.mgprc;
475 regs_buff[94] = adapter->stats.mgpdc;
476 regs_buff[95] = adapter->stats.mgptc;
477 regs_buff[96] = adapter->stats.tor;
478 regs_buff[98] = adapter->stats.tot;
479 regs_buff[100] = adapter->stats.tpr;
480 regs_buff[101] = adapter->stats.tpt;
481 regs_buff[102] = adapter->stats.ptc64;
482 regs_buff[103] = adapter->stats.ptc127;
483 regs_buff[104] = adapter->stats.ptc255;
484 regs_buff[105] = adapter->stats.ptc511;
485 regs_buff[106] = adapter->stats.ptc1023;
486 regs_buff[107] = adapter->stats.ptc1522;
487 regs_buff[108] = adapter->stats.mptc;
488 regs_buff[109] = adapter->stats.bptc;
489 regs_buff[110] = adapter->stats.tsctc;
490 regs_buff[111] = adapter->stats.iac;
491 regs_buff[112] = adapter->stats.rpthc;
492 regs_buff[113] = adapter->stats.hgptc;
493 regs_buff[114] = adapter->stats.hgorc;
494 regs_buff[116] = adapter->stats.hgotc;
495 regs_buff[118] = adapter->stats.lenerrs;
496 regs_buff[119] = adapter->stats.scvpc;
497 regs_buff[120] = adapter->stats.hrmpc;
498
499 /* These should probably be added to e1000_regs.h instead */
500 #define E1000_PSRTYPE_REG(_i) (0x05480 + ((_i) * 4))
501 #define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8))
502 #define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4))
503 #define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4))
504 #define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8))
505 #define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8))
506 #define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8))
507
508 for (i = 0; i < 4; i++)
509 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
510 for (i = 0; i < 4; i++)
511 regs_buff[125 + i] = rd32(E1000_PSRTYPE_REG(i));
512 for (i = 0; i < 4; i++)
513 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
514 for (i = 0; i < 4; i++)
515 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
516 for (i = 0; i < 4; i++)
517 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
518 for (i = 0; i < 4; i++)
519 regs_buff[141 + i] = rd32(E1000_RDH(i));
520 for (i = 0; i < 4; i++)
521 regs_buff[145 + i] = rd32(E1000_RDT(i));
522 for (i = 0; i < 4; i++)
523 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
524
525 for (i = 0; i < 10; i++)
526 regs_buff[153 + i] = rd32(E1000_EITR(i));
527 for (i = 0; i < 8; i++)
528 regs_buff[163 + i] = rd32(E1000_IMIR(i));
529 for (i = 0; i < 8; i++)
530 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
531 for (i = 0; i < 16; i++)
532 regs_buff[179 + i] = rd32(E1000_RAL(i));
533 for (i = 0; i < 16; i++)
534 regs_buff[195 + i] = rd32(E1000_RAH(i));
535
536 for (i = 0; i < 4; i++)
537 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
538 for (i = 0; i < 4; i++)
539 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
540 for (i = 0; i < 4; i++)
541 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
542 for (i = 0; i < 4; i++)
543 regs_buff[223 + i] = rd32(E1000_TDH(i));
544 for (i = 0; i < 4; i++)
545 regs_buff[227 + i] = rd32(E1000_TDT(i));
546 for (i = 0; i < 4; i++)
547 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
548 for (i = 0; i < 4; i++)
549 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
550 for (i = 0; i < 4; i++)
551 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
552 for (i = 0; i < 4; i++)
553 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
554
555 for (i = 0; i < 4; i++)
556 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
557 for (i = 0; i < 4; i++)
558 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
559 for (i = 0; i < 32; i++)
560 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
561 for (i = 0; i < 128; i++)
562 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
563 for (i = 0; i < 128; i++)
564 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
565 for (i = 0; i < 4; i++)
566 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
567
568 regs_buff[547] = rd32(E1000_TDFH);
569 regs_buff[548] = rd32(E1000_TDFT);
570 regs_buff[549] = rd32(E1000_TDFHS);
571 regs_buff[550] = rd32(E1000_TDFPC);
572
573 }
574
575 static int igb_get_eeprom_len(struct net_device *netdev)
576 {
577 struct igb_adapter *adapter = netdev_priv(netdev);
578 return adapter->hw.nvm.word_size * 2;
579 }
580
581 static int igb_get_eeprom(struct net_device *netdev,
582 struct ethtool_eeprom *eeprom, u8 *bytes)
583 {
584 struct igb_adapter *adapter = netdev_priv(netdev);
585 struct e1000_hw *hw = &adapter->hw;
586 u16 *eeprom_buff;
587 int first_word, last_word;
588 int ret_val = 0;
589 u16 i;
590
591 if (eeprom->len == 0)
592 return -EINVAL;
593
594 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
595
596 first_word = eeprom->offset >> 1;
597 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
598
599 eeprom_buff = kmalloc(sizeof(u16) *
600 (last_word - first_word + 1), GFP_KERNEL);
601 if (!eeprom_buff)
602 return -ENOMEM;
603
604 if (hw->nvm.type == e1000_nvm_eeprom_spi)
605 ret_val = hw->nvm.ops.read(hw, first_word,
606 last_word - first_word + 1,
607 eeprom_buff);
608 else {
609 for (i = 0; i < last_word - first_word + 1; i++) {
610 ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
611 &eeprom_buff[i]);
612 if (ret_val)
613 break;
614 }
615 }
616
617 /* Device's eeprom is always little-endian, word addressable */
618 for (i = 0; i < last_word - first_word + 1; i++)
619 le16_to_cpus(&eeprom_buff[i]);
620
621 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
622 eeprom->len);
623 kfree(eeprom_buff);
624
625 return ret_val;
626 }
627
628 static int igb_set_eeprom(struct net_device *netdev,
629 struct ethtool_eeprom *eeprom, u8 *bytes)
630 {
631 struct igb_adapter *adapter = netdev_priv(netdev);
632 struct e1000_hw *hw = &adapter->hw;
633 u16 *eeprom_buff;
634 void *ptr;
635 int max_len, first_word, last_word, ret_val = 0;
636 u16 i;
637
638 if (eeprom->len == 0)
639 return -EOPNOTSUPP;
640
641 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
642 return -EFAULT;
643
644 max_len = hw->nvm.word_size * 2;
645
646 first_word = eeprom->offset >> 1;
647 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
648 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
649 if (!eeprom_buff)
650 return -ENOMEM;
651
652 ptr = (void *)eeprom_buff;
653
654 if (eeprom->offset & 1) {
655 /* need read/modify/write of first changed EEPROM word */
656 /* only the second byte of the word is being modified */
657 ret_val = hw->nvm.ops.read(hw, first_word, 1,
658 &eeprom_buff[0]);
659 ptr++;
660 }
661 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
662 /* need read/modify/write of last changed EEPROM word */
663 /* only the first byte of the word is being modified */
664 ret_val = hw->nvm.ops.read(hw, last_word, 1,
665 &eeprom_buff[last_word - first_word]);
666 }
667
668 /* Device's eeprom is always little-endian, word addressable */
669 for (i = 0; i < last_word - first_word + 1; i++)
670 le16_to_cpus(&eeprom_buff[i]);
671
672 memcpy(ptr, bytes, eeprom->len);
673
674 for (i = 0; i < last_word - first_word + 1; i++)
675 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
676
677 ret_val = hw->nvm.ops.write(hw, first_word,
678 last_word - first_word + 1, eeprom_buff);
679
680 /* Update the checksum over the first part of the EEPROM if needed
681 * and flush shadow RAM for 82573 controllers */
682 if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
683 igb_update_nvm_checksum(hw);
684
685 kfree(eeprom_buff);
686 return ret_val;
687 }
688
689 static void igb_get_drvinfo(struct net_device *netdev,
690 struct ethtool_drvinfo *drvinfo)
691 {
692 struct igb_adapter *adapter = netdev_priv(netdev);
693 char firmware_version[32];
694 u16 eeprom_data;
695
696 strncpy(drvinfo->driver, igb_driver_name, 32);
697 strncpy(drvinfo->version, igb_driver_version, 32);
698
699 /* EEPROM image version # is reported as firmware version # for
700 * 82575 controllers */
701 adapter->hw.nvm.ops.read(&adapter->hw, 5, 1, &eeprom_data);
702 sprintf(firmware_version, "%d.%d-%d",
703 (eeprom_data & 0xF000) >> 12,
704 (eeprom_data & 0x0FF0) >> 4,
705 eeprom_data & 0x000F);
706
707 strncpy(drvinfo->fw_version, firmware_version, 32);
708 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
709 drvinfo->n_stats = IGB_STATS_LEN;
710 drvinfo->testinfo_len = IGB_TEST_LEN;
711 drvinfo->regdump_len = igb_get_regs_len(netdev);
712 drvinfo->eedump_len = igb_get_eeprom_len(netdev);
713 }
714
715 static void igb_get_ringparam(struct net_device *netdev,
716 struct ethtool_ringparam *ring)
717 {
718 struct igb_adapter *adapter = netdev_priv(netdev);
719
720 ring->rx_max_pending = IGB_MAX_RXD;
721 ring->tx_max_pending = IGB_MAX_TXD;
722 ring->rx_mini_max_pending = 0;
723 ring->rx_jumbo_max_pending = 0;
724 ring->rx_pending = adapter->rx_ring_count;
725 ring->tx_pending = adapter->tx_ring_count;
726 ring->rx_mini_pending = 0;
727 ring->rx_jumbo_pending = 0;
728 }
729
730 static int igb_set_ringparam(struct net_device *netdev,
731 struct ethtool_ringparam *ring)
732 {
733 struct igb_adapter *adapter = netdev_priv(netdev);
734 struct igb_ring *temp_ring;
735 int i, err;
736 u32 new_rx_count, new_tx_count;
737
738 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
739 return -EINVAL;
740
741 new_rx_count = max(ring->rx_pending, (u32)IGB_MIN_RXD);
742 new_rx_count = min(new_rx_count, (u32)IGB_MAX_RXD);
743 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
744
745 new_tx_count = max(ring->tx_pending, (u32)IGB_MIN_TXD);
746 new_tx_count = min(new_tx_count, (u32)IGB_MAX_TXD);
747 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
748
749 if ((new_tx_count == adapter->tx_ring_count) &&
750 (new_rx_count == adapter->rx_ring_count)) {
751 /* nothing to do */
752 return 0;
753 }
754
755 if (adapter->num_tx_queues > adapter->num_rx_queues)
756 temp_ring = vmalloc(adapter->num_tx_queues * sizeof(struct igb_ring));
757 else
758 temp_ring = vmalloc(adapter->num_rx_queues * sizeof(struct igb_ring));
759 if (!temp_ring)
760 return -ENOMEM;
761
762 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
763 msleep(1);
764
765 if (netif_running(adapter->netdev))
766 igb_down(adapter);
767
768 /*
769 * We can't just free everything and then setup again,
770 * because the ISRs in MSI-X mode get passed pointers
771 * to the tx and rx ring structs.
772 */
773 if (new_tx_count != adapter->tx_ring_count) {
774 memcpy(temp_ring, adapter->tx_ring,
775 adapter->num_tx_queues * sizeof(struct igb_ring));
776
777 for (i = 0; i < adapter->num_tx_queues; i++) {
778 temp_ring[i].count = new_tx_count;
779 err = igb_setup_tx_resources(adapter, &temp_ring[i]);
780 if (err) {
781 while (i) {
782 i--;
783 igb_free_tx_resources(&temp_ring[i]);
784 }
785 goto err_setup;
786 }
787 }
788
789 for (i = 0; i < adapter->num_tx_queues; i++)
790 igb_free_tx_resources(&adapter->tx_ring[i]);
791
792 memcpy(adapter->tx_ring, temp_ring,
793 adapter->num_tx_queues * sizeof(struct igb_ring));
794
795 adapter->tx_ring_count = new_tx_count;
796 }
797
798 if (new_rx_count != adapter->rx_ring->count) {
799 memcpy(temp_ring, adapter->rx_ring,
800 adapter->num_rx_queues * sizeof(struct igb_ring));
801
802 for (i = 0; i < adapter->num_rx_queues; i++) {
803 temp_ring[i].count = new_rx_count;
804 err = igb_setup_rx_resources(adapter, &temp_ring[i]);
805 if (err) {
806 while (i) {
807 i--;
808 igb_free_rx_resources(&temp_ring[i]);
809 }
810 goto err_setup;
811 }
812
813 }
814
815 for (i = 0; i < adapter->num_rx_queues; i++)
816 igb_free_rx_resources(&adapter->rx_ring[i]);
817
818 memcpy(adapter->rx_ring, temp_ring,
819 adapter->num_rx_queues * sizeof(struct igb_ring));
820
821 adapter->rx_ring_count = new_rx_count;
822 }
823
824 err = 0;
825 err_setup:
826 if (netif_running(adapter->netdev))
827 igb_up(adapter);
828
829 clear_bit(__IGB_RESETTING, &adapter->state);
830 vfree(temp_ring);
831 return err;
832 }
833
834 /* ethtool register test data */
835 struct igb_reg_test {
836 u16 reg;
837 u16 reg_offset;
838 u16 array_len;
839 u16 test_type;
840 u32 mask;
841 u32 write;
842 };
843
844 /* In the hardware, registers are laid out either singly, in arrays
845 * spaced 0x100 bytes apart, or in contiguous tables. We assume
846 * most tests take place on arrays or single registers (handled
847 * as a single-element array) and special-case the tables.
848 * Table tests are always pattern tests.
849 *
850 * We also make provision for some required setup steps by specifying
851 * registers to be written without any read-back testing.
852 */
853
854 #define PATTERN_TEST 1
855 #define SET_READ_TEST 2
856 #define WRITE_NO_TEST 3
857 #define TABLE32_TEST 4
858 #define TABLE64_TEST_LO 5
859 #define TABLE64_TEST_HI 6
860
861 /* 82576 reg test */
862 static struct igb_reg_test reg_test_82576[] = {
863 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
864 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
865 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
866 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
867 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
868 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
869 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
870 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
871 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
872 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
873 /* Enable all RX queues before testing. */
874 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
875 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
876 /* RDH is read-only for 82576, only test RDT. */
877 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
878 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
879 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
880 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 },
881 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
882 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
883 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
884 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
885 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
886 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
887 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
888 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
889 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
890 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
891 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
892 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
893 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
894 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
895 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
896 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
897 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
898 { E1000_MTA, 0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
899 { 0, 0, 0, 0 }
900 };
901
902 /* 82575 register test */
903 static struct igb_reg_test reg_test_82575[] = {
904 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
905 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
906 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
907 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
908 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
909 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
910 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
911 /* Enable all four RX queues before testing. */
912 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
913 /* RDH is read-only for 82575, only test RDT. */
914 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
915 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
916 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
917 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
918 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
919 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
920 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
921 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
922 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
923 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
924 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
925 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
926 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
927 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
928 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
929 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
930 { 0, 0, 0, 0 }
931 };
932
933 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
934 int reg, u32 mask, u32 write)
935 {
936 struct e1000_hw *hw = &adapter->hw;
937 u32 pat, val;
938 u32 _test[] =
939 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
940 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
941 wr32(reg, (_test[pat] & write));
942 val = rd32(reg);
943 if (val != (_test[pat] & write & mask)) {
944 dev_err(&adapter->pdev->dev, "pattern test reg %04X "
945 "failed: got 0x%08X expected 0x%08X\n",
946 reg, val, (_test[pat] & write & mask));
947 *data = reg;
948 return 1;
949 }
950 }
951 return 0;
952 }
953
954 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
955 int reg, u32 mask, u32 write)
956 {
957 struct e1000_hw *hw = &adapter->hw;
958 u32 val;
959 wr32(reg, write & mask);
960 val = rd32(reg);
961 if ((write & mask) != (val & mask)) {
962 dev_err(&adapter->pdev->dev, "set/check reg %04X test failed:"
963 " got 0x%08X expected 0x%08X\n", reg,
964 (val & mask), (write & mask));
965 *data = reg;
966 return 1;
967 }
968 return 0;
969 }
970
971 #define REG_PATTERN_TEST(reg, mask, write) \
972 do { \
973 if (reg_pattern_test(adapter, data, reg, mask, write)) \
974 return 1; \
975 } while (0)
976
977 #define REG_SET_AND_CHECK(reg, mask, write) \
978 do { \
979 if (reg_set_and_check(adapter, data, reg, mask, write)) \
980 return 1; \
981 } while (0)
982
983 static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
984 {
985 struct e1000_hw *hw = &adapter->hw;
986 struct igb_reg_test *test;
987 u32 value, before, after;
988 u32 i, toggle;
989
990 toggle = 0x7FFFF3FF;
991
992 switch (adapter->hw.mac.type) {
993 case e1000_82576:
994 test = reg_test_82576;
995 break;
996 default:
997 test = reg_test_82575;
998 break;
999 }
1000
1001 /* Because the status register is such a special case,
1002 * we handle it separately from the rest of the register
1003 * tests. Some bits are read-only, some toggle, and some
1004 * are writable on newer MACs.
1005 */
1006 before = rd32(E1000_STATUS);
1007 value = (rd32(E1000_STATUS) & toggle);
1008 wr32(E1000_STATUS, toggle);
1009 after = rd32(E1000_STATUS) & toggle;
1010 if (value != after) {
1011 dev_err(&adapter->pdev->dev, "failed STATUS register test "
1012 "got: 0x%08X expected: 0x%08X\n", after, value);
1013 *data = 1;
1014 return 1;
1015 }
1016 /* restore previous status */
1017 wr32(E1000_STATUS, before);
1018
1019 /* Perform the remainder of the register test, looping through
1020 * the test table until we either fail or reach the null entry.
1021 */
1022 while (test->reg) {
1023 for (i = 0; i < test->array_len; i++) {
1024 switch (test->test_type) {
1025 case PATTERN_TEST:
1026 REG_PATTERN_TEST(test->reg +
1027 (i * test->reg_offset),
1028 test->mask,
1029 test->write);
1030 break;
1031 case SET_READ_TEST:
1032 REG_SET_AND_CHECK(test->reg +
1033 (i * test->reg_offset),
1034 test->mask,
1035 test->write);
1036 break;
1037 case WRITE_NO_TEST:
1038 writel(test->write,
1039 (adapter->hw.hw_addr + test->reg)
1040 + (i * test->reg_offset));
1041 break;
1042 case TABLE32_TEST:
1043 REG_PATTERN_TEST(test->reg + (i * 4),
1044 test->mask,
1045 test->write);
1046 break;
1047 case TABLE64_TEST_LO:
1048 REG_PATTERN_TEST(test->reg + (i * 8),
1049 test->mask,
1050 test->write);
1051 break;
1052 case TABLE64_TEST_HI:
1053 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1054 test->mask,
1055 test->write);
1056 break;
1057 }
1058 }
1059 test++;
1060 }
1061
1062 *data = 0;
1063 return 0;
1064 }
1065
1066 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1067 {
1068 u16 temp;
1069 u16 checksum = 0;
1070 u16 i;
1071
1072 *data = 0;
1073 /* Read and add up the contents of the EEPROM */
1074 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1075 if ((adapter->hw.nvm.ops.read(&adapter->hw, i, 1, &temp))
1076 < 0) {
1077 *data = 1;
1078 break;
1079 }
1080 checksum += temp;
1081 }
1082
1083 /* If Checksum is not Correct return error else test passed */
1084 if ((checksum != (u16) NVM_SUM) && !(*data))
1085 *data = 2;
1086
1087 return *data;
1088 }
1089
1090 static irqreturn_t igb_test_intr(int irq, void *data)
1091 {
1092 struct net_device *netdev = (struct net_device *) data;
1093 struct igb_adapter *adapter = netdev_priv(netdev);
1094 struct e1000_hw *hw = &adapter->hw;
1095
1096 adapter->test_icr |= rd32(E1000_ICR);
1097
1098 return IRQ_HANDLED;
1099 }
1100
1101 static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1102 {
1103 struct e1000_hw *hw = &adapter->hw;
1104 struct net_device *netdev = adapter->netdev;
1105 u32 mask, ics_mask, i = 0, shared_int = true;
1106 u32 irq = adapter->pdev->irq;
1107
1108 *data = 0;
1109
1110 /* Hook up test interrupt handler just for this test */
1111 if (adapter->msix_entries)
1112 /* NOTE: we don't test MSI-X interrupts here, yet */
1113 return 0;
1114
1115 if (adapter->flags & IGB_FLAG_HAS_MSI) {
1116 shared_int = false;
1117 if (request_irq(irq, &igb_test_intr, 0, netdev->name, netdev)) {
1118 *data = 1;
1119 return -1;
1120 }
1121 } else if (!request_irq(irq, &igb_test_intr, IRQF_PROBE_SHARED,
1122 netdev->name, netdev)) {
1123 shared_int = false;
1124 } else if (request_irq(irq, &igb_test_intr, IRQF_SHARED,
1125 netdev->name, netdev)) {
1126 *data = 1;
1127 return -1;
1128 }
1129 dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1130 (shared_int ? "shared" : "unshared"));
1131 /* Disable all the interrupts */
1132 wr32(E1000_IMC, 0xFFFFFFFF);
1133 msleep(10);
1134
1135 /* Define all writable bits for ICS */
1136 switch(hw->mac.type) {
1137 case e1000_82575:
1138 ics_mask = 0x37F47EDD;
1139 break;
1140 case e1000_82576:
1141 ics_mask = 0x77D4FBFD;
1142 break;
1143 default:
1144 ics_mask = 0x7FFFFFFF;
1145 break;
1146 }
1147
1148 /* Test each interrupt */
1149 for (; i < 31; i++) {
1150 /* Interrupt to test */
1151 mask = 1 << i;
1152
1153 if (!(mask & ics_mask))
1154 continue;
1155
1156 if (!shared_int) {
1157 /* Disable the interrupt to be reported in
1158 * the cause register and then force the same
1159 * interrupt and see if one gets posted. If
1160 * an interrupt was posted to the bus, the
1161 * test failed.
1162 */
1163 adapter->test_icr = 0;
1164
1165 /* Flush any pending interrupts */
1166 wr32(E1000_ICR, ~0);
1167
1168 wr32(E1000_IMC, mask);
1169 wr32(E1000_ICS, mask);
1170 msleep(10);
1171
1172 if (adapter->test_icr & mask) {
1173 *data = 3;
1174 break;
1175 }
1176 }
1177
1178 /* Enable the interrupt to be reported in
1179 * the cause register and then force the same
1180 * interrupt and see if one gets posted. If
1181 * an interrupt was not posted to the bus, the
1182 * test failed.
1183 */
1184 adapter->test_icr = 0;
1185
1186 /* Flush any pending interrupts */
1187 wr32(E1000_ICR, ~0);
1188
1189 wr32(E1000_IMS, mask);
1190 wr32(E1000_ICS, mask);
1191 msleep(10);
1192
1193 if (!(adapter->test_icr & mask)) {
1194 *data = 4;
1195 break;
1196 }
1197
1198 if (!shared_int) {
1199 /* Disable the other interrupts to be reported in
1200 * the cause register and then force the other
1201 * interrupts and see if any get posted. If
1202 * an interrupt was posted to the bus, the
1203 * test failed.
1204 */
1205 adapter->test_icr = 0;
1206
1207 /* Flush any pending interrupts */
1208 wr32(E1000_ICR, ~0);
1209
1210 wr32(E1000_IMC, ~mask);
1211 wr32(E1000_ICS, ~mask);
1212 msleep(10);
1213
1214 if (adapter->test_icr & mask) {
1215 *data = 5;
1216 break;
1217 }
1218 }
1219 }
1220
1221 /* Disable all the interrupts */
1222 wr32(E1000_IMC, ~0);
1223 msleep(10);
1224
1225 /* Unhook test interrupt handler */
1226 free_irq(irq, netdev);
1227
1228 return *data;
1229 }
1230
1231 static void igb_free_desc_rings(struct igb_adapter *adapter)
1232 {
1233 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1234 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1235 struct pci_dev *pdev = adapter->pdev;
1236 int i;
1237
1238 if (tx_ring->desc && tx_ring->buffer_info) {
1239 for (i = 0; i < tx_ring->count; i++) {
1240 struct igb_buffer *buf = &(tx_ring->buffer_info[i]);
1241 if (buf->dma)
1242 pci_unmap_single(pdev, buf->dma, buf->length,
1243 PCI_DMA_TODEVICE);
1244 if (buf->skb)
1245 dev_kfree_skb(buf->skb);
1246 }
1247 }
1248
1249 if (rx_ring->desc && rx_ring->buffer_info) {
1250 for (i = 0; i < rx_ring->count; i++) {
1251 struct igb_buffer *buf = &(rx_ring->buffer_info[i]);
1252 if (buf->dma)
1253 pci_unmap_single(pdev, buf->dma,
1254 IGB_RXBUFFER_2048,
1255 PCI_DMA_FROMDEVICE);
1256 if (buf->skb)
1257 dev_kfree_skb(buf->skb);
1258 }
1259 }
1260
1261 if (tx_ring->desc) {
1262 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc,
1263 tx_ring->dma);
1264 tx_ring->desc = NULL;
1265 }
1266 if (rx_ring->desc) {
1267 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc,
1268 rx_ring->dma);
1269 rx_ring->desc = NULL;
1270 }
1271
1272 kfree(tx_ring->buffer_info);
1273 tx_ring->buffer_info = NULL;
1274 kfree(rx_ring->buffer_info);
1275 rx_ring->buffer_info = NULL;
1276
1277 return;
1278 }
1279
1280 static int igb_setup_desc_rings(struct igb_adapter *adapter)
1281 {
1282 struct e1000_hw *hw = &adapter->hw;
1283 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1284 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1285 struct pci_dev *pdev = adapter->pdev;
1286 struct igb_buffer *buffer_info;
1287 u32 rctl;
1288 int i, ret_val;
1289
1290 /* Setup Tx descriptor ring and Tx buffers */
1291
1292 if (!tx_ring->count)
1293 tx_ring->count = IGB_DEFAULT_TXD;
1294
1295 tx_ring->buffer_info = kcalloc(tx_ring->count,
1296 sizeof(struct igb_buffer),
1297 GFP_KERNEL);
1298 if (!tx_ring->buffer_info) {
1299 ret_val = 1;
1300 goto err_nomem;
1301 }
1302
1303 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
1304 tx_ring->size = ALIGN(tx_ring->size, 4096);
1305 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1306 &tx_ring->dma);
1307 if (!tx_ring->desc) {
1308 ret_val = 2;
1309 goto err_nomem;
1310 }
1311 tx_ring->next_to_use = tx_ring->next_to_clean = 0;
1312
1313 wr32(E1000_TDBAL(0),
1314 ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
1315 wr32(E1000_TDBAH(0), ((u64) tx_ring->dma >> 32));
1316 wr32(E1000_TDLEN(0),
1317 tx_ring->count * sizeof(union e1000_adv_tx_desc));
1318 wr32(E1000_TDH(0), 0);
1319 wr32(E1000_TDT(0), 0);
1320 wr32(E1000_TCTL,
1321 E1000_TCTL_PSP | E1000_TCTL_EN |
1322 E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT |
1323 E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT);
1324
1325 for (i = 0; i < tx_ring->count; i++) {
1326 union e1000_adv_tx_desc *tx_desc;
1327 struct sk_buff *skb;
1328 unsigned int size = 1024;
1329
1330 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
1331 skb = alloc_skb(size, GFP_KERNEL);
1332 if (!skb) {
1333 ret_val = 3;
1334 goto err_nomem;
1335 }
1336 skb_put(skb, size);
1337 buffer_info = &tx_ring->buffer_info[i];
1338 buffer_info->skb = skb;
1339 buffer_info->length = skb->len;
1340 buffer_info->dma = pci_map_single(pdev, skb->data, skb->len,
1341 PCI_DMA_TODEVICE);
1342 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
1343 tx_desc->read.olinfo_status = cpu_to_le32(skb->len) <<
1344 E1000_ADVTXD_PAYLEN_SHIFT;
1345 tx_desc->read.cmd_type_len = cpu_to_le32(skb->len);
1346 tx_desc->read.cmd_type_len |= cpu_to_le32(E1000_TXD_CMD_EOP |
1347 E1000_TXD_CMD_IFCS |
1348 E1000_TXD_CMD_RS |
1349 E1000_ADVTXD_DTYP_DATA |
1350 E1000_ADVTXD_DCMD_DEXT);
1351 }
1352
1353 /* Setup Rx descriptor ring and Rx buffers */
1354
1355 if (!rx_ring->count)
1356 rx_ring->count = IGB_DEFAULT_RXD;
1357
1358 rx_ring->buffer_info = kcalloc(rx_ring->count,
1359 sizeof(struct igb_buffer),
1360 GFP_KERNEL);
1361 if (!rx_ring->buffer_info) {
1362 ret_val = 4;
1363 goto err_nomem;
1364 }
1365
1366 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
1367 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1368 &rx_ring->dma);
1369 if (!rx_ring->desc) {
1370 ret_val = 5;
1371 goto err_nomem;
1372 }
1373 rx_ring->next_to_use = rx_ring->next_to_clean = 0;
1374
1375 rctl = rd32(E1000_RCTL);
1376 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1377 wr32(E1000_RDBAL(0),
1378 ((u64) rx_ring->dma & 0xFFFFFFFF));
1379 wr32(E1000_RDBAH(0),
1380 ((u64) rx_ring->dma >> 32));
1381 wr32(E1000_RDLEN(0), rx_ring->size);
1382 wr32(E1000_RDH(0), 0);
1383 wr32(E1000_RDT(0), 0);
1384 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1385 rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
1386 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1387 wr32(E1000_RCTL, rctl);
1388 wr32(E1000_SRRCTL(0), E1000_SRRCTL_DESCTYPE_ADV_ONEBUF);
1389
1390 for (i = 0; i < rx_ring->count; i++) {
1391 union e1000_adv_rx_desc *rx_desc;
1392 struct sk_buff *skb;
1393
1394 buffer_info = &rx_ring->buffer_info[i];
1395 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
1396 skb = alloc_skb(IGB_RXBUFFER_2048 + NET_IP_ALIGN,
1397 GFP_KERNEL);
1398 if (!skb) {
1399 ret_val = 6;
1400 goto err_nomem;
1401 }
1402 skb_reserve(skb, NET_IP_ALIGN);
1403 buffer_info->skb = skb;
1404 buffer_info->dma = pci_map_single(pdev, skb->data,
1405 IGB_RXBUFFER_2048,
1406 PCI_DMA_FROMDEVICE);
1407 rx_desc->read.pkt_addr = cpu_to_le64(buffer_info->dma);
1408 memset(skb->data, 0x00, skb->len);
1409 }
1410
1411 return 0;
1412
1413 err_nomem:
1414 igb_free_desc_rings(adapter);
1415 return ret_val;
1416 }
1417
1418 static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1419 {
1420 struct e1000_hw *hw = &adapter->hw;
1421
1422 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1423 igb_write_phy_reg(hw, 29, 0x001F);
1424 igb_write_phy_reg(hw, 30, 0x8FFC);
1425 igb_write_phy_reg(hw, 29, 0x001A);
1426 igb_write_phy_reg(hw, 30, 0x8FF0);
1427 }
1428
1429 static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1430 {
1431 struct e1000_hw *hw = &adapter->hw;
1432 u32 ctrl_reg = 0;
1433
1434 hw->mac.autoneg = false;
1435
1436 if (hw->phy.type == e1000_phy_m88) {
1437 /* Auto-MDI/MDIX Off */
1438 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1439 /* reset to update Auto-MDI/MDIX */
1440 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1441 /* autoneg off */
1442 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1443 }
1444
1445 ctrl_reg = rd32(E1000_CTRL);
1446
1447 /* force 1000, set loopback */
1448 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1449
1450 /* Now set up the MAC to the same speed/duplex as the PHY. */
1451 ctrl_reg = rd32(E1000_CTRL);
1452 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1453 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1454 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1455 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1456 E1000_CTRL_FD | /* Force Duplex to FULL */
1457 E1000_CTRL_SLU); /* Set link up enable bit */
1458
1459 if (hw->phy.type == e1000_phy_m88)
1460 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1461
1462 wr32(E1000_CTRL, ctrl_reg);
1463
1464 /* Disable the receiver on the PHY so when a cable is plugged in, the
1465 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1466 */
1467 if (hw->phy.type == e1000_phy_m88)
1468 igb_phy_disable_receiver(adapter);
1469
1470 udelay(500);
1471
1472 return 0;
1473 }
1474
1475 static int igb_set_phy_loopback(struct igb_adapter *adapter)
1476 {
1477 return igb_integrated_phy_loopback(adapter);
1478 }
1479
1480 static int igb_setup_loopback_test(struct igb_adapter *adapter)
1481 {
1482 struct e1000_hw *hw = &adapter->hw;
1483 u32 reg;
1484
1485 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1486 reg = rd32(E1000_RCTL);
1487 reg |= E1000_RCTL_LBM_TCVR;
1488 wr32(E1000_RCTL, reg);
1489
1490 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1491
1492 reg = rd32(E1000_CTRL);
1493 reg &= ~(E1000_CTRL_RFCE |
1494 E1000_CTRL_TFCE |
1495 E1000_CTRL_LRST);
1496 reg |= E1000_CTRL_SLU |
1497 E1000_CTRL_FD;
1498 wr32(E1000_CTRL, reg);
1499
1500 /* Unset switch control to serdes energy detect */
1501 reg = rd32(E1000_CONNSW);
1502 reg &= ~E1000_CONNSW_ENRGSRC;
1503 wr32(E1000_CONNSW, reg);
1504
1505 /* Set PCS register for forced speed */
1506 reg = rd32(E1000_PCS_LCTL);
1507 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/
1508 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1509 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1510 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1511 E1000_PCS_LCTL_FSD | /* Force Speed */
1512 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1513 wr32(E1000_PCS_LCTL, reg);
1514
1515 return 0;
1516 } else if (hw->phy.media_type == e1000_media_type_copper) {
1517 return igb_set_phy_loopback(adapter);
1518 }
1519
1520 return 7;
1521 }
1522
1523 static void igb_loopback_cleanup(struct igb_adapter *adapter)
1524 {
1525 struct e1000_hw *hw = &adapter->hw;
1526 u32 rctl;
1527 u16 phy_reg;
1528
1529 rctl = rd32(E1000_RCTL);
1530 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1531 wr32(E1000_RCTL, rctl);
1532
1533 hw->mac.autoneg = true;
1534 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
1535 if (phy_reg & MII_CR_LOOPBACK) {
1536 phy_reg &= ~MII_CR_LOOPBACK;
1537 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
1538 igb_phy_sw_reset(hw);
1539 }
1540 }
1541
1542 static void igb_create_lbtest_frame(struct sk_buff *skb,
1543 unsigned int frame_size)
1544 {
1545 memset(skb->data, 0xFF, frame_size);
1546 frame_size &= ~1;
1547 memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1548 memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1549 memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1550 }
1551
1552 static int igb_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
1553 {
1554 frame_size &= ~1;
1555 if (*(skb->data + 3) == 0xFF)
1556 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1557 (*(skb->data + frame_size / 2 + 12) == 0xAF))
1558 return 0;
1559 return 13;
1560 }
1561
1562 static int igb_run_loopback_test(struct igb_adapter *adapter)
1563 {
1564 struct e1000_hw *hw = &adapter->hw;
1565 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1566 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1567 struct pci_dev *pdev = adapter->pdev;
1568 int i, j, k, l, lc, good_cnt;
1569 int ret_val = 0;
1570 unsigned long time;
1571
1572 wr32(E1000_RDT(0), rx_ring->count - 1);
1573
1574 /* Calculate the loop count based on the largest descriptor ring
1575 * The idea is to wrap the largest ring a number of times using 64
1576 * send/receive pairs during each loop
1577 */
1578
1579 if (rx_ring->count <= tx_ring->count)
1580 lc = ((tx_ring->count / 64) * 2) + 1;
1581 else
1582 lc = ((rx_ring->count / 64) * 2) + 1;
1583
1584 k = l = 0;
1585 for (j = 0; j <= lc; j++) { /* loop count loop */
1586 for (i = 0; i < 64; i++) { /* send the packets */
1587 igb_create_lbtest_frame(tx_ring->buffer_info[k].skb,
1588 1024);
1589 pci_dma_sync_single_for_device(pdev,
1590 tx_ring->buffer_info[k].dma,
1591 tx_ring->buffer_info[k].length,
1592 PCI_DMA_TODEVICE);
1593 k++;
1594 if (k == tx_ring->count)
1595 k = 0;
1596 }
1597 wr32(E1000_TDT(0), k);
1598 msleep(200);
1599 time = jiffies; /* set the start time for the receive */
1600 good_cnt = 0;
1601 do { /* receive the sent packets */
1602 pci_dma_sync_single_for_cpu(pdev,
1603 rx_ring->buffer_info[l].dma,
1604 IGB_RXBUFFER_2048,
1605 PCI_DMA_FROMDEVICE);
1606
1607 ret_val = igb_check_lbtest_frame(
1608 rx_ring->buffer_info[l].skb, 1024);
1609 if (!ret_val)
1610 good_cnt++;
1611 l++;
1612 if (l == rx_ring->count)
1613 l = 0;
1614 /* time + 20 msecs (200 msecs on 2.4) is more than
1615 * enough time to complete the receives, if it's
1616 * exceeded, break and error off
1617 */
1618 } while (good_cnt < 64 && jiffies < (time + 20));
1619 if (good_cnt != 64) {
1620 ret_val = 13; /* ret_val is the same as mis-compare */
1621 break;
1622 }
1623 if (jiffies >= (time + 20)) {
1624 ret_val = 14; /* error code for time out error */
1625 break;
1626 }
1627 } /* end loop count loop */
1628 return ret_val;
1629 }
1630
1631 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1632 {
1633 /* PHY loopback cannot be performed if SoL/IDER
1634 * sessions are active */
1635 if (igb_check_reset_block(&adapter->hw)) {
1636 dev_err(&adapter->pdev->dev,
1637 "Cannot do PHY loopback test "
1638 "when SoL/IDER is active.\n");
1639 *data = 0;
1640 goto out;
1641 }
1642 *data = igb_setup_desc_rings(adapter);
1643 if (*data)
1644 goto out;
1645 *data = igb_setup_loopback_test(adapter);
1646 if (*data)
1647 goto err_loopback;
1648 *data = igb_run_loopback_test(adapter);
1649 igb_loopback_cleanup(adapter);
1650
1651 err_loopback:
1652 igb_free_desc_rings(adapter);
1653 out:
1654 return *data;
1655 }
1656
1657 static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1658 {
1659 struct e1000_hw *hw = &adapter->hw;
1660 *data = 0;
1661 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1662 int i = 0;
1663 hw->mac.serdes_has_link = false;
1664
1665 /* On some blade server designs, link establishment
1666 * could take as long as 2-3 minutes */
1667 do {
1668 hw->mac.ops.check_for_link(&adapter->hw);
1669 if (hw->mac.serdes_has_link)
1670 return *data;
1671 msleep(20);
1672 } while (i++ < 3750);
1673
1674 *data = 1;
1675 } else {
1676 hw->mac.ops.check_for_link(&adapter->hw);
1677 if (hw->mac.autoneg)
1678 msleep(4000);
1679
1680 if (!(rd32(E1000_STATUS) &
1681 E1000_STATUS_LU))
1682 *data = 1;
1683 }
1684 return *data;
1685 }
1686
1687 static void igb_diag_test(struct net_device *netdev,
1688 struct ethtool_test *eth_test, u64 *data)
1689 {
1690 struct igb_adapter *adapter = netdev_priv(netdev);
1691 u16 autoneg_advertised;
1692 u8 forced_speed_duplex, autoneg;
1693 bool if_running = netif_running(netdev);
1694
1695 set_bit(__IGB_TESTING, &adapter->state);
1696 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1697 /* Offline tests */
1698
1699 /* save speed, duplex, autoneg settings */
1700 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1701 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1702 autoneg = adapter->hw.mac.autoneg;
1703
1704 dev_info(&adapter->pdev->dev, "offline testing starting\n");
1705
1706 /* Link test performed before hardware reset so autoneg doesn't
1707 * interfere with test result */
1708 if (igb_link_test(adapter, &data[4]))
1709 eth_test->flags |= ETH_TEST_FL_FAILED;
1710
1711 if (if_running)
1712 /* indicate we're in test mode */
1713 dev_close(netdev);
1714 else
1715 igb_reset(adapter);
1716
1717 if (igb_reg_test(adapter, &data[0]))
1718 eth_test->flags |= ETH_TEST_FL_FAILED;
1719
1720 igb_reset(adapter);
1721 if (igb_eeprom_test(adapter, &data[1]))
1722 eth_test->flags |= ETH_TEST_FL_FAILED;
1723
1724 igb_reset(adapter);
1725 if (igb_intr_test(adapter, &data[2]))
1726 eth_test->flags |= ETH_TEST_FL_FAILED;
1727
1728 igb_reset(adapter);
1729 if (igb_loopback_test(adapter, &data[3]))
1730 eth_test->flags |= ETH_TEST_FL_FAILED;
1731
1732 /* restore speed, duplex, autoneg settings */
1733 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
1734 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
1735 adapter->hw.mac.autoneg = autoneg;
1736
1737 /* force this routine to wait until autoneg complete/timeout */
1738 adapter->hw.phy.autoneg_wait_to_complete = true;
1739 igb_reset(adapter);
1740 adapter->hw.phy.autoneg_wait_to_complete = false;
1741
1742 clear_bit(__IGB_TESTING, &adapter->state);
1743 if (if_running)
1744 dev_open(netdev);
1745 } else {
1746 dev_info(&adapter->pdev->dev, "online testing starting\n");
1747 /* Online tests */
1748 if (igb_link_test(adapter, &data[4]))
1749 eth_test->flags |= ETH_TEST_FL_FAILED;
1750
1751 /* Online tests aren't run; pass by default */
1752 data[0] = 0;
1753 data[1] = 0;
1754 data[2] = 0;
1755 data[3] = 0;
1756
1757 clear_bit(__IGB_TESTING, &adapter->state);
1758 }
1759 msleep_interruptible(4 * 1000);
1760 }
1761
1762 static int igb_wol_exclusion(struct igb_adapter *adapter,
1763 struct ethtool_wolinfo *wol)
1764 {
1765 struct e1000_hw *hw = &adapter->hw;
1766 int retval = 1; /* fail by default */
1767
1768 switch (hw->device_id) {
1769 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1770 /* WoL not supported */
1771 wol->supported = 0;
1772 break;
1773 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1774 case E1000_DEV_ID_82576_FIBER:
1775 case E1000_DEV_ID_82576_SERDES:
1776 /* Wake events not supported on port B */
1777 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) {
1778 wol->supported = 0;
1779 break;
1780 }
1781 /* return success for non excluded adapter ports */
1782 retval = 0;
1783 break;
1784 case E1000_DEV_ID_82576_QUAD_COPPER:
1785 /* quad port adapters only support WoL on port A */
1786 if (!(adapter->flags & IGB_FLAG_QUAD_PORT_A)) {
1787 wol->supported = 0;
1788 break;
1789 }
1790 /* return success for non excluded adapter ports */
1791 retval = 0;
1792 break;
1793 default:
1794 /* dual port cards only support WoL on port A from now on
1795 * unless it was enabled in the eeprom for port B
1796 * so exclude FUNC_1 ports from having WoL enabled */
1797 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1 &&
1798 !adapter->eeprom_wol) {
1799 wol->supported = 0;
1800 break;
1801 }
1802
1803 retval = 0;
1804 }
1805
1806 return retval;
1807 }
1808
1809 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1810 {
1811 struct igb_adapter *adapter = netdev_priv(netdev);
1812
1813 wol->supported = WAKE_UCAST | WAKE_MCAST |
1814 WAKE_BCAST | WAKE_MAGIC;
1815 wol->wolopts = 0;
1816
1817 /* this function will set ->supported = 0 and return 1 if wol is not
1818 * supported by this hardware */
1819 if (igb_wol_exclusion(adapter, wol) ||
1820 !device_can_wakeup(&adapter->pdev->dev))
1821 return;
1822
1823 /* apply any specific unsupported masks here */
1824 switch (adapter->hw.device_id) {
1825 default:
1826 break;
1827 }
1828
1829 if (adapter->wol & E1000_WUFC_EX)
1830 wol->wolopts |= WAKE_UCAST;
1831 if (adapter->wol & E1000_WUFC_MC)
1832 wol->wolopts |= WAKE_MCAST;
1833 if (adapter->wol & E1000_WUFC_BC)
1834 wol->wolopts |= WAKE_BCAST;
1835 if (adapter->wol & E1000_WUFC_MAG)
1836 wol->wolopts |= WAKE_MAGIC;
1837
1838 return;
1839 }
1840
1841 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1842 {
1843 struct igb_adapter *adapter = netdev_priv(netdev);
1844
1845 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1846 return -EOPNOTSUPP;
1847
1848 if (igb_wol_exclusion(adapter, wol) ||
1849 !device_can_wakeup(&adapter->pdev->dev))
1850 return wol->wolopts ? -EOPNOTSUPP : 0;
1851
1852 /* these settings will always override what we currently have */
1853 adapter->wol = 0;
1854
1855 if (wol->wolopts & WAKE_UCAST)
1856 adapter->wol |= E1000_WUFC_EX;
1857 if (wol->wolopts & WAKE_MCAST)
1858 adapter->wol |= E1000_WUFC_MC;
1859 if (wol->wolopts & WAKE_BCAST)
1860 adapter->wol |= E1000_WUFC_BC;
1861 if (wol->wolopts & WAKE_MAGIC)
1862 adapter->wol |= E1000_WUFC_MAG;
1863
1864 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1865
1866 return 0;
1867 }
1868
1869 /* bit defines for adapter->led_status */
1870 #define IGB_LED_ON 0
1871
1872 static int igb_phys_id(struct net_device *netdev, u32 data)
1873 {
1874 struct igb_adapter *adapter = netdev_priv(netdev);
1875 struct e1000_hw *hw = &adapter->hw;
1876
1877 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
1878 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
1879
1880 igb_blink_led(hw);
1881 msleep_interruptible(data * 1000);
1882
1883 igb_led_off(hw);
1884 clear_bit(IGB_LED_ON, &adapter->led_status);
1885 igb_cleanup_led(hw);
1886
1887 return 0;
1888 }
1889
1890 static int igb_set_coalesce(struct net_device *netdev,
1891 struct ethtool_coalesce *ec)
1892 {
1893 struct igb_adapter *adapter = netdev_priv(netdev);
1894 struct e1000_hw *hw = &adapter->hw;
1895 int i;
1896
1897 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1898 ((ec->rx_coalesce_usecs > 3) &&
1899 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
1900 (ec->rx_coalesce_usecs == 2))
1901 return -EINVAL;
1902
1903 /* convert to rate of irq's per second */
1904 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3) {
1905 adapter->itr_setting = ec->rx_coalesce_usecs;
1906 adapter->itr = IGB_START_ITR;
1907 } else {
1908 adapter->itr_setting = ec->rx_coalesce_usecs << 2;
1909 adapter->itr = adapter->itr_setting;
1910 }
1911
1912 for (i = 0; i < adapter->num_rx_queues; i++)
1913 wr32(adapter->rx_ring[i].itr_register, adapter->itr);
1914
1915 return 0;
1916 }
1917
1918 static int igb_get_coalesce(struct net_device *netdev,
1919 struct ethtool_coalesce *ec)
1920 {
1921 struct igb_adapter *adapter = netdev_priv(netdev);
1922
1923 if (adapter->itr_setting <= 3)
1924 ec->rx_coalesce_usecs = adapter->itr_setting;
1925 else
1926 ec->rx_coalesce_usecs = adapter->itr_setting >> 2;
1927
1928 return 0;
1929 }
1930
1931
1932 static int igb_nway_reset(struct net_device *netdev)
1933 {
1934 struct igb_adapter *adapter = netdev_priv(netdev);
1935 if (netif_running(netdev))
1936 igb_reinit_locked(adapter);
1937 return 0;
1938 }
1939
1940 static int igb_get_sset_count(struct net_device *netdev, int sset)
1941 {
1942 switch (sset) {
1943 case ETH_SS_STATS:
1944 return IGB_STATS_LEN;
1945 case ETH_SS_TEST:
1946 return IGB_TEST_LEN;
1947 default:
1948 return -ENOTSUPP;
1949 }
1950 }
1951
1952 static void igb_get_ethtool_stats(struct net_device *netdev,
1953 struct ethtool_stats *stats, u64 *data)
1954 {
1955 struct igb_adapter *adapter = netdev_priv(netdev);
1956 u64 *queue_stat;
1957 int stat_count_tx = sizeof(struct igb_tx_queue_stats) / sizeof(u64);
1958 int stat_count_rx = sizeof(struct igb_rx_queue_stats) / sizeof(u64);
1959 int j;
1960 int i;
1961
1962 igb_update_stats(adapter);
1963 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
1964 char *p = (char *)adapter+igb_gstrings_stats[i].stat_offset;
1965 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
1966 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1967 }
1968 for (j = 0; j < adapter->num_tx_queues; j++) {
1969 int k;
1970 queue_stat = (u64 *)&adapter->tx_ring[j].tx_stats;
1971 for (k = 0; k < stat_count_tx; k++)
1972 data[i + k] = queue_stat[k];
1973 i += k;
1974 }
1975 for (j = 0; j < adapter->num_rx_queues; j++) {
1976 int k;
1977 queue_stat = (u64 *)&adapter->rx_ring[j].rx_stats;
1978 for (k = 0; k < stat_count_rx; k++)
1979 data[i + k] = queue_stat[k];
1980 i += k;
1981 }
1982 }
1983
1984 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
1985 {
1986 struct igb_adapter *adapter = netdev_priv(netdev);
1987 u8 *p = data;
1988 int i;
1989
1990 switch (stringset) {
1991 case ETH_SS_TEST:
1992 memcpy(data, *igb_gstrings_test,
1993 IGB_TEST_LEN*ETH_GSTRING_LEN);
1994 break;
1995 case ETH_SS_STATS:
1996 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
1997 memcpy(p, igb_gstrings_stats[i].stat_string,
1998 ETH_GSTRING_LEN);
1999 p += ETH_GSTRING_LEN;
2000 }
2001 for (i = 0; i < adapter->num_tx_queues; i++) {
2002 sprintf(p, "tx_queue_%u_packets", i);
2003 p += ETH_GSTRING_LEN;
2004 sprintf(p, "tx_queue_%u_bytes", i);
2005 p += ETH_GSTRING_LEN;
2006 }
2007 for (i = 0; i < adapter->num_rx_queues; i++) {
2008 sprintf(p, "rx_queue_%u_packets", i);
2009 p += ETH_GSTRING_LEN;
2010 sprintf(p, "rx_queue_%u_bytes", i);
2011 p += ETH_GSTRING_LEN;
2012 sprintf(p, "rx_queue_%u_drops", i);
2013 p += ETH_GSTRING_LEN;
2014 }
2015 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2016 break;
2017 }
2018 }
2019
2020 static const struct ethtool_ops igb_ethtool_ops = {
2021 .get_settings = igb_get_settings,
2022 .set_settings = igb_set_settings,
2023 .get_drvinfo = igb_get_drvinfo,
2024 .get_regs_len = igb_get_regs_len,
2025 .get_regs = igb_get_regs,
2026 .get_wol = igb_get_wol,
2027 .set_wol = igb_set_wol,
2028 .get_msglevel = igb_get_msglevel,
2029 .set_msglevel = igb_set_msglevel,
2030 .nway_reset = igb_nway_reset,
2031 .get_link = ethtool_op_get_link,
2032 .get_eeprom_len = igb_get_eeprom_len,
2033 .get_eeprom = igb_get_eeprom,
2034 .set_eeprom = igb_set_eeprom,
2035 .get_ringparam = igb_get_ringparam,
2036 .set_ringparam = igb_set_ringparam,
2037 .get_pauseparam = igb_get_pauseparam,
2038 .set_pauseparam = igb_set_pauseparam,
2039 .get_rx_csum = igb_get_rx_csum,
2040 .set_rx_csum = igb_set_rx_csum,
2041 .get_tx_csum = igb_get_tx_csum,
2042 .set_tx_csum = igb_set_tx_csum,
2043 .get_sg = ethtool_op_get_sg,
2044 .set_sg = ethtool_op_set_sg,
2045 .get_tso = ethtool_op_get_tso,
2046 .set_tso = igb_set_tso,
2047 .self_test = igb_diag_test,
2048 .get_strings = igb_get_strings,
2049 .phys_id = igb_phys_id,
2050 .get_sset_count = igb_get_sset_count,
2051 .get_ethtool_stats = igb_get_ethtool_stats,
2052 .get_coalesce = igb_get_coalesce,
2053 .set_coalesce = igb_set_coalesce,
2054 };
2055
2056 void igb_set_ethtool_ops(struct net_device *netdev)
2057 {
2058 SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);
2059 }
Linux kernel - Deliverables
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