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igb: add 82576 MAC support
[deliverable/linux.git] / drivers / net / igb / igb_ethtool.c
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 /* ethtool support for igb */
29
30 #include <linux/vmalloc.h>
31 #include <linux/netdevice.h>
32 #include <linux/pci.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
35 #include <linux/if_ether.h>
36 #include <linux/ethtool.h>
37
38 #include "igb.h"
39
40 struct igb_stats {
41 char stat_string[ETH_GSTRING_LEN];
42 int sizeof_stat;
43 int stat_offset;
44 };
45
46 #define IGB_STAT(m) FIELD_SIZEOF(struct igb_adapter, m), \
47 offsetof(struct igb_adapter, m)
48 static const struct igb_stats igb_gstrings_stats[] = {
49 { "rx_packets", IGB_STAT(stats.gprc) },
50 { "tx_packets", IGB_STAT(stats.gptc) },
51 { "rx_bytes", IGB_STAT(stats.gorc) },
52 { "tx_bytes", IGB_STAT(stats.gotc) },
53 { "rx_broadcast", IGB_STAT(stats.bprc) },
54 { "tx_broadcast", IGB_STAT(stats.bptc) },
55 { "rx_multicast", IGB_STAT(stats.mprc) },
56 { "tx_multicast", IGB_STAT(stats.mptc) },
57 { "rx_errors", IGB_STAT(net_stats.rx_errors) },
58 { "tx_errors", IGB_STAT(net_stats.tx_errors) },
59 { "tx_dropped", IGB_STAT(net_stats.tx_dropped) },
60 { "multicast", IGB_STAT(stats.mprc) },
61 { "collisions", IGB_STAT(stats.colc) },
62 { "rx_length_errors", IGB_STAT(net_stats.rx_length_errors) },
63 { "rx_over_errors", IGB_STAT(net_stats.rx_over_errors) },
64 { "rx_crc_errors", IGB_STAT(stats.crcerrs) },
65 { "rx_frame_errors", IGB_STAT(net_stats.rx_frame_errors) },
66 { "rx_no_buffer_count", IGB_STAT(stats.rnbc) },
67 { "rx_missed_errors", IGB_STAT(stats.mpc) },
68 { "tx_aborted_errors", IGB_STAT(stats.ecol) },
69 { "tx_carrier_errors", IGB_STAT(stats.tncrs) },
70 { "tx_fifo_errors", IGB_STAT(net_stats.tx_fifo_errors) },
71 { "tx_heartbeat_errors", IGB_STAT(net_stats.tx_heartbeat_errors) },
72 { "tx_window_errors", IGB_STAT(stats.latecol) },
73 { "tx_abort_late_coll", IGB_STAT(stats.latecol) },
74 { "tx_deferred_ok", IGB_STAT(stats.dc) },
75 { "tx_single_coll_ok", IGB_STAT(stats.scc) },
76 { "tx_multi_coll_ok", IGB_STAT(stats.mcc) },
77 { "tx_timeout_count", IGB_STAT(tx_timeout_count) },
78 { "tx_restart_queue", IGB_STAT(restart_queue) },
79 { "rx_long_length_errors", IGB_STAT(stats.roc) },
80 { "rx_short_length_errors", IGB_STAT(stats.ruc) },
81 { "rx_align_errors", IGB_STAT(stats.algnerrc) },
82 { "tx_tcp_seg_good", IGB_STAT(stats.tsctc) },
83 { "tx_tcp_seg_failed", IGB_STAT(stats.tsctfc) },
84 { "rx_flow_control_xon", IGB_STAT(stats.xonrxc) },
85 { "rx_flow_control_xoff", IGB_STAT(stats.xoffrxc) },
86 { "tx_flow_control_xon", IGB_STAT(stats.xontxc) },
87 { "tx_flow_control_xoff", IGB_STAT(stats.xofftxc) },
88 { "rx_long_byte_count", IGB_STAT(stats.gorc) },
89 { "rx_csum_offload_good", IGB_STAT(hw_csum_good) },
90 { "rx_csum_offload_errors", IGB_STAT(hw_csum_err) },
91 { "rx_header_split", IGB_STAT(rx_hdr_split) },
92 { "alloc_rx_buff_failed", IGB_STAT(alloc_rx_buff_failed) },
93 { "tx_smbus", IGB_STAT(stats.mgptc) },
94 { "rx_smbus", IGB_STAT(stats.mgprc) },
95 { "dropped_smbus", IGB_STAT(stats.mgpdc) },
96 };
97
98 #define IGB_QUEUE_STATS_LEN \
99 ((((struct igb_adapter *)netdev->priv)->num_rx_queues + \
100 ((struct igb_adapter *)netdev->priv)->num_tx_queues) * \
101 (sizeof(struct igb_queue_stats) / sizeof(u64)))
102 #define IGB_GLOBAL_STATS_LEN \
103 sizeof(igb_gstrings_stats) / sizeof(struct igb_stats)
104 #define IGB_STATS_LEN (IGB_GLOBAL_STATS_LEN + IGB_QUEUE_STATS_LEN)
105 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
106 "Register test (offline)", "Eeprom test (offline)",
107 "Interrupt test (offline)", "Loopback test (offline)",
108 "Link test (on/offline)"
109 };
110 #define IGB_TEST_LEN sizeof(igb_gstrings_test) / ETH_GSTRING_LEN
111
112 static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
113 {
114 struct igb_adapter *adapter = netdev_priv(netdev);
115 struct e1000_hw *hw = &adapter->hw;
116
117 if (hw->phy.media_type == e1000_media_type_copper) {
118
119 ecmd->supported = (SUPPORTED_10baseT_Half |
120 SUPPORTED_10baseT_Full |
121 SUPPORTED_100baseT_Half |
122 SUPPORTED_100baseT_Full |
123 SUPPORTED_1000baseT_Full|
124 SUPPORTED_Autoneg |
125 SUPPORTED_TP);
126 ecmd->advertising = ADVERTISED_TP;
127
128 if (hw->mac.autoneg == 1) {
129 ecmd->advertising |= ADVERTISED_Autoneg;
130 /* the e1000 autoneg seems to match ethtool nicely */
131 ecmd->advertising |= hw->phy.autoneg_advertised;
132 }
133
134 ecmd->port = PORT_TP;
135 ecmd->phy_address = hw->phy.addr;
136 } else {
137 ecmd->supported = (SUPPORTED_1000baseT_Full |
138 SUPPORTED_FIBRE |
139 SUPPORTED_Autoneg);
140
141 ecmd->advertising = (ADVERTISED_1000baseT_Full |
142 ADVERTISED_FIBRE |
143 ADVERTISED_Autoneg);
144
145 ecmd->port = PORT_FIBRE;
146 }
147
148 ecmd->transceiver = XCVR_INTERNAL;
149
150 if (rd32(E1000_STATUS) & E1000_STATUS_LU) {
151
152 adapter->hw.mac.ops.get_speed_and_duplex(hw,
153 &adapter->link_speed,
154 &adapter->link_duplex);
155 ecmd->speed = adapter->link_speed;
156
157 /* unfortunately FULL_DUPLEX != DUPLEX_FULL
158 * and HALF_DUPLEX != DUPLEX_HALF */
159
160 if (adapter->link_duplex == FULL_DUPLEX)
161 ecmd->duplex = DUPLEX_FULL;
162 else
163 ecmd->duplex = DUPLEX_HALF;
164 } else {
165 ecmd->speed = -1;
166 ecmd->duplex = -1;
167 }
168
169 ecmd->autoneg = ((hw->phy.media_type == e1000_media_type_fiber) ||
170 hw->mac.autoneg) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
171 return 0;
172 }
173
174 static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
175 {
176 struct igb_adapter *adapter = netdev_priv(netdev);
177 struct e1000_hw *hw = &adapter->hw;
178
179 /* When SoL/IDER sessions are active, autoneg/speed/duplex
180 * cannot be changed */
181 if (igb_check_reset_block(hw)) {
182 dev_err(&adapter->pdev->dev, "Cannot change link "
183 "characteristics when SoL/IDER is active.\n");
184 return -EINVAL;
185 }
186
187 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
188 msleep(1);
189
190 if (ecmd->autoneg == AUTONEG_ENABLE) {
191 hw->mac.autoneg = 1;
192 if (hw->phy.media_type == e1000_media_type_fiber)
193 hw->phy.autoneg_advertised = ADVERTISED_1000baseT_Full |
194 ADVERTISED_FIBRE |
195 ADVERTISED_Autoneg;
196 else
197 hw->phy.autoneg_advertised = ecmd->advertising |
198 ADVERTISED_TP |
199 ADVERTISED_Autoneg;
200 ecmd->advertising = hw->phy.autoneg_advertised;
201 } else
202 if (igb_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
203 clear_bit(__IGB_RESETTING, &adapter->state);
204 return -EINVAL;
205 }
206
207 /* reset the link */
208
209 if (netif_running(adapter->netdev)) {
210 igb_down(adapter);
211 igb_up(adapter);
212 } else
213 igb_reset(adapter);
214
215 clear_bit(__IGB_RESETTING, &adapter->state);
216 return 0;
217 }
218
219 static void igb_get_pauseparam(struct net_device *netdev,
220 struct ethtool_pauseparam *pause)
221 {
222 struct igb_adapter *adapter = netdev_priv(netdev);
223 struct e1000_hw *hw = &adapter->hw;
224
225 pause->autoneg =
226 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
227
228 if (hw->fc.type == e1000_fc_rx_pause)
229 pause->rx_pause = 1;
230 else if (hw->fc.type == e1000_fc_tx_pause)
231 pause->tx_pause = 1;
232 else if (hw->fc.type == e1000_fc_full) {
233 pause->rx_pause = 1;
234 pause->tx_pause = 1;
235 }
236 }
237
238 static int igb_set_pauseparam(struct net_device *netdev,
239 struct ethtool_pauseparam *pause)
240 {
241 struct igb_adapter *adapter = netdev_priv(netdev);
242 struct e1000_hw *hw = &adapter->hw;
243 int retval = 0;
244
245 adapter->fc_autoneg = pause->autoneg;
246
247 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
248 msleep(1);
249
250 if (pause->rx_pause && pause->tx_pause)
251 hw->fc.type = e1000_fc_full;
252 else if (pause->rx_pause && !pause->tx_pause)
253 hw->fc.type = e1000_fc_rx_pause;
254 else if (!pause->rx_pause && pause->tx_pause)
255 hw->fc.type = e1000_fc_tx_pause;
256 else if (!pause->rx_pause && !pause->tx_pause)
257 hw->fc.type = e1000_fc_none;
258
259 hw->fc.original_type = hw->fc.type;
260
261 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
262 if (netif_running(adapter->netdev)) {
263 igb_down(adapter);
264 igb_up(adapter);
265 } else
266 igb_reset(adapter);
267 } else
268 retval = ((hw->phy.media_type == e1000_media_type_fiber) ?
269 igb_setup_link(hw) : igb_force_mac_fc(hw));
270
271 clear_bit(__IGB_RESETTING, &adapter->state);
272 return retval;
273 }
274
275 static u32 igb_get_rx_csum(struct net_device *netdev)
276 {
277 struct igb_adapter *adapter = netdev_priv(netdev);
278 return adapter->rx_csum;
279 }
280
281 static int igb_set_rx_csum(struct net_device *netdev, u32 data)
282 {
283 struct igb_adapter *adapter = netdev_priv(netdev);
284 adapter->rx_csum = data;
285
286 return 0;
287 }
288
289 static u32 igb_get_tx_csum(struct net_device *netdev)
290 {
291 return (netdev->features & NETIF_F_HW_CSUM) != 0;
292 }
293
294 static int igb_set_tx_csum(struct net_device *netdev, u32 data)
295 {
296 if (data)
297 netdev->features |= NETIF_F_HW_CSUM;
298 else
299 netdev->features &= ~NETIF_F_HW_CSUM;
300
301 return 0;
302 }
303
304 static int igb_set_tso(struct net_device *netdev, u32 data)
305 {
306 struct igb_adapter *adapter = netdev_priv(netdev);
307
308 if (data)
309 netdev->features |= NETIF_F_TSO;
310 else
311 netdev->features &= ~NETIF_F_TSO;
312
313 if (data)
314 netdev->features |= NETIF_F_TSO6;
315 else
316 netdev->features &= ~NETIF_F_TSO6;
317
318 dev_info(&adapter->pdev->dev, "TSO is %s\n",
319 data ? "Enabled" : "Disabled");
320 return 0;
321 }
322
323 static u32 igb_get_msglevel(struct net_device *netdev)
324 {
325 struct igb_adapter *adapter = netdev_priv(netdev);
326 return adapter->msg_enable;
327 }
328
329 static void igb_set_msglevel(struct net_device *netdev, u32 data)
330 {
331 struct igb_adapter *adapter = netdev_priv(netdev);
332 adapter->msg_enable = data;
333 }
334
335 static int igb_get_regs_len(struct net_device *netdev)
336 {
337 #define IGB_REGS_LEN 551
338 return IGB_REGS_LEN * sizeof(u32);
339 }
340
341 static void igb_get_regs(struct net_device *netdev,
342 struct ethtool_regs *regs, void *p)
343 {
344 struct igb_adapter *adapter = netdev_priv(netdev);
345 struct e1000_hw *hw = &adapter->hw;
346 u32 *regs_buff = p;
347 u8 i;
348
349 memset(p, 0, IGB_REGS_LEN * sizeof(u32));
350
351 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
352
353 /* General Registers */
354 regs_buff[0] = rd32(E1000_CTRL);
355 regs_buff[1] = rd32(E1000_STATUS);
356 regs_buff[2] = rd32(E1000_CTRL_EXT);
357 regs_buff[3] = rd32(E1000_MDIC);
358 regs_buff[4] = rd32(E1000_SCTL);
359 regs_buff[5] = rd32(E1000_CONNSW);
360 regs_buff[6] = rd32(E1000_VET);
361 regs_buff[7] = rd32(E1000_LEDCTL);
362 regs_buff[8] = rd32(E1000_PBA);
363 regs_buff[9] = rd32(E1000_PBS);
364 regs_buff[10] = rd32(E1000_FRTIMER);
365 regs_buff[11] = rd32(E1000_TCPTIMER);
366
367 /* NVM Register */
368 regs_buff[12] = rd32(E1000_EECD);
369
370 /* Interrupt */
371 regs_buff[13] = rd32(E1000_EICR);
372 regs_buff[14] = rd32(E1000_EICS);
373 regs_buff[15] = rd32(E1000_EIMS);
374 regs_buff[16] = rd32(E1000_EIMC);
375 regs_buff[17] = rd32(E1000_EIAC);
376 regs_buff[18] = rd32(E1000_EIAM);
377 regs_buff[19] = rd32(E1000_ICR);
378 regs_buff[20] = rd32(E1000_ICS);
379 regs_buff[21] = rd32(E1000_IMS);
380 regs_buff[22] = rd32(E1000_IMC);
381 regs_buff[23] = rd32(E1000_IAC);
382 regs_buff[24] = rd32(E1000_IAM);
383 regs_buff[25] = rd32(E1000_IMIRVP);
384
385 /* Flow Control */
386 regs_buff[26] = rd32(E1000_FCAL);
387 regs_buff[27] = rd32(E1000_FCAH);
388 regs_buff[28] = rd32(E1000_FCTTV);
389 regs_buff[29] = rd32(E1000_FCRTL);
390 regs_buff[30] = rd32(E1000_FCRTH);
391 regs_buff[31] = rd32(E1000_FCRTV);
392
393 /* Receive */
394 regs_buff[32] = rd32(E1000_RCTL);
395 regs_buff[33] = rd32(E1000_RXCSUM);
396 regs_buff[34] = rd32(E1000_RLPML);
397 regs_buff[35] = rd32(E1000_RFCTL);
398 regs_buff[36] = rd32(E1000_MRQC);
399 regs_buff[37] = rd32(E1000_VMD_CTL);
400
401 /* Transmit */
402 regs_buff[38] = rd32(E1000_TCTL);
403 regs_buff[39] = rd32(E1000_TCTL_EXT);
404 regs_buff[40] = rd32(E1000_TIPG);
405 regs_buff[41] = rd32(E1000_DTXCTL);
406
407 /* Wake Up */
408 regs_buff[42] = rd32(E1000_WUC);
409 regs_buff[43] = rd32(E1000_WUFC);
410 regs_buff[44] = rd32(E1000_WUS);
411 regs_buff[45] = rd32(E1000_IPAV);
412 regs_buff[46] = rd32(E1000_WUPL);
413
414 /* MAC */
415 regs_buff[47] = rd32(E1000_PCS_CFG0);
416 regs_buff[48] = rd32(E1000_PCS_LCTL);
417 regs_buff[49] = rd32(E1000_PCS_LSTAT);
418 regs_buff[50] = rd32(E1000_PCS_ANADV);
419 regs_buff[51] = rd32(E1000_PCS_LPAB);
420 regs_buff[52] = rd32(E1000_PCS_NPTX);
421 regs_buff[53] = rd32(E1000_PCS_LPABNP);
422
423 /* Statistics */
424 regs_buff[54] = adapter->stats.crcerrs;
425 regs_buff[55] = adapter->stats.algnerrc;
426 regs_buff[56] = adapter->stats.symerrs;
427 regs_buff[57] = adapter->stats.rxerrc;
428 regs_buff[58] = adapter->stats.mpc;
429 regs_buff[59] = adapter->stats.scc;
430 regs_buff[60] = adapter->stats.ecol;
431 regs_buff[61] = adapter->stats.mcc;
432 regs_buff[62] = adapter->stats.latecol;
433 regs_buff[63] = adapter->stats.colc;
434 regs_buff[64] = adapter->stats.dc;
435 regs_buff[65] = adapter->stats.tncrs;
436 regs_buff[66] = adapter->stats.sec;
437 regs_buff[67] = adapter->stats.htdpmc;
438 regs_buff[68] = adapter->stats.rlec;
439 regs_buff[69] = adapter->stats.xonrxc;
440 regs_buff[70] = adapter->stats.xontxc;
441 regs_buff[71] = adapter->stats.xoffrxc;
442 regs_buff[72] = adapter->stats.xofftxc;
443 regs_buff[73] = adapter->stats.fcruc;
444 regs_buff[74] = adapter->stats.prc64;
445 regs_buff[75] = adapter->stats.prc127;
446 regs_buff[76] = adapter->stats.prc255;
447 regs_buff[77] = adapter->stats.prc511;
448 regs_buff[78] = adapter->stats.prc1023;
449 regs_buff[79] = adapter->stats.prc1522;
450 regs_buff[80] = adapter->stats.gprc;
451 regs_buff[81] = adapter->stats.bprc;
452 regs_buff[82] = adapter->stats.mprc;
453 regs_buff[83] = adapter->stats.gptc;
454 regs_buff[84] = adapter->stats.gorc;
455 regs_buff[86] = adapter->stats.gotc;
456 regs_buff[88] = adapter->stats.rnbc;
457 regs_buff[89] = adapter->stats.ruc;
458 regs_buff[90] = adapter->stats.rfc;
459 regs_buff[91] = adapter->stats.roc;
460 regs_buff[92] = adapter->stats.rjc;
461 regs_buff[93] = adapter->stats.mgprc;
462 regs_buff[94] = adapter->stats.mgpdc;
463 regs_buff[95] = adapter->stats.mgptc;
464 regs_buff[96] = adapter->stats.tor;
465 regs_buff[98] = adapter->stats.tot;
466 regs_buff[100] = adapter->stats.tpr;
467 regs_buff[101] = adapter->stats.tpt;
468 regs_buff[102] = adapter->stats.ptc64;
469 regs_buff[103] = adapter->stats.ptc127;
470 regs_buff[104] = adapter->stats.ptc255;
471 regs_buff[105] = adapter->stats.ptc511;
472 regs_buff[106] = adapter->stats.ptc1023;
473 regs_buff[107] = adapter->stats.ptc1522;
474 regs_buff[108] = adapter->stats.mptc;
475 regs_buff[109] = adapter->stats.bptc;
476 regs_buff[110] = adapter->stats.tsctc;
477 regs_buff[111] = adapter->stats.iac;
478 regs_buff[112] = adapter->stats.rpthc;
479 regs_buff[113] = adapter->stats.hgptc;
480 regs_buff[114] = adapter->stats.hgorc;
481 regs_buff[116] = adapter->stats.hgotc;
482 regs_buff[118] = adapter->stats.lenerrs;
483 regs_buff[119] = adapter->stats.scvpc;
484 regs_buff[120] = adapter->stats.hrmpc;
485
486 /* These should probably be added to e1000_regs.h instead */
487 #define E1000_PSRTYPE_REG(_i) (0x05480 + ((_i) * 4))
488 #define E1000_RAL(_i) (0x05400 + ((_i) * 8))
489 #define E1000_RAH(_i) (0x05404 + ((_i) * 8))
490 #define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8))
491 #define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4))
492 #define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4))
493 #define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8))
494 #define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8))
495 #define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8))
496
497 for (i = 0; i < 4; i++)
498 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
499 for (i = 0; i < 4; i++)
500 regs_buff[125 + i] = rd32(E1000_PSRTYPE_REG(i));
501 for (i = 0; i < 4; i++)
502 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
503 for (i = 0; i < 4; i++)
504 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
505 for (i = 0; i < 4; i++)
506 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
507 for (i = 0; i < 4; i++)
508 regs_buff[141 + i] = rd32(E1000_RDH(i));
509 for (i = 0; i < 4; i++)
510 regs_buff[145 + i] = rd32(E1000_RDT(i));
511 for (i = 0; i < 4; i++)
512 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
513
514 for (i = 0; i < 10; i++)
515 regs_buff[153 + i] = rd32(E1000_EITR(i));
516 for (i = 0; i < 8; i++)
517 regs_buff[163 + i] = rd32(E1000_IMIR(i));
518 for (i = 0; i < 8; i++)
519 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
520 for (i = 0; i < 16; i++)
521 regs_buff[179 + i] = rd32(E1000_RAL(i));
522 for (i = 0; i < 16; i++)
523 regs_buff[195 + i] = rd32(E1000_RAH(i));
524
525 for (i = 0; i < 4; i++)
526 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
527 for (i = 0; i < 4; i++)
528 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
529 for (i = 0; i < 4; i++)
530 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
531 for (i = 0; i < 4; i++)
532 regs_buff[223 + i] = rd32(E1000_TDH(i));
533 for (i = 0; i < 4; i++)
534 regs_buff[227 + i] = rd32(E1000_TDT(i));
535 for (i = 0; i < 4; i++)
536 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
537 for (i = 0; i < 4; i++)
538 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
539 for (i = 0; i < 4; i++)
540 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
541 for (i = 0; i < 4; i++)
542 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
543
544 for (i = 0; i < 4; i++)
545 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
546 for (i = 0; i < 4; i++)
547 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
548 for (i = 0; i < 32; i++)
549 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
550 for (i = 0; i < 128; i++)
551 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
552 for (i = 0; i < 128; i++)
553 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
554 for (i = 0; i < 4; i++)
555 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
556
557 regs_buff[547] = rd32(E1000_TDFH);
558 regs_buff[548] = rd32(E1000_TDFT);
559 regs_buff[549] = rd32(E1000_TDFHS);
560 regs_buff[550] = rd32(E1000_TDFPC);
561
562 }
563
564 static int igb_get_eeprom_len(struct net_device *netdev)
565 {
566 struct igb_adapter *adapter = netdev_priv(netdev);
567 return adapter->hw.nvm.word_size * 2;
568 }
569
570 static int igb_get_eeprom(struct net_device *netdev,
571 struct ethtool_eeprom *eeprom, u8 *bytes)
572 {
573 struct igb_adapter *adapter = netdev_priv(netdev);
574 struct e1000_hw *hw = &adapter->hw;
575 u16 *eeprom_buff;
576 int first_word, last_word;
577 int ret_val = 0;
578 u16 i;
579
580 if (eeprom->len == 0)
581 return -EINVAL;
582
583 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
584
585 first_word = eeprom->offset >> 1;
586 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
587
588 eeprom_buff = kmalloc(sizeof(u16) *
589 (last_word - first_word + 1), GFP_KERNEL);
590 if (!eeprom_buff)
591 return -ENOMEM;
592
593 if (hw->nvm.type == e1000_nvm_eeprom_spi)
594 ret_val = hw->nvm.ops.read_nvm(hw, first_word,
595 last_word - first_word + 1,
596 eeprom_buff);
597 else {
598 for (i = 0; i < last_word - first_word + 1; i++) {
599 ret_val = hw->nvm.ops.read_nvm(hw, first_word + i, 1,
600 &eeprom_buff[i]);
601 if (ret_val)
602 break;
603 }
604 }
605
606 /* Device's eeprom is always little-endian, word addressable */
607 for (i = 0; i < last_word - first_word + 1; i++)
608 le16_to_cpus(&eeprom_buff[i]);
609
610 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
611 eeprom->len);
612 kfree(eeprom_buff);
613
614 return ret_val;
615 }
616
617 static int igb_set_eeprom(struct net_device *netdev,
618 struct ethtool_eeprom *eeprom, u8 *bytes)
619 {
620 struct igb_adapter *adapter = netdev_priv(netdev);
621 struct e1000_hw *hw = &adapter->hw;
622 u16 *eeprom_buff;
623 void *ptr;
624 int max_len, first_word, last_word, ret_val = 0;
625 u16 i;
626
627 if (eeprom->len == 0)
628 return -EOPNOTSUPP;
629
630 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
631 return -EFAULT;
632
633 max_len = hw->nvm.word_size * 2;
634
635 first_word = eeprom->offset >> 1;
636 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
637 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
638 if (!eeprom_buff)
639 return -ENOMEM;
640
641 ptr = (void *)eeprom_buff;
642
643 if (eeprom->offset & 1) {
644 /* need read/modify/write of first changed EEPROM word */
645 /* only the second byte of the word is being modified */
646 ret_val = hw->nvm.ops.read_nvm(hw, first_word, 1,
647 &eeprom_buff[0]);
648 ptr++;
649 }
650 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
651 /* need read/modify/write of last changed EEPROM word */
652 /* only the first byte of the word is being modified */
653 ret_val = hw->nvm.ops.read_nvm(hw, last_word, 1,
654 &eeprom_buff[last_word - first_word]);
655 }
656
657 /* Device's eeprom is always little-endian, word addressable */
658 for (i = 0; i < last_word - first_word + 1; i++)
659 le16_to_cpus(&eeprom_buff[i]);
660
661 memcpy(ptr, bytes, eeprom->len);
662
663 for (i = 0; i < last_word - first_word + 1; i++)
664 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
665
666 ret_val = hw->nvm.ops.write_nvm(hw, first_word,
667 last_word - first_word + 1, eeprom_buff);
668
669 /* Update the checksum over the first part of the EEPROM if needed
670 * and flush shadow RAM for 82573 controllers */
671 if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
672 igb_update_nvm_checksum(hw);
673
674 kfree(eeprom_buff);
675 return ret_val;
676 }
677
678 static void igb_get_drvinfo(struct net_device *netdev,
679 struct ethtool_drvinfo *drvinfo)
680 {
681 struct igb_adapter *adapter = netdev_priv(netdev);
682 char firmware_version[32];
683 u16 eeprom_data;
684
685 strncpy(drvinfo->driver, igb_driver_name, 32);
686 strncpy(drvinfo->version, igb_driver_version, 32);
687
688 /* EEPROM image version # is reported as firmware version # for
689 * 82575 controllers */
690 adapter->hw.nvm.ops.read_nvm(&adapter->hw, 5, 1, &eeprom_data);
691 sprintf(firmware_version, "%d.%d-%d",
692 (eeprom_data & 0xF000) >> 12,
693 (eeprom_data & 0x0FF0) >> 4,
694 eeprom_data & 0x000F);
695
696 strncpy(drvinfo->fw_version, firmware_version, 32);
697 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
698 drvinfo->n_stats = IGB_STATS_LEN;
699 drvinfo->testinfo_len = IGB_TEST_LEN;
700 drvinfo->regdump_len = igb_get_regs_len(netdev);
701 drvinfo->eedump_len = igb_get_eeprom_len(netdev);
702 }
703
704 static void igb_get_ringparam(struct net_device *netdev,
705 struct ethtool_ringparam *ring)
706 {
707 struct igb_adapter *adapter = netdev_priv(netdev);
708 struct igb_ring *tx_ring = adapter->tx_ring;
709 struct igb_ring *rx_ring = adapter->rx_ring;
710
711 ring->rx_max_pending = IGB_MAX_RXD;
712 ring->tx_max_pending = IGB_MAX_TXD;
713 ring->rx_mini_max_pending = 0;
714 ring->rx_jumbo_max_pending = 0;
715 ring->rx_pending = rx_ring->count;
716 ring->tx_pending = tx_ring->count;
717 ring->rx_mini_pending = 0;
718 ring->rx_jumbo_pending = 0;
719 }
720
721 static int igb_set_ringparam(struct net_device *netdev,
722 struct ethtool_ringparam *ring)
723 {
724 struct igb_adapter *adapter = netdev_priv(netdev);
725 struct igb_buffer *old_buf;
726 struct igb_buffer *old_rx_buf;
727 void *old_desc;
728 int i, err;
729 u32 new_rx_count, new_tx_count, old_size;
730 dma_addr_t old_dma;
731
732 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
733 return -EINVAL;
734
735 new_rx_count = max(ring->rx_pending, (u32)IGB_MIN_RXD);
736 new_rx_count = min(new_rx_count, (u32)IGB_MAX_RXD);
737 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
738
739 new_tx_count = max(ring->tx_pending, (u32)IGB_MIN_TXD);
740 new_tx_count = min(new_tx_count, (u32)IGB_MAX_TXD);
741 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
742
743 if ((new_tx_count == adapter->tx_ring->count) &&
744 (new_rx_count == adapter->rx_ring->count)) {
745 /* nothing to do */
746 return 0;
747 }
748
749 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
750 msleep(1);
751
752 if (netif_running(adapter->netdev))
753 igb_down(adapter);
754
755 /*
756 * We can't just free everything and then setup again,
757 * because the ISRs in MSI-X mode get passed pointers
758 * to the tx and rx ring structs.
759 */
760 if (new_tx_count != adapter->tx_ring->count) {
761 for (i = 0; i < adapter->num_tx_queues; i++) {
762 /* Save existing descriptor ring */
763 old_buf = adapter->tx_ring[i].buffer_info;
764 old_desc = adapter->tx_ring[i].desc;
765 old_size = adapter->tx_ring[i].size;
766 old_dma = adapter->tx_ring[i].dma;
767 /* Try to allocate a new one */
768 adapter->tx_ring[i].buffer_info = NULL;
769 adapter->tx_ring[i].desc = NULL;
770 adapter->tx_ring[i].count = new_tx_count;
771 err = igb_setup_tx_resources(adapter,
772 &adapter->tx_ring[i]);
773 if (err) {
774 /* Restore the old one so at least
775 the adapter still works, even if
776 we failed the request */
777 adapter->tx_ring[i].buffer_info = old_buf;
778 adapter->tx_ring[i].desc = old_desc;
779 adapter->tx_ring[i].size = old_size;
780 adapter->tx_ring[i].dma = old_dma;
781 goto err_setup;
782 }
783 /* Free the old buffer manually */
784 vfree(old_buf);
785 pci_free_consistent(adapter->pdev, old_size,
786 old_desc, old_dma);
787 }
788 }
789
790 if (new_rx_count != adapter->rx_ring->count) {
791 for (i = 0; i < adapter->num_rx_queues; i++) {
792
793 old_rx_buf = adapter->rx_ring[i].buffer_info;
794 old_desc = adapter->rx_ring[i].desc;
795 old_size = adapter->rx_ring[i].size;
796 old_dma = adapter->rx_ring[i].dma;
797
798 adapter->rx_ring[i].buffer_info = NULL;
799 adapter->rx_ring[i].desc = NULL;
800 adapter->rx_ring[i].dma = 0;
801 adapter->rx_ring[i].count = new_rx_count;
802 err = igb_setup_rx_resources(adapter,
803 &adapter->rx_ring[i]);
804 if (err) {
805 adapter->rx_ring[i].buffer_info = old_rx_buf;
806 adapter->rx_ring[i].desc = old_desc;
807 adapter->rx_ring[i].size = old_size;
808 adapter->rx_ring[i].dma = old_dma;
809 goto err_setup;
810 }
811
812 vfree(old_rx_buf);
813 pci_free_consistent(adapter->pdev, old_size, old_desc,
814 old_dma);
815 }
816 }
817
818 err = 0;
819 err_setup:
820 if (netif_running(adapter->netdev))
821 igb_up(adapter);
822
823 clear_bit(__IGB_RESETTING, &adapter->state);
824 return err;
825 }
826
827 /* ethtool register test data */
828 struct igb_reg_test {
829 u16 reg;
830 u16 reg_offset;
831 u16 array_len;
832 u16 test_type;
833 u32 mask;
834 u32 write;
835 };
836
837 /* In the hardware, registers are laid out either singly, in arrays
838 * spaced 0x100 bytes apart, or in contiguous tables. We assume
839 * most tests take place on arrays or single registers (handled
840 * as a single-element array) and special-case the tables.
841 * Table tests are always pattern tests.
842 *
843 * We also make provision for some required setup steps by specifying
844 * registers to be written without any read-back testing.
845 */
846
847 #define PATTERN_TEST 1
848 #define SET_READ_TEST 2
849 #define WRITE_NO_TEST 3
850 #define TABLE32_TEST 4
851 #define TABLE64_TEST_LO 5
852 #define TABLE64_TEST_HI 6
853
854 /* 82576 reg test */
855 static struct igb_reg_test reg_test_82576[] = {
856 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
857 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
858 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
859 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
860 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
861 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
862 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
863 { E1000_RDBAL(4), 0x40, 8, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
864 { E1000_RDBAH(4), 0x40, 8, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
865 { E1000_RDLEN(4), 0x40, 8, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
866 /* Enable all four RX queues before testing. */
867 { E1000_RXDCTL(0), 0x100, 1, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
868 /* RDH is read-only for 82576, only test RDT. */
869 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
870 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
871 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
872 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
873 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
874 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
875 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
876 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
877 { E1000_TDBAL(4), 0x40, 8, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
878 { E1000_TDBAH(4), 0x40, 8, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
879 { E1000_TDLEN(4), 0x40, 8, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
880 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
881 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
882 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
883 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
884 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
885 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
886 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
887 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
888 { E1000_MTA, 0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
889 { 0, 0, 0, 0 }
890 };
891
892 /* 82575 register test */
893 static struct igb_reg_test reg_test_82575[] = {
894 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
895 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
896 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
897 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
898 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
899 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
900 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
901 /* Enable all four RX queues before testing. */
902 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
903 /* RDH is read-only for 82575, only test RDT. */
904 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
905 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
906 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
907 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
908 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
909 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
910 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
911 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
912 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
913 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
914 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
915 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
916 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
917 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
918 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
919 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
920 { 0, 0, 0, 0 }
921 };
922
923 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
924 int reg, u32 mask, u32 write)
925 {
926 u32 pat, val;
927 u32 _test[] =
928 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
929 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
930 writel((_test[pat] & write), (adapter->hw.hw_addr + reg));
931 val = readl(adapter->hw.hw_addr + reg);
932 if (val != (_test[pat] & write & mask)) {
933 dev_err(&adapter->pdev->dev, "pattern test reg %04X "
934 "failed: got 0x%08X expected 0x%08X\n",
935 reg, val, (_test[pat] & write & mask));
936 *data = reg;
937 return 1;
938 }
939 }
940 return 0;
941 }
942
943 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
944 int reg, u32 mask, u32 write)
945 {
946 u32 val;
947 writel((write & mask), (adapter->hw.hw_addr + reg));
948 val = readl(adapter->hw.hw_addr + reg);
949 if ((write & mask) != (val & mask)) {
950 dev_err(&adapter->pdev->dev, "set/check reg %04X test failed:"
951 " got 0x%08X expected 0x%08X\n", reg,
952 (val & mask), (write & mask));
953 *data = reg;
954 return 1;
955 }
956 return 0;
957 }
958
959 #define REG_PATTERN_TEST(reg, mask, write) \
960 do { \
961 if (reg_pattern_test(adapter, data, reg, mask, write)) \
962 return 1; \
963 } while (0)
964
965 #define REG_SET_AND_CHECK(reg, mask, write) \
966 do { \
967 if (reg_set_and_check(adapter, data, reg, mask, write)) \
968 return 1; \
969 } while (0)
970
971 static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
972 {
973 struct e1000_hw *hw = &adapter->hw;
974 struct igb_reg_test *test;
975 u32 value, before, after;
976 u32 i, toggle;
977
978 toggle = 0x7FFFF3FF;
979
980 switch (adapter->hw.mac.type) {
981 case e1000_82576:
982 test = reg_test_82576;
983 break;
984 default:
985 test = reg_test_82575;
986 break;
987 }
988
989 /* Because the status register is such a special case,
990 * we handle it separately from the rest of the register
991 * tests. Some bits are read-only, some toggle, and some
992 * are writable on newer MACs.
993 */
994 before = rd32(E1000_STATUS);
995 value = (rd32(E1000_STATUS) & toggle);
996 wr32(E1000_STATUS, toggle);
997 after = rd32(E1000_STATUS) & toggle;
998 if (value != after) {
999 dev_err(&adapter->pdev->dev, "failed STATUS register test "
1000 "got: 0x%08X expected: 0x%08X\n", after, value);
1001 *data = 1;
1002 return 1;
1003 }
1004 /* restore previous status */
1005 wr32(E1000_STATUS, before);
1006
1007 /* Perform the remainder of the register test, looping through
1008 * the test table until we either fail or reach the null entry.
1009 */
1010 while (test->reg) {
1011 for (i = 0; i < test->array_len; i++) {
1012 switch (test->test_type) {
1013 case PATTERN_TEST:
1014 REG_PATTERN_TEST(test->reg + (i * test->reg_offset),
1015 test->mask,
1016 test->write);
1017 break;
1018 case SET_READ_TEST:
1019 REG_SET_AND_CHECK(test->reg + (i * test->reg_offset),
1020 test->mask,
1021 test->write);
1022 break;
1023 case WRITE_NO_TEST:
1024 writel(test->write,
1025 (adapter->hw.hw_addr + test->reg)
1026 + (i * test->reg_offset));
1027 break;
1028 case TABLE32_TEST:
1029 REG_PATTERN_TEST(test->reg + (i * 4),
1030 test->mask,
1031 test->write);
1032 break;
1033 case TABLE64_TEST_LO:
1034 REG_PATTERN_TEST(test->reg + (i * 8),
1035 test->mask,
1036 test->write);
1037 break;
1038 case TABLE64_TEST_HI:
1039 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1040 test->mask,
1041 test->write);
1042 break;
1043 }
1044 }
1045 test++;
1046 }
1047
1048 *data = 0;
1049 return 0;
1050 }
1051
1052 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1053 {
1054 u16 temp;
1055 u16 checksum = 0;
1056 u16 i;
1057
1058 *data = 0;
1059 /* Read and add up the contents of the EEPROM */
1060 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1061 if ((adapter->hw.nvm.ops.read_nvm(&adapter->hw, i, 1, &temp))
1062 < 0) {
1063 *data = 1;
1064 break;
1065 }
1066 checksum += temp;
1067 }
1068
1069 /* If Checksum is not Correct return error else test passed */
1070 if ((checksum != (u16) NVM_SUM) && !(*data))
1071 *data = 2;
1072
1073 return *data;
1074 }
1075
1076 static irqreturn_t igb_test_intr(int irq, void *data)
1077 {
1078 struct net_device *netdev = (struct net_device *) data;
1079 struct igb_adapter *adapter = netdev_priv(netdev);
1080 struct e1000_hw *hw = &adapter->hw;
1081
1082 adapter->test_icr |= rd32(E1000_ICR);
1083
1084 return IRQ_HANDLED;
1085 }
1086
1087 static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1088 {
1089 struct e1000_hw *hw = &adapter->hw;
1090 struct net_device *netdev = adapter->netdev;
1091 u32 mask, i = 0, shared_int = true;
1092 u32 irq = adapter->pdev->irq;
1093
1094 *data = 0;
1095
1096 /* Hook up test interrupt handler just for this test */
1097 if (adapter->msix_entries) {
1098 /* NOTE: we don't test MSI-X interrupts here, yet */
1099 return 0;
1100 } else if (adapter->msi_enabled) {
1101 shared_int = false;
1102 if (request_irq(irq, &igb_test_intr, 0, netdev->name, netdev)) {
1103 *data = 1;
1104 return -1;
1105 }
1106 } else if (!request_irq(irq, &igb_test_intr, IRQF_PROBE_SHARED,
1107 netdev->name, netdev)) {
1108 shared_int = false;
1109 } else if (request_irq(irq, &igb_test_intr, IRQF_SHARED,
1110 netdev->name, netdev)) {
1111 *data = 1;
1112 return -1;
1113 }
1114 dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1115 (shared_int ? "shared" : "unshared"));
1116
1117 /* Disable all the interrupts */
1118 wr32(E1000_IMC, 0xFFFFFFFF);
1119 msleep(10);
1120
1121 /* Test each interrupt */
1122 for (; i < 10; i++) {
1123 /* Interrupt to test */
1124 mask = 1 << i;
1125
1126 if (!shared_int) {
1127 /* Disable the interrupt to be reported in
1128 * the cause register and then force the same
1129 * interrupt and see if one gets posted. If
1130 * an interrupt was posted to the bus, the
1131 * test failed.
1132 */
1133 adapter->test_icr = 0;
1134 wr32(E1000_IMC, ~mask & 0x00007FFF);
1135 wr32(E1000_ICS, ~mask & 0x00007FFF);
1136 msleep(10);
1137
1138 if (adapter->test_icr & mask) {
1139 *data = 3;
1140 break;
1141 }
1142 }
1143
1144 /* Enable the interrupt to be reported in
1145 * the cause register and then force the same
1146 * interrupt and see if one gets posted. If
1147 * an interrupt was not posted to the bus, the
1148 * test failed.
1149 */
1150 adapter->test_icr = 0;
1151 wr32(E1000_IMS, mask);
1152 wr32(E1000_ICS, mask);
1153 msleep(10);
1154
1155 if (!(adapter->test_icr & mask)) {
1156 *data = 4;
1157 break;
1158 }
1159
1160 if (!shared_int) {
1161 /* Disable the other interrupts to be reported in
1162 * the cause register and then force the other
1163 * interrupts and see if any get posted. If
1164 * an interrupt was posted to the bus, the
1165 * test failed.
1166 */
1167 adapter->test_icr = 0;
1168 wr32(E1000_IMC, ~mask & 0x00007FFF);
1169 wr32(E1000_ICS, ~mask & 0x00007FFF);
1170 msleep(10);
1171
1172 if (adapter->test_icr) {
1173 *data = 5;
1174 break;
1175 }
1176 }
1177 }
1178
1179 /* Disable all the interrupts */
1180 wr32(E1000_IMC, 0xFFFFFFFF);
1181 msleep(10);
1182
1183 /* Unhook test interrupt handler */
1184 free_irq(irq, netdev);
1185
1186 return *data;
1187 }
1188
1189 static void igb_free_desc_rings(struct igb_adapter *adapter)
1190 {
1191 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1192 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1193 struct pci_dev *pdev = adapter->pdev;
1194 int i;
1195
1196 if (tx_ring->desc && tx_ring->buffer_info) {
1197 for (i = 0; i < tx_ring->count; i++) {
1198 struct igb_buffer *buf = &(tx_ring->buffer_info[i]);
1199 if (buf->dma)
1200 pci_unmap_single(pdev, buf->dma, buf->length,
1201 PCI_DMA_TODEVICE);
1202 if (buf->skb)
1203 dev_kfree_skb(buf->skb);
1204 }
1205 }
1206
1207 if (rx_ring->desc && rx_ring->buffer_info) {
1208 for (i = 0; i < rx_ring->count; i++) {
1209 struct igb_buffer *buf = &(rx_ring->buffer_info[i]);
1210 if (buf->dma)
1211 pci_unmap_single(pdev, buf->dma,
1212 IGB_RXBUFFER_2048,
1213 PCI_DMA_FROMDEVICE);
1214 if (buf->skb)
1215 dev_kfree_skb(buf->skb);
1216 }
1217 }
1218
1219 if (tx_ring->desc) {
1220 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc,
1221 tx_ring->dma);
1222 tx_ring->desc = NULL;
1223 }
1224 if (rx_ring->desc) {
1225 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc,
1226 rx_ring->dma);
1227 rx_ring->desc = NULL;
1228 }
1229
1230 kfree(tx_ring->buffer_info);
1231 tx_ring->buffer_info = NULL;
1232 kfree(rx_ring->buffer_info);
1233 rx_ring->buffer_info = NULL;
1234
1235 return;
1236 }
1237
1238 static int igb_setup_desc_rings(struct igb_adapter *adapter)
1239 {
1240 struct e1000_hw *hw = &adapter->hw;
1241 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1242 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1243 struct pci_dev *pdev = adapter->pdev;
1244 u32 rctl;
1245 int i, ret_val;
1246
1247 /* Setup Tx descriptor ring and Tx buffers */
1248
1249 if (!tx_ring->count)
1250 tx_ring->count = IGB_DEFAULT_TXD;
1251
1252 tx_ring->buffer_info = kcalloc(tx_ring->count,
1253 sizeof(struct igb_buffer),
1254 GFP_KERNEL);
1255 if (!tx_ring->buffer_info) {
1256 ret_val = 1;
1257 goto err_nomem;
1258 }
1259
1260 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
1261 tx_ring->size = ALIGN(tx_ring->size, 4096);
1262 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1263 &tx_ring->dma);
1264 if (!tx_ring->desc) {
1265 ret_val = 2;
1266 goto err_nomem;
1267 }
1268 tx_ring->next_to_use = tx_ring->next_to_clean = 0;
1269
1270 wr32(E1000_TDBAL(0),
1271 ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
1272 wr32(E1000_TDBAH(0), ((u64) tx_ring->dma >> 32));
1273 wr32(E1000_TDLEN(0),
1274 tx_ring->count * sizeof(struct e1000_tx_desc));
1275 wr32(E1000_TDH(0), 0);
1276 wr32(E1000_TDT(0), 0);
1277 wr32(E1000_TCTL,
1278 E1000_TCTL_PSP | E1000_TCTL_EN |
1279 E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT |
1280 E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT);
1281
1282 for (i = 0; i < tx_ring->count; i++) {
1283 struct e1000_tx_desc *tx_desc = E1000_TX_DESC(*tx_ring, i);
1284 struct sk_buff *skb;
1285 unsigned int size = 1024;
1286
1287 skb = alloc_skb(size, GFP_KERNEL);
1288 if (!skb) {
1289 ret_val = 3;
1290 goto err_nomem;
1291 }
1292 skb_put(skb, size);
1293 tx_ring->buffer_info[i].skb = skb;
1294 tx_ring->buffer_info[i].length = skb->len;
1295 tx_ring->buffer_info[i].dma =
1296 pci_map_single(pdev, skb->data, skb->len,
1297 PCI_DMA_TODEVICE);
1298 tx_desc->buffer_addr = cpu_to_le64(tx_ring->buffer_info[i].dma);
1299 tx_desc->lower.data = cpu_to_le32(skb->len);
1300 tx_desc->lower.data |= cpu_to_le32(E1000_TXD_CMD_EOP |
1301 E1000_TXD_CMD_IFCS |
1302 E1000_TXD_CMD_RS);
1303 tx_desc->upper.data = 0;
1304 }
1305
1306 /* Setup Rx descriptor ring and Rx buffers */
1307
1308 if (!rx_ring->count)
1309 rx_ring->count = IGB_DEFAULT_RXD;
1310
1311 rx_ring->buffer_info = kcalloc(rx_ring->count,
1312 sizeof(struct igb_buffer),
1313 GFP_KERNEL);
1314 if (!rx_ring->buffer_info) {
1315 ret_val = 4;
1316 goto err_nomem;
1317 }
1318
1319 rx_ring->size = rx_ring->count * sizeof(struct e1000_rx_desc);
1320 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1321 &rx_ring->dma);
1322 if (!rx_ring->desc) {
1323 ret_val = 5;
1324 goto err_nomem;
1325 }
1326 rx_ring->next_to_use = rx_ring->next_to_clean = 0;
1327
1328 rctl = rd32(E1000_RCTL);
1329 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1330 wr32(E1000_RDBAL(0),
1331 ((u64) rx_ring->dma & 0xFFFFFFFF));
1332 wr32(E1000_RDBAH(0),
1333 ((u64) rx_ring->dma >> 32));
1334 wr32(E1000_RDLEN(0), rx_ring->size);
1335 wr32(E1000_RDH(0), 0);
1336 wr32(E1000_RDT(0), 0);
1337 rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 |
1338 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1339 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1340 wr32(E1000_RCTL, rctl);
1341 wr32(E1000_SRRCTL(0), 0);
1342
1343 for (i = 0; i < rx_ring->count; i++) {
1344 struct e1000_rx_desc *rx_desc = E1000_RX_DESC(*rx_ring, i);
1345 struct sk_buff *skb;
1346
1347 skb = alloc_skb(IGB_RXBUFFER_2048 + NET_IP_ALIGN,
1348 GFP_KERNEL);
1349 if (!skb) {
1350 ret_val = 6;
1351 goto err_nomem;
1352 }
1353 skb_reserve(skb, NET_IP_ALIGN);
1354 rx_ring->buffer_info[i].skb = skb;
1355 rx_ring->buffer_info[i].dma =
1356 pci_map_single(pdev, skb->data, IGB_RXBUFFER_2048,
1357 PCI_DMA_FROMDEVICE);
1358 rx_desc->buffer_addr = cpu_to_le64(rx_ring->buffer_info[i].dma);
1359 memset(skb->data, 0x00, skb->len);
1360 }
1361
1362 return 0;
1363
1364 err_nomem:
1365 igb_free_desc_rings(adapter);
1366 return ret_val;
1367 }
1368
1369 static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1370 {
1371 struct e1000_hw *hw = &adapter->hw;
1372
1373 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1374 hw->phy.ops.write_phy_reg(hw, 29, 0x001F);
1375 hw->phy.ops.write_phy_reg(hw, 30, 0x8FFC);
1376 hw->phy.ops.write_phy_reg(hw, 29, 0x001A);
1377 hw->phy.ops.write_phy_reg(hw, 30, 0x8FF0);
1378 }
1379
1380 static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1381 {
1382 struct e1000_hw *hw = &adapter->hw;
1383 u32 ctrl_reg = 0;
1384 u32 stat_reg = 0;
1385
1386 hw->mac.autoneg = false;
1387
1388 if (hw->phy.type == e1000_phy_m88) {
1389 /* Auto-MDI/MDIX Off */
1390 hw->phy.ops.write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1391 /* reset to update Auto-MDI/MDIX */
1392 hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, 0x9140);
1393 /* autoneg off */
1394 hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, 0x8140);
1395 }
1396
1397 ctrl_reg = rd32(E1000_CTRL);
1398
1399 /* force 1000, set loopback */
1400 hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, 0x4140);
1401
1402 /* Now set up the MAC to the same speed/duplex as the PHY. */
1403 ctrl_reg = rd32(E1000_CTRL);
1404 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1405 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1406 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1407 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1408 E1000_CTRL_FD); /* Force Duplex to FULL */
1409
1410 if (hw->phy.media_type == e1000_media_type_copper &&
1411 hw->phy.type == e1000_phy_m88)
1412 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1413 else {
1414 /* Set the ILOS bit on the fiber Nic if half duplex link is
1415 * detected. */
1416 stat_reg = rd32(E1000_STATUS);
1417 if ((stat_reg & E1000_STATUS_FD) == 0)
1418 ctrl_reg |= (E1000_CTRL_ILOS | E1000_CTRL_SLU);
1419 }
1420
1421 wr32(E1000_CTRL, ctrl_reg);
1422
1423 /* Disable the receiver on the PHY so when a cable is plugged in, the
1424 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1425 */
1426 if (hw->phy.type == e1000_phy_m88)
1427 igb_phy_disable_receiver(adapter);
1428
1429 udelay(500);
1430
1431 return 0;
1432 }
1433
1434 static int igb_set_phy_loopback(struct igb_adapter *adapter)
1435 {
1436 return igb_integrated_phy_loopback(adapter);
1437 }
1438
1439 static int igb_setup_loopback_test(struct igb_adapter *adapter)
1440 {
1441 struct e1000_hw *hw = &adapter->hw;
1442 u32 reg;
1443
1444 if (hw->phy.media_type == e1000_media_type_fiber ||
1445 hw->phy.media_type == e1000_media_type_internal_serdes) {
1446 reg = rd32(E1000_RCTL);
1447 reg |= E1000_RCTL_LBM_TCVR;
1448 wr32(E1000_RCTL, reg);
1449
1450 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1451
1452 reg = rd32(E1000_CTRL);
1453 reg &= ~(E1000_CTRL_RFCE |
1454 E1000_CTRL_TFCE |
1455 E1000_CTRL_LRST);
1456 reg |= E1000_CTRL_SLU |
1457 E1000_CTRL_FD;
1458 wr32(E1000_CTRL, reg);
1459
1460 /* Unset switch control to serdes energy detect */
1461 reg = rd32(E1000_CONNSW);
1462 reg &= ~E1000_CONNSW_ENRGSRC;
1463 wr32(E1000_CONNSW, reg);
1464
1465 /* Set PCS register for forced speed */
1466 reg = rd32(E1000_PCS_LCTL);
1467 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/
1468 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1469 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1470 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1471 E1000_PCS_LCTL_FSD | /* Force Speed */
1472 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1473 wr32(E1000_PCS_LCTL, reg);
1474
1475 return 0;
1476 } else if (hw->phy.media_type == e1000_media_type_copper) {
1477 return igb_set_phy_loopback(adapter);
1478 }
1479
1480 return 7;
1481 }
1482
1483 static void igb_loopback_cleanup(struct igb_adapter *adapter)
1484 {
1485 struct e1000_hw *hw = &adapter->hw;
1486 u32 rctl;
1487 u16 phy_reg;
1488
1489 rctl = rd32(E1000_RCTL);
1490 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1491 wr32(E1000_RCTL, rctl);
1492
1493 hw->mac.autoneg = true;
1494 hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &phy_reg);
1495 if (phy_reg & MII_CR_LOOPBACK) {
1496 phy_reg &= ~MII_CR_LOOPBACK;
1497 hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, phy_reg);
1498 igb_phy_sw_reset(hw);
1499 }
1500 }
1501
1502 static void igb_create_lbtest_frame(struct sk_buff *skb,
1503 unsigned int frame_size)
1504 {
1505 memset(skb->data, 0xFF, frame_size);
1506 frame_size &= ~1;
1507 memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1508 memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1509 memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1510 }
1511
1512 static int igb_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
1513 {
1514 frame_size &= ~1;
1515 if (*(skb->data + 3) == 0xFF)
1516 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1517 (*(skb->data + frame_size / 2 + 12) == 0xAF))
1518 return 0;
1519 return 13;
1520 }
1521
1522 static int igb_run_loopback_test(struct igb_adapter *adapter)
1523 {
1524 struct e1000_hw *hw = &adapter->hw;
1525 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1526 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1527 struct pci_dev *pdev = adapter->pdev;
1528 int i, j, k, l, lc, good_cnt;
1529 int ret_val = 0;
1530 unsigned long time;
1531
1532 wr32(E1000_RDT(0), rx_ring->count - 1);
1533
1534 /* Calculate the loop count based on the largest descriptor ring
1535 * The idea is to wrap the largest ring a number of times using 64
1536 * send/receive pairs during each loop
1537 */
1538
1539 if (rx_ring->count <= tx_ring->count)
1540 lc = ((tx_ring->count / 64) * 2) + 1;
1541 else
1542 lc = ((rx_ring->count / 64) * 2) + 1;
1543
1544 k = l = 0;
1545 for (j = 0; j <= lc; j++) { /* loop count loop */
1546 for (i = 0; i < 64; i++) { /* send the packets */
1547 igb_create_lbtest_frame(tx_ring->buffer_info[k].skb,
1548 1024);
1549 pci_dma_sync_single_for_device(pdev,
1550 tx_ring->buffer_info[k].dma,
1551 tx_ring->buffer_info[k].length,
1552 PCI_DMA_TODEVICE);
1553 k++;
1554 if (k == tx_ring->count)
1555 k = 0;
1556 }
1557 wr32(E1000_TDT(0), k);
1558 msleep(200);
1559 time = jiffies; /* set the start time for the receive */
1560 good_cnt = 0;
1561 do { /* receive the sent packets */
1562 pci_dma_sync_single_for_cpu(pdev,
1563 rx_ring->buffer_info[l].dma,
1564 IGB_RXBUFFER_2048,
1565 PCI_DMA_FROMDEVICE);
1566
1567 ret_val = igb_check_lbtest_frame(
1568 rx_ring->buffer_info[l].skb, 1024);
1569 if (!ret_val)
1570 good_cnt++;
1571 l++;
1572 if (l == rx_ring->count)
1573 l = 0;
1574 /* time + 20 msecs (200 msecs on 2.4) is more than
1575 * enough time to complete the receives, if it's
1576 * exceeded, break and error off
1577 */
1578 } while (good_cnt < 64 && jiffies < (time + 20));
1579 if (good_cnt != 64) {
1580 ret_val = 13; /* ret_val is the same as mis-compare */
1581 break;
1582 }
1583 if (jiffies >= (time + 20)) {
1584 ret_val = 14; /* error code for time out error */
1585 break;
1586 }
1587 } /* end loop count loop */
1588 return ret_val;
1589 }
1590
1591 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1592 {
1593 /* PHY loopback cannot be performed if SoL/IDER
1594 * sessions are active */
1595 if (igb_check_reset_block(&adapter->hw)) {
1596 dev_err(&adapter->pdev->dev,
1597 "Cannot do PHY loopback test "
1598 "when SoL/IDER is active.\n");
1599 *data = 0;
1600 goto out;
1601 }
1602 *data = igb_setup_desc_rings(adapter);
1603 if (*data)
1604 goto out;
1605 *data = igb_setup_loopback_test(adapter);
1606 if (*data)
1607 goto err_loopback;
1608 *data = igb_run_loopback_test(adapter);
1609 igb_loopback_cleanup(adapter);
1610
1611 err_loopback:
1612 igb_free_desc_rings(adapter);
1613 out:
1614 return *data;
1615 }
1616
1617 static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1618 {
1619 struct e1000_hw *hw = &adapter->hw;
1620 *data = 0;
1621 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1622 int i = 0;
1623 hw->mac.serdes_has_link = false;
1624
1625 /* On some blade server designs, link establishment
1626 * could take as long as 2-3 minutes */
1627 do {
1628 hw->mac.ops.check_for_link(&adapter->hw);
1629 if (hw->mac.serdes_has_link)
1630 return *data;
1631 msleep(20);
1632 } while (i++ < 3750);
1633
1634 *data = 1;
1635 } else {
1636 hw->mac.ops.check_for_link(&adapter->hw);
1637 if (hw->mac.autoneg)
1638 msleep(4000);
1639
1640 if (!(rd32(E1000_STATUS) &
1641 E1000_STATUS_LU))
1642 *data = 1;
1643 }
1644 return *data;
1645 }
1646
1647 static void igb_diag_test(struct net_device *netdev,
1648 struct ethtool_test *eth_test, u64 *data)
1649 {
1650 struct igb_adapter *adapter = netdev_priv(netdev);
1651 u16 autoneg_advertised;
1652 u8 forced_speed_duplex, autoneg;
1653 bool if_running = netif_running(netdev);
1654
1655 set_bit(__IGB_TESTING, &adapter->state);
1656 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1657 /* Offline tests */
1658
1659 /* save speed, duplex, autoneg settings */
1660 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1661 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1662 autoneg = adapter->hw.mac.autoneg;
1663
1664 dev_info(&adapter->pdev->dev, "offline testing starting\n");
1665
1666 /* Link test performed before hardware reset so autoneg doesn't
1667 * interfere with test result */
1668 if (igb_link_test(adapter, &data[4]))
1669 eth_test->flags |= ETH_TEST_FL_FAILED;
1670
1671 if (if_running)
1672 /* indicate we're in test mode */
1673 dev_close(netdev);
1674 else
1675 igb_reset(adapter);
1676
1677 if (igb_reg_test(adapter, &data[0]))
1678 eth_test->flags |= ETH_TEST_FL_FAILED;
1679
1680 igb_reset(adapter);
1681 if (igb_eeprom_test(adapter, &data[1]))
1682 eth_test->flags |= ETH_TEST_FL_FAILED;
1683
1684 igb_reset(adapter);
1685 if (igb_intr_test(adapter, &data[2]))
1686 eth_test->flags |= ETH_TEST_FL_FAILED;
1687
1688 igb_reset(adapter);
1689 if (igb_loopback_test(adapter, &data[3]))
1690 eth_test->flags |= ETH_TEST_FL_FAILED;
1691
1692 /* restore speed, duplex, autoneg settings */
1693 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
1694 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
1695 adapter->hw.mac.autoneg = autoneg;
1696
1697 /* force this routine to wait until autoneg complete/timeout */
1698 adapter->hw.phy.autoneg_wait_to_complete = true;
1699 igb_reset(adapter);
1700 adapter->hw.phy.autoneg_wait_to_complete = false;
1701
1702 clear_bit(__IGB_TESTING, &adapter->state);
1703 if (if_running)
1704 dev_open(netdev);
1705 } else {
1706 dev_info(&adapter->pdev->dev, "online testing starting\n");
1707 /* Online tests */
1708 if (igb_link_test(adapter, &data[4]))
1709 eth_test->flags |= ETH_TEST_FL_FAILED;
1710
1711 /* Online tests aren't run; pass by default */
1712 data[0] = 0;
1713 data[1] = 0;
1714 data[2] = 0;
1715 data[3] = 0;
1716
1717 clear_bit(__IGB_TESTING, &adapter->state);
1718 }
1719 msleep_interruptible(4 * 1000);
1720 }
1721
1722 static int igb_wol_exclusion(struct igb_adapter *adapter,
1723 struct ethtool_wolinfo *wol)
1724 {
1725 struct e1000_hw *hw = &adapter->hw;
1726 int retval = 1; /* fail by default */
1727
1728 switch (hw->device_id) {
1729 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1730 case E1000_DEV_ID_82576_QUAD_COPPER:
1731 /* WoL not supported */
1732 wol->supported = 0;
1733 break;
1734 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1735 case E1000_DEV_ID_82576_FIBER:
1736 case E1000_DEV_ID_82576_SERDES:
1737 /* Wake events not supported on port B */
1738 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) {
1739 wol->supported = 0;
1740 break;
1741 }
1742 /* return success for non excluded adapter ports */
1743 retval = 0;
1744 break;
1745 default:
1746 /* dual port cards only support WoL on port A from now on
1747 * unless it was enabled in the eeprom for port B
1748 * so exclude FUNC_1 ports from having WoL enabled */
1749 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1 &&
1750 !adapter->eeprom_wol) {
1751 wol->supported = 0;
1752 break;
1753 }
1754
1755 retval = 0;
1756 }
1757
1758 return retval;
1759 }
1760
1761 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1762 {
1763 struct igb_adapter *adapter = netdev_priv(netdev);
1764
1765 wol->supported = WAKE_UCAST | WAKE_MCAST |
1766 WAKE_BCAST | WAKE_MAGIC;
1767 wol->wolopts = 0;
1768
1769 /* this function will set ->supported = 0 and return 1 if wol is not
1770 * supported by this hardware */
1771 if (igb_wol_exclusion(adapter, wol))
1772 return;
1773
1774 /* apply any specific unsupported masks here */
1775 switch (adapter->hw.device_id) {
1776 default:
1777 break;
1778 }
1779
1780 if (adapter->wol & E1000_WUFC_EX)
1781 wol->wolopts |= WAKE_UCAST;
1782 if (adapter->wol & E1000_WUFC_MC)
1783 wol->wolopts |= WAKE_MCAST;
1784 if (adapter->wol & E1000_WUFC_BC)
1785 wol->wolopts |= WAKE_BCAST;
1786 if (adapter->wol & E1000_WUFC_MAG)
1787 wol->wolopts |= WAKE_MAGIC;
1788
1789 return;
1790 }
1791
1792 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1793 {
1794 struct igb_adapter *adapter = netdev_priv(netdev);
1795 struct e1000_hw *hw = &adapter->hw;
1796
1797 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1798 return -EOPNOTSUPP;
1799
1800 if (igb_wol_exclusion(adapter, wol))
1801 return wol->wolopts ? -EOPNOTSUPP : 0;
1802
1803 switch (hw->device_id) {
1804 default:
1805 break;
1806 }
1807
1808 /* these settings will always override what we currently have */
1809 adapter->wol = 0;
1810
1811 if (wol->wolopts & WAKE_UCAST)
1812 adapter->wol |= E1000_WUFC_EX;
1813 if (wol->wolopts & WAKE_MCAST)
1814 adapter->wol |= E1000_WUFC_MC;
1815 if (wol->wolopts & WAKE_BCAST)
1816 adapter->wol |= E1000_WUFC_BC;
1817 if (wol->wolopts & WAKE_MAGIC)
1818 adapter->wol |= E1000_WUFC_MAG;
1819
1820 return 0;
1821 }
1822
1823 /* toggle LED 4 times per second = 2 "blinks" per second */
1824 #define IGB_ID_INTERVAL (HZ/4)
1825
1826 /* bit defines for adapter->led_status */
1827 #define IGB_LED_ON 0
1828
1829 static int igb_phys_id(struct net_device *netdev, u32 data)
1830 {
1831 struct igb_adapter *adapter = netdev_priv(netdev);
1832 struct e1000_hw *hw = &adapter->hw;
1833
1834 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
1835 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
1836
1837 igb_blink_led(hw);
1838 msleep_interruptible(data * 1000);
1839
1840 igb_led_off(hw);
1841 clear_bit(IGB_LED_ON, &adapter->led_status);
1842 igb_cleanup_led(hw);
1843
1844 return 0;
1845 }
1846
1847 static int igb_set_coalesce(struct net_device *netdev,
1848 struct ethtool_coalesce *ec)
1849 {
1850 struct igb_adapter *adapter = netdev_priv(netdev);
1851
1852 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1853 ((ec->rx_coalesce_usecs > 3) &&
1854 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
1855 (ec->rx_coalesce_usecs == 2))
1856 return -EINVAL;
1857
1858 /* convert to rate of irq's per second */
1859 if (ec->rx_coalesce_usecs <= 3)
1860 adapter->itr_setting = ec->rx_coalesce_usecs;
1861 else
1862 adapter->itr_setting = (1000000 / ec->rx_coalesce_usecs);
1863
1864 if (netif_running(netdev))
1865 igb_reinit_locked(adapter);
1866
1867 return 0;
1868 }
1869
1870 static int igb_get_coalesce(struct net_device *netdev,
1871 struct ethtool_coalesce *ec)
1872 {
1873 struct igb_adapter *adapter = netdev_priv(netdev);
1874
1875 if (adapter->itr_setting <= 3)
1876 ec->rx_coalesce_usecs = adapter->itr_setting;
1877 else
1878 ec->rx_coalesce_usecs = 1000000 / adapter->itr_setting;
1879
1880 return 0;
1881 }
1882
1883
1884 static int igb_nway_reset(struct net_device *netdev)
1885 {
1886 struct igb_adapter *adapter = netdev_priv(netdev);
1887 if (netif_running(netdev))
1888 igb_reinit_locked(adapter);
1889 return 0;
1890 }
1891
1892 static int igb_get_sset_count(struct net_device *netdev, int sset)
1893 {
1894 switch (sset) {
1895 case ETH_SS_STATS:
1896 return IGB_STATS_LEN;
1897 case ETH_SS_TEST:
1898 return IGB_TEST_LEN;
1899 default:
1900 return -ENOTSUPP;
1901 }
1902 }
1903
1904 static void igb_get_ethtool_stats(struct net_device *netdev,
1905 struct ethtool_stats *stats, u64 *data)
1906 {
1907 struct igb_adapter *adapter = netdev_priv(netdev);
1908 u64 *queue_stat;
1909 int stat_count = sizeof(struct igb_queue_stats) / sizeof(u64);
1910 int j;
1911 int i;
1912
1913 igb_update_stats(adapter);
1914 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
1915 char *p = (char *)adapter+igb_gstrings_stats[i].stat_offset;
1916 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
1917 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1918 }
1919 for (j = 0; j < adapter->num_tx_queues; j++) {
1920 int k;
1921 queue_stat = (u64 *)&adapter->tx_ring[j].tx_stats;
1922 for (k = 0; k < stat_count; k++)
1923 data[i + k] = queue_stat[k];
1924 i += k;
1925 }
1926 for (j = 0; j < adapter->num_rx_queues; j++) {
1927 int k;
1928 queue_stat = (u64 *)&adapter->rx_ring[j].rx_stats;
1929 for (k = 0; k < stat_count; k++)
1930 data[i + k] = queue_stat[k];
1931 i += k;
1932 }
1933 }
1934
1935 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
1936 {
1937 struct igb_adapter *adapter = netdev_priv(netdev);
1938 u8 *p = data;
1939 int i;
1940
1941 switch (stringset) {
1942 case ETH_SS_TEST:
1943 memcpy(data, *igb_gstrings_test,
1944 IGB_TEST_LEN*ETH_GSTRING_LEN);
1945 break;
1946 case ETH_SS_STATS:
1947 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
1948 memcpy(p, igb_gstrings_stats[i].stat_string,
1949 ETH_GSTRING_LEN);
1950 p += ETH_GSTRING_LEN;
1951 }
1952 for (i = 0; i < adapter->num_tx_queues; i++) {
1953 sprintf(p, "tx_queue_%u_packets", i);
1954 p += ETH_GSTRING_LEN;
1955 sprintf(p, "tx_queue_%u_bytes", i);
1956 p += ETH_GSTRING_LEN;
1957 }
1958 for (i = 0; i < adapter->num_rx_queues; i++) {
1959 sprintf(p, "rx_queue_%u_packets", i);
1960 p += ETH_GSTRING_LEN;
1961 sprintf(p, "rx_queue_%u_bytes", i);
1962 p += ETH_GSTRING_LEN;
1963 }
1964 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
1965 break;
1966 }
1967 }
1968
1969 static struct ethtool_ops igb_ethtool_ops = {
1970 .get_settings = igb_get_settings,
1971 .set_settings = igb_set_settings,
1972 .get_drvinfo = igb_get_drvinfo,
1973 .get_regs_len = igb_get_regs_len,
1974 .get_regs = igb_get_regs,
1975 .get_wol = igb_get_wol,
1976 .set_wol = igb_set_wol,
1977 .get_msglevel = igb_get_msglevel,
1978 .set_msglevel = igb_set_msglevel,
1979 .nway_reset = igb_nway_reset,
1980 .get_link = ethtool_op_get_link,
1981 .get_eeprom_len = igb_get_eeprom_len,
1982 .get_eeprom = igb_get_eeprom,
1983 .set_eeprom = igb_set_eeprom,
1984 .get_ringparam = igb_get_ringparam,
1985 .set_ringparam = igb_set_ringparam,
1986 .get_pauseparam = igb_get_pauseparam,
1987 .set_pauseparam = igb_set_pauseparam,
1988 .get_rx_csum = igb_get_rx_csum,
1989 .set_rx_csum = igb_set_rx_csum,
1990 .get_tx_csum = igb_get_tx_csum,
1991 .set_tx_csum = igb_set_tx_csum,
1992 .get_sg = ethtool_op_get_sg,
1993 .set_sg = ethtool_op_set_sg,
1994 .get_tso = ethtool_op_get_tso,
1995 .set_tso = igb_set_tso,
1996 .self_test = igb_diag_test,
1997 .get_strings = igb_get_strings,
1998 .phys_id = igb_phys_id,
1999 .get_sset_count = igb_get_sset_count,
2000 .get_ethtool_stats = igb_get_ethtool_stats,
2001 .get_coalesce = igb_get_coalesce,
2002 .set_coalesce = igb_set_coalesce,
2003 };
2004
2005 void igb_set_ethtool_ops(struct net_device *netdev)
2006 {
2007 SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);
2008 }
Linux kernel - Deliverables
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