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[deliverable/linux.git] / drivers / net / igb / igb_ethtool.c
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 /* ethtool support for igb */
29
30 #include <linux/vmalloc.h>
31 #include <linux/netdevice.h>
32 #include <linux/pci.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
35 #include <linux/if_ether.h>
36 #include <linux/ethtool.h>
37
38 #include "igb.h"
39
40 struct igb_stats {
41 char stat_string[ETH_GSTRING_LEN];
42 int sizeof_stat;
43 int stat_offset;
44 };
45
46 #define IGB_STAT(m) FIELD_SIZEOF(struct igb_adapter, m), \
47 offsetof(struct igb_adapter, m)
48 static const struct igb_stats igb_gstrings_stats[] = {
49 { "rx_packets", IGB_STAT(stats.gprc) },
50 { "tx_packets", IGB_STAT(stats.gptc) },
51 { "rx_bytes", IGB_STAT(stats.gorc) },
52 { "tx_bytes", IGB_STAT(stats.gotc) },
53 { "rx_broadcast", IGB_STAT(stats.bprc) },
54 { "tx_broadcast", IGB_STAT(stats.bptc) },
55 { "rx_multicast", IGB_STAT(stats.mprc) },
56 { "tx_multicast", IGB_STAT(stats.mptc) },
57 { "rx_errors", IGB_STAT(net_stats.rx_errors) },
58 { "tx_errors", IGB_STAT(net_stats.tx_errors) },
59 { "tx_dropped", IGB_STAT(net_stats.tx_dropped) },
60 { "multicast", IGB_STAT(stats.mprc) },
61 { "collisions", IGB_STAT(stats.colc) },
62 { "rx_length_errors", IGB_STAT(net_stats.rx_length_errors) },
63 { "rx_over_errors", IGB_STAT(net_stats.rx_over_errors) },
64 { "rx_crc_errors", IGB_STAT(stats.crcerrs) },
65 { "rx_frame_errors", IGB_STAT(net_stats.rx_frame_errors) },
66 { "rx_no_buffer_count", IGB_STAT(stats.rnbc) },
67 { "rx_missed_errors", IGB_STAT(stats.mpc) },
68 { "tx_aborted_errors", IGB_STAT(stats.ecol) },
69 { "tx_carrier_errors", IGB_STAT(stats.tncrs) },
70 { "tx_fifo_errors", IGB_STAT(net_stats.tx_fifo_errors) },
71 { "tx_heartbeat_errors", IGB_STAT(net_stats.tx_heartbeat_errors) },
72 { "tx_window_errors", IGB_STAT(stats.latecol) },
73 { "tx_abort_late_coll", IGB_STAT(stats.latecol) },
74 { "tx_deferred_ok", IGB_STAT(stats.dc) },
75 { "tx_single_coll_ok", IGB_STAT(stats.scc) },
76 { "tx_multi_coll_ok", IGB_STAT(stats.mcc) },
77 { "tx_timeout_count", IGB_STAT(tx_timeout_count) },
78 { "tx_restart_queue", IGB_STAT(restart_queue) },
79 { "rx_long_length_errors", IGB_STAT(stats.roc) },
80 { "rx_short_length_errors", IGB_STAT(stats.ruc) },
81 { "rx_align_errors", IGB_STAT(stats.algnerrc) },
82 { "tx_tcp_seg_good", IGB_STAT(stats.tsctc) },
83 { "tx_tcp_seg_failed", IGB_STAT(stats.tsctfc) },
84 { "rx_flow_control_xon", IGB_STAT(stats.xonrxc) },
85 { "rx_flow_control_xoff", IGB_STAT(stats.xoffrxc) },
86 { "tx_flow_control_xon", IGB_STAT(stats.xontxc) },
87 { "tx_flow_control_xoff", IGB_STAT(stats.xofftxc) },
88 { "rx_long_byte_count", IGB_STAT(stats.gorc) },
89 { "rx_csum_offload_good", IGB_STAT(hw_csum_good) },
90 { "rx_csum_offload_errors", IGB_STAT(hw_csum_err) },
91 { "rx_header_split", IGB_STAT(rx_hdr_split) },
92 { "alloc_rx_buff_failed", IGB_STAT(alloc_rx_buff_failed) },
93 { "tx_smbus", IGB_STAT(stats.mgptc) },
94 { "rx_smbus", IGB_STAT(stats.mgprc) },
95 { "dropped_smbus", IGB_STAT(stats.mgpdc) },
96 };
97
98 #define IGB_QUEUE_STATS_LEN \
99 ((((struct igb_adapter *)netdev->priv)->num_rx_queues + \
100 ((struct igb_adapter *)netdev->priv)->num_tx_queues) * \
101 (sizeof(struct igb_queue_stats) / sizeof(u64)))
102 #define IGB_GLOBAL_STATS_LEN \
103 sizeof(igb_gstrings_stats) / sizeof(struct igb_stats)
104 #define IGB_STATS_LEN (IGB_GLOBAL_STATS_LEN + IGB_QUEUE_STATS_LEN)
105 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
106 "Register test (offline)", "Eeprom test (offline)",
107 "Interrupt test (offline)", "Loopback test (offline)",
108 "Link test (on/offline)"
109 };
110 #define IGB_TEST_LEN sizeof(igb_gstrings_test) / ETH_GSTRING_LEN
111
112 static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
113 {
114 struct igb_adapter *adapter = netdev_priv(netdev);
115 struct e1000_hw *hw = &adapter->hw;
116
117 if (hw->phy.media_type == e1000_media_type_copper) {
118
119 ecmd->supported = (SUPPORTED_10baseT_Half |
120 SUPPORTED_10baseT_Full |
121 SUPPORTED_100baseT_Half |
122 SUPPORTED_100baseT_Full |
123 SUPPORTED_1000baseT_Full|
124 SUPPORTED_Autoneg |
125 SUPPORTED_TP);
126 ecmd->advertising = ADVERTISED_TP;
127
128 if (hw->mac.autoneg == 1) {
129 ecmd->advertising |= ADVERTISED_Autoneg;
130 /* the e1000 autoneg seems to match ethtool nicely */
131 ecmd->advertising |= hw->phy.autoneg_advertised;
132 }
133
134 ecmd->port = PORT_TP;
135 ecmd->phy_address = hw->phy.addr;
136 } else {
137 ecmd->supported = (SUPPORTED_1000baseT_Full |
138 SUPPORTED_FIBRE |
139 SUPPORTED_Autoneg);
140
141 ecmd->advertising = (ADVERTISED_1000baseT_Full |
142 ADVERTISED_FIBRE |
143 ADVERTISED_Autoneg);
144
145 ecmd->port = PORT_FIBRE;
146 }
147
148 ecmd->transceiver = XCVR_INTERNAL;
149
150 if (rd32(E1000_STATUS) & E1000_STATUS_LU) {
151
152 adapter->hw.mac.ops.get_speed_and_duplex(hw,
153 &adapter->link_speed,
154 &adapter->link_duplex);
155 ecmd->speed = adapter->link_speed;
156
157 /* unfortunately FULL_DUPLEX != DUPLEX_FULL
158 * and HALF_DUPLEX != DUPLEX_HALF */
159
160 if (adapter->link_duplex == FULL_DUPLEX)
161 ecmd->duplex = DUPLEX_FULL;
162 else
163 ecmd->duplex = DUPLEX_HALF;
164 } else {
165 ecmd->speed = -1;
166 ecmd->duplex = -1;
167 }
168
169 ecmd->autoneg = ((hw->phy.media_type == e1000_media_type_fiber) ||
170 hw->mac.autoneg) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
171 return 0;
172 }
173
174 static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
175 {
176 struct igb_adapter *adapter = netdev_priv(netdev);
177 struct e1000_hw *hw = &adapter->hw;
178
179 /* When SoL/IDER sessions are active, autoneg/speed/duplex
180 * cannot be changed */
181 if (igb_check_reset_block(hw)) {
182 dev_err(&adapter->pdev->dev, "Cannot change link "
183 "characteristics when SoL/IDER is active.\n");
184 return -EINVAL;
185 }
186
187 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
188 msleep(1);
189
190 if (ecmd->autoneg == AUTONEG_ENABLE) {
191 hw->mac.autoneg = 1;
192 if (hw->phy.media_type == e1000_media_type_fiber)
193 hw->phy.autoneg_advertised = ADVERTISED_1000baseT_Full |
194 ADVERTISED_FIBRE |
195 ADVERTISED_Autoneg;
196 else
197 hw->phy.autoneg_advertised = ecmd->advertising |
198 ADVERTISED_TP |
199 ADVERTISED_Autoneg;
200 ecmd->advertising = hw->phy.autoneg_advertised;
201 } else
202 if (igb_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
203 clear_bit(__IGB_RESETTING, &adapter->state);
204 return -EINVAL;
205 }
206
207 /* reset the link */
208
209 if (netif_running(adapter->netdev)) {
210 igb_down(adapter);
211 igb_up(adapter);
212 } else
213 igb_reset(adapter);
214
215 clear_bit(__IGB_RESETTING, &adapter->state);
216 return 0;
217 }
218
219 static void igb_get_pauseparam(struct net_device *netdev,
220 struct ethtool_pauseparam *pause)
221 {
222 struct igb_adapter *adapter = netdev_priv(netdev);
223 struct e1000_hw *hw = &adapter->hw;
224
225 pause->autoneg =
226 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
227
228 if (hw->fc.type == e1000_fc_rx_pause)
229 pause->rx_pause = 1;
230 else if (hw->fc.type == e1000_fc_tx_pause)
231 pause->tx_pause = 1;
232 else if (hw->fc.type == e1000_fc_full) {
233 pause->rx_pause = 1;
234 pause->tx_pause = 1;
235 }
236 }
237
238 static int igb_set_pauseparam(struct net_device *netdev,
239 struct ethtool_pauseparam *pause)
240 {
241 struct igb_adapter *adapter = netdev_priv(netdev);
242 struct e1000_hw *hw = &adapter->hw;
243 int retval = 0;
244
245 adapter->fc_autoneg = pause->autoneg;
246
247 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
248 msleep(1);
249
250 if (pause->rx_pause && pause->tx_pause)
251 hw->fc.type = e1000_fc_full;
252 else if (pause->rx_pause && !pause->tx_pause)
253 hw->fc.type = e1000_fc_rx_pause;
254 else if (!pause->rx_pause && pause->tx_pause)
255 hw->fc.type = e1000_fc_tx_pause;
256 else if (!pause->rx_pause && !pause->tx_pause)
257 hw->fc.type = e1000_fc_none;
258
259 hw->fc.original_type = hw->fc.type;
260
261 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
262 if (netif_running(adapter->netdev)) {
263 igb_down(adapter);
264 igb_up(adapter);
265 } else
266 igb_reset(adapter);
267 } else
268 retval = ((hw->phy.media_type == e1000_media_type_fiber) ?
269 igb_setup_link(hw) : igb_force_mac_fc(hw));
270
271 clear_bit(__IGB_RESETTING, &adapter->state);
272 return retval;
273 }
274
275 static u32 igb_get_rx_csum(struct net_device *netdev)
276 {
277 struct igb_adapter *adapter = netdev_priv(netdev);
278 return adapter->rx_csum;
279 }
280
281 static int igb_set_rx_csum(struct net_device *netdev, u32 data)
282 {
283 struct igb_adapter *adapter = netdev_priv(netdev);
284 adapter->rx_csum = data;
285
286 return 0;
287 }
288
289 static u32 igb_get_tx_csum(struct net_device *netdev)
290 {
291 return (netdev->features & NETIF_F_HW_CSUM) != 0;
292 }
293
294 static int igb_set_tx_csum(struct net_device *netdev, u32 data)
295 {
296 if (data)
297 netdev->features |= NETIF_F_HW_CSUM;
298 else
299 netdev->features &= ~NETIF_F_HW_CSUM;
300
301 return 0;
302 }
303
304 static int igb_set_tso(struct net_device *netdev, u32 data)
305 {
306 struct igb_adapter *adapter = netdev_priv(netdev);
307
308 if (data)
309 netdev->features |= NETIF_F_TSO;
310 else
311 netdev->features &= ~NETIF_F_TSO;
312
313 if (data)
314 netdev->features |= NETIF_F_TSO6;
315 else
316 netdev->features &= ~NETIF_F_TSO6;
317
318 dev_info(&adapter->pdev->dev, "TSO is %s\n",
319 data ? "Enabled" : "Disabled");
320 return 0;
321 }
322
323 static u32 igb_get_msglevel(struct net_device *netdev)
324 {
325 struct igb_adapter *adapter = netdev_priv(netdev);
326 return adapter->msg_enable;
327 }
328
329 static void igb_set_msglevel(struct net_device *netdev, u32 data)
330 {
331 struct igb_adapter *adapter = netdev_priv(netdev);
332 adapter->msg_enable = data;
333 }
334
335 static int igb_get_regs_len(struct net_device *netdev)
336 {
337 #define IGB_REGS_LEN 551
338 return IGB_REGS_LEN * sizeof(u32);
339 }
340
341 static void igb_get_regs(struct net_device *netdev,
342 struct ethtool_regs *regs, void *p)
343 {
344 struct igb_adapter *adapter = netdev_priv(netdev);
345 struct e1000_hw *hw = &adapter->hw;
346 u32 *regs_buff = p;
347 u8 i;
348
349 memset(p, 0, IGB_REGS_LEN * sizeof(u32));
350
351 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
352
353 /* General Registers */
354 regs_buff[0] = rd32(E1000_CTRL);
355 regs_buff[1] = rd32(E1000_STATUS);
356 regs_buff[2] = rd32(E1000_CTRL_EXT);
357 regs_buff[3] = rd32(E1000_MDIC);
358 regs_buff[4] = rd32(E1000_SCTL);
359 regs_buff[5] = rd32(E1000_CONNSW);
360 regs_buff[6] = rd32(E1000_VET);
361 regs_buff[7] = rd32(E1000_LEDCTL);
362 regs_buff[8] = rd32(E1000_PBA);
363 regs_buff[9] = rd32(E1000_PBS);
364 regs_buff[10] = rd32(E1000_FRTIMER);
365 regs_buff[11] = rd32(E1000_TCPTIMER);
366
367 /* NVM Register */
368 regs_buff[12] = rd32(E1000_EECD);
369
370 /* Interrupt */
371 regs_buff[13] = rd32(E1000_EICR);
372 regs_buff[14] = rd32(E1000_EICS);
373 regs_buff[15] = rd32(E1000_EIMS);
374 regs_buff[16] = rd32(E1000_EIMC);
375 regs_buff[17] = rd32(E1000_EIAC);
376 regs_buff[18] = rd32(E1000_EIAM);
377 regs_buff[19] = rd32(E1000_ICR);
378 regs_buff[20] = rd32(E1000_ICS);
379 regs_buff[21] = rd32(E1000_IMS);
380 regs_buff[22] = rd32(E1000_IMC);
381 regs_buff[23] = rd32(E1000_IAC);
382 regs_buff[24] = rd32(E1000_IAM);
383 regs_buff[25] = rd32(E1000_IMIRVP);
384
385 /* Flow Control */
386 regs_buff[26] = rd32(E1000_FCAL);
387 regs_buff[27] = rd32(E1000_FCAH);
388 regs_buff[28] = rd32(E1000_FCTTV);
389 regs_buff[29] = rd32(E1000_FCRTL);
390 regs_buff[30] = rd32(E1000_FCRTH);
391 regs_buff[31] = rd32(E1000_FCRTV);
392
393 /* Receive */
394 regs_buff[32] = rd32(E1000_RCTL);
395 regs_buff[33] = rd32(E1000_RXCSUM);
396 regs_buff[34] = rd32(E1000_RLPML);
397 regs_buff[35] = rd32(E1000_RFCTL);
398 regs_buff[36] = rd32(E1000_MRQC);
399 regs_buff[37] = rd32(E1000_VMD_CTL);
400
401 /* Transmit */
402 regs_buff[38] = rd32(E1000_TCTL);
403 regs_buff[39] = rd32(E1000_TCTL_EXT);
404 regs_buff[40] = rd32(E1000_TIPG);
405 regs_buff[41] = rd32(E1000_DTXCTL);
406
407 /* Wake Up */
408 regs_buff[42] = rd32(E1000_WUC);
409 regs_buff[43] = rd32(E1000_WUFC);
410 regs_buff[44] = rd32(E1000_WUS);
411 regs_buff[45] = rd32(E1000_IPAV);
412 regs_buff[46] = rd32(E1000_WUPL);
413
414 /* MAC */
415 regs_buff[47] = rd32(E1000_PCS_CFG0);
416 regs_buff[48] = rd32(E1000_PCS_LCTL);
417 regs_buff[49] = rd32(E1000_PCS_LSTAT);
418 regs_buff[50] = rd32(E1000_PCS_ANADV);
419 regs_buff[51] = rd32(E1000_PCS_LPAB);
420 regs_buff[52] = rd32(E1000_PCS_NPTX);
421 regs_buff[53] = rd32(E1000_PCS_LPABNP);
422
423 /* Statistics */
424 regs_buff[54] = adapter->stats.crcerrs;
425 regs_buff[55] = adapter->stats.algnerrc;
426 regs_buff[56] = adapter->stats.symerrs;
427 regs_buff[57] = adapter->stats.rxerrc;
428 regs_buff[58] = adapter->stats.mpc;
429 regs_buff[59] = adapter->stats.scc;
430 regs_buff[60] = adapter->stats.ecol;
431 regs_buff[61] = adapter->stats.mcc;
432 regs_buff[62] = adapter->stats.latecol;
433 regs_buff[63] = adapter->stats.colc;
434 regs_buff[64] = adapter->stats.dc;
435 regs_buff[65] = adapter->stats.tncrs;
436 regs_buff[66] = adapter->stats.sec;
437 regs_buff[67] = adapter->stats.htdpmc;
438 regs_buff[68] = adapter->stats.rlec;
439 regs_buff[69] = adapter->stats.xonrxc;
440 regs_buff[70] = adapter->stats.xontxc;
441 regs_buff[71] = adapter->stats.xoffrxc;
442 regs_buff[72] = adapter->stats.xofftxc;
443 regs_buff[73] = adapter->stats.fcruc;
444 regs_buff[74] = adapter->stats.prc64;
445 regs_buff[75] = adapter->stats.prc127;
446 regs_buff[76] = adapter->stats.prc255;
447 regs_buff[77] = adapter->stats.prc511;
448 regs_buff[78] = adapter->stats.prc1023;
449 regs_buff[79] = adapter->stats.prc1522;
450 regs_buff[80] = adapter->stats.gprc;
451 regs_buff[81] = adapter->stats.bprc;
452 regs_buff[82] = adapter->stats.mprc;
453 regs_buff[83] = adapter->stats.gptc;
454 regs_buff[84] = adapter->stats.gorc;
455 regs_buff[86] = adapter->stats.gotc;
456 regs_buff[88] = adapter->stats.rnbc;
457 regs_buff[89] = adapter->stats.ruc;
458 regs_buff[90] = adapter->stats.rfc;
459 regs_buff[91] = adapter->stats.roc;
460 regs_buff[92] = adapter->stats.rjc;
461 regs_buff[93] = adapter->stats.mgprc;
462 regs_buff[94] = adapter->stats.mgpdc;
463 regs_buff[95] = adapter->stats.mgptc;
464 regs_buff[96] = adapter->stats.tor;
465 regs_buff[98] = adapter->stats.tot;
466 regs_buff[100] = adapter->stats.tpr;
467 regs_buff[101] = adapter->stats.tpt;
468 regs_buff[102] = adapter->stats.ptc64;
469 regs_buff[103] = adapter->stats.ptc127;
470 regs_buff[104] = adapter->stats.ptc255;
471 regs_buff[105] = adapter->stats.ptc511;
472 regs_buff[106] = adapter->stats.ptc1023;
473 regs_buff[107] = adapter->stats.ptc1522;
474 regs_buff[108] = adapter->stats.mptc;
475 regs_buff[109] = adapter->stats.bptc;
476 regs_buff[110] = adapter->stats.tsctc;
477 regs_buff[111] = adapter->stats.iac;
478 regs_buff[112] = adapter->stats.rpthc;
479 regs_buff[113] = adapter->stats.hgptc;
480 regs_buff[114] = adapter->stats.hgorc;
481 regs_buff[116] = adapter->stats.hgotc;
482 regs_buff[118] = adapter->stats.lenerrs;
483 regs_buff[119] = adapter->stats.scvpc;
484 regs_buff[120] = adapter->stats.hrmpc;
485
486 /* These should probably be added to e1000_regs.h instead */
487 #define E1000_PSRTYPE_REG(_i) (0x05480 + ((_i) * 4))
488 #define E1000_RAL(_i) (0x05400 + ((_i) * 8))
489 #define E1000_RAH(_i) (0x05404 + ((_i) * 8))
490 #define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8))
491 #define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4))
492 #define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4))
493 #define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8))
494 #define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8))
495 #define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8))
496
497 for (i = 0; i < 4; i++)
498 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
499 for (i = 0; i < 4; i++)
500 regs_buff[125 + i] = rd32(E1000_PSRTYPE_REG(i));
501 for (i = 0; i < 4; i++)
502 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
503 for (i = 0; i < 4; i++)
504 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
505 for (i = 0; i < 4; i++)
506 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
507 for (i = 0; i < 4; i++)
508 regs_buff[141 + i] = rd32(E1000_RDH(i));
509 for (i = 0; i < 4; i++)
510 regs_buff[145 + i] = rd32(E1000_RDT(i));
511 for (i = 0; i < 4; i++)
512 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
513
514 for (i = 0; i < 10; i++)
515 regs_buff[153 + i] = rd32(E1000_EITR(i));
516 for (i = 0; i < 8; i++)
517 regs_buff[163 + i] = rd32(E1000_IMIR(i));
518 for (i = 0; i < 8; i++)
519 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
520 for (i = 0; i < 16; i++)
521 regs_buff[179 + i] = rd32(E1000_RAL(i));
522 for (i = 0; i < 16; i++)
523 regs_buff[195 + i] = rd32(E1000_RAH(i));
524
525 for (i = 0; i < 4; i++)
526 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
527 for (i = 0; i < 4; i++)
528 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
529 for (i = 0; i < 4; i++)
530 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
531 for (i = 0; i < 4; i++)
532 regs_buff[223 + i] = rd32(E1000_TDH(i));
533 for (i = 0; i < 4; i++)
534 regs_buff[227 + i] = rd32(E1000_TDT(i));
535 for (i = 0; i < 4; i++)
536 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
537 for (i = 0; i < 4; i++)
538 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
539 for (i = 0; i < 4; i++)
540 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
541 for (i = 0; i < 4; i++)
542 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
543
544 for (i = 0; i < 4; i++)
545 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
546 for (i = 0; i < 4; i++)
547 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
548 for (i = 0; i < 32; i++)
549 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
550 for (i = 0; i < 128; i++)
551 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
552 for (i = 0; i < 128; i++)
553 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
554 for (i = 0; i < 4; i++)
555 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
556
557 regs_buff[547] = rd32(E1000_TDFH);
558 regs_buff[548] = rd32(E1000_TDFT);
559 regs_buff[549] = rd32(E1000_TDFHS);
560 regs_buff[550] = rd32(E1000_TDFPC);
561
562 }
563
564 static int igb_get_eeprom_len(struct net_device *netdev)
565 {
566 struct igb_adapter *adapter = netdev_priv(netdev);
567 return adapter->hw.nvm.word_size * 2;
568 }
569
570 static int igb_get_eeprom(struct net_device *netdev,
571 struct ethtool_eeprom *eeprom, u8 *bytes)
572 {
573 struct igb_adapter *adapter = netdev_priv(netdev);
574 struct e1000_hw *hw = &adapter->hw;
575 u16 *eeprom_buff;
576 int first_word, last_word;
577 int ret_val = 0;
578 u16 i;
579
580 if (eeprom->len == 0)
581 return -EINVAL;
582
583 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
584
585 first_word = eeprom->offset >> 1;
586 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
587
588 eeprom_buff = kmalloc(sizeof(u16) *
589 (last_word - first_word + 1), GFP_KERNEL);
590 if (!eeprom_buff)
591 return -ENOMEM;
592
593 if (hw->nvm.type == e1000_nvm_eeprom_spi)
594 ret_val = hw->nvm.ops.read_nvm(hw, first_word,
595 last_word - first_word + 1,
596 eeprom_buff);
597 else {
598 for (i = 0; i < last_word - first_word + 1; i++) {
599 ret_val = hw->nvm.ops.read_nvm(hw, first_word + i, 1,
600 &eeprom_buff[i]);
601 if (ret_val)
602 break;
603 }
604 }
605
606 /* Device's eeprom is always little-endian, word addressable */
607 for (i = 0; i < last_word - first_word + 1; i++)
608 le16_to_cpus(&eeprom_buff[i]);
609
610 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
611 eeprom->len);
612 kfree(eeprom_buff);
613
614 return ret_val;
615 }
616
617 static int igb_set_eeprom(struct net_device *netdev,
618 struct ethtool_eeprom *eeprom, u8 *bytes)
619 {
620 struct igb_adapter *adapter = netdev_priv(netdev);
621 struct e1000_hw *hw = &adapter->hw;
622 u16 *eeprom_buff;
623 void *ptr;
624 int max_len, first_word, last_word, ret_val = 0;
625 u16 i;
626
627 if (eeprom->len == 0)
628 return -EOPNOTSUPP;
629
630 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
631 return -EFAULT;
632
633 max_len = hw->nvm.word_size * 2;
634
635 first_word = eeprom->offset >> 1;
636 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
637 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
638 if (!eeprom_buff)
639 return -ENOMEM;
640
641 ptr = (void *)eeprom_buff;
642
643 if (eeprom->offset & 1) {
644 /* need read/modify/write of first changed EEPROM word */
645 /* only the second byte of the word is being modified */
646 ret_val = hw->nvm.ops.read_nvm(hw, first_word, 1,
647 &eeprom_buff[0]);
648 ptr++;
649 }
650 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
651 /* need read/modify/write of last changed EEPROM word */
652 /* only the first byte of the word is being modified */
653 ret_val = hw->nvm.ops.read_nvm(hw, last_word, 1,
654 &eeprom_buff[last_word - first_word]);
655 }
656
657 /* Device's eeprom is always little-endian, word addressable */
658 for (i = 0; i < last_word - first_word + 1; i++)
659 le16_to_cpus(&eeprom_buff[i]);
660
661 memcpy(ptr, bytes, eeprom->len);
662
663 for (i = 0; i < last_word - first_word + 1; i++)
664 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
665
666 ret_val = hw->nvm.ops.write_nvm(hw, first_word,
667 last_word - first_word + 1, eeprom_buff);
668
669 /* Update the checksum over the first part of the EEPROM if needed
670 * and flush shadow RAM for 82573 controllers */
671 if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
672 igb_update_nvm_checksum(hw);
673
674 kfree(eeprom_buff);
675 return ret_val;
676 }
677
678 static void igb_get_drvinfo(struct net_device *netdev,
679 struct ethtool_drvinfo *drvinfo)
680 {
681 struct igb_adapter *adapter = netdev_priv(netdev);
682 char firmware_version[32];
683 u16 eeprom_data;
684
685 strncpy(drvinfo->driver, igb_driver_name, 32);
686 strncpy(drvinfo->version, igb_driver_version, 32);
687
688 /* EEPROM image version # is reported as firmware version # for
689 * 82575 controllers */
690 adapter->hw.nvm.ops.read_nvm(&adapter->hw, 5, 1, &eeprom_data);
691 sprintf(firmware_version, "%d.%d-%d",
692 (eeprom_data & 0xF000) >> 12,
693 (eeprom_data & 0x0FF0) >> 4,
694 eeprom_data & 0x000F);
695
696 strncpy(drvinfo->fw_version, firmware_version, 32);
697 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
698 drvinfo->n_stats = IGB_STATS_LEN;
699 drvinfo->testinfo_len = IGB_TEST_LEN;
700 drvinfo->regdump_len = igb_get_regs_len(netdev);
701 drvinfo->eedump_len = igb_get_eeprom_len(netdev);
702 }
703
704 static void igb_get_ringparam(struct net_device *netdev,
705 struct ethtool_ringparam *ring)
706 {
707 struct igb_adapter *adapter = netdev_priv(netdev);
708 struct igb_ring *tx_ring = adapter->tx_ring;
709 struct igb_ring *rx_ring = adapter->rx_ring;
710
711 ring->rx_max_pending = IGB_MAX_RXD;
712 ring->tx_max_pending = IGB_MAX_TXD;
713 ring->rx_mini_max_pending = 0;
714 ring->rx_jumbo_max_pending = 0;
715 ring->rx_pending = rx_ring->count;
716 ring->tx_pending = tx_ring->count;
717 ring->rx_mini_pending = 0;
718 ring->rx_jumbo_pending = 0;
719 }
720
721 static int igb_set_ringparam(struct net_device *netdev,
722 struct ethtool_ringparam *ring)
723 {
724 struct igb_adapter *adapter = netdev_priv(netdev);
725 struct igb_buffer *old_buf;
726 struct igb_buffer *old_rx_buf;
727 void *old_desc;
728 int i, err;
729 u32 new_rx_count, new_tx_count, old_size;
730 dma_addr_t old_dma;
731
732 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
733 return -EINVAL;
734
735 new_rx_count = max(ring->rx_pending, (u32)IGB_MIN_RXD);
736 new_rx_count = min(new_rx_count, (u32)IGB_MAX_RXD);
737 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
738
739 new_tx_count = max(ring->tx_pending, (u32)IGB_MIN_TXD);
740 new_tx_count = min(new_tx_count, (u32)IGB_MAX_TXD);
741 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
742
743 if ((new_tx_count == adapter->tx_ring->count) &&
744 (new_rx_count == adapter->rx_ring->count)) {
745 /* nothing to do */
746 return 0;
747 }
748
749 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
750 msleep(1);
751
752 if (netif_running(adapter->netdev))
753 igb_down(adapter);
754
755 /*
756 * We can't just free everything and then setup again,
757 * because the ISRs in MSI-X mode get passed pointers
758 * to the tx and rx ring structs.
759 */
760 if (new_tx_count != adapter->tx_ring->count) {
761 for (i = 0; i < adapter->num_tx_queues; i++) {
762 /* Save existing descriptor ring */
763 old_buf = adapter->tx_ring[i].buffer_info;
764 old_desc = adapter->tx_ring[i].desc;
765 old_size = adapter->tx_ring[i].size;
766 old_dma = adapter->tx_ring[i].dma;
767 /* Try to allocate a new one */
768 adapter->tx_ring[i].buffer_info = NULL;
769 adapter->tx_ring[i].desc = NULL;
770 adapter->tx_ring[i].count = new_tx_count;
771 err = igb_setup_tx_resources(adapter,
772 &adapter->tx_ring[i]);
773 if (err) {
774 /* Restore the old one so at least
775 the adapter still works, even if
776 we failed the request */
777 adapter->tx_ring[i].buffer_info = old_buf;
778 adapter->tx_ring[i].desc = old_desc;
779 adapter->tx_ring[i].size = old_size;
780 adapter->tx_ring[i].dma = old_dma;
781 goto err_setup;
782 }
783 /* Free the old buffer manually */
784 vfree(old_buf);
785 pci_free_consistent(adapter->pdev, old_size,
786 old_desc, old_dma);
787 }
788 }
789
790 if (new_rx_count != adapter->rx_ring->count) {
791 for (i = 0; i < adapter->num_rx_queues; i++) {
792
793 old_rx_buf = adapter->rx_ring[i].buffer_info;
794 old_desc = adapter->rx_ring[i].desc;
795 old_size = adapter->rx_ring[i].size;
796 old_dma = adapter->rx_ring[i].dma;
797
798 adapter->rx_ring[i].buffer_info = NULL;
799 adapter->rx_ring[i].desc = NULL;
800 adapter->rx_ring[i].dma = 0;
801 adapter->rx_ring[i].count = new_rx_count;
802 err = igb_setup_rx_resources(adapter,
803 &adapter->rx_ring[i]);
804 if (err) {
805 adapter->rx_ring[i].buffer_info = old_rx_buf;
806 adapter->rx_ring[i].desc = old_desc;
807 adapter->rx_ring[i].size = old_size;
808 adapter->rx_ring[i].dma = old_dma;
809 goto err_setup;
810 }
811
812 vfree(old_rx_buf);
813 pci_free_consistent(adapter->pdev, old_size, old_desc,
814 old_dma);
815 }
816 }
817
818 err = 0;
819 err_setup:
820 if (netif_running(adapter->netdev))
821 igb_up(adapter);
822
823 clear_bit(__IGB_RESETTING, &adapter->state);
824 return err;
825 }
826
827 /* ethtool register test data */
828 struct igb_reg_test {
829 u16 reg;
830 u8 array_len;
831 u8 test_type;
832 u32 mask;
833 u32 write;
834 };
835
836 /* In the hardware, registers are laid out either singly, in arrays
837 * spaced 0x100 bytes apart, or in contiguous tables. We assume
838 * most tests take place on arrays or single registers (handled
839 * as a single-element array) and special-case the tables.
840 * Table tests are always pattern tests.
841 *
842 * We also make provision for some required setup steps by specifying
843 * registers to be written without any read-back testing.
844 */
845
846 #define PATTERN_TEST 1
847 #define SET_READ_TEST 2
848 #define WRITE_NO_TEST 3
849 #define TABLE32_TEST 4
850 #define TABLE64_TEST_LO 5
851 #define TABLE64_TEST_HI 6
852
853 /* default register test */
854 static struct igb_reg_test reg_test_82575[] = {
855 { E1000_FCAL, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
856 { E1000_FCAH, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
857 { E1000_FCT, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
858 { E1000_VET, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
859 { E1000_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
860 { E1000_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
861 { E1000_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
862 /* Enable all four RX queues before testing. */
863 { E1000_RXDCTL(0), 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
864 /* RDH is read-only for 82575, only test RDT. */
865 { E1000_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
866 { E1000_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
867 { E1000_FCRTH, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
868 { E1000_FCTTV, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
869 { E1000_TIPG, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
870 { E1000_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
871 { E1000_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
872 { E1000_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
873 { E1000_RCTL, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
874 { E1000_RCTL, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
875 { E1000_RCTL, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
876 { E1000_TCTL, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
877 { E1000_TXCW, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
878 { E1000_RA, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
879 { E1000_RA, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
880 { E1000_MTA, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
881 { 0, 0, 0, 0 }
882 };
883
884 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
885 int reg, u32 mask, u32 write)
886 {
887 u32 pat, val;
888 u32 _test[] =
889 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
890 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
891 writel((_test[pat] & write), (adapter->hw.hw_addr + reg));
892 val = readl(adapter->hw.hw_addr + reg);
893 if (val != (_test[pat] & write & mask)) {
894 dev_err(&adapter->pdev->dev, "pattern test reg %04X "
895 "failed: got 0x%08X expected 0x%08X\n",
896 reg, val, (_test[pat] & write & mask));
897 *data = reg;
898 return 1;
899 }
900 }
901 return 0;
902 }
903
904 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
905 int reg, u32 mask, u32 write)
906 {
907 u32 val;
908 writel((write & mask), (adapter->hw.hw_addr + reg));
909 val = readl(adapter->hw.hw_addr + reg);
910 if ((write & mask) != (val & mask)) {
911 dev_err(&adapter->pdev->dev, "set/check reg %04X test failed:"
912 " got 0x%08X expected 0x%08X\n", reg,
913 (val & mask), (write & mask));
914 *data = reg;
915 return 1;
916 }
917 return 0;
918 }
919
920 #define REG_PATTERN_TEST(reg, mask, write) \
921 do { \
922 if (reg_pattern_test(adapter, data, reg, mask, write)) \
923 return 1; \
924 } while (0)
925
926 #define REG_SET_AND_CHECK(reg, mask, write) \
927 do { \
928 if (reg_set_and_check(adapter, data, reg, mask, write)) \
929 return 1; \
930 } while (0)
931
932 static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
933 {
934 struct e1000_hw *hw = &adapter->hw;
935 struct igb_reg_test *test;
936 u32 value, before, after;
937 u32 i, toggle;
938
939 toggle = 0x7FFFF3FF;
940 test = reg_test_82575;
941
942 /* Because the status register is such a special case,
943 * we handle it separately from the rest of the register
944 * tests. Some bits are read-only, some toggle, and some
945 * are writable on newer MACs.
946 */
947 before = rd32(E1000_STATUS);
948 value = (rd32(E1000_STATUS) & toggle);
949 wr32(E1000_STATUS, toggle);
950 after = rd32(E1000_STATUS) & toggle;
951 if (value != after) {
952 dev_err(&adapter->pdev->dev, "failed STATUS register test "
953 "got: 0x%08X expected: 0x%08X\n", after, value);
954 *data = 1;
955 return 1;
956 }
957 /* restore previous status */
958 wr32(E1000_STATUS, before);
959
960 /* Perform the remainder of the register test, looping through
961 * the test table until we either fail or reach the null entry.
962 */
963 while (test->reg) {
964 for (i = 0; i < test->array_len; i++) {
965 switch (test->test_type) {
966 case PATTERN_TEST:
967 REG_PATTERN_TEST(test->reg + (i * 0x100),
968 test->mask,
969 test->write);
970 break;
971 case SET_READ_TEST:
972 REG_SET_AND_CHECK(test->reg + (i * 0x100),
973 test->mask,
974 test->write);
975 break;
976 case WRITE_NO_TEST:
977 writel(test->write,
978 (adapter->hw.hw_addr + test->reg)
979 + (i * 0x100));
980 break;
981 case TABLE32_TEST:
982 REG_PATTERN_TEST(test->reg + (i * 4),
983 test->mask,
984 test->write);
985 break;
986 case TABLE64_TEST_LO:
987 REG_PATTERN_TEST(test->reg + (i * 8),
988 test->mask,
989 test->write);
990 break;
991 case TABLE64_TEST_HI:
992 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
993 test->mask,
994 test->write);
995 break;
996 }
997 }
998 test++;
999 }
1000
1001 *data = 0;
1002 return 0;
1003 }
1004
1005 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1006 {
1007 u16 temp;
1008 u16 checksum = 0;
1009 u16 i;
1010
1011 *data = 0;
1012 /* Read and add up the contents of the EEPROM */
1013 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1014 if ((adapter->hw.nvm.ops.read_nvm(&adapter->hw, i, 1, &temp))
1015 < 0) {
1016 *data = 1;
1017 break;
1018 }
1019 checksum += temp;
1020 }
1021
1022 /* If Checksum is not Correct return error else test passed */
1023 if ((checksum != (u16) NVM_SUM) && !(*data))
1024 *data = 2;
1025
1026 return *data;
1027 }
1028
1029 static irqreturn_t igb_test_intr(int irq, void *data)
1030 {
1031 struct net_device *netdev = (struct net_device *) data;
1032 struct igb_adapter *adapter = netdev_priv(netdev);
1033 struct e1000_hw *hw = &adapter->hw;
1034
1035 adapter->test_icr |= rd32(E1000_ICR);
1036
1037 return IRQ_HANDLED;
1038 }
1039
1040 static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1041 {
1042 struct e1000_hw *hw = &adapter->hw;
1043 struct net_device *netdev = adapter->netdev;
1044 u32 mask, i = 0, shared_int = true;
1045 u32 irq = adapter->pdev->irq;
1046
1047 *data = 0;
1048
1049 /* Hook up test interrupt handler just for this test */
1050 if (adapter->msix_entries) {
1051 /* NOTE: we don't test MSI-X interrupts here, yet */
1052 return 0;
1053 } else if (adapter->msi_enabled) {
1054 shared_int = false;
1055 if (request_irq(irq, &igb_test_intr, 0, netdev->name, netdev)) {
1056 *data = 1;
1057 return -1;
1058 }
1059 } else if (!request_irq(irq, &igb_test_intr, IRQF_PROBE_SHARED,
1060 netdev->name, netdev)) {
1061 shared_int = false;
1062 } else if (request_irq(irq, &igb_test_intr, IRQF_SHARED,
1063 netdev->name, netdev)) {
1064 *data = 1;
1065 return -1;
1066 }
1067 dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1068 (shared_int ? "shared" : "unshared"));
1069
1070 /* Disable all the interrupts */
1071 wr32(E1000_IMC, 0xFFFFFFFF);
1072 msleep(10);
1073
1074 /* Test each interrupt */
1075 for (; i < 10; i++) {
1076 /* Interrupt to test */
1077 mask = 1 << i;
1078
1079 if (!shared_int) {
1080 /* Disable the interrupt to be reported in
1081 * the cause register and then force the same
1082 * interrupt and see if one gets posted. If
1083 * an interrupt was posted to the bus, the
1084 * test failed.
1085 */
1086 adapter->test_icr = 0;
1087 wr32(E1000_IMC, ~mask & 0x00007FFF);
1088 wr32(E1000_ICS, ~mask & 0x00007FFF);
1089 msleep(10);
1090
1091 if (adapter->test_icr & mask) {
1092 *data = 3;
1093 break;
1094 }
1095 }
1096
1097 /* Enable the interrupt to be reported in
1098 * the cause register and then force the same
1099 * interrupt and see if one gets posted. If
1100 * an interrupt was not posted to the bus, the
1101 * test failed.
1102 */
1103 adapter->test_icr = 0;
1104 wr32(E1000_IMS, mask);
1105 wr32(E1000_ICS, mask);
1106 msleep(10);
1107
1108 if (!(adapter->test_icr & mask)) {
1109 *data = 4;
1110 break;
1111 }
1112
1113 if (!shared_int) {
1114 /* Disable the other interrupts to be reported in
1115 * the cause register and then force the other
1116 * interrupts and see if any get posted. If
1117 * an interrupt was posted to the bus, the
1118 * test failed.
1119 */
1120 adapter->test_icr = 0;
1121 wr32(E1000_IMC, ~mask & 0x00007FFF);
1122 wr32(E1000_ICS, ~mask & 0x00007FFF);
1123 msleep(10);
1124
1125 if (adapter->test_icr) {
1126 *data = 5;
1127 break;
1128 }
1129 }
1130 }
1131
1132 /* Disable all the interrupts */
1133 wr32(E1000_IMC, 0xFFFFFFFF);
1134 msleep(10);
1135
1136 /* Unhook test interrupt handler */
1137 free_irq(irq, netdev);
1138
1139 return *data;
1140 }
1141
1142 static void igb_free_desc_rings(struct igb_adapter *adapter)
1143 {
1144 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1145 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1146 struct pci_dev *pdev = adapter->pdev;
1147 int i;
1148
1149 if (tx_ring->desc && tx_ring->buffer_info) {
1150 for (i = 0; i < tx_ring->count; i++) {
1151 struct igb_buffer *buf = &(tx_ring->buffer_info[i]);
1152 if (buf->dma)
1153 pci_unmap_single(pdev, buf->dma, buf->length,
1154 PCI_DMA_TODEVICE);
1155 if (buf->skb)
1156 dev_kfree_skb(buf->skb);
1157 }
1158 }
1159
1160 if (rx_ring->desc && rx_ring->buffer_info) {
1161 for (i = 0; i < rx_ring->count; i++) {
1162 struct igb_buffer *buf = &(rx_ring->buffer_info[i]);
1163 if (buf->dma)
1164 pci_unmap_single(pdev, buf->dma,
1165 IGB_RXBUFFER_2048,
1166 PCI_DMA_FROMDEVICE);
1167 if (buf->skb)
1168 dev_kfree_skb(buf->skb);
1169 }
1170 }
1171
1172 if (tx_ring->desc) {
1173 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc,
1174 tx_ring->dma);
1175 tx_ring->desc = NULL;
1176 }
1177 if (rx_ring->desc) {
1178 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc,
1179 rx_ring->dma);
1180 rx_ring->desc = NULL;
1181 }
1182
1183 kfree(tx_ring->buffer_info);
1184 tx_ring->buffer_info = NULL;
1185 kfree(rx_ring->buffer_info);
1186 rx_ring->buffer_info = NULL;
1187
1188 return;
1189 }
1190
1191 static int igb_setup_desc_rings(struct igb_adapter *adapter)
1192 {
1193 struct e1000_hw *hw = &adapter->hw;
1194 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1195 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1196 struct pci_dev *pdev = adapter->pdev;
1197 u32 rctl;
1198 int i, ret_val;
1199
1200 /* Setup Tx descriptor ring and Tx buffers */
1201
1202 if (!tx_ring->count)
1203 tx_ring->count = IGB_DEFAULT_TXD;
1204
1205 tx_ring->buffer_info = kcalloc(tx_ring->count,
1206 sizeof(struct igb_buffer),
1207 GFP_KERNEL);
1208 if (!tx_ring->buffer_info) {
1209 ret_val = 1;
1210 goto err_nomem;
1211 }
1212
1213 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
1214 tx_ring->size = ALIGN(tx_ring->size, 4096);
1215 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1216 &tx_ring->dma);
1217 if (!tx_ring->desc) {
1218 ret_val = 2;
1219 goto err_nomem;
1220 }
1221 tx_ring->next_to_use = tx_ring->next_to_clean = 0;
1222
1223 wr32(E1000_TDBAL(0),
1224 ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
1225 wr32(E1000_TDBAH(0), ((u64) tx_ring->dma >> 32));
1226 wr32(E1000_TDLEN(0),
1227 tx_ring->count * sizeof(struct e1000_tx_desc));
1228 wr32(E1000_TDH(0), 0);
1229 wr32(E1000_TDT(0), 0);
1230 wr32(E1000_TCTL,
1231 E1000_TCTL_PSP | E1000_TCTL_EN |
1232 E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT |
1233 E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT);
1234
1235 for (i = 0; i < tx_ring->count; i++) {
1236 struct e1000_tx_desc *tx_desc = E1000_TX_DESC(*tx_ring, i);
1237 struct sk_buff *skb;
1238 unsigned int size = 1024;
1239
1240 skb = alloc_skb(size, GFP_KERNEL);
1241 if (!skb) {
1242 ret_val = 3;
1243 goto err_nomem;
1244 }
1245 skb_put(skb, size);
1246 tx_ring->buffer_info[i].skb = skb;
1247 tx_ring->buffer_info[i].length = skb->len;
1248 tx_ring->buffer_info[i].dma =
1249 pci_map_single(pdev, skb->data, skb->len,
1250 PCI_DMA_TODEVICE);
1251 tx_desc->buffer_addr = cpu_to_le64(tx_ring->buffer_info[i].dma);
1252 tx_desc->lower.data = cpu_to_le32(skb->len);
1253 tx_desc->lower.data |= cpu_to_le32(E1000_TXD_CMD_EOP |
1254 E1000_TXD_CMD_IFCS |
1255 E1000_TXD_CMD_RS);
1256 tx_desc->upper.data = 0;
1257 }
1258
1259 /* Setup Rx descriptor ring and Rx buffers */
1260
1261 if (!rx_ring->count)
1262 rx_ring->count = IGB_DEFAULT_RXD;
1263
1264 rx_ring->buffer_info = kcalloc(rx_ring->count,
1265 sizeof(struct igb_buffer),
1266 GFP_KERNEL);
1267 if (!rx_ring->buffer_info) {
1268 ret_val = 4;
1269 goto err_nomem;
1270 }
1271
1272 rx_ring->size = rx_ring->count * sizeof(struct e1000_rx_desc);
1273 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1274 &rx_ring->dma);
1275 if (!rx_ring->desc) {
1276 ret_val = 5;
1277 goto err_nomem;
1278 }
1279 rx_ring->next_to_use = rx_ring->next_to_clean = 0;
1280
1281 rctl = rd32(E1000_RCTL);
1282 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1283 wr32(E1000_RDBAL(0),
1284 ((u64) rx_ring->dma & 0xFFFFFFFF));
1285 wr32(E1000_RDBAH(0),
1286 ((u64) rx_ring->dma >> 32));
1287 wr32(E1000_RDLEN(0), rx_ring->size);
1288 wr32(E1000_RDH(0), 0);
1289 wr32(E1000_RDT(0), 0);
1290 rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 |
1291 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1292 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1293 wr32(E1000_RCTL, rctl);
1294 wr32(E1000_SRRCTL(0), 0);
1295
1296 for (i = 0; i < rx_ring->count; i++) {
1297 struct e1000_rx_desc *rx_desc = E1000_RX_DESC(*rx_ring, i);
1298 struct sk_buff *skb;
1299
1300 skb = alloc_skb(IGB_RXBUFFER_2048 + NET_IP_ALIGN,
1301 GFP_KERNEL);
1302 if (!skb) {
1303 ret_val = 6;
1304 goto err_nomem;
1305 }
1306 skb_reserve(skb, NET_IP_ALIGN);
1307 rx_ring->buffer_info[i].skb = skb;
1308 rx_ring->buffer_info[i].dma =
1309 pci_map_single(pdev, skb->data, IGB_RXBUFFER_2048,
1310 PCI_DMA_FROMDEVICE);
1311 rx_desc->buffer_addr = cpu_to_le64(rx_ring->buffer_info[i].dma);
1312 memset(skb->data, 0x00, skb->len);
1313 }
1314
1315 return 0;
1316
1317 err_nomem:
1318 igb_free_desc_rings(adapter);
1319 return ret_val;
1320 }
1321
1322 static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1323 {
1324 struct e1000_hw *hw = &adapter->hw;
1325
1326 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1327 hw->phy.ops.write_phy_reg(hw, 29, 0x001F);
1328 hw->phy.ops.write_phy_reg(hw, 30, 0x8FFC);
1329 hw->phy.ops.write_phy_reg(hw, 29, 0x001A);
1330 hw->phy.ops.write_phy_reg(hw, 30, 0x8FF0);
1331 }
1332
1333 static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1334 {
1335 struct e1000_hw *hw = &adapter->hw;
1336 u32 ctrl_reg = 0;
1337 u32 stat_reg = 0;
1338
1339 hw->mac.autoneg = false;
1340
1341 if (hw->phy.type == e1000_phy_m88) {
1342 /* Auto-MDI/MDIX Off */
1343 hw->phy.ops.write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1344 /* reset to update Auto-MDI/MDIX */
1345 hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, 0x9140);
1346 /* autoneg off */
1347 hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, 0x8140);
1348 }
1349
1350 ctrl_reg = rd32(E1000_CTRL);
1351
1352 /* force 1000, set loopback */
1353 hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, 0x4140);
1354
1355 /* Now set up the MAC to the same speed/duplex as the PHY. */
1356 ctrl_reg = rd32(E1000_CTRL);
1357 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1358 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1359 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1360 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1361 E1000_CTRL_FD); /* Force Duplex to FULL */
1362
1363 if (hw->phy.media_type == e1000_media_type_copper &&
1364 hw->phy.type == e1000_phy_m88)
1365 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1366 else {
1367 /* Set the ILOS bit on the fiber Nic if half duplex link is
1368 * detected. */
1369 stat_reg = rd32(E1000_STATUS);
1370 if ((stat_reg & E1000_STATUS_FD) == 0)
1371 ctrl_reg |= (E1000_CTRL_ILOS | E1000_CTRL_SLU);
1372 }
1373
1374 wr32(E1000_CTRL, ctrl_reg);
1375
1376 /* Disable the receiver on the PHY so when a cable is plugged in, the
1377 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1378 */
1379 if (hw->phy.type == e1000_phy_m88)
1380 igb_phy_disable_receiver(adapter);
1381
1382 udelay(500);
1383
1384 return 0;
1385 }
1386
1387 static int igb_set_phy_loopback(struct igb_adapter *adapter)
1388 {
1389 return igb_integrated_phy_loopback(adapter);
1390 }
1391
1392 static int igb_setup_loopback_test(struct igb_adapter *adapter)
1393 {
1394 struct e1000_hw *hw = &adapter->hw;
1395 u32 rctl;
1396
1397 if (hw->phy.media_type == e1000_media_type_fiber ||
1398 hw->phy.media_type == e1000_media_type_internal_serdes) {
1399 rctl = rd32(E1000_RCTL);
1400 rctl |= E1000_RCTL_LBM_TCVR;
1401 wr32(E1000_RCTL, rctl);
1402 return 0;
1403 } else if (hw->phy.media_type == e1000_media_type_copper) {
1404 return igb_set_phy_loopback(adapter);
1405 }
1406
1407 return 7;
1408 }
1409
1410 static void igb_loopback_cleanup(struct igb_adapter *adapter)
1411 {
1412 struct e1000_hw *hw = &adapter->hw;
1413 u32 rctl;
1414 u16 phy_reg;
1415
1416 rctl = rd32(E1000_RCTL);
1417 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1418 wr32(E1000_RCTL, rctl);
1419
1420 hw->mac.autoneg = true;
1421 hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &phy_reg);
1422 if (phy_reg & MII_CR_LOOPBACK) {
1423 phy_reg &= ~MII_CR_LOOPBACK;
1424 hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, phy_reg);
1425 igb_phy_sw_reset(hw);
1426 }
1427 }
1428
1429 static void igb_create_lbtest_frame(struct sk_buff *skb,
1430 unsigned int frame_size)
1431 {
1432 memset(skb->data, 0xFF, frame_size);
1433 frame_size &= ~1;
1434 memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1435 memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1436 memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1437 }
1438
1439 static int igb_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
1440 {
1441 frame_size &= ~1;
1442 if (*(skb->data + 3) == 0xFF)
1443 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1444 (*(skb->data + frame_size / 2 + 12) == 0xAF))
1445 return 0;
1446 return 13;
1447 }
1448
1449 static int igb_run_loopback_test(struct igb_adapter *adapter)
1450 {
1451 struct e1000_hw *hw = &adapter->hw;
1452 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1453 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1454 struct pci_dev *pdev = adapter->pdev;
1455 int i, j, k, l, lc, good_cnt;
1456 int ret_val = 0;
1457 unsigned long time;
1458
1459 wr32(E1000_RDT(0), rx_ring->count - 1);
1460
1461 /* Calculate the loop count based on the largest descriptor ring
1462 * The idea is to wrap the largest ring a number of times using 64
1463 * send/receive pairs during each loop
1464 */
1465
1466 if (rx_ring->count <= tx_ring->count)
1467 lc = ((tx_ring->count / 64) * 2) + 1;
1468 else
1469 lc = ((rx_ring->count / 64) * 2) + 1;
1470
1471 k = l = 0;
1472 for (j = 0; j <= lc; j++) { /* loop count loop */
1473 for (i = 0; i < 64; i++) { /* send the packets */
1474 igb_create_lbtest_frame(tx_ring->buffer_info[k].skb,
1475 1024);
1476 pci_dma_sync_single_for_device(pdev,
1477 tx_ring->buffer_info[k].dma,
1478 tx_ring->buffer_info[k].length,
1479 PCI_DMA_TODEVICE);
1480 k++;
1481 if (k == tx_ring->count)
1482 k = 0;
1483 }
1484 wr32(E1000_TDT(0), k);
1485 msleep(200);
1486 time = jiffies; /* set the start time for the receive */
1487 good_cnt = 0;
1488 do { /* receive the sent packets */
1489 pci_dma_sync_single_for_cpu(pdev,
1490 rx_ring->buffer_info[l].dma,
1491 IGB_RXBUFFER_2048,
1492 PCI_DMA_FROMDEVICE);
1493
1494 ret_val = igb_check_lbtest_frame(
1495 rx_ring->buffer_info[l].skb, 1024);
1496 if (!ret_val)
1497 good_cnt++;
1498 l++;
1499 if (l == rx_ring->count)
1500 l = 0;
1501 /* time + 20 msecs (200 msecs on 2.4) is more than
1502 * enough time to complete the receives, if it's
1503 * exceeded, break and error off
1504 */
1505 } while (good_cnt < 64 && jiffies < (time + 20));
1506 if (good_cnt != 64) {
1507 ret_val = 13; /* ret_val is the same as mis-compare */
1508 break;
1509 }
1510 if (jiffies >= (time + 20)) {
1511 ret_val = 14; /* error code for time out error */
1512 break;
1513 }
1514 } /* end loop count loop */
1515 return ret_val;
1516 }
1517
1518 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1519 {
1520 /* PHY loopback cannot be performed if SoL/IDER
1521 * sessions are active */
1522 if (igb_check_reset_block(&adapter->hw)) {
1523 dev_err(&adapter->pdev->dev,
1524 "Cannot do PHY loopback test "
1525 "when SoL/IDER is active.\n");
1526 *data = 0;
1527 goto out;
1528 }
1529 *data = igb_setup_desc_rings(adapter);
1530 if (*data)
1531 goto out;
1532 *data = igb_setup_loopback_test(adapter);
1533 if (*data)
1534 goto err_loopback;
1535 *data = igb_run_loopback_test(adapter);
1536 igb_loopback_cleanup(adapter);
1537
1538 err_loopback:
1539 igb_free_desc_rings(adapter);
1540 out:
1541 return *data;
1542 }
1543
1544 static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1545 {
1546 struct e1000_hw *hw = &adapter->hw;
1547 *data = 0;
1548 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1549 int i = 0;
1550 hw->mac.serdes_has_link = false;
1551
1552 /* On some blade server designs, link establishment
1553 * could take as long as 2-3 minutes */
1554 do {
1555 hw->mac.ops.check_for_link(&adapter->hw);
1556 if (hw->mac.serdes_has_link)
1557 return *data;
1558 msleep(20);
1559 } while (i++ < 3750);
1560
1561 *data = 1;
1562 } else {
1563 hw->mac.ops.check_for_link(&adapter->hw);
1564 if (hw->mac.autoneg)
1565 msleep(4000);
1566
1567 if (!(rd32(E1000_STATUS) &
1568 E1000_STATUS_LU))
1569 *data = 1;
1570 }
1571 return *data;
1572 }
1573
1574 static void igb_diag_test(struct net_device *netdev,
1575 struct ethtool_test *eth_test, u64 *data)
1576 {
1577 struct igb_adapter *adapter = netdev_priv(netdev);
1578 u16 autoneg_advertised;
1579 u8 forced_speed_duplex, autoneg;
1580 bool if_running = netif_running(netdev);
1581
1582 set_bit(__IGB_TESTING, &adapter->state);
1583 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1584 /* Offline tests */
1585
1586 /* save speed, duplex, autoneg settings */
1587 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1588 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1589 autoneg = adapter->hw.mac.autoneg;
1590
1591 dev_info(&adapter->pdev->dev, "offline testing starting\n");
1592
1593 /* Link test performed before hardware reset so autoneg doesn't
1594 * interfere with test result */
1595 if (igb_link_test(adapter, &data[4]))
1596 eth_test->flags |= ETH_TEST_FL_FAILED;
1597
1598 if (if_running)
1599 /* indicate we're in test mode */
1600 dev_close(netdev);
1601 else
1602 igb_reset(adapter);
1603
1604 if (igb_reg_test(adapter, &data[0]))
1605 eth_test->flags |= ETH_TEST_FL_FAILED;
1606
1607 igb_reset(adapter);
1608 if (igb_eeprom_test(adapter, &data[1]))
1609 eth_test->flags |= ETH_TEST_FL_FAILED;
1610
1611 igb_reset(adapter);
1612 if (igb_intr_test(adapter, &data[2]))
1613 eth_test->flags |= ETH_TEST_FL_FAILED;
1614
1615 igb_reset(adapter);
1616 if (igb_loopback_test(adapter, &data[3]))
1617 eth_test->flags |= ETH_TEST_FL_FAILED;
1618
1619 /* restore speed, duplex, autoneg settings */
1620 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
1621 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
1622 adapter->hw.mac.autoneg = autoneg;
1623
1624 /* force this routine to wait until autoneg complete/timeout */
1625 adapter->hw.phy.autoneg_wait_to_complete = true;
1626 igb_reset(adapter);
1627 adapter->hw.phy.autoneg_wait_to_complete = false;
1628
1629 clear_bit(__IGB_TESTING, &adapter->state);
1630 if (if_running)
1631 dev_open(netdev);
1632 } else {
1633 dev_info(&adapter->pdev->dev, "online testing starting\n");
1634 /* Online tests */
1635 if (igb_link_test(adapter, &data[4]))
1636 eth_test->flags |= ETH_TEST_FL_FAILED;
1637
1638 /* Online tests aren't run; pass by default */
1639 data[0] = 0;
1640 data[1] = 0;
1641 data[2] = 0;
1642 data[3] = 0;
1643
1644 clear_bit(__IGB_TESTING, &adapter->state);
1645 }
1646 msleep_interruptible(4 * 1000);
1647 }
1648
1649 static int igb_wol_exclusion(struct igb_adapter *adapter,
1650 struct ethtool_wolinfo *wol)
1651 {
1652 struct e1000_hw *hw = &adapter->hw;
1653 int retval = 1; /* fail by default */
1654
1655 switch (hw->device_id) {
1656 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1657 /* WoL not supported */
1658 wol->supported = 0;
1659 break;
1660 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1661 /* Wake events not supported on port B */
1662 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) {
1663 wol->supported = 0;
1664 break;
1665 }
1666 /* return success for non excluded adapter ports */
1667 retval = 0;
1668 break;
1669 default:
1670 /* dual port cards only support WoL on port A from now on
1671 * unless it was enabled in the eeprom for port B
1672 * so exclude FUNC_1 ports from having WoL enabled */
1673 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1 &&
1674 !adapter->eeprom_wol) {
1675 wol->supported = 0;
1676 break;
1677 }
1678
1679 retval = 0;
1680 }
1681
1682 return retval;
1683 }
1684
1685 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1686 {
1687 struct igb_adapter *adapter = netdev_priv(netdev);
1688
1689 wol->supported = WAKE_UCAST | WAKE_MCAST |
1690 WAKE_BCAST | WAKE_MAGIC;
1691 wol->wolopts = 0;
1692
1693 /* this function will set ->supported = 0 and return 1 if wol is not
1694 * supported by this hardware */
1695 if (igb_wol_exclusion(adapter, wol))
1696 return;
1697
1698 /* apply any specific unsupported masks here */
1699 switch (adapter->hw.device_id) {
1700 default:
1701 break;
1702 }
1703
1704 if (adapter->wol & E1000_WUFC_EX)
1705 wol->wolopts |= WAKE_UCAST;
1706 if (adapter->wol & E1000_WUFC_MC)
1707 wol->wolopts |= WAKE_MCAST;
1708 if (adapter->wol & E1000_WUFC_BC)
1709 wol->wolopts |= WAKE_BCAST;
1710 if (adapter->wol & E1000_WUFC_MAG)
1711 wol->wolopts |= WAKE_MAGIC;
1712
1713 return;
1714 }
1715
1716 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1717 {
1718 struct igb_adapter *adapter = netdev_priv(netdev);
1719 struct e1000_hw *hw = &adapter->hw;
1720
1721 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1722 return -EOPNOTSUPP;
1723
1724 if (igb_wol_exclusion(adapter, wol))
1725 return wol->wolopts ? -EOPNOTSUPP : 0;
1726
1727 switch (hw->device_id) {
1728 default:
1729 break;
1730 }
1731
1732 /* these settings will always override what we currently have */
1733 adapter->wol = 0;
1734
1735 if (wol->wolopts & WAKE_UCAST)
1736 adapter->wol |= E1000_WUFC_EX;
1737 if (wol->wolopts & WAKE_MCAST)
1738 adapter->wol |= E1000_WUFC_MC;
1739 if (wol->wolopts & WAKE_BCAST)
1740 adapter->wol |= E1000_WUFC_BC;
1741 if (wol->wolopts & WAKE_MAGIC)
1742 adapter->wol |= E1000_WUFC_MAG;
1743
1744 return 0;
1745 }
1746
1747 /* toggle LED 4 times per second = 2 "blinks" per second */
1748 #define IGB_ID_INTERVAL (HZ/4)
1749
1750 /* bit defines for adapter->led_status */
1751 #define IGB_LED_ON 0
1752
1753 static int igb_phys_id(struct net_device *netdev, u32 data)
1754 {
1755 struct igb_adapter *adapter = netdev_priv(netdev);
1756 struct e1000_hw *hw = &adapter->hw;
1757
1758 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
1759 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
1760
1761 igb_blink_led(hw);
1762 msleep_interruptible(data * 1000);
1763
1764 igb_led_off(hw);
1765 clear_bit(IGB_LED_ON, &adapter->led_status);
1766 igb_cleanup_led(hw);
1767
1768 return 0;
1769 }
1770
1771 static int igb_set_coalesce(struct net_device *netdev,
1772 struct ethtool_coalesce *ec)
1773 {
1774 struct igb_adapter *adapter = netdev_priv(netdev);
1775
1776 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1777 ((ec->rx_coalesce_usecs > 3) &&
1778 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
1779 (ec->rx_coalesce_usecs == 2))
1780 return -EINVAL;
1781
1782 /* convert to rate of irq's per second */
1783 if (ec->rx_coalesce_usecs <= 3)
1784 adapter->itr_setting = ec->rx_coalesce_usecs;
1785 else
1786 adapter->itr_setting = (1000000 / ec->rx_coalesce_usecs);
1787
1788 if (netif_running(netdev))
1789 igb_reinit_locked(adapter);
1790
1791 return 0;
1792 }
1793
1794 static int igb_get_coalesce(struct net_device *netdev,
1795 struct ethtool_coalesce *ec)
1796 {
1797 struct igb_adapter *adapter = netdev_priv(netdev);
1798
1799 if (adapter->itr_setting <= 3)
1800 ec->rx_coalesce_usecs = adapter->itr_setting;
1801 else
1802 ec->rx_coalesce_usecs = 1000000 / adapter->itr_setting;
1803
1804 return 0;
1805 }
1806
1807
1808 static int igb_nway_reset(struct net_device *netdev)
1809 {
1810 struct igb_adapter *adapter = netdev_priv(netdev);
1811 if (netif_running(netdev))
1812 igb_reinit_locked(adapter);
1813 return 0;
1814 }
1815
1816 static int igb_get_sset_count(struct net_device *netdev, int sset)
1817 {
1818 switch (sset) {
1819 case ETH_SS_STATS:
1820 return IGB_STATS_LEN;
1821 case ETH_SS_TEST:
1822 return IGB_TEST_LEN;
1823 default:
1824 return -ENOTSUPP;
1825 }
1826 }
1827
1828 static void igb_get_ethtool_stats(struct net_device *netdev,
1829 struct ethtool_stats *stats, u64 *data)
1830 {
1831 struct igb_adapter *adapter = netdev_priv(netdev);
1832 u64 *queue_stat;
1833 int stat_count = sizeof(struct igb_queue_stats) / sizeof(u64);
1834 int j;
1835 int i;
1836
1837 igb_update_stats(adapter);
1838 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
1839 char *p = (char *)adapter+igb_gstrings_stats[i].stat_offset;
1840 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
1841 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1842 }
1843 for (j = 0; j < adapter->num_tx_queues; j++) {
1844 int k;
1845 queue_stat = (u64 *)&adapter->tx_ring[j].tx_stats;
1846 for (k = 0; k < stat_count; k++)
1847 data[i + k] = queue_stat[k];
1848 i += k;
1849 }
1850 for (j = 0; j < adapter->num_rx_queues; j++) {
1851 int k;
1852 queue_stat = (u64 *)&adapter->rx_ring[j].rx_stats;
1853 for (k = 0; k < stat_count; k++)
1854 data[i + k] = queue_stat[k];
1855 i += k;
1856 }
1857 }
1858
1859 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
1860 {
1861 struct igb_adapter *adapter = netdev_priv(netdev);
1862 u8 *p = data;
1863 int i;
1864
1865 switch (stringset) {
1866 case ETH_SS_TEST:
1867 memcpy(data, *igb_gstrings_test,
1868 IGB_TEST_LEN*ETH_GSTRING_LEN);
1869 break;
1870 case ETH_SS_STATS:
1871 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
1872 memcpy(p, igb_gstrings_stats[i].stat_string,
1873 ETH_GSTRING_LEN);
1874 p += ETH_GSTRING_LEN;
1875 }
1876 for (i = 0; i < adapter->num_tx_queues; i++) {
1877 sprintf(p, "tx_queue_%u_packets", i);
1878 p += ETH_GSTRING_LEN;
1879 sprintf(p, "tx_queue_%u_bytes", i);
1880 p += ETH_GSTRING_LEN;
1881 }
1882 for (i = 0; i < adapter->num_rx_queues; i++) {
1883 sprintf(p, "rx_queue_%u_packets", i);
1884 p += ETH_GSTRING_LEN;
1885 sprintf(p, "rx_queue_%u_bytes", i);
1886 p += ETH_GSTRING_LEN;
1887 }
1888 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
1889 break;
1890 }
1891 }
1892
1893 static struct ethtool_ops igb_ethtool_ops = {
1894 .get_settings = igb_get_settings,
1895 .set_settings = igb_set_settings,
1896 .get_drvinfo = igb_get_drvinfo,
1897 .get_regs_len = igb_get_regs_len,
1898 .get_regs = igb_get_regs,
1899 .get_wol = igb_get_wol,
1900 .set_wol = igb_set_wol,
1901 .get_msglevel = igb_get_msglevel,
1902 .set_msglevel = igb_set_msglevel,
1903 .nway_reset = igb_nway_reset,
1904 .get_link = ethtool_op_get_link,
1905 .get_eeprom_len = igb_get_eeprom_len,
1906 .get_eeprom = igb_get_eeprom,
1907 .set_eeprom = igb_set_eeprom,
1908 .get_ringparam = igb_get_ringparam,
1909 .set_ringparam = igb_set_ringparam,
1910 .get_pauseparam = igb_get_pauseparam,
1911 .set_pauseparam = igb_set_pauseparam,
1912 .get_rx_csum = igb_get_rx_csum,
1913 .set_rx_csum = igb_set_rx_csum,
1914 .get_tx_csum = igb_get_tx_csum,
1915 .set_tx_csum = igb_set_tx_csum,
1916 .get_sg = ethtool_op_get_sg,
1917 .set_sg = ethtool_op_set_sg,
1918 .get_tso = ethtool_op_get_tso,
1919 .set_tso = igb_set_tso,
1920 .self_test = igb_diag_test,
1921 .get_strings = igb_get_strings,
1922 .phys_id = igb_phys_id,
1923 .get_sset_count = igb_get_sset_count,
1924 .get_ethtool_stats = igb_get_ethtool_stats,
1925 .get_coalesce = igb_get_coalesce,
1926 .set_coalesce = igb_set_coalesce,
1927 };
1928
1929 void igb_set_ethtool_ops(struct net_device *netdev)
1930 {
1931 SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);
1932 }
Linux kernel - Deliverables
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