projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[deliverable/linux.git] / drivers / net / igb / igb_main.c
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/module.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/vmalloc.h>
32 #include <linux/pagemap.h>
33 #include <linux/netdevice.h>
34 #include <linux/ipv6.h>
35 #include <net/checksum.h>
36 #include <net/ip6_checksum.h>
37 #include <linux/mii.h>
38 #include <linux/ethtool.h>
39 #include <linux/if_vlan.h>
40 #include <linux/pci.h>
41 #include <linux/delay.h>
42 #include <linux/interrupt.h>
43 #include <linux/if_ether.h>
44
45 #include "igb.h"
46
47 #define DRV_VERSION "1.0.8-k2"
48 char igb_driver_name[] = "igb";
49 char igb_driver_version[] = DRV_VERSION;
50 static const char igb_driver_string[] =
51 "Intel(R) Gigabit Ethernet Network Driver";
52 static const char igb_copyright[] = "Copyright (c) 2007 Intel Corporation.";
53
54
55 static const struct e1000_info *igb_info_tbl[] = {
56 [board_82575] = &e1000_82575_info,
57 };
58
59 static struct pci_device_id igb_pci_tbl[] = {
60 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
61 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
62 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
63 /* required last entry */
64 {0, }
65 };
66
67 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
68
69 void igb_reset(struct igb_adapter *);
70 static int igb_setup_all_tx_resources(struct igb_adapter *);
71 static int igb_setup_all_rx_resources(struct igb_adapter *);
72 static void igb_free_all_tx_resources(struct igb_adapter *);
73 static void igb_free_all_rx_resources(struct igb_adapter *);
74 static void igb_free_tx_resources(struct igb_adapter *, struct igb_ring *);
75 static void igb_free_rx_resources(struct igb_adapter *, struct igb_ring *);
76 void igb_update_stats(struct igb_adapter *);
77 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
78 static void __devexit igb_remove(struct pci_dev *pdev);
79 static int igb_sw_init(struct igb_adapter *);
80 static int igb_open(struct net_device *);
81 static int igb_close(struct net_device *);
82 static void igb_configure_tx(struct igb_adapter *);
83 static void igb_configure_rx(struct igb_adapter *);
84 static void igb_setup_rctl(struct igb_adapter *);
85 static void igb_clean_all_tx_rings(struct igb_adapter *);
86 static void igb_clean_all_rx_rings(struct igb_adapter *);
87 static void igb_clean_tx_ring(struct igb_adapter *, struct igb_ring *);
88 static void igb_clean_rx_ring(struct igb_adapter *, struct igb_ring *);
89 static void igb_set_multi(struct net_device *);
90 static void igb_update_phy_info(unsigned long);
91 static void igb_watchdog(unsigned long);
92 static void igb_watchdog_task(struct work_struct *);
93 static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
94 struct igb_ring *);
95 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
96 static struct net_device_stats *igb_get_stats(struct net_device *);
97 static int igb_change_mtu(struct net_device *, int);
98 static int igb_set_mac(struct net_device *, void *);
99 static irqreturn_t igb_intr(int irq, void *);
100 static irqreturn_t igb_intr_msi(int irq, void *);
101 static irqreturn_t igb_msix_other(int irq, void *);
102 static irqreturn_t igb_msix_rx(int irq, void *);
103 static irqreturn_t igb_msix_tx(int irq, void *);
104 static int igb_clean_rx_ring_msix(struct napi_struct *, int);
105 static bool igb_clean_tx_irq(struct igb_adapter *, struct igb_ring *);
106 static int igb_clean(struct napi_struct *, int);
107 static bool igb_clean_rx_irq_adv(struct igb_adapter *,
108 struct igb_ring *, int *, int);
109 static void igb_alloc_rx_buffers_adv(struct igb_adapter *,
110 struct igb_ring *, int);
111 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
112 static void igb_tx_timeout(struct net_device *);
113 static void igb_reset_task(struct work_struct *);
114 static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
115 static void igb_vlan_rx_add_vid(struct net_device *, u16);
116 static void igb_vlan_rx_kill_vid(struct net_device *, u16);
117 static void igb_restore_vlan(struct igb_adapter *);
118
119 static int igb_suspend(struct pci_dev *, pm_message_t);
120 #ifdef CONFIG_PM
121 static int igb_resume(struct pci_dev *);
122 #endif
123 static void igb_shutdown(struct pci_dev *);
124
125 #ifdef CONFIG_NET_POLL_CONTROLLER
126 /* for netdump / net console */
127 static void igb_netpoll(struct net_device *);
128 #endif
129
130 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
131 pci_channel_state_t);
132 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
133 static void igb_io_resume(struct pci_dev *);
134
135 static struct pci_error_handlers igb_err_handler = {
136 .error_detected = igb_io_error_detected,
137 .slot_reset = igb_io_slot_reset,
138 .resume = igb_io_resume,
139 };
140
141
142 static struct pci_driver igb_driver = {
143 .name = igb_driver_name,
144 .id_table = igb_pci_tbl,
145 .probe = igb_probe,
146 .remove = __devexit_p(igb_remove),
147 #ifdef CONFIG_PM
148 /* Power Managment Hooks */
149 .suspend = igb_suspend,
150 .resume = igb_resume,
151 #endif
152 .shutdown = igb_shutdown,
153 .err_handler = &igb_err_handler
154 };
155
156 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
157 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
158 MODULE_LICENSE("GPL");
159 MODULE_VERSION(DRV_VERSION);
160
161 #ifdef DEBUG
162 /**
163 * igb_get_hw_dev_name - return device name string
164 * used by hardware layer to print debugging information
165 **/
166 char *igb_get_hw_dev_name(struct e1000_hw *hw)
167 {
168 struct igb_adapter *adapter = hw->back;
169 return adapter->netdev->name;
170 }
171 #endif
172
173 /**
174 * igb_init_module - Driver Registration Routine
175 *
176 * igb_init_module is the first routine called when the driver is
177 * loaded. All it does is register with the PCI subsystem.
178 **/
179 static int __init igb_init_module(void)
180 {
181 int ret;
182 printk(KERN_INFO "%s - version %s\n",
183 igb_driver_string, igb_driver_version);
184
185 printk(KERN_INFO "%s\n", igb_copyright);
186
187 ret = pci_register_driver(&igb_driver);
188 return ret;
189 }
190
191 module_init(igb_init_module);
192
193 /**
194 * igb_exit_module - Driver Exit Cleanup Routine
195 *
196 * igb_exit_module is called just before the driver is removed
197 * from memory.
198 **/
199 static void __exit igb_exit_module(void)
200 {
201 pci_unregister_driver(&igb_driver);
202 }
203
204 module_exit(igb_exit_module);
205
206 /**
207 * igb_alloc_queues - Allocate memory for all rings
208 * @adapter: board private structure to initialize
209 *
210 * We allocate one ring per queue at run-time since we don't know the
211 * number of queues at compile-time.
212 **/
213 static int igb_alloc_queues(struct igb_adapter *adapter)
214 {
215 int i;
216
217 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
218 sizeof(struct igb_ring), GFP_KERNEL);
219 if (!adapter->tx_ring)
220 return -ENOMEM;
221
222 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
223 sizeof(struct igb_ring), GFP_KERNEL);
224 if (!adapter->rx_ring) {
225 kfree(adapter->tx_ring);
226 return -ENOMEM;
227 }
228
229 for (i = 0; i < adapter->num_rx_queues; i++) {
230 struct igb_ring *ring = &(adapter->rx_ring[i]);
231 ring->adapter = adapter;
232 ring->itr_register = E1000_ITR;
233
234 if (!ring->napi.poll)
235 netif_napi_add(adapter->netdev, &ring->napi, igb_clean,
236 adapter->napi.weight /
237 adapter->num_rx_queues);
238 }
239 return 0;
240 }
241
242 #define IGB_N0_QUEUE -1
243 static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
244 int tx_queue, int msix_vector)
245 {
246 u32 msixbm = 0;
247 struct e1000_hw *hw = &adapter->hw;
248 /* The 82575 assigns vectors using a bitmask, which matches the
249 bitmask for the EICR/EIMS/EIMC registers. To assign one
250 or more queues to a vector, we write the appropriate bits
251 into the MSIXBM register for that vector. */
252 if (rx_queue > IGB_N0_QUEUE) {
253 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
254 adapter->rx_ring[rx_queue].eims_value = msixbm;
255 }
256 if (tx_queue > IGB_N0_QUEUE) {
257 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
258 adapter->tx_ring[tx_queue].eims_value =
259 E1000_EICR_TX_QUEUE0 << tx_queue;
260 }
261 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
262 }
263
264 /**
265 * igb_configure_msix - Configure MSI-X hardware
266 *
267 * igb_configure_msix sets up the hardware to properly
268 * generate MSI-X interrupts.
269 **/
270 static void igb_configure_msix(struct igb_adapter *adapter)
271 {
272 u32 tmp;
273 int i, vector = 0;
274 struct e1000_hw *hw = &adapter->hw;
275
276 adapter->eims_enable_mask = 0;
277
278 for (i = 0; i < adapter->num_tx_queues; i++) {
279 struct igb_ring *tx_ring = &adapter->tx_ring[i];
280 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
281 adapter->eims_enable_mask |= tx_ring->eims_value;
282 if (tx_ring->itr_val)
283 writel(1000000000 / (tx_ring->itr_val * 256),
284 hw->hw_addr + tx_ring->itr_register);
285 else
286 writel(1, hw->hw_addr + tx_ring->itr_register);
287 }
288
289 for (i = 0; i < adapter->num_rx_queues; i++) {
290 struct igb_ring *rx_ring = &adapter->rx_ring[i];
291 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
292 adapter->eims_enable_mask |= rx_ring->eims_value;
293 if (rx_ring->itr_val)
294 writel(1000000000 / (rx_ring->itr_val * 256),
295 hw->hw_addr + rx_ring->itr_register);
296 else
297 writel(1, hw->hw_addr + rx_ring->itr_register);
298 }
299
300
301 /* set vector for other causes, i.e. link changes */
302 array_wr32(E1000_MSIXBM(0), vector++,
303 E1000_EIMS_OTHER);
304
305 /* disable IAM for ICR interrupt bits */
306 wr32(E1000_IAM, 0);
307
308 tmp = rd32(E1000_CTRL_EXT);
309 /* enable MSI-X PBA support*/
310 tmp |= E1000_CTRL_EXT_PBA_CLR;
311
312 /* Auto-Mask interrupts upon ICR read. */
313 tmp |= E1000_CTRL_EXT_EIAME;
314 tmp |= E1000_CTRL_EXT_IRCA;
315
316 wr32(E1000_CTRL_EXT, tmp);
317 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
318
319 wrfl();
320 }
321
322 /**
323 * igb_request_msix - Initialize MSI-X interrupts
324 *
325 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
326 * kernel.
327 **/
328 static int igb_request_msix(struct igb_adapter *adapter)
329 {
330 struct net_device *netdev = adapter->netdev;
331 int i, err = 0, vector = 0;
332
333 vector = 0;
334
335 for (i = 0; i < adapter->num_tx_queues; i++) {
336 struct igb_ring *ring = &(adapter->tx_ring[i]);
337 sprintf(ring->name, "%s-tx%d", netdev->name, i);
338 err = request_irq(adapter->msix_entries[vector].vector,
339 &igb_msix_tx, 0, ring->name,
340 &(adapter->tx_ring[i]));
341 if (err)
342 goto out;
343 ring->itr_register = E1000_EITR(0) + (vector << 2);
344 ring->itr_val = adapter->itr;
345 vector++;
346 }
347 for (i = 0; i < adapter->num_rx_queues; i++) {
348 struct igb_ring *ring = &(adapter->rx_ring[i]);
349 if (strlen(netdev->name) < (IFNAMSIZ - 5))
350 sprintf(ring->name, "%s-rx%d", netdev->name, i);
351 else
352 memcpy(ring->name, netdev->name, IFNAMSIZ);
353 err = request_irq(adapter->msix_entries[vector].vector,
354 &igb_msix_rx, 0, ring->name,
355 &(adapter->rx_ring[i]));
356 if (err)
357 goto out;
358 ring->itr_register = E1000_EITR(0) + (vector << 2);
359 ring->itr_val = adapter->itr;
360 vector++;
361 }
362
363 err = request_irq(adapter->msix_entries[vector].vector,
364 &igb_msix_other, 0, netdev->name, netdev);
365 if (err)
366 goto out;
367
368 adapter->napi.poll = igb_clean_rx_ring_msix;
369 for (i = 0; i < adapter->num_rx_queues; i++)
370 adapter->rx_ring[i].napi.poll = adapter->napi.poll;
371 igb_configure_msix(adapter);
372 return 0;
373 out:
374 return err;
375 }
376
377 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
378 {
379 if (adapter->msix_entries) {
380 pci_disable_msix(adapter->pdev);
381 kfree(adapter->msix_entries);
382 adapter->msix_entries = NULL;
383 } else if (adapter->msi_enabled)
384 pci_disable_msi(adapter->pdev);
385 return;
386 }
387
388
389 /**
390 * igb_set_interrupt_capability - set MSI or MSI-X if supported
391 *
392 * Attempt to configure interrupts using the best available
393 * capabilities of the hardware and kernel.
394 **/
395 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
396 {
397 int err;
398 int numvecs, i;
399
400 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
401 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
402 GFP_KERNEL);
403 if (!adapter->msix_entries)
404 goto msi_only;
405
406 for (i = 0; i < numvecs; i++)
407 adapter->msix_entries[i].entry = i;
408
409 err = pci_enable_msix(adapter->pdev,
410 adapter->msix_entries,
411 numvecs);
412 if (err == 0)
413 return;
414
415 igb_reset_interrupt_capability(adapter);
416
417 /* If we can't do MSI-X, try MSI */
418 msi_only:
419 adapter->num_rx_queues = 1;
420 if (!pci_enable_msi(adapter->pdev))
421 adapter->msi_enabled = 1;
422 return;
423 }
424
425 /**
426 * igb_request_irq - initialize interrupts
427 *
428 * Attempts to configure interrupts using the best available
429 * capabilities of the hardware and kernel.
430 **/
431 static int igb_request_irq(struct igb_adapter *adapter)
432 {
433 struct net_device *netdev = adapter->netdev;
434 struct e1000_hw *hw = &adapter->hw;
435 int err = 0;
436
437 if (adapter->msix_entries) {
438 err = igb_request_msix(adapter);
439 if (!err) {
440 /* enable IAM, auto-mask,
441 * DO NOT USE EIAM or IAM in legacy mode */
442 wr32(E1000_IAM, IMS_ENABLE_MASK);
443 goto request_done;
444 }
445 /* fall back to MSI */
446 igb_reset_interrupt_capability(adapter);
447 if (!pci_enable_msi(adapter->pdev))
448 adapter->msi_enabled = 1;
449 igb_free_all_tx_resources(adapter);
450 igb_free_all_rx_resources(adapter);
451 adapter->num_rx_queues = 1;
452 igb_alloc_queues(adapter);
453 }
454 if (adapter->msi_enabled) {
455 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
456 netdev->name, netdev);
457 if (!err)
458 goto request_done;
459 /* fall back to legacy interrupts */
460 igb_reset_interrupt_capability(adapter);
461 adapter->msi_enabled = 0;
462 }
463
464 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
465 netdev->name, netdev);
466
467 if (err)
468 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
469 err);
470
471 request_done:
472 return err;
473 }
474
475 static void igb_free_irq(struct igb_adapter *adapter)
476 {
477 struct net_device *netdev = adapter->netdev;
478
479 if (adapter->msix_entries) {
480 int vector = 0, i;
481
482 for (i = 0; i < adapter->num_tx_queues; i++)
483 free_irq(adapter->msix_entries[vector++].vector,
484 &(adapter->tx_ring[i]));
485 for (i = 0; i < adapter->num_rx_queues; i++)
486 free_irq(adapter->msix_entries[vector++].vector,
487 &(adapter->rx_ring[i]));
488
489 free_irq(adapter->msix_entries[vector++].vector, netdev);
490 return;
491 }
492
493 free_irq(adapter->pdev->irq, netdev);
494 }
495
496 /**
497 * igb_irq_disable - Mask off interrupt generation on the NIC
498 * @adapter: board private structure
499 **/
500 static void igb_irq_disable(struct igb_adapter *adapter)
501 {
502 struct e1000_hw *hw = &adapter->hw;
503
504 if (adapter->msix_entries) {
505 wr32(E1000_EIMC, ~0);
506 wr32(E1000_EIAC, 0);
507 }
508 wr32(E1000_IMC, ~0);
509 wrfl();
510 synchronize_irq(adapter->pdev->irq);
511 }
512
513 /**
514 * igb_irq_enable - Enable default interrupt generation settings
515 * @adapter: board private structure
516 **/
517 static void igb_irq_enable(struct igb_adapter *adapter)
518 {
519 struct e1000_hw *hw = &adapter->hw;
520
521 if (adapter->msix_entries) {
522 wr32(E1000_EIMS,
523 adapter->eims_enable_mask);
524 wr32(E1000_EIAC,
525 adapter->eims_enable_mask);
526 wr32(E1000_IMS, E1000_IMS_LSC);
527 } else
528 wr32(E1000_IMS, IMS_ENABLE_MASK);
529 }
530
531 static void igb_update_mng_vlan(struct igb_adapter *adapter)
532 {
533 struct net_device *netdev = adapter->netdev;
534 u16 vid = adapter->hw.mng_cookie.vlan_id;
535 u16 old_vid = adapter->mng_vlan_id;
536 if (adapter->vlgrp) {
537 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
538 if (adapter->hw.mng_cookie.status &
539 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
540 igb_vlan_rx_add_vid(netdev, vid);
541 adapter->mng_vlan_id = vid;
542 } else
543 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
544
545 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
546 (vid != old_vid) &&
547 !vlan_group_get_device(adapter->vlgrp, old_vid))
548 igb_vlan_rx_kill_vid(netdev, old_vid);
549 } else
550 adapter->mng_vlan_id = vid;
551 }
552 }
553
554 /**
555 * igb_release_hw_control - release control of the h/w to f/w
556 * @adapter: address of board private structure
557 *
558 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
559 * For ASF and Pass Through versions of f/w this means that the
560 * driver is no longer loaded.
561 *
562 **/
563 static void igb_release_hw_control(struct igb_adapter *adapter)
564 {
565 struct e1000_hw *hw = &adapter->hw;
566 u32 ctrl_ext;
567
568 /* Let firmware take over control of h/w */
569 ctrl_ext = rd32(E1000_CTRL_EXT);
570 wr32(E1000_CTRL_EXT,
571 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
572 }
573
574
575 /**
576 * igb_get_hw_control - get control of the h/w from f/w
577 * @adapter: address of board private structure
578 *
579 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
580 * For ASF and Pass Through versions of f/w this means that
581 * the driver is loaded.
582 *
583 **/
584 static void igb_get_hw_control(struct igb_adapter *adapter)
585 {
586 struct e1000_hw *hw = &adapter->hw;
587 u32 ctrl_ext;
588
589 /* Let firmware know the driver has taken over */
590 ctrl_ext = rd32(E1000_CTRL_EXT);
591 wr32(E1000_CTRL_EXT,
592 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
593 }
594
595 static void igb_init_manageability(struct igb_adapter *adapter)
596 {
597 struct e1000_hw *hw = &adapter->hw;
598
599 if (adapter->en_mng_pt) {
600 u32 manc2h = rd32(E1000_MANC2H);
601 u32 manc = rd32(E1000_MANC);
602
603 /* enable receiving management packets to the host */
604 /* this will probably generate destination unreachable messages
605 * from the host OS, but the packets will be handled on SMBUS */
606 manc |= E1000_MANC_EN_MNG2HOST;
607 #define E1000_MNG2HOST_PORT_623 (1 << 5)
608 #define E1000_MNG2HOST_PORT_664 (1 << 6)
609 manc2h |= E1000_MNG2HOST_PORT_623;
610 manc2h |= E1000_MNG2HOST_PORT_664;
611 wr32(E1000_MANC2H, manc2h);
612
613 wr32(E1000_MANC, manc);
614 }
615 }
616
617 /**
618 * igb_configure - configure the hardware for RX and TX
619 * @adapter: private board structure
620 **/
621 static void igb_configure(struct igb_adapter *adapter)
622 {
623 struct net_device *netdev = adapter->netdev;
624 int i;
625
626 igb_get_hw_control(adapter);
627 igb_set_multi(netdev);
628
629 igb_restore_vlan(adapter);
630 igb_init_manageability(adapter);
631
632 igb_configure_tx(adapter);
633 igb_setup_rctl(adapter);
634 igb_configure_rx(adapter);
635 /* call IGB_DESC_UNUSED which always leaves
636 * at least 1 descriptor unused to make sure
637 * next_to_use != next_to_clean */
638 for (i = 0; i < adapter->num_rx_queues; i++) {
639 struct igb_ring *ring = &adapter->rx_ring[i];
640 igb_alloc_rx_buffers_adv(adapter, ring, IGB_DESC_UNUSED(ring));
641 }
642
643
644 adapter->tx_queue_len = netdev->tx_queue_len;
645 }
646
647
648 /**
649 * igb_up - Open the interface and prepare it to handle traffic
650 * @adapter: board private structure
651 **/
652
653 int igb_up(struct igb_adapter *adapter)
654 {
655 struct e1000_hw *hw = &adapter->hw;
656 int i;
657
658 /* hardware has been reset, we need to reload some things */
659 igb_configure(adapter);
660
661 clear_bit(__IGB_DOWN, &adapter->state);
662
663 napi_enable(&adapter->napi);
664
665 if (adapter->msix_entries) {
666 for (i = 0; i < adapter->num_rx_queues; i++)
667 napi_enable(&adapter->rx_ring[i].napi);
668 igb_configure_msix(adapter);
669 }
670
671 /* Clear any pending interrupts. */
672 rd32(E1000_ICR);
673 igb_irq_enable(adapter);
674
675 /* Fire a link change interrupt to start the watchdog. */
676 wr32(E1000_ICS, E1000_ICS_LSC);
677 return 0;
678 }
679
680 void igb_down(struct igb_adapter *adapter)
681 {
682 struct e1000_hw *hw = &adapter->hw;
683 struct net_device *netdev = adapter->netdev;
684 u32 tctl, rctl;
685 int i;
686
687 /* signal that we're down so the interrupt handler does not
688 * reschedule our watchdog timer */
689 set_bit(__IGB_DOWN, &adapter->state);
690
691 /* disable receives in the hardware */
692 rctl = rd32(E1000_RCTL);
693 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
694 /* flush and sleep below */
695
696 netif_stop_queue(netdev);
697
698 /* disable transmits in the hardware */
699 tctl = rd32(E1000_TCTL);
700 tctl &= ~E1000_TCTL_EN;
701 wr32(E1000_TCTL, tctl);
702 /* flush both disables and wait for them to finish */
703 wrfl();
704 msleep(10);
705
706 napi_disable(&adapter->napi);
707
708 if (adapter->msix_entries)
709 for (i = 0; i < adapter->num_rx_queues; i++)
710 napi_disable(&adapter->rx_ring[i].napi);
711 igb_irq_disable(adapter);
712
713 del_timer_sync(&adapter->watchdog_timer);
714 del_timer_sync(&adapter->phy_info_timer);
715
716 netdev->tx_queue_len = adapter->tx_queue_len;
717 netif_carrier_off(netdev);
718 adapter->link_speed = 0;
719 adapter->link_duplex = 0;
720
721 if (!pci_channel_offline(adapter->pdev))
722 igb_reset(adapter);
723 igb_clean_all_tx_rings(adapter);
724 igb_clean_all_rx_rings(adapter);
725 }
726
727 void igb_reinit_locked(struct igb_adapter *adapter)
728 {
729 WARN_ON(in_interrupt());
730 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
731 msleep(1);
732 igb_down(adapter);
733 igb_up(adapter);
734 clear_bit(__IGB_RESETTING, &adapter->state);
735 }
736
737 void igb_reset(struct igb_adapter *adapter)
738 {
739 struct e1000_hw *hw = &adapter->hw;
740 struct e1000_fc_info *fc = &adapter->hw.fc;
741 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
742 u16 hwm;
743
744 /* Repartition Pba for greater than 9k mtu
745 * To take effect CTRL.RST is required.
746 */
747 pba = E1000_PBA_34K;
748
749 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
750 /* adjust PBA for jumbo frames */
751 wr32(E1000_PBA, pba);
752
753 /* To maintain wire speed transmits, the Tx FIFO should be
754 * large enough to accommodate two full transmit packets,
755 * rounded up to the next 1KB and expressed in KB. Likewise,
756 * the Rx FIFO should be large enough to accommodate at least
757 * one full receive packet and is similarly rounded up and
758 * expressed in KB. */
759 pba = rd32(E1000_PBA);
760 /* upper 16 bits has Tx packet buffer allocation size in KB */
761 tx_space = pba >> 16;
762 /* lower 16 bits has Rx packet buffer allocation size in KB */
763 pba &= 0xffff;
764 /* the tx fifo also stores 16 bytes of information about the tx
765 * but don't include ethernet FCS because hardware appends it */
766 min_tx_space = (adapter->max_frame_size +
767 sizeof(struct e1000_tx_desc) -
768 ETH_FCS_LEN) * 2;
769 min_tx_space = ALIGN(min_tx_space, 1024);
770 min_tx_space >>= 10;
771 /* software strips receive CRC, so leave room for it */
772 min_rx_space = adapter->max_frame_size;
773 min_rx_space = ALIGN(min_rx_space, 1024);
774 min_rx_space >>= 10;
775
776 /* If current Tx allocation is less than the min Tx FIFO size,
777 * and the min Tx FIFO size is less than the current Rx FIFO
778 * allocation, take space away from current Rx allocation */
779 if (tx_space < min_tx_space &&
780 ((min_tx_space - tx_space) < pba)) {
781 pba = pba - (min_tx_space - tx_space);
782
783 /* if short on rx space, rx wins and must trump tx
784 * adjustment */
785 if (pba < min_rx_space)
786 pba = min_rx_space;
787 }
788 }
789 wr32(E1000_PBA, pba);
790
791 /* flow control settings */
792 /* The high water mark must be low enough to fit one full frame
793 * (or the size used for early receive) above it in the Rx FIFO.
794 * Set it to the lower of:
795 * - 90% of the Rx FIFO size, or
796 * - the full Rx FIFO size minus one full frame */
797 hwm = min(((pba << 10) * 9 / 10),
798 ((pba << 10) - adapter->max_frame_size));
799
800 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
801 fc->low_water = fc->high_water - 8;
802 fc->pause_time = 0xFFFF;
803 fc->send_xon = 1;
804 fc->type = fc->original_type;
805
806 /* Allow time for pending master requests to run */
807 adapter->hw.mac.ops.reset_hw(&adapter->hw);
808 wr32(E1000_WUC, 0);
809
810 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
811 dev_err(&adapter->pdev->dev, "Hardware Error\n");
812
813 igb_update_mng_vlan(adapter);
814
815 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
816 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
817
818 igb_reset_adaptive(&adapter->hw);
819 if (adapter->hw.phy.ops.get_phy_info)
820 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
821 }
822
823 /**
824 * igb_probe - Device Initialization Routine
825 * @pdev: PCI device information struct
826 * @ent: entry in igb_pci_tbl
827 *
828 * Returns 0 on success, negative on failure
829 *
830 * igb_probe initializes an adapter identified by a pci_dev structure.
831 * The OS initialization, configuring of the adapter private structure,
832 * and a hardware reset occur.
833 **/
834 static int __devinit igb_probe(struct pci_dev *pdev,
835 const struct pci_device_id *ent)
836 {
837 struct net_device *netdev;
838 struct igb_adapter *adapter;
839 struct e1000_hw *hw;
840 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
841 unsigned long mmio_start, mmio_len;
842 static int cards_found;
843 int i, err, pci_using_dac;
844 u16 eeprom_data = 0;
845 u16 eeprom_apme_mask = IGB_EEPROM_APME;
846 u32 part_num;
847
848 err = pci_enable_device(pdev);
849 if (err)
850 return err;
851
852 pci_using_dac = 0;
853 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
854 if (!err) {
855 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
856 if (!err)
857 pci_using_dac = 1;
858 } else {
859 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
860 if (err) {
861 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
862 if (err) {
863 dev_err(&pdev->dev, "No usable DMA "
864 "configuration, aborting\n");
865 goto err_dma;
866 }
867 }
868 }
869
870 err = pci_request_regions(pdev, igb_driver_name);
871 if (err)
872 goto err_pci_reg;
873
874 pci_set_master(pdev);
875 pci_save_state(pdev);
876
877 err = -ENOMEM;
878 netdev = alloc_etherdev(sizeof(struct igb_adapter));
879 if (!netdev)
880 goto err_alloc_etherdev;
881
882 SET_NETDEV_DEV(netdev, &pdev->dev);
883
884 pci_set_drvdata(pdev, netdev);
885 adapter = netdev_priv(netdev);
886 adapter->netdev = netdev;
887 adapter->pdev = pdev;
888 hw = &adapter->hw;
889 hw->back = adapter;
890 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
891
892 mmio_start = pci_resource_start(pdev, 0);
893 mmio_len = pci_resource_len(pdev, 0);
894
895 err = -EIO;
896 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
897 if (!adapter->hw.hw_addr)
898 goto err_ioremap;
899
900 netdev->open = &igb_open;
901 netdev->stop = &igb_close;
902 netdev->get_stats = &igb_get_stats;
903 netdev->set_multicast_list = &igb_set_multi;
904 netdev->set_mac_address = &igb_set_mac;
905 netdev->change_mtu = &igb_change_mtu;
906 netdev->do_ioctl = &igb_ioctl;
907 igb_set_ethtool_ops(netdev);
908 netdev->tx_timeout = &igb_tx_timeout;
909 netdev->watchdog_timeo = 5 * HZ;
910 netif_napi_add(netdev, &adapter->napi, igb_clean, 64);
911 netdev->vlan_rx_register = igb_vlan_rx_register;
912 netdev->vlan_rx_add_vid = igb_vlan_rx_add_vid;
913 netdev->vlan_rx_kill_vid = igb_vlan_rx_kill_vid;
914 #ifdef CONFIG_NET_POLL_CONTROLLER
915 netdev->poll_controller = igb_netpoll;
916 #endif
917 netdev->hard_start_xmit = &igb_xmit_frame_adv;
918
919 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
920
921 netdev->mem_start = mmio_start;
922 netdev->mem_end = mmio_start + mmio_len;
923
924 adapter->bd_number = cards_found;
925
926 /* PCI config space info */
927 hw->vendor_id = pdev->vendor;
928 hw->device_id = pdev->device;
929 hw->revision_id = pdev->revision;
930 hw->subsystem_vendor_id = pdev->subsystem_vendor;
931 hw->subsystem_device_id = pdev->subsystem_device;
932
933 /* setup the private structure */
934 hw->back = adapter;
935 /* Copy the default MAC, PHY and NVM function pointers */
936 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
937 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
938 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
939 /* Initialize skew-specific constants */
940 err = ei->get_invariants(hw);
941 if (err)
942 goto err_hw_init;
943
944 err = igb_sw_init(adapter);
945 if (err)
946 goto err_sw_init;
947
948 igb_get_bus_info_pcie(hw);
949
950 hw->phy.autoneg_wait_to_complete = false;
951 hw->mac.adaptive_ifs = true;
952
953 /* Copper options */
954 if (hw->phy.media_type == e1000_media_type_copper) {
955 hw->phy.mdix = AUTO_ALL_MODES;
956 hw->phy.disable_polarity_correction = false;
957 hw->phy.ms_type = e1000_ms_hw_default;
958 }
959
960 if (igb_check_reset_block(hw))
961 dev_info(&pdev->dev,
962 "PHY reset is blocked due to SOL/IDER session.\n");
963
964 netdev->features = NETIF_F_SG |
965 NETIF_F_HW_CSUM |
966 NETIF_F_HW_VLAN_TX |
967 NETIF_F_HW_VLAN_RX |
968 NETIF_F_HW_VLAN_FILTER;
969
970 netdev->features |= NETIF_F_TSO;
971 netdev->features |= NETIF_F_TSO6;
972
973 netdev->vlan_features |= NETIF_F_TSO;
974 netdev->vlan_features |= NETIF_F_TSO6;
975 netdev->vlan_features |= NETIF_F_HW_CSUM;
976 netdev->vlan_features |= NETIF_F_SG;
977
978 if (pci_using_dac)
979 netdev->features |= NETIF_F_HIGHDMA;
980
981 netdev->features |= NETIF_F_LLTX;
982 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
983
984 /* before reading the NVM, reset the controller to put the device in a
985 * known good starting state */
986 hw->mac.ops.reset_hw(hw);
987
988 /* make sure the NVM is good */
989 if (igb_validate_nvm_checksum(hw) < 0) {
990 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
991 err = -EIO;
992 goto err_eeprom;
993 }
994
995 /* copy the MAC address out of the NVM */
996 if (hw->mac.ops.read_mac_addr(hw))
997 dev_err(&pdev->dev, "NVM Read Error\n");
998
999 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1000 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1001
1002 if (!is_valid_ether_addr(netdev->perm_addr)) {
1003 dev_err(&pdev->dev, "Invalid MAC Address\n");
1004 err = -EIO;
1005 goto err_eeprom;
1006 }
1007
1008 init_timer(&adapter->watchdog_timer);
1009 adapter->watchdog_timer.function = &igb_watchdog;
1010 adapter->watchdog_timer.data = (unsigned long) adapter;
1011
1012 init_timer(&adapter->phy_info_timer);
1013 adapter->phy_info_timer.function = &igb_update_phy_info;
1014 adapter->phy_info_timer.data = (unsigned long) adapter;
1015
1016 INIT_WORK(&adapter->reset_task, igb_reset_task);
1017 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1018
1019 /* Initialize link & ring properties that are user-changeable */
1020 adapter->tx_ring->count = 256;
1021 for (i = 0; i < adapter->num_tx_queues; i++)
1022 adapter->tx_ring[i].count = adapter->tx_ring->count;
1023 adapter->rx_ring->count = 256;
1024 for (i = 0; i < adapter->num_rx_queues; i++)
1025 adapter->rx_ring[i].count = adapter->rx_ring->count;
1026
1027 adapter->fc_autoneg = true;
1028 hw->mac.autoneg = true;
1029 hw->phy.autoneg_advertised = 0x2f;
1030
1031 hw->fc.original_type = e1000_fc_default;
1032 hw->fc.type = e1000_fc_default;
1033
1034 adapter->itr_setting = 3;
1035 adapter->itr = IGB_START_ITR;
1036
1037 igb_validate_mdi_setting(hw);
1038
1039 adapter->rx_csum = 1;
1040
1041 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1042 * enable the ACPI Magic Packet filter
1043 */
1044
1045 if (hw->bus.func == 0 ||
1046 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
1047 hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL3_PORT_A, 1,
1048 &eeprom_data);
1049
1050 if (eeprom_data & eeprom_apme_mask)
1051 adapter->eeprom_wol |= E1000_WUFC_MAG;
1052
1053 /* now that we have the eeprom settings, apply the special cases where
1054 * the eeprom may be wrong or the board simply won't support wake on
1055 * lan on a particular port */
1056 switch (pdev->device) {
1057 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1058 adapter->eeprom_wol = 0;
1059 break;
1060 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1061 /* Wake events only supported on port A for dual fiber
1062 * regardless of eeprom setting */
1063 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1064 adapter->eeprom_wol = 0;
1065 break;
1066 }
1067
1068 /* initialize the wol settings based on the eeprom settings */
1069 adapter->wol = adapter->eeprom_wol;
1070
1071 /* reset the hardware with the new settings */
1072 igb_reset(adapter);
1073
1074 /* let the f/w know that the h/w is now under the control of the
1075 * driver. */
1076 igb_get_hw_control(adapter);
1077
1078 /* tell the stack to leave us alone until igb_open() is called */
1079 netif_carrier_off(netdev);
1080 netif_stop_queue(netdev);
1081
1082 strcpy(netdev->name, "eth%d");
1083 err = register_netdev(netdev);
1084 if (err)
1085 goto err_register;
1086
1087 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1088 /* print bus type/speed/width info */
1089 dev_info(&pdev->dev,
1090 "%s: (PCIe:%s:%s) %02x:%02x:%02x:%02x:%02x:%02x\n",
1091 netdev->name,
1092 ((hw->bus.speed == e1000_bus_speed_2500)
1093 ? "2.5Gb/s" : "unknown"),
1094 ((hw->bus.width == e1000_bus_width_pcie_x4)
1095 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1096 ? "Width x1" : "unknown"),
1097 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
1098 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
1099
1100 igb_read_part_num(hw, &part_num);
1101 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1102 (part_num >> 8), (part_num & 0xff));
1103
1104 dev_info(&pdev->dev,
1105 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1106 adapter->msix_entries ? "MSI-X" :
1107 adapter->msi_enabled ? "MSI" : "legacy",
1108 adapter->num_rx_queues, adapter->num_tx_queues);
1109
1110 cards_found++;
1111 return 0;
1112
1113 err_register:
1114 igb_release_hw_control(adapter);
1115 err_eeprom:
1116 if (!igb_check_reset_block(hw))
1117 hw->phy.ops.reset_phy(hw);
1118
1119 if (hw->flash_address)
1120 iounmap(hw->flash_address);
1121
1122 igb_remove_device(hw);
1123 kfree(adapter->tx_ring);
1124 kfree(adapter->rx_ring);
1125 err_sw_init:
1126 err_hw_init:
1127 iounmap(hw->hw_addr);
1128 err_ioremap:
1129 free_netdev(netdev);
1130 err_alloc_etherdev:
1131 pci_release_regions(pdev);
1132 err_pci_reg:
1133 err_dma:
1134 pci_disable_device(pdev);
1135 return err;
1136 }
1137
1138 /**
1139 * igb_remove - Device Removal Routine
1140 * @pdev: PCI device information struct
1141 *
1142 * igb_remove is called by the PCI subsystem to alert the driver
1143 * that it should release a PCI device. The could be caused by a
1144 * Hot-Plug event, or because the driver is going to be removed from
1145 * memory.
1146 **/
1147 static void __devexit igb_remove(struct pci_dev *pdev)
1148 {
1149 struct net_device *netdev = pci_get_drvdata(pdev);
1150 struct igb_adapter *adapter = netdev_priv(netdev);
1151
1152 /* flush_scheduled work may reschedule our watchdog task, so
1153 * explicitly disable watchdog tasks from being rescheduled */
1154 set_bit(__IGB_DOWN, &adapter->state);
1155 del_timer_sync(&adapter->watchdog_timer);
1156 del_timer_sync(&adapter->phy_info_timer);
1157
1158 flush_scheduled_work();
1159
1160 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1161 * would have already happened in close and is redundant. */
1162 igb_release_hw_control(adapter);
1163
1164 unregister_netdev(netdev);
1165
1166 if (!igb_check_reset_block(&adapter->hw))
1167 adapter->hw.phy.ops.reset_phy(&adapter->hw);
1168
1169 igb_remove_device(&adapter->hw);
1170 igb_reset_interrupt_capability(adapter);
1171
1172 kfree(adapter->tx_ring);
1173 kfree(adapter->rx_ring);
1174
1175 iounmap(adapter->hw.hw_addr);
1176 if (adapter->hw.flash_address)
1177 iounmap(adapter->hw.flash_address);
1178 pci_release_regions(pdev);
1179
1180 free_netdev(netdev);
1181
1182 pci_disable_device(pdev);
1183 }
1184
1185 /**
1186 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1187 * @adapter: board private structure to initialize
1188 *
1189 * igb_sw_init initializes the Adapter private data structure.
1190 * Fields are initialized based on PCI device information and
1191 * OS network device settings (MTU size).
1192 **/
1193 static int __devinit igb_sw_init(struct igb_adapter *adapter)
1194 {
1195 struct e1000_hw *hw = &adapter->hw;
1196 struct net_device *netdev = adapter->netdev;
1197 struct pci_dev *pdev = adapter->pdev;
1198
1199 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1200
1201 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1202 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1203 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1204 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1205
1206 /* Number of supported queues. */
1207 /* Having more queues than CPUs doesn't make sense. */
1208 adapter->num_tx_queues = 1;
1209 adapter->num_rx_queues = min(IGB_MAX_RX_QUEUES, num_online_cpus());
1210
1211 igb_set_interrupt_capability(adapter);
1212
1213 if (igb_alloc_queues(adapter)) {
1214 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1215 return -ENOMEM;
1216 }
1217
1218 /* Explicitly disable IRQ since the NIC can be in any state. */
1219 igb_irq_disable(adapter);
1220
1221 set_bit(__IGB_DOWN, &adapter->state);
1222 return 0;
1223 }
1224
1225 /**
1226 * igb_open - Called when a network interface is made active
1227 * @netdev: network interface device structure
1228 *
1229 * Returns 0 on success, negative value on failure
1230 *
1231 * The open entry point is called when a network interface is made
1232 * active by the system (IFF_UP). At this point all resources needed
1233 * for transmit and receive operations are allocated, the interrupt
1234 * handler is registered with the OS, the watchdog timer is started,
1235 * and the stack is notified that the interface is ready.
1236 **/
1237 static int igb_open(struct net_device *netdev)
1238 {
1239 struct igb_adapter *adapter = netdev_priv(netdev);
1240 struct e1000_hw *hw = &adapter->hw;
1241 int err;
1242 int i;
1243
1244 /* disallow open during test */
1245 if (test_bit(__IGB_TESTING, &adapter->state))
1246 return -EBUSY;
1247
1248 /* allocate transmit descriptors */
1249 err = igb_setup_all_tx_resources(adapter);
1250 if (err)
1251 goto err_setup_tx;
1252
1253 /* allocate receive descriptors */
1254 err = igb_setup_all_rx_resources(adapter);
1255 if (err)
1256 goto err_setup_rx;
1257
1258 /* e1000_power_up_phy(adapter); */
1259
1260 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1261 if ((adapter->hw.mng_cookie.status &
1262 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1263 igb_update_mng_vlan(adapter);
1264
1265 /* before we allocate an interrupt, we must be ready to handle it.
1266 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1267 * as soon as we call pci_request_irq, so we have to setup our
1268 * clean_rx handler before we do so. */
1269 igb_configure(adapter);
1270
1271 err = igb_request_irq(adapter);
1272 if (err)
1273 goto err_req_irq;
1274
1275 /* From here on the code is the same as igb_up() */
1276 clear_bit(__IGB_DOWN, &adapter->state);
1277
1278 napi_enable(&adapter->napi);
1279 if (adapter->msix_entries)
1280 for (i = 0; i < adapter->num_rx_queues; i++)
1281 napi_enable(&adapter->rx_ring[i].napi);
1282
1283 igb_irq_enable(adapter);
1284
1285 /* Clear any pending interrupts. */
1286 rd32(E1000_ICR);
1287 /* Fire a link status change interrupt to start the watchdog. */
1288 wr32(E1000_ICS, E1000_ICS_LSC);
1289
1290 return 0;
1291
1292 err_req_irq:
1293 igb_release_hw_control(adapter);
1294 /* e1000_power_down_phy(adapter); */
1295 igb_free_all_rx_resources(adapter);
1296 err_setup_rx:
1297 igb_free_all_tx_resources(adapter);
1298 err_setup_tx:
1299 igb_reset(adapter);
1300
1301 return err;
1302 }
1303
1304 /**
1305 * igb_close - Disables a network interface
1306 * @netdev: network interface device structure
1307 *
1308 * Returns 0, this is not allowed to fail
1309 *
1310 * The close entry point is called when an interface is de-activated
1311 * by the OS. The hardware is still under the driver's control, but
1312 * needs to be disabled. A global MAC reset is issued to stop the
1313 * hardware, and all transmit and receive resources are freed.
1314 **/
1315 static int igb_close(struct net_device *netdev)
1316 {
1317 struct igb_adapter *adapter = netdev_priv(netdev);
1318
1319 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1320 igb_down(adapter);
1321
1322 igb_free_irq(adapter);
1323
1324 igb_free_all_tx_resources(adapter);
1325 igb_free_all_rx_resources(adapter);
1326
1327 /* kill manageability vlan ID if supported, but not if a vlan with
1328 * the same ID is registered on the host OS (let 8021q kill it) */
1329 if ((adapter->hw.mng_cookie.status &
1330 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1331 !(adapter->vlgrp &&
1332 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1333 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1334
1335 return 0;
1336 }
1337
1338 /**
1339 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1340 * @adapter: board private structure
1341 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1342 *
1343 * Return 0 on success, negative on failure
1344 **/
1345
1346 int igb_setup_tx_resources(struct igb_adapter *adapter,
1347 struct igb_ring *tx_ring)
1348 {
1349 struct pci_dev *pdev = adapter->pdev;
1350 int size;
1351
1352 size = sizeof(struct igb_buffer) * tx_ring->count;
1353 tx_ring->buffer_info = vmalloc(size);
1354 if (!tx_ring->buffer_info)
1355 goto err;
1356 memset(tx_ring->buffer_info, 0, size);
1357
1358 /* round up to nearest 4K */
1359 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc)
1360 + sizeof(u32);
1361 tx_ring->size = ALIGN(tx_ring->size, 4096);
1362
1363 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1364 &tx_ring->dma);
1365
1366 if (!tx_ring->desc)
1367 goto err;
1368
1369 tx_ring->adapter = adapter;
1370 tx_ring->next_to_use = 0;
1371 tx_ring->next_to_clean = 0;
1372 spin_lock_init(&tx_ring->tx_clean_lock);
1373 spin_lock_init(&tx_ring->tx_lock);
1374 return 0;
1375
1376 err:
1377 vfree(tx_ring->buffer_info);
1378 dev_err(&adapter->pdev->dev,
1379 "Unable to allocate memory for the transmit descriptor ring\n");
1380 return -ENOMEM;
1381 }
1382
1383 /**
1384 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1385 * (Descriptors) for all queues
1386 * @adapter: board private structure
1387 *
1388 * Return 0 on success, negative on failure
1389 **/
1390 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1391 {
1392 int i, err = 0;
1393
1394 for (i = 0; i < adapter->num_tx_queues; i++) {
1395 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1396 if (err) {
1397 dev_err(&adapter->pdev->dev,
1398 "Allocation for Tx Queue %u failed\n", i);
1399 for (i--; i >= 0; i--)
1400 igb_free_tx_resources(adapter,
1401 &adapter->tx_ring[i]);
1402 break;
1403 }
1404 }
1405
1406 return err;
1407 }
1408
1409 /**
1410 * igb_configure_tx - Configure transmit Unit after Reset
1411 * @adapter: board private structure
1412 *
1413 * Configure the Tx unit of the MAC after a reset.
1414 **/
1415 static void igb_configure_tx(struct igb_adapter *adapter)
1416 {
1417 u64 tdba, tdwba;
1418 struct e1000_hw *hw = &adapter->hw;
1419 u32 tctl;
1420 u32 txdctl, txctrl;
1421 int i;
1422
1423 for (i = 0; i < adapter->num_tx_queues; i++) {
1424 struct igb_ring *ring = &(adapter->tx_ring[i]);
1425
1426 wr32(E1000_TDLEN(i),
1427 ring->count * sizeof(struct e1000_tx_desc));
1428 tdba = ring->dma;
1429 wr32(E1000_TDBAL(i),
1430 tdba & 0x00000000ffffffffULL);
1431 wr32(E1000_TDBAH(i), tdba >> 32);
1432
1433 tdwba = ring->dma + ring->count * sizeof(struct e1000_tx_desc);
1434 tdwba |= 1; /* enable head wb */
1435 wr32(E1000_TDWBAL(i),
1436 tdwba & 0x00000000ffffffffULL);
1437 wr32(E1000_TDWBAH(i), tdwba >> 32);
1438
1439 ring->head = E1000_TDH(i);
1440 ring->tail = E1000_TDT(i);
1441 writel(0, hw->hw_addr + ring->tail);
1442 writel(0, hw->hw_addr + ring->head);
1443 txdctl = rd32(E1000_TXDCTL(i));
1444 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1445 wr32(E1000_TXDCTL(i), txdctl);
1446
1447 /* Turn off Relaxed Ordering on head write-backs. The
1448 * writebacks MUST be delivered in order or it will
1449 * completely screw up our bookeeping.
1450 */
1451 txctrl = rd32(E1000_DCA_TXCTRL(i));
1452 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1453 wr32(E1000_DCA_TXCTRL(i), txctrl);
1454 }
1455
1456
1457
1458 /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1459
1460 /* Program the Transmit Control Register */
1461
1462 tctl = rd32(E1000_TCTL);
1463 tctl &= ~E1000_TCTL_CT;
1464 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1465 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1466
1467 igb_config_collision_dist(hw);
1468
1469 /* Setup Transmit Descriptor Settings for eop descriptor */
1470 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1471
1472 /* Enable transmits */
1473 tctl |= E1000_TCTL_EN;
1474
1475 wr32(E1000_TCTL, tctl);
1476 }
1477
1478 /**
1479 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1480 * @adapter: board private structure
1481 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1482 *
1483 * Returns 0 on success, negative on failure
1484 **/
1485
1486 int igb_setup_rx_resources(struct igb_adapter *adapter,
1487 struct igb_ring *rx_ring)
1488 {
1489 struct pci_dev *pdev = adapter->pdev;
1490 int size, desc_len;
1491
1492 size = sizeof(struct igb_buffer) * rx_ring->count;
1493 rx_ring->buffer_info = vmalloc(size);
1494 if (!rx_ring->buffer_info)
1495 goto err;
1496 memset(rx_ring->buffer_info, 0, size);
1497
1498 desc_len = sizeof(union e1000_adv_rx_desc);
1499
1500 /* Round up to nearest 4K */
1501 rx_ring->size = rx_ring->count * desc_len;
1502 rx_ring->size = ALIGN(rx_ring->size, 4096);
1503
1504 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1505 &rx_ring->dma);
1506
1507 if (!rx_ring->desc)
1508 goto err;
1509
1510 rx_ring->next_to_clean = 0;
1511 rx_ring->next_to_use = 0;
1512 rx_ring->pending_skb = NULL;
1513
1514 rx_ring->adapter = adapter;
1515 /* FIXME: do we want to setup ring->napi->poll here? */
1516 rx_ring->napi.poll = adapter->napi.poll;
1517
1518 return 0;
1519
1520 err:
1521 vfree(rx_ring->buffer_info);
1522 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1523 "the receive descriptor ring\n");
1524 return -ENOMEM;
1525 }
1526
1527 /**
1528 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1529 * (Descriptors) for all queues
1530 * @adapter: board private structure
1531 *
1532 * Return 0 on success, negative on failure
1533 **/
1534 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1535 {
1536 int i, err = 0;
1537
1538 for (i = 0; i < adapter->num_rx_queues; i++) {
1539 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1540 if (err) {
1541 dev_err(&adapter->pdev->dev,
1542 "Allocation for Rx Queue %u failed\n", i);
1543 for (i--; i >= 0; i--)
1544 igb_free_rx_resources(adapter,
1545 &adapter->rx_ring[i]);
1546 break;
1547 }
1548 }
1549
1550 return err;
1551 }
1552
1553 /**
1554 * igb_setup_rctl - configure the receive control registers
1555 * @adapter: Board private structure
1556 **/
1557 static void igb_setup_rctl(struct igb_adapter *adapter)
1558 {
1559 struct e1000_hw *hw = &adapter->hw;
1560 u32 rctl;
1561 u32 srrctl = 0;
1562 int i;
1563
1564 rctl = rd32(E1000_RCTL);
1565
1566 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1567
1568 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1569 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1570 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1571
1572 /* disable the stripping of CRC because it breaks
1573 * BMC firmware connected over SMBUS
1574 rctl |= E1000_RCTL_SECRC;
1575 */
1576
1577 rctl &= ~E1000_RCTL_SBP;
1578
1579 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1580 rctl &= ~E1000_RCTL_LPE;
1581 else
1582 rctl |= E1000_RCTL_LPE;
1583 if (adapter->rx_buffer_len <= IGB_RXBUFFER_2048) {
1584 /* Setup buffer sizes */
1585 rctl &= ~E1000_RCTL_SZ_4096;
1586 rctl |= E1000_RCTL_BSEX;
1587 switch (adapter->rx_buffer_len) {
1588 case IGB_RXBUFFER_256:
1589 rctl |= E1000_RCTL_SZ_256;
1590 rctl &= ~E1000_RCTL_BSEX;
1591 break;
1592 case IGB_RXBUFFER_512:
1593 rctl |= E1000_RCTL_SZ_512;
1594 rctl &= ~E1000_RCTL_BSEX;
1595 break;
1596 case IGB_RXBUFFER_1024:
1597 rctl |= E1000_RCTL_SZ_1024;
1598 rctl &= ~E1000_RCTL_BSEX;
1599 break;
1600 case IGB_RXBUFFER_2048:
1601 default:
1602 rctl |= E1000_RCTL_SZ_2048;
1603 rctl &= ~E1000_RCTL_BSEX;
1604 break;
1605 case IGB_RXBUFFER_4096:
1606 rctl |= E1000_RCTL_SZ_4096;
1607 break;
1608 case IGB_RXBUFFER_8192:
1609 rctl |= E1000_RCTL_SZ_8192;
1610 break;
1611 case IGB_RXBUFFER_16384:
1612 rctl |= E1000_RCTL_SZ_16384;
1613 break;
1614 }
1615 } else {
1616 rctl &= ~E1000_RCTL_BSEX;
1617 srrctl = adapter->rx_buffer_len >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1618 }
1619
1620 /* 82575 and greater support packet-split where the protocol
1621 * header is placed in skb->data and the packet data is
1622 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1623 * In the case of a non-split, skb->data is linearly filled,
1624 * followed by the page buffers. Therefore, skb->data is
1625 * sized to hold the largest protocol header.
1626 */
1627 /* allocations using alloc_page take too long for regular MTU
1628 * so only enable packet split for jumbo frames */
1629 if (rctl & E1000_RCTL_LPE) {
1630 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
1631 srrctl = adapter->rx_ps_hdr_size <<
1632 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
1633 /* buffer size is ALWAYS one page */
1634 srrctl |= PAGE_SIZE >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1635 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1636 } else {
1637 adapter->rx_ps_hdr_size = 0;
1638 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1639 }
1640
1641 for (i = 0; i < adapter->num_rx_queues; i++)
1642 wr32(E1000_SRRCTL(i), srrctl);
1643
1644 wr32(E1000_RCTL, rctl);
1645 }
1646
1647 /**
1648 * igb_configure_rx - Configure receive Unit after Reset
1649 * @adapter: board private structure
1650 *
1651 * Configure the Rx unit of the MAC after a reset.
1652 **/
1653 static void igb_configure_rx(struct igb_adapter *adapter)
1654 {
1655 u64 rdba;
1656 struct e1000_hw *hw = &adapter->hw;
1657 u32 rctl, rxcsum;
1658 u32 rxdctl;
1659 int i;
1660
1661 /* disable receives while setting up the descriptors */
1662 rctl = rd32(E1000_RCTL);
1663 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1664 wrfl();
1665 mdelay(10);
1666
1667 if (adapter->itr_setting > 3)
1668 wr32(E1000_ITR,
1669 1000000000 / (adapter->itr * 256));
1670
1671 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1672 * the Base and Length of the Rx Descriptor Ring */
1673 for (i = 0; i < adapter->num_rx_queues; i++) {
1674 struct igb_ring *ring = &(adapter->rx_ring[i]);
1675 rdba = ring->dma;
1676 wr32(E1000_RDBAL(i),
1677 rdba & 0x00000000ffffffffULL);
1678 wr32(E1000_RDBAH(i), rdba >> 32);
1679 wr32(E1000_RDLEN(i),
1680 ring->count * sizeof(union e1000_adv_rx_desc));
1681
1682 ring->head = E1000_RDH(i);
1683 ring->tail = E1000_RDT(i);
1684 writel(0, hw->hw_addr + ring->tail);
1685 writel(0, hw->hw_addr + ring->head);
1686
1687 rxdctl = rd32(E1000_RXDCTL(i));
1688 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1689 rxdctl &= 0xFFF00000;
1690 rxdctl |= IGB_RX_PTHRESH;
1691 rxdctl |= IGB_RX_HTHRESH << 8;
1692 rxdctl |= IGB_RX_WTHRESH << 16;
1693 wr32(E1000_RXDCTL(i), rxdctl);
1694 }
1695
1696 if (adapter->num_rx_queues > 1) {
1697 u32 random[10];
1698 u32 mrqc;
1699 u32 j, shift;
1700 union e1000_reta {
1701 u32 dword;
1702 u8 bytes[4];
1703 } reta;
1704
1705 get_random_bytes(&random[0], 40);
1706
1707 shift = 6;
1708 for (j = 0; j < (32 * 4); j++) {
1709 reta.bytes[j & 3] =
1710 (j % adapter->num_rx_queues) << shift;
1711 if ((j & 3) == 3)
1712 writel(reta.dword,
1713 hw->hw_addr + E1000_RETA(0) + (j & ~3));
1714 }
1715 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
1716
1717 /* Fill out hash function seeds */
1718 for (j = 0; j < 10; j++)
1719 array_wr32(E1000_RSSRK(0), j, random[j]);
1720
1721 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1722 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1723 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
1724 E1000_MRQC_RSS_FIELD_IPV6_TCP);
1725 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
1726 E1000_MRQC_RSS_FIELD_IPV6_UDP);
1727 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
1728 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
1729
1730
1731 wr32(E1000_MRQC, mrqc);
1732
1733 /* Multiqueue and raw packet checksumming are mutually
1734 * exclusive. Note that this not the same as TCP/IP
1735 * checksumming, which works fine. */
1736 rxcsum = rd32(E1000_RXCSUM);
1737 rxcsum |= E1000_RXCSUM_PCSD;
1738 wr32(E1000_RXCSUM, rxcsum);
1739 } else {
1740 /* Enable Receive Checksum Offload for TCP and UDP */
1741 rxcsum = rd32(E1000_RXCSUM);
1742 if (adapter->rx_csum) {
1743 rxcsum |= E1000_RXCSUM_TUOFL;
1744
1745 /* Enable IPv4 payload checksum for UDP fragments
1746 * Must be used in conjunction with packet-split. */
1747 if (adapter->rx_ps_hdr_size)
1748 rxcsum |= E1000_RXCSUM_IPPCSE;
1749 } else {
1750 rxcsum &= ~E1000_RXCSUM_TUOFL;
1751 /* don't need to clear IPPCSE as it defaults to 0 */
1752 }
1753 wr32(E1000_RXCSUM, rxcsum);
1754 }
1755
1756 if (adapter->vlgrp)
1757 wr32(E1000_RLPML,
1758 adapter->max_frame_size + VLAN_TAG_SIZE);
1759 else
1760 wr32(E1000_RLPML, adapter->max_frame_size);
1761
1762 /* Enable Receives */
1763 wr32(E1000_RCTL, rctl);
1764 }
1765
1766 /**
1767 * igb_free_tx_resources - Free Tx Resources per Queue
1768 * @adapter: board private structure
1769 * @tx_ring: Tx descriptor ring for a specific queue
1770 *
1771 * Free all transmit software resources
1772 **/
1773 static void igb_free_tx_resources(struct igb_adapter *adapter,
1774 struct igb_ring *tx_ring)
1775 {
1776 struct pci_dev *pdev = adapter->pdev;
1777
1778 igb_clean_tx_ring(adapter, tx_ring);
1779
1780 vfree(tx_ring->buffer_info);
1781 tx_ring->buffer_info = NULL;
1782
1783 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1784
1785 tx_ring->desc = NULL;
1786 }
1787
1788 /**
1789 * igb_free_all_tx_resources - Free Tx Resources for All Queues
1790 * @adapter: board private structure
1791 *
1792 * Free all transmit software resources
1793 **/
1794 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
1795 {
1796 int i;
1797
1798 for (i = 0; i < adapter->num_tx_queues; i++)
1799 igb_free_tx_resources(adapter, &adapter->tx_ring[i]);
1800 }
1801
1802 static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
1803 struct igb_buffer *buffer_info)
1804 {
1805 if (buffer_info->dma) {
1806 pci_unmap_page(adapter->pdev,
1807 buffer_info->dma,
1808 buffer_info->length,
1809 PCI_DMA_TODEVICE);
1810 buffer_info->dma = 0;
1811 }
1812 if (buffer_info->skb) {
1813 dev_kfree_skb_any(buffer_info->skb);
1814 buffer_info->skb = NULL;
1815 }
1816 buffer_info->time_stamp = 0;
1817 /* buffer_info must be completely set up in the transmit path */
1818 }
1819
1820 /**
1821 * igb_clean_tx_ring - Free Tx Buffers
1822 * @adapter: board private structure
1823 * @tx_ring: ring to be cleaned
1824 **/
1825 static void igb_clean_tx_ring(struct igb_adapter *adapter,
1826 struct igb_ring *tx_ring)
1827 {
1828 struct igb_buffer *buffer_info;
1829 unsigned long size;
1830 unsigned int i;
1831
1832 if (!tx_ring->buffer_info)
1833 return;
1834 /* Free all the Tx ring sk_buffs */
1835
1836 for (i = 0; i < tx_ring->count; i++) {
1837 buffer_info = &tx_ring->buffer_info[i];
1838 igb_unmap_and_free_tx_resource(adapter, buffer_info);
1839 }
1840
1841 size = sizeof(struct igb_buffer) * tx_ring->count;
1842 memset(tx_ring->buffer_info, 0, size);
1843
1844 /* Zero out the descriptor ring */
1845
1846 memset(tx_ring->desc, 0, tx_ring->size);
1847
1848 tx_ring->next_to_use = 0;
1849 tx_ring->next_to_clean = 0;
1850
1851 writel(0, adapter->hw.hw_addr + tx_ring->head);
1852 writel(0, adapter->hw.hw_addr + tx_ring->tail);
1853 }
1854
1855 /**
1856 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
1857 * @adapter: board private structure
1858 **/
1859 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
1860 {
1861 int i;
1862
1863 for (i = 0; i < adapter->num_tx_queues; i++)
1864 igb_clean_tx_ring(adapter, &adapter->tx_ring[i]);
1865 }
1866
1867 /**
1868 * igb_free_rx_resources - Free Rx Resources
1869 * @adapter: board private structure
1870 * @rx_ring: ring to clean the resources from
1871 *
1872 * Free all receive software resources
1873 **/
1874 static void igb_free_rx_resources(struct igb_adapter *adapter,
1875 struct igb_ring *rx_ring)
1876 {
1877 struct pci_dev *pdev = adapter->pdev;
1878
1879 igb_clean_rx_ring(adapter, rx_ring);
1880
1881 vfree(rx_ring->buffer_info);
1882 rx_ring->buffer_info = NULL;
1883
1884 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1885
1886 rx_ring->desc = NULL;
1887 }
1888
1889 /**
1890 * igb_free_all_rx_resources - Free Rx Resources for All Queues
1891 * @adapter: board private structure
1892 *
1893 * Free all receive software resources
1894 **/
1895 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
1896 {
1897 int i;
1898
1899 for (i = 0; i < adapter->num_rx_queues; i++)
1900 igb_free_rx_resources(adapter, &adapter->rx_ring[i]);
1901 }
1902
1903 /**
1904 * igb_clean_rx_ring - Free Rx Buffers per Queue
1905 * @adapter: board private structure
1906 * @rx_ring: ring to free buffers from
1907 **/
1908 static void igb_clean_rx_ring(struct igb_adapter *adapter,
1909 struct igb_ring *rx_ring)
1910 {
1911 struct igb_buffer *buffer_info;
1912 struct pci_dev *pdev = adapter->pdev;
1913 unsigned long size;
1914 unsigned int i;
1915
1916 if (!rx_ring->buffer_info)
1917 return;
1918 /* Free all the Rx ring sk_buffs */
1919 for (i = 0; i < rx_ring->count; i++) {
1920 buffer_info = &rx_ring->buffer_info[i];
1921 if (buffer_info->dma) {
1922 if (adapter->rx_ps_hdr_size)
1923 pci_unmap_single(pdev, buffer_info->dma,
1924 adapter->rx_ps_hdr_size,
1925 PCI_DMA_FROMDEVICE);
1926 else
1927 pci_unmap_single(pdev, buffer_info->dma,
1928 adapter->rx_buffer_len,
1929 PCI_DMA_FROMDEVICE);
1930 buffer_info->dma = 0;
1931 }
1932
1933 if (buffer_info->skb) {
1934 dev_kfree_skb(buffer_info->skb);
1935 buffer_info->skb = NULL;
1936 }
1937 if (buffer_info->page) {
1938 pci_unmap_page(pdev, buffer_info->page_dma,
1939 PAGE_SIZE, PCI_DMA_FROMDEVICE);
1940 put_page(buffer_info->page);
1941 buffer_info->page = NULL;
1942 buffer_info->page_dma = 0;
1943 }
1944 }
1945
1946 /* there also may be some cached data from a chained receive */
1947 if (rx_ring->pending_skb) {
1948 dev_kfree_skb(rx_ring->pending_skb);
1949 rx_ring->pending_skb = NULL;
1950 }
1951
1952 size = sizeof(struct igb_buffer) * rx_ring->count;
1953 memset(rx_ring->buffer_info, 0, size);
1954
1955 /* Zero out the descriptor ring */
1956 memset(rx_ring->desc, 0, rx_ring->size);
1957
1958 rx_ring->next_to_clean = 0;
1959 rx_ring->next_to_use = 0;
1960
1961 writel(0, adapter->hw.hw_addr + rx_ring->head);
1962 writel(0, adapter->hw.hw_addr + rx_ring->tail);
1963 }
1964
1965 /**
1966 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
1967 * @adapter: board private structure
1968 **/
1969 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
1970 {
1971 int i;
1972
1973 for (i = 0; i < adapter->num_rx_queues; i++)
1974 igb_clean_rx_ring(adapter, &adapter->rx_ring[i]);
1975 }
1976
1977 /**
1978 * igb_set_mac - Change the Ethernet Address of the NIC
1979 * @netdev: network interface device structure
1980 * @p: pointer to an address structure
1981 *
1982 * Returns 0 on success, negative on failure
1983 **/
1984 static int igb_set_mac(struct net_device *netdev, void *p)
1985 {
1986 struct igb_adapter *adapter = netdev_priv(netdev);
1987 struct sockaddr *addr = p;
1988
1989 if (!is_valid_ether_addr(addr->sa_data))
1990 return -EADDRNOTAVAIL;
1991
1992 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1993 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
1994
1995 adapter->hw.mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1996
1997 return 0;
1998 }
1999
2000 /**
2001 * igb_set_multi - Multicast and Promiscuous mode set
2002 * @netdev: network interface device structure
2003 *
2004 * The set_multi entry point is called whenever the multicast address
2005 * list or the network interface flags are updated. This routine is
2006 * responsible for configuring the hardware for proper multicast,
2007 * promiscuous mode, and all-multi behavior.
2008 **/
2009 static void igb_set_multi(struct net_device *netdev)
2010 {
2011 struct igb_adapter *adapter = netdev_priv(netdev);
2012 struct e1000_hw *hw = &adapter->hw;
2013 struct e1000_mac_info *mac = &hw->mac;
2014 struct dev_mc_list *mc_ptr;
2015 u8 *mta_list;
2016 u32 rctl;
2017 int i;
2018
2019 /* Check for Promiscuous and All Multicast modes */
2020
2021 rctl = rd32(E1000_RCTL);
2022
2023 if (netdev->flags & IFF_PROMISC)
2024 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2025 else if (netdev->flags & IFF_ALLMULTI) {
2026 rctl |= E1000_RCTL_MPE;
2027 rctl &= ~E1000_RCTL_UPE;
2028 } else
2029 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2030
2031 wr32(E1000_RCTL, rctl);
2032
2033 if (!netdev->mc_count) {
2034 /* nothing to program, so clear mc list */
2035 igb_update_mc_addr_list(hw, NULL, 0, 1,
2036 mac->rar_entry_count);
2037 return;
2038 }
2039
2040 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2041 if (!mta_list)
2042 return;
2043
2044 /* The shared function expects a packed array of only addresses. */
2045 mc_ptr = netdev->mc_list;
2046
2047 for (i = 0; i < netdev->mc_count; i++) {
2048 if (!mc_ptr)
2049 break;
2050 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2051 mc_ptr = mc_ptr->next;
2052 }
2053 igb_update_mc_addr_list(hw, mta_list, i, 1, mac->rar_entry_count);
2054 kfree(mta_list);
2055 }
2056
2057 /* Need to wait a few seconds after link up to get diagnostic information from
2058 * the phy */
2059 static void igb_update_phy_info(unsigned long data)
2060 {
2061 struct igb_adapter *adapter = (struct igb_adapter *) data;
2062 if (adapter->hw.phy.ops.get_phy_info)
2063 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
2064 }
2065
2066 /**
2067 * igb_watchdog - Timer Call-back
2068 * @data: pointer to adapter cast into an unsigned long
2069 **/
2070 static void igb_watchdog(unsigned long data)
2071 {
2072 struct igb_adapter *adapter = (struct igb_adapter *)data;
2073 /* Do the rest outside of interrupt context */
2074 schedule_work(&adapter->watchdog_task);
2075 }
2076
2077 static void igb_watchdog_task(struct work_struct *work)
2078 {
2079 struct igb_adapter *adapter = container_of(work,
2080 struct igb_adapter, watchdog_task);
2081 struct e1000_hw *hw = &adapter->hw;
2082
2083 struct net_device *netdev = adapter->netdev;
2084 struct igb_ring *tx_ring = adapter->tx_ring;
2085 struct e1000_mac_info *mac = &adapter->hw.mac;
2086 u32 link;
2087 s32 ret_val;
2088
2089 if ((netif_carrier_ok(netdev)) &&
2090 (rd32(E1000_STATUS) & E1000_STATUS_LU))
2091 goto link_up;
2092
2093 ret_val = hw->mac.ops.check_for_link(&adapter->hw);
2094 if ((ret_val == E1000_ERR_PHY) &&
2095 (hw->phy.type == e1000_phy_igp_3) &&
2096 (rd32(E1000_CTRL) &
2097 E1000_PHY_CTRL_GBE_DISABLE))
2098 dev_info(&adapter->pdev->dev,
2099 "Gigabit has been disabled, downgrading speed\n");
2100
2101 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
2102 !(rd32(E1000_TXCW) & E1000_TXCW_ANE))
2103 link = mac->serdes_has_link;
2104 else
2105 link = rd32(E1000_STATUS) &
2106 E1000_STATUS_LU;
2107
2108 if (link) {
2109 if (!netif_carrier_ok(netdev)) {
2110 u32 ctrl;
2111 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2112 &adapter->link_speed,
2113 &adapter->link_duplex);
2114
2115 ctrl = rd32(E1000_CTRL);
2116 dev_info(&adapter->pdev->dev,
2117 "NIC Link is Up %d Mbps %s, "
2118 "Flow Control: %s\n",
2119 adapter->link_speed,
2120 adapter->link_duplex == FULL_DUPLEX ?
2121 "Full Duplex" : "Half Duplex",
2122 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2123 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2124 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2125 E1000_CTRL_TFCE) ? "TX" : "None")));
2126
2127 /* tweak tx_queue_len according to speed/duplex and
2128 * adjust the timeout factor */
2129 netdev->tx_queue_len = adapter->tx_queue_len;
2130 adapter->tx_timeout_factor = 1;
2131 switch (adapter->link_speed) {
2132 case SPEED_10:
2133 netdev->tx_queue_len = 10;
2134 adapter->tx_timeout_factor = 14;
2135 break;
2136 case SPEED_100:
2137 netdev->tx_queue_len = 100;
2138 /* maybe add some timeout factor ? */
2139 break;
2140 }
2141
2142 netif_carrier_on(netdev);
2143 netif_wake_queue(netdev);
2144
2145 if (!test_bit(__IGB_DOWN, &adapter->state))
2146 mod_timer(&adapter->phy_info_timer,
2147 round_jiffies(jiffies + 2 * HZ));
2148 }
2149 } else {
2150 if (netif_carrier_ok(netdev)) {
2151 adapter->link_speed = 0;
2152 adapter->link_duplex = 0;
2153 dev_info(&adapter->pdev->dev, "NIC Link is Down\n");
2154 netif_carrier_off(netdev);
2155 netif_stop_queue(netdev);
2156 if (!test_bit(__IGB_DOWN, &adapter->state))
2157 mod_timer(&adapter->phy_info_timer,
2158 round_jiffies(jiffies + 2 * HZ));
2159 }
2160 }
2161
2162 link_up:
2163 igb_update_stats(adapter);
2164
2165 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2166 adapter->tpt_old = adapter->stats.tpt;
2167 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
2168 adapter->colc_old = adapter->stats.colc;
2169
2170 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2171 adapter->gorc_old = adapter->stats.gorc;
2172 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2173 adapter->gotc_old = adapter->stats.gotc;
2174
2175 igb_update_adaptive(&adapter->hw);
2176
2177 if (!netif_carrier_ok(netdev)) {
2178 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2179 /* We've lost link, so the controller stops DMA,
2180 * but we've got queued Tx work that's never going
2181 * to get done, so reset controller to flush Tx.
2182 * (Do the reset outside of interrupt context). */
2183 adapter->tx_timeout_count++;
2184 schedule_work(&adapter->reset_task);
2185 }
2186 }
2187
2188 /* Cause software interrupt to ensure rx ring is cleaned */
2189 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2190
2191 /* Force detection of hung controller every watchdog period */
2192 tx_ring->detect_tx_hung = true;
2193
2194 /* Reset the timer */
2195 if (!test_bit(__IGB_DOWN, &adapter->state))
2196 mod_timer(&adapter->watchdog_timer,
2197 round_jiffies(jiffies + 2 * HZ));
2198 }
2199
2200 enum latency_range {
2201 lowest_latency = 0,
2202 low_latency = 1,
2203 bulk_latency = 2,
2204 latency_invalid = 255
2205 };
2206
2207
2208 static void igb_lower_rx_eitr(struct igb_adapter *adapter,
2209 struct igb_ring *rx_ring)
2210 {
2211 struct e1000_hw *hw = &adapter->hw;
2212 int new_val;
2213
2214 new_val = rx_ring->itr_val / 2;
2215 if (new_val < IGB_MIN_DYN_ITR)
2216 new_val = IGB_MIN_DYN_ITR;
2217
2218 if (new_val != rx_ring->itr_val) {
2219 rx_ring->itr_val = new_val;
2220 wr32(rx_ring->itr_register,
2221 1000000000 / (new_val * 256));
2222 }
2223 }
2224
2225 static void igb_raise_rx_eitr(struct igb_adapter *adapter,
2226 struct igb_ring *rx_ring)
2227 {
2228 struct e1000_hw *hw = &adapter->hw;
2229 int new_val;
2230
2231 new_val = rx_ring->itr_val * 2;
2232 if (new_val > IGB_MAX_DYN_ITR)
2233 new_val = IGB_MAX_DYN_ITR;
2234
2235 if (new_val != rx_ring->itr_val) {
2236 rx_ring->itr_val = new_val;
2237 wr32(rx_ring->itr_register,
2238 1000000000 / (new_val * 256));
2239 }
2240 }
2241
2242 /**
2243 * igb_update_itr - update the dynamic ITR value based on statistics
2244 * Stores a new ITR value based on packets and byte
2245 * counts during the last interrupt. The advantage of per interrupt
2246 * computation is faster updates and more accurate ITR for the current
2247 * traffic pattern. Constants in this function were computed
2248 * based on theoretical maximum wire speed and thresholds were set based
2249 * on testing data as well as attempting to minimize response time
2250 * while increasing bulk throughput.
2251 * this functionality is controlled by the InterruptThrottleRate module
2252 * parameter (see igb_param.c)
2253 * NOTE: These calculations are only valid when operating in a single-
2254 * queue environment.
2255 * @adapter: pointer to adapter
2256 * @itr_setting: current adapter->itr
2257 * @packets: the number of packets during this measurement interval
2258 * @bytes: the number of bytes during this measurement interval
2259 **/
2260 static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2261 int packets, int bytes)
2262 {
2263 unsigned int retval = itr_setting;
2264
2265 if (packets == 0)
2266 goto update_itr_done;
2267
2268 switch (itr_setting) {
2269 case lowest_latency:
2270 /* handle TSO and jumbo frames */
2271 if (bytes/packets > 8000)
2272 retval = bulk_latency;
2273 else if ((packets < 5) && (bytes > 512))
2274 retval = low_latency;
2275 break;
2276 case low_latency: /* 50 usec aka 20000 ints/s */
2277 if (bytes > 10000) {
2278 /* this if handles the TSO accounting */
2279 if (bytes/packets > 8000) {
2280 retval = bulk_latency;
2281 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2282 retval = bulk_latency;
2283 } else if ((packets > 35)) {
2284 retval = lowest_latency;
2285 }
2286 } else if (bytes/packets > 2000) {
2287 retval = bulk_latency;
2288 } else if (packets <= 2 && bytes < 512) {
2289 retval = lowest_latency;
2290 }
2291 break;
2292 case bulk_latency: /* 250 usec aka 4000 ints/s */
2293 if (bytes > 25000) {
2294 if (packets > 35)
2295 retval = low_latency;
2296 } else if (bytes < 6000) {
2297 retval = low_latency;
2298 }
2299 break;
2300 }
2301
2302 update_itr_done:
2303 return retval;
2304 }
2305
2306 static void igb_set_itr(struct igb_adapter *adapter, u16 itr_register,
2307 int rx_only)
2308 {
2309 u16 current_itr;
2310 u32 new_itr = adapter->itr;
2311
2312 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2313 if (adapter->link_speed != SPEED_1000) {
2314 current_itr = 0;
2315 new_itr = 4000;
2316 goto set_itr_now;
2317 }
2318
2319 adapter->rx_itr = igb_update_itr(adapter,
2320 adapter->rx_itr,
2321 adapter->rx_ring->total_packets,
2322 adapter->rx_ring->total_bytes);
2323 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2324 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2325 adapter->rx_itr = low_latency;
2326
2327 if (!rx_only) {
2328 adapter->tx_itr = igb_update_itr(adapter,
2329 adapter->tx_itr,
2330 adapter->tx_ring->total_packets,
2331 adapter->tx_ring->total_bytes);
2332 /* conservative mode (itr 3) eliminates the
2333 * lowest_latency setting */
2334 if (adapter->itr_setting == 3 &&
2335 adapter->tx_itr == lowest_latency)
2336 adapter->tx_itr = low_latency;
2337
2338 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2339 } else {
2340 current_itr = adapter->rx_itr;
2341 }
2342
2343 switch (current_itr) {
2344 /* counts and packets in update_itr are dependent on these numbers */
2345 case lowest_latency:
2346 new_itr = 70000;
2347 break;
2348 case low_latency:
2349 new_itr = 20000; /* aka hwitr = ~200 */
2350 break;
2351 case bulk_latency:
2352 new_itr = 4000;
2353 break;
2354 default:
2355 break;
2356 }
2357
2358 set_itr_now:
2359 if (new_itr != adapter->itr) {
2360 /* this attempts to bias the interrupt rate towards Bulk
2361 * by adding intermediate steps when interrupt rate is
2362 * increasing */
2363 new_itr = new_itr > adapter->itr ?
2364 min(adapter->itr + (new_itr >> 2), new_itr) :
2365 new_itr;
2366 /* Don't write the value here; it resets the adapter's
2367 * internal timer, and causes us to delay far longer than
2368 * we should between interrupts. Instead, we write the ITR
2369 * value at the beginning of the next interrupt so the timing
2370 * ends up being correct.
2371 */
2372 adapter->itr = new_itr;
2373 adapter->set_itr = 1;
2374 }
2375
2376 return;
2377 }
2378
2379
2380 #define IGB_TX_FLAGS_CSUM 0x00000001
2381 #define IGB_TX_FLAGS_VLAN 0x00000002
2382 #define IGB_TX_FLAGS_TSO 0x00000004
2383 #define IGB_TX_FLAGS_IPV4 0x00000008
2384 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2385 #define IGB_TX_FLAGS_VLAN_SHIFT 16
2386
2387 static inline int igb_tso_adv(struct igb_adapter *adapter,
2388 struct igb_ring *tx_ring,
2389 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2390 {
2391 struct e1000_adv_tx_context_desc *context_desc;
2392 unsigned int i;
2393 int err;
2394 struct igb_buffer *buffer_info;
2395 u32 info = 0, tu_cmd = 0;
2396 u32 mss_l4len_idx, l4len;
2397 *hdr_len = 0;
2398
2399 if (skb_header_cloned(skb)) {
2400 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2401 if (err)
2402 return err;
2403 }
2404
2405 l4len = tcp_hdrlen(skb);
2406 *hdr_len += l4len;
2407
2408 if (skb->protocol == htons(ETH_P_IP)) {
2409 struct iphdr *iph = ip_hdr(skb);
2410 iph->tot_len = 0;
2411 iph->check = 0;
2412 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2413 iph->daddr, 0,
2414 IPPROTO_TCP,
2415 0);
2416 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2417 ipv6_hdr(skb)->payload_len = 0;
2418 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2419 &ipv6_hdr(skb)->daddr,
2420 0, IPPROTO_TCP, 0);
2421 }
2422
2423 i = tx_ring->next_to_use;
2424
2425 buffer_info = &tx_ring->buffer_info[i];
2426 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2427 /* VLAN MACLEN IPLEN */
2428 if (tx_flags & IGB_TX_FLAGS_VLAN)
2429 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2430 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2431 *hdr_len += skb_network_offset(skb);
2432 info |= skb_network_header_len(skb);
2433 *hdr_len += skb_network_header_len(skb);
2434 context_desc->vlan_macip_lens = cpu_to_le32(info);
2435
2436 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2437 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2438
2439 if (skb->protocol == htons(ETH_P_IP))
2440 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2441 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2442
2443 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2444
2445 /* MSS L4LEN IDX */
2446 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2447 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2448
2449 /* Context index must be unique per ring. Luckily, so is the interrupt
2450 * mask value. */
2451 mss_l4len_idx |= tx_ring->eims_value >> 4;
2452
2453 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2454 context_desc->seqnum_seed = 0;
2455
2456 buffer_info->time_stamp = jiffies;
2457 buffer_info->dma = 0;
2458 i++;
2459 if (i == tx_ring->count)
2460 i = 0;
2461
2462 tx_ring->next_to_use = i;
2463
2464 return true;
2465 }
2466
2467 static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2468 struct igb_ring *tx_ring,
2469 struct sk_buff *skb, u32 tx_flags)
2470 {
2471 struct e1000_adv_tx_context_desc *context_desc;
2472 unsigned int i;
2473 struct igb_buffer *buffer_info;
2474 u32 info = 0, tu_cmd = 0;
2475
2476 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2477 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2478 i = tx_ring->next_to_use;
2479 buffer_info = &tx_ring->buffer_info[i];
2480 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2481
2482 if (tx_flags & IGB_TX_FLAGS_VLAN)
2483 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2484 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2485 if (skb->ip_summed == CHECKSUM_PARTIAL)
2486 info |= skb_network_header_len(skb);
2487
2488 context_desc->vlan_macip_lens = cpu_to_le32(info);
2489
2490 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2491
2492 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2493 switch (skb->protocol) {
2494 case __constant_htons(ETH_P_IP):
2495 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2496 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2497 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2498 break;
2499 case __constant_htons(ETH_P_IPV6):
2500 /* XXX what about other V6 headers?? */
2501 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2502 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2503 break;
2504 default:
2505 if (unlikely(net_ratelimit()))
2506 dev_warn(&adapter->pdev->dev,
2507 "partial checksum but proto=%x!\n",
2508 skb->protocol);
2509 break;
2510 }
2511 }
2512
2513 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2514 context_desc->seqnum_seed = 0;
2515 context_desc->mss_l4len_idx =
2516 cpu_to_le32(tx_ring->eims_value >> 4);
2517
2518 buffer_info->time_stamp = jiffies;
2519 buffer_info->dma = 0;
2520
2521 i++;
2522 if (i == tx_ring->count)
2523 i = 0;
2524 tx_ring->next_to_use = i;
2525
2526 return true;
2527 }
2528
2529
2530 return false;
2531 }
2532
2533 #define IGB_MAX_TXD_PWR 16
2534 #define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
2535
2536 static inline int igb_tx_map_adv(struct igb_adapter *adapter,
2537 struct igb_ring *tx_ring,
2538 struct sk_buff *skb)
2539 {
2540 struct igb_buffer *buffer_info;
2541 unsigned int len = skb_headlen(skb);
2542 unsigned int count = 0, i;
2543 unsigned int f;
2544
2545 i = tx_ring->next_to_use;
2546
2547 buffer_info = &tx_ring->buffer_info[i];
2548 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2549 buffer_info->length = len;
2550 /* set time_stamp *before* dma to help avoid a possible race */
2551 buffer_info->time_stamp = jiffies;
2552 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2553 PCI_DMA_TODEVICE);
2554 count++;
2555 i++;
2556 if (i == tx_ring->count)
2557 i = 0;
2558
2559 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2560 struct skb_frag_struct *frag;
2561
2562 frag = &skb_shinfo(skb)->frags[f];
2563 len = frag->size;
2564
2565 buffer_info = &tx_ring->buffer_info[i];
2566 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2567 buffer_info->length = len;
2568 buffer_info->time_stamp = jiffies;
2569 buffer_info->dma = pci_map_page(adapter->pdev,
2570 frag->page,
2571 frag->page_offset,
2572 len,
2573 PCI_DMA_TODEVICE);
2574
2575 count++;
2576 i++;
2577 if (i == tx_ring->count)
2578 i = 0;
2579 }
2580
2581 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2582 tx_ring->buffer_info[i].skb = skb;
2583
2584 return count;
2585 }
2586
2587 static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2588 struct igb_ring *tx_ring,
2589 int tx_flags, int count, u32 paylen,
2590 u8 hdr_len)
2591 {
2592 union e1000_adv_tx_desc *tx_desc = NULL;
2593 struct igb_buffer *buffer_info;
2594 u32 olinfo_status = 0, cmd_type_len;
2595 unsigned int i;
2596
2597 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2598 E1000_ADVTXD_DCMD_DEXT);
2599
2600 if (tx_flags & IGB_TX_FLAGS_VLAN)
2601 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2602
2603 if (tx_flags & IGB_TX_FLAGS_TSO) {
2604 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2605
2606 /* insert tcp checksum */
2607 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2608
2609 /* insert ip checksum */
2610 if (tx_flags & IGB_TX_FLAGS_IPV4)
2611 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2612
2613 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2614 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2615 }
2616
2617 if (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2618 IGB_TX_FLAGS_VLAN))
2619 olinfo_status |= tx_ring->eims_value >> 4;
2620
2621 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2622
2623 i = tx_ring->next_to_use;
2624 while (count--) {
2625 buffer_info = &tx_ring->buffer_info[i];
2626 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
2627 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
2628 tx_desc->read.cmd_type_len =
2629 cpu_to_le32(cmd_type_len | buffer_info->length);
2630 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2631 i++;
2632 if (i == tx_ring->count)
2633 i = 0;
2634 }
2635
2636 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
2637 /* Force memory writes to complete before letting h/w
2638 * know there are new descriptors to fetch. (Only
2639 * applicable for weak-ordered memory model archs,
2640 * such as IA-64). */
2641 wmb();
2642
2643 tx_ring->next_to_use = i;
2644 writel(i, adapter->hw.hw_addr + tx_ring->tail);
2645 /* we need this if more than one processor can write to our tail
2646 * at a time, it syncronizes IO on IA64/Altix systems */
2647 mmiowb();
2648 }
2649
2650 static int __igb_maybe_stop_tx(struct net_device *netdev,
2651 struct igb_ring *tx_ring, int size)
2652 {
2653 struct igb_adapter *adapter = netdev_priv(netdev);
2654
2655 netif_stop_queue(netdev);
2656 /* Herbert's original patch had:
2657 * smp_mb__after_netif_stop_queue();
2658 * but since that doesn't exist yet, just open code it. */
2659 smp_mb();
2660
2661 /* We need to check again in a case another CPU has just
2662 * made room available. */
2663 if (IGB_DESC_UNUSED(tx_ring) < size)
2664 return -EBUSY;
2665
2666 /* A reprieve! */
2667 netif_start_queue(netdev);
2668 ++adapter->restart_queue;
2669 return 0;
2670 }
2671
2672 static int igb_maybe_stop_tx(struct net_device *netdev,
2673 struct igb_ring *tx_ring, int size)
2674 {
2675 if (IGB_DESC_UNUSED(tx_ring) >= size)
2676 return 0;
2677 return __igb_maybe_stop_tx(netdev, tx_ring, size);
2678 }
2679
2680 #define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
2681
2682 static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2683 struct net_device *netdev,
2684 struct igb_ring *tx_ring)
2685 {
2686 struct igb_adapter *adapter = netdev_priv(netdev);
2687 unsigned int tx_flags = 0;
2688 unsigned int len;
2689 unsigned long irq_flags;
2690 u8 hdr_len = 0;
2691 int tso = 0;
2692
2693 len = skb_headlen(skb);
2694
2695 if (test_bit(__IGB_DOWN, &adapter->state)) {
2696 dev_kfree_skb_any(skb);
2697 return NETDEV_TX_OK;
2698 }
2699
2700 if (skb->len <= 0) {
2701 dev_kfree_skb_any(skb);
2702 return NETDEV_TX_OK;
2703 }
2704
2705 if (!spin_trylock_irqsave(&tx_ring->tx_lock, irq_flags))
2706 /* Collision - tell upper layer to requeue */
2707 return NETDEV_TX_LOCKED;
2708
2709 /* need: 1 descriptor per page,
2710 * + 2 desc gap to keep tail from touching head,
2711 * + 1 desc for skb->data,
2712 * + 1 desc for context descriptor,
2713 * otherwise try next time */
2714 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2715 /* this is a hard error */
2716 spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags);
2717 return NETDEV_TX_BUSY;
2718 }
2719
2720 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2721 tx_flags |= IGB_TX_FLAGS_VLAN;
2722 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2723 }
2724
2725 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
2726 &hdr_len) : 0;
2727
2728 if (tso < 0) {
2729 dev_kfree_skb_any(skb);
2730 spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags);
2731 return NETDEV_TX_OK;
2732 }
2733
2734 if (tso)
2735 tx_flags |= IGB_TX_FLAGS_TSO;
2736 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
2737 if (skb->ip_summed == CHECKSUM_PARTIAL)
2738 tx_flags |= IGB_TX_FLAGS_CSUM;
2739
2740 if (skb->protocol == htons(ETH_P_IP))
2741 tx_flags |= IGB_TX_FLAGS_IPV4;
2742
2743 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
2744 igb_tx_map_adv(adapter, tx_ring, skb),
2745 skb->len, hdr_len);
2746
2747 netdev->trans_start = jiffies;
2748
2749 /* Make sure there is space in the ring for the next send. */
2750 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
2751
2752 spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags);
2753 return NETDEV_TX_OK;
2754 }
2755
2756 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
2757 {
2758 struct igb_adapter *adapter = netdev_priv(netdev);
2759 struct igb_ring *tx_ring = &adapter->tx_ring[0];
2760
2761 /* This goes back to the question of how to logically map a tx queue
2762 * to a flow. Right now, performance is impacted slightly negatively
2763 * if using multiple tx queues. If the stack breaks away from a
2764 * single qdisc implementation, we can look at this again. */
2765 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
2766 }
2767
2768 /**
2769 * igb_tx_timeout - Respond to a Tx Hang
2770 * @netdev: network interface device structure
2771 **/
2772 static void igb_tx_timeout(struct net_device *netdev)
2773 {
2774 struct igb_adapter *adapter = netdev_priv(netdev);
2775 struct e1000_hw *hw = &adapter->hw;
2776
2777 /* Do the reset outside of interrupt context */
2778 adapter->tx_timeout_count++;
2779 schedule_work(&adapter->reset_task);
2780 wr32(E1000_EICS, adapter->eims_enable_mask &
2781 ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER));
2782 }
2783
2784 static void igb_reset_task(struct work_struct *work)
2785 {
2786 struct igb_adapter *adapter;
2787 adapter = container_of(work, struct igb_adapter, reset_task);
2788
2789 igb_reinit_locked(adapter);
2790 }
2791
2792 /**
2793 * igb_get_stats - Get System Network Statistics
2794 * @netdev: network interface device structure
2795 *
2796 * Returns the address of the device statistics structure.
2797 * The statistics are actually updated from the timer callback.
2798 **/
2799 static struct net_device_stats *
2800 igb_get_stats(struct net_device *netdev)
2801 {
2802 struct igb_adapter *adapter = netdev_priv(netdev);
2803
2804 /* only return the current stats */
2805 return &adapter->net_stats;
2806 }
2807
2808 /**
2809 * igb_change_mtu - Change the Maximum Transfer Unit
2810 * @netdev: network interface device structure
2811 * @new_mtu: new value for maximum frame size
2812 *
2813 * Returns 0 on success, negative on failure
2814 **/
2815 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
2816 {
2817 struct igb_adapter *adapter = netdev_priv(netdev);
2818 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2819
2820 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2821 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
2822 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
2823 return -EINVAL;
2824 }
2825
2826 #define MAX_STD_JUMBO_FRAME_SIZE 9234
2827 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
2828 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
2829 return -EINVAL;
2830 }
2831
2832 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
2833 msleep(1);
2834 /* igb_down has a dependency on max_frame_size */
2835 adapter->max_frame_size = max_frame;
2836 if (netif_running(netdev))
2837 igb_down(adapter);
2838
2839 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
2840 * means we reserve 2 more, this pushes us to allocate from the next
2841 * larger slab size.
2842 * i.e. RXBUFFER_2048 --> size-4096 slab
2843 */
2844
2845 if (max_frame <= IGB_RXBUFFER_256)
2846 adapter->rx_buffer_len = IGB_RXBUFFER_256;
2847 else if (max_frame <= IGB_RXBUFFER_512)
2848 adapter->rx_buffer_len = IGB_RXBUFFER_512;
2849 else if (max_frame <= IGB_RXBUFFER_1024)
2850 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
2851 else if (max_frame <= IGB_RXBUFFER_2048)
2852 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
2853 else
2854 adapter->rx_buffer_len = IGB_RXBUFFER_4096;
2855 /* adjust allocation if LPE protects us, and we aren't using SBP */
2856 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
2857 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
2858 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2859
2860 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
2861 netdev->mtu, new_mtu);
2862 netdev->mtu = new_mtu;
2863
2864 if (netif_running(netdev))
2865 igb_up(adapter);
2866 else
2867 igb_reset(adapter);
2868
2869 clear_bit(__IGB_RESETTING, &adapter->state);
2870
2871 return 0;
2872 }
2873
2874 /**
2875 * igb_update_stats - Update the board statistics counters
2876 * @adapter: board private structure
2877 **/
2878
2879 void igb_update_stats(struct igb_adapter *adapter)
2880 {
2881 struct e1000_hw *hw = &adapter->hw;
2882 struct pci_dev *pdev = adapter->pdev;
2883 u16 phy_tmp;
2884
2885 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
2886
2887 /*
2888 * Prevent stats update while adapter is being reset, or if the pci
2889 * connection is down.
2890 */
2891 if (adapter->link_speed == 0)
2892 return;
2893 if (pci_channel_offline(pdev))
2894 return;
2895
2896 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
2897 adapter->stats.gprc += rd32(E1000_GPRC);
2898 adapter->stats.gorc += rd32(E1000_GORCL);
2899 rd32(E1000_GORCH); /* clear GORCL */
2900 adapter->stats.bprc += rd32(E1000_BPRC);
2901 adapter->stats.mprc += rd32(E1000_MPRC);
2902 adapter->stats.roc += rd32(E1000_ROC);
2903
2904 adapter->stats.prc64 += rd32(E1000_PRC64);
2905 adapter->stats.prc127 += rd32(E1000_PRC127);
2906 adapter->stats.prc255 += rd32(E1000_PRC255);
2907 adapter->stats.prc511 += rd32(E1000_PRC511);
2908 adapter->stats.prc1023 += rd32(E1000_PRC1023);
2909 adapter->stats.prc1522 += rd32(E1000_PRC1522);
2910 adapter->stats.symerrs += rd32(E1000_SYMERRS);
2911 adapter->stats.sec += rd32(E1000_SEC);
2912
2913 adapter->stats.mpc += rd32(E1000_MPC);
2914 adapter->stats.scc += rd32(E1000_SCC);
2915 adapter->stats.ecol += rd32(E1000_ECOL);
2916 adapter->stats.mcc += rd32(E1000_MCC);
2917 adapter->stats.latecol += rd32(E1000_LATECOL);
2918 adapter->stats.dc += rd32(E1000_DC);
2919 adapter->stats.rlec += rd32(E1000_RLEC);
2920 adapter->stats.xonrxc += rd32(E1000_XONRXC);
2921 adapter->stats.xontxc += rd32(E1000_XONTXC);
2922 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
2923 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
2924 adapter->stats.fcruc += rd32(E1000_FCRUC);
2925 adapter->stats.gptc += rd32(E1000_GPTC);
2926 adapter->stats.gotc += rd32(E1000_GOTCL);
2927 rd32(E1000_GOTCH); /* clear GOTCL */
2928 adapter->stats.rnbc += rd32(E1000_RNBC);
2929 adapter->stats.ruc += rd32(E1000_RUC);
2930 adapter->stats.rfc += rd32(E1000_RFC);
2931 adapter->stats.rjc += rd32(E1000_RJC);
2932 adapter->stats.tor += rd32(E1000_TORH);
2933 adapter->stats.tot += rd32(E1000_TOTH);
2934 adapter->stats.tpr += rd32(E1000_TPR);
2935
2936 adapter->stats.ptc64 += rd32(E1000_PTC64);
2937 adapter->stats.ptc127 += rd32(E1000_PTC127);
2938 adapter->stats.ptc255 += rd32(E1000_PTC255);
2939 adapter->stats.ptc511 += rd32(E1000_PTC511);
2940 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
2941 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
2942
2943 adapter->stats.mptc += rd32(E1000_MPTC);
2944 adapter->stats.bptc += rd32(E1000_BPTC);
2945
2946 /* used for adaptive IFS */
2947
2948 hw->mac.tx_packet_delta = rd32(E1000_TPT);
2949 adapter->stats.tpt += hw->mac.tx_packet_delta;
2950 hw->mac.collision_delta = rd32(E1000_COLC);
2951 adapter->stats.colc += hw->mac.collision_delta;
2952
2953 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
2954 adapter->stats.rxerrc += rd32(E1000_RXERRC);
2955 adapter->stats.tncrs += rd32(E1000_TNCRS);
2956 adapter->stats.tsctc += rd32(E1000_TSCTC);
2957 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
2958
2959 adapter->stats.iac += rd32(E1000_IAC);
2960 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
2961 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
2962 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
2963 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
2964 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
2965 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
2966 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
2967 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
2968
2969 /* Fill out the OS statistics structure */
2970 adapter->net_stats.multicast = adapter->stats.mprc;
2971 adapter->net_stats.collisions = adapter->stats.colc;
2972
2973 /* Rx Errors */
2974
2975 /* RLEC on some newer hardware can be incorrect so build
2976 * our own version based on RUC and ROC */
2977 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
2978 adapter->stats.crcerrs + adapter->stats.algnerrc +
2979 adapter->stats.ruc + adapter->stats.roc +
2980 adapter->stats.cexterr;
2981 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
2982 adapter->stats.roc;
2983 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
2984 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
2985 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
2986
2987 /* Tx Errors */
2988 adapter->net_stats.tx_errors = adapter->stats.ecol +
2989 adapter->stats.latecol;
2990 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
2991 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
2992 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
2993
2994 /* Tx Dropped needs to be maintained elsewhere */
2995
2996 /* Phy Stats */
2997 if (hw->phy.media_type == e1000_media_type_copper) {
2998 if ((adapter->link_speed == SPEED_1000) &&
2999 (!hw->phy.ops.read_phy_reg(hw, PHY_1000T_STATUS,
3000 &phy_tmp))) {
3001 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3002 adapter->phy_stats.idle_errors += phy_tmp;
3003 }
3004 }
3005
3006 /* Management Stats */
3007 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3008 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3009 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3010 }
3011
3012
3013 static irqreturn_t igb_msix_other(int irq, void *data)
3014 {
3015 struct net_device *netdev = data;
3016 struct igb_adapter *adapter = netdev_priv(netdev);
3017 struct e1000_hw *hw = &adapter->hw;
3018 u32 eicr;
3019 /* disable interrupts from the "other" bit, avoid re-entry */
3020 wr32(E1000_EIMC, E1000_EIMS_OTHER);
3021
3022 eicr = rd32(E1000_EICR);
3023
3024 if (eicr & E1000_EIMS_OTHER) {
3025 u32 icr = rd32(E1000_ICR);
3026 /* reading ICR causes bit 31 of EICR to be cleared */
3027 if (!(icr & E1000_ICR_LSC))
3028 goto no_link_interrupt;
3029 hw->mac.get_link_status = 1;
3030 /* guard against interrupt when we're going down */
3031 if (!test_bit(__IGB_DOWN, &adapter->state))
3032 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3033 }
3034
3035 no_link_interrupt:
3036 wr32(E1000_IMS, E1000_IMS_LSC);
3037 wr32(E1000_EIMS, E1000_EIMS_OTHER);
3038
3039 return IRQ_HANDLED;
3040 }
3041
3042 static irqreturn_t igb_msix_tx(int irq, void *data)
3043 {
3044 struct igb_ring *tx_ring = data;
3045 struct igb_adapter *adapter = tx_ring->adapter;
3046 struct e1000_hw *hw = &adapter->hw;
3047
3048 if (!tx_ring->itr_val)
3049 wr32(E1000_EIMC, tx_ring->eims_value);
3050
3051 tx_ring->total_bytes = 0;
3052 tx_ring->total_packets = 0;
3053 if (!igb_clean_tx_irq(adapter, tx_ring))
3054 /* Ring was not completely cleaned, so fire another interrupt */
3055 wr32(E1000_EICS, tx_ring->eims_value);
3056
3057 if (!tx_ring->itr_val)
3058 wr32(E1000_EIMS, tx_ring->eims_value);
3059 return IRQ_HANDLED;
3060 }
3061
3062 static irqreturn_t igb_msix_rx(int irq, void *data)
3063 {
3064 struct igb_ring *rx_ring = data;
3065 struct igb_adapter *adapter = rx_ring->adapter;
3066 struct e1000_hw *hw = &adapter->hw;
3067
3068 if (!rx_ring->itr_val)
3069 wr32(E1000_EIMC, rx_ring->eims_value);
3070
3071 if (netif_rx_schedule_prep(adapter->netdev, &rx_ring->napi)) {
3072 rx_ring->total_bytes = 0;
3073 rx_ring->total_packets = 0;
3074 rx_ring->no_itr_adjust = 0;
3075 __netif_rx_schedule(adapter->netdev, &rx_ring->napi);
3076 } else {
3077 if (!rx_ring->no_itr_adjust) {
3078 igb_lower_rx_eitr(adapter, rx_ring);
3079 rx_ring->no_itr_adjust = 1;
3080 }
3081 }
3082
3083 return IRQ_HANDLED;
3084 }
3085
3086
3087 /**
3088 * igb_intr_msi - Interrupt Handler
3089 * @irq: interrupt number
3090 * @data: pointer to a network interface device structure
3091 **/
3092 static irqreturn_t igb_intr_msi(int irq, void *data)
3093 {
3094 struct net_device *netdev = data;
3095 struct igb_adapter *adapter = netdev_priv(netdev);
3096 struct napi_struct *napi = &adapter->napi;
3097 struct e1000_hw *hw = &adapter->hw;
3098 /* read ICR disables interrupts using IAM */
3099 u32 icr = rd32(E1000_ICR);
3100
3101 /* Write the ITR value calculated at the end of the
3102 * previous interrupt.
3103 */
3104 if (adapter->set_itr) {
3105 wr32(E1000_ITR,
3106 1000000000 / (adapter->itr * 256));
3107 adapter->set_itr = 0;
3108 }
3109
3110 /* read ICR disables interrupts using IAM */
3111 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3112 hw->mac.get_link_status = 1;
3113 if (!test_bit(__IGB_DOWN, &adapter->state))
3114 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3115 }
3116
3117 if (netif_rx_schedule_prep(netdev, napi)) {
3118 adapter->tx_ring->total_bytes = 0;
3119 adapter->tx_ring->total_packets = 0;
3120 adapter->rx_ring->total_bytes = 0;
3121 adapter->rx_ring->total_packets = 0;
3122 __netif_rx_schedule(netdev, napi);
3123 }
3124
3125 return IRQ_HANDLED;
3126 }
3127
3128 /**
3129 * igb_intr - Interrupt Handler
3130 * @irq: interrupt number
3131 * @data: pointer to a network interface device structure
3132 **/
3133 static irqreturn_t igb_intr(int irq, void *data)
3134 {
3135 struct net_device *netdev = data;
3136 struct igb_adapter *adapter = netdev_priv(netdev);
3137 struct napi_struct *napi = &adapter->napi;
3138 struct e1000_hw *hw = &adapter->hw;
3139 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3140 * need for the IMC write */
3141 u32 icr = rd32(E1000_ICR);
3142 u32 eicr = 0;
3143 if (!icr)
3144 return IRQ_NONE; /* Not our interrupt */
3145
3146 /* Write the ITR value calculated at the end of the
3147 * previous interrupt.
3148 */
3149 if (adapter->set_itr) {
3150 wr32(E1000_ITR,
3151 1000000000 / (adapter->itr * 256));
3152 adapter->set_itr = 0;
3153 }
3154
3155 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3156 * not set, then the adapter didn't send an interrupt */
3157 if (!(icr & E1000_ICR_INT_ASSERTED))
3158 return IRQ_NONE;
3159
3160 eicr = rd32(E1000_EICR);
3161
3162 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3163 hw->mac.get_link_status = 1;
3164 /* guard against interrupt when we're going down */
3165 if (!test_bit(__IGB_DOWN, &adapter->state))
3166 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3167 }
3168
3169 if (netif_rx_schedule_prep(netdev, napi)) {
3170 adapter->tx_ring->total_bytes = 0;
3171 adapter->rx_ring->total_bytes = 0;
3172 adapter->tx_ring->total_packets = 0;
3173 adapter->rx_ring->total_packets = 0;
3174 __netif_rx_schedule(netdev, napi);
3175 }
3176
3177 return IRQ_HANDLED;
3178 }
3179
3180 /**
3181 * igb_clean - NAPI Rx polling callback
3182 * @adapter: board private structure
3183 **/
3184 static int igb_clean(struct napi_struct *napi, int budget)
3185 {
3186 struct igb_adapter *adapter = container_of(napi, struct igb_adapter,
3187 napi);
3188 struct net_device *netdev = adapter->netdev;
3189 int tx_clean_complete = 1, work_done = 0;
3190 int i;
3191
3192 /* Must NOT use netdev_priv macro here. */
3193 adapter = netdev->priv;
3194
3195 /* Keep link state information with original netdev */
3196 if (!netif_carrier_ok(netdev))
3197 goto quit_polling;
3198
3199 /* igb_clean is called per-cpu. This lock protects tx_ring[i] from
3200 * being cleaned by multiple cpus simultaneously. A failure obtaining
3201 * the lock means tx_ring[i] is currently being cleaned anyway. */
3202 for (i = 0; i < adapter->num_tx_queues; i++) {
3203 if (spin_trylock(&adapter->tx_ring[i].tx_clean_lock)) {
3204 tx_clean_complete &= igb_clean_tx_irq(adapter,
3205 &adapter->tx_ring[i]);
3206 spin_unlock(&adapter->tx_ring[i].tx_clean_lock);
3207 }
3208 }
3209
3210 for (i = 0; i < adapter->num_rx_queues; i++)
3211 igb_clean_rx_irq_adv(adapter, &adapter->rx_ring[i], &work_done,
3212 adapter->rx_ring[i].napi.weight);
3213
3214 /* If no Tx and not enough Rx work done, exit the polling mode */
3215 if ((tx_clean_complete && (work_done < budget)) ||
3216 !netif_running(netdev)) {
3217 quit_polling:
3218 if (adapter->itr_setting & 3)
3219 igb_set_itr(adapter, E1000_ITR, false);
3220 netif_rx_complete(netdev, napi);
3221 if (!test_bit(__IGB_DOWN, &adapter->state))
3222 igb_irq_enable(adapter);
3223 return 0;
3224 }
3225
3226 return 1;
3227 }
3228
3229 static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3230 {
3231 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3232 struct igb_adapter *adapter = rx_ring->adapter;
3233 struct e1000_hw *hw = &adapter->hw;
3234 struct net_device *netdev = adapter->netdev;
3235 int work_done = 0;
3236
3237 /* Keep link state information with original netdev */
3238 if (!netif_carrier_ok(netdev))
3239 goto quit_polling;
3240
3241 igb_clean_rx_irq_adv(adapter, rx_ring, &work_done, budget);
3242
3243
3244 /* If not enough Rx work done, exit the polling mode */
3245 if ((work_done == 0) || !netif_running(netdev)) {
3246 quit_polling:
3247 netif_rx_complete(netdev, napi);
3248
3249 wr32(E1000_EIMS, rx_ring->eims_value);
3250 if ((adapter->itr_setting & 3) && !rx_ring->no_itr_adjust &&
3251 (rx_ring->total_packets > IGB_DYN_ITR_PACKET_THRESHOLD)) {
3252 int mean_size = rx_ring->total_bytes /
3253 rx_ring->total_packets;
3254 if (mean_size < IGB_DYN_ITR_LENGTH_LOW)
3255 igb_raise_rx_eitr(adapter, rx_ring);
3256 else if (mean_size > IGB_DYN_ITR_LENGTH_HIGH)
3257 igb_lower_rx_eitr(adapter, rx_ring);
3258 }
3259 return 0;
3260 }
3261
3262 return 1;
3263 }
3264
3265 static inline u32 get_head(struct igb_ring *tx_ring)
3266 {
3267 void *end = (struct e1000_tx_desc *)tx_ring->desc + tx_ring->count;
3268 return le32_to_cpu(*(volatile __le32 *)end);
3269 }
3270
3271 /**
3272 * igb_clean_tx_irq - Reclaim resources after transmit completes
3273 * @adapter: board private structure
3274 * returns true if ring is completely cleaned
3275 **/
3276 static bool igb_clean_tx_irq(struct igb_adapter *adapter,
3277 struct igb_ring *tx_ring)
3278 {
3279 struct net_device *netdev = adapter->netdev;
3280 struct e1000_hw *hw = &adapter->hw;
3281 struct e1000_tx_desc *tx_desc;
3282 struct igb_buffer *buffer_info;
3283 struct sk_buff *skb;
3284 unsigned int i;
3285 u32 head, oldhead;
3286 unsigned int count = 0;
3287 bool cleaned = false;
3288 bool retval = true;
3289 unsigned int total_bytes = 0, total_packets = 0;
3290
3291 rmb();
3292 head = get_head(tx_ring);
3293 i = tx_ring->next_to_clean;
3294 while (1) {
3295 while (i != head) {
3296 cleaned = true;
3297 tx_desc = E1000_TX_DESC(*tx_ring, i);
3298 buffer_info = &tx_ring->buffer_info[i];
3299 skb = buffer_info->skb;
3300
3301 if (skb) {
3302 unsigned int segs, bytecount;
3303 /* gso_segs is currently only valid for tcp */
3304 segs = skb_shinfo(skb)->gso_segs ?: 1;
3305 /* multiply data chunks by size of headers */
3306 bytecount = ((segs - 1) * skb_headlen(skb)) +
3307 skb->len;
3308 total_packets += segs;
3309 total_bytes += bytecount;
3310 }
3311
3312 igb_unmap_and_free_tx_resource(adapter, buffer_info);
3313 tx_desc->upper.data = 0;
3314
3315 i++;
3316 if (i == tx_ring->count)
3317 i = 0;
3318
3319 count++;
3320 if (count == IGB_MAX_TX_CLEAN) {
3321 retval = false;
3322 goto done_cleaning;
3323 }
3324 }
3325 oldhead = head;
3326 rmb();
3327 head = get_head(tx_ring);
3328 if (head == oldhead)
3329 goto done_cleaning;
3330 } /* while (1) */
3331
3332 done_cleaning:
3333 tx_ring->next_to_clean = i;
3334
3335 if (unlikely(cleaned &&
3336 netif_carrier_ok(netdev) &&
3337 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3338 /* Make sure that anybody stopping the queue after this
3339 * sees the new next_to_clean.
3340 */
3341 smp_mb();
3342 if (netif_queue_stopped(netdev) &&
3343 !(test_bit(__IGB_DOWN, &adapter->state))) {
3344 netif_wake_queue(netdev);
3345 ++adapter->restart_queue;
3346 }
3347 }
3348
3349 if (tx_ring->detect_tx_hung) {
3350 /* Detect a transmit hang in hardware, this serializes the
3351 * check with the clearing of time_stamp and movement of i */
3352 tx_ring->detect_tx_hung = false;
3353 if (tx_ring->buffer_info[i].time_stamp &&
3354 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3355 (adapter->tx_timeout_factor * HZ))
3356 && !(rd32(E1000_STATUS) &
3357 E1000_STATUS_TXOFF)) {
3358
3359 tx_desc = E1000_TX_DESC(*tx_ring, i);
3360 /* detected Tx unit hang */
3361 dev_err(&adapter->pdev->dev,
3362 "Detected Tx Unit Hang\n"
3363 " Tx Queue <%lu>\n"
3364 " TDH <%x>\n"
3365 " TDT <%x>\n"
3366 " next_to_use <%x>\n"
3367 " next_to_clean <%x>\n"
3368 " head (WB) <%x>\n"
3369 "buffer_info[next_to_clean]\n"
3370 " time_stamp <%lx>\n"
3371 " jiffies <%lx>\n"
3372 " desc.status <%x>\n",
3373 (unsigned long)((tx_ring - adapter->tx_ring) /
3374 sizeof(struct igb_ring)),
3375 readl(adapter->hw.hw_addr + tx_ring->head),
3376 readl(adapter->hw.hw_addr + tx_ring->tail),
3377 tx_ring->next_to_use,
3378 tx_ring->next_to_clean,
3379 head,
3380 tx_ring->buffer_info[i].time_stamp,
3381 jiffies,
3382 tx_desc->upper.fields.status);
3383 netif_stop_queue(netdev);
3384 }
3385 }
3386 tx_ring->total_bytes += total_bytes;
3387 tx_ring->total_packets += total_packets;
3388 adapter->net_stats.tx_bytes += total_bytes;
3389 adapter->net_stats.tx_packets += total_packets;
3390 return retval;
3391 }
3392
3393
3394 /**
3395 * igb_receive_skb - helper function to handle rx indications
3396 * @adapter: board private structure
3397 * @status: descriptor status field as written by hardware
3398 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3399 * @skb: pointer to sk_buff to be indicated to stack
3400 **/
3401 static void igb_receive_skb(struct igb_adapter *adapter, u8 status, __le16 vlan,
3402 struct sk_buff *skb)
3403 {
3404 if (adapter->vlgrp && (status & E1000_RXD_STAT_VP))
3405 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3406 le16_to_cpu(vlan) &
3407 E1000_RXD_SPC_VLAN_MASK);
3408 else
3409 netif_receive_skb(skb);
3410 }
3411
3412
3413 static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3414 u32 status_err, struct sk_buff *skb)
3415 {
3416 skb->ip_summed = CHECKSUM_NONE;
3417
3418 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3419 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3420 return;
3421 /* TCP/UDP checksum error bit is set */
3422 if (status_err &
3423 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3424 /* let the stack verify checksum errors */
3425 adapter->hw_csum_err++;
3426 return;
3427 }
3428 /* It must be a TCP or UDP packet with a valid checksum */
3429 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3430 skb->ip_summed = CHECKSUM_UNNECESSARY;
3431
3432 adapter->hw_csum_good++;
3433 }
3434
3435 static bool igb_clean_rx_irq_adv(struct igb_adapter *adapter,
3436 struct igb_ring *rx_ring,
3437 int *work_done, int budget)
3438 {
3439 struct net_device *netdev = adapter->netdev;
3440 struct pci_dev *pdev = adapter->pdev;
3441 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3442 struct igb_buffer *buffer_info , *next_buffer;
3443 struct sk_buff *skb;
3444 unsigned int i, j;
3445 u32 length, hlen, staterr;
3446 bool cleaned = false;
3447 int cleaned_count = 0;
3448 unsigned int total_bytes = 0, total_packets = 0;
3449
3450 i = rx_ring->next_to_clean;
3451 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3452 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3453
3454 while (staterr & E1000_RXD_STAT_DD) {
3455 if (*work_done >= budget)
3456 break;
3457 (*work_done)++;
3458 buffer_info = &rx_ring->buffer_info[i];
3459
3460 /* HW will not DMA in data larger than the given buffer, even
3461 * if it parses the (NFS, of course) header to be larger. In
3462 * that case, it fills the header buffer and spills the rest
3463 * into the page.
3464 */
3465 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
3466 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
3467 if (hlen > adapter->rx_ps_hdr_size)
3468 hlen = adapter->rx_ps_hdr_size;
3469
3470 length = le16_to_cpu(rx_desc->wb.upper.length);
3471 cleaned = true;
3472 cleaned_count++;
3473
3474 if (rx_ring->pending_skb != NULL) {
3475 skb = rx_ring->pending_skb;
3476 rx_ring->pending_skb = NULL;
3477 j = rx_ring->pending_skb_page;
3478 } else {
3479 skb = buffer_info->skb;
3480 prefetch(skb->data - NET_IP_ALIGN);
3481 buffer_info->skb = NULL;
3482 if (hlen) {
3483 pci_unmap_single(pdev, buffer_info->dma,
3484 adapter->rx_ps_hdr_size +
3485 NET_IP_ALIGN,
3486 PCI_DMA_FROMDEVICE);
3487 skb_put(skb, hlen);
3488 } else {
3489 pci_unmap_single(pdev, buffer_info->dma,
3490 adapter->rx_buffer_len +
3491 NET_IP_ALIGN,
3492 PCI_DMA_FROMDEVICE);
3493 skb_put(skb, length);
3494 goto send_up;
3495 }
3496 j = 0;
3497 }
3498
3499 while (length) {
3500 pci_unmap_page(pdev, buffer_info->page_dma,
3501 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3502 buffer_info->page_dma = 0;
3503 skb_fill_page_desc(skb, j, buffer_info->page,
3504 0, length);
3505 buffer_info->page = NULL;
3506
3507 skb->len += length;
3508 skb->data_len += length;
3509 skb->truesize += length;
3510 rx_desc->wb.upper.status_error = 0;
3511 if (staterr & E1000_RXD_STAT_EOP)
3512 break;
3513
3514 j++;
3515 cleaned_count++;
3516 i++;
3517 if (i == rx_ring->count)
3518 i = 0;
3519
3520 buffer_info = &rx_ring->buffer_info[i];
3521 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3522 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3523 length = le16_to_cpu(rx_desc->wb.upper.length);
3524 if (!(staterr & E1000_RXD_STAT_DD)) {
3525 rx_ring->pending_skb = skb;
3526 rx_ring->pending_skb_page = j;
3527 goto out;
3528 }
3529 }
3530 send_up:
3531 pskb_trim(skb, skb->len - 4);
3532 i++;
3533 if (i == rx_ring->count)
3534 i = 0;
3535 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3536 prefetch(next_rxd);
3537 next_buffer = &rx_ring->buffer_info[i];
3538
3539 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3540 dev_kfree_skb_irq(skb);
3541 goto next_desc;
3542 }
3543 rx_ring->no_itr_adjust |= (staterr & E1000_RXD_STAT_DYNINT);
3544
3545 total_bytes += skb->len;
3546 total_packets++;
3547
3548 igb_rx_checksum_adv(adapter, staterr, skb);
3549
3550 skb->protocol = eth_type_trans(skb, netdev);
3551
3552 igb_receive_skb(adapter, staterr, rx_desc->wb.upper.vlan, skb);
3553
3554 netdev->last_rx = jiffies;
3555
3556 next_desc:
3557 rx_desc->wb.upper.status_error = 0;
3558
3559 /* return some buffers to hardware, one at a time is too slow */
3560 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3561 igb_alloc_rx_buffers_adv(adapter, rx_ring,
3562 cleaned_count);
3563 cleaned_count = 0;
3564 }
3565
3566 /* use prefetched values */
3567 rx_desc = next_rxd;
3568 buffer_info = next_buffer;
3569
3570 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3571 }
3572 out:
3573 rx_ring->next_to_clean = i;
3574 cleaned_count = IGB_DESC_UNUSED(rx_ring);
3575
3576 if (cleaned_count)
3577 igb_alloc_rx_buffers_adv(adapter, rx_ring, cleaned_count);
3578
3579 rx_ring->total_packets += total_packets;
3580 rx_ring->total_bytes += total_bytes;
3581 rx_ring->rx_stats.packets += total_packets;
3582 rx_ring->rx_stats.bytes += total_bytes;
3583 adapter->net_stats.rx_bytes += total_bytes;
3584 adapter->net_stats.rx_packets += total_packets;
3585 return cleaned;
3586 }
3587
3588
3589 /**
3590 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
3591 * @adapter: address of board private structure
3592 **/
3593 static void igb_alloc_rx_buffers_adv(struct igb_adapter *adapter,
3594 struct igb_ring *rx_ring,
3595 int cleaned_count)
3596 {
3597 struct net_device *netdev = adapter->netdev;
3598 struct pci_dev *pdev = adapter->pdev;
3599 union e1000_adv_rx_desc *rx_desc;
3600 struct igb_buffer *buffer_info;
3601 struct sk_buff *skb;
3602 unsigned int i;
3603
3604 i = rx_ring->next_to_use;
3605 buffer_info = &rx_ring->buffer_info[i];
3606
3607 while (cleaned_count--) {
3608 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3609
3610 if (adapter->rx_ps_hdr_size && !buffer_info->page) {
3611 buffer_info->page = alloc_page(GFP_ATOMIC);
3612 if (!buffer_info->page) {
3613 adapter->alloc_rx_buff_failed++;
3614 goto no_buffers;
3615 }
3616 buffer_info->page_dma =
3617 pci_map_page(pdev,
3618 buffer_info->page,
3619 0, PAGE_SIZE,
3620 PCI_DMA_FROMDEVICE);
3621 }
3622
3623 if (!buffer_info->skb) {
3624 int bufsz;
3625
3626 if (adapter->rx_ps_hdr_size)
3627 bufsz = adapter->rx_ps_hdr_size;
3628 else
3629 bufsz = adapter->rx_buffer_len;
3630 bufsz += NET_IP_ALIGN;
3631 skb = netdev_alloc_skb(netdev, bufsz);
3632
3633 if (!skb) {
3634 adapter->alloc_rx_buff_failed++;
3635 goto no_buffers;
3636 }
3637
3638 /* Make buffer alignment 2 beyond a 16 byte boundary
3639 * this will result in a 16 byte aligned IP header after
3640 * the 14 byte MAC header is removed
3641 */
3642 skb_reserve(skb, NET_IP_ALIGN);
3643
3644 buffer_info->skb = skb;
3645 buffer_info->dma = pci_map_single(pdev, skb->data,
3646 bufsz,
3647 PCI_DMA_FROMDEVICE);
3648
3649 }
3650 /* Refresh the desc even if buffer_addrs didn't change because
3651 * each write-back erases this info. */
3652 if (adapter->rx_ps_hdr_size) {
3653 rx_desc->read.pkt_addr =
3654 cpu_to_le64(buffer_info->page_dma);
3655 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
3656 } else {
3657 rx_desc->read.pkt_addr =
3658 cpu_to_le64(buffer_info->dma);
3659 rx_desc->read.hdr_addr = 0;
3660 }
3661
3662 i++;
3663 if (i == rx_ring->count)
3664 i = 0;
3665 buffer_info = &rx_ring->buffer_info[i];
3666 }
3667
3668 no_buffers:
3669 if (rx_ring->next_to_use != i) {
3670 rx_ring->next_to_use = i;
3671 if (i == 0)
3672 i = (rx_ring->count - 1);
3673 else
3674 i--;
3675
3676 /* Force memory writes to complete before letting h/w
3677 * know there are new descriptors to fetch. (Only
3678 * applicable for weak-ordered memory model archs,
3679 * such as IA-64). */
3680 wmb();
3681 writel(i, adapter->hw.hw_addr + rx_ring->tail);
3682 }
3683 }
3684
3685 /**
3686 * igb_mii_ioctl -
3687 * @netdev:
3688 * @ifreq:
3689 * @cmd:
3690 **/
3691 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3692 {
3693 struct igb_adapter *adapter = netdev_priv(netdev);
3694 struct mii_ioctl_data *data = if_mii(ifr);
3695
3696 if (adapter->hw.phy.media_type != e1000_media_type_copper)
3697 return -EOPNOTSUPP;
3698
3699 switch (cmd) {
3700 case SIOCGMIIPHY:
3701 data->phy_id = adapter->hw.phy.addr;
3702 break;
3703 case SIOCGMIIREG:
3704 if (!capable(CAP_NET_ADMIN))
3705 return -EPERM;
3706 if (adapter->hw.phy.ops.read_phy_reg(&adapter->hw,
3707 data->reg_num
3708 & 0x1F, &data->val_out))
3709 return -EIO;
3710 break;
3711 case SIOCSMIIREG:
3712 default:
3713 return -EOPNOTSUPP;
3714 }
3715 return 0;
3716 }
3717
3718 /**
3719 * igb_ioctl -
3720 * @netdev:
3721 * @ifreq:
3722 * @cmd:
3723 **/
3724 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3725 {
3726 switch (cmd) {
3727 case SIOCGMIIPHY:
3728 case SIOCGMIIREG:
3729 case SIOCSMIIREG:
3730 return igb_mii_ioctl(netdev, ifr, cmd);
3731 default:
3732 return -EOPNOTSUPP;
3733 }
3734 }
3735
3736 static void igb_vlan_rx_register(struct net_device *netdev,
3737 struct vlan_group *grp)
3738 {
3739 struct igb_adapter *adapter = netdev_priv(netdev);
3740 struct e1000_hw *hw = &adapter->hw;
3741 u32 ctrl, rctl;
3742
3743 igb_irq_disable(adapter);
3744 adapter->vlgrp = grp;
3745
3746 if (grp) {
3747 /* enable VLAN tag insert/strip */
3748 ctrl = rd32(E1000_CTRL);
3749 ctrl |= E1000_CTRL_VME;
3750 wr32(E1000_CTRL, ctrl);
3751
3752 /* enable VLAN receive filtering */
3753 rctl = rd32(E1000_RCTL);
3754 rctl |= E1000_RCTL_VFE;
3755 rctl &= ~E1000_RCTL_CFIEN;
3756 wr32(E1000_RCTL, rctl);
3757 igb_update_mng_vlan(adapter);
3758 wr32(E1000_RLPML,
3759 adapter->max_frame_size + VLAN_TAG_SIZE);
3760 } else {
3761 /* disable VLAN tag insert/strip */
3762 ctrl = rd32(E1000_CTRL);
3763 ctrl &= ~E1000_CTRL_VME;
3764 wr32(E1000_CTRL, ctrl);
3765
3766 /* disable VLAN filtering */
3767 rctl = rd32(E1000_RCTL);
3768 rctl &= ~E1000_RCTL_VFE;
3769 wr32(E1000_RCTL, rctl);
3770 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
3771 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
3772 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
3773 }
3774 wr32(E1000_RLPML,
3775 adapter->max_frame_size);
3776 }
3777
3778 if (!test_bit(__IGB_DOWN, &adapter->state))
3779 igb_irq_enable(adapter);
3780 }
3781
3782 static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3783 {
3784 struct igb_adapter *adapter = netdev_priv(netdev);
3785 struct e1000_hw *hw = &adapter->hw;
3786 u32 vfta, index;
3787
3788 if ((adapter->hw.mng_cookie.status &
3789 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
3790 (vid == adapter->mng_vlan_id))
3791 return;
3792 /* add VID to filter table */
3793 index = (vid >> 5) & 0x7F;
3794 vfta = array_rd32(E1000_VFTA, index);
3795 vfta |= (1 << (vid & 0x1F));
3796 igb_write_vfta(&adapter->hw, index, vfta);
3797 }
3798
3799 static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3800 {
3801 struct igb_adapter *adapter = netdev_priv(netdev);
3802 struct e1000_hw *hw = &adapter->hw;
3803 u32 vfta, index;
3804
3805 igb_irq_disable(adapter);
3806 vlan_group_set_device(adapter->vlgrp, vid, NULL);
3807
3808 if (!test_bit(__IGB_DOWN, &adapter->state))
3809 igb_irq_enable(adapter);
3810
3811 if ((adapter->hw.mng_cookie.status &
3812 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
3813 (vid == adapter->mng_vlan_id)) {
3814 /* release control to f/w */
3815 igb_release_hw_control(adapter);
3816 return;
3817 }
3818
3819 /* remove VID from filter table */
3820 index = (vid >> 5) & 0x7F;
3821 vfta = array_rd32(E1000_VFTA, index);
3822 vfta &= ~(1 << (vid & 0x1F));
3823 igb_write_vfta(&adapter->hw, index, vfta);
3824 }
3825
3826 static void igb_restore_vlan(struct igb_adapter *adapter)
3827 {
3828 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
3829
3830 if (adapter->vlgrp) {
3831 u16 vid;
3832 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
3833 if (!vlan_group_get_device(adapter->vlgrp, vid))
3834 continue;
3835 igb_vlan_rx_add_vid(adapter->netdev, vid);
3836 }
3837 }
3838 }
3839
3840 int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
3841 {
3842 struct e1000_mac_info *mac = &adapter->hw.mac;
3843
3844 mac->autoneg = 0;
3845
3846 /* Fiber NICs only allow 1000 gbps Full duplex */
3847 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
3848 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
3849 dev_err(&adapter->pdev->dev,
3850 "Unsupported Speed/Duplex configuration\n");
3851 return -EINVAL;
3852 }
3853
3854 switch (spddplx) {
3855 case SPEED_10 + DUPLEX_HALF:
3856 mac->forced_speed_duplex = ADVERTISE_10_HALF;
3857 break;
3858 case SPEED_10 + DUPLEX_FULL:
3859 mac->forced_speed_duplex = ADVERTISE_10_FULL;
3860 break;
3861 case SPEED_100 + DUPLEX_HALF:
3862 mac->forced_speed_duplex = ADVERTISE_100_HALF;
3863 break;
3864 case SPEED_100 + DUPLEX_FULL:
3865 mac->forced_speed_duplex = ADVERTISE_100_FULL;
3866 break;
3867 case SPEED_1000 + DUPLEX_FULL:
3868 mac->autoneg = 1;
3869 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
3870 break;
3871 case SPEED_1000 + DUPLEX_HALF: /* not supported */
3872 default:
3873 dev_err(&adapter->pdev->dev,
3874 "Unsupported Speed/Duplex configuration\n");
3875 return -EINVAL;
3876 }
3877 return 0;
3878 }
3879
3880
3881 static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
3882 {
3883 struct net_device *netdev = pci_get_drvdata(pdev);
3884 struct igb_adapter *adapter = netdev_priv(netdev);
3885 struct e1000_hw *hw = &adapter->hw;
3886 u32 ctrl, ctrl_ext, rctl, status;
3887 u32 wufc = adapter->wol;
3888 #ifdef CONFIG_PM
3889 int retval = 0;
3890 #endif
3891
3892 netif_device_detach(netdev);
3893
3894 if (netif_running(netdev)) {
3895 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
3896 igb_down(adapter);
3897 igb_free_irq(adapter);
3898 }
3899
3900 #ifdef CONFIG_PM
3901 retval = pci_save_state(pdev);
3902 if (retval)
3903 return retval;
3904 #endif
3905
3906 status = rd32(E1000_STATUS);
3907 if (status & E1000_STATUS_LU)
3908 wufc &= ~E1000_WUFC_LNKC;
3909
3910 if (wufc) {
3911 igb_setup_rctl(adapter);
3912 igb_set_multi(netdev);
3913
3914 /* turn on all-multi mode if wake on multicast is enabled */
3915 if (wufc & E1000_WUFC_MC) {
3916 rctl = rd32(E1000_RCTL);
3917 rctl |= E1000_RCTL_MPE;
3918 wr32(E1000_RCTL, rctl);
3919 }
3920
3921 ctrl = rd32(E1000_CTRL);
3922 /* advertise wake from D3Cold */
3923 #define E1000_CTRL_ADVD3WUC 0x00100000
3924 /* phy power management enable */
3925 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
3926 ctrl |= E1000_CTRL_ADVD3WUC;
3927 wr32(E1000_CTRL, ctrl);
3928
3929 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
3930 adapter->hw.phy.media_type ==
3931 e1000_media_type_internal_serdes) {
3932 /* keep the laser running in D3 */
3933 ctrl_ext = rd32(E1000_CTRL_EXT);
3934 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
3935 wr32(E1000_CTRL_EXT, ctrl_ext);
3936 }
3937
3938 /* Allow time for pending master requests to run */
3939 igb_disable_pcie_master(&adapter->hw);
3940
3941 wr32(E1000_WUC, E1000_WUC_PME_EN);
3942 wr32(E1000_WUFC, wufc);
3943 pci_enable_wake(pdev, PCI_D3hot, 1);
3944 pci_enable_wake(pdev, PCI_D3cold, 1);
3945 } else {
3946 wr32(E1000_WUC, 0);
3947 wr32(E1000_WUFC, 0);
3948 pci_enable_wake(pdev, PCI_D3hot, 0);
3949 pci_enable_wake(pdev, PCI_D3cold, 0);
3950 }
3951
3952 /* make sure adapter isn't asleep if manageability is enabled */
3953 if (adapter->en_mng_pt) {
3954 pci_enable_wake(pdev, PCI_D3hot, 1);
3955 pci_enable_wake(pdev, PCI_D3cold, 1);
3956 }
3957
3958 /* Release control of h/w to f/w. If f/w is AMT enabled, this
3959 * would have already happened in close and is redundant. */
3960 igb_release_hw_control(adapter);
3961
3962 pci_disable_device(pdev);
3963
3964 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3965
3966 return 0;
3967 }
3968
3969 #ifdef CONFIG_PM
3970 static int igb_resume(struct pci_dev *pdev)
3971 {
3972 struct net_device *netdev = pci_get_drvdata(pdev);
3973 struct igb_adapter *adapter = netdev_priv(netdev);
3974 struct e1000_hw *hw = &adapter->hw;
3975 u32 err;
3976
3977 pci_set_power_state(pdev, PCI_D0);
3978 pci_restore_state(pdev);
3979 err = pci_enable_device(pdev);
3980 if (err) {
3981 dev_err(&pdev->dev,
3982 "igb: Cannot enable PCI device from suspend\n");
3983 return err;
3984 }
3985 pci_set_master(pdev);
3986
3987 pci_enable_wake(pdev, PCI_D3hot, 0);
3988 pci_enable_wake(pdev, PCI_D3cold, 0);
3989
3990 if (netif_running(netdev)) {
3991 err = igb_request_irq(adapter);
3992 if (err)
3993 return err;
3994 }
3995
3996 /* e1000_power_up_phy(adapter); */
3997
3998 igb_reset(adapter);
3999 wr32(E1000_WUS, ~0);
4000
4001 igb_init_manageability(adapter);
4002
4003 if (netif_running(netdev))
4004 igb_up(adapter);
4005
4006 netif_device_attach(netdev);
4007
4008 /* let the f/w know that the h/w is now under the control of the
4009 * driver. */
4010 igb_get_hw_control(adapter);
4011
4012 return 0;
4013 }
4014 #endif
4015
4016 static void igb_shutdown(struct pci_dev *pdev)
4017 {
4018 igb_suspend(pdev, PMSG_SUSPEND);
4019 }
4020
4021 #ifdef CONFIG_NET_POLL_CONTROLLER
4022 /*
4023 * Polling 'interrupt' - used by things like netconsole to send skbs
4024 * without having to re-enable interrupts. It's not called while
4025 * the interrupt routine is executing.
4026 */
4027 static void igb_netpoll(struct net_device *netdev)
4028 {
4029 struct igb_adapter *adapter = netdev_priv(netdev);
4030 int i;
4031 int work_done = 0;
4032
4033 igb_irq_disable(adapter);
4034 for (i = 0; i < adapter->num_tx_queues; i++)
4035 igb_clean_tx_irq(adapter, &adapter->tx_ring[i]);
4036
4037 for (i = 0; i < adapter->num_rx_queues; i++)
4038 igb_clean_rx_irq_adv(adapter, &adapter->rx_ring[i],
4039 &work_done,
4040 adapter->rx_ring[i].napi.weight);
4041
4042 igb_irq_enable(adapter);
4043 }
4044 #endif /* CONFIG_NET_POLL_CONTROLLER */
4045
4046 /**
4047 * igb_io_error_detected - called when PCI error is detected
4048 * @pdev: Pointer to PCI device
4049 * @state: The current pci connection state
4050 *
4051 * This function is called after a PCI bus error affecting
4052 * this device has been detected.
4053 */
4054 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4055 pci_channel_state_t state)
4056 {
4057 struct net_device *netdev = pci_get_drvdata(pdev);
4058 struct igb_adapter *adapter = netdev_priv(netdev);
4059
4060 netif_device_detach(netdev);
4061
4062 if (netif_running(netdev))
4063 igb_down(adapter);
4064 pci_disable_device(pdev);
4065
4066 /* Request a slot slot reset. */
4067 return PCI_ERS_RESULT_NEED_RESET;
4068 }
4069
4070 /**
4071 * igb_io_slot_reset - called after the pci bus has been reset.
4072 * @pdev: Pointer to PCI device
4073 *
4074 * Restart the card from scratch, as if from a cold-boot. Implementation
4075 * resembles the first-half of the igb_resume routine.
4076 */
4077 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4078 {
4079 struct net_device *netdev = pci_get_drvdata(pdev);
4080 struct igb_adapter *adapter = netdev_priv(netdev);
4081 struct e1000_hw *hw = &adapter->hw;
4082
4083 if (pci_enable_device(pdev)) {
4084 dev_err(&pdev->dev,
4085 "Cannot re-enable PCI device after reset.\n");
4086 return PCI_ERS_RESULT_DISCONNECT;
4087 }
4088 pci_set_master(pdev);
4089 pci_restore_state(pdev);
4090
4091 pci_enable_wake(pdev, PCI_D3hot, 0);
4092 pci_enable_wake(pdev, PCI_D3cold, 0);
4093
4094 igb_reset(adapter);
4095 wr32(E1000_WUS, ~0);
4096
4097 return PCI_ERS_RESULT_RECOVERED;
4098 }
4099
4100 /**
4101 * igb_io_resume - called when traffic can start flowing again.
4102 * @pdev: Pointer to PCI device
4103 *
4104 * This callback is called when the error recovery driver tells us that
4105 * its OK to resume normal operation. Implementation resembles the
4106 * second-half of the igb_resume routine.
4107 */
4108 static void igb_io_resume(struct pci_dev *pdev)
4109 {
4110 struct net_device *netdev = pci_get_drvdata(pdev);
4111 struct igb_adapter *adapter = netdev_priv(netdev);
4112
4113 igb_init_manageability(adapter);
4114
4115 if (netif_running(netdev)) {
4116 if (igb_up(adapter)) {
4117 dev_err(&pdev->dev, "igb_up failed after reset\n");
4118 return;
4119 }
4120 }
4121
4122 netif_device_attach(netdev);
4123
4124 /* let the f/w know that the h/w is now under the control of the
4125 * driver. */
4126 igb_get_hw_control(adapter);
4127
4128 }
4129
4130 /* igb_main.c */
Linux kernel - Deliverables
This page took 0.114224 seconds and 6 git commands to generate.