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Merge branch 'for-linus' of git://oss.sgi.com/xfs/xfs
[deliverable/linux.git] / drivers / net / igb / igb_main.c
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/module.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/vmalloc.h>
32 #include <linux/pagemap.h>
33 #include <linux/netdevice.h>
34 #include <linux/ipv6.h>
35 #include <net/checksum.h>
36 #include <net/ip6_checksum.h>
37 #include <linux/net_tstamp.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
40 #include <linux/if_vlan.h>
41 #include <linux/pci.h>
42 #include <linux/pci-aspm.h>
43 #include <linux/delay.h>
44 #include <linux/interrupt.h>
45 #include <linux/if_ether.h>
46 #include <linux/aer.h>
47 #ifdef CONFIG_IGB_DCA
48 #include <linux/dca.h>
49 #endif
50 #include "igb.h"
51
52 #define DRV_VERSION "1.3.16-k2"
53 char igb_driver_name[] = "igb";
54 char igb_driver_version[] = DRV_VERSION;
55 static const char igb_driver_string[] =
56 "Intel(R) Gigabit Ethernet Network Driver";
57 static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
58
59 static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
61 };
62
63 static struct pci_device_id igb_pci_tbl[] = {
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
72 /* required last entry */
73 {0, }
74 };
75
76 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
77
78 void igb_reset(struct igb_adapter *);
79 static int igb_setup_all_tx_resources(struct igb_adapter *);
80 static int igb_setup_all_rx_resources(struct igb_adapter *);
81 static void igb_free_all_tx_resources(struct igb_adapter *);
82 static void igb_free_all_rx_resources(struct igb_adapter *);
83 void igb_update_stats(struct igb_adapter *);
84 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
85 static void __devexit igb_remove(struct pci_dev *pdev);
86 static int igb_sw_init(struct igb_adapter *);
87 static int igb_open(struct net_device *);
88 static int igb_close(struct net_device *);
89 static void igb_configure_tx(struct igb_adapter *);
90 static void igb_configure_rx(struct igb_adapter *);
91 static void igb_setup_rctl(struct igb_adapter *);
92 static void igb_clean_all_tx_rings(struct igb_adapter *);
93 static void igb_clean_all_rx_rings(struct igb_adapter *);
94 static void igb_clean_tx_ring(struct igb_ring *);
95 static void igb_clean_rx_ring(struct igb_ring *);
96 static void igb_set_multi(struct net_device *);
97 static void igb_update_phy_info(unsigned long);
98 static void igb_watchdog(unsigned long);
99 static void igb_watchdog_task(struct work_struct *);
100 static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
101 struct igb_ring *);
102 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
103 static struct net_device_stats *igb_get_stats(struct net_device *);
104 static int igb_change_mtu(struct net_device *, int);
105 static int igb_set_mac(struct net_device *, void *);
106 static irqreturn_t igb_intr(int irq, void *);
107 static irqreturn_t igb_intr_msi(int irq, void *);
108 static irqreturn_t igb_msix_other(int irq, void *);
109 static irqreturn_t igb_msix_rx(int irq, void *);
110 static irqreturn_t igb_msix_tx(int irq, void *);
111 #ifdef CONFIG_IGB_DCA
112 static void igb_update_rx_dca(struct igb_ring *);
113 static void igb_update_tx_dca(struct igb_ring *);
114 static void igb_setup_dca(struct igb_adapter *);
115 #endif /* CONFIG_IGB_DCA */
116 static bool igb_clean_tx_irq(struct igb_ring *);
117 static int igb_poll(struct napi_struct *, int);
118 static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
119 static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
120 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
121 static void igb_tx_timeout(struct net_device *);
122 static void igb_reset_task(struct work_struct *);
123 static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
124 static void igb_vlan_rx_add_vid(struct net_device *, u16);
125 static void igb_vlan_rx_kill_vid(struct net_device *, u16);
126 static void igb_restore_vlan(struct igb_adapter *);
127 static void igb_ping_all_vfs(struct igb_adapter *);
128 static void igb_msg_task(struct igb_adapter *);
129 static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
130 static inline void igb_set_rah_pool(struct e1000_hw *, int , int);
131 static void igb_set_mc_list_pools(struct igb_adapter *, int, u16);
132 static void igb_vmm_control(struct igb_adapter *);
133 static inline void igb_set_vmolr(struct e1000_hw *, int);
134 static inline int igb_set_vf_rlpml(struct igb_adapter *, int, int);
135 static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
136 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
137
138 #ifdef CONFIG_PM
139 static int igb_suspend(struct pci_dev *, pm_message_t);
140 static int igb_resume(struct pci_dev *);
141 #endif
142 static void igb_shutdown(struct pci_dev *);
143 #ifdef CONFIG_IGB_DCA
144 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
145 static struct notifier_block dca_notifier = {
146 .notifier_call = igb_notify_dca,
147 .next = NULL,
148 .priority = 0
149 };
150 #endif
151 #ifdef CONFIG_NET_POLL_CONTROLLER
152 /* for netdump / net console */
153 static void igb_netpoll(struct net_device *);
154 #endif
155 #ifdef CONFIG_PCI_IOV
156 static unsigned int max_vfs = 0;
157 module_param(max_vfs, uint, 0);
158 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
159 "per physical function");
160 #endif /* CONFIG_PCI_IOV */
161
162 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
163 pci_channel_state_t);
164 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
165 static void igb_io_resume(struct pci_dev *);
166
167 static struct pci_error_handlers igb_err_handler = {
168 .error_detected = igb_io_error_detected,
169 .slot_reset = igb_io_slot_reset,
170 .resume = igb_io_resume,
171 };
172
173
174 static struct pci_driver igb_driver = {
175 .name = igb_driver_name,
176 .id_table = igb_pci_tbl,
177 .probe = igb_probe,
178 .remove = __devexit_p(igb_remove),
179 #ifdef CONFIG_PM
180 /* Power Managment Hooks */
181 .suspend = igb_suspend,
182 .resume = igb_resume,
183 #endif
184 .shutdown = igb_shutdown,
185 .err_handler = &igb_err_handler
186 };
187
188 static int global_quad_port_a; /* global quad port a indication */
189
190 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
191 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
192 MODULE_LICENSE("GPL");
193 MODULE_VERSION(DRV_VERSION);
194
195 /**
196 * Scale the NIC clock cycle by a large factor so that
197 * relatively small clock corrections can be added or
198 * substracted at each clock tick. The drawbacks of a
199 * large factor are a) that the clock register overflows
200 * more quickly (not such a big deal) and b) that the
201 * increment per tick has to fit into 24 bits.
202 *
203 * Note that
204 * TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
205 * IGB_TSYNC_SCALE
206 * TIMINCA += TIMINCA * adjustment [ppm] / 1e9
207 *
208 * The base scale factor is intentionally a power of two
209 * so that the division in %struct timecounter can be done with
210 * a shift.
211 */
212 #define IGB_TSYNC_SHIFT (19)
213 #define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
214
215 /**
216 * The duration of one clock cycle of the NIC.
217 *
218 * @todo This hard-coded value is part of the specification and might change
219 * in future hardware revisions. Add revision check.
220 */
221 #define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
222
223 #if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
224 # error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
225 #endif
226
227 /**
228 * igb_read_clock - read raw cycle counter (to be used by time counter)
229 */
230 static cycle_t igb_read_clock(const struct cyclecounter *tc)
231 {
232 struct igb_adapter *adapter =
233 container_of(tc, struct igb_adapter, cycles);
234 struct e1000_hw *hw = &adapter->hw;
235 u64 stamp;
236
237 stamp = rd32(E1000_SYSTIML);
238 stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
239
240 return stamp;
241 }
242
243 #ifdef DEBUG
244 /**
245 * igb_get_hw_dev_name - return device name string
246 * used by hardware layer to print debugging information
247 **/
248 char *igb_get_hw_dev_name(struct e1000_hw *hw)
249 {
250 struct igb_adapter *adapter = hw->back;
251 return adapter->netdev->name;
252 }
253
254 /**
255 * igb_get_time_str - format current NIC and system time as string
256 */
257 static char *igb_get_time_str(struct igb_adapter *adapter,
258 char buffer[160])
259 {
260 cycle_t hw = adapter->cycles.read(&adapter->cycles);
261 struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
262 struct timespec sys;
263 struct timespec delta;
264 getnstimeofday(&sys);
265
266 delta = timespec_sub(nic, sys);
267
268 sprintf(buffer,
269 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
270 hw,
271 (long)nic.tv_sec, nic.tv_nsec,
272 (long)sys.tv_sec, sys.tv_nsec,
273 (long)delta.tv_sec, delta.tv_nsec);
274
275 return buffer;
276 }
277 #endif
278
279 /**
280 * igb_desc_unused - calculate if we have unused descriptors
281 **/
282 static int igb_desc_unused(struct igb_ring *ring)
283 {
284 if (ring->next_to_clean > ring->next_to_use)
285 return ring->next_to_clean - ring->next_to_use - 1;
286
287 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
288 }
289
290 /**
291 * igb_init_module - Driver Registration Routine
292 *
293 * igb_init_module is the first routine called when the driver is
294 * loaded. All it does is register with the PCI subsystem.
295 **/
296 static int __init igb_init_module(void)
297 {
298 int ret;
299 printk(KERN_INFO "%s - version %s\n",
300 igb_driver_string, igb_driver_version);
301
302 printk(KERN_INFO "%s\n", igb_copyright);
303
304 global_quad_port_a = 0;
305
306 #ifdef CONFIG_IGB_DCA
307 dca_register_notify(&dca_notifier);
308 #endif
309
310 ret = pci_register_driver(&igb_driver);
311 return ret;
312 }
313
314 module_init(igb_init_module);
315
316 /**
317 * igb_exit_module - Driver Exit Cleanup Routine
318 *
319 * igb_exit_module is called just before the driver is removed
320 * from memory.
321 **/
322 static void __exit igb_exit_module(void)
323 {
324 #ifdef CONFIG_IGB_DCA
325 dca_unregister_notify(&dca_notifier);
326 #endif
327 pci_unregister_driver(&igb_driver);
328 }
329
330 module_exit(igb_exit_module);
331
332 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
333 /**
334 * igb_cache_ring_register - Descriptor ring to register mapping
335 * @adapter: board private structure to initialize
336 *
337 * Once we know the feature-set enabled for the device, we'll cache
338 * the register offset the descriptor ring is assigned to.
339 **/
340 static void igb_cache_ring_register(struct igb_adapter *adapter)
341 {
342 int i;
343 unsigned int rbase_offset = adapter->vfs_allocated_count;
344
345 switch (adapter->hw.mac.type) {
346 case e1000_82576:
347 /* The queues are allocated for virtualization such that VF 0
348 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
349 * In order to avoid collision we start at the first free queue
350 * and continue consuming queues in the same sequence
351 */
352 for (i = 0; i < adapter->num_rx_queues; i++)
353 adapter->rx_ring[i].reg_idx = rbase_offset +
354 Q_IDX_82576(i);
355 for (i = 0; i < adapter->num_tx_queues; i++)
356 adapter->tx_ring[i].reg_idx = rbase_offset +
357 Q_IDX_82576(i);
358 break;
359 case e1000_82575:
360 default:
361 for (i = 0; i < adapter->num_rx_queues; i++)
362 adapter->rx_ring[i].reg_idx = i;
363 for (i = 0; i < adapter->num_tx_queues; i++)
364 adapter->tx_ring[i].reg_idx = i;
365 break;
366 }
367 }
368
369 /**
370 * igb_alloc_queues - Allocate memory for all rings
371 * @adapter: board private structure to initialize
372 *
373 * We allocate one ring per queue at run-time since we don't know the
374 * number of queues at compile-time.
375 **/
376 static int igb_alloc_queues(struct igb_adapter *adapter)
377 {
378 int i;
379
380 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
381 sizeof(struct igb_ring), GFP_KERNEL);
382 if (!adapter->tx_ring)
383 return -ENOMEM;
384
385 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
386 sizeof(struct igb_ring), GFP_KERNEL);
387 if (!adapter->rx_ring) {
388 kfree(adapter->tx_ring);
389 return -ENOMEM;
390 }
391
392 adapter->rx_ring->buddy = adapter->tx_ring;
393
394 for (i = 0; i < adapter->num_tx_queues; i++) {
395 struct igb_ring *ring = &(adapter->tx_ring[i]);
396 ring->count = adapter->tx_ring_count;
397 ring->adapter = adapter;
398 ring->queue_index = i;
399 }
400 for (i = 0; i < adapter->num_rx_queues; i++) {
401 struct igb_ring *ring = &(adapter->rx_ring[i]);
402 ring->count = adapter->rx_ring_count;
403 ring->adapter = adapter;
404 ring->queue_index = i;
405 ring->itr_register = E1000_ITR;
406
407 /* set a default napi handler for each rx_ring */
408 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
409 }
410
411 igb_cache_ring_register(adapter);
412 return 0;
413 }
414
415 static void igb_free_queues(struct igb_adapter *adapter)
416 {
417 int i;
418
419 for (i = 0; i < adapter->num_rx_queues; i++)
420 netif_napi_del(&adapter->rx_ring[i].napi);
421
422 adapter->num_rx_queues = 0;
423 adapter->num_tx_queues = 0;
424
425 kfree(adapter->tx_ring);
426 kfree(adapter->rx_ring);
427 }
428
429 #define IGB_N0_QUEUE -1
430 static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
431 int tx_queue, int msix_vector)
432 {
433 u32 msixbm = 0;
434 struct e1000_hw *hw = &adapter->hw;
435 u32 ivar, index;
436
437 switch (hw->mac.type) {
438 case e1000_82575:
439 /* The 82575 assigns vectors using a bitmask, which matches the
440 bitmask for the EICR/EIMS/EIMC registers. To assign one
441 or more queues to a vector, we write the appropriate bits
442 into the MSIXBM register for that vector. */
443 if (rx_queue > IGB_N0_QUEUE) {
444 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
445 adapter->rx_ring[rx_queue].eims_value = msixbm;
446 }
447 if (tx_queue > IGB_N0_QUEUE) {
448 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
449 adapter->tx_ring[tx_queue].eims_value =
450 E1000_EICR_TX_QUEUE0 << tx_queue;
451 }
452 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
453 break;
454 case e1000_82576:
455 /* 82576 uses a table-based method for assigning vectors.
456 Each queue has a single entry in the table to which we write
457 a vector number along with a "valid" bit. Sadly, the layout
458 of the table is somewhat counterintuitive. */
459 if (rx_queue > IGB_N0_QUEUE) {
460 index = (rx_queue >> 1) + adapter->vfs_allocated_count;
461 ivar = array_rd32(E1000_IVAR0, index);
462 if (rx_queue & 0x1) {
463 /* vector goes into third byte of register */
464 ivar = ivar & 0xFF00FFFF;
465 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
466 } else {
467 /* vector goes into low byte of register */
468 ivar = ivar & 0xFFFFFF00;
469 ivar |= msix_vector | E1000_IVAR_VALID;
470 }
471 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
472 array_wr32(E1000_IVAR0, index, ivar);
473 }
474 if (tx_queue > IGB_N0_QUEUE) {
475 index = (tx_queue >> 1) + adapter->vfs_allocated_count;
476 ivar = array_rd32(E1000_IVAR0, index);
477 if (tx_queue & 0x1) {
478 /* vector goes into high byte of register */
479 ivar = ivar & 0x00FFFFFF;
480 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
481 } else {
482 /* vector goes into second byte of register */
483 ivar = ivar & 0xFFFF00FF;
484 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
485 }
486 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
487 array_wr32(E1000_IVAR0, index, ivar);
488 }
489 break;
490 default:
491 BUG();
492 break;
493 }
494 }
495
496 /**
497 * igb_configure_msix - Configure MSI-X hardware
498 *
499 * igb_configure_msix sets up the hardware to properly
500 * generate MSI-X interrupts.
501 **/
502 static void igb_configure_msix(struct igb_adapter *adapter)
503 {
504 u32 tmp;
505 int i, vector = 0;
506 struct e1000_hw *hw = &adapter->hw;
507
508 adapter->eims_enable_mask = 0;
509 if (hw->mac.type == e1000_82576)
510 /* Turn on MSI-X capability first, or our settings
511 * won't stick. And it will take days to debug. */
512 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
513 E1000_GPIE_PBA | E1000_GPIE_EIAME |
514 E1000_GPIE_NSICR);
515
516 for (i = 0; i < adapter->num_tx_queues; i++) {
517 struct igb_ring *tx_ring = &adapter->tx_ring[i];
518 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
519 adapter->eims_enable_mask |= tx_ring->eims_value;
520 if (tx_ring->itr_val)
521 writel(tx_ring->itr_val,
522 hw->hw_addr + tx_ring->itr_register);
523 else
524 writel(1, hw->hw_addr + tx_ring->itr_register);
525 }
526
527 for (i = 0; i < adapter->num_rx_queues; i++) {
528 struct igb_ring *rx_ring = &adapter->rx_ring[i];
529 rx_ring->buddy = NULL;
530 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
531 adapter->eims_enable_mask |= rx_ring->eims_value;
532 if (rx_ring->itr_val)
533 writel(rx_ring->itr_val,
534 hw->hw_addr + rx_ring->itr_register);
535 else
536 writel(1, hw->hw_addr + rx_ring->itr_register);
537 }
538
539
540 /* set vector for other causes, i.e. link changes */
541 switch (hw->mac.type) {
542 case e1000_82575:
543 array_wr32(E1000_MSIXBM(0), vector++,
544 E1000_EIMS_OTHER);
545
546 tmp = rd32(E1000_CTRL_EXT);
547 /* enable MSI-X PBA support*/
548 tmp |= E1000_CTRL_EXT_PBA_CLR;
549
550 /* Auto-Mask interrupts upon ICR read. */
551 tmp |= E1000_CTRL_EXT_EIAME;
552 tmp |= E1000_CTRL_EXT_IRCA;
553
554 wr32(E1000_CTRL_EXT, tmp);
555 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
556 adapter->eims_other = E1000_EIMS_OTHER;
557
558 break;
559
560 case e1000_82576:
561 tmp = (vector++ | E1000_IVAR_VALID) << 8;
562 wr32(E1000_IVAR_MISC, tmp);
563
564 adapter->eims_enable_mask = (1 << (vector)) - 1;
565 adapter->eims_other = 1 << (vector - 1);
566 break;
567 default:
568 /* do nothing, since nothing else supports MSI-X */
569 break;
570 } /* switch (hw->mac.type) */
571 wrfl();
572 }
573
574 /**
575 * igb_request_msix - Initialize MSI-X interrupts
576 *
577 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
578 * kernel.
579 **/
580 static int igb_request_msix(struct igb_adapter *adapter)
581 {
582 struct net_device *netdev = adapter->netdev;
583 int i, err = 0, vector = 0;
584
585 vector = 0;
586
587 for (i = 0; i < adapter->num_tx_queues; i++) {
588 struct igb_ring *ring = &(adapter->tx_ring[i]);
589 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
590 err = request_irq(adapter->msix_entries[vector].vector,
591 &igb_msix_tx, 0, ring->name,
592 &(adapter->tx_ring[i]));
593 if (err)
594 goto out;
595 ring->itr_register = E1000_EITR(0) + (vector << 2);
596 ring->itr_val = 976; /* ~4000 ints/sec */
597 vector++;
598 }
599 for (i = 0; i < adapter->num_rx_queues; i++) {
600 struct igb_ring *ring = &(adapter->rx_ring[i]);
601 if (strlen(netdev->name) < (IFNAMSIZ - 5))
602 sprintf(ring->name, "%s-rx-%d", netdev->name, i);
603 else
604 memcpy(ring->name, netdev->name, IFNAMSIZ);
605 err = request_irq(adapter->msix_entries[vector].vector,
606 &igb_msix_rx, 0, ring->name,
607 &(adapter->rx_ring[i]));
608 if (err)
609 goto out;
610 ring->itr_register = E1000_EITR(0) + (vector << 2);
611 ring->itr_val = adapter->itr;
612 vector++;
613 }
614
615 err = request_irq(adapter->msix_entries[vector].vector,
616 &igb_msix_other, 0, netdev->name, netdev);
617 if (err)
618 goto out;
619
620 igb_configure_msix(adapter);
621 return 0;
622 out:
623 return err;
624 }
625
626 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
627 {
628 if (adapter->msix_entries) {
629 pci_disable_msix(adapter->pdev);
630 kfree(adapter->msix_entries);
631 adapter->msix_entries = NULL;
632 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
633 pci_disable_msi(adapter->pdev);
634 return;
635 }
636
637
638 /**
639 * igb_set_interrupt_capability - set MSI or MSI-X if supported
640 *
641 * Attempt to configure interrupts using the best available
642 * capabilities of the hardware and kernel.
643 **/
644 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
645 {
646 int err;
647 int numvecs, i;
648
649 /* Number of supported queues. */
650 /* Having more queues than CPUs doesn't make sense. */
651 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
652 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
653
654 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
655 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
656 GFP_KERNEL);
657 if (!adapter->msix_entries)
658 goto msi_only;
659
660 for (i = 0; i < numvecs; i++)
661 adapter->msix_entries[i].entry = i;
662
663 err = pci_enable_msix(adapter->pdev,
664 adapter->msix_entries,
665 numvecs);
666 if (err == 0)
667 goto out;
668
669 igb_reset_interrupt_capability(adapter);
670
671 /* If we can't do MSI-X, try MSI */
672 msi_only:
673 #ifdef CONFIG_PCI_IOV
674 /* disable SR-IOV for non MSI-X configurations */
675 if (adapter->vf_data) {
676 struct e1000_hw *hw = &adapter->hw;
677 /* disable iov and allow time for transactions to clear */
678 pci_disable_sriov(adapter->pdev);
679 msleep(500);
680
681 kfree(adapter->vf_data);
682 adapter->vf_data = NULL;
683 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
684 msleep(100);
685 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
686 }
687 #endif
688 adapter->num_rx_queues = 1;
689 adapter->num_tx_queues = 1;
690 if (!pci_enable_msi(adapter->pdev))
691 adapter->flags |= IGB_FLAG_HAS_MSI;
692 out:
693 /* Notify the stack of the (possibly) reduced Tx Queue count. */
694 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
695 return;
696 }
697
698 /**
699 * igb_request_irq - initialize interrupts
700 *
701 * Attempts to configure interrupts using the best available
702 * capabilities of the hardware and kernel.
703 **/
704 static int igb_request_irq(struct igb_adapter *adapter)
705 {
706 struct net_device *netdev = adapter->netdev;
707 struct e1000_hw *hw = &adapter->hw;
708 int err = 0;
709
710 if (adapter->msix_entries) {
711 err = igb_request_msix(adapter);
712 if (!err)
713 goto request_done;
714 /* fall back to MSI */
715 igb_reset_interrupt_capability(adapter);
716 if (!pci_enable_msi(adapter->pdev))
717 adapter->flags |= IGB_FLAG_HAS_MSI;
718 igb_free_all_tx_resources(adapter);
719 igb_free_all_rx_resources(adapter);
720 adapter->num_rx_queues = 1;
721 igb_alloc_queues(adapter);
722 } else {
723 switch (hw->mac.type) {
724 case e1000_82575:
725 wr32(E1000_MSIXBM(0),
726 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
727 break;
728 case e1000_82576:
729 wr32(E1000_IVAR0, E1000_IVAR_VALID);
730 break;
731 default:
732 break;
733 }
734 }
735
736 if (adapter->flags & IGB_FLAG_HAS_MSI) {
737 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
738 netdev->name, netdev);
739 if (!err)
740 goto request_done;
741 /* fall back to legacy interrupts */
742 igb_reset_interrupt_capability(adapter);
743 adapter->flags &= ~IGB_FLAG_HAS_MSI;
744 }
745
746 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
747 netdev->name, netdev);
748
749 if (err)
750 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
751 err);
752
753 request_done:
754 return err;
755 }
756
757 static void igb_free_irq(struct igb_adapter *adapter)
758 {
759 struct net_device *netdev = adapter->netdev;
760
761 if (adapter->msix_entries) {
762 int vector = 0, i;
763
764 for (i = 0; i < adapter->num_tx_queues; i++)
765 free_irq(adapter->msix_entries[vector++].vector,
766 &(adapter->tx_ring[i]));
767 for (i = 0; i < adapter->num_rx_queues; i++)
768 free_irq(adapter->msix_entries[vector++].vector,
769 &(adapter->rx_ring[i]));
770
771 free_irq(adapter->msix_entries[vector++].vector, netdev);
772 return;
773 }
774
775 free_irq(adapter->pdev->irq, netdev);
776 }
777
778 /**
779 * igb_irq_disable - Mask off interrupt generation on the NIC
780 * @adapter: board private structure
781 **/
782 static void igb_irq_disable(struct igb_adapter *adapter)
783 {
784 struct e1000_hw *hw = &adapter->hw;
785
786 if (adapter->msix_entries) {
787 wr32(E1000_EIAM, 0);
788 wr32(E1000_EIMC, ~0);
789 wr32(E1000_EIAC, 0);
790 }
791
792 wr32(E1000_IAM, 0);
793 wr32(E1000_IMC, ~0);
794 wrfl();
795 synchronize_irq(adapter->pdev->irq);
796 }
797
798 /**
799 * igb_irq_enable - Enable default interrupt generation settings
800 * @adapter: board private structure
801 **/
802 static void igb_irq_enable(struct igb_adapter *adapter)
803 {
804 struct e1000_hw *hw = &adapter->hw;
805
806 if (adapter->msix_entries) {
807 wr32(E1000_EIAC, adapter->eims_enable_mask);
808 wr32(E1000_EIAM, adapter->eims_enable_mask);
809 wr32(E1000_EIMS, adapter->eims_enable_mask);
810 if (adapter->vfs_allocated_count)
811 wr32(E1000_MBVFIMR, 0xFF);
812 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
813 E1000_IMS_DOUTSYNC));
814 } else {
815 wr32(E1000_IMS, IMS_ENABLE_MASK);
816 wr32(E1000_IAM, IMS_ENABLE_MASK);
817 }
818 }
819
820 static void igb_update_mng_vlan(struct igb_adapter *adapter)
821 {
822 struct net_device *netdev = adapter->netdev;
823 u16 vid = adapter->hw.mng_cookie.vlan_id;
824 u16 old_vid = adapter->mng_vlan_id;
825 if (adapter->vlgrp) {
826 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
827 if (adapter->hw.mng_cookie.status &
828 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
829 igb_vlan_rx_add_vid(netdev, vid);
830 adapter->mng_vlan_id = vid;
831 } else
832 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
833
834 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
835 (vid != old_vid) &&
836 !vlan_group_get_device(adapter->vlgrp, old_vid))
837 igb_vlan_rx_kill_vid(netdev, old_vid);
838 } else
839 adapter->mng_vlan_id = vid;
840 }
841 }
842
843 /**
844 * igb_release_hw_control - release control of the h/w to f/w
845 * @adapter: address of board private structure
846 *
847 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
848 * For ASF and Pass Through versions of f/w this means that the
849 * driver is no longer loaded.
850 *
851 **/
852 static void igb_release_hw_control(struct igb_adapter *adapter)
853 {
854 struct e1000_hw *hw = &adapter->hw;
855 u32 ctrl_ext;
856
857 /* Let firmware take over control of h/w */
858 ctrl_ext = rd32(E1000_CTRL_EXT);
859 wr32(E1000_CTRL_EXT,
860 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
861 }
862
863
864 /**
865 * igb_get_hw_control - get control of the h/w from f/w
866 * @adapter: address of board private structure
867 *
868 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
869 * For ASF and Pass Through versions of f/w this means that
870 * the driver is loaded.
871 *
872 **/
873 static void igb_get_hw_control(struct igb_adapter *adapter)
874 {
875 struct e1000_hw *hw = &adapter->hw;
876 u32 ctrl_ext;
877
878 /* Let firmware know the driver has taken over */
879 ctrl_ext = rd32(E1000_CTRL_EXT);
880 wr32(E1000_CTRL_EXT,
881 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
882 }
883
884 /**
885 * igb_configure - configure the hardware for RX and TX
886 * @adapter: private board structure
887 **/
888 static void igb_configure(struct igb_adapter *adapter)
889 {
890 struct net_device *netdev = adapter->netdev;
891 int i;
892
893 igb_get_hw_control(adapter);
894 igb_set_multi(netdev);
895
896 igb_restore_vlan(adapter);
897
898 igb_configure_tx(adapter);
899 igb_setup_rctl(adapter);
900 igb_configure_rx(adapter);
901
902 igb_rx_fifo_flush_82575(&adapter->hw);
903
904 /* call igb_desc_unused which always leaves
905 * at least 1 descriptor unused to make sure
906 * next_to_use != next_to_clean */
907 for (i = 0; i < adapter->num_rx_queues; i++) {
908 struct igb_ring *ring = &adapter->rx_ring[i];
909 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
910 }
911
912
913 adapter->tx_queue_len = netdev->tx_queue_len;
914 }
915
916
917 /**
918 * igb_up - Open the interface and prepare it to handle traffic
919 * @adapter: board private structure
920 **/
921
922 int igb_up(struct igb_adapter *adapter)
923 {
924 struct e1000_hw *hw = &adapter->hw;
925 int i;
926
927 /* hardware has been reset, we need to reload some things */
928 igb_configure(adapter);
929
930 clear_bit(__IGB_DOWN, &adapter->state);
931
932 for (i = 0; i < adapter->num_rx_queues; i++)
933 napi_enable(&adapter->rx_ring[i].napi);
934 if (adapter->msix_entries)
935 igb_configure_msix(adapter);
936
937 igb_vmm_control(adapter);
938 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
939 igb_set_vmolr(hw, adapter->vfs_allocated_count);
940
941 /* Clear any pending interrupts. */
942 rd32(E1000_ICR);
943 igb_irq_enable(adapter);
944
945 /* Fire a link change interrupt to start the watchdog. */
946 wr32(E1000_ICS, E1000_ICS_LSC);
947 return 0;
948 }
949
950 void igb_down(struct igb_adapter *adapter)
951 {
952 struct e1000_hw *hw = &adapter->hw;
953 struct net_device *netdev = adapter->netdev;
954 u32 tctl, rctl;
955 int i;
956
957 /* signal that we're down so the interrupt handler does not
958 * reschedule our watchdog timer */
959 set_bit(__IGB_DOWN, &adapter->state);
960
961 /* disable receives in the hardware */
962 rctl = rd32(E1000_RCTL);
963 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
964 /* flush and sleep below */
965
966 netif_tx_stop_all_queues(netdev);
967
968 /* disable transmits in the hardware */
969 tctl = rd32(E1000_TCTL);
970 tctl &= ~E1000_TCTL_EN;
971 wr32(E1000_TCTL, tctl);
972 /* flush both disables and wait for them to finish */
973 wrfl();
974 msleep(10);
975
976 for (i = 0; i < adapter->num_rx_queues; i++)
977 napi_disable(&adapter->rx_ring[i].napi);
978
979 igb_irq_disable(adapter);
980
981 del_timer_sync(&adapter->watchdog_timer);
982 del_timer_sync(&adapter->phy_info_timer);
983
984 netdev->tx_queue_len = adapter->tx_queue_len;
985 netif_carrier_off(netdev);
986
987 /* record the stats before reset*/
988 igb_update_stats(adapter);
989
990 adapter->link_speed = 0;
991 adapter->link_duplex = 0;
992
993 if (!pci_channel_offline(adapter->pdev))
994 igb_reset(adapter);
995 igb_clean_all_tx_rings(adapter);
996 igb_clean_all_rx_rings(adapter);
997 }
998
999 void igb_reinit_locked(struct igb_adapter *adapter)
1000 {
1001 WARN_ON(in_interrupt());
1002 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1003 msleep(1);
1004 igb_down(adapter);
1005 igb_up(adapter);
1006 clear_bit(__IGB_RESETTING, &adapter->state);
1007 }
1008
1009 void igb_reset(struct igb_adapter *adapter)
1010 {
1011 struct e1000_hw *hw = &adapter->hw;
1012 struct e1000_mac_info *mac = &hw->mac;
1013 struct e1000_fc_info *fc = &hw->fc;
1014 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1015 u16 hwm;
1016
1017 /* Repartition Pba for greater than 9k mtu
1018 * To take effect CTRL.RST is required.
1019 */
1020 switch (mac->type) {
1021 case e1000_82576:
1022 pba = E1000_PBA_64K;
1023 break;
1024 case e1000_82575:
1025 default:
1026 pba = E1000_PBA_34K;
1027 break;
1028 }
1029
1030 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1031 (mac->type < e1000_82576)) {
1032 /* adjust PBA for jumbo frames */
1033 wr32(E1000_PBA, pba);
1034
1035 /* To maintain wire speed transmits, the Tx FIFO should be
1036 * large enough to accommodate two full transmit packets,
1037 * rounded up to the next 1KB and expressed in KB. Likewise,
1038 * the Rx FIFO should be large enough to accommodate at least
1039 * one full receive packet and is similarly rounded up and
1040 * expressed in KB. */
1041 pba = rd32(E1000_PBA);
1042 /* upper 16 bits has Tx packet buffer allocation size in KB */
1043 tx_space = pba >> 16;
1044 /* lower 16 bits has Rx packet buffer allocation size in KB */
1045 pba &= 0xffff;
1046 /* the tx fifo also stores 16 bytes of information about the tx
1047 * but don't include ethernet FCS because hardware appends it */
1048 min_tx_space = (adapter->max_frame_size +
1049 sizeof(union e1000_adv_tx_desc) -
1050 ETH_FCS_LEN) * 2;
1051 min_tx_space = ALIGN(min_tx_space, 1024);
1052 min_tx_space >>= 10;
1053 /* software strips receive CRC, so leave room for it */
1054 min_rx_space = adapter->max_frame_size;
1055 min_rx_space = ALIGN(min_rx_space, 1024);
1056 min_rx_space >>= 10;
1057
1058 /* If current Tx allocation is less than the min Tx FIFO size,
1059 * and the min Tx FIFO size is less than the current Rx FIFO
1060 * allocation, take space away from current Rx allocation */
1061 if (tx_space < min_tx_space &&
1062 ((min_tx_space - tx_space) < pba)) {
1063 pba = pba - (min_tx_space - tx_space);
1064
1065 /* if short on rx space, rx wins and must trump tx
1066 * adjustment */
1067 if (pba < min_rx_space)
1068 pba = min_rx_space;
1069 }
1070 wr32(E1000_PBA, pba);
1071 }
1072
1073 /* flow control settings */
1074 /* The high water mark must be low enough to fit one full frame
1075 * (or the size used for early receive) above it in the Rx FIFO.
1076 * Set it to the lower of:
1077 * - 90% of the Rx FIFO size, or
1078 * - the full Rx FIFO size minus one full frame */
1079 hwm = min(((pba << 10) * 9 / 10),
1080 ((pba << 10) - 2 * adapter->max_frame_size));
1081
1082 if (mac->type < e1000_82576) {
1083 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1084 fc->low_water = fc->high_water - 8;
1085 } else {
1086 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1087 fc->low_water = fc->high_water - 16;
1088 }
1089 fc->pause_time = 0xFFFF;
1090 fc->send_xon = 1;
1091 fc->type = fc->original_type;
1092
1093 /* disable receive for all VFs and wait one second */
1094 if (adapter->vfs_allocated_count) {
1095 int i;
1096 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1097 adapter->vf_data[i].clear_to_send = false;
1098
1099 /* ping all the active vfs to let them know we are going down */
1100 igb_ping_all_vfs(adapter);
1101
1102 /* disable transmits and receives */
1103 wr32(E1000_VFRE, 0);
1104 wr32(E1000_VFTE, 0);
1105 }
1106
1107 /* Allow time for pending master requests to run */
1108 adapter->hw.mac.ops.reset_hw(&adapter->hw);
1109 wr32(E1000_WUC, 0);
1110
1111 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1112 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1113
1114 igb_update_mng_vlan(adapter);
1115
1116 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1117 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1118
1119 igb_reset_adaptive(&adapter->hw);
1120 igb_get_phy_info(&adapter->hw);
1121 }
1122
1123 static const struct net_device_ops igb_netdev_ops = {
1124 .ndo_open = igb_open,
1125 .ndo_stop = igb_close,
1126 .ndo_start_xmit = igb_xmit_frame_adv,
1127 .ndo_get_stats = igb_get_stats,
1128 .ndo_set_multicast_list = igb_set_multi,
1129 .ndo_set_mac_address = igb_set_mac,
1130 .ndo_change_mtu = igb_change_mtu,
1131 .ndo_do_ioctl = igb_ioctl,
1132 .ndo_tx_timeout = igb_tx_timeout,
1133 .ndo_validate_addr = eth_validate_addr,
1134 .ndo_vlan_rx_register = igb_vlan_rx_register,
1135 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1136 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1137 #ifdef CONFIG_NET_POLL_CONTROLLER
1138 .ndo_poll_controller = igb_netpoll,
1139 #endif
1140 };
1141
1142 /**
1143 * igb_probe - Device Initialization Routine
1144 * @pdev: PCI device information struct
1145 * @ent: entry in igb_pci_tbl
1146 *
1147 * Returns 0 on success, negative on failure
1148 *
1149 * igb_probe initializes an adapter identified by a pci_dev structure.
1150 * The OS initialization, configuring of the adapter private structure,
1151 * and a hardware reset occur.
1152 **/
1153 static int __devinit igb_probe(struct pci_dev *pdev,
1154 const struct pci_device_id *ent)
1155 {
1156 struct net_device *netdev;
1157 struct igb_adapter *adapter;
1158 struct e1000_hw *hw;
1159 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1160 unsigned long mmio_start, mmio_len;
1161 int err, pci_using_dac;
1162 u16 eeprom_data = 0;
1163 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1164 u32 part_num;
1165
1166 err = pci_enable_device_mem(pdev);
1167 if (err)
1168 return err;
1169
1170 pci_using_dac = 0;
1171 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1172 if (!err) {
1173 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1174 if (!err)
1175 pci_using_dac = 1;
1176 } else {
1177 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1178 if (err) {
1179 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1180 if (err) {
1181 dev_err(&pdev->dev, "No usable DMA "
1182 "configuration, aborting\n");
1183 goto err_dma;
1184 }
1185 }
1186 }
1187
1188 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1189 IORESOURCE_MEM),
1190 igb_driver_name);
1191 if (err)
1192 goto err_pci_reg;
1193
1194 err = pci_enable_pcie_error_reporting(pdev);
1195 if (err) {
1196 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1197 "0x%x\n", err);
1198 /* non-fatal, continue */
1199 }
1200
1201 pci_set_master(pdev);
1202 pci_save_state(pdev);
1203
1204 err = -ENOMEM;
1205 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1206 IGB_ABS_MAX_TX_QUEUES);
1207 if (!netdev)
1208 goto err_alloc_etherdev;
1209
1210 SET_NETDEV_DEV(netdev, &pdev->dev);
1211
1212 pci_set_drvdata(pdev, netdev);
1213 adapter = netdev_priv(netdev);
1214 adapter->netdev = netdev;
1215 adapter->pdev = pdev;
1216 hw = &adapter->hw;
1217 hw->back = adapter;
1218 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1219
1220 mmio_start = pci_resource_start(pdev, 0);
1221 mmio_len = pci_resource_len(pdev, 0);
1222
1223 err = -EIO;
1224 hw->hw_addr = ioremap(mmio_start, mmio_len);
1225 if (!hw->hw_addr)
1226 goto err_ioremap;
1227
1228 netdev->netdev_ops = &igb_netdev_ops;
1229 igb_set_ethtool_ops(netdev);
1230 netdev->watchdog_timeo = 5 * HZ;
1231
1232 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1233
1234 netdev->mem_start = mmio_start;
1235 netdev->mem_end = mmio_start + mmio_len;
1236
1237 /* PCI config space info */
1238 hw->vendor_id = pdev->vendor;
1239 hw->device_id = pdev->device;
1240 hw->revision_id = pdev->revision;
1241 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1242 hw->subsystem_device_id = pdev->subsystem_device;
1243
1244 /* setup the private structure */
1245 hw->back = adapter;
1246 /* Copy the default MAC, PHY and NVM function pointers */
1247 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1248 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1249 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1250 /* Initialize skew-specific constants */
1251 err = ei->get_invariants(hw);
1252 if (err)
1253 goto err_sw_init;
1254
1255 #ifdef CONFIG_PCI_IOV
1256 /* since iov functionality isn't critical to base device function we
1257 * can accept failure. If it fails we don't allow iov to be enabled */
1258 if (hw->mac.type == e1000_82576) {
1259 /* 82576 supports a maximum of 7 VFs in addition to the PF */
1260 unsigned int num_vfs = (max_vfs > 7) ? 7 : max_vfs;
1261 int i;
1262 unsigned char mac_addr[ETH_ALEN];
1263
1264 if (num_vfs)
1265 adapter->vf_data = kcalloc(num_vfs,
1266 sizeof(struct vf_data_storage),
1267 GFP_KERNEL);
1268 if (!adapter->vf_data) {
1269 dev_err(&pdev->dev, "Could not allocate VF private "
1270 "data - IOV enable failed\n");
1271 } else {
1272 err = pci_enable_sriov(pdev, num_vfs);
1273 if (!err) {
1274 adapter->vfs_allocated_count = num_vfs;
1275 dev_info(&pdev->dev, "%d vfs allocated\n", num_vfs);
1276 for (i = 0; i < adapter->vfs_allocated_count; i++) {
1277 random_ether_addr(mac_addr);
1278 igb_set_vf_mac(adapter, i, mac_addr);
1279 }
1280 } else {
1281 kfree(adapter->vf_data);
1282 adapter->vf_data = NULL;
1283 }
1284 }
1285 }
1286
1287 #endif
1288 /* setup the private structure */
1289 err = igb_sw_init(adapter);
1290 if (err)
1291 goto err_sw_init;
1292
1293 igb_get_bus_info_pcie(hw);
1294
1295 /* set flags */
1296 switch (hw->mac.type) {
1297 case e1000_82575:
1298 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1299 break;
1300 case e1000_82576:
1301 default:
1302 break;
1303 }
1304
1305 hw->phy.autoneg_wait_to_complete = false;
1306 hw->mac.adaptive_ifs = true;
1307
1308 /* Copper options */
1309 if (hw->phy.media_type == e1000_media_type_copper) {
1310 hw->phy.mdix = AUTO_ALL_MODES;
1311 hw->phy.disable_polarity_correction = false;
1312 hw->phy.ms_type = e1000_ms_hw_default;
1313 }
1314
1315 if (igb_check_reset_block(hw))
1316 dev_info(&pdev->dev,
1317 "PHY reset is blocked due to SOL/IDER session.\n");
1318
1319 netdev->features = NETIF_F_SG |
1320 NETIF_F_IP_CSUM |
1321 NETIF_F_HW_VLAN_TX |
1322 NETIF_F_HW_VLAN_RX |
1323 NETIF_F_HW_VLAN_FILTER;
1324
1325 netdev->features |= NETIF_F_IPV6_CSUM;
1326 netdev->features |= NETIF_F_TSO;
1327 netdev->features |= NETIF_F_TSO6;
1328
1329 netdev->features |= NETIF_F_GRO;
1330
1331 netdev->vlan_features |= NETIF_F_TSO;
1332 netdev->vlan_features |= NETIF_F_TSO6;
1333 netdev->vlan_features |= NETIF_F_IP_CSUM;
1334 netdev->vlan_features |= NETIF_F_SG;
1335
1336 if (pci_using_dac)
1337 netdev->features |= NETIF_F_HIGHDMA;
1338
1339 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1340
1341 /* before reading the NVM, reset the controller to put the device in a
1342 * known good starting state */
1343 hw->mac.ops.reset_hw(hw);
1344
1345 /* make sure the NVM is good */
1346 if (igb_validate_nvm_checksum(hw) < 0) {
1347 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1348 err = -EIO;
1349 goto err_eeprom;
1350 }
1351
1352 /* copy the MAC address out of the NVM */
1353 if (hw->mac.ops.read_mac_addr(hw))
1354 dev_err(&pdev->dev, "NVM Read Error\n");
1355
1356 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1357 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1358
1359 if (!is_valid_ether_addr(netdev->perm_addr)) {
1360 dev_err(&pdev->dev, "Invalid MAC Address\n");
1361 err = -EIO;
1362 goto err_eeprom;
1363 }
1364
1365 setup_timer(&adapter->watchdog_timer, &igb_watchdog,
1366 (unsigned long) adapter);
1367 setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
1368 (unsigned long) adapter);
1369
1370 INIT_WORK(&adapter->reset_task, igb_reset_task);
1371 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1372
1373 /* Initialize link properties that are user-changeable */
1374 adapter->fc_autoneg = true;
1375 hw->mac.autoneg = true;
1376 hw->phy.autoneg_advertised = 0x2f;
1377
1378 hw->fc.original_type = e1000_fc_default;
1379 hw->fc.type = e1000_fc_default;
1380
1381 adapter->itr_setting = IGB_DEFAULT_ITR;
1382 adapter->itr = IGB_START_ITR;
1383
1384 igb_validate_mdi_setting(hw);
1385
1386 adapter->rx_csum = 1;
1387
1388 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1389 * enable the ACPI Magic Packet filter
1390 */
1391
1392 if (hw->bus.func == 0)
1393 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
1394 else if (hw->bus.func == 1)
1395 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
1396
1397 if (eeprom_data & eeprom_apme_mask)
1398 adapter->eeprom_wol |= E1000_WUFC_MAG;
1399
1400 /* now that we have the eeprom settings, apply the special cases where
1401 * the eeprom may be wrong or the board simply won't support wake on
1402 * lan on a particular port */
1403 switch (pdev->device) {
1404 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1405 adapter->eeprom_wol = 0;
1406 break;
1407 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1408 case E1000_DEV_ID_82576_FIBER:
1409 case E1000_DEV_ID_82576_SERDES:
1410 /* Wake events only supported on port A for dual fiber
1411 * regardless of eeprom setting */
1412 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1413 adapter->eeprom_wol = 0;
1414 break;
1415 case E1000_DEV_ID_82576_QUAD_COPPER:
1416 /* if quad port adapter, disable WoL on all but port A */
1417 if (global_quad_port_a != 0)
1418 adapter->eeprom_wol = 0;
1419 else
1420 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1421 /* Reset for multiple quad port adapters */
1422 if (++global_quad_port_a == 4)
1423 global_quad_port_a = 0;
1424 break;
1425 }
1426
1427 /* initialize the wol settings based on the eeprom settings */
1428 adapter->wol = adapter->eeprom_wol;
1429 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1430
1431 /* reset the hardware with the new settings */
1432 igb_reset(adapter);
1433
1434 /* let the f/w know that the h/w is now under the control of the
1435 * driver. */
1436 igb_get_hw_control(adapter);
1437
1438 /* tell the stack to leave us alone until igb_open() is called */
1439 netif_carrier_off(netdev);
1440 netif_tx_stop_all_queues(netdev);
1441
1442 strcpy(netdev->name, "eth%d");
1443 err = register_netdev(netdev);
1444 if (err)
1445 goto err_register;
1446
1447 #ifdef CONFIG_IGB_DCA
1448 if (dca_add_requester(&pdev->dev) == 0) {
1449 adapter->flags |= IGB_FLAG_DCA_ENABLED;
1450 dev_info(&pdev->dev, "DCA enabled\n");
1451 /* Always use CB2 mode, difference is masked
1452 * in the CB driver. */
1453 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
1454 igb_setup_dca(adapter);
1455 }
1456 #endif
1457
1458 /*
1459 * Initialize hardware timer: we keep it running just in case
1460 * that some program needs it later on.
1461 */
1462 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1463 adapter->cycles.read = igb_read_clock;
1464 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1465 adapter->cycles.mult = 1;
1466 adapter->cycles.shift = IGB_TSYNC_SHIFT;
1467 wr32(E1000_TIMINCA,
1468 (1<<24) |
1469 IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1470 #if 0
1471 /*
1472 * Avoid rollover while we initialize by resetting the time counter.
1473 */
1474 wr32(E1000_SYSTIML, 0x00000000);
1475 wr32(E1000_SYSTIMH, 0x00000000);
1476 #else
1477 /*
1478 * Set registers so that rollover occurs soon to test this.
1479 */
1480 wr32(E1000_SYSTIML, 0x00000000);
1481 wr32(E1000_SYSTIMH, 0xFF800000);
1482 #endif
1483 wrfl();
1484 timecounter_init(&adapter->clock,
1485 &adapter->cycles,
1486 ktime_to_ns(ktime_get_real()));
1487
1488 /*
1489 * Synchronize our NIC clock against system wall clock. NIC
1490 * time stamp reading requires ~3us per sample, each sample
1491 * was pretty stable even under load => only require 10
1492 * samples for each offset comparison.
1493 */
1494 memset(&adapter->compare, 0, sizeof(adapter->compare));
1495 adapter->compare.source = &adapter->clock;
1496 adapter->compare.target = ktime_get_real;
1497 adapter->compare.num_samples = 10;
1498 timecompare_update(&adapter->compare, 0);
1499
1500 #ifdef DEBUG
1501 {
1502 char buffer[160];
1503 printk(KERN_DEBUG
1504 "igb: %s: hw %p initialized timer\n",
1505 igb_get_time_str(adapter, buffer),
1506 &adapter->hw);
1507 }
1508 #endif
1509
1510 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1511 /* print bus type/speed/width info */
1512 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
1513 netdev->name,
1514 ((hw->bus.speed == e1000_bus_speed_2500)
1515 ? "2.5Gb/s" : "unknown"),
1516 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1517 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1518 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1519 "unknown"),
1520 netdev->dev_addr);
1521
1522 igb_read_part_num(hw, &part_num);
1523 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1524 (part_num >> 8), (part_num & 0xff));
1525
1526 dev_info(&pdev->dev,
1527 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1528 adapter->msix_entries ? "MSI-X" :
1529 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
1530 adapter->num_rx_queues, adapter->num_tx_queues);
1531
1532 return 0;
1533
1534 err_register:
1535 igb_release_hw_control(adapter);
1536 err_eeprom:
1537 if (!igb_check_reset_block(hw))
1538 igb_reset_phy(hw);
1539
1540 if (hw->flash_address)
1541 iounmap(hw->flash_address);
1542
1543 igb_free_queues(adapter);
1544 err_sw_init:
1545 iounmap(hw->hw_addr);
1546 err_ioremap:
1547 free_netdev(netdev);
1548 err_alloc_etherdev:
1549 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1550 IORESOURCE_MEM));
1551 err_pci_reg:
1552 err_dma:
1553 pci_disable_device(pdev);
1554 return err;
1555 }
1556
1557 /**
1558 * igb_remove - Device Removal Routine
1559 * @pdev: PCI device information struct
1560 *
1561 * igb_remove is called by the PCI subsystem to alert the driver
1562 * that it should release a PCI device. The could be caused by a
1563 * Hot-Plug event, or because the driver is going to be removed from
1564 * memory.
1565 **/
1566 static void __devexit igb_remove(struct pci_dev *pdev)
1567 {
1568 struct net_device *netdev = pci_get_drvdata(pdev);
1569 struct igb_adapter *adapter = netdev_priv(netdev);
1570 struct e1000_hw *hw = &adapter->hw;
1571 int err;
1572
1573 /* flush_scheduled work may reschedule our watchdog task, so
1574 * explicitly disable watchdog tasks from being rescheduled */
1575 set_bit(__IGB_DOWN, &adapter->state);
1576 del_timer_sync(&adapter->watchdog_timer);
1577 del_timer_sync(&adapter->phy_info_timer);
1578
1579 flush_scheduled_work();
1580
1581 #ifdef CONFIG_IGB_DCA
1582 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
1583 dev_info(&pdev->dev, "DCA disabled\n");
1584 dca_remove_requester(&pdev->dev);
1585 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
1586 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
1587 }
1588 #endif
1589
1590 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1591 * would have already happened in close and is redundant. */
1592 igb_release_hw_control(adapter);
1593
1594 unregister_netdev(netdev);
1595
1596 if (!igb_check_reset_block(&adapter->hw))
1597 igb_reset_phy(&adapter->hw);
1598
1599 igb_reset_interrupt_capability(adapter);
1600
1601 igb_free_queues(adapter);
1602
1603 #ifdef CONFIG_PCI_IOV
1604 /* reclaim resources allocated to VFs */
1605 if (adapter->vf_data) {
1606 /* disable iov and allow time for transactions to clear */
1607 pci_disable_sriov(pdev);
1608 msleep(500);
1609
1610 kfree(adapter->vf_data);
1611 adapter->vf_data = NULL;
1612 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1613 msleep(100);
1614 dev_info(&pdev->dev, "IOV Disabled\n");
1615 }
1616 #endif
1617 iounmap(hw->hw_addr);
1618 if (hw->flash_address)
1619 iounmap(hw->flash_address);
1620 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1621 IORESOURCE_MEM));
1622
1623 free_netdev(netdev);
1624
1625 err = pci_disable_pcie_error_reporting(pdev);
1626 if (err)
1627 dev_err(&pdev->dev,
1628 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
1629
1630 pci_disable_device(pdev);
1631 }
1632
1633 /**
1634 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1635 * @adapter: board private structure to initialize
1636 *
1637 * igb_sw_init initializes the Adapter private data structure.
1638 * Fields are initialized based on PCI device information and
1639 * OS network device settings (MTU size).
1640 **/
1641 static int __devinit igb_sw_init(struct igb_adapter *adapter)
1642 {
1643 struct e1000_hw *hw = &adapter->hw;
1644 struct net_device *netdev = adapter->netdev;
1645 struct pci_dev *pdev = adapter->pdev;
1646
1647 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1648
1649 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1650 adapter->rx_ring_count = IGB_DEFAULT_RXD;
1651 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1652 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1653 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1654 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1655
1656 /* This call may decrease the number of queues depending on
1657 * interrupt mode. */
1658 igb_set_interrupt_capability(adapter);
1659
1660 if (igb_alloc_queues(adapter)) {
1661 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1662 return -ENOMEM;
1663 }
1664
1665 /* Explicitly disable IRQ since the NIC can be in any state. */
1666 igb_irq_disable(adapter);
1667
1668 set_bit(__IGB_DOWN, &adapter->state);
1669 return 0;
1670 }
1671
1672 /**
1673 * igb_open - Called when a network interface is made active
1674 * @netdev: network interface device structure
1675 *
1676 * Returns 0 on success, negative value on failure
1677 *
1678 * The open entry point is called when a network interface is made
1679 * active by the system (IFF_UP). At this point all resources needed
1680 * for transmit and receive operations are allocated, the interrupt
1681 * handler is registered with the OS, the watchdog timer is started,
1682 * and the stack is notified that the interface is ready.
1683 **/
1684 static int igb_open(struct net_device *netdev)
1685 {
1686 struct igb_adapter *adapter = netdev_priv(netdev);
1687 struct e1000_hw *hw = &adapter->hw;
1688 int err;
1689 int i;
1690
1691 /* disallow open during test */
1692 if (test_bit(__IGB_TESTING, &adapter->state))
1693 return -EBUSY;
1694
1695 /* allocate transmit descriptors */
1696 err = igb_setup_all_tx_resources(adapter);
1697 if (err)
1698 goto err_setup_tx;
1699
1700 /* allocate receive descriptors */
1701 err = igb_setup_all_rx_resources(adapter);
1702 if (err)
1703 goto err_setup_rx;
1704
1705 /* e1000_power_up_phy(adapter); */
1706
1707 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1708 if ((adapter->hw.mng_cookie.status &
1709 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1710 igb_update_mng_vlan(adapter);
1711
1712 /* before we allocate an interrupt, we must be ready to handle it.
1713 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1714 * as soon as we call pci_request_irq, so we have to setup our
1715 * clean_rx handler before we do so. */
1716 igb_configure(adapter);
1717
1718 igb_vmm_control(adapter);
1719 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
1720 igb_set_vmolr(hw, adapter->vfs_allocated_count);
1721
1722 err = igb_request_irq(adapter);
1723 if (err)
1724 goto err_req_irq;
1725
1726 /* From here on the code is the same as igb_up() */
1727 clear_bit(__IGB_DOWN, &adapter->state);
1728
1729 for (i = 0; i < adapter->num_rx_queues; i++)
1730 napi_enable(&adapter->rx_ring[i].napi);
1731
1732 /* Clear any pending interrupts. */
1733 rd32(E1000_ICR);
1734
1735 igb_irq_enable(adapter);
1736
1737 netif_tx_start_all_queues(netdev);
1738
1739 /* Fire a link status change interrupt to start the watchdog. */
1740 wr32(E1000_ICS, E1000_ICS_LSC);
1741
1742 return 0;
1743
1744 err_req_irq:
1745 igb_release_hw_control(adapter);
1746 /* e1000_power_down_phy(adapter); */
1747 igb_free_all_rx_resources(adapter);
1748 err_setup_rx:
1749 igb_free_all_tx_resources(adapter);
1750 err_setup_tx:
1751 igb_reset(adapter);
1752
1753 return err;
1754 }
1755
1756 /**
1757 * igb_close - Disables a network interface
1758 * @netdev: network interface device structure
1759 *
1760 * Returns 0, this is not allowed to fail
1761 *
1762 * The close entry point is called when an interface is de-activated
1763 * by the OS. The hardware is still under the driver's control, but
1764 * needs to be disabled. A global MAC reset is issued to stop the
1765 * hardware, and all transmit and receive resources are freed.
1766 **/
1767 static int igb_close(struct net_device *netdev)
1768 {
1769 struct igb_adapter *adapter = netdev_priv(netdev);
1770
1771 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1772 igb_down(adapter);
1773
1774 igb_free_irq(adapter);
1775
1776 igb_free_all_tx_resources(adapter);
1777 igb_free_all_rx_resources(adapter);
1778
1779 /* kill manageability vlan ID if supported, but not if a vlan with
1780 * the same ID is registered on the host OS (let 8021q kill it) */
1781 if ((adapter->hw.mng_cookie.status &
1782 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1783 !(adapter->vlgrp &&
1784 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1785 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1786
1787 return 0;
1788 }
1789
1790 /**
1791 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1792 * @adapter: board private structure
1793 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1794 *
1795 * Return 0 on success, negative on failure
1796 **/
1797 int igb_setup_tx_resources(struct igb_adapter *adapter,
1798 struct igb_ring *tx_ring)
1799 {
1800 struct pci_dev *pdev = adapter->pdev;
1801 int size;
1802
1803 size = sizeof(struct igb_buffer) * tx_ring->count;
1804 tx_ring->buffer_info = vmalloc(size);
1805 if (!tx_ring->buffer_info)
1806 goto err;
1807 memset(tx_ring->buffer_info, 0, size);
1808
1809 /* round up to nearest 4K */
1810 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
1811 tx_ring->size = ALIGN(tx_ring->size, 4096);
1812
1813 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1814 &tx_ring->dma);
1815
1816 if (!tx_ring->desc)
1817 goto err;
1818
1819 tx_ring->adapter = adapter;
1820 tx_ring->next_to_use = 0;
1821 tx_ring->next_to_clean = 0;
1822 return 0;
1823
1824 err:
1825 vfree(tx_ring->buffer_info);
1826 dev_err(&adapter->pdev->dev,
1827 "Unable to allocate memory for the transmit descriptor ring\n");
1828 return -ENOMEM;
1829 }
1830
1831 /**
1832 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1833 * (Descriptors) for all queues
1834 * @adapter: board private structure
1835 *
1836 * Return 0 on success, negative on failure
1837 **/
1838 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1839 {
1840 int i, err = 0;
1841 int r_idx;
1842
1843 for (i = 0; i < adapter->num_tx_queues; i++) {
1844 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1845 if (err) {
1846 dev_err(&adapter->pdev->dev,
1847 "Allocation for Tx Queue %u failed\n", i);
1848 for (i--; i >= 0; i--)
1849 igb_free_tx_resources(&adapter->tx_ring[i]);
1850 break;
1851 }
1852 }
1853
1854 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1855 r_idx = i % adapter->num_tx_queues;
1856 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1857 }
1858 return err;
1859 }
1860
1861 /**
1862 * igb_configure_tx - Configure transmit Unit after Reset
1863 * @adapter: board private structure
1864 *
1865 * Configure the Tx unit of the MAC after a reset.
1866 **/
1867 static void igb_configure_tx(struct igb_adapter *adapter)
1868 {
1869 u64 tdba;
1870 struct e1000_hw *hw = &adapter->hw;
1871 u32 tctl;
1872 u32 txdctl, txctrl;
1873 int i, j;
1874
1875 for (i = 0; i < adapter->num_tx_queues; i++) {
1876 struct igb_ring *ring = &adapter->tx_ring[i];
1877 j = ring->reg_idx;
1878 wr32(E1000_TDLEN(j),
1879 ring->count * sizeof(union e1000_adv_tx_desc));
1880 tdba = ring->dma;
1881 wr32(E1000_TDBAL(j),
1882 tdba & 0x00000000ffffffffULL);
1883 wr32(E1000_TDBAH(j), tdba >> 32);
1884
1885 ring->head = E1000_TDH(j);
1886 ring->tail = E1000_TDT(j);
1887 writel(0, hw->hw_addr + ring->tail);
1888 writel(0, hw->hw_addr + ring->head);
1889 txdctl = rd32(E1000_TXDCTL(j));
1890 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1891 wr32(E1000_TXDCTL(j), txdctl);
1892
1893 /* Turn off Relaxed Ordering on head write-backs. The
1894 * writebacks MUST be delivered in order or it will
1895 * completely screw up our bookeeping.
1896 */
1897 txctrl = rd32(E1000_DCA_TXCTRL(j));
1898 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1899 wr32(E1000_DCA_TXCTRL(j), txctrl);
1900 }
1901
1902 /* disable queue 0 to prevent tail bump w/o re-configuration */
1903 if (adapter->vfs_allocated_count)
1904 wr32(E1000_TXDCTL(0), 0);
1905
1906 /* Program the Transmit Control Register */
1907 tctl = rd32(E1000_TCTL);
1908 tctl &= ~E1000_TCTL_CT;
1909 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1910 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1911
1912 igb_config_collision_dist(hw);
1913
1914 /* Setup Transmit Descriptor Settings for eop descriptor */
1915 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1916
1917 /* Enable transmits */
1918 tctl |= E1000_TCTL_EN;
1919
1920 wr32(E1000_TCTL, tctl);
1921 }
1922
1923 /**
1924 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1925 * @adapter: board private structure
1926 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1927 *
1928 * Returns 0 on success, negative on failure
1929 **/
1930 int igb_setup_rx_resources(struct igb_adapter *adapter,
1931 struct igb_ring *rx_ring)
1932 {
1933 struct pci_dev *pdev = adapter->pdev;
1934 int size, desc_len;
1935
1936 size = sizeof(struct igb_buffer) * rx_ring->count;
1937 rx_ring->buffer_info = vmalloc(size);
1938 if (!rx_ring->buffer_info)
1939 goto err;
1940 memset(rx_ring->buffer_info, 0, size);
1941
1942 desc_len = sizeof(union e1000_adv_rx_desc);
1943
1944 /* Round up to nearest 4K */
1945 rx_ring->size = rx_ring->count * desc_len;
1946 rx_ring->size = ALIGN(rx_ring->size, 4096);
1947
1948 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1949 &rx_ring->dma);
1950
1951 if (!rx_ring->desc)
1952 goto err;
1953
1954 rx_ring->next_to_clean = 0;
1955 rx_ring->next_to_use = 0;
1956
1957 rx_ring->adapter = adapter;
1958
1959 return 0;
1960
1961 err:
1962 vfree(rx_ring->buffer_info);
1963 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1964 "the receive descriptor ring\n");
1965 return -ENOMEM;
1966 }
1967
1968 /**
1969 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1970 * (Descriptors) for all queues
1971 * @adapter: board private structure
1972 *
1973 * Return 0 on success, negative on failure
1974 **/
1975 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1976 {
1977 int i, err = 0;
1978
1979 for (i = 0; i < adapter->num_rx_queues; i++) {
1980 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1981 if (err) {
1982 dev_err(&adapter->pdev->dev,
1983 "Allocation for Rx Queue %u failed\n", i);
1984 for (i--; i >= 0; i--)
1985 igb_free_rx_resources(&adapter->rx_ring[i]);
1986 break;
1987 }
1988 }
1989
1990 return err;
1991 }
1992
1993 /**
1994 * igb_setup_rctl - configure the receive control registers
1995 * @adapter: Board private structure
1996 **/
1997 static void igb_setup_rctl(struct igb_adapter *adapter)
1998 {
1999 struct e1000_hw *hw = &adapter->hw;
2000 u32 rctl;
2001 u32 srrctl = 0;
2002 int i, j;
2003
2004 rctl = rd32(E1000_RCTL);
2005
2006 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2007 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
2008
2009 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
2010 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2011
2012 /*
2013 * enable stripping of CRC. It's unlikely this will break BMC
2014 * redirection as it did with e1000. Newer features require
2015 * that the HW strips the CRC.
2016 */
2017 rctl |= E1000_RCTL_SECRC;
2018
2019 /*
2020 * disable store bad packets and clear size bits.
2021 */
2022 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
2023
2024 /* enable LPE when to prevent packets larger than max_frame_size */
2025 rctl |= E1000_RCTL_LPE;
2026
2027 /* Setup buffer sizes */
2028 switch (adapter->rx_buffer_len) {
2029 case IGB_RXBUFFER_256:
2030 rctl |= E1000_RCTL_SZ_256;
2031 break;
2032 case IGB_RXBUFFER_512:
2033 rctl |= E1000_RCTL_SZ_512;
2034 break;
2035 default:
2036 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
2037 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2038 break;
2039 }
2040
2041 /* 82575 and greater support packet-split where the protocol
2042 * header is placed in skb->data and the packet data is
2043 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2044 * In the case of a non-split, skb->data is linearly filled,
2045 * followed by the page buffers. Therefore, skb->data is
2046 * sized to hold the largest protocol header.
2047 */
2048 /* allocations using alloc_page take too long for regular MTU
2049 * so only enable packet split for jumbo frames */
2050 if (adapter->netdev->mtu > ETH_DATA_LEN) {
2051 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
2052 srrctl |= adapter->rx_ps_hdr_size <<
2053 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2054 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2055 } else {
2056 adapter->rx_ps_hdr_size = 0;
2057 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2058 }
2059
2060 /* Attention!!! For SR-IOV PF driver operations you must enable
2061 * queue drop for all VF and PF queues to prevent head of line blocking
2062 * if an un-trusted VF does not provide descriptors to hardware.
2063 */
2064 if (adapter->vfs_allocated_count) {
2065 u32 vmolr;
2066
2067 j = adapter->rx_ring[0].reg_idx;
2068
2069 /* set all queue drop enable bits */
2070 wr32(E1000_QDE, ALL_QUEUES);
2071 srrctl |= E1000_SRRCTL_DROP_EN;
2072
2073 /* disable queue 0 to prevent tail write w/o re-config */
2074 wr32(E1000_RXDCTL(0), 0);
2075
2076 vmolr = rd32(E1000_VMOLR(j));
2077 if (rctl & E1000_RCTL_LPE)
2078 vmolr |= E1000_VMOLR_LPE;
2079 if (adapter->num_rx_queues > 0)
2080 vmolr |= E1000_VMOLR_RSSE;
2081 wr32(E1000_VMOLR(j), vmolr);
2082 }
2083
2084 for (i = 0; i < adapter->num_rx_queues; i++) {
2085 j = adapter->rx_ring[i].reg_idx;
2086 wr32(E1000_SRRCTL(j), srrctl);
2087 }
2088
2089 wr32(E1000_RCTL, rctl);
2090 }
2091
2092 /**
2093 * igb_rlpml_set - set maximum receive packet size
2094 * @adapter: board private structure
2095 *
2096 * Configure maximum receivable packet size.
2097 **/
2098 static void igb_rlpml_set(struct igb_adapter *adapter)
2099 {
2100 u32 max_frame_size = adapter->max_frame_size;
2101 struct e1000_hw *hw = &adapter->hw;
2102 u16 pf_id = adapter->vfs_allocated_count;
2103
2104 if (adapter->vlgrp)
2105 max_frame_size += VLAN_TAG_SIZE;
2106
2107 /* if vfs are enabled we set RLPML to the largest possible request
2108 * size and set the VMOLR RLPML to the size we need */
2109 if (pf_id) {
2110 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2111 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2112 }
2113
2114 wr32(E1000_RLPML, max_frame_size);
2115 }
2116
2117 /**
2118 * igb_configure_vt_default_pool - Configure VT default pool
2119 * @adapter: board private structure
2120 *
2121 * Configure the default pool
2122 **/
2123 static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2124 {
2125 struct e1000_hw *hw = &adapter->hw;
2126 u16 pf_id = adapter->vfs_allocated_count;
2127 u32 vtctl;
2128
2129 /* not in sr-iov mode - do nothing */
2130 if (!pf_id)
2131 return;
2132
2133 vtctl = rd32(E1000_VT_CTL);
2134 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2135 E1000_VT_CTL_DISABLE_DEF_POOL);
2136 vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2137 wr32(E1000_VT_CTL, vtctl);
2138 }
2139
2140 /**
2141 * igb_configure_rx - Configure receive Unit after Reset
2142 * @adapter: board private structure
2143 *
2144 * Configure the Rx unit of the MAC after a reset.
2145 **/
2146 static void igb_configure_rx(struct igb_adapter *adapter)
2147 {
2148 u64 rdba;
2149 struct e1000_hw *hw = &adapter->hw;
2150 u32 rctl, rxcsum;
2151 u32 rxdctl;
2152 int i;
2153
2154 /* disable receives while setting up the descriptors */
2155 rctl = rd32(E1000_RCTL);
2156 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2157 wrfl();
2158 mdelay(10);
2159
2160 if (adapter->itr_setting > 3)
2161 wr32(E1000_ITR, adapter->itr);
2162
2163 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2164 * the Base and Length of the Rx Descriptor Ring */
2165 for (i = 0; i < adapter->num_rx_queues; i++) {
2166 struct igb_ring *ring = &adapter->rx_ring[i];
2167 int j = ring->reg_idx;
2168 rdba = ring->dma;
2169 wr32(E1000_RDBAL(j),
2170 rdba & 0x00000000ffffffffULL);
2171 wr32(E1000_RDBAH(j), rdba >> 32);
2172 wr32(E1000_RDLEN(j),
2173 ring->count * sizeof(union e1000_adv_rx_desc));
2174
2175 ring->head = E1000_RDH(j);
2176 ring->tail = E1000_RDT(j);
2177 writel(0, hw->hw_addr + ring->tail);
2178 writel(0, hw->hw_addr + ring->head);
2179
2180 rxdctl = rd32(E1000_RXDCTL(j));
2181 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2182 rxdctl &= 0xFFF00000;
2183 rxdctl |= IGB_RX_PTHRESH;
2184 rxdctl |= IGB_RX_HTHRESH << 8;
2185 rxdctl |= IGB_RX_WTHRESH << 16;
2186 wr32(E1000_RXDCTL(j), rxdctl);
2187 }
2188
2189 if (adapter->num_rx_queues > 1) {
2190 u32 random[10];
2191 u32 mrqc;
2192 u32 j, shift;
2193 union e1000_reta {
2194 u32 dword;
2195 u8 bytes[4];
2196 } reta;
2197
2198 get_random_bytes(&random[0], 40);
2199
2200 if (hw->mac.type >= e1000_82576)
2201 shift = 0;
2202 else
2203 shift = 6;
2204 for (j = 0; j < (32 * 4); j++) {
2205 reta.bytes[j & 3] =
2206 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
2207 if ((j & 3) == 3)
2208 writel(reta.dword,
2209 hw->hw_addr + E1000_RETA(0) + (j & ~3));
2210 }
2211 if (adapter->vfs_allocated_count)
2212 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2213 else
2214 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2215
2216 /* Fill out hash function seeds */
2217 for (j = 0; j < 10; j++)
2218 array_wr32(E1000_RSSRK(0), j, random[j]);
2219
2220 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2221 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2222 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2223 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2224 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2225 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2226 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2227 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2228
2229
2230 wr32(E1000_MRQC, mrqc);
2231
2232 /* Multiqueue and raw packet checksumming are mutually
2233 * exclusive. Note that this not the same as TCP/IP
2234 * checksumming, which works fine. */
2235 rxcsum = rd32(E1000_RXCSUM);
2236 rxcsum |= E1000_RXCSUM_PCSD;
2237 wr32(E1000_RXCSUM, rxcsum);
2238 } else {
2239 /* Enable multi-queue for sr-iov */
2240 if (adapter->vfs_allocated_count)
2241 wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
2242 /* Enable Receive Checksum Offload for TCP and UDP */
2243 rxcsum = rd32(E1000_RXCSUM);
2244 if (adapter->rx_csum)
2245 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE;
2246 else
2247 rxcsum &= ~(E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE);
2248
2249 wr32(E1000_RXCSUM, rxcsum);
2250 }
2251
2252 /* Set the default pool for the PF's first queue */
2253 igb_configure_vt_default_pool(adapter);
2254
2255 igb_rlpml_set(adapter);
2256
2257 /* Enable Receives */
2258 wr32(E1000_RCTL, rctl);
2259 }
2260
2261 /**
2262 * igb_free_tx_resources - Free Tx Resources per Queue
2263 * @tx_ring: Tx descriptor ring for a specific queue
2264 *
2265 * Free all transmit software resources
2266 **/
2267 void igb_free_tx_resources(struct igb_ring *tx_ring)
2268 {
2269 struct pci_dev *pdev = tx_ring->adapter->pdev;
2270
2271 igb_clean_tx_ring(tx_ring);
2272
2273 vfree(tx_ring->buffer_info);
2274 tx_ring->buffer_info = NULL;
2275
2276 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2277
2278 tx_ring->desc = NULL;
2279 }
2280
2281 /**
2282 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2283 * @adapter: board private structure
2284 *
2285 * Free all transmit software resources
2286 **/
2287 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2288 {
2289 int i;
2290
2291 for (i = 0; i < adapter->num_tx_queues; i++)
2292 igb_free_tx_resources(&adapter->tx_ring[i]);
2293 }
2294
2295 static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2296 struct igb_buffer *buffer_info)
2297 {
2298 buffer_info->dma = 0;
2299 if (buffer_info->skb) {
2300 skb_dma_unmap(&adapter->pdev->dev, buffer_info->skb,
2301 DMA_TO_DEVICE);
2302 dev_kfree_skb_any(buffer_info->skb);
2303 buffer_info->skb = NULL;
2304 }
2305 buffer_info->time_stamp = 0;
2306 /* buffer_info must be completely set up in the transmit path */
2307 }
2308
2309 /**
2310 * igb_clean_tx_ring - Free Tx Buffers
2311 * @tx_ring: ring to be cleaned
2312 **/
2313 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
2314 {
2315 struct igb_adapter *adapter = tx_ring->adapter;
2316 struct igb_buffer *buffer_info;
2317 unsigned long size;
2318 unsigned int i;
2319
2320 if (!tx_ring->buffer_info)
2321 return;
2322 /* Free all the Tx ring sk_buffs */
2323
2324 for (i = 0; i < tx_ring->count; i++) {
2325 buffer_info = &tx_ring->buffer_info[i];
2326 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2327 }
2328
2329 size = sizeof(struct igb_buffer) * tx_ring->count;
2330 memset(tx_ring->buffer_info, 0, size);
2331
2332 /* Zero out the descriptor ring */
2333
2334 memset(tx_ring->desc, 0, tx_ring->size);
2335
2336 tx_ring->next_to_use = 0;
2337 tx_ring->next_to_clean = 0;
2338
2339 writel(0, adapter->hw.hw_addr + tx_ring->head);
2340 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2341 }
2342
2343 /**
2344 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2345 * @adapter: board private structure
2346 **/
2347 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2348 {
2349 int i;
2350
2351 for (i = 0; i < adapter->num_tx_queues; i++)
2352 igb_clean_tx_ring(&adapter->tx_ring[i]);
2353 }
2354
2355 /**
2356 * igb_free_rx_resources - Free Rx Resources
2357 * @rx_ring: ring to clean the resources from
2358 *
2359 * Free all receive software resources
2360 **/
2361 void igb_free_rx_resources(struct igb_ring *rx_ring)
2362 {
2363 struct pci_dev *pdev = rx_ring->adapter->pdev;
2364
2365 igb_clean_rx_ring(rx_ring);
2366
2367 vfree(rx_ring->buffer_info);
2368 rx_ring->buffer_info = NULL;
2369
2370 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2371
2372 rx_ring->desc = NULL;
2373 }
2374
2375 /**
2376 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2377 * @adapter: board private structure
2378 *
2379 * Free all receive software resources
2380 **/
2381 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2382 {
2383 int i;
2384
2385 for (i = 0; i < adapter->num_rx_queues; i++)
2386 igb_free_rx_resources(&adapter->rx_ring[i]);
2387 }
2388
2389 /**
2390 * igb_clean_rx_ring - Free Rx Buffers per Queue
2391 * @rx_ring: ring to free buffers from
2392 **/
2393 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
2394 {
2395 struct igb_adapter *adapter = rx_ring->adapter;
2396 struct igb_buffer *buffer_info;
2397 struct pci_dev *pdev = adapter->pdev;
2398 unsigned long size;
2399 unsigned int i;
2400
2401 if (!rx_ring->buffer_info)
2402 return;
2403 /* Free all the Rx ring sk_buffs */
2404 for (i = 0; i < rx_ring->count; i++) {
2405 buffer_info = &rx_ring->buffer_info[i];
2406 if (buffer_info->dma) {
2407 if (adapter->rx_ps_hdr_size)
2408 pci_unmap_single(pdev, buffer_info->dma,
2409 adapter->rx_ps_hdr_size,
2410 PCI_DMA_FROMDEVICE);
2411 else
2412 pci_unmap_single(pdev, buffer_info->dma,
2413 adapter->rx_buffer_len,
2414 PCI_DMA_FROMDEVICE);
2415 buffer_info->dma = 0;
2416 }
2417
2418 if (buffer_info->skb) {
2419 dev_kfree_skb(buffer_info->skb);
2420 buffer_info->skb = NULL;
2421 }
2422 if (buffer_info->page) {
2423 if (buffer_info->page_dma)
2424 pci_unmap_page(pdev, buffer_info->page_dma,
2425 PAGE_SIZE / 2,
2426 PCI_DMA_FROMDEVICE);
2427 put_page(buffer_info->page);
2428 buffer_info->page = NULL;
2429 buffer_info->page_dma = 0;
2430 buffer_info->page_offset = 0;
2431 }
2432 }
2433
2434 size = sizeof(struct igb_buffer) * rx_ring->count;
2435 memset(rx_ring->buffer_info, 0, size);
2436
2437 /* Zero out the descriptor ring */
2438 memset(rx_ring->desc, 0, rx_ring->size);
2439
2440 rx_ring->next_to_clean = 0;
2441 rx_ring->next_to_use = 0;
2442
2443 writel(0, adapter->hw.hw_addr + rx_ring->head);
2444 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2445 }
2446
2447 /**
2448 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2449 * @adapter: board private structure
2450 **/
2451 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2452 {
2453 int i;
2454
2455 for (i = 0; i < adapter->num_rx_queues; i++)
2456 igb_clean_rx_ring(&adapter->rx_ring[i]);
2457 }
2458
2459 /**
2460 * igb_set_mac - Change the Ethernet Address of the NIC
2461 * @netdev: network interface device structure
2462 * @p: pointer to an address structure
2463 *
2464 * Returns 0 on success, negative on failure
2465 **/
2466 static int igb_set_mac(struct net_device *netdev, void *p)
2467 {
2468 struct igb_adapter *adapter = netdev_priv(netdev);
2469 struct e1000_hw *hw = &adapter->hw;
2470 struct sockaddr *addr = p;
2471
2472 if (!is_valid_ether_addr(addr->sa_data))
2473 return -EADDRNOTAVAIL;
2474
2475 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2476 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
2477
2478 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
2479
2480 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
2481
2482 return 0;
2483 }
2484
2485 /**
2486 * igb_set_multi - Multicast and Promiscuous mode set
2487 * @netdev: network interface device structure
2488 *
2489 * The set_multi entry point is called whenever the multicast address
2490 * list or the network interface flags are updated. This routine is
2491 * responsible for configuring the hardware for proper multicast,
2492 * promiscuous mode, and all-multi behavior.
2493 **/
2494 static void igb_set_multi(struct net_device *netdev)
2495 {
2496 struct igb_adapter *adapter = netdev_priv(netdev);
2497 struct e1000_hw *hw = &adapter->hw;
2498 struct e1000_mac_info *mac = &hw->mac;
2499 struct dev_mc_list *mc_ptr;
2500 u8 *mta_list = NULL;
2501 u32 rctl;
2502 int i;
2503
2504 /* Check for Promiscuous and All Multicast modes */
2505
2506 rctl = rd32(E1000_RCTL);
2507
2508 if (netdev->flags & IFF_PROMISC) {
2509 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2510 rctl &= ~E1000_RCTL_VFE;
2511 } else {
2512 if (netdev->flags & IFF_ALLMULTI) {
2513 rctl |= E1000_RCTL_MPE;
2514 rctl &= ~E1000_RCTL_UPE;
2515 } else
2516 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2517 rctl |= E1000_RCTL_VFE;
2518 }
2519 wr32(E1000_RCTL, rctl);
2520
2521 if (netdev->mc_count) {
2522 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2523 if (!mta_list) {
2524 dev_err(&adapter->pdev->dev,
2525 "failed to allocate multicast filter list\n");
2526 return;
2527 }
2528 }
2529
2530 /* The shared function expects a packed array of only addresses. */
2531 mc_ptr = netdev->mc_list;
2532
2533 for (i = 0; i < netdev->mc_count; i++) {
2534 if (!mc_ptr)
2535 break;
2536 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2537 mc_ptr = mc_ptr->next;
2538 }
2539 igb_update_mc_addr_list(hw, mta_list, i,
2540 adapter->vfs_allocated_count + 1,
2541 mac->rar_entry_count);
2542
2543 igb_set_mc_list_pools(adapter, i, mac->rar_entry_count);
2544 igb_restore_vf_multicasts(adapter);
2545
2546 kfree(mta_list);
2547 }
2548
2549 /* Need to wait a few seconds after link up to get diagnostic information from
2550 * the phy */
2551 static void igb_update_phy_info(unsigned long data)
2552 {
2553 struct igb_adapter *adapter = (struct igb_adapter *) data;
2554 igb_get_phy_info(&adapter->hw);
2555 }
2556
2557 /**
2558 * igb_has_link - check shared code for link and determine up/down
2559 * @adapter: pointer to driver private info
2560 **/
2561 static bool igb_has_link(struct igb_adapter *adapter)
2562 {
2563 struct e1000_hw *hw = &adapter->hw;
2564 bool link_active = false;
2565 s32 ret_val = 0;
2566
2567 /* get_link_status is set on LSC (link status) interrupt or
2568 * rx sequence error interrupt. get_link_status will stay
2569 * false until the e1000_check_for_link establishes link
2570 * for copper adapters ONLY
2571 */
2572 switch (hw->phy.media_type) {
2573 case e1000_media_type_copper:
2574 if (hw->mac.get_link_status) {
2575 ret_val = hw->mac.ops.check_for_link(hw);
2576 link_active = !hw->mac.get_link_status;
2577 } else {
2578 link_active = true;
2579 }
2580 break;
2581 case e1000_media_type_fiber:
2582 ret_val = hw->mac.ops.check_for_link(hw);
2583 link_active = !!(rd32(E1000_STATUS) & E1000_STATUS_LU);
2584 break;
2585 case e1000_media_type_internal_serdes:
2586 ret_val = hw->mac.ops.check_for_link(hw);
2587 link_active = hw->mac.serdes_has_link;
2588 break;
2589 default:
2590 case e1000_media_type_unknown:
2591 break;
2592 }
2593
2594 return link_active;
2595 }
2596
2597 /**
2598 * igb_watchdog - Timer Call-back
2599 * @data: pointer to adapter cast into an unsigned long
2600 **/
2601 static void igb_watchdog(unsigned long data)
2602 {
2603 struct igb_adapter *adapter = (struct igb_adapter *)data;
2604 /* Do the rest outside of interrupt context */
2605 schedule_work(&adapter->watchdog_task);
2606 }
2607
2608 static void igb_watchdog_task(struct work_struct *work)
2609 {
2610 struct igb_adapter *adapter = container_of(work,
2611 struct igb_adapter, watchdog_task);
2612 struct e1000_hw *hw = &adapter->hw;
2613 struct net_device *netdev = adapter->netdev;
2614 struct igb_ring *tx_ring = adapter->tx_ring;
2615 u32 link;
2616 u32 eics = 0;
2617 int i;
2618
2619 link = igb_has_link(adapter);
2620 if ((netif_carrier_ok(netdev)) && link)
2621 goto link_up;
2622
2623 if (link) {
2624 if (!netif_carrier_ok(netdev)) {
2625 u32 ctrl;
2626 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2627 &adapter->link_speed,
2628 &adapter->link_duplex);
2629
2630 ctrl = rd32(E1000_CTRL);
2631 /* Links status message must follow this format */
2632 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
2633 "Flow Control: %s\n",
2634 netdev->name,
2635 adapter->link_speed,
2636 adapter->link_duplex == FULL_DUPLEX ?
2637 "Full Duplex" : "Half Duplex",
2638 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2639 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2640 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2641 E1000_CTRL_TFCE) ? "TX" : "None")));
2642
2643 /* tweak tx_queue_len according to speed/duplex and
2644 * adjust the timeout factor */
2645 netdev->tx_queue_len = adapter->tx_queue_len;
2646 adapter->tx_timeout_factor = 1;
2647 switch (adapter->link_speed) {
2648 case SPEED_10:
2649 netdev->tx_queue_len = 10;
2650 adapter->tx_timeout_factor = 14;
2651 break;
2652 case SPEED_100:
2653 netdev->tx_queue_len = 100;
2654 /* maybe add some timeout factor ? */
2655 break;
2656 }
2657
2658 netif_carrier_on(netdev);
2659 netif_tx_wake_all_queues(netdev);
2660
2661 igb_ping_all_vfs(adapter);
2662
2663 /* link state has changed, schedule phy info update */
2664 if (!test_bit(__IGB_DOWN, &adapter->state))
2665 mod_timer(&adapter->phy_info_timer,
2666 round_jiffies(jiffies + 2 * HZ));
2667 }
2668 } else {
2669 if (netif_carrier_ok(netdev)) {
2670 adapter->link_speed = 0;
2671 adapter->link_duplex = 0;
2672 /* Links status message must follow this format */
2673 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2674 netdev->name);
2675 netif_carrier_off(netdev);
2676 netif_tx_stop_all_queues(netdev);
2677
2678 igb_ping_all_vfs(adapter);
2679
2680 /* link state has changed, schedule phy info update */
2681 if (!test_bit(__IGB_DOWN, &adapter->state))
2682 mod_timer(&adapter->phy_info_timer,
2683 round_jiffies(jiffies + 2 * HZ));
2684 }
2685 }
2686
2687 link_up:
2688 igb_update_stats(adapter);
2689
2690 hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2691 adapter->tpt_old = adapter->stats.tpt;
2692 hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
2693 adapter->colc_old = adapter->stats.colc;
2694
2695 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2696 adapter->gorc_old = adapter->stats.gorc;
2697 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2698 adapter->gotc_old = adapter->stats.gotc;
2699
2700 igb_update_adaptive(&adapter->hw);
2701
2702 if (!netif_carrier_ok(netdev)) {
2703 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
2704 /* We've lost link, so the controller stops DMA,
2705 * but we've got queued Tx work that's never going
2706 * to get done, so reset controller to flush Tx.
2707 * (Do the reset outside of interrupt context). */
2708 adapter->tx_timeout_count++;
2709 schedule_work(&adapter->reset_task);
2710 }
2711 }
2712
2713 /* Cause software interrupt to ensure rx ring is cleaned */
2714 if (adapter->msix_entries) {
2715 for (i = 0; i < adapter->num_rx_queues; i++)
2716 eics |= adapter->rx_ring[i].eims_value;
2717 wr32(E1000_EICS, eics);
2718 } else {
2719 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2720 }
2721
2722 /* Force detection of hung controller every watchdog period */
2723 tx_ring->detect_tx_hung = true;
2724
2725 /* Reset the timer */
2726 if (!test_bit(__IGB_DOWN, &adapter->state))
2727 mod_timer(&adapter->watchdog_timer,
2728 round_jiffies(jiffies + 2 * HZ));
2729 }
2730
2731 enum latency_range {
2732 lowest_latency = 0,
2733 low_latency = 1,
2734 bulk_latency = 2,
2735 latency_invalid = 255
2736 };
2737
2738
2739 /**
2740 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2741 *
2742 * Stores a new ITR value based on strictly on packet size. This
2743 * algorithm is less sophisticated than that used in igb_update_itr,
2744 * due to the difficulty of synchronizing statistics across multiple
2745 * receive rings. The divisors and thresholds used by this fuction
2746 * were determined based on theoretical maximum wire speed and testing
2747 * data, in order to minimize response time while increasing bulk
2748 * throughput.
2749 * This functionality is controlled by the InterruptThrottleRate module
2750 * parameter (see igb_param.c)
2751 * NOTE: This function is called only when operating in a multiqueue
2752 * receive environment.
2753 * @rx_ring: pointer to ring
2754 **/
2755 static void igb_update_ring_itr(struct igb_ring *rx_ring)
2756 {
2757 int new_val = rx_ring->itr_val;
2758 int avg_wire_size = 0;
2759 struct igb_adapter *adapter = rx_ring->adapter;
2760
2761 if (!rx_ring->total_packets)
2762 goto clear_counts; /* no packets, so don't do anything */
2763
2764 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2765 * ints/sec - ITR timer value of 120 ticks.
2766 */
2767 if (adapter->link_speed != SPEED_1000) {
2768 new_val = 120;
2769 goto set_itr_val;
2770 }
2771 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
2772
2773 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2774 avg_wire_size += 24;
2775
2776 /* Don't starve jumbo frames */
2777 avg_wire_size = min(avg_wire_size, 3000);
2778
2779 /* Give a little boost to mid-size frames */
2780 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2781 new_val = avg_wire_size / 3;
2782 else
2783 new_val = avg_wire_size / 2;
2784
2785 set_itr_val:
2786 if (new_val != rx_ring->itr_val) {
2787 rx_ring->itr_val = new_val;
2788 rx_ring->set_itr = 1;
2789 }
2790 clear_counts:
2791 rx_ring->total_bytes = 0;
2792 rx_ring->total_packets = 0;
2793 }
2794
2795 /**
2796 * igb_update_itr - update the dynamic ITR value based on statistics
2797 * Stores a new ITR value based on packets and byte
2798 * counts during the last interrupt. The advantage of per interrupt
2799 * computation is faster updates and more accurate ITR for the current
2800 * traffic pattern. Constants in this function were computed
2801 * based on theoretical maximum wire speed and thresholds were set based
2802 * on testing data as well as attempting to minimize response time
2803 * while increasing bulk throughput.
2804 * this functionality is controlled by the InterruptThrottleRate module
2805 * parameter (see igb_param.c)
2806 * NOTE: These calculations are only valid when operating in a single-
2807 * queue environment.
2808 * @adapter: pointer to adapter
2809 * @itr_setting: current adapter->itr
2810 * @packets: the number of packets during this measurement interval
2811 * @bytes: the number of bytes during this measurement interval
2812 **/
2813 static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2814 int packets, int bytes)
2815 {
2816 unsigned int retval = itr_setting;
2817
2818 if (packets == 0)
2819 goto update_itr_done;
2820
2821 switch (itr_setting) {
2822 case lowest_latency:
2823 /* handle TSO and jumbo frames */
2824 if (bytes/packets > 8000)
2825 retval = bulk_latency;
2826 else if ((packets < 5) && (bytes > 512))
2827 retval = low_latency;
2828 break;
2829 case low_latency: /* 50 usec aka 20000 ints/s */
2830 if (bytes > 10000) {
2831 /* this if handles the TSO accounting */
2832 if (bytes/packets > 8000) {
2833 retval = bulk_latency;
2834 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2835 retval = bulk_latency;
2836 } else if ((packets > 35)) {
2837 retval = lowest_latency;
2838 }
2839 } else if (bytes/packets > 2000) {
2840 retval = bulk_latency;
2841 } else if (packets <= 2 && bytes < 512) {
2842 retval = lowest_latency;
2843 }
2844 break;
2845 case bulk_latency: /* 250 usec aka 4000 ints/s */
2846 if (bytes > 25000) {
2847 if (packets > 35)
2848 retval = low_latency;
2849 } else if (bytes < 1500) {
2850 retval = low_latency;
2851 }
2852 break;
2853 }
2854
2855 update_itr_done:
2856 return retval;
2857 }
2858
2859 static void igb_set_itr(struct igb_adapter *adapter)
2860 {
2861 u16 current_itr;
2862 u32 new_itr = adapter->itr;
2863
2864 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2865 if (adapter->link_speed != SPEED_1000) {
2866 current_itr = 0;
2867 new_itr = 4000;
2868 goto set_itr_now;
2869 }
2870
2871 adapter->rx_itr = igb_update_itr(adapter,
2872 adapter->rx_itr,
2873 adapter->rx_ring->total_packets,
2874 adapter->rx_ring->total_bytes);
2875
2876 if (adapter->rx_ring->buddy) {
2877 adapter->tx_itr = igb_update_itr(adapter,
2878 adapter->tx_itr,
2879 adapter->tx_ring->total_packets,
2880 adapter->tx_ring->total_bytes);
2881 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2882 } else {
2883 current_itr = adapter->rx_itr;
2884 }
2885
2886 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2887 if (adapter->itr_setting == 3 && current_itr == lowest_latency)
2888 current_itr = low_latency;
2889
2890 switch (current_itr) {
2891 /* counts and packets in update_itr are dependent on these numbers */
2892 case lowest_latency:
2893 new_itr = 70000;
2894 break;
2895 case low_latency:
2896 new_itr = 20000; /* aka hwitr = ~200 */
2897 break;
2898 case bulk_latency:
2899 new_itr = 4000;
2900 break;
2901 default:
2902 break;
2903 }
2904
2905 set_itr_now:
2906 adapter->rx_ring->total_bytes = 0;
2907 adapter->rx_ring->total_packets = 0;
2908 if (adapter->rx_ring->buddy) {
2909 adapter->rx_ring->buddy->total_bytes = 0;
2910 adapter->rx_ring->buddy->total_packets = 0;
2911 }
2912
2913 if (new_itr != adapter->itr) {
2914 /* this attempts to bias the interrupt rate towards Bulk
2915 * by adding intermediate steps when interrupt rate is
2916 * increasing */
2917 new_itr = new_itr > adapter->itr ?
2918 min(adapter->itr + (new_itr >> 2), new_itr) :
2919 new_itr;
2920 /* Don't write the value here; it resets the adapter's
2921 * internal timer, and causes us to delay far longer than
2922 * we should between interrupts. Instead, we write the ITR
2923 * value at the beginning of the next interrupt so the timing
2924 * ends up being correct.
2925 */
2926 adapter->itr = new_itr;
2927 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2928 adapter->rx_ring->set_itr = 1;
2929 }
2930
2931 return;
2932 }
2933
2934
2935 #define IGB_TX_FLAGS_CSUM 0x00000001
2936 #define IGB_TX_FLAGS_VLAN 0x00000002
2937 #define IGB_TX_FLAGS_TSO 0x00000004
2938 #define IGB_TX_FLAGS_IPV4 0x00000008
2939 #define IGB_TX_FLAGS_TSTAMP 0x00000010
2940 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2941 #define IGB_TX_FLAGS_VLAN_SHIFT 16
2942
2943 static inline int igb_tso_adv(struct igb_adapter *adapter,
2944 struct igb_ring *tx_ring,
2945 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2946 {
2947 struct e1000_adv_tx_context_desc *context_desc;
2948 unsigned int i;
2949 int err;
2950 struct igb_buffer *buffer_info;
2951 u32 info = 0, tu_cmd = 0;
2952 u32 mss_l4len_idx, l4len;
2953 *hdr_len = 0;
2954
2955 if (skb_header_cloned(skb)) {
2956 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2957 if (err)
2958 return err;
2959 }
2960
2961 l4len = tcp_hdrlen(skb);
2962 *hdr_len += l4len;
2963
2964 if (skb->protocol == htons(ETH_P_IP)) {
2965 struct iphdr *iph = ip_hdr(skb);
2966 iph->tot_len = 0;
2967 iph->check = 0;
2968 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2969 iph->daddr, 0,
2970 IPPROTO_TCP,
2971 0);
2972 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2973 ipv6_hdr(skb)->payload_len = 0;
2974 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2975 &ipv6_hdr(skb)->daddr,
2976 0, IPPROTO_TCP, 0);
2977 }
2978
2979 i = tx_ring->next_to_use;
2980
2981 buffer_info = &tx_ring->buffer_info[i];
2982 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2983 /* VLAN MACLEN IPLEN */
2984 if (tx_flags & IGB_TX_FLAGS_VLAN)
2985 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2986 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2987 *hdr_len += skb_network_offset(skb);
2988 info |= skb_network_header_len(skb);
2989 *hdr_len += skb_network_header_len(skb);
2990 context_desc->vlan_macip_lens = cpu_to_le32(info);
2991
2992 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2993 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2994
2995 if (skb->protocol == htons(ETH_P_IP))
2996 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2997 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2998
2999 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3000
3001 /* MSS L4LEN IDX */
3002 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3003 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3004
3005 /* For 82575, context index must be unique per ring. */
3006 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3007 mss_l4len_idx |= tx_ring->queue_index << 4;
3008
3009 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3010 context_desc->seqnum_seed = 0;
3011
3012 buffer_info->time_stamp = jiffies;
3013 buffer_info->next_to_watch = i;
3014 buffer_info->dma = 0;
3015 i++;
3016 if (i == tx_ring->count)
3017 i = 0;
3018
3019 tx_ring->next_to_use = i;
3020
3021 return true;
3022 }
3023
3024 static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
3025 struct igb_ring *tx_ring,
3026 struct sk_buff *skb, u32 tx_flags)
3027 {
3028 struct e1000_adv_tx_context_desc *context_desc;
3029 unsigned int i;
3030 struct igb_buffer *buffer_info;
3031 u32 info = 0, tu_cmd = 0;
3032
3033 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3034 (tx_flags & IGB_TX_FLAGS_VLAN)) {
3035 i = tx_ring->next_to_use;
3036 buffer_info = &tx_ring->buffer_info[i];
3037 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3038
3039 if (tx_flags & IGB_TX_FLAGS_VLAN)
3040 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3041 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3042 if (skb->ip_summed == CHECKSUM_PARTIAL)
3043 info |= skb_network_header_len(skb);
3044
3045 context_desc->vlan_macip_lens = cpu_to_le32(info);
3046
3047 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3048
3049 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3050 __be16 protocol;
3051
3052 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3053 const struct vlan_ethhdr *vhdr =
3054 (const struct vlan_ethhdr*)skb->data;
3055
3056 protocol = vhdr->h_vlan_encapsulated_proto;
3057 } else {
3058 protocol = skb->protocol;
3059 }
3060
3061 switch (protocol) {
3062 case cpu_to_be16(ETH_P_IP):
3063 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3064 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3065 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3066 break;
3067 case cpu_to_be16(ETH_P_IPV6):
3068 /* XXX what about other V6 headers?? */
3069 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3070 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3071 break;
3072 default:
3073 if (unlikely(net_ratelimit()))
3074 dev_warn(&adapter->pdev->dev,
3075 "partial checksum but proto=%x!\n",
3076 skb->protocol);
3077 break;
3078 }
3079 }
3080
3081 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3082 context_desc->seqnum_seed = 0;
3083 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3084 context_desc->mss_l4len_idx =
3085 cpu_to_le32(tx_ring->queue_index << 4);
3086 else
3087 context_desc->mss_l4len_idx = 0;
3088
3089 buffer_info->time_stamp = jiffies;
3090 buffer_info->next_to_watch = i;
3091 buffer_info->dma = 0;
3092
3093 i++;
3094 if (i == tx_ring->count)
3095 i = 0;
3096 tx_ring->next_to_use = i;
3097
3098 return true;
3099 }
3100 return false;
3101 }
3102
3103 #define IGB_MAX_TXD_PWR 16
3104 #define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
3105
3106 static inline int igb_tx_map_adv(struct igb_adapter *adapter,
3107 struct igb_ring *tx_ring, struct sk_buff *skb,
3108 unsigned int first)
3109 {
3110 struct igb_buffer *buffer_info;
3111 unsigned int len = skb_headlen(skb);
3112 unsigned int count = 0, i;
3113 unsigned int f;
3114 dma_addr_t *map;
3115
3116 i = tx_ring->next_to_use;
3117
3118 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
3119 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
3120 return 0;
3121 }
3122
3123 map = skb_shinfo(skb)->dma_maps;
3124
3125 buffer_info = &tx_ring->buffer_info[i];
3126 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3127 buffer_info->length = len;
3128 /* set time_stamp *before* dma to help avoid a possible race */
3129 buffer_info->time_stamp = jiffies;
3130 buffer_info->next_to_watch = i;
3131 buffer_info->dma = map[count];
3132 count++;
3133
3134 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3135 struct skb_frag_struct *frag;
3136
3137 i++;
3138 if (i == tx_ring->count)
3139 i = 0;
3140
3141 frag = &skb_shinfo(skb)->frags[f];
3142 len = frag->size;
3143
3144 buffer_info = &tx_ring->buffer_info[i];
3145 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3146 buffer_info->length = len;
3147 buffer_info->time_stamp = jiffies;
3148 buffer_info->next_to_watch = i;
3149 buffer_info->dma = map[count];
3150 count++;
3151 }
3152
3153 tx_ring->buffer_info[i].skb = skb;
3154 tx_ring->buffer_info[first].next_to_watch = i;
3155
3156 return count;
3157 }
3158
3159 static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
3160 struct igb_ring *tx_ring,
3161 int tx_flags, int count, u32 paylen,
3162 u8 hdr_len)
3163 {
3164 union e1000_adv_tx_desc *tx_desc = NULL;
3165 struct igb_buffer *buffer_info;
3166 u32 olinfo_status = 0, cmd_type_len;
3167 unsigned int i;
3168
3169 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3170 E1000_ADVTXD_DCMD_DEXT);
3171
3172 if (tx_flags & IGB_TX_FLAGS_VLAN)
3173 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3174
3175 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3176 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3177
3178 if (tx_flags & IGB_TX_FLAGS_TSO) {
3179 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3180
3181 /* insert tcp checksum */
3182 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3183
3184 /* insert ip checksum */
3185 if (tx_flags & IGB_TX_FLAGS_IPV4)
3186 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3187
3188 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3189 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3190 }
3191
3192 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
3193 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
3194 IGB_TX_FLAGS_VLAN)))
3195 olinfo_status |= tx_ring->queue_index << 4;
3196
3197 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3198
3199 i = tx_ring->next_to_use;
3200 while (count--) {
3201 buffer_info = &tx_ring->buffer_info[i];
3202 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3203 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3204 tx_desc->read.cmd_type_len =
3205 cpu_to_le32(cmd_type_len | buffer_info->length);
3206 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3207 i++;
3208 if (i == tx_ring->count)
3209 i = 0;
3210 }
3211
3212 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3213 /* Force memory writes to complete before letting h/w
3214 * know there are new descriptors to fetch. (Only
3215 * applicable for weak-ordered memory model archs,
3216 * such as IA-64). */
3217 wmb();
3218
3219 tx_ring->next_to_use = i;
3220 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3221 /* we need this if more than one processor can write to our tail
3222 * at a time, it syncronizes IO on IA64/Altix systems */
3223 mmiowb();
3224 }
3225
3226 static int __igb_maybe_stop_tx(struct net_device *netdev,
3227 struct igb_ring *tx_ring, int size)
3228 {
3229 struct igb_adapter *adapter = netdev_priv(netdev);
3230
3231 netif_stop_subqueue(netdev, tx_ring->queue_index);
3232
3233 /* Herbert's original patch had:
3234 * smp_mb__after_netif_stop_queue();
3235 * but since that doesn't exist yet, just open code it. */
3236 smp_mb();
3237
3238 /* We need to check again in a case another CPU has just
3239 * made room available. */
3240 if (igb_desc_unused(tx_ring) < size)
3241 return -EBUSY;
3242
3243 /* A reprieve! */
3244 netif_wake_subqueue(netdev, tx_ring->queue_index);
3245 ++adapter->restart_queue;
3246 return 0;
3247 }
3248
3249 static int igb_maybe_stop_tx(struct net_device *netdev,
3250 struct igb_ring *tx_ring, int size)
3251 {
3252 if (igb_desc_unused(tx_ring) >= size)
3253 return 0;
3254 return __igb_maybe_stop_tx(netdev, tx_ring, size);
3255 }
3256
3257 static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
3258 struct net_device *netdev,
3259 struct igb_ring *tx_ring)
3260 {
3261 struct igb_adapter *adapter = netdev_priv(netdev);
3262 unsigned int first;
3263 unsigned int tx_flags = 0;
3264 u8 hdr_len = 0;
3265 int count = 0;
3266 int tso = 0;
3267 union skb_shared_tx *shtx;
3268
3269 if (test_bit(__IGB_DOWN, &adapter->state)) {
3270 dev_kfree_skb_any(skb);
3271 return NETDEV_TX_OK;
3272 }
3273
3274 if (skb->len <= 0) {
3275 dev_kfree_skb_any(skb);
3276 return NETDEV_TX_OK;
3277 }
3278
3279 /* need: 1 descriptor per page,
3280 * + 2 desc gap to keep tail from touching head,
3281 * + 1 desc for skb->data,
3282 * + 1 desc for context descriptor,
3283 * otherwise try next time */
3284 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3285 /* this is a hard error */
3286 return NETDEV_TX_BUSY;
3287 }
3288
3289 /*
3290 * TODO: check that there currently is no other packet with
3291 * time stamping in the queue
3292 *
3293 * When doing time stamping, keep the connection to the socket
3294 * a while longer: it is still needed by skb_hwtstamp_tx(),
3295 * called either in igb_tx_hwtstamp() or by our caller when
3296 * doing software time stamping.
3297 */
3298 shtx = skb_tx(skb);
3299 if (unlikely(shtx->hardware)) {
3300 shtx->in_progress = 1;
3301 tx_flags |= IGB_TX_FLAGS_TSTAMP;
3302 }
3303
3304 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3305 tx_flags |= IGB_TX_FLAGS_VLAN;
3306 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3307 }
3308
3309 if (skb->protocol == htons(ETH_P_IP))
3310 tx_flags |= IGB_TX_FLAGS_IPV4;
3311
3312 first = tx_ring->next_to_use;
3313 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3314 &hdr_len) : 0;
3315
3316 if (tso < 0) {
3317 dev_kfree_skb_any(skb);
3318 return NETDEV_TX_OK;
3319 }
3320
3321 if (tso)
3322 tx_flags |= IGB_TX_FLAGS_TSO;
3323 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) &&
3324 (skb->ip_summed == CHECKSUM_PARTIAL))
3325 tx_flags |= IGB_TX_FLAGS_CSUM;
3326
3327 /*
3328 * count reflects descriptors mapped, if 0 then mapping error
3329 * has occured and we need to rewind the descriptor queue
3330 */
3331 count = igb_tx_map_adv(adapter, tx_ring, skb, first);
3332
3333 if (count) {
3334 igb_tx_queue_adv(adapter, tx_ring, tx_flags, count,
3335 skb->len, hdr_len);
3336 netdev->trans_start = jiffies;
3337 /* Make sure there is space in the ring for the next send. */
3338 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3339 } else {
3340 dev_kfree_skb_any(skb);
3341 tx_ring->buffer_info[first].time_stamp = 0;
3342 tx_ring->next_to_use = first;
3343 }
3344
3345 return NETDEV_TX_OK;
3346 }
3347
3348 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3349 {
3350 struct igb_adapter *adapter = netdev_priv(netdev);
3351 struct igb_ring *tx_ring;
3352
3353 int r_idx = 0;
3354 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
3355 tx_ring = adapter->multi_tx_table[r_idx];
3356
3357 /* This goes back to the question of how to logically map a tx queue
3358 * to a flow. Right now, performance is impacted slightly negatively
3359 * if using multiple tx queues. If the stack breaks away from a
3360 * single qdisc implementation, we can look at this again. */
3361 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3362 }
3363
3364 /**
3365 * igb_tx_timeout - Respond to a Tx Hang
3366 * @netdev: network interface device structure
3367 **/
3368 static void igb_tx_timeout(struct net_device *netdev)
3369 {
3370 struct igb_adapter *adapter = netdev_priv(netdev);
3371 struct e1000_hw *hw = &adapter->hw;
3372
3373 /* Do the reset outside of interrupt context */
3374 adapter->tx_timeout_count++;
3375 schedule_work(&adapter->reset_task);
3376 wr32(E1000_EICS,
3377 (adapter->eims_enable_mask & ~adapter->eims_other));
3378 }
3379
3380 static void igb_reset_task(struct work_struct *work)
3381 {
3382 struct igb_adapter *adapter;
3383 adapter = container_of(work, struct igb_adapter, reset_task);
3384
3385 igb_reinit_locked(adapter);
3386 }
3387
3388 /**
3389 * igb_get_stats - Get System Network Statistics
3390 * @netdev: network interface device structure
3391 *
3392 * Returns the address of the device statistics structure.
3393 * The statistics are actually updated from the timer callback.
3394 **/
3395 static struct net_device_stats *igb_get_stats(struct net_device *netdev)
3396 {
3397 struct igb_adapter *adapter = netdev_priv(netdev);
3398
3399 /* only return the current stats */
3400 return &adapter->net_stats;
3401 }
3402
3403 /**
3404 * igb_change_mtu - Change the Maximum Transfer Unit
3405 * @netdev: network interface device structure
3406 * @new_mtu: new value for maximum frame size
3407 *
3408 * Returns 0 on success, negative on failure
3409 **/
3410 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3411 {
3412 struct igb_adapter *adapter = netdev_priv(netdev);
3413 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3414
3415 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3416 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3417 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3418 return -EINVAL;
3419 }
3420
3421 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3422 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3423 return -EINVAL;
3424 }
3425
3426 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3427 msleep(1);
3428
3429 /* igb_down has a dependency on max_frame_size */
3430 adapter->max_frame_size = max_frame;
3431 if (netif_running(netdev))
3432 igb_down(adapter);
3433
3434 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3435 * means we reserve 2 more, this pushes us to allocate from the next
3436 * larger slab size.
3437 * i.e. RXBUFFER_2048 --> size-4096 slab
3438 */
3439
3440 if (max_frame <= IGB_RXBUFFER_256)
3441 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3442 else if (max_frame <= IGB_RXBUFFER_512)
3443 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3444 else if (max_frame <= IGB_RXBUFFER_1024)
3445 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3446 else if (max_frame <= IGB_RXBUFFER_2048)
3447 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3448 else
3449 #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3450 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3451 #else
3452 adapter->rx_buffer_len = PAGE_SIZE / 2;
3453 #endif
3454
3455 /* if sr-iov is enabled we need to force buffer size to 1K or larger */
3456 if (adapter->vfs_allocated_count &&
3457 (adapter->rx_buffer_len < IGB_RXBUFFER_1024))
3458 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3459
3460 /* adjust allocation if LPE protects us, and we aren't using SBP */
3461 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3462 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3463 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3464
3465 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3466 netdev->mtu, new_mtu);
3467 netdev->mtu = new_mtu;
3468
3469 if (netif_running(netdev))
3470 igb_up(adapter);
3471 else
3472 igb_reset(adapter);
3473
3474 clear_bit(__IGB_RESETTING, &adapter->state);
3475
3476 return 0;
3477 }
3478
3479 /**
3480 * igb_update_stats - Update the board statistics counters
3481 * @adapter: board private structure
3482 **/
3483
3484 void igb_update_stats(struct igb_adapter *adapter)
3485 {
3486 struct e1000_hw *hw = &adapter->hw;
3487 struct pci_dev *pdev = adapter->pdev;
3488 u16 phy_tmp;
3489
3490 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3491
3492 /*
3493 * Prevent stats update while adapter is being reset, or if the pci
3494 * connection is down.
3495 */
3496 if (adapter->link_speed == 0)
3497 return;
3498 if (pci_channel_offline(pdev))
3499 return;
3500
3501 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3502 adapter->stats.gprc += rd32(E1000_GPRC);
3503 adapter->stats.gorc += rd32(E1000_GORCL);
3504 rd32(E1000_GORCH); /* clear GORCL */
3505 adapter->stats.bprc += rd32(E1000_BPRC);
3506 adapter->stats.mprc += rd32(E1000_MPRC);
3507 adapter->stats.roc += rd32(E1000_ROC);
3508
3509 adapter->stats.prc64 += rd32(E1000_PRC64);
3510 adapter->stats.prc127 += rd32(E1000_PRC127);
3511 adapter->stats.prc255 += rd32(E1000_PRC255);
3512 adapter->stats.prc511 += rd32(E1000_PRC511);
3513 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3514 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3515 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3516 adapter->stats.sec += rd32(E1000_SEC);
3517
3518 adapter->stats.mpc += rd32(E1000_MPC);
3519 adapter->stats.scc += rd32(E1000_SCC);
3520 adapter->stats.ecol += rd32(E1000_ECOL);
3521 adapter->stats.mcc += rd32(E1000_MCC);
3522 adapter->stats.latecol += rd32(E1000_LATECOL);
3523 adapter->stats.dc += rd32(E1000_DC);
3524 adapter->stats.rlec += rd32(E1000_RLEC);
3525 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3526 adapter->stats.xontxc += rd32(E1000_XONTXC);
3527 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3528 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3529 adapter->stats.fcruc += rd32(E1000_FCRUC);
3530 adapter->stats.gptc += rd32(E1000_GPTC);
3531 adapter->stats.gotc += rd32(E1000_GOTCL);
3532 rd32(E1000_GOTCH); /* clear GOTCL */
3533 adapter->stats.rnbc += rd32(E1000_RNBC);
3534 adapter->stats.ruc += rd32(E1000_RUC);
3535 adapter->stats.rfc += rd32(E1000_RFC);
3536 adapter->stats.rjc += rd32(E1000_RJC);
3537 adapter->stats.tor += rd32(E1000_TORH);
3538 adapter->stats.tot += rd32(E1000_TOTH);
3539 adapter->stats.tpr += rd32(E1000_TPR);
3540
3541 adapter->stats.ptc64 += rd32(E1000_PTC64);
3542 adapter->stats.ptc127 += rd32(E1000_PTC127);
3543 adapter->stats.ptc255 += rd32(E1000_PTC255);
3544 adapter->stats.ptc511 += rd32(E1000_PTC511);
3545 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3546 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3547
3548 adapter->stats.mptc += rd32(E1000_MPTC);
3549 adapter->stats.bptc += rd32(E1000_BPTC);
3550
3551 /* used for adaptive IFS */
3552
3553 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3554 adapter->stats.tpt += hw->mac.tx_packet_delta;
3555 hw->mac.collision_delta = rd32(E1000_COLC);
3556 adapter->stats.colc += hw->mac.collision_delta;
3557
3558 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3559 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3560 adapter->stats.tncrs += rd32(E1000_TNCRS);
3561 adapter->stats.tsctc += rd32(E1000_TSCTC);
3562 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3563
3564 adapter->stats.iac += rd32(E1000_IAC);
3565 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3566 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3567 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3568 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3569 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3570 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3571 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3572 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3573
3574 /* Fill out the OS statistics structure */
3575 adapter->net_stats.multicast = adapter->stats.mprc;
3576 adapter->net_stats.collisions = adapter->stats.colc;
3577
3578 /* Rx Errors */
3579
3580 /* RLEC on some newer hardware can be incorrect so build
3581 * our own version based on RUC and ROC */
3582 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3583 adapter->stats.crcerrs + adapter->stats.algnerrc +
3584 adapter->stats.ruc + adapter->stats.roc +
3585 adapter->stats.cexterr;
3586 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3587 adapter->stats.roc;
3588 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3589 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3590 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3591
3592 /* Tx Errors */
3593 adapter->net_stats.tx_errors = adapter->stats.ecol +
3594 adapter->stats.latecol;
3595 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3596 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3597 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3598
3599 /* Tx Dropped needs to be maintained elsewhere */
3600
3601 /* Phy Stats */
3602 if (hw->phy.media_type == e1000_media_type_copper) {
3603 if ((adapter->link_speed == SPEED_1000) &&
3604 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3605 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3606 adapter->phy_stats.idle_errors += phy_tmp;
3607 }
3608 }
3609
3610 /* Management Stats */
3611 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3612 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3613 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3614 }
3615
3616 static irqreturn_t igb_msix_other(int irq, void *data)
3617 {
3618 struct net_device *netdev = data;
3619 struct igb_adapter *adapter = netdev_priv(netdev);
3620 struct e1000_hw *hw = &adapter->hw;
3621 u32 icr = rd32(E1000_ICR);
3622
3623 /* reading ICR causes bit 31 of EICR to be cleared */
3624
3625 if(icr & E1000_ICR_DOUTSYNC) {
3626 /* HW is reporting DMA is out of sync */
3627 adapter->stats.doosync++;
3628 }
3629
3630 /* Check for a mailbox event */
3631 if (icr & E1000_ICR_VMMB)
3632 igb_msg_task(adapter);
3633
3634 if (icr & E1000_ICR_LSC) {
3635 hw->mac.get_link_status = 1;
3636 /* guard against interrupt when we're going down */
3637 if (!test_bit(__IGB_DOWN, &adapter->state))
3638 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3639 }
3640
3641 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
3642 wr32(E1000_EIMS, adapter->eims_other);
3643
3644 return IRQ_HANDLED;
3645 }
3646
3647 static irqreturn_t igb_msix_tx(int irq, void *data)
3648 {
3649 struct igb_ring *tx_ring = data;
3650 struct igb_adapter *adapter = tx_ring->adapter;
3651 struct e1000_hw *hw = &adapter->hw;
3652
3653 #ifdef CONFIG_IGB_DCA
3654 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3655 igb_update_tx_dca(tx_ring);
3656 #endif
3657
3658 tx_ring->total_bytes = 0;
3659 tx_ring->total_packets = 0;
3660
3661 /* auto mask will automatically reenable the interrupt when we write
3662 * EICS */
3663 if (!igb_clean_tx_irq(tx_ring))
3664 /* Ring was not completely cleaned, so fire another interrupt */
3665 wr32(E1000_EICS, tx_ring->eims_value);
3666 else
3667 wr32(E1000_EIMS, tx_ring->eims_value);
3668
3669 return IRQ_HANDLED;
3670 }
3671
3672 static void igb_write_itr(struct igb_ring *ring)
3673 {
3674 struct e1000_hw *hw = &ring->adapter->hw;
3675 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3676 switch (hw->mac.type) {
3677 case e1000_82576:
3678 wr32(ring->itr_register, ring->itr_val |
3679 0x80000000);
3680 break;
3681 default:
3682 wr32(ring->itr_register, ring->itr_val |
3683 (ring->itr_val << 16));
3684 break;
3685 }
3686 ring->set_itr = 0;
3687 }
3688 }
3689
3690 static irqreturn_t igb_msix_rx(int irq, void *data)
3691 {
3692 struct igb_ring *rx_ring = data;
3693
3694 /* Write the ITR value calculated at the end of the
3695 * previous interrupt.
3696 */
3697
3698 igb_write_itr(rx_ring);
3699
3700 if (napi_schedule_prep(&rx_ring->napi))
3701 __napi_schedule(&rx_ring->napi);
3702
3703 #ifdef CONFIG_IGB_DCA
3704 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
3705 igb_update_rx_dca(rx_ring);
3706 #endif
3707 return IRQ_HANDLED;
3708 }
3709
3710 #ifdef CONFIG_IGB_DCA
3711 static void igb_update_rx_dca(struct igb_ring *rx_ring)
3712 {
3713 u32 dca_rxctrl;
3714 struct igb_adapter *adapter = rx_ring->adapter;
3715 struct e1000_hw *hw = &adapter->hw;
3716 int cpu = get_cpu();
3717 int q = rx_ring->reg_idx;
3718
3719 if (rx_ring->cpu != cpu) {
3720 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
3721 if (hw->mac.type == e1000_82576) {
3722 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3723 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3724 E1000_DCA_RXCTRL_CPUID_SHIFT;
3725 } else {
3726 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3727 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3728 }
3729 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3730 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3731 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3732 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3733 rx_ring->cpu = cpu;
3734 }
3735 put_cpu();
3736 }
3737
3738 static void igb_update_tx_dca(struct igb_ring *tx_ring)
3739 {
3740 u32 dca_txctrl;
3741 struct igb_adapter *adapter = tx_ring->adapter;
3742 struct e1000_hw *hw = &adapter->hw;
3743 int cpu = get_cpu();
3744 int q = tx_ring->reg_idx;
3745
3746 if (tx_ring->cpu != cpu) {
3747 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
3748 if (hw->mac.type == e1000_82576) {
3749 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3750 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3751 E1000_DCA_TXCTRL_CPUID_SHIFT;
3752 } else {
3753 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3754 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3755 }
3756 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3757 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3758 tx_ring->cpu = cpu;
3759 }
3760 put_cpu();
3761 }
3762
3763 static void igb_setup_dca(struct igb_adapter *adapter)
3764 {
3765 int i;
3766
3767 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
3768 return;
3769
3770 for (i = 0; i < adapter->num_tx_queues; i++) {
3771 adapter->tx_ring[i].cpu = -1;
3772 igb_update_tx_dca(&adapter->tx_ring[i]);
3773 }
3774 for (i = 0; i < adapter->num_rx_queues; i++) {
3775 adapter->rx_ring[i].cpu = -1;
3776 igb_update_rx_dca(&adapter->rx_ring[i]);
3777 }
3778 }
3779
3780 static int __igb_notify_dca(struct device *dev, void *data)
3781 {
3782 struct net_device *netdev = dev_get_drvdata(dev);
3783 struct igb_adapter *adapter = netdev_priv(netdev);
3784 struct e1000_hw *hw = &adapter->hw;
3785 unsigned long event = *(unsigned long *)data;
3786
3787 switch (event) {
3788 case DCA_PROVIDER_ADD:
3789 /* if already enabled, don't do it again */
3790 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3791 break;
3792 /* Always use CB2 mode, difference is masked
3793 * in the CB driver. */
3794 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
3795 if (dca_add_requester(dev) == 0) {
3796 adapter->flags |= IGB_FLAG_DCA_ENABLED;
3797 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3798 igb_setup_dca(adapter);
3799 break;
3800 }
3801 /* Fall Through since DCA is disabled. */
3802 case DCA_PROVIDER_REMOVE:
3803 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3804 /* without this a class_device is left
3805 * hanging around in the sysfs model */
3806 dca_remove_requester(dev);
3807 dev_info(&adapter->pdev->dev, "DCA disabled\n");
3808 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3809 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
3810 }
3811 break;
3812 }
3813
3814 return 0;
3815 }
3816
3817 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3818 void *p)
3819 {
3820 int ret_val;
3821
3822 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3823 __igb_notify_dca);
3824
3825 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3826 }
3827 #endif /* CONFIG_IGB_DCA */
3828
3829 static void igb_ping_all_vfs(struct igb_adapter *adapter)
3830 {
3831 struct e1000_hw *hw = &adapter->hw;
3832 u32 ping;
3833 int i;
3834
3835 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
3836 ping = E1000_PF_CONTROL_MSG;
3837 if (adapter->vf_data[i].clear_to_send)
3838 ping |= E1000_VT_MSGTYPE_CTS;
3839 igb_write_mbx(hw, &ping, 1, i);
3840 }
3841 }
3842
3843 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
3844 u32 *msgbuf, u32 vf)
3845 {
3846 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3847 u16 *hash_list = (u16 *)&msgbuf[1];
3848 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
3849 int i;
3850
3851 /* only up to 30 hash values supported */
3852 if (n > 30)
3853 n = 30;
3854
3855 /* salt away the number of multi cast addresses assigned
3856 * to this VF for later use to restore when the PF multi cast
3857 * list changes
3858 */
3859 vf_data->num_vf_mc_hashes = n;
3860
3861 /* VFs are limited to using the MTA hash table for their multicast
3862 * addresses */
3863 for (i = 0; i < n; i++)
3864 vf_data->vf_mc_hashes[i] = hash_list[i];;
3865
3866 /* Flush and reset the mta with the new values */
3867 igb_set_multi(adapter->netdev);
3868
3869 return 0;
3870 }
3871
3872 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
3873 {
3874 struct e1000_hw *hw = &adapter->hw;
3875 struct vf_data_storage *vf_data;
3876 int i, j;
3877
3878 for (i = 0; i < adapter->vfs_allocated_count; i++) {
3879 vf_data = &adapter->vf_data[i];
3880 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
3881 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
3882 }
3883 }
3884
3885 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
3886 {
3887 struct e1000_hw *hw = &adapter->hw;
3888 u32 pool_mask, reg, vid;
3889 int i;
3890
3891 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3892
3893 /* Find the vlan filter for this id */
3894 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3895 reg = rd32(E1000_VLVF(i));
3896
3897 /* remove the vf from the pool */
3898 reg &= ~pool_mask;
3899
3900 /* if pool is empty then remove entry from vfta */
3901 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
3902 (reg & E1000_VLVF_VLANID_ENABLE)) {
3903 reg = 0;
3904 vid = reg & E1000_VLVF_VLANID_MASK;
3905 igb_vfta_set(hw, vid, false);
3906 }
3907
3908 wr32(E1000_VLVF(i), reg);
3909 }
3910 }
3911
3912 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
3913 {
3914 struct e1000_hw *hw = &adapter->hw;
3915 u32 reg, i;
3916
3917 /* It is an error to call this function when VFs are not enabled */
3918 if (!adapter->vfs_allocated_count)
3919 return -1;
3920
3921 /* Find the vlan filter for this id */
3922 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3923 reg = rd32(E1000_VLVF(i));
3924 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
3925 vid == (reg & E1000_VLVF_VLANID_MASK))
3926 break;
3927 }
3928
3929 if (add) {
3930 if (i == E1000_VLVF_ARRAY_SIZE) {
3931 /* Did not find a matching VLAN ID entry that was
3932 * enabled. Search for a free filter entry, i.e.
3933 * one without the enable bit set
3934 */
3935 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3936 reg = rd32(E1000_VLVF(i));
3937 if (!(reg & E1000_VLVF_VLANID_ENABLE))
3938 break;
3939 }
3940 }
3941 if (i < E1000_VLVF_ARRAY_SIZE) {
3942 /* Found an enabled/available entry */
3943 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3944
3945 /* if !enabled we need to set this up in vfta */
3946 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
3947 /* add VID to filter table, if bit already set
3948 * PF must have added it outside of table */
3949 if (igb_vfta_set(hw, vid, true))
3950 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT +
3951 adapter->vfs_allocated_count);
3952 reg |= E1000_VLVF_VLANID_ENABLE;
3953 }
3954 reg &= ~E1000_VLVF_VLANID_MASK;
3955 reg |= vid;
3956
3957 wr32(E1000_VLVF(i), reg);
3958 return 0;
3959 }
3960 } else {
3961 if (i < E1000_VLVF_ARRAY_SIZE) {
3962 /* remove vf from the pool */
3963 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
3964 /* if pool is empty then remove entry from vfta */
3965 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
3966 reg = 0;
3967 igb_vfta_set(hw, vid, false);
3968 }
3969 wr32(E1000_VLVF(i), reg);
3970 return 0;
3971 }
3972 }
3973 return -1;
3974 }
3975
3976 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
3977 {
3978 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3979 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
3980
3981 return igb_vlvf_set(adapter, vid, add, vf);
3982 }
3983
3984 static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
3985 {
3986 struct e1000_hw *hw = &adapter->hw;
3987
3988 /* disable mailbox functionality for vf */
3989 adapter->vf_data[vf].clear_to_send = false;
3990
3991 /* reset offloads to defaults */
3992 igb_set_vmolr(hw, vf);
3993
3994 /* reset vlans for device */
3995 igb_clear_vf_vfta(adapter, vf);
3996
3997 /* reset multicast table array for vf */
3998 adapter->vf_data[vf].num_vf_mc_hashes = 0;
3999
4000 /* Flush and reset the mta with the new values */
4001 igb_set_multi(adapter->netdev);
4002 }
4003
4004 static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4005 {
4006 struct e1000_hw *hw = &adapter->hw;
4007 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
4008 u32 reg, msgbuf[3];
4009 u8 *addr = (u8 *)(&msgbuf[1]);
4010
4011 /* process all the same items cleared in a function level reset */
4012 igb_vf_reset_event(adapter, vf);
4013
4014 /* set vf mac address */
4015 igb_rar_set(hw, vf_mac, vf + 1);
4016 igb_set_rah_pool(hw, vf, vf + 1);
4017
4018 /* enable transmit and receive for vf */
4019 reg = rd32(E1000_VFTE);
4020 wr32(E1000_VFTE, reg | (1 << vf));
4021 reg = rd32(E1000_VFRE);
4022 wr32(E1000_VFRE, reg | (1 << vf));
4023
4024 /* enable mailbox functionality for vf */
4025 adapter->vf_data[vf].clear_to_send = true;
4026
4027 /* reply to reset with ack and vf mac address */
4028 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4029 memcpy(addr, vf_mac, 6);
4030 igb_write_mbx(hw, msgbuf, 3, vf);
4031 }
4032
4033 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4034 {
4035 unsigned char *addr = (char *)&msg[1];
4036 int err = -1;
4037
4038 if (is_valid_ether_addr(addr))
4039 err = igb_set_vf_mac(adapter, vf, addr);
4040
4041 return err;
4042
4043 }
4044
4045 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4046 {
4047 struct e1000_hw *hw = &adapter->hw;
4048 u32 msg = E1000_VT_MSGTYPE_NACK;
4049
4050 /* if device isn't clear to send it shouldn't be reading either */
4051 if (!adapter->vf_data[vf].clear_to_send)
4052 igb_write_mbx(hw, &msg, 1, vf);
4053 }
4054
4055
4056 static void igb_msg_task(struct igb_adapter *adapter)
4057 {
4058 struct e1000_hw *hw = &adapter->hw;
4059 u32 vf;
4060
4061 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4062 /* process any reset requests */
4063 if (!igb_check_for_rst(hw, vf)) {
4064 adapter->vf_data[vf].clear_to_send = false;
4065 igb_vf_reset_event(adapter, vf);
4066 }
4067
4068 /* process any messages pending */
4069 if (!igb_check_for_msg(hw, vf))
4070 igb_rcv_msg_from_vf(adapter, vf);
4071
4072 /* process any acks */
4073 if (!igb_check_for_ack(hw, vf))
4074 igb_rcv_ack_from_vf(adapter, vf);
4075
4076 }
4077 }
4078
4079 static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4080 {
4081 u32 mbx_size = E1000_VFMAILBOX_SIZE;
4082 u32 msgbuf[mbx_size];
4083 struct e1000_hw *hw = &adapter->hw;
4084 s32 retval;
4085
4086 retval = igb_read_mbx(hw, msgbuf, mbx_size, vf);
4087
4088 if (retval)
4089 dev_err(&adapter->pdev->dev,
4090 "Error receiving message from VF\n");
4091
4092 /* this is a message we already processed, do nothing */
4093 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4094 return retval;
4095
4096 /*
4097 * until the vf completes a reset it should not be
4098 * allowed to start any configuration.
4099 */
4100
4101 if (msgbuf[0] == E1000_VF_RESET) {
4102 igb_vf_reset_msg(adapter, vf);
4103
4104 return retval;
4105 }
4106
4107 if (!adapter->vf_data[vf].clear_to_send) {
4108 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4109 igb_write_mbx(hw, msgbuf, 1, vf);
4110 return retval;
4111 }
4112
4113 switch ((msgbuf[0] & 0xFFFF)) {
4114 case E1000_VF_SET_MAC_ADDR:
4115 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4116 break;
4117 case E1000_VF_SET_MULTICAST:
4118 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4119 break;
4120 case E1000_VF_SET_LPE:
4121 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4122 break;
4123 case E1000_VF_SET_VLAN:
4124 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4125 break;
4126 default:
4127 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4128 retval = -1;
4129 break;
4130 }
4131
4132 /* notify the VF of the results of what it sent us */
4133 if (retval)
4134 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4135 else
4136 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4137
4138 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4139
4140 igb_write_mbx(hw, msgbuf, 1, vf);
4141
4142 return retval;
4143 }
4144
4145 /**
4146 * igb_intr_msi - Interrupt Handler
4147 * @irq: interrupt number
4148 * @data: pointer to a network interface device structure
4149 **/
4150 static irqreturn_t igb_intr_msi(int irq, void *data)
4151 {
4152 struct net_device *netdev = data;
4153 struct igb_adapter *adapter = netdev_priv(netdev);
4154 struct e1000_hw *hw = &adapter->hw;
4155 /* read ICR disables interrupts using IAM */
4156 u32 icr = rd32(E1000_ICR);
4157
4158 igb_write_itr(adapter->rx_ring);
4159
4160 if(icr & E1000_ICR_DOUTSYNC) {
4161 /* HW is reporting DMA is out of sync */
4162 adapter->stats.doosync++;
4163 }
4164
4165 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4166 hw->mac.get_link_status = 1;
4167 if (!test_bit(__IGB_DOWN, &adapter->state))
4168 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4169 }
4170
4171 napi_schedule(&adapter->rx_ring[0].napi);
4172
4173 return IRQ_HANDLED;
4174 }
4175
4176 /**
4177 * igb_intr - Legacy Interrupt Handler
4178 * @irq: interrupt number
4179 * @data: pointer to a network interface device structure
4180 **/
4181 static irqreturn_t igb_intr(int irq, void *data)
4182 {
4183 struct net_device *netdev = data;
4184 struct igb_adapter *adapter = netdev_priv(netdev);
4185 struct e1000_hw *hw = &adapter->hw;
4186 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
4187 * need for the IMC write */
4188 u32 icr = rd32(E1000_ICR);
4189 if (!icr)
4190 return IRQ_NONE; /* Not our interrupt */
4191
4192 igb_write_itr(adapter->rx_ring);
4193
4194 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4195 * not set, then the adapter didn't send an interrupt */
4196 if (!(icr & E1000_ICR_INT_ASSERTED))
4197 return IRQ_NONE;
4198
4199 if(icr & E1000_ICR_DOUTSYNC) {
4200 /* HW is reporting DMA is out of sync */
4201 adapter->stats.doosync++;
4202 }
4203
4204 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4205 hw->mac.get_link_status = 1;
4206 /* guard against interrupt when we're going down */
4207 if (!test_bit(__IGB_DOWN, &adapter->state))
4208 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4209 }
4210
4211 napi_schedule(&adapter->rx_ring[0].napi);
4212
4213 return IRQ_HANDLED;
4214 }
4215
4216 static inline void igb_rx_irq_enable(struct igb_ring *rx_ring)
4217 {
4218 struct igb_adapter *adapter = rx_ring->adapter;
4219 struct e1000_hw *hw = &adapter->hw;
4220
4221 if (adapter->itr_setting & 3) {
4222 if (adapter->num_rx_queues == 1)
4223 igb_set_itr(adapter);
4224 else
4225 igb_update_ring_itr(rx_ring);
4226 }
4227
4228 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4229 if (adapter->msix_entries)
4230 wr32(E1000_EIMS, rx_ring->eims_value);
4231 else
4232 igb_irq_enable(adapter);
4233 }
4234 }
4235
4236 /**
4237 * igb_poll - NAPI Rx polling callback
4238 * @napi: napi polling structure
4239 * @budget: count of how many packets we should handle
4240 **/
4241 static int igb_poll(struct napi_struct *napi, int budget)
4242 {
4243 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
4244 int work_done = 0;
4245
4246 #ifdef CONFIG_IGB_DCA
4247 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4248 igb_update_rx_dca(rx_ring);
4249 #endif
4250 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
4251
4252 if (rx_ring->buddy) {
4253 #ifdef CONFIG_IGB_DCA
4254 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4255 igb_update_tx_dca(rx_ring->buddy);
4256 #endif
4257 if (!igb_clean_tx_irq(rx_ring->buddy))
4258 work_done = budget;
4259 }
4260
4261 /* If not enough Rx work done, exit the polling mode */
4262 if (work_done < budget) {
4263 napi_complete(napi);
4264 igb_rx_irq_enable(rx_ring);
4265 }
4266
4267 return work_done;
4268 }
4269
4270 /**
4271 * igb_hwtstamp - utility function which checks for TX time stamp
4272 * @adapter: board private structure
4273 * @skb: packet that was just sent
4274 *
4275 * If we were asked to do hardware stamping and such a time stamp is
4276 * available, then it must have been for this skb here because we only
4277 * allow only one such packet into the queue.
4278 */
4279 static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
4280 {
4281 union skb_shared_tx *shtx = skb_tx(skb);
4282 struct e1000_hw *hw = &adapter->hw;
4283
4284 if (unlikely(shtx->hardware)) {
4285 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
4286 if (valid) {
4287 u64 regval = rd32(E1000_TXSTMPL);
4288 u64 ns;
4289 struct skb_shared_hwtstamps shhwtstamps;
4290
4291 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
4292 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4293 ns = timecounter_cyc2time(&adapter->clock,
4294 regval);
4295 timecompare_update(&adapter->compare, ns);
4296 shhwtstamps.hwtstamp = ns_to_ktime(ns);
4297 shhwtstamps.syststamp =
4298 timecompare_transform(&adapter->compare, ns);
4299 skb_tstamp_tx(skb, &shhwtstamps);
4300 }
4301 }
4302 }
4303
4304 /**
4305 * igb_clean_tx_irq - Reclaim resources after transmit completes
4306 * @adapter: board private structure
4307 * returns true if ring is completely cleaned
4308 **/
4309 static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
4310 {
4311 struct igb_adapter *adapter = tx_ring->adapter;
4312 struct net_device *netdev = adapter->netdev;
4313 struct e1000_hw *hw = &adapter->hw;
4314 struct igb_buffer *buffer_info;
4315 struct sk_buff *skb;
4316 union e1000_adv_tx_desc *tx_desc, *eop_desc;
4317 unsigned int total_bytes = 0, total_packets = 0;
4318 unsigned int i, eop, count = 0;
4319 bool cleaned = false;
4320
4321 i = tx_ring->next_to_clean;
4322 eop = tx_ring->buffer_info[i].next_to_watch;
4323 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4324
4325 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4326 (count < tx_ring->count)) {
4327 for (cleaned = false; !cleaned; count++) {
4328 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
4329 buffer_info = &tx_ring->buffer_info[i];
4330 cleaned = (i == eop);
4331 skb = buffer_info->skb;
4332
4333 if (skb) {
4334 unsigned int segs, bytecount;
4335 /* gso_segs is currently only valid for tcp */
4336 segs = skb_shinfo(skb)->gso_segs ?: 1;
4337 /* multiply data chunks by size of headers */
4338 bytecount = ((segs - 1) * skb_headlen(skb)) +
4339 skb->len;
4340 total_packets += segs;
4341 total_bytes += bytecount;
4342
4343 igb_tx_hwtstamp(adapter, skb);
4344 }
4345
4346 igb_unmap_and_free_tx_resource(adapter, buffer_info);
4347 tx_desc->wb.status = 0;
4348
4349 i++;
4350 if (i == tx_ring->count)
4351 i = 0;
4352 }
4353 eop = tx_ring->buffer_info[i].next_to_watch;
4354 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4355 }
4356
4357 tx_ring->next_to_clean = i;
4358
4359 if (unlikely(count &&
4360 netif_carrier_ok(netdev) &&
4361 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
4362 /* Make sure that anybody stopping the queue after this
4363 * sees the new next_to_clean.
4364 */
4365 smp_mb();
4366 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4367 !(test_bit(__IGB_DOWN, &adapter->state))) {
4368 netif_wake_subqueue(netdev, tx_ring->queue_index);
4369 ++adapter->restart_queue;
4370 }
4371 }
4372
4373 if (tx_ring->detect_tx_hung) {
4374 /* Detect a transmit hang in hardware, this serializes the
4375 * check with the clearing of time_stamp and movement of i */
4376 tx_ring->detect_tx_hung = false;
4377 if (tx_ring->buffer_info[i].time_stamp &&
4378 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4379 (adapter->tx_timeout_factor * HZ))
4380 && !(rd32(E1000_STATUS) &
4381 E1000_STATUS_TXOFF)) {
4382
4383 /* detected Tx unit hang */
4384 dev_err(&adapter->pdev->dev,
4385 "Detected Tx Unit Hang\n"
4386 " Tx Queue <%d>\n"
4387 " TDH <%x>\n"
4388 " TDT <%x>\n"
4389 " next_to_use <%x>\n"
4390 " next_to_clean <%x>\n"
4391 "buffer_info[next_to_clean]\n"
4392 " time_stamp <%lx>\n"
4393 " next_to_watch <%x>\n"
4394 " jiffies <%lx>\n"
4395 " desc.status <%x>\n",
4396 tx_ring->queue_index,
4397 readl(adapter->hw.hw_addr + tx_ring->head),
4398 readl(adapter->hw.hw_addr + tx_ring->tail),
4399 tx_ring->next_to_use,
4400 tx_ring->next_to_clean,
4401 tx_ring->buffer_info[i].time_stamp,
4402 eop,
4403 jiffies,
4404 eop_desc->wb.status);
4405 netif_stop_subqueue(netdev, tx_ring->queue_index);
4406 }
4407 }
4408 tx_ring->total_bytes += total_bytes;
4409 tx_ring->total_packets += total_packets;
4410 tx_ring->tx_stats.bytes += total_bytes;
4411 tx_ring->tx_stats.packets += total_packets;
4412 adapter->net_stats.tx_bytes += total_bytes;
4413 adapter->net_stats.tx_packets += total_packets;
4414 return (count < tx_ring->count);
4415 }
4416
4417 /**
4418 * igb_receive_skb - helper function to handle rx indications
4419 * @ring: pointer to receive ring receving this packet
4420 * @status: descriptor status field as written by hardware
4421 * @rx_desc: receive descriptor containing vlan and type information.
4422 * @skb: pointer to sk_buff to be indicated to stack
4423 **/
4424 static void igb_receive_skb(struct igb_ring *ring, u8 status,
4425 union e1000_adv_rx_desc * rx_desc,
4426 struct sk_buff *skb)
4427 {
4428 struct igb_adapter * adapter = ring->adapter;
4429 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
4430
4431 skb_record_rx_queue(skb, ring->queue_index);
4432 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
4433 if (vlan_extracted)
4434 vlan_gro_receive(&ring->napi, adapter->vlgrp,
4435 le16_to_cpu(rx_desc->wb.upper.vlan),
4436 skb);
4437 else
4438 napi_gro_receive(&ring->napi, skb);
4439 } else {
4440 if (vlan_extracted)
4441 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
4442 le16_to_cpu(rx_desc->wb.upper.vlan));
4443 else
4444 netif_receive_skb(skb);
4445 }
4446 }
4447
4448 static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
4449 u32 status_err, struct sk_buff *skb)
4450 {
4451 skb->ip_summed = CHECKSUM_NONE;
4452
4453 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
4454 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
4455 return;
4456 /* TCP/UDP checksum error bit is set */
4457 if (status_err &
4458 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
4459 /* let the stack verify checksum errors */
4460 adapter->hw_csum_err++;
4461 return;
4462 }
4463 /* It must be a TCP or UDP packet with a valid checksum */
4464 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4465 skb->ip_summed = CHECKSUM_UNNECESSARY;
4466
4467 adapter->hw_csum_good++;
4468 }
4469
4470 static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
4471 int *work_done, int budget)
4472 {
4473 struct igb_adapter *adapter = rx_ring->adapter;
4474 struct net_device *netdev = adapter->netdev;
4475 struct e1000_hw *hw = &adapter->hw;
4476 struct pci_dev *pdev = adapter->pdev;
4477 union e1000_adv_rx_desc *rx_desc , *next_rxd;
4478 struct igb_buffer *buffer_info , *next_buffer;
4479 struct sk_buff *skb;
4480 bool cleaned = false;
4481 int cleaned_count = 0;
4482 unsigned int total_bytes = 0, total_packets = 0;
4483 unsigned int i;
4484 u32 length, hlen, staterr;
4485
4486 i = rx_ring->next_to_clean;
4487 buffer_info = &rx_ring->buffer_info[i];
4488 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4489 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4490
4491 while (staterr & E1000_RXD_STAT_DD) {
4492 if (*work_done >= budget)
4493 break;
4494 (*work_done)++;
4495
4496 skb = buffer_info->skb;
4497 prefetch(skb->data - NET_IP_ALIGN);
4498 buffer_info->skb = NULL;
4499
4500 i++;
4501 if (i == rx_ring->count)
4502 i = 0;
4503 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4504 prefetch(next_rxd);
4505 next_buffer = &rx_ring->buffer_info[i];
4506
4507 length = le16_to_cpu(rx_desc->wb.upper.length);
4508 cleaned = true;
4509 cleaned_count++;
4510
4511 if (!adapter->rx_ps_hdr_size) {
4512 pci_unmap_single(pdev, buffer_info->dma,
4513 adapter->rx_buffer_len +
4514 NET_IP_ALIGN,
4515 PCI_DMA_FROMDEVICE);
4516 skb_put(skb, length);
4517 goto send_up;
4518 }
4519
4520 /* HW will not DMA in data larger than the given buffer, even
4521 * if it parses the (NFS, of course) header to be larger. In
4522 * that case, it fills the header buffer and spills the rest
4523 * into the page.
4524 */
4525 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4526 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4527 if (hlen > adapter->rx_ps_hdr_size)
4528 hlen = adapter->rx_ps_hdr_size;
4529
4530 if (!skb_shinfo(skb)->nr_frags) {
4531 pci_unmap_single(pdev, buffer_info->dma,
4532 adapter->rx_ps_hdr_size + NET_IP_ALIGN,
4533 PCI_DMA_FROMDEVICE);
4534 skb_put(skb, hlen);
4535 }
4536
4537 if (length) {
4538 pci_unmap_page(pdev, buffer_info->page_dma,
4539 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
4540 buffer_info->page_dma = 0;
4541
4542 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4543 buffer_info->page,
4544 buffer_info->page_offset,
4545 length);
4546
4547 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
4548 (page_count(buffer_info->page) != 1))
4549 buffer_info->page = NULL;
4550 else
4551 get_page(buffer_info->page);
4552
4553 skb->len += length;
4554 skb->data_len += length;
4555
4556 skb->truesize += length;
4557 }
4558
4559 if (!(staterr & E1000_RXD_STAT_EOP)) {
4560 buffer_info->skb = next_buffer->skb;
4561 buffer_info->dma = next_buffer->dma;
4562 next_buffer->skb = skb;
4563 next_buffer->dma = 0;
4564 goto next_desc;
4565 }
4566 send_up:
4567 /*
4568 * If this bit is set, then the RX registers contain
4569 * the time stamp. No other packet will be time
4570 * stamped until we read these registers, so read the
4571 * registers to make them available again. Because
4572 * only one packet can be time stamped at a time, we
4573 * know that the register values must belong to this
4574 * one here and therefore we don't need to compare
4575 * any of the additional attributes stored for it.
4576 *
4577 * If nothing went wrong, then it should have a
4578 * skb_shared_tx that we can turn into a
4579 * skb_shared_hwtstamps.
4580 *
4581 * TODO: can time stamping be triggered (thus locking
4582 * the registers) without the packet reaching this point
4583 * here? In that case RX time stamping would get stuck.
4584 *
4585 * TODO: in "time stamp all packets" mode this bit is
4586 * not set. Need a global flag for this mode and then
4587 * always read the registers. Cannot be done without
4588 * a race condition.
4589 */
4590 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4591 u64 regval;
4592 u64 ns;
4593 struct skb_shared_hwtstamps *shhwtstamps =
4594 skb_hwtstamps(skb);
4595
4596 WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4597 "igb: no RX time stamp available for time stamped packet");
4598 regval = rd32(E1000_RXSTMPL);
4599 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4600 ns = timecounter_cyc2time(&adapter->clock, regval);
4601 timecompare_update(&adapter->compare, ns);
4602 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4603 shhwtstamps->hwtstamp = ns_to_ktime(ns);
4604 shhwtstamps->syststamp =
4605 timecompare_transform(&adapter->compare, ns);
4606 }
4607
4608 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4609 dev_kfree_skb_irq(skb);
4610 goto next_desc;
4611 }
4612
4613 total_bytes += skb->len;
4614 total_packets++;
4615
4616 igb_rx_checksum_adv(adapter, staterr, skb);
4617
4618 skb->protocol = eth_type_trans(skb, netdev);
4619
4620 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
4621
4622 next_desc:
4623 rx_desc->wb.upper.status_error = 0;
4624
4625 /* return some buffers to hardware, one at a time is too slow */
4626 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
4627 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4628 cleaned_count = 0;
4629 }
4630
4631 /* use prefetched values */
4632 rx_desc = next_rxd;
4633 buffer_info = next_buffer;
4634 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4635 }
4636
4637 rx_ring->next_to_clean = i;
4638 cleaned_count = igb_desc_unused(rx_ring);
4639
4640 if (cleaned_count)
4641 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4642
4643 rx_ring->total_packets += total_packets;
4644 rx_ring->total_bytes += total_bytes;
4645 rx_ring->rx_stats.packets += total_packets;
4646 rx_ring->rx_stats.bytes += total_bytes;
4647 adapter->net_stats.rx_bytes += total_bytes;
4648 adapter->net_stats.rx_packets += total_packets;
4649 return cleaned;
4650 }
4651
4652 /**
4653 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4654 * @adapter: address of board private structure
4655 **/
4656 static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
4657 int cleaned_count)
4658 {
4659 struct igb_adapter *adapter = rx_ring->adapter;
4660 struct net_device *netdev = adapter->netdev;
4661 struct pci_dev *pdev = adapter->pdev;
4662 union e1000_adv_rx_desc *rx_desc;
4663 struct igb_buffer *buffer_info;
4664 struct sk_buff *skb;
4665 unsigned int i;
4666 int bufsz;
4667
4668 i = rx_ring->next_to_use;
4669 buffer_info = &rx_ring->buffer_info[i];
4670
4671 if (adapter->rx_ps_hdr_size)
4672 bufsz = adapter->rx_ps_hdr_size;
4673 else
4674 bufsz = adapter->rx_buffer_len;
4675 bufsz += NET_IP_ALIGN;
4676
4677 while (cleaned_count--) {
4678 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4679
4680 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
4681 if (!buffer_info->page) {
4682 buffer_info->page = alloc_page(GFP_ATOMIC);
4683 if (!buffer_info->page) {
4684 adapter->alloc_rx_buff_failed++;
4685 goto no_buffers;
4686 }
4687 buffer_info->page_offset = 0;
4688 } else {
4689 buffer_info->page_offset ^= PAGE_SIZE / 2;
4690 }
4691 buffer_info->page_dma =
4692 pci_map_page(pdev, buffer_info->page,
4693 buffer_info->page_offset,
4694 PAGE_SIZE / 2,
4695 PCI_DMA_FROMDEVICE);
4696 }
4697
4698 if (!buffer_info->skb) {
4699 skb = netdev_alloc_skb(netdev, bufsz);
4700 if (!skb) {
4701 adapter->alloc_rx_buff_failed++;
4702 goto no_buffers;
4703 }
4704
4705 /* Make buffer alignment 2 beyond a 16 byte boundary
4706 * this will result in a 16 byte aligned IP header after
4707 * the 14 byte MAC header is removed
4708 */
4709 skb_reserve(skb, NET_IP_ALIGN);
4710
4711 buffer_info->skb = skb;
4712 buffer_info->dma = pci_map_single(pdev, skb->data,
4713 bufsz,
4714 PCI_DMA_FROMDEVICE);
4715 }
4716 /* Refresh the desc even if buffer_addrs didn't change because
4717 * each write-back erases this info. */
4718 if (adapter->rx_ps_hdr_size) {
4719 rx_desc->read.pkt_addr =
4720 cpu_to_le64(buffer_info->page_dma);
4721 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4722 } else {
4723 rx_desc->read.pkt_addr =
4724 cpu_to_le64(buffer_info->dma);
4725 rx_desc->read.hdr_addr = 0;
4726 }
4727
4728 i++;
4729 if (i == rx_ring->count)
4730 i = 0;
4731 buffer_info = &rx_ring->buffer_info[i];
4732 }
4733
4734 no_buffers:
4735 if (rx_ring->next_to_use != i) {
4736 rx_ring->next_to_use = i;
4737 if (i == 0)
4738 i = (rx_ring->count - 1);
4739 else
4740 i--;
4741
4742 /* Force memory writes to complete before letting h/w
4743 * know there are new descriptors to fetch. (Only
4744 * applicable for weak-ordered memory model archs,
4745 * such as IA-64). */
4746 wmb();
4747 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4748 }
4749 }
4750
4751 /**
4752 * igb_mii_ioctl -
4753 * @netdev:
4754 * @ifreq:
4755 * @cmd:
4756 **/
4757 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4758 {
4759 struct igb_adapter *adapter = netdev_priv(netdev);
4760 struct mii_ioctl_data *data = if_mii(ifr);
4761
4762 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4763 return -EOPNOTSUPP;
4764
4765 switch (cmd) {
4766 case SIOCGMIIPHY:
4767 data->phy_id = adapter->hw.phy.addr;
4768 break;
4769 case SIOCGMIIREG:
4770 if (!capable(CAP_NET_ADMIN))
4771 return -EPERM;
4772 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4773 &data->val_out))
4774 return -EIO;
4775 break;
4776 case SIOCSMIIREG:
4777 default:
4778 return -EOPNOTSUPP;
4779 }
4780 return 0;
4781 }
4782
4783 /**
4784 * igb_hwtstamp_ioctl - control hardware time stamping
4785 * @netdev:
4786 * @ifreq:
4787 * @cmd:
4788 *
4789 * Outgoing time stamping can be enabled and disabled. Play nice and
4790 * disable it when requested, although it shouldn't case any overhead
4791 * when no packet needs it. At most one packet in the queue may be
4792 * marked for time stamping, otherwise it would be impossible to tell
4793 * for sure to which packet the hardware time stamp belongs.
4794 *
4795 * Incoming time stamping has to be configured via the hardware
4796 * filters. Not all combinations are supported, in particular event
4797 * type has to be specified. Matching the kind of event packet is
4798 * not supported, with the exception of "all V2 events regardless of
4799 * level 2 or 4".
4800 *
4801 **/
4802 static int igb_hwtstamp_ioctl(struct net_device *netdev,
4803 struct ifreq *ifr, int cmd)
4804 {
4805 struct igb_adapter *adapter = netdev_priv(netdev);
4806 struct e1000_hw *hw = &adapter->hw;
4807 struct hwtstamp_config config;
4808 u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4809 u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
4810 u32 tsync_rx_ctl_type = 0;
4811 u32 tsync_rx_cfg = 0;
4812 int is_l4 = 0;
4813 int is_l2 = 0;
4814 short port = 319; /* PTP */
4815 u32 regval;
4816
4817 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4818 return -EFAULT;
4819
4820 /* reserved for future extensions */
4821 if (config.flags)
4822 return -EINVAL;
4823
4824 switch (config.tx_type) {
4825 case HWTSTAMP_TX_OFF:
4826 tsync_tx_ctl_bit = 0;
4827 break;
4828 case HWTSTAMP_TX_ON:
4829 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4830 break;
4831 default:
4832 return -ERANGE;
4833 }
4834
4835 switch (config.rx_filter) {
4836 case HWTSTAMP_FILTER_NONE:
4837 tsync_rx_ctl_bit = 0;
4838 break;
4839 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4840 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4841 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4842 case HWTSTAMP_FILTER_ALL:
4843 /*
4844 * register TSYNCRXCFG must be set, therefore it is not
4845 * possible to time stamp both Sync and Delay_Req messages
4846 * => fall back to time stamping all packets
4847 */
4848 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
4849 config.rx_filter = HWTSTAMP_FILTER_ALL;
4850 break;
4851 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4852 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4853 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
4854 is_l4 = 1;
4855 break;
4856 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4857 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4858 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
4859 is_l4 = 1;
4860 break;
4861 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4862 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4863 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4864 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
4865 is_l2 = 1;
4866 is_l4 = 1;
4867 config.rx_filter = HWTSTAMP_FILTER_SOME;
4868 break;
4869 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4870 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4871 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4872 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
4873 is_l2 = 1;
4874 is_l4 = 1;
4875 config.rx_filter = HWTSTAMP_FILTER_SOME;
4876 break;
4877 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4878 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4879 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4880 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
4881 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
4882 is_l2 = 1;
4883 break;
4884 default:
4885 return -ERANGE;
4886 }
4887
4888 /* enable/disable TX */
4889 regval = rd32(E1000_TSYNCTXCTL);
4890 regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
4891 wr32(E1000_TSYNCTXCTL, regval);
4892
4893 /* enable/disable RX, define which PTP packets are time stamped */
4894 regval = rd32(E1000_TSYNCRXCTL);
4895 regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
4896 regval = (regval & ~0xE) | tsync_rx_ctl_type;
4897 wr32(E1000_TSYNCRXCTL, regval);
4898 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
4899
4900 /*
4901 * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
4902 * (Ethertype to filter on)
4903 * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
4904 * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
4905 */
4906 wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
4907
4908 /* L4 Queue Filter[0]: only filter by source and destination port */
4909 wr32(E1000_SPQF0, htons(port));
4910 wr32(E1000_IMIREXT(0), is_l4 ?
4911 ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
4912 wr32(E1000_IMIR(0), is_l4 ?
4913 (htons(port)
4914 | (0<<16) /* immediate interrupt disabled */
4915 | 0 /* (1<<17) bit cleared: do not bypass
4916 destination port check */)
4917 : 0);
4918 wr32(E1000_FTQF0, is_l4 ?
4919 (0x11 /* UDP */
4920 | (1<<15) /* VF not compared */
4921 | (1<<27) /* Enable Timestamping */
4922 | (7<<28) /* only source port filter enabled,
4923 source/target address and protocol
4924 masked */)
4925 : ((1<<15) | (15<<28) /* all mask bits set = filter not
4926 enabled */));
4927
4928 wrfl();
4929
4930 adapter->hwtstamp_config = config;
4931
4932 /* clear TX/RX time stamp registers, just to be sure */
4933 regval = rd32(E1000_TXSTMPH);
4934 regval = rd32(E1000_RXSTMPH);
4935
4936 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
4937 -EFAULT : 0;
4938 }
4939
4940 /**
4941 * igb_ioctl -
4942 * @netdev:
4943 * @ifreq:
4944 * @cmd:
4945 **/
4946 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4947 {
4948 switch (cmd) {
4949 case SIOCGMIIPHY:
4950 case SIOCGMIIREG:
4951 case SIOCSMIIREG:
4952 return igb_mii_ioctl(netdev, ifr, cmd);
4953 case SIOCSHWTSTAMP:
4954 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
4955 default:
4956 return -EOPNOTSUPP;
4957 }
4958 }
4959
4960 static void igb_vlan_rx_register(struct net_device *netdev,
4961 struct vlan_group *grp)
4962 {
4963 struct igb_adapter *adapter = netdev_priv(netdev);
4964 struct e1000_hw *hw = &adapter->hw;
4965 u32 ctrl, rctl;
4966
4967 igb_irq_disable(adapter);
4968 adapter->vlgrp = grp;
4969
4970 if (grp) {
4971 /* enable VLAN tag insert/strip */
4972 ctrl = rd32(E1000_CTRL);
4973 ctrl |= E1000_CTRL_VME;
4974 wr32(E1000_CTRL, ctrl);
4975
4976 /* enable VLAN receive filtering */
4977 rctl = rd32(E1000_RCTL);
4978 rctl &= ~E1000_RCTL_CFIEN;
4979 wr32(E1000_RCTL, rctl);
4980 igb_update_mng_vlan(adapter);
4981 } else {
4982 /* disable VLAN tag insert/strip */
4983 ctrl = rd32(E1000_CTRL);
4984 ctrl &= ~E1000_CTRL_VME;
4985 wr32(E1000_CTRL, ctrl);
4986
4987 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4988 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4989 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4990 }
4991 }
4992
4993 igb_rlpml_set(adapter);
4994
4995 if (!test_bit(__IGB_DOWN, &adapter->state))
4996 igb_irq_enable(adapter);
4997 }
4998
4999 static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
5000 {
5001 struct igb_adapter *adapter = netdev_priv(netdev);
5002 struct e1000_hw *hw = &adapter->hw;
5003 int pf_id = adapter->vfs_allocated_count;
5004
5005 if ((hw->mng_cookie.status &
5006 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5007 (vid == adapter->mng_vlan_id))
5008 return;
5009
5010 /* add vid to vlvf if sr-iov is enabled,
5011 * if that fails add directly to filter table */
5012 if (igb_vlvf_set(adapter, vid, true, pf_id))
5013 igb_vfta_set(hw, vid, true);
5014
5015 }
5016
5017 static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
5018 {
5019 struct igb_adapter *adapter = netdev_priv(netdev);
5020 struct e1000_hw *hw = &adapter->hw;
5021 int pf_id = adapter->vfs_allocated_count;
5022
5023 igb_irq_disable(adapter);
5024 vlan_group_set_device(adapter->vlgrp, vid, NULL);
5025
5026 if (!test_bit(__IGB_DOWN, &adapter->state))
5027 igb_irq_enable(adapter);
5028
5029 if ((adapter->hw.mng_cookie.status &
5030 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5031 (vid == adapter->mng_vlan_id)) {
5032 /* release control to f/w */
5033 igb_release_hw_control(adapter);
5034 return;
5035 }
5036
5037 /* remove vid from vlvf if sr-iov is enabled,
5038 * if not in vlvf remove from vfta */
5039 if (igb_vlvf_set(adapter, vid, false, pf_id))
5040 igb_vfta_set(hw, vid, false);
5041 }
5042
5043 static void igb_restore_vlan(struct igb_adapter *adapter)
5044 {
5045 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5046
5047 if (adapter->vlgrp) {
5048 u16 vid;
5049 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5050 if (!vlan_group_get_device(adapter->vlgrp, vid))
5051 continue;
5052 igb_vlan_rx_add_vid(adapter->netdev, vid);
5053 }
5054 }
5055 }
5056
5057 int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5058 {
5059 struct e1000_mac_info *mac = &adapter->hw.mac;
5060
5061 mac->autoneg = 0;
5062
5063 /* Fiber NICs only allow 1000 gbps Full duplex */
5064 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
5065 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
5066 dev_err(&adapter->pdev->dev,
5067 "Unsupported Speed/Duplex configuration\n");
5068 return -EINVAL;
5069 }
5070
5071 switch (spddplx) {
5072 case SPEED_10 + DUPLEX_HALF:
5073 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5074 break;
5075 case SPEED_10 + DUPLEX_FULL:
5076 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5077 break;
5078 case SPEED_100 + DUPLEX_HALF:
5079 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5080 break;
5081 case SPEED_100 + DUPLEX_FULL:
5082 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5083 break;
5084 case SPEED_1000 + DUPLEX_FULL:
5085 mac->autoneg = 1;
5086 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5087 break;
5088 case SPEED_1000 + DUPLEX_HALF: /* not supported */
5089 default:
5090 dev_err(&adapter->pdev->dev,
5091 "Unsupported Speed/Duplex configuration\n");
5092 return -EINVAL;
5093 }
5094 return 0;
5095 }
5096
5097 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
5098 {
5099 struct net_device *netdev = pci_get_drvdata(pdev);
5100 struct igb_adapter *adapter = netdev_priv(netdev);
5101 struct e1000_hw *hw = &adapter->hw;
5102 u32 ctrl, rctl, status;
5103 u32 wufc = adapter->wol;
5104 #ifdef CONFIG_PM
5105 int retval = 0;
5106 #endif
5107
5108 netif_device_detach(netdev);
5109
5110 if (netif_running(netdev))
5111 igb_close(netdev);
5112
5113 igb_reset_interrupt_capability(adapter);
5114
5115 igb_free_queues(adapter);
5116
5117 #ifdef CONFIG_PM
5118 retval = pci_save_state(pdev);
5119 if (retval)
5120 return retval;
5121 #endif
5122
5123 status = rd32(E1000_STATUS);
5124 if (status & E1000_STATUS_LU)
5125 wufc &= ~E1000_WUFC_LNKC;
5126
5127 if (wufc) {
5128 igb_setup_rctl(adapter);
5129 igb_set_multi(netdev);
5130
5131 /* turn on all-multi mode if wake on multicast is enabled */
5132 if (wufc & E1000_WUFC_MC) {
5133 rctl = rd32(E1000_RCTL);
5134 rctl |= E1000_RCTL_MPE;
5135 wr32(E1000_RCTL, rctl);
5136 }
5137
5138 ctrl = rd32(E1000_CTRL);
5139 /* advertise wake from D3Cold */
5140 #define E1000_CTRL_ADVD3WUC 0x00100000
5141 /* phy power management enable */
5142 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5143 ctrl |= E1000_CTRL_ADVD3WUC;
5144 wr32(E1000_CTRL, ctrl);
5145
5146 /* Allow time for pending master requests to run */
5147 igb_disable_pcie_master(&adapter->hw);
5148
5149 wr32(E1000_WUC, E1000_WUC_PME_EN);
5150 wr32(E1000_WUFC, wufc);
5151 } else {
5152 wr32(E1000_WUC, 0);
5153 wr32(E1000_WUFC, 0);
5154 }
5155
5156 *enable_wake = wufc || adapter->en_mng_pt;
5157 if (!*enable_wake)
5158 igb_shutdown_fiber_serdes_link_82575(hw);
5159
5160 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5161 * would have already happened in close and is redundant. */
5162 igb_release_hw_control(adapter);
5163
5164 pci_disable_device(pdev);
5165
5166 return 0;
5167 }
5168
5169 #ifdef CONFIG_PM
5170 static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5171 {
5172 int retval;
5173 bool wake;
5174
5175 retval = __igb_shutdown(pdev, &wake);
5176 if (retval)
5177 return retval;
5178
5179 if (wake) {
5180 pci_prepare_to_sleep(pdev);
5181 } else {
5182 pci_wake_from_d3(pdev, false);
5183 pci_set_power_state(pdev, PCI_D3hot);
5184 }
5185
5186 return 0;
5187 }
5188
5189 static int igb_resume(struct pci_dev *pdev)
5190 {
5191 struct net_device *netdev = pci_get_drvdata(pdev);
5192 struct igb_adapter *adapter = netdev_priv(netdev);
5193 struct e1000_hw *hw = &adapter->hw;
5194 u32 err;
5195
5196 pci_set_power_state(pdev, PCI_D0);
5197 pci_restore_state(pdev);
5198
5199 err = pci_enable_device_mem(pdev);
5200 if (err) {
5201 dev_err(&pdev->dev,
5202 "igb: Cannot enable PCI device from suspend\n");
5203 return err;
5204 }
5205 pci_set_master(pdev);
5206
5207 pci_enable_wake(pdev, PCI_D3hot, 0);
5208 pci_enable_wake(pdev, PCI_D3cold, 0);
5209
5210 igb_set_interrupt_capability(adapter);
5211
5212 if (igb_alloc_queues(adapter)) {
5213 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5214 return -ENOMEM;
5215 }
5216
5217 /* e1000_power_up_phy(adapter); */
5218
5219 igb_reset(adapter);
5220
5221 /* let the f/w know that the h/w is now under the control of the
5222 * driver. */
5223 igb_get_hw_control(adapter);
5224
5225 wr32(E1000_WUS, ~0);
5226
5227 if (netif_running(netdev)) {
5228 err = igb_open(netdev);
5229 if (err)
5230 return err;
5231 }
5232
5233 netif_device_attach(netdev);
5234
5235 return 0;
5236 }
5237 #endif
5238
5239 static void igb_shutdown(struct pci_dev *pdev)
5240 {
5241 bool wake;
5242
5243 __igb_shutdown(pdev, &wake);
5244
5245 if (system_state == SYSTEM_POWER_OFF) {
5246 pci_wake_from_d3(pdev, wake);
5247 pci_set_power_state(pdev, PCI_D3hot);
5248 }
5249 }
5250
5251 #ifdef CONFIG_NET_POLL_CONTROLLER
5252 /*
5253 * Polling 'interrupt' - used by things like netconsole to send skbs
5254 * without having to re-enable interrupts. It's not called while
5255 * the interrupt routine is executing.
5256 */
5257 static void igb_netpoll(struct net_device *netdev)
5258 {
5259 struct igb_adapter *adapter = netdev_priv(netdev);
5260 struct e1000_hw *hw = &adapter->hw;
5261 int i;
5262
5263 if (!adapter->msix_entries) {
5264 igb_irq_disable(adapter);
5265 napi_schedule(&adapter->rx_ring[0].napi);
5266 return;
5267 }
5268
5269 for (i = 0; i < adapter->num_tx_queues; i++) {
5270 struct igb_ring *tx_ring = &adapter->tx_ring[i];
5271 wr32(E1000_EIMC, tx_ring->eims_value);
5272 igb_clean_tx_irq(tx_ring);
5273 wr32(E1000_EIMS, tx_ring->eims_value);
5274 }
5275
5276 for (i = 0; i < adapter->num_rx_queues; i++) {
5277 struct igb_ring *rx_ring = &adapter->rx_ring[i];
5278 wr32(E1000_EIMC, rx_ring->eims_value);
5279 napi_schedule(&rx_ring->napi);
5280 }
5281 }
5282 #endif /* CONFIG_NET_POLL_CONTROLLER */
5283
5284 /**
5285 * igb_io_error_detected - called when PCI error is detected
5286 * @pdev: Pointer to PCI device
5287 * @state: The current pci connection state
5288 *
5289 * This function is called after a PCI bus error affecting
5290 * this device has been detected.
5291 */
5292 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5293 pci_channel_state_t state)
5294 {
5295 struct net_device *netdev = pci_get_drvdata(pdev);
5296 struct igb_adapter *adapter = netdev_priv(netdev);
5297
5298 netif_device_detach(netdev);
5299
5300 if (netif_running(netdev))
5301 igb_down(adapter);
5302 pci_disable_device(pdev);
5303
5304 /* Request a slot slot reset. */
5305 return PCI_ERS_RESULT_NEED_RESET;
5306 }
5307
5308 /**
5309 * igb_io_slot_reset - called after the pci bus has been reset.
5310 * @pdev: Pointer to PCI device
5311 *
5312 * Restart the card from scratch, as if from a cold-boot. Implementation
5313 * resembles the first-half of the igb_resume routine.
5314 */
5315 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5316 {
5317 struct net_device *netdev = pci_get_drvdata(pdev);
5318 struct igb_adapter *adapter = netdev_priv(netdev);
5319 struct e1000_hw *hw = &adapter->hw;
5320 pci_ers_result_t result;
5321 int err;
5322
5323 if (pci_enable_device_mem(pdev)) {
5324 dev_err(&pdev->dev,
5325 "Cannot re-enable PCI device after reset.\n");
5326 result = PCI_ERS_RESULT_DISCONNECT;
5327 } else {
5328 pci_set_master(pdev);
5329 pci_restore_state(pdev);
5330
5331 pci_enable_wake(pdev, PCI_D3hot, 0);
5332 pci_enable_wake(pdev, PCI_D3cold, 0);
5333
5334 igb_reset(adapter);
5335 wr32(E1000_WUS, ~0);
5336 result = PCI_ERS_RESULT_RECOVERED;
5337 }
5338
5339 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5340 if (err) {
5341 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5342 "failed 0x%0x\n", err);
5343 /* non-fatal, continue */
5344 }
5345
5346 return result;
5347 }
5348
5349 /**
5350 * igb_io_resume - called when traffic can start flowing again.
5351 * @pdev: Pointer to PCI device
5352 *
5353 * This callback is called when the error recovery driver tells us that
5354 * its OK to resume normal operation. Implementation resembles the
5355 * second-half of the igb_resume routine.
5356 */
5357 static void igb_io_resume(struct pci_dev *pdev)
5358 {
5359 struct net_device *netdev = pci_get_drvdata(pdev);
5360 struct igb_adapter *adapter = netdev_priv(netdev);
5361
5362 if (netif_running(netdev)) {
5363 if (igb_up(adapter)) {
5364 dev_err(&pdev->dev, "igb_up failed after reset\n");
5365 return;
5366 }
5367 }
5368
5369 netif_device_attach(netdev);
5370
5371 /* let the f/w know that the h/w is now under the control of the
5372 * driver. */
5373 igb_get_hw_control(adapter);
5374 }
5375
5376 static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
5377 {
5378 u32 reg_data;
5379
5380 reg_data = rd32(E1000_VMOLR(vfn));
5381 reg_data |= E1000_VMOLR_BAM | /* Accept broadcast */
5382 E1000_VMOLR_ROPE | /* Accept packets matched in UTA */
5383 E1000_VMOLR_ROMPE | /* Accept packets matched in MTA */
5384 E1000_VMOLR_AUPE | /* Accept untagged packets */
5385 E1000_VMOLR_STRVLAN; /* Strip vlan tags */
5386 wr32(E1000_VMOLR(vfn), reg_data);
5387 }
5388
5389 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
5390 int vfn)
5391 {
5392 struct e1000_hw *hw = &adapter->hw;
5393 u32 vmolr;
5394
5395 vmolr = rd32(E1000_VMOLR(vfn));
5396 vmolr &= ~E1000_VMOLR_RLPML_MASK;
5397 vmolr |= size | E1000_VMOLR_LPE;
5398 wr32(E1000_VMOLR(vfn), vmolr);
5399
5400 return 0;
5401 }
5402
5403 static inline void igb_set_rah_pool(struct e1000_hw *hw, int pool, int entry)
5404 {
5405 u32 reg_data;
5406
5407 reg_data = rd32(E1000_RAH(entry));
5408 reg_data &= ~E1000_RAH_POOL_MASK;
5409 reg_data |= E1000_RAH_POOL_1 << pool;;
5410 wr32(E1000_RAH(entry), reg_data);
5411 }
5412
5413 static void igb_set_mc_list_pools(struct igb_adapter *adapter,
5414 int entry_count, u16 total_rar_filters)
5415 {
5416 struct e1000_hw *hw = &adapter->hw;
5417 int i = adapter->vfs_allocated_count + 1;
5418
5419 if ((i + entry_count) < total_rar_filters)
5420 total_rar_filters = i + entry_count;
5421
5422 for (; i < total_rar_filters; i++)
5423 igb_set_rah_pool(hw, adapter->vfs_allocated_count, i);
5424 }
5425
5426 static int igb_set_vf_mac(struct igb_adapter *adapter,
5427 int vf, unsigned char *mac_addr)
5428 {
5429 struct e1000_hw *hw = &adapter->hw;
5430 int rar_entry = vf + 1; /* VF MAC addresses start at entry 1 */
5431
5432 igb_rar_set(hw, mac_addr, rar_entry);
5433
5434 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
5435
5436 igb_set_rah_pool(hw, vf, rar_entry);
5437
5438 return 0;
5439 }
5440
5441 static void igb_vmm_control(struct igb_adapter *adapter)
5442 {
5443 struct e1000_hw *hw = &adapter->hw;
5444 u32 reg_data;
5445
5446 if (!adapter->vfs_allocated_count)
5447 return;
5448
5449 /* VF's need PF reset indication before they
5450 * can send/receive mail */
5451 reg_data = rd32(E1000_CTRL_EXT);
5452 reg_data |= E1000_CTRL_EXT_PFRSTD;
5453 wr32(E1000_CTRL_EXT, reg_data);
5454
5455 igb_vmdq_set_loopback_pf(hw, true);
5456 igb_vmdq_set_replication_pf(hw, true);
5457 }
5458
5459 /* igb_main.c */
Linux kernel - Deliverables
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