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Merge branch 'davem-next' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik...
[deliverable/linux.git] / drivers / net / igb / igb_main.c
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/module.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/vmalloc.h>
32 #include <linux/pagemap.h>
33 #include <linux/netdevice.h>
34 #include <linux/ipv6.h>
35 #include <net/checksum.h>
36 #include <net/ip6_checksum.h>
37 #include <linux/mii.h>
38 #include <linux/ethtool.h>
39 #include <linux/if_vlan.h>
40 #include <linux/pci.h>
41 #include <linux/delay.h>
42 #include <linux/interrupt.h>
43 #include <linux/if_ether.h>
44
45 #include "igb.h"
46
47 #define DRV_VERSION "1.0.8-k2"
48 char igb_driver_name[] = "igb";
49 char igb_driver_version[] = DRV_VERSION;
50 static const char igb_driver_string[] =
51 "Intel(R) Gigabit Ethernet Network Driver";
52 static const char igb_copyright[] = "Copyright (c) 2007 Intel Corporation.";
53
54
55 static const struct e1000_info *igb_info_tbl[] = {
56 [board_82575] = &e1000_82575_info,
57 };
58
59 static struct pci_device_id igb_pci_tbl[] = {
60 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
61 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
62 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
63 /* required last entry */
64 {0, }
65 };
66
67 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
68
69 void igb_reset(struct igb_adapter *);
70 static int igb_setup_all_tx_resources(struct igb_adapter *);
71 static int igb_setup_all_rx_resources(struct igb_adapter *);
72 static void igb_free_all_tx_resources(struct igb_adapter *);
73 static void igb_free_all_rx_resources(struct igb_adapter *);
74 static void igb_free_tx_resources(struct igb_ring *);
75 static void igb_free_rx_resources(struct igb_ring *);
76 void igb_update_stats(struct igb_adapter *);
77 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
78 static void __devexit igb_remove(struct pci_dev *pdev);
79 static int igb_sw_init(struct igb_adapter *);
80 static int igb_open(struct net_device *);
81 static int igb_close(struct net_device *);
82 static void igb_configure_tx(struct igb_adapter *);
83 static void igb_configure_rx(struct igb_adapter *);
84 static void igb_setup_rctl(struct igb_adapter *);
85 static void igb_clean_all_tx_rings(struct igb_adapter *);
86 static void igb_clean_all_rx_rings(struct igb_adapter *);
87 static void igb_clean_tx_ring(struct igb_ring *);
88 static void igb_clean_rx_ring(struct igb_ring *);
89 static void igb_set_multi(struct net_device *);
90 static void igb_update_phy_info(unsigned long);
91 static void igb_watchdog(unsigned long);
92 static void igb_watchdog_task(struct work_struct *);
93 static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
94 struct igb_ring *);
95 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
96 static struct net_device_stats *igb_get_stats(struct net_device *);
97 static int igb_change_mtu(struct net_device *, int);
98 static int igb_set_mac(struct net_device *, void *);
99 static irqreturn_t igb_intr(int irq, void *);
100 static irqreturn_t igb_intr_msi(int irq, void *);
101 static irqreturn_t igb_msix_other(int irq, void *);
102 static irqreturn_t igb_msix_rx(int irq, void *);
103 static irqreturn_t igb_msix_tx(int irq, void *);
104 static int igb_clean_rx_ring_msix(struct napi_struct *, int);
105 static bool igb_clean_tx_irq(struct igb_ring *);
106 static int igb_clean(struct napi_struct *, int);
107 static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
108 static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
109 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
110 static void igb_tx_timeout(struct net_device *);
111 static void igb_reset_task(struct work_struct *);
112 static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
113 static void igb_vlan_rx_add_vid(struct net_device *, u16);
114 static void igb_vlan_rx_kill_vid(struct net_device *, u16);
115 static void igb_restore_vlan(struct igb_adapter *);
116
117 static int igb_suspend(struct pci_dev *, pm_message_t);
118 #ifdef CONFIG_PM
119 static int igb_resume(struct pci_dev *);
120 #endif
121 static void igb_shutdown(struct pci_dev *);
122
123 #ifdef CONFIG_NET_POLL_CONTROLLER
124 /* for netdump / net console */
125 static void igb_netpoll(struct net_device *);
126 #endif
127
128 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
129 pci_channel_state_t);
130 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
131 static void igb_io_resume(struct pci_dev *);
132
133 static struct pci_error_handlers igb_err_handler = {
134 .error_detected = igb_io_error_detected,
135 .slot_reset = igb_io_slot_reset,
136 .resume = igb_io_resume,
137 };
138
139
140 static struct pci_driver igb_driver = {
141 .name = igb_driver_name,
142 .id_table = igb_pci_tbl,
143 .probe = igb_probe,
144 .remove = __devexit_p(igb_remove),
145 #ifdef CONFIG_PM
146 /* Power Managment Hooks */
147 .suspend = igb_suspend,
148 .resume = igb_resume,
149 #endif
150 .shutdown = igb_shutdown,
151 .err_handler = &igb_err_handler
152 };
153
154 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
155 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
156 MODULE_LICENSE("GPL");
157 MODULE_VERSION(DRV_VERSION);
158
159 #ifdef DEBUG
160 /**
161 * igb_get_hw_dev_name - return device name string
162 * used by hardware layer to print debugging information
163 **/
164 char *igb_get_hw_dev_name(struct e1000_hw *hw)
165 {
166 struct igb_adapter *adapter = hw->back;
167 return adapter->netdev->name;
168 }
169 #endif
170
171 /**
172 * igb_init_module - Driver Registration Routine
173 *
174 * igb_init_module is the first routine called when the driver is
175 * loaded. All it does is register with the PCI subsystem.
176 **/
177 static int __init igb_init_module(void)
178 {
179 int ret;
180 printk(KERN_INFO "%s - version %s\n",
181 igb_driver_string, igb_driver_version);
182
183 printk(KERN_INFO "%s\n", igb_copyright);
184
185 ret = pci_register_driver(&igb_driver);
186 return ret;
187 }
188
189 module_init(igb_init_module);
190
191 /**
192 * igb_exit_module - Driver Exit Cleanup Routine
193 *
194 * igb_exit_module is called just before the driver is removed
195 * from memory.
196 **/
197 static void __exit igb_exit_module(void)
198 {
199 pci_unregister_driver(&igb_driver);
200 }
201
202 module_exit(igb_exit_module);
203
204 /**
205 * igb_alloc_queues - Allocate memory for all rings
206 * @adapter: board private structure to initialize
207 *
208 * We allocate one ring per queue at run-time since we don't know the
209 * number of queues at compile-time.
210 **/
211 static int igb_alloc_queues(struct igb_adapter *adapter)
212 {
213 int i;
214
215 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
216 sizeof(struct igb_ring), GFP_KERNEL);
217 if (!adapter->tx_ring)
218 return -ENOMEM;
219
220 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
221 sizeof(struct igb_ring), GFP_KERNEL);
222 if (!adapter->rx_ring) {
223 kfree(adapter->tx_ring);
224 return -ENOMEM;
225 }
226
227 for (i = 0; i < adapter->num_rx_queues; i++) {
228 struct igb_ring *ring = &(adapter->rx_ring[i]);
229 ring->adapter = adapter;
230 ring->queue_index = i;
231 ring->itr_register = E1000_ITR;
232
233 /* set a default napi handler for each rx_ring */
234 netif_napi_add(adapter->netdev, &ring->napi, igb_clean, 64);
235 }
236 return 0;
237 }
238
239 #define IGB_N0_QUEUE -1
240 static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
241 int tx_queue, int msix_vector)
242 {
243 u32 msixbm = 0;
244 struct e1000_hw *hw = &adapter->hw;
245 /* The 82575 assigns vectors using a bitmask, which matches the
246 bitmask for the EICR/EIMS/EIMC registers. To assign one
247 or more queues to a vector, we write the appropriate bits
248 into the MSIXBM register for that vector. */
249 if (rx_queue > IGB_N0_QUEUE) {
250 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
251 adapter->rx_ring[rx_queue].eims_value = msixbm;
252 }
253 if (tx_queue > IGB_N0_QUEUE) {
254 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
255 adapter->tx_ring[tx_queue].eims_value =
256 E1000_EICR_TX_QUEUE0 << tx_queue;
257 }
258 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
259 }
260
261 /**
262 * igb_configure_msix - Configure MSI-X hardware
263 *
264 * igb_configure_msix sets up the hardware to properly
265 * generate MSI-X interrupts.
266 **/
267 static void igb_configure_msix(struct igb_adapter *adapter)
268 {
269 u32 tmp;
270 int i, vector = 0;
271 struct e1000_hw *hw = &adapter->hw;
272
273 adapter->eims_enable_mask = 0;
274
275 for (i = 0; i < adapter->num_tx_queues; i++) {
276 struct igb_ring *tx_ring = &adapter->tx_ring[i];
277 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
278 adapter->eims_enable_mask |= tx_ring->eims_value;
279 if (tx_ring->itr_val)
280 writel(1000000000 / (tx_ring->itr_val * 256),
281 hw->hw_addr + tx_ring->itr_register);
282 else
283 writel(1, hw->hw_addr + tx_ring->itr_register);
284 }
285
286 for (i = 0; i < adapter->num_rx_queues; i++) {
287 struct igb_ring *rx_ring = &adapter->rx_ring[i];
288 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
289 adapter->eims_enable_mask |= rx_ring->eims_value;
290 if (rx_ring->itr_val)
291 writel(1000000000 / (rx_ring->itr_val * 256),
292 hw->hw_addr + rx_ring->itr_register);
293 else
294 writel(1, hw->hw_addr + rx_ring->itr_register);
295 }
296
297
298 /* set vector for other causes, i.e. link changes */
299 array_wr32(E1000_MSIXBM(0), vector++,
300 E1000_EIMS_OTHER);
301
302 tmp = rd32(E1000_CTRL_EXT);
303 /* enable MSI-X PBA support*/
304 tmp |= E1000_CTRL_EXT_PBA_CLR;
305
306 /* Auto-Mask interrupts upon ICR read. */
307 tmp |= E1000_CTRL_EXT_EIAME;
308 tmp |= E1000_CTRL_EXT_IRCA;
309
310 wr32(E1000_CTRL_EXT, tmp);
311 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
312 adapter->eims_other = E1000_EIMS_OTHER;
313
314 wrfl();
315 }
316
317 /**
318 * igb_request_msix - Initialize MSI-X interrupts
319 *
320 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
321 * kernel.
322 **/
323 static int igb_request_msix(struct igb_adapter *adapter)
324 {
325 struct net_device *netdev = adapter->netdev;
326 int i, err = 0, vector = 0;
327
328 vector = 0;
329
330 for (i = 0; i < adapter->num_tx_queues; i++) {
331 struct igb_ring *ring = &(adapter->tx_ring[i]);
332 sprintf(ring->name, "%s-tx%d", netdev->name, i);
333 err = request_irq(adapter->msix_entries[vector].vector,
334 &igb_msix_tx, 0, ring->name,
335 &(adapter->tx_ring[i]));
336 if (err)
337 goto out;
338 ring->itr_register = E1000_EITR(0) + (vector << 2);
339 ring->itr_val = adapter->itr;
340 vector++;
341 }
342 for (i = 0; i < adapter->num_rx_queues; i++) {
343 struct igb_ring *ring = &(adapter->rx_ring[i]);
344 if (strlen(netdev->name) < (IFNAMSIZ - 5))
345 sprintf(ring->name, "%s-rx%d", netdev->name, i);
346 else
347 memcpy(ring->name, netdev->name, IFNAMSIZ);
348 err = request_irq(adapter->msix_entries[vector].vector,
349 &igb_msix_rx, 0, ring->name,
350 &(adapter->rx_ring[i]));
351 if (err)
352 goto out;
353 ring->itr_register = E1000_EITR(0) + (vector << 2);
354 ring->itr_val = adapter->itr;
355 /* overwrite the poll routine for MSIX, we've already done
356 * netif_napi_add */
357 ring->napi.poll = &igb_clean_rx_ring_msix;
358 vector++;
359 }
360
361 err = request_irq(adapter->msix_entries[vector].vector,
362 &igb_msix_other, 0, netdev->name, netdev);
363 if (err)
364 goto out;
365
366 igb_configure_msix(adapter);
367 return 0;
368 out:
369 return err;
370 }
371
372 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
373 {
374 if (adapter->msix_entries) {
375 pci_disable_msix(adapter->pdev);
376 kfree(adapter->msix_entries);
377 adapter->msix_entries = NULL;
378 } else if (adapter->msi_enabled)
379 pci_disable_msi(adapter->pdev);
380 return;
381 }
382
383
384 /**
385 * igb_set_interrupt_capability - set MSI or MSI-X if supported
386 *
387 * Attempt to configure interrupts using the best available
388 * capabilities of the hardware and kernel.
389 **/
390 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
391 {
392 int err;
393 int numvecs, i;
394
395 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
396 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
397 GFP_KERNEL);
398 if (!adapter->msix_entries)
399 goto msi_only;
400
401 for (i = 0; i < numvecs; i++)
402 adapter->msix_entries[i].entry = i;
403
404 err = pci_enable_msix(adapter->pdev,
405 adapter->msix_entries,
406 numvecs);
407 if (err == 0)
408 return;
409
410 igb_reset_interrupt_capability(adapter);
411
412 /* If we can't do MSI-X, try MSI */
413 msi_only:
414 adapter->num_rx_queues = 1;
415 if (!pci_enable_msi(adapter->pdev))
416 adapter->msi_enabled = 1;
417 return;
418 }
419
420 /**
421 * igb_request_irq - initialize interrupts
422 *
423 * Attempts to configure interrupts using the best available
424 * capabilities of the hardware and kernel.
425 **/
426 static int igb_request_irq(struct igb_adapter *adapter)
427 {
428 struct net_device *netdev = adapter->netdev;
429 struct e1000_hw *hw = &adapter->hw;
430 int err = 0;
431
432 if (adapter->msix_entries) {
433 err = igb_request_msix(adapter);
434 if (!err)
435 goto request_done;
436 /* fall back to MSI */
437 igb_reset_interrupt_capability(adapter);
438 if (!pci_enable_msi(adapter->pdev))
439 adapter->msi_enabled = 1;
440 igb_free_all_tx_resources(adapter);
441 igb_free_all_rx_resources(adapter);
442 adapter->num_rx_queues = 1;
443 igb_alloc_queues(adapter);
444 } else {
445 wr32(E1000_MSIXBM(0), (E1000_EICR_RX_QUEUE0 |
446 E1000_EIMS_OTHER));
447 }
448
449 if (adapter->msi_enabled) {
450 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
451 netdev->name, netdev);
452 if (!err)
453 goto request_done;
454 /* fall back to legacy interrupts */
455 igb_reset_interrupt_capability(adapter);
456 adapter->msi_enabled = 0;
457 }
458
459 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
460 netdev->name, netdev);
461
462 if (err)
463 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
464 err);
465
466 request_done:
467 return err;
468 }
469
470 static void igb_free_irq(struct igb_adapter *adapter)
471 {
472 struct net_device *netdev = adapter->netdev;
473
474 if (adapter->msix_entries) {
475 int vector = 0, i;
476
477 for (i = 0; i < adapter->num_tx_queues; i++)
478 free_irq(adapter->msix_entries[vector++].vector,
479 &(adapter->tx_ring[i]));
480 for (i = 0; i < adapter->num_rx_queues; i++)
481 free_irq(adapter->msix_entries[vector++].vector,
482 &(adapter->rx_ring[i]));
483
484 free_irq(adapter->msix_entries[vector++].vector, netdev);
485 return;
486 }
487
488 free_irq(adapter->pdev->irq, netdev);
489 }
490
491 /**
492 * igb_irq_disable - Mask off interrupt generation on the NIC
493 * @adapter: board private structure
494 **/
495 static void igb_irq_disable(struct igb_adapter *adapter)
496 {
497 struct e1000_hw *hw = &adapter->hw;
498
499 if (adapter->msix_entries) {
500 wr32(E1000_EIAM, 0);
501 wr32(E1000_EIMC, ~0);
502 wr32(E1000_EIAC, 0);
503 }
504
505 wr32(E1000_IAM, 0);
506 wr32(E1000_IMC, ~0);
507 wrfl();
508 synchronize_irq(adapter->pdev->irq);
509 }
510
511 /**
512 * igb_irq_enable - Enable default interrupt generation settings
513 * @adapter: board private structure
514 **/
515 static void igb_irq_enable(struct igb_adapter *adapter)
516 {
517 struct e1000_hw *hw = &adapter->hw;
518
519 if (adapter->msix_entries) {
520 wr32(E1000_EIAC, adapter->eims_enable_mask);
521 wr32(E1000_EIAM, adapter->eims_enable_mask);
522 wr32(E1000_EIMS, adapter->eims_enable_mask);
523 wr32(E1000_IMS, E1000_IMS_LSC);
524 } else {
525 wr32(E1000_IMS, IMS_ENABLE_MASK);
526 wr32(E1000_IAM, IMS_ENABLE_MASK);
527 }
528 }
529
530 static void igb_update_mng_vlan(struct igb_adapter *adapter)
531 {
532 struct net_device *netdev = adapter->netdev;
533 u16 vid = adapter->hw.mng_cookie.vlan_id;
534 u16 old_vid = adapter->mng_vlan_id;
535 if (adapter->vlgrp) {
536 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
537 if (adapter->hw.mng_cookie.status &
538 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
539 igb_vlan_rx_add_vid(netdev, vid);
540 adapter->mng_vlan_id = vid;
541 } else
542 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
543
544 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
545 (vid != old_vid) &&
546 !vlan_group_get_device(adapter->vlgrp, old_vid))
547 igb_vlan_rx_kill_vid(netdev, old_vid);
548 } else
549 adapter->mng_vlan_id = vid;
550 }
551 }
552
553 /**
554 * igb_release_hw_control - release control of the h/w to f/w
555 * @adapter: address of board private structure
556 *
557 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
558 * For ASF and Pass Through versions of f/w this means that the
559 * driver is no longer loaded.
560 *
561 **/
562 static void igb_release_hw_control(struct igb_adapter *adapter)
563 {
564 struct e1000_hw *hw = &adapter->hw;
565 u32 ctrl_ext;
566
567 /* Let firmware take over control of h/w */
568 ctrl_ext = rd32(E1000_CTRL_EXT);
569 wr32(E1000_CTRL_EXT,
570 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
571 }
572
573
574 /**
575 * igb_get_hw_control - get control of the h/w from f/w
576 * @adapter: address of board private structure
577 *
578 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
579 * For ASF and Pass Through versions of f/w this means that
580 * the driver is loaded.
581 *
582 **/
583 static void igb_get_hw_control(struct igb_adapter *adapter)
584 {
585 struct e1000_hw *hw = &adapter->hw;
586 u32 ctrl_ext;
587
588 /* Let firmware know the driver has taken over */
589 ctrl_ext = rd32(E1000_CTRL_EXT);
590 wr32(E1000_CTRL_EXT,
591 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
592 }
593
594 static void igb_init_manageability(struct igb_adapter *adapter)
595 {
596 struct e1000_hw *hw = &adapter->hw;
597
598 if (adapter->en_mng_pt) {
599 u32 manc2h = rd32(E1000_MANC2H);
600 u32 manc = rd32(E1000_MANC);
601
602 /* enable receiving management packets to the host */
603 /* this will probably generate destination unreachable messages
604 * from the host OS, but the packets will be handled on SMBUS */
605 manc |= E1000_MANC_EN_MNG2HOST;
606 #define E1000_MNG2HOST_PORT_623 (1 << 5)
607 #define E1000_MNG2HOST_PORT_664 (1 << 6)
608 manc2h |= E1000_MNG2HOST_PORT_623;
609 manc2h |= E1000_MNG2HOST_PORT_664;
610 wr32(E1000_MANC2H, manc2h);
611
612 wr32(E1000_MANC, manc);
613 }
614 }
615
616 /**
617 * igb_configure - configure the hardware for RX and TX
618 * @adapter: private board structure
619 **/
620 static void igb_configure(struct igb_adapter *adapter)
621 {
622 struct net_device *netdev = adapter->netdev;
623 int i;
624
625 igb_get_hw_control(adapter);
626 igb_set_multi(netdev);
627
628 igb_restore_vlan(adapter);
629 igb_init_manageability(adapter);
630
631 igb_configure_tx(adapter);
632 igb_setup_rctl(adapter);
633 igb_configure_rx(adapter);
634
635 igb_rx_fifo_flush_82575(&adapter->hw);
636
637 /* call IGB_DESC_UNUSED which always leaves
638 * at least 1 descriptor unused to make sure
639 * next_to_use != next_to_clean */
640 for (i = 0; i < adapter->num_rx_queues; i++) {
641 struct igb_ring *ring = &adapter->rx_ring[i];
642 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
643 }
644
645
646 adapter->tx_queue_len = netdev->tx_queue_len;
647 }
648
649
650 /**
651 * igb_up - Open the interface and prepare it to handle traffic
652 * @adapter: board private structure
653 **/
654
655 int igb_up(struct igb_adapter *adapter)
656 {
657 struct e1000_hw *hw = &adapter->hw;
658 int i;
659
660 /* hardware has been reset, we need to reload some things */
661 igb_configure(adapter);
662
663 clear_bit(__IGB_DOWN, &adapter->state);
664
665 for (i = 0; i < adapter->num_rx_queues; i++)
666 napi_enable(&adapter->rx_ring[i].napi);
667 if (adapter->msix_entries)
668 igb_configure_msix(adapter);
669
670 /* Clear any pending interrupts. */
671 rd32(E1000_ICR);
672 igb_irq_enable(adapter);
673
674 /* Fire a link change interrupt to start the watchdog. */
675 wr32(E1000_ICS, E1000_ICS_LSC);
676 return 0;
677 }
678
679 void igb_down(struct igb_adapter *adapter)
680 {
681 struct e1000_hw *hw = &adapter->hw;
682 struct net_device *netdev = adapter->netdev;
683 u32 tctl, rctl;
684 int i;
685
686 /* signal that we're down so the interrupt handler does not
687 * reschedule our watchdog timer */
688 set_bit(__IGB_DOWN, &adapter->state);
689
690 /* disable receives in the hardware */
691 rctl = rd32(E1000_RCTL);
692 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
693 /* flush and sleep below */
694
695 netif_stop_queue(netdev);
696
697 /* disable transmits in the hardware */
698 tctl = rd32(E1000_TCTL);
699 tctl &= ~E1000_TCTL_EN;
700 wr32(E1000_TCTL, tctl);
701 /* flush both disables and wait for them to finish */
702 wrfl();
703 msleep(10);
704
705 for (i = 0; i < adapter->num_rx_queues; i++)
706 napi_disable(&adapter->rx_ring[i].napi);
707
708 igb_irq_disable(adapter);
709
710 del_timer_sync(&adapter->watchdog_timer);
711 del_timer_sync(&adapter->phy_info_timer);
712
713 netdev->tx_queue_len = adapter->tx_queue_len;
714 netif_carrier_off(netdev);
715 adapter->link_speed = 0;
716 adapter->link_duplex = 0;
717
718 if (!pci_channel_offline(adapter->pdev))
719 igb_reset(adapter);
720 igb_clean_all_tx_rings(adapter);
721 igb_clean_all_rx_rings(adapter);
722 }
723
724 void igb_reinit_locked(struct igb_adapter *adapter)
725 {
726 WARN_ON(in_interrupt());
727 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
728 msleep(1);
729 igb_down(adapter);
730 igb_up(adapter);
731 clear_bit(__IGB_RESETTING, &adapter->state);
732 }
733
734 void igb_reset(struct igb_adapter *adapter)
735 {
736 struct e1000_hw *hw = &adapter->hw;
737 struct e1000_fc_info *fc = &adapter->hw.fc;
738 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
739 u16 hwm;
740
741 /* Repartition Pba for greater than 9k mtu
742 * To take effect CTRL.RST is required.
743 */
744 pba = E1000_PBA_34K;
745
746 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
747 /* adjust PBA for jumbo frames */
748 wr32(E1000_PBA, pba);
749
750 /* To maintain wire speed transmits, the Tx FIFO should be
751 * large enough to accommodate two full transmit packets,
752 * rounded up to the next 1KB and expressed in KB. Likewise,
753 * the Rx FIFO should be large enough to accommodate at least
754 * one full receive packet and is similarly rounded up and
755 * expressed in KB. */
756 pba = rd32(E1000_PBA);
757 /* upper 16 bits has Tx packet buffer allocation size in KB */
758 tx_space = pba >> 16;
759 /* lower 16 bits has Rx packet buffer allocation size in KB */
760 pba &= 0xffff;
761 /* the tx fifo also stores 16 bytes of information about the tx
762 * but don't include ethernet FCS because hardware appends it */
763 min_tx_space = (adapter->max_frame_size +
764 sizeof(struct e1000_tx_desc) -
765 ETH_FCS_LEN) * 2;
766 min_tx_space = ALIGN(min_tx_space, 1024);
767 min_tx_space >>= 10;
768 /* software strips receive CRC, so leave room for it */
769 min_rx_space = adapter->max_frame_size;
770 min_rx_space = ALIGN(min_rx_space, 1024);
771 min_rx_space >>= 10;
772
773 /* If current Tx allocation is less than the min Tx FIFO size,
774 * and the min Tx FIFO size is less than the current Rx FIFO
775 * allocation, take space away from current Rx allocation */
776 if (tx_space < min_tx_space &&
777 ((min_tx_space - tx_space) < pba)) {
778 pba = pba - (min_tx_space - tx_space);
779
780 /* if short on rx space, rx wins and must trump tx
781 * adjustment */
782 if (pba < min_rx_space)
783 pba = min_rx_space;
784 }
785 }
786 wr32(E1000_PBA, pba);
787
788 /* flow control settings */
789 /* The high water mark must be low enough to fit one full frame
790 * (or the size used for early receive) above it in the Rx FIFO.
791 * Set it to the lower of:
792 * - 90% of the Rx FIFO size, or
793 * - the full Rx FIFO size minus one full frame */
794 hwm = min(((pba << 10) * 9 / 10),
795 ((pba << 10) - adapter->max_frame_size));
796
797 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
798 fc->low_water = fc->high_water - 8;
799 fc->pause_time = 0xFFFF;
800 fc->send_xon = 1;
801 fc->type = fc->original_type;
802
803 /* Allow time for pending master requests to run */
804 adapter->hw.mac.ops.reset_hw(&adapter->hw);
805 wr32(E1000_WUC, 0);
806
807 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
808 dev_err(&adapter->pdev->dev, "Hardware Error\n");
809
810 igb_update_mng_vlan(adapter);
811
812 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
813 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
814
815 igb_reset_adaptive(&adapter->hw);
816 if (adapter->hw.phy.ops.get_phy_info)
817 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
818 }
819
820 /**
821 * igb_is_need_ioport - determine if an adapter needs ioport resources or not
822 * @pdev: PCI device information struct
823 *
824 * Returns true if an adapter needs ioport resources
825 **/
826 static int igb_is_need_ioport(struct pci_dev *pdev)
827 {
828 switch (pdev->device) {
829 /* Currently there are no adapters that need ioport resources */
830 default:
831 return false;
832 }
833 }
834
835 /**
836 * igb_probe - Device Initialization Routine
837 * @pdev: PCI device information struct
838 * @ent: entry in igb_pci_tbl
839 *
840 * Returns 0 on success, negative on failure
841 *
842 * igb_probe initializes an adapter identified by a pci_dev structure.
843 * The OS initialization, configuring of the adapter private structure,
844 * and a hardware reset occur.
845 **/
846 static int __devinit igb_probe(struct pci_dev *pdev,
847 const struct pci_device_id *ent)
848 {
849 struct net_device *netdev;
850 struct igb_adapter *adapter;
851 struct e1000_hw *hw;
852 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
853 unsigned long mmio_start, mmio_len;
854 int i, err, pci_using_dac;
855 u16 eeprom_data = 0;
856 u16 eeprom_apme_mask = IGB_EEPROM_APME;
857 u32 part_num;
858 int bars, need_ioport;
859
860 /* do not allocate ioport bars when not needed */
861 need_ioport = igb_is_need_ioport(pdev);
862 if (need_ioport) {
863 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
864 err = pci_enable_device(pdev);
865 } else {
866 bars = pci_select_bars(pdev, IORESOURCE_MEM);
867 err = pci_enable_device_mem(pdev);
868 }
869 if (err)
870 return err;
871
872 pci_using_dac = 0;
873 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
874 if (!err) {
875 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
876 if (!err)
877 pci_using_dac = 1;
878 } else {
879 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
880 if (err) {
881 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
882 if (err) {
883 dev_err(&pdev->dev, "No usable DMA "
884 "configuration, aborting\n");
885 goto err_dma;
886 }
887 }
888 }
889
890 err = pci_request_selected_regions(pdev, bars, igb_driver_name);
891 if (err)
892 goto err_pci_reg;
893
894 pci_set_master(pdev);
895 pci_save_state(pdev);
896
897 err = -ENOMEM;
898 netdev = alloc_etherdev(sizeof(struct igb_adapter));
899 if (!netdev)
900 goto err_alloc_etherdev;
901
902 SET_NETDEV_DEV(netdev, &pdev->dev);
903
904 pci_set_drvdata(pdev, netdev);
905 adapter = netdev_priv(netdev);
906 adapter->netdev = netdev;
907 adapter->pdev = pdev;
908 hw = &adapter->hw;
909 hw->back = adapter;
910 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
911 adapter->bars = bars;
912 adapter->need_ioport = need_ioport;
913
914 mmio_start = pci_resource_start(pdev, 0);
915 mmio_len = pci_resource_len(pdev, 0);
916
917 err = -EIO;
918 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
919 if (!adapter->hw.hw_addr)
920 goto err_ioremap;
921
922 netdev->open = &igb_open;
923 netdev->stop = &igb_close;
924 netdev->get_stats = &igb_get_stats;
925 netdev->set_multicast_list = &igb_set_multi;
926 netdev->set_mac_address = &igb_set_mac;
927 netdev->change_mtu = &igb_change_mtu;
928 netdev->do_ioctl = &igb_ioctl;
929 igb_set_ethtool_ops(netdev);
930 netdev->tx_timeout = &igb_tx_timeout;
931 netdev->watchdog_timeo = 5 * HZ;
932 netdev->vlan_rx_register = igb_vlan_rx_register;
933 netdev->vlan_rx_add_vid = igb_vlan_rx_add_vid;
934 netdev->vlan_rx_kill_vid = igb_vlan_rx_kill_vid;
935 #ifdef CONFIG_NET_POLL_CONTROLLER
936 netdev->poll_controller = igb_netpoll;
937 #endif
938 netdev->hard_start_xmit = &igb_xmit_frame_adv;
939
940 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
941
942 netdev->mem_start = mmio_start;
943 netdev->mem_end = mmio_start + mmio_len;
944
945 /* PCI config space info */
946 hw->vendor_id = pdev->vendor;
947 hw->device_id = pdev->device;
948 hw->revision_id = pdev->revision;
949 hw->subsystem_vendor_id = pdev->subsystem_vendor;
950 hw->subsystem_device_id = pdev->subsystem_device;
951
952 /* setup the private structure */
953 hw->back = adapter;
954 /* Copy the default MAC, PHY and NVM function pointers */
955 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
956 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
957 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
958 /* Initialize skew-specific constants */
959 err = ei->get_invariants(hw);
960 if (err)
961 goto err_hw_init;
962
963 err = igb_sw_init(adapter);
964 if (err)
965 goto err_sw_init;
966
967 igb_get_bus_info_pcie(hw);
968
969 hw->phy.autoneg_wait_to_complete = false;
970 hw->mac.adaptive_ifs = true;
971
972 /* Copper options */
973 if (hw->phy.media_type == e1000_media_type_copper) {
974 hw->phy.mdix = AUTO_ALL_MODES;
975 hw->phy.disable_polarity_correction = false;
976 hw->phy.ms_type = e1000_ms_hw_default;
977 }
978
979 if (igb_check_reset_block(hw))
980 dev_info(&pdev->dev,
981 "PHY reset is blocked due to SOL/IDER session.\n");
982
983 netdev->features = NETIF_F_SG |
984 NETIF_F_HW_CSUM |
985 NETIF_F_HW_VLAN_TX |
986 NETIF_F_HW_VLAN_RX |
987 NETIF_F_HW_VLAN_FILTER;
988
989 netdev->features |= NETIF_F_TSO;
990 netdev->features |= NETIF_F_TSO6;
991
992 netdev->vlan_features |= NETIF_F_TSO;
993 netdev->vlan_features |= NETIF_F_TSO6;
994 netdev->vlan_features |= NETIF_F_HW_CSUM;
995 netdev->vlan_features |= NETIF_F_SG;
996
997 if (pci_using_dac)
998 netdev->features |= NETIF_F_HIGHDMA;
999
1000 netdev->features |= NETIF_F_LLTX;
1001 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1002
1003 /* before reading the NVM, reset the controller to put the device in a
1004 * known good starting state */
1005 hw->mac.ops.reset_hw(hw);
1006
1007 /* make sure the NVM is good */
1008 if (igb_validate_nvm_checksum(hw) < 0) {
1009 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1010 err = -EIO;
1011 goto err_eeprom;
1012 }
1013
1014 /* copy the MAC address out of the NVM */
1015 if (hw->mac.ops.read_mac_addr(hw))
1016 dev_err(&pdev->dev, "NVM Read Error\n");
1017
1018 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1019 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1020
1021 if (!is_valid_ether_addr(netdev->perm_addr)) {
1022 dev_err(&pdev->dev, "Invalid MAC Address\n");
1023 err = -EIO;
1024 goto err_eeprom;
1025 }
1026
1027 init_timer(&adapter->watchdog_timer);
1028 adapter->watchdog_timer.function = &igb_watchdog;
1029 adapter->watchdog_timer.data = (unsigned long) adapter;
1030
1031 init_timer(&adapter->phy_info_timer);
1032 adapter->phy_info_timer.function = &igb_update_phy_info;
1033 adapter->phy_info_timer.data = (unsigned long) adapter;
1034
1035 INIT_WORK(&adapter->reset_task, igb_reset_task);
1036 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1037
1038 /* Initialize link & ring properties that are user-changeable */
1039 adapter->tx_ring->count = 256;
1040 for (i = 0; i < adapter->num_tx_queues; i++)
1041 adapter->tx_ring[i].count = adapter->tx_ring->count;
1042 adapter->rx_ring->count = 256;
1043 for (i = 0; i < adapter->num_rx_queues; i++)
1044 adapter->rx_ring[i].count = adapter->rx_ring->count;
1045
1046 adapter->fc_autoneg = true;
1047 hw->mac.autoneg = true;
1048 hw->phy.autoneg_advertised = 0x2f;
1049
1050 hw->fc.original_type = e1000_fc_default;
1051 hw->fc.type = e1000_fc_default;
1052
1053 adapter->itr_setting = 3;
1054 adapter->itr = IGB_START_ITR;
1055
1056 igb_validate_mdi_setting(hw);
1057
1058 adapter->rx_csum = 1;
1059
1060 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1061 * enable the ACPI Magic Packet filter
1062 */
1063
1064 if (hw->bus.func == 0 ||
1065 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
1066 hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL3_PORT_A, 1,
1067 &eeprom_data);
1068
1069 if (eeprom_data & eeprom_apme_mask)
1070 adapter->eeprom_wol |= E1000_WUFC_MAG;
1071
1072 /* now that we have the eeprom settings, apply the special cases where
1073 * the eeprom may be wrong or the board simply won't support wake on
1074 * lan on a particular port */
1075 switch (pdev->device) {
1076 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1077 adapter->eeprom_wol = 0;
1078 break;
1079 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1080 /* Wake events only supported on port A for dual fiber
1081 * regardless of eeprom setting */
1082 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1083 adapter->eeprom_wol = 0;
1084 break;
1085 }
1086
1087 /* initialize the wol settings based on the eeprom settings */
1088 adapter->wol = adapter->eeprom_wol;
1089
1090 /* reset the hardware with the new settings */
1091 igb_reset(adapter);
1092
1093 /* let the f/w know that the h/w is now under the control of the
1094 * driver. */
1095 igb_get_hw_control(adapter);
1096
1097 /* tell the stack to leave us alone until igb_open() is called */
1098 netif_carrier_off(netdev);
1099 netif_stop_queue(netdev);
1100
1101 strcpy(netdev->name, "eth%d");
1102 err = register_netdev(netdev);
1103 if (err)
1104 goto err_register;
1105
1106 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1107 /* print bus type/speed/width info */
1108 dev_info(&pdev->dev,
1109 "%s: (PCIe:%s:%s) %02x:%02x:%02x:%02x:%02x:%02x\n",
1110 netdev->name,
1111 ((hw->bus.speed == e1000_bus_speed_2500)
1112 ? "2.5Gb/s" : "unknown"),
1113 ((hw->bus.width == e1000_bus_width_pcie_x4)
1114 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1115 ? "Width x1" : "unknown"),
1116 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
1117 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
1118
1119 igb_read_part_num(hw, &part_num);
1120 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1121 (part_num >> 8), (part_num & 0xff));
1122
1123 dev_info(&pdev->dev,
1124 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1125 adapter->msix_entries ? "MSI-X" :
1126 adapter->msi_enabled ? "MSI" : "legacy",
1127 adapter->num_rx_queues, adapter->num_tx_queues);
1128
1129 return 0;
1130
1131 err_register:
1132 igb_release_hw_control(adapter);
1133 err_eeprom:
1134 if (!igb_check_reset_block(hw))
1135 hw->phy.ops.reset_phy(hw);
1136
1137 if (hw->flash_address)
1138 iounmap(hw->flash_address);
1139
1140 igb_remove_device(hw);
1141 kfree(adapter->tx_ring);
1142 kfree(adapter->rx_ring);
1143 err_sw_init:
1144 err_hw_init:
1145 iounmap(hw->hw_addr);
1146 err_ioremap:
1147 free_netdev(netdev);
1148 err_alloc_etherdev:
1149 pci_release_selected_regions(pdev, bars);
1150 err_pci_reg:
1151 err_dma:
1152 pci_disable_device(pdev);
1153 return err;
1154 }
1155
1156 /**
1157 * igb_remove - Device Removal Routine
1158 * @pdev: PCI device information struct
1159 *
1160 * igb_remove is called by the PCI subsystem to alert the driver
1161 * that it should release a PCI device. The could be caused by a
1162 * Hot-Plug event, or because the driver is going to be removed from
1163 * memory.
1164 **/
1165 static void __devexit igb_remove(struct pci_dev *pdev)
1166 {
1167 struct net_device *netdev = pci_get_drvdata(pdev);
1168 struct igb_adapter *adapter = netdev_priv(netdev);
1169
1170 /* flush_scheduled work may reschedule our watchdog task, so
1171 * explicitly disable watchdog tasks from being rescheduled */
1172 set_bit(__IGB_DOWN, &adapter->state);
1173 del_timer_sync(&adapter->watchdog_timer);
1174 del_timer_sync(&adapter->phy_info_timer);
1175
1176 flush_scheduled_work();
1177
1178 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1179 * would have already happened in close and is redundant. */
1180 igb_release_hw_control(adapter);
1181
1182 unregister_netdev(netdev);
1183
1184 if (!igb_check_reset_block(&adapter->hw))
1185 adapter->hw.phy.ops.reset_phy(&adapter->hw);
1186
1187 igb_remove_device(&adapter->hw);
1188 igb_reset_interrupt_capability(adapter);
1189
1190 kfree(adapter->tx_ring);
1191 kfree(adapter->rx_ring);
1192
1193 iounmap(adapter->hw.hw_addr);
1194 if (adapter->hw.flash_address)
1195 iounmap(adapter->hw.flash_address);
1196 pci_release_selected_regions(pdev, adapter->bars);
1197
1198 free_netdev(netdev);
1199
1200 pci_disable_device(pdev);
1201 }
1202
1203 /**
1204 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1205 * @adapter: board private structure to initialize
1206 *
1207 * igb_sw_init initializes the Adapter private data structure.
1208 * Fields are initialized based on PCI device information and
1209 * OS network device settings (MTU size).
1210 **/
1211 static int __devinit igb_sw_init(struct igb_adapter *adapter)
1212 {
1213 struct e1000_hw *hw = &adapter->hw;
1214 struct net_device *netdev = adapter->netdev;
1215 struct pci_dev *pdev = adapter->pdev;
1216
1217 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1218
1219 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1220 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1221 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1222 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1223
1224 /* Number of supported queues. */
1225 /* Having more queues than CPUs doesn't make sense. */
1226 adapter->num_tx_queues = 1;
1227 adapter->num_rx_queues = min(IGB_MAX_RX_QUEUES, num_online_cpus());
1228
1229 igb_set_interrupt_capability(adapter);
1230
1231 if (igb_alloc_queues(adapter)) {
1232 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1233 return -ENOMEM;
1234 }
1235
1236 /* Explicitly disable IRQ since the NIC can be in any state. */
1237 igb_irq_disable(adapter);
1238
1239 set_bit(__IGB_DOWN, &adapter->state);
1240 return 0;
1241 }
1242
1243 /**
1244 * igb_open - Called when a network interface is made active
1245 * @netdev: network interface device structure
1246 *
1247 * Returns 0 on success, negative value on failure
1248 *
1249 * The open entry point is called when a network interface is made
1250 * active by the system (IFF_UP). At this point all resources needed
1251 * for transmit and receive operations are allocated, the interrupt
1252 * handler is registered with the OS, the watchdog timer is started,
1253 * and the stack is notified that the interface is ready.
1254 **/
1255 static int igb_open(struct net_device *netdev)
1256 {
1257 struct igb_adapter *adapter = netdev_priv(netdev);
1258 struct e1000_hw *hw = &adapter->hw;
1259 int err;
1260 int i;
1261
1262 /* disallow open during test */
1263 if (test_bit(__IGB_TESTING, &adapter->state))
1264 return -EBUSY;
1265
1266 /* allocate transmit descriptors */
1267 err = igb_setup_all_tx_resources(adapter);
1268 if (err)
1269 goto err_setup_tx;
1270
1271 /* allocate receive descriptors */
1272 err = igb_setup_all_rx_resources(adapter);
1273 if (err)
1274 goto err_setup_rx;
1275
1276 /* e1000_power_up_phy(adapter); */
1277
1278 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1279 if ((adapter->hw.mng_cookie.status &
1280 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1281 igb_update_mng_vlan(adapter);
1282
1283 /* before we allocate an interrupt, we must be ready to handle it.
1284 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1285 * as soon as we call pci_request_irq, so we have to setup our
1286 * clean_rx handler before we do so. */
1287 igb_configure(adapter);
1288
1289 err = igb_request_irq(adapter);
1290 if (err)
1291 goto err_req_irq;
1292
1293 /* From here on the code is the same as igb_up() */
1294 clear_bit(__IGB_DOWN, &adapter->state);
1295
1296 for (i = 0; i < adapter->num_rx_queues; i++)
1297 napi_enable(&adapter->rx_ring[i].napi);
1298
1299 /* Clear any pending interrupts. */
1300 rd32(E1000_ICR);
1301
1302 igb_irq_enable(adapter);
1303
1304 /* Fire a link status change interrupt to start the watchdog. */
1305 wr32(E1000_ICS, E1000_ICS_LSC);
1306
1307 return 0;
1308
1309 err_req_irq:
1310 igb_release_hw_control(adapter);
1311 /* e1000_power_down_phy(adapter); */
1312 igb_free_all_rx_resources(adapter);
1313 err_setup_rx:
1314 igb_free_all_tx_resources(adapter);
1315 err_setup_tx:
1316 igb_reset(adapter);
1317
1318 return err;
1319 }
1320
1321 /**
1322 * igb_close - Disables a network interface
1323 * @netdev: network interface device structure
1324 *
1325 * Returns 0, this is not allowed to fail
1326 *
1327 * The close entry point is called when an interface is de-activated
1328 * by the OS. The hardware is still under the driver's control, but
1329 * needs to be disabled. A global MAC reset is issued to stop the
1330 * hardware, and all transmit and receive resources are freed.
1331 **/
1332 static int igb_close(struct net_device *netdev)
1333 {
1334 struct igb_adapter *adapter = netdev_priv(netdev);
1335
1336 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1337 igb_down(adapter);
1338
1339 igb_free_irq(adapter);
1340
1341 igb_free_all_tx_resources(adapter);
1342 igb_free_all_rx_resources(adapter);
1343
1344 /* kill manageability vlan ID if supported, but not if a vlan with
1345 * the same ID is registered on the host OS (let 8021q kill it) */
1346 if ((adapter->hw.mng_cookie.status &
1347 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1348 !(adapter->vlgrp &&
1349 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1350 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1351
1352 return 0;
1353 }
1354
1355 /**
1356 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1357 * @adapter: board private structure
1358 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1359 *
1360 * Return 0 on success, negative on failure
1361 **/
1362
1363 int igb_setup_tx_resources(struct igb_adapter *adapter,
1364 struct igb_ring *tx_ring)
1365 {
1366 struct pci_dev *pdev = adapter->pdev;
1367 int size;
1368
1369 size = sizeof(struct igb_buffer) * tx_ring->count;
1370 tx_ring->buffer_info = vmalloc(size);
1371 if (!tx_ring->buffer_info)
1372 goto err;
1373 memset(tx_ring->buffer_info, 0, size);
1374
1375 /* round up to nearest 4K */
1376 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc)
1377 + sizeof(u32);
1378 tx_ring->size = ALIGN(tx_ring->size, 4096);
1379
1380 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1381 &tx_ring->dma);
1382
1383 if (!tx_ring->desc)
1384 goto err;
1385
1386 tx_ring->adapter = adapter;
1387 tx_ring->next_to_use = 0;
1388 tx_ring->next_to_clean = 0;
1389 spin_lock_init(&tx_ring->tx_clean_lock);
1390 spin_lock_init(&tx_ring->tx_lock);
1391 return 0;
1392
1393 err:
1394 vfree(tx_ring->buffer_info);
1395 dev_err(&adapter->pdev->dev,
1396 "Unable to allocate memory for the transmit descriptor ring\n");
1397 return -ENOMEM;
1398 }
1399
1400 /**
1401 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1402 * (Descriptors) for all queues
1403 * @adapter: board private structure
1404 *
1405 * Return 0 on success, negative on failure
1406 **/
1407 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1408 {
1409 int i, err = 0;
1410
1411 for (i = 0; i < adapter->num_tx_queues; i++) {
1412 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1413 if (err) {
1414 dev_err(&adapter->pdev->dev,
1415 "Allocation for Tx Queue %u failed\n", i);
1416 for (i--; i >= 0; i--)
1417 igb_free_tx_resources(&adapter->tx_ring[i]);
1418 break;
1419 }
1420 }
1421
1422 return err;
1423 }
1424
1425 /**
1426 * igb_configure_tx - Configure transmit Unit after Reset
1427 * @adapter: board private structure
1428 *
1429 * Configure the Tx unit of the MAC after a reset.
1430 **/
1431 static void igb_configure_tx(struct igb_adapter *adapter)
1432 {
1433 u64 tdba, tdwba;
1434 struct e1000_hw *hw = &adapter->hw;
1435 u32 tctl;
1436 u32 txdctl, txctrl;
1437 int i;
1438
1439 for (i = 0; i < adapter->num_tx_queues; i++) {
1440 struct igb_ring *ring = &(adapter->tx_ring[i]);
1441
1442 wr32(E1000_TDLEN(i),
1443 ring->count * sizeof(struct e1000_tx_desc));
1444 tdba = ring->dma;
1445 wr32(E1000_TDBAL(i),
1446 tdba & 0x00000000ffffffffULL);
1447 wr32(E1000_TDBAH(i), tdba >> 32);
1448
1449 tdwba = ring->dma + ring->count * sizeof(struct e1000_tx_desc);
1450 tdwba |= 1; /* enable head wb */
1451 wr32(E1000_TDWBAL(i),
1452 tdwba & 0x00000000ffffffffULL);
1453 wr32(E1000_TDWBAH(i), tdwba >> 32);
1454
1455 ring->head = E1000_TDH(i);
1456 ring->tail = E1000_TDT(i);
1457 writel(0, hw->hw_addr + ring->tail);
1458 writel(0, hw->hw_addr + ring->head);
1459 txdctl = rd32(E1000_TXDCTL(i));
1460 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1461 wr32(E1000_TXDCTL(i), txdctl);
1462
1463 /* Turn off Relaxed Ordering on head write-backs. The
1464 * writebacks MUST be delivered in order or it will
1465 * completely screw up our bookeeping.
1466 */
1467 txctrl = rd32(E1000_DCA_TXCTRL(i));
1468 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1469 wr32(E1000_DCA_TXCTRL(i), txctrl);
1470 }
1471
1472
1473
1474 /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1475
1476 /* Program the Transmit Control Register */
1477
1478 tctl = rd32(E1000_TCTL);
1479 tctl &= ~E1000_TCTL_CT;
1480 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1481 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1482
1483 igb_config_collision_dist(hw);
1484
1485 /* Setup Transmit Descriptor Settings for eop descriptor */
1486 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1487
1488 /* Enable transmits */
1489 tctl |= E1000_TCTL_EN;
1490
1491 wr32(E1000_TCTL, tctl);
1492 }
1493
1494 /**
1495 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1496 * @adapter: board private structure
1497 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1498 *
1499 * Returns 0 on success, negative on failure
1500 **/
1501
1502 int igb_setup_rx_resources(struct igb_adapter *adapter,
1503 struct igb_ring *rx_ring)
1504 {
1505 struct pci_dev *pdev = adapter->pdev;
1506 int size, desc_len;
1507
1508 size = sizeof(struct igb_buffer) * rx_ring->count;
1509 rx_ring->buffer_info = vmalloc(size);
1510 if (!rx_ring->buffer_info)
1511 goto err;
1512 memset(rx_ring->buffer_info, 0, size);
1513
1514 desc_len = sizeof(union e1000_adv_rx_desc);
1515
1516 /* Round up to nearest 4K */
1517 rx_ring->size = rx_ring->count * desc_len;
1518 rx_ring->size = ALIGN(rx_ring->size, 4096);
1519
1520 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1521 &rx_ring->dma);
1522
1523 if (!rx_ring->desc)
1524 goto err;
1525
1526 rx_ring->next_to_clean = 0;
1527 rx_ring->next_to_use = 0;
1528 rx_ring->pending_skb = NULL;
1529
1530 rx_ring->adapter = adapter;
1531
1532 return 0;
1533
1534 err:
1535 vfree(rx_ring->buffer_info);
1536 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1537 "the receive descriptor ring\n");
1538 return -ENOMEM;
1539 }
1540
1541 /**
1542 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1543 * (Descriptors) for all queues
1544 * @adapter: board private structure
1545 *
1546 * Return 0 on success, negative on failure
1547 **/
1548 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1549 {
1550 int i, err = 0;
1551
1552 for (i = 0; i < adapter->num_rx_queues; i++) {
1553 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1554 if (err) {
1555 dev_err(&adapter->pdev->dev,
1556 "Allocation for Rx Queue %u failed\n", i);
1557 for (i--; i >= 0; i--)
1558 igb_free_rx_resources(&adapter->rx_ring[i]);
1559 break;
1560 }
1561 }
1562
1563 return err;
1564 }
1565
1566 /**
1567 * igb_setup_rctl - configure the receive control registers
1568 * @adapter: Board private structure
1569 **/
1570 static void igb_setup_rctl(struct igb_adapter *adapter)
1571 {
1572 struct e1000_hw *hw = &adapter->hw;
1573 u32 rctl;
1574 u32 srrctl = 0;
1575 int i;
1576
1577 rctl = rd32(E1000_RCTL);
1578
1579 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1580
1581 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1582 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1583 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1584
1585 /* disable the stripping of CRC because it breaks
1586 * BMC firmware connected over SMBUS
1587 rctl |= E1000_RCTL_SECRC;
1588 */
1589
1590 rctl &= ~E1000_RCTL_SBP;
1591
1592 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1593 rctl &= ~E1000_RCTL_LPE;
1594 else
1595 rctl |= E1000_RCTL_LPE;
1596 if (adapter->rx_buffer_len <= IGB_RXBUFFER_2048) {
1597 /* Setup buffer sizes */
1598 rctl &= ~E1000_RCTL_SZ_4096;
1599 rctl |= E1000_RCTL_BSEX;
1600 switch (adapter->rx_buffer_len) {
1601 case IGB_RXBUFFER_256:
1602 rctl |= E1000_RCTL_SZ_256;
1603 rctl &= ~E1000_RCTL_BSEX;
1604 break;
1605 case IGB_RXBUFFER_512:
1606 rctl |= E1000_RCTL_SZ_512;
1607 rctl &= ~E1000_RCTL_BSEX;
1608 break;
1609 case IGB_RXBUFFER_1024:
1610 rctl |= E1000_RCTL_SZ_1024;
1611 rctl &= ~E1000_RCTL_BSEX;
1612 break;
1613 case IGB_RXBUFFER_2048:
1614 default:
1615 rctl |= E1000_RCTL_SZ_2048;
1616 rctl &= ~E1000_RCTL_BSEX;
1617 break;
1618 case IGB_RXBUFFER_4096:
1619 rctl |= E1000_RCTL_SZ_4096;
1620 break;
1621 case IGB_RXBUFFER_8192:
1622 rctl |= E1000_RCTL_SZ_8192;
1623 break;
1624 case IGB_RXBUFFER_16384:
1625 rctl |= E1000_RCTL_SZ_16384;
1626 break;
1627 }
1628 } else {
1629 rctl &= ~E1000_RCTL_BSEX;
1630 srrctl = adapter->rx_buffer_len >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1631 }
1632
1633 /* 82575 and greater support packet-split where the protocol
1634 * header is placed in skb->data and the packet data is
1635 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1636 * In the case of a non-split, skb->data is linearly filled,
1637 * followed by the page buffers. Therefore, skb->data is
1638 * sized to hold the largest protocol header.
1639 */
1640 /* allocations using alloc_page take too long for regular MTU
1641 * so only enable packet split for jumbo frames */
1642 if (rctl & E1000_RCTL_LPE) {
1643 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
1644 srrctl = adapter->rx_ps_hdr_size <<
1645 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
1646 /* buffer size is ALWAYS one page */
1647 srrctl |= PAGE_SIZE >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1648 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1649 } else {
1650 adapter->rx_ps_hdr_size = 0;
1651 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1652 }
1653
1654 for (i = 0; i < adapter->num_rx_queues; i++)
1655 wr32(E1000_SRRCTL(i), srrctl);
1656
1657 wr32(E1000_RCTL, rctl);
1658 }
1659
1660 /**
1661 * igb_configure_rx - Configure receive Unit after Reset
1662 * @adapter: board private structure
1663 *
1664 * Configure the Rx unit of the MAC after a reset.
1665 **/
1666 static void igb_configure_rx(struct igb_adapter *adapter)
1667 {
1668 u64 rdba;
1669 struct e1000_hw *hw = &adapter->hw;
1670 u32 rctl, rxcsum;
1671 u32 rxdctl;
1672 int i;
1673
1674 /* disable receives while setting up the descriptors */
1675 rctl = rd32(E1000_RCTL);
1676 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1677 wrfl();
1678 mdelay(10);
1679
1680 if (adapter->itr_setting > 3)
1681 wr32(E1000_ITR,
1682 1000000000 / (adapter->itr * 256));
1683
1684 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1685 * the Base and Length of the Rx Descriptor Ring */
1686 for (i = 0; i < adapter->num_rx_queues; i++) {
1687 struct igb_ring *ring = &(adapter->rx_ring[i]);
1688 rdba = ring->dma;
1689 wr32(E1000_RDBAL(i),
1690 rdba & 0x00000000ffffffffULL);
1691 wr32(E1000_RDBAH(i), rdba >> 32);
1692 wr32(E1000_RDLEN(i),
1693 ring->count * sizeof(union e1000_adv_rx_desc));
1694
1695 ring->head = E1000_RDH(i);
1696 ring->tail = E1000_RDT(i);
1697 writel(0, hw->hw_addr + ring->tail);
1698 writel(0, hw->hw_addr + ring->head);
1699
1700 rxdctl = rd32(E1000_RXDCTL(i));
1701 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1702 rxdctl &= 0xFFF00000;
1703 rxdctl |= IGB_RX_PTHRESH;
1704 rxdctl |= IGB_RX_HTHRESH << 8;
1705 rxdctl |= IGB_RX_WTHRESH << 16;
1706 wr32(E1000_RXDCTL(i), rxdctl);
1707 }
1708
1709 if (adapter->num_rx_queues > 1) {
1710 u32 random[10];
1711 u32 mrqc;
1712 u32 j, shift;
1713 union e1000_reta {
1714 u32 dword;
1715 u8 bytes[4];
1716 } reta;
1717
1718 get_random_bytes(&random[0], 40);
1719
1720 shift = 6;
1721 for (j = 0; j < (32 * 4); j++) {
1722 reta.bytes[j & 3] =
1723 (j % adapter->num_rx_queues) << shift;
1724 if ((j & 3) == 3)
1725 writel(reta.dword,
1726 hw->hw_addr + E1000_RETA(0) + (j & ~3));
1727 }
1728 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
1729
1730 /* Fill out hash function seeds */
1731 for (j = 0; j < 10; j++)
1732 array_wr32(E1000_RSSRK(0), j, random[j]);
1733
1734 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1735 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1736 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
1737 E1000_MRQC_RSS_FIELD_IPV6_TCP);
1738 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
1739 E1000_MRQC_RSS_FIELD_IPV6_UDP);
1740 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
1741 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
1742
1743
1744 wr32(E1000_MRQC, mrqc);
1745
1746 /* Multiqueue and raw packet checksumming are mutually
1747 * exclusive. Note that this not the same as TCP/IP
1748 * checksumming, which works fine. */
1749 rxcsum = rd32(E1000_RXCSUM);
1750 rxcsum |= E1000_RXCSUM_PCSD;
1751 wr32(E1000_RXCSUM, rxcsum);
1752 } else {
1753 /* Enable Receive Checksum Offload for TCP and UDP */
1754 rxcsum = rd32(E1000_RXCSUM);
1755 if (adapter->rx_csum) {
1756 rxcsum |= E1000_RXCSUM_TUOFL;
1757
1758 /* Enable IPv4 payload checksum for UDP fragments
1759 * Must be used in conjunction with packet-split. */
1760 if (adapter->rx_ps_hdr_size)
1761 rxcsum |= E1000_RXCSUM_IPPCSE;
1762 } else {
1763 rxcsum &= ~E1000_RXCSUM_TUOFL;
1764 /* don't need to clear IPPCSE as it defaults to 0 */
1765 }
1766 wr32(E1000_RXCSUM, rxcsum);
1767 }
1768
1769 if (adapter->vlgrp)
1770 wr32(E1000_RLPML,
1771 adapter->max_frame_size + VLAN_TAG_SIZE);
1772 else
1773 wr32(E1000_RLPML, adapter->max_frame_size);
1774
1775 /* Enable Receives */
1776 wr32(E1000_RCTL, rctl);
1777 }
1778
1779 /**
1780 * igb_free_tx_resources - Free Tx Resources per Queue
1781 * @adapter: board private structure
1782 * @tx_ring: Tx descriptor ring for a specific queue
1783 *
1784 * Free all transmit software resources
1785 **/
1786 static void igb_free_tx_resources(struct igb_ring *tx_ring)
1787 {
1788 struct pci_dev *pdev = tx_ring->adapter->pdev;
1789
1790 igb_clean_tx_ring(tx_ring);
1791
1792 vfree(tx_ring->buffer_info);
1793 tx_ring->buffer_info = NULL;
1794
1795 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1796
1797 tx_ring->desc = NULL;
1798 }
1799
1800 /**
1801 * igb_free_all_tx_resources - Free Tx Resources for All Queues
1802 * @adapter: board private structure
1803 *
1804 * Free all transmit software resources
1805 **/
1806 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
1807 {
1808 int i;
1809
1810 for (i = 0; i < adapter->num_tx_queues; i++)
1811 igb_free_tx_resources(&adapter->tx_ring[i]);
1812 }
1813
1814 static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
1815 struct igb_buffer *buffer_info)
1816 {
1817 if (buffer_info->dma) {
1818 pci_unmap_page(adapter->pdev,
1819 buffer_info->dma,
1820 buffer_info->length,
1821 PCI_DMA_TODEVICE);
1822 buffer_info->dma = 0;
1823 }
1824 if (buffer_info->skb) {
1825 dev_kfree_skb_any(buffer_info->skb);
1826 buffer_info->skb = NULL;
1827 }
1828 buffer_info->time_stamp = 0;
1829 /* buffer_info must be completely set up in the transmit path */
1830 }
1831
1832 /**
1833 * igb_clean_tx_ring - Free Tx Buffers
1834 * @adapter: board private structure
1835 * @tx_ring: ring to be cleaned
1836 **/
1837 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
1838 {
1839 struct igb_adapter *adapter = tx_ring->adapter;
1840 struct igb_buffer *buffer_info;
1841 unsigned long size;
1842 unsigned int i;
1843
1844 if (!tx_ring->buffer_info)
1845 return;
1846 /* Free all the Tx ring sk_buffs */
1847
1848 for (i = 0; i < tx_ring->count; i++) {
1849 buffer_info = &tx_ring->buffer_info[i];
1850 igb_unmap_and_free_tx_resource(adapter, buffer_info);
1851 }
1852
1853 size = sizeof(struct igb_buffer) * tx_ring->count;
1854 memset(tx_ring->buffer_info, 0, size);
1855
1856 /* Zero out the descriptor ring */
1857
1858 memset(tx_ring->desc, 0, tx_ring->size);
1859
1860 tx_ring->next_to_use = 0;
1861 tx_ring->next_to_clean = 0;
1862
1863 writel(0, adapter->hw.hw_addr + tx_ring->head);
1864 writel(0, adapter->hw.hw_addr + tx_ring->tail);
1865 }
1866
1867 /**
1868 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
1869 * @adapter: board private structure
1870 **/
1871 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
1872 {
1873 int i;
1874
1875 for (i = 0; i < adapter->num_tx_queues; i++)
1876 igb_clean_tx_ring(&adapter->tx_ring[i]);
1877 }
1878
1879 /**
1880 * igb_free_rx_resources - Free Rx Resources
1881 * @adapter: board private structure
1882 * @rx_ring: ring to clean the resources from
1883 *
1884 * Free all receive software resources
1885 **/
1886 static void igb_free_rx_resources(struct igb_ring *rx_ring)
1887 {
1888 struct pci_dev *pdev = rx_ring->adapter->pdev;
1889
1890 igb_clean_rx_ring(rx_ring);
1891
1892 vfree(rx_ring->buffer_info);
1893 rx_ring->buffer_info = NULL;
1894
1895 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1896
1897 rx_ring->desc = NULL;
1898 }
1899
1900 /**
1901 * igb_free_all_rx_resources - Free Rx Resources for All Queues
1902 * @adapter: board private structure
1903 *
1904 * Free all receive software resources
1905 **/
1906 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
1907 {
1908 int i;
1909
1910 for (i = 0; i < adapter->num_rx_queues; i++)
1911 igb_free_rx_resources(&adapter->rx_ring[i]);
1912 }
1913
1914 /**
1915 * igb_clean_rx_ring - Free Rx Buffers per Queue
1916 * @adapter: board private structure
1917 * @rx_ring: ring to free buffers from
1918 **/
1919 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
1920 {
1921 struct igb_adapter *adapter = rx_ring->adapter;
1922 struct igb_buffer *buffer_info;
1923 struct pci_dev *pdev = adapter->pdev;
1924 unsigned long size;
1925 unsigned int i;
1926
1927 if (!rx_ring->buffer_info)
1928 return;
1929 /* Free all the Rx ring sk_buffs */
1930 for (i = 0; i < rx_ring->count; i++) {
1931 buffer_info = &rx_ring->buffer_info[i];
1932 if (buffer_info->dma) {
1933 if (adapter->rx_ps_hdr_size)
1934 pci_unmap_single(pdev, buffer_info->dma,
1935 adapter->rx_ps_hdr_size,
1936 PCI_DMA_FROMDEVICE);
1937 else
1938 pci_unmap_single(pdev, buffer_info->dma,
1939 adapter->rx_buffer_len,
1940 PCI_DMA_FROMDEVICE);
1941 buffer_info->dma = 0;
1942 }
1943
1944 if (buffer_info->skb) {
1945 dev_kfree_skb(buffer_info->skb);
1946 buffer_info->skb = NULL;
1947 }
1948 if (buffer_info->page) {
1949 pci_unmap_page(pdev, buffer_info->page_dma,
1950 PAGE_SIZE, PCI_DMA_FROMDEVICE);
1951 put_page(buffer_info->page);
1952 buffer_info->page = NULL;
1953 buffer_info->page_dma = 0;
1954 }
1955 }
1956
1957 /* there also may be some cached data from a chained receive */
1958 if (rx_ring->pending_skb) {
1959 dev_kfree_skb(rx_ring->pending_skb);
1960 rx_ring->pending_skb = NULL;
1961 }
1962
1963 size = sizeof(struct igb_buffer) * rx_ring->count;
1964 memset(rx_ring->buffer_info, 0, size);
1965
1966 /* Zero out the descriptor ring */
1967 memset(rx_ring->desc, 0, rx_ring->size);
1968
1969 rx_ring->next_to_clean = 0;
1970 rx_ring->next_to_use = 0;
1971
1972 writel(0, adapter->hw.hw_addr + rx_ring->head);
1973 writel(0, adapter->hw.hw_addr + rx_ring->tail);
1974 }
1975
1976 /**
1977 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
1978 * @adapter: board private structure
1979 **/
1980 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
1981 {
1982 int i;
1983
1984 for (i = 0; i < adapter->num_rx_queues; i++)
1985 igb_clean_rx_ring(&adapter->rx_ring[i]);
1986 }
1987
1988 /**
1989 * igb_set_mac - Change the Ethernet Address of the NIC
1990 * @netdev: network interface device structure
1991 * @p: pointer to an address structure
1992 *
1993 * Returns 0 on success, negative on failure
1994 **/
1995 static int igb_set_mac(struct net_device *netdev, void *p)
1996 {
1997 struct igb_adapter *adapter = netdev_priv(netdev);
1998 struct sockaddr *addr = p;
1999
2000 if (!is_valid_ether_addr(addr->sa_data))
2001 return -EADDRNOTAVAIL;
2002
2003 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2004 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
2005
2006 adapter->hw.mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2007
2008 return 0;
2009 }
2010
2011 /**
2012 * igb_set_multi - Multicast and Promiscuous mode set
2013 * @netdev: network interface device structure
2014 *
2015 * The set_multi entry point is called whenever the multicast address
2016 * list or the network interface flags are updated. This routine is
2017 * responsible for configuring the hardware for proper multicast,
2018 * promiscuous mode, and all-multi behavior.
2019 **/
2020 static void igb_set_multi(struct net_device *netdev)
2021 {
2022 struct igb_adapter *adapter = netdev_priv(netdev);
2023 struct e1000_hw *hw = &adapter->hw;
2024 struct e1000_mac_info *mac = &hw->mac;
2025 struct dev_mc_list *mc_ptr;
2026 u8 *mta_list;
2027 u32 rctl;
2028 int i;
2029
2030 /* Check for Promiscuous and All Multicast modes */
2031
2032 rctl = rd32(E1000_RCTL);
2033
2034 if (netdev->flags & IFF_PROMISC)
2035 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2036 else if (netdev->flags & IFF_ALLMULTI) {
2037 rctl |= E1000_RCTL_MPE;
2038 rctl &= ~E1000_RCTL_UPE;
2039 } else
2040 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2041
2042 wr32(E1000_RCTL, rctl);
2043
2044 if (!netdev->mc_count) {
2045 /* nothing to program, so clear mc list */
2046 igb_update_mc_addr_list(hw, NULL, 0, 1,
2047 mac->rar_entry_count);
2048 return;
2049 }
2050
2051 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2052 if (!mta_list)
2053 return;
2054
2055 /* The shared function expects a packed array of only addresses. */
2056 mc_ptr = netdev->mc_list;
2057
2058 for (i = 0; i < netdev->mc_count; i++) {
2059 if (!mc_ptr)
2060 break;
2061 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2062 mc_ptr = mc_ptr->next;
2063 }
2064 igb_update_mc_addr_list(hw, mta_list, i, 1, mac->rar_entry_count);
2065 kfree(mta_list);
2066 }
2067
2068 /* Need to wait a few seconds after link up to get diagnostic information from
2069 * the phy */
2070 static void igb_update_phy_info(unsigned long data)
2071 {
2072 struct igb_adapter *adapter = (struct igb_adapter *) data;
2073 if (adapter->hw.phy.ops.get_phy_info)
2074 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
2075 }
2076
2077 /**
2078 * igb_watchdog - Timer Call-back
2079 * @data: pointer to adapter cast into an unsigned long
2080 **/
2081 static void igb_watchdog(unsigned long data)
2082 {
2083 struct igb_adapter *adapter = (struct igb_adapter *)data;
2084 /* Do the rest outside of interrupt context */
2085 schedule_work(&adapter->watchdog_task);
2086 }
2087
2088 static void igb_watchdog_task(struct work_struct *work)
2089 {
2090 struct igb_adapter *adapter = container_of(work,
2091 struct igb_adapter, watchdog_task);
2092 struct e1000_hw *hw = &adapter->hw;
2093
2094 struct net_device *netdev = adapter->netdev;
2095 struct igb_ring *tx_ring = adapter->tx_ring;
2096 struct e1000_mac_info *mac = &adapter->hw.mac;
2097 u32 link;
2098 s32 ret_val;
2099
2100 if ((netif_carrier_ok(netdev)) &&
2101 (rd32(E1000_STATUS) & E1000_STATUS_LU))
2102 goto link_up;
2103
2104 ret_val = hw->mac.ops.check_for_link(&adapter->hw);
2105 if ((ret_val == E1000_ERR_PHY) &&
2106 (hw->phy.type == e1000_phy_igp_3) &&
2107 (rd32(E1000_CTRL) &
2108 E1000_PHY_CTRL_GBE_DISABLE))
2109 dev_info(&adapter->pdev->dev,
2110 "Gigabit has been disabled, downgrading speed\n");
2111
2112 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
2113 !(rd32(E1000_TXCW) & E1000_TXCW_ANE))
2114 link = mac->serdes_has_link;
2115 else
2116 link = rd32(E1000_STATUS) &
2117 E1000_STATUS_LU;
2118
2119 if (link) {
2120 if (!netif_carrier_ok(netdev)) {
2121 u32 ctrl;
2122 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2123 &adapter->link_speed,
2124 &adapter->link_duplex);
2125
2126 ctrl = rd32(E1000_CTRL);
2127 dev_info(&adapter->pdev->dev,
2128 "NIC Link is Up %d Mbps %s, "
2129 "Flow Control: %s\n",
2130 adapter->link_speed,
2131 adapter->link_duplex == FULL_DUPLEX ?
2132 "Full Duplex" : "Half Duplex",
2133 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2134 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2135 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2136 E1000_CTRL_TFCE) ? "TX" : "None")));
2137
2138 /* tweak tx_queue_len according to speed/duplex and
2139 * adjust the timeout factor */
2140 netdev->tx_queue_len = adapter->tx_queue_len;
2141 adapter->tx_timeout_factor = 1;
2142 switch (adapter->link_speed) {
2143 case SPEED_10:
2144 netdev->tx_queue_len = 10;
2145 adapter->tx_timeout_factor = 14;
2146 break;
2147 case SPEED_100:
2148 netdev->tx_queue_len = 100;
2149 /* maybe add some timeout factor ? */
2150 break;
2151 }
2152
2153 netif_carrier_on(netdev);
2154 netif_wake_queue(netdev);
2155
2156 if (!test_bit(__IGB_DOWN, &adapter->state))
2157 mod_timer(&adapter->phy_info_timer,
2158 round_jiffies(jiffies + 2 * HZ));
2159 }
2160 } else {
2161 if (netif_carrier_ok(netdev)) {
2162 adapter->link_speed = 0;
2163 adapter->link_duplex = 0;
2164 dev_info(&adapter->pdev->dev, "NIC Link is Down\n");
2165 netif_carrier_off(netdev);
2166 netif_stop_queue(netdev);
2167 if (!test_bit(__IGB_DOWN, &adapter->state))
2168 mod_timer(&adapter->phy_info_timer,
2169 round_jiffies(jiffies + 2 * HZ));
2170 }
2171 }
2172
2173 link_up:
2174 igb_update_stats(adapter);
2175
2176 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2177 adapter->tpt_old = adapter->stats.tpt;
2178 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
2179 adapter->colc_old = adapter->stats.colc;
2180
2181 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2182 adapter->gorc_old = adapter->stats.gorc;
2183 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2184 adapter->gotc_old = adapter->stats.gotc;
2185
2186 igb_update_adaptive(&adapter->hw);
2187
2188 if (!netif_carrier_ok(netdev)) {
2189 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2190 /* We've lost link, so the controller stops DMA,
2191 * but we've got queued Tx work that's never going
2192 * to get done, so reset controller to flush Tx.
2193 * (Do the reset outside of interrupt context). */
2194 adapter->tx_timeout_count++;
2195 schedule_work(&adapter->reset_task);
2196 }
2197 }
2198
2199 /* Cause software interrupt to ensure rx ring is cleaned */
2200 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2201
2202 /* Force detection of hung controller every watchdog period */
2203 tx_ring->detect_tx_hung = true;
2204
2205 /* Reset the timer */
2206 if (!test_bit(__IGB_DOWN, &adapter->state))
2207 mod_timer(&adapter->watchdog_timer,
2208 round_jiffies(jiffies + 2 * HZ));
2209 }
2210
2211 enum latency_range {
2212 lowest_latency = 0,
2213 low_latency = 1,
2214 bulk_latency = 2,
2215 latency_invalid = 255
2216 };
2217
2218
2219 static void igb_lower_rx_eitr(struct igb_adapter *adapter,
2220 struct igb_ring *rx_ring)
2221 {
2222 struct e1000_hw *hw = &adapter->hw;
2223 int new_val;
2224
2225 new_val = rx_ring->itr_val / 2;
2226 if (new_val < IGB_MIN_DYN_ITR)
2227 new_val = IGB_MIN_DYN_ITR;
2228
2229 if (new_val != rx_ring->itr_val) {
2230 rx_ring->itr_val = new_val;
2231 wr32(rx_ring->itr_register,
2232 1000000000 / (new_val * 256));
2233 }
2234 }
2235
2236 static void igb_raise_rx_eitr(struct igb_adapter *adapter,
2237 struct igb_ring *rx_ring)
2238 {
2239 struct e1000_hw *hw = &adapter->hw;
2240 int new_val;
2241
2242 new_val = rx_ring->itr_val * 2;
2243 if (new_val > IGB_MAX_DYN_ITR)
2244 new_val = IGB_MAX_DYN_ITR;
2245
2246 if (new_val != rx_ring->itr_val) {
2247 rx_ring->itr_val = new_val;
2248 wr32(rx_ring->itr_register,
2249 1000000000 / (new_val * 256));
2250 }
2251 }
2252
2253 /**
2254 * igb_update_itr - update the dynamic ITR value based on statistics
2255 * Stores a new ITR value based on packets and byte
2256 * counts during the last interrupt. The advantage of per interrupt
2257 * computation is faster updates and more accurate ITR for the current
2258 * traffic pattern. Constants in this function were computed
2259 * based on theoretical maximum wire speed and thresholds were set based
2260 * on testing data as well as attempting to minimize response time
2261 * while increasing bulk throughput.
2262 * this functionality is controlled by the InterruptThrottleRate module
2263 * parameter (see igb_param.c)
2264 * NOTE: These calculations are only valid when operating in a single-
2265 * queue environment.
2266 * @adapter: pointer to adapter
2267 * @itr_setting: current adapter->itr
2268 * @packets: the number of packets during this measurement interval
2269 * @bytes: the number of bytes during this measurement interval
2270 **/
2271 static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2272 int packets, int bytes)
2273 {
2274 unsigned int retval = itr_setting;
2275
2276 if (packets == 0)
2277 goto update_itr_done;
2278
2279 switch (itr_setting) {
2280 case lowest_latency:
2281 /* handle TSO and jumbo frames */
2282 if (bytes/packets > 8000)
2283 retval = bulk_latency;
2284 else if ((packets < 5) && (bytes > 512))
2285 retval = low_latency;
2286 break;
2287 case low_latency: /* 50 usec aka 20000 ints/s */
2288 if (bytes > 10000) {
2289 /* this if handles the TSO accounting */
2290 if (bytes/packets > 8000) {
2291 retval = bulk_latency;
2292 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2293 retval = bulk_latency;
2294 } else if ((packets > 35)) {
2295 retval = lowest_latency;
2296 }
2297 } else if (bytes/packets > 2000) {
2298 retval = bulk_latency;
2299 } else if (packets <= 2 && bytes < 512) {
2300 retval = lowest_latency;
2301 }
2302 break;
2303 case bulk_latency: /* 250 usec aka 4000 ints/s */
2304 if (bytes > 25000) {
2305 if (packets > 35)
2306 retval = low_latency;
2307 } else if (bytes < 6000) {
2308 retval = low_latency;
2309 }
2310 break;
2311 }
2312
2313 update_itr_done:
2314 return retval;
2315 }
2316
2317 static void igb_set_itr(struct igb_adapter *adapter, u16 itr_register,
2318 int rx_only)
2319 {
2320 u16 current_itr;
2321 u32 new_itr = adapter->itr;
2322
2323 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2324 if (adapter->link_speed != SPEED_1000) {
2325 current_itr = 0;
2326 new_itr = 4000;
2327 goto set_itr_now;
2328 }
2329
2330 adapter->rx_itr = igb_update_itr(adapter,
2331 adapter->rx_itr,
2332 adapter->rx_ring->total_packets,
2333 adapter->rx_ring->total_bytes);
2334 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2335 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2336 adapter->rx_itr = low_latency;
2337
2338 if (!rx_only) {
2339 adapter->tx_itr = igb_update_itr(adapter,
2340 adapter->tx_itr,
2341 adapter->tx_ring->total_packets,
2342 adapter->tx_ring->total_bytes);
2343 /* conservative mode (itr 3) eliminates the
2344 * lowest_latency setting */
2345 if (adapter->itr_setting == 3 &&
2346 adapter->tx_itr == lowest_latency)
2347 adapter->tx_itr = low_latency;
2348
2349 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2350 } else {
2351 current_itr = adapter->rx_itr;
2352 }
2353
2354 switch (current_itr) {
2355 /* counts and packets in update_itr are dependent on these numbers */
2356 case lowest_latency:
2357 new_itr = 70000;
2358 break;
2359 case low_latency:
2360 new_itr = 20000; /* aka hwitr = ~200 */
2361 break;
2362 case bulk_latency:
2363 new_itr = 4000;
2364 break;
2365 default:
2366 break;
2367 }
2368
2369 set_itr_now:
2370 if (new_itr != adapter->itr) {
2371 /* this attempts to bias the interrupt rate towards Bulk
2372 * by adding intermediate steps when interrupt rate is
2373 * increasing */
2374 new_itr = new_itr > adapter->itr ?
2375 min(adapter->itr + (new_itr >> 2), new_itr) :
2376 new_itr;
2377 /* Don't write the value here; it resets the adapter's
2378 * internal timer, and causes us to delay far longer than
2379 * we should between interrupts. Instead, we write the ITR
2380 * value at the beginning of the next interrupt so the timing
2381 * ends up being correct.
2382 */
2383 adapter->itr = new_itr;
2384 adapter->set_itr = 1;
2385 }
2386
2387 return;
2388 }
2389
2390
2391 #define IGB_TX_FLAGS_CSUM 0x00000001
2392 #define IGB_TX_FLAGS_VLAN 0x00000002
2393 #define IGB_TX_FLAGS_TSO 0x00000004
2394 #define IGB_TX_FLAGS_IPV4 0x00000008
2395 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2396 #define IGB_TX_FLAGS_VLAN_SHIFT 16
2397
2398 static inline int igb_tso_adv(struct igb_adapter *adapter,
2399 struct igb_ring *tx_ring,
2400 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2401 {
2402 struct e1000_adv_tx_context_desc *context_desc;
2403 unsigned int i;
2404 int err;
2405 struct igb_buffer *buffer_info;
2406 u32 info = 0, tu_cmd = 0;
2407 u32 mss_l4len_idx, l4len;
2408 *hdr_len = 0;
2409
2410 if (skb_header_cloned(skb)) {
2411 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2412 if (err)
2413 return err;
2414 }
2415
2416 l4len = tcp_hdrlen(skb);
2417 *hdr_len += l4len;
2418
2419 if (skb->protocol == htons(ETH_P_IP)) {
2420 struct iphdr *iph = ip_hdr(skb);
2421 iph->tot_len = 0;
2422 iph->check = 0;
2423 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2424 iph->daddr, 0,
2425 IPPROTO_TCP,
2426 0);
2427 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2428 ipv6_hdr(skb)->payload_len = 0;
2429 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2430 &ipv6_hdr(skb)->daddr,
2431 0, IPPROTO_TCP, 0);
2432 }
2433
2434 i = tx_ring->next_to_use;
2435
2436 buffer_info = &tx_ring->buffer_info[i];
2437 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2438 /* VLAN MACLEN IPLEN */
2439 if (tx_flags & IGB_TX_FLAGS_VLAN)
2440 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2441 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2442 *hdr_len += skb_network_offset(skb);
2443 info |= skb_network_header_len(skb);
2444 *hdr_len += skb_network_header_len(skb);
2445 context_desc->vlan_macip_lens = cpu_to_le32(info);
2446
2447 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2448 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2449
2450 if (skb->protocol == htons(ETH_P_IP))
2451 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2452 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2453
2454 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2455
2456 /* MSS L4LEN IDX */
2457 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2458 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2459
2460 /* Context index must be unique per ring. Luckily, so is the interrupt
2461 * mask value. */
2462 mss_l4len_idx |= tx_ring->eims_value >> 4;
2463
2464 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2465 context_desc->seqnum_seed = 0;
2466
2467 buffer_info->time_stamp = jiffies;
2468 buffer_info->dma = 0;
2469 i++;
2470 if (i == tx_ring->count)
2471 i = 0;
2472
2473 tx_ring->next_to_use = i;
2474
2475 return true;
2476 }
2477
2478 static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2479 struct igb_ring *tx_ring,
2480 struct sk_buff *skb, u32 tx_flags)
2481 {
2482 struct e1000_adv_tx_context_desc *context_desc;
2483 unsigned int i;
2484 struct igb_buffer *buffer_info;
2485 u32 info = 0, tu_cmd = 0;
2486
2487 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2488 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2489 i = tx_ring->next_to_use;
2490 buffer_info = &tx_ring->buffer_info[i];
2491 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2492
2493 if (tx_flags & IGB_TX_FLAGS_VLAN)
2494 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2495 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2496 if (skb->ip_summed == CHECKSUM_PARTIAL)
2497 info |= skb_network_header_len(skb);
2498
2499 context_desc->vlan_macip_lens = cpu_to_le32(info);
2500
2501 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2502
2503 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2504 switch (skb->protocol) {
2505 case __constant_htons(ETH_P_IP):
2506 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2507 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2508 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2509 break;
2510 case __constant_htons(ETH_P_IPV6):
2511 /* XXX what about other V6 headers?? */
2512 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2513 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2514 break;
2515 default:
2516 if (unlikely(net_ratelimit()))
2517 dev_warn(&adapter->pdev->dev,
2518 "partial checksum but proto=%x!\n",
2519 skb->protocol);
2520 break;
2521 }
2522 }
2523
2524 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2525 context_desc->seqnum_seed = 0;
2526 context_desc->mss_l4len_idx =
2527 cpu_to_le32(tx_ring->eims_value >> 4);
2528
2529 buffer_info->time_stamp = jiffies;
2530 buffer_info->dma = 0;
2531
2532 i++;
2533 if (i == tx_ring->count)
2534 i = 0;
2535 tx_ring->next_to_use = i;
2536
2537 return true;
2538 }
2539
2540
2541 return false;
2542 }
2543
2544 #define IGB_MAX_TXD_PWR 16
2545 #define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
2546
2547 static inline int igb_tx_map_adv(struct igb_adapter *adapter,
2548 struct igb_ring *tx_ring,
2549 struct sk_buff *skb)
2550 {
2551 struct igb_buffer *buffer_info;
2552 unsigned int len = skb_headlen(skb);
2553 unsigned int count = 0, i;
2554 unsigned int f;
2555
2556 i = tx_ring->next_to_use;
2557
2558 buffer_info = &tx_ring->buffer_info[i];
2559 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2560 buffer_info->length = len;
2561 /* set time_stamp *before* dma to help avoid a possible race */
2562 buffer_info->time_stamp = jiffies;
2563 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2564 PCI_DMA_TODEVICE);
2565 count++;
2566 i++;
2567 if (i == tx_ring->count)
2568 i = 0;
2569
2570 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2571 struct skb_frag_struct *frag;
2572
2573 frag = &skb_shinfo(skb)->frags[f];
2574 len = frag->size;
2575
2576 buffer_info = &tx_ring->buffer_info[i];
2577 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2578 buffer_info->length = len;
2579 buffer_info->time_stamp = jiffies;
2580 buffer_info->dma = pci_map_page(adapter->pdev,
2581 frag->page,
2582 frag->page_offset,
2583 len,
2584 PCI_DMA_TODEVICE);
2585
2586 count++;
2587 i++;
2588 if (i == tx_ring->count)
2589 i = 0;
2590 }
2591
2592 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2593 tx_ring->buffer_info[i].skb = skb;
2594
2595 return count;
2596 }
2597
2598 static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2599 struct igb_ring *tx_ring,
2600 int tx_flags, int count, u32 paylen,
2601 u8 hdr_len)
2602 {
2603 union e1000_adv_tx_desc *tx_desc = NULL;
2604 struct igb_buffer *buffer_info;
2605 u32 olinfo_status = 0, cmd_type_len;
2606 unsigned int i;
2607
2608 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2609 E1000_ADVTXD_DCMD_DEXT);
2610
2611 if (tx_flags & IGB_TX_FLAGS_VLAN)
2612 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2613
2614 if (tx_flags & IGB_TX_FLAGS_TSO) {
2615 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2616
2617 /* insert tcp checksum */
2618 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2619
2620 /* insert ip checksum */
2621 if (tx_flags & IGB_TX_FLAGS_IPV4)
2622 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2623
2624 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2625 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2626 }
2627
2628 if (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2629 IGB_TX_FLAGS_VLAN))
2630 olinfo_status |= tx_ring->eims_value >> 4;
2631
2632 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2633
2634 i = tx_ring->next_to_use;
2635 while (count--) {
2636 buffer_info = &tx_ring->buffer_info[i];
2637 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
2638 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
2639 tx_desc->read.cmd_type_len =
2640 cpu_to_le32(cmd_type_len | buffer_info->length);
2641 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2642 i++;
2643 if (i == tx_ring->count)
2644 i = 0;
2645 }
2646
2647 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
2648 /* Force memory writes to complete before letting h/w
2649 * know there are new descriptors to fetch. (Only
2650 * applicable for weak-ordered memory model archs,
2651 * such as IA-64). */
2652 wmb();
2653
2654 tx_ring->next_to_use = i;
2655 writel(i, adapter->hw.hw_addr + tx_ring->tail);
2656 /* we need this if more than one processor can write to our tail
2657 * at a time, it syncronizes IO on IA64/Altix systems */
2658 mmiowb();
2659 }
2660
2661 static int __igb_maybe_stop_tx(struct net_device *netdev,
2662 struct igb_ring *tx_ring, int size)
2663 {
2664 struct igb_adapter *adapter = netdev_priv(netdev);
2665
2666 netif_stop_queue(netdev);
2667 /* Herbert's original patch had:
2668 * smp_mb__after_netif_stop_queue();
2669 * but since that doesn't exist yet, just open code it. */
2670 smp_mb();
2671
2672 /* We need to check again in a case another CPU has just
2673 * made room available. */
2674 if (IGB_DESC_UNUSED(tx_ring) < size)
2675 return -EBUSY;
2676
2677 /* A reprieve! */
2678 netif_start_queue(netdev);
2679 ++adapter->restart_queue;
2680 return 0;
2681 }
2682
2683 static int igb_maybe_stop_tx(struct net_device *netdev,
2684 struct igb_ring *tx_ring, int size)
2685 {
2686 if (IGB_DESC_UNUSED(tx_ring) >= size)
2687 return 0;
2688 return __igb_maybe_stop_tx(netdev, tx_ring, size);
2689 }
2690
2691 #define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
2692
2693 static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2694 struct net_device *netdev,
2695 struct igb_ring *tx_ring)
2696 {
2697 struct igb_adapter *adapter = netdev_priv(netdev);
2698 unsigned int tx_flags = 0;
2699 unsigned int len;
2700 unsigned long irq_flags;
2701 u8 hdr_len = 0;
2702 int tso = 0;
2703
2704 len = skb_headlen(skb);
2705
2706 if (test_bit(__IGB_DOWN, &adapter->state)) {
2707 dev_kfree_skb_any(skb);
2708 return NETDEV_TX_OK;
2709 }
2710
2711 if (skb->len <= 0) {
2712 dev_kfree_skb_any(skb);
2713 return NETDEV_TX_OK;
2714 }
2715
2716 if (!spin_trylock_irqsave(&tx_ring->tx_lock, irq_flags))
2717 /* Collision - tell upper layer to requeue */
2718 return NETDEV_TX_LOCKED;
2719
2720 /* need: 1 descriptor per page,
2721 * + 2 desc gap to keep tail from touching head,
2722 * + 1 desc for skb->data,
2723 * + 1 desc for context descriptor,
2724 * otherwise try next time */
2725 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2726 /* this is a hard error */
2727 spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags);
2728 return NETDEV_TX_BUSY;
2729 }
2730
2731 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2732 tx_flags |= IGB_TX_FLAGS_VLAN;
2733 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2734 }
2735
2736 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
2737 &hdr_len) : 0;
2738
2739 if (tso < 0) {
2740 dev_kfree_skb_any(skb);
2741 spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags);
2742 return NETDEV_TX_OK;
2743 }
2744
2745 if (tso)
2746 tx_flags |= IGB_TX_FLAGS_TSO;
2747 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
2748 if (skb->ip_summed == CHECKSUM_PARTIAL)
2749 tx_flags |= IGB_TX_FLAGS_CSUM;
2750
2751 if (skb->protocol == htons(ETH_P_IP))
2752 tx_flags |= IGB_TX_FLAGS_IPV4;
2753
2754 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
2755 igb_tx_map_adv(adapter, tx_ring, skb),
2756 skb->len, hdr_len);
2757
2758 netdev->trans_start = jiffies;
2759
2760 /* Make sure there is space in the ring for the next send. */
2761 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
2762
2763 spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags);
2764 return NETDEV_TX_OK;
2765 }
2766
2767 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
2768 {
2769 struct igb_adapter *adapter = netdev_priv(netdev);
2770 struct igb_ring *tx_ring = &adapter->tx_ring[0];
2771
2772 /* This goes back to the question of how to logically map a tx queue
2773 * to a flow. Right now, performance is impacted slightly negatively
2774 * if using multiple tx queues. If the stack breaks away from a
2775 * single qdisc implementation, we can look at this again. */
2776 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
2777 }
2778
2779 /**
2780 * igb_tx_timeout - Respond to a Tx Hang
2781 * @netdev: network interface device structure
2782 **/
2783 static void igb_tx_timeout(struct net_device *netdev)
2784 {
2785 struct igb_adapter *adapter = netdev_priv(netdev);
2786 struct e1000_hw *hw = &adapter->hw;
2787
2788 /* Do the reset outside of interrupt context */
2789 adapter->tx_timeout_count++;
2790 schedule_work(&adapter->reset_task);
2791 wr32(E1000_EICS, adapter->eims_enable_mask &
2792 ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER));
2793 }
2794
2795 static void igb_reset_task(struct work_struct *work)
2796 {
2797 struct igb_adapter *adapter;
2798 adapter = container_of(work, struct igb_adapter, reset_task);
2799
2800 igb_reinit_locked(adapter);
2801 }
2802
2803 /**
2804 * igb_get_stats - Get System Network Statistics
2805 * @netdev: network interface device structure
2806 *
2807 * Returns the address of the device statistics structure.
2808 * The statistics are actually updated from the timer callback.
2809 **/
2810 static struct net_device_stats *
2811 igb_get_stats(struct net_device *netdev)
2812 {
2813 struct igb_adapter *adapter = netdev_priv(netdev);
2814
2815 /* only return the current stats */
2816 return &adapter->net_stats;
2817 }
2818
2819 /**
2820 * igb_change_mtu - Change the Maximum Transfer Unit
2821 * @netdev: network interface device structure
2822 * @new_mtu: new value for maximum frame size
2823 *
2824 * Returns 0 on success, negative on failure
2825 **/
2826 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
2827 {
2828 struct igb_adapter *adapter = netdev_priv(netdev);
2829 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2830
2831 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2832 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
2833 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
2834 return -EINVAL;
2835 }
2836
2837 #define MAX_STD_JUMBO_FRAME_SIZE 9234
2838 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
2839 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
2840 return -EINVAL;
2841 }
2842
2843 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
2844 msleep(1);
2845 /* igb_down has a dependency on max_frame_size */
2846 adapter->max_frame_size = max_frame;
2847 if (netif_running(netdev))
2848 igb_down(adapter);
2849
2850 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
2851 * means we reserve 2 more, this pushes us to allocate from the next
2852 * larger slab size.
2853 * i.e. RXBUFFER_2048 --> size-4096 slab
2854 */
2855
2856 if (max_frame <= IGB_RXBUFFER_256)
2857 adapter->rx_buffer_len = IGB_RXBUFFER_256;
2858 else if (max_frame <= IGB_RXBUFFER_512)
2859 adapter->rx_buffer_len = IGB_RXBUFFER_512;
2860 else if (max_frame <= IGB_RXBUFFER_1024)
2861 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
2862 else if (max_frame <= IGB_RXBUFFER_2048)
2863 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
2864 else
2865 adapter->rx_buffer_len = IGB_RXBUFFER_4096;
2866 /* adjust allocation if LPE protects us, and we aren't using SBP */
2867 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
2868 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
2869 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2870
2871 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
2872 netdev->mtu, new_mtu);
2873 netdev->mtu = new_mtu;
2874
2875 if (netif_running(netdev))
2876 igb_up(adapter);
2877 else
2878 igb_reset(adapter);
2879
2880 clear_bit(__IGB_RESETTING, &adapter->state);
2881
2882 return 0;
2883 }
2884
2885 /**
2886 * igb_update_stats - Update the board statistics counters
2887 * @adapter: board private structure
2888 **/
2889
2890 void igb_update_stats(struct igb_adapter *adapter)
2891 {
2892 struct e1000_hw *hw = &adapter->hw;
2893 struct pci_dev *pdev = adapter->pdev;
2894 u16 phy_tmp;
2895
2896 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
2897
2898 /*
2899 * Prevent stats update while adapter is being reset, or if the pci
2900 * connection is down.
2901 */
2902 if (adapter->link_speed == 0)
2903 return;
2904 if (pci_channel_offline(pdev))
2905 return;
2906
2907 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
2908 adapter->stats.gprc += rd32(E1000_GPRC);
2909 adapter->stats.gorc += rd32(E1000_GORCL);
2910 rd32(E1000_GORCH); /* clear GORCL */
2911 adapter->stats.bprc += rd32(E1000_BPRC);
2912 adapter->stats.mprc += rd32(E1000_MPRC);
2913 adapter->stats.roc += rd32(E1000_ROC);
2914
2915 adapter->stats.prc64 += rd32(E1000_PRC64);
2916 adapter->stats.prc127 += rd32(E1000_PRC127);
2917 adapter->stats.prc255 += rd32(E1000_PRC255);
2918 adapter->stats.prc511 += rd32(E1000_PRC511);
2919 adapter->stats.prc1023 += rd32(E1000_PRC1023);
2920 adapter->stats.prc1522 += rd32(E1000_PRC1522);
2921 adapter->stats.symerrs += rd32(E1000_SYMERRS);
2922 adapter->stats.sec += rd32(E1000_SEC);
2923
2924 adapter->stats.mpc += rd32(E1000_MPC);
2925 adapter->stats.scc += rd32(E1000_SCC);
2926 adapter->stats.ecol += rd32(E1000_ECOL);
2927 adapter->stats.mcc += rd32(E1000_MCC);
2928 adapter->stats.latecol += rd32(E1000_LATECOL);
2929 adapter->stats.dc += rd32(E1000_DC);
2930 adapter->stats.rlec += rd32(E1000_RLEC);
2931 adapter->stats.xonrxc += rd32(E1000_XONRXC);
2932 adapter->stats.xontxc += rd32(E1000_XONTXC);
2933 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
2934 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
2935 adapter->stats.fcruc += rd32(E1000_FCRUC);
2936 adapter->stats.gptc += rd32(E1000_GPTC);
2937 adapter->stats.gotc += rd32(E1000_GOTCL);
2938 rd32(E1000_GOTCH); /* clear GOTCL */
2939 adapter->stats.rnbc += rd32(E1000_RNBC);
2940 adapter->stats.ruc += rd32(E1000_RUC);
2941 adapter->stats.rfc += rd32(E1000_RFC);
2942 adapter->stats.rjc += rd32(E1000_RJC);
2943 adapter->stats.tor += rd32(E1000_TORH);
2944 adapter->stats.tot += rd32(E1000_TOTH);
2945 adapter->stats.tpr += rd32(E1000_TPR);
2946
2947 adapter->stats.ptc64 += rd32(E1000_PTC64);
2948 adapter->stats.ptc127 += rd32(E1000_PTC127);
2949 adapter->stats.ptc255 += rd32(E1000_PTC255);
2950 adapter->stats.ptc511 += rd32(E1000_PTC511);
2951 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
2952 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
2953
2954 adapter->stats.mptc += rd32(E1000_MPTC);
2955 adapter->stats.bptc += rd32(E1000_BPTC);
2956
2957 /* used for adaptive IFS */
2958
2959 hw->mac.tx_packet_delta = rd32(E1000_TPT);
2960 adapter->stats.tpt += hw->mac.tx_packet_delta;
2961 hw->mac.collision_delta = rd32(E1000_COLC);
2962 adapter->stats.colc += hw->mac.collision_delta;
2963
2964 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
2965 adapter->stats.rxerrc += rd32(E1000_RXERRC);
2966 adapter->stats.tncrs += rd32(E1000_TNCRS);
2967 adapter->stats.tsctc += rd32(E1000_TSCTC);
2968 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
2969
2970 adapter->stats.iac += rd32(E1000_IAC);
2971 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
2972 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
2973 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
2974 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
2975 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
2976 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
2977 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
2978 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
2979
2980 /* Fill out the OS statistics structure */
2981 adapter->net_stats.multicast = adapter->stats.mprc;
2982 adapter->net_stats.collisions = adapter->stats.colc;
2983
2984 /* Rx Errors */
2985
2986 /* RLEC on some newer hardware can be incorrect so build
2987 * our own version based on RUC and ROC */
2988 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
2989 adapter->stats.crcerrs + adapter->stats.algnerrc +
2990 adapter->stats.ruc + adapter->stats.roc +
2991 adapter->stats.cexterr;
2992 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
2993 adapter->stats.roc;
2994 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
2995 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
2996 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
2997
2998 /* Tx Errors */
2999 adapter->net_stats.tx_errors = adapter->stats.ecol +
3000 adapter->stats.latecol;
3001 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3002 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3003 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3004
3005 /* Tx Dropped needs to be maintained elsewhere */
3006
3007 /* Phy Stats */
3008 if (hw->phy.media_type == e1000_media_type_copper) {
3009 if ((adapter->link_speed == SPEED_1000) &&
3010 (!hw->phy.ops.read_phy_reg(hw, PHY_1000T_STATUS,
3011 &phy_tmp))) {
3012 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3013 adapter->phy_stats.idle_errors += phy_tmp;
3014 }
3015 }
3016
3017 /* Management Stats */
3018 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3019 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3020 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3021 }
3022
3023
3024 static irqreturn_t igb_msix_other(int irq, void *data)
3025 {
3026 struct net_device *netdev = data;
3027 struct igb_adapter *adapter = netdev_priv(netdev);
3028 struct e1000_hw *hw = &adapter->hw;
3029 u32 icr = rd32(E1000_ICR);
3030
3031 /* reading ICR causes bit 31 of EICR to be cleared */
3032 if (!(icr & E1000_ICR_LSC))
3033 goto no_link_interrupt;
3034 hw->mac.get_link_status = 1;
3035 /* guard against interrupt when we're going down */
3036 if (!test_bit(__IGB_DOWN, &adapter->state))
3037 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3038
3039 no_link_interrupt:
3040 wr32(E1000_IMS, E1000_IMS_LSC);
3041 wr32(E1000_EIMS, adapter->eims_other);
3042
3043 return IRQ_HANDLED;
3044 }
3045
3046 static irqreturn_t igb_msix_tx(int irq, void *data)
3047 {
3048 struct igb_ring *tx_ring = data;
3049 struct igb_adapter *adapter = tx_ring->adapter;
3050 struct e1000_hw *hw = &adapter->hw;
3051
3052 if (!tx_ring->itr_val)
3053 wr32(E1000_EIMC, tx_ring->eims_value);
3054
3055 tx_ring->total_bytes = 0;
3056 tx_ring->total_packets = 0;
3057 if (!igb_clean_tx_irq(tx_ring))
3058 /* Ring was not completely cleaned, so fire another interrupt */
3059 wr32(E1000_EICS, tx_ring->eims_value);
3060
3061 if (!tx_ring->itr_val)
3062 wr32(E1000_EIMS, tx_ring->eims_value);
3063 return IRQ_HANDLED;
3064 }
3065
3066 static irqreturn_t igb_msix_rx(int irq, void *data)
3067 {
3068 struct igb_ring *rx_ring = data;
3069 struct igb_adapter *adapter = rx_ring->adapter;
3070 struct e1000_hw *hw = &adapter->hw;
3071
3072 /* Write the ITR value calculated at the end of the
3073 * previous interrupt.
3074 */
3075
3076 if (adapter->set_itr) {
3077 wr32(rx_ring->itr_register,
3078 1000000000 / (rx_ring->itr_val * 256));
3079 adapter->set_itr = 0;
3080 }
3081
3082 if (netif_rx_schedule_prep(adapter->netdev, &rx_ring->napi))
3083 __netif_rx_schedule(adapter->netdev, &rx_ring->napi);
3084
3085 return IRQ_HANDLED;
3086 }
3087
3088
3089 /**
3090 * igb_intr_msi - Interrupt Handler
3091 * @irq: interrupt number
3092 * @data: pointer to a network interface device structure
3093 **/
3094 static irqreturn_t igb_intr_msi(int irq, void *data)
3095 {
3096 struct net_device *netdev = data;
3097 struct igb_adapter *adapter = netdev_priv(netdev);
3098 struct e1000_hw *hw = &adapter->hw;
3099 /* read ICR disables interrupts using IAM */
3100 u32 icr = rd32(E1000_ICR);
3101
3102 /* Write the ITR value calculated at the end of the
3103 * previous interrupt.
3104 */
3105 if (adapter->set_itr) {
3106 wr32(E1000_ITR, 1000000000 / (adapter->itr * 256));
3107 adapter->set_itr = 0;
3108 }
3109
3110 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3111 hw->mac.get_link_status = 1;
3112 if (!test_bit(__IGB_DOWN, &adapter->state))
3113 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3114 }
3115
3116 netif_rx_schedule(netdev, &adapter->rx_ring[0].napi);
3117
3118 return IRQ_HANDLED;
3119 }
3120
3121 /**
3122 * igb_intr - Interrupt Handler
3123 * @irq: interrupt number
3124 * @data: pointer to a network interface device structure
3125 **/
3126 static irqreturn_t igb_intr(int irq, void *data)
3127 {
3128 struct net_device *netdev = data;
3129 struct igb_adapter *adapter = netdev_priv(netdev);
3130 struct e1000_hw *hw = &adapter->hw;
3131 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3132 * need for the IMC write */
3133 u32 icr = rd32(E1000_ICR);
3134 u32 eicr = 0;
3135 if (!icr)
3136 return IRQ_NONE; /* Not our interrupt */
3137
3138 /* Write the ITR value calculated at the end of the
3139 * previous interrupt.
3140 */
3141 if (adapter->set_itr) {
3142 wr32(E1000_ITR, 1000000000 / (adapter->itr * 256));
3143 adapter->set_itr = 0;
3144 }
3145
3146 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3147 * not set, then the adapter didn't send an interrupt */
3148 if (!(icr & E1000_ICR_INT_ASSERTED))
3149 return IRQ_NONE;
3150
3151 eicr = rd32(E1000_EICR);
3152
3153 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3154 hw->mac.get_link_status = 1;
3155 /* guard against interrupt when we're going down */
3156 if (!test_bit(__IGB_DOWN, &adapter->state))
3157 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3158 }
3159
3160 netif_rx_schedule(netdev, &adapter->rx_ring[0].napi);
3161
3162 return IRQ_HANDLED;
3163 }
3164
3165 /**
3166 * igb_clean - NAPI Rx polling callback
3167 * @adapter: board private structure
3168 **/
3169 static int igb_clean(struct napi_struct *napi, int budget)
3170 {
3171 struct igb_adapter *adapter = container_of(napi, struct igb_adapter,
3172 napi);
3173 struct net_device *netdev = adapter->netdev;
3174 int tx_clean_complete = 1, work_done = 0;
3175 int i;
3176
3177 /* Must NOT use netdev_priv macro here. */
3178 adapter = netdev->priv;
3179
3180 /* Keep link state information with original netdev */
3181 if (!netif_carrier_ok(netdev))
3182 goto quit_polling;
3183
3184 /* igb_clean is called per-cpu. This lock protects tx_ring[i] from
3185 * being cleaned by multiple cpus simultaneously. A failure obtaining
3186 * the lock means tx_ring[i] is currently being cleaned anyway. */
3187 for (i = 0; i < adapter->num_tx_queues; i++) {
3188 if (spin_trylock(&adapter->tx_ring[i].tx_clean_lock)) {
3189 tx_clean_complete &= igb_clean_tx_irq(&adapter->tx_ring[i]);
3190 spin_unlock(&adapter->tx_ring[i].tx_clean_lock);
3191 }
3192 }
3193
3194 for (i = 0; i < adapter->num_rx_queues; i++)
3195 igb_clean_rx_irq_adv(&adapter->rx_ring[i], &work_done,
3196 adapter->rx_ring[i].napi.weight);
3197
3198 /* If no Tx and not enough Rx work done, exit the polling mode */
3199 if ((tx_clean_complete && (work_done < budget)) ||
3200 !netif_running(netdev)) {
3201 quit_polling:
3202 if (adapter->itr_setting & 3)
3203 igb_set_itr(adapter, E1000_ITR, false);
3204 netif_rx_complete(netdev, napi);
3205 if (!test_bit(__IGB_DOWN, &adapter->state))
3206 igb_irq_enable(adapter);
3207 return 0;
3208 }
3209
3210 return 1;
3211 }
3212
3213 static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3214 {
3215 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3216 struct igb_adapter *adapter = rx_ring->adapter;
3217 struct e1000_hw *hw = &adapter->hw;
3218 struct net_device *netdev = adapter->netdev;
3219 int work_done = 0;
3220
3221 /* Keep link state information with original netdev */
3222 if (!netif_carrier_ok(netdev))
3223 goto quit_polling;
3224
3225 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
3226
3227
3228 /* If not enough Rx work done, exit the polling mode */
3229 if ((work_done == 0) || !netif_running(netdev)) {
3230 quit_polling:
3231 netif_rx_complete(netdev, napi);
3232
3233 wr32(E1000_EIMS, rx_ring->eims_value);
3234 if ((adapter->itr_setting & 3) && !rx_ring->no_itr_adjust &&
3235 (rx_ring->total_packets > IGB_DYN_ITR_PACKET_THRESHOLD)) {
3236 int mean_size = rx_ring->total_bytes /
3237 rx_ring->total_packets;
3238 if (mean_size < IGB_DYN_ITR_LENGTH_LOW)
3239 igb_raise_rx_eitr(adapter, rx_ring);
3240 else if (mean_size > IGB_DYN_ITR_LENGTH_HIGH)
3241 igb_lower_rx_eitr(adapter, rx_ring);
3242 }
3243
3244 if (!test_bit(__IGB_DOWN, &adapter->state))
3245 wr32(E1000_EIMS, rx_ring->eims_value);
3246
3247 return 0;
3248 }
3249
3250 return 1;
3251 }
3252
3253 static inline u32 get_head(struct igb_ring *tx_ring)
3254 {
3255 void *end = (struct e1000_tx_desc *)tx_ring->desc + tx_ring->count;
3256 return le32_to_cpu(*(volatile __le32 *)end);
3257 }
3258
3259 /**
3260 * igb_clean_tx_irq - Reclaim resources after transmit completes
3261 * @adapter: board private structure
3262 * returns true if ring is completely cleaned
3263 **/
3264 static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
3265 {
3266 struct igb_adapter *adapter = tx_ring->adapter;
3267 struct e1000_hw *hw = &adapter->hw;
3268 struct net_device *netdev = adapter->netdev;
3269 struct e1000_tx_desc *tx_desc;
3270 struct igb_buffer *buffer_info;
3271 struct sk_buff *skb;
3272 unsigned int i;
3273 u32 head, oldhead;
3274 unsigned int count = 0;
3275 bool cleaned = false;
3276 bool retval = true;
3277 unsigned int total_bytes = 0, total_packets = 0;
3278
3279 rmb();
3280 head = get_head(tx_ring);
3281 i = tx_ring->next_to_clean;
3282 while (1) {
3283 while (i != head) {
3284 cleaned = true;
3285 tx_desc = E1000_TX_DESC(*tx_ring, i);
3286 buffer_info = &tx_ring->buffer_info[i];
3287 skb = buffer_info->skb;
3288
3289 if (skb) {
3290 unsigned int segs, bytecount;
3291 /* gso_segs is currently only valid for tcp */
3292 segs = skb_shinfo(skb)->gso_segs ?: 1;
3293 /* multiply data chunks by size of headers */
3294 bytecount = ((segs - 1) * skb_headlen(skb)) +
3295 skb->len;
3296 total_packets += segs;
3297 total_bytes += bytecount;
3298 }
3299
3300 igb_unmap_and_free_tx_resource(adapter, buffer_info);
3301 tx_desc->upper.data = 0;
3302
3303 i++;
3304 if (i == tx_ring->count)
3305 i = 0;
3306
3307 count++;
3308 if (count == IGB_MAX_TX_CLEAN) {
3309 retval = false;
3310 goto done_cleaning;
3311 }
3312 }
3313 oldhead = head;
3314 rmb();
3315 head = get_head(tx_ring);
3316 if (head == oldhead)
3317 goto done_cleaning;
3318 } /* while (1) */
3319
3320 done_cleaning:
3321 tx_ring->next_to_clean = i;
3322
3323 if (unlikely(cleaned &&
3324 netif_carrier_ok(netdev) &&
3325 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3326 /* Make sure that anybody stopping the queue after this
3327 * sees the new next_to_clean.
3328 */
3329 smp_mb();
3330 if (netif_queue_stopped(netdev) &&
3331 !(test_bit(__IGB_DOWN, &adapter->state))) {
3332 netif_wake_queue(netdev);
3333 ++adapter->restart_queue;
3334 }
3335 }
3336
3337 if (tx_ring->detect_tx_hung) {
3338 /* Detect a transmit hang in hardware, this serializes the
3339 * check with the clearing of time_stamp and movement of i */
3340 tx_ring->detect_tx_hung = false;
3341 if (tx_ring->buffer_info[i].time_stamp &&
3342 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3343 (adapter->tx_timeout_factor * HZ))
3344 && !(rd32(E1000_STATUS) &
3345 E1000_STATUS_TXOFF)) {
3346
3347 tx_desc = E1000_TX_DESC(*tx_ring, i);
3348 /* detected Tx unit hang */
3349 dev_err(&adapter->pdev->dev,
3350 "Detected Tx Unit Hang\n"
3351 " Tx Queue <%lu>\n"
3352 " TDH <%x>\n"
3353 " TDT <%x>\n"
3354 " next_to_use <%x>\n"
3355 " next_to_clean <%x>\n"
3356 " head (WB) <%x>\n"
3357 "buffer_info[next_to_clean]\n"
3358 " time_stamp <%lx>\n"
3359 " jiffies <%lx>\n"
3360 " desc.status <%x>\n",
3361 (unsigned long)((tx_ring - adapter->tx_ring) /
3362 sizeof(struct igb_ring)),
3363 readl(adapter->hw.hw_addr + tx_ring->head),
3364 readl(adapter->hw.hw_addr + tx_ring->tail),
3365 tx_ring->next_to_use,
3366 tx_ring->next_to_clean,
3367 head,
3368 tx_ring->buffer_info[i].time_stamp,
3369 jiffies,
3370 tx_desc->upper.fields.status);
3371 netif_stop_queue(netdev);
3372 }
3373 }
3374 tx_ring->total_bytes += total_bytes;
3375 tx_ring->total_packets += total_packets;
3376 adapter->net_stats.tx_bytes += total_bytes;
3377 adapter->net_stats.tx_packets += total_packets;
3378 return retval;
3379 }
3380
3381
3382 /**
3383 * igb_receive_skb - helper function to handle rx indications
3384 * @adapter: board private structure
3385 * @status: descriptor status field as written by hardware
3386 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3387 * @skb: pointer to sk_buff to be indicated to stack
3388 **/
3389 static void igb_receive_skb(struct igb_adapter *adapter, u8 status, __le16 vlan,
3390 struct sk_buff *skb)
3391 {
3392 if (adapter->vlgrp && (status & E1000_RXD_STAT_VP))
3393 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3394 le16_to_cpu(vlan) &
3395 E1000_RXD_SPC_VLAN_MASK);
3396 else
3397 netif_receive_skb(skb);
3398 }
3399
3400
3401 static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3402 u32 status_err, struct sk_buff *skb)
3403 {
3404 skb->ip_summed = CHECKSUM_NONE;
3405
3406 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3407 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3408 return;
3409 /* TCP/UDP checksum error bit is set */
3410 if (status_err &
3411 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3412 /* let the stack verify checksum errors */
3413 adapter->hw_csum_err++;
3414 return;
3415 }
3416 /* It must be a TCP or UDP packet with a valid checksum */
3417 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3418 skb->ip_summed = CHECKSUM_UNNECESSARY;
3419
3420 adapter->hw_csum_good++;
3421 }
3422
3423 static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3424 int *work_done, int budget)
3425 {
3426 struct igb_adapter *adapter = rx_ring->adapter;
3427 struct net_device *netdev = adapter->netdev;
3428 struct pci_dev *pdev = adapter->pdev;
3429 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3430 struct igb_buffer *buffer_info , *next_buffer;
3431 struct sk_buff *skb;
3432 unsigned int i, j;
3433 u32 length, hlen, staterr;
3434 bool cleaned = false;
3435 int cleaned_count = 0;
3436 unsigned int total_bytes = 0, total_packets = 0;
3437
3438 i = rx_ring->next_to_clean;
3439 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3440 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3441
3442 while (staterr & E1000_RXD_STAT_DD) {
3443 if (*work_done >= budget)
3444 break;
3445 (*work_done)++;
3446 buffer_info = &rx_ring->buffer_info[i];
3447
3448 /* HW will not DMA in data larger than the given buffer, even
3449 * if it parses the (NFS, of course) header to be larger. In
3450 * that case, it fills the header buffer and spills the rest
3451 * into the page.
3452 */
3453 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
3454 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
3455 if (hlen > adapter->rx_ps_hdr_size)
3456 hlen = adapter->rx_ps_hdr_size;
3457
3458 length = le16_to_cpu(rx_desc->wb.upper.length);
3459 cleaned = true;
3460 cleaned_count++;
3461
3462 if (rx_ring->pending_skb != NULL) {
3463 skb = rx_ring->pending_skb;
3464 rx_ring->pending_skb = NULL;
3465 j = rx_ring->pending_skb_page;
3466 } else {
3467 skb = buffer_info->skb;
3468 prefetch(skb->data - NET_IP_ALIGN);
3469 buffer_info->skb = NULL;
3470 if (hlen) {
3471 pci_unmap_single(pdev, buffer_info->dma,
3472 adapter->rx_ps_hdr_size +
3473 NET_IP_ALIGN,
3474 PCI_DMA_FROMDEVICE);
3475 skb_put(skb, hlen);
3476 } else {
3477 pci_unmap_single(pdev, buffer_info->dma,
3478 adapter->rx_buffer_len +
3479 NET_IP_ALIGN,
3480 PCI_DMA_FROMDEVICE);
3481 skb_put(skb, length);
3482 goto send_up;
3483 }
3484 j = 0;
3485 }
3486
3487 while (length) {
3488 pci_unmap_page(pdev, buffer_info->page_dma,
3489 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3490 buffer_info->page_dma = 0;
3491 skb_fill_page_desc(skb, j, buffer_info->page,
3492 0, length);
3493 buffer_info->page = NULL;
3494
3495 skb->len += length;
3496 skb->data_len += length;
3497 skb->truesize += length;
3498 rx_desc->wb.upper.status_error = 0;
3499 if (staterr & E1000_RXD_STAT_EOP)
3500 break;
3501
3502 j++;
3503 cleaned_count++;
3504 i++;
3505 if (i == rx_ring->count)
3506 i = 0;
3507
3508 buffer_info = &rx_ring->buffer_info[i];
3509 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3510 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3511 length = le16_to_cpu(rx_desc->wb.upper.length);
3512 if (!(staterr & E1000_RXD_STAT_DD)) {
3513 rx_ring->pending_skb = skb;
3514 rx_ring->pending_skb_page = j;
3515 goto out;
3516 }
3517 }
3518 send_up:
3519 pskb_trim(skb, skb->len - 4);
3520 i++;
3521 if (i == rx_ring->count)
3522 i = 0;
3523 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3524 prefetch(next_rxd);
3525 next_buffer = &rx_ring->buffer_info[i];
3526
3527 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3528 dev_kfree_skb_irq(skb);
3529 goto next_desc;
3530 }
3531 rx_ring->no_itr_adjust |= (staterr & E1000_RXD_STAT_DYNINT);
3532
3533 total_bytes += skb->len;
3534 total_packets++;
3535
3536 igb_rx_checksum_adv(adapter, staterr, skb);
3537
3538 skb->protocol = eth_type_trans(skb, netdev);
3539
3540 igb_receive_skb(adapter, staterr, rx_desc->wb.upper.vlan, skb);
3541
3542 netdev->last_rx = jiffies;
3543
3544 next_desc:
3545 rx_desc->wb.upper.status_error = 0;
3546
3547 /* return some buffers to hardware, one at a time is too slow */
3548 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3549 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
3550 cleaned_count = 0;
3551 }
3552
3553 /* use prefetched values */
3554 rx_desc = next_rxd;
3555 buffer_info = next_buffer;
3556
3557 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3558 }
3559 out:
3560 rx_ring->next_to_clean = i;
3561 cleaned_count = IGB_DESC_UNUSED(rx_ring);
3562
3563 if (cleaned_count)
3564 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
3565
3566 rx_ring->total_packets += total_packets;
3567 rx_ring->total_bytes += total_bytes;
3568 rx_ring->rx_stats.packets += total_packets;
3569 rx_ring->rx_stats.bytes += total_bytes;
3570 adapter->net_stats.rx_bytes += total_bytes;
3571 adapter->net_stats.rx_packets += total_packets;
3572 return cleaned;
3573 }
3574
3575
3576 /**
3577 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
3578 * @adapter: address of board private structure
3579 **/
3580 static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
3581 int cleaned_count)
3582 {
3583 struct igb_adapter *adapter = rx_ring->adapter;
3584 struct net_device *netdev = adapter->netdev;
3585 struct pci_dev *pdev = adapter->pdev;
3586 union e1000_adv_rx_desc *rx_desc;
3587 struct igb_buffer *buffer_info;
3588 struct sk_buff *skb;
3589 unsigned int i;
3590
3591 i = rx_ring->next_to_use;
3592 buffer_info = &rx_ring->buffer_info[i];
3593
3594 while (cleaned_count--) {
3595 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3596
3597 if (adapter->rx_ps_hdr_size && !buffer_info->page) {
3598 buffer_info->page = alloc_page(GFP_ATOMIC);
3599 if (!buffer_info->page) {
3600 adapter->alloc_rx_buff_failed++;
3601 goto no_buffers;
3602 }
3603 buffer_info->page_dma =
3604 pci_map_page(pdev,
3605 buffer_info->page,
3606 0, PAGE_SIZE,
3607 PCI_DMA_FROMDEVICE);
3608 }
3609
3610 if (!buffer_info->skb) {
3611 int bufsz;
3612
3613 if (adapter->rx_ps_hdr_size)
3614 bufsz = adapter->rx_ps_hdr_size;
3615 else
3616 bufsz = adapter->rx_buffer_len;
3617 bufsz += NET_IP_ALIGN;
3618 skb = netdev_alloc_skb(netdev, bufsz);
3619
3620 if (!skb) {
3621 adapter->alloc_rx_buff_failed++;
3622 goto no_buffers;
3623 }
3624
3625 /* Make buffer alignment 2 beyond a 16 byte boundary
3626 * this will result in a 16 byte aligned IP header after
3627 * the 14 byte MAC header is removed
3628 */
3629 skb_reserve(skb, NET_IP_ALIGN);
3630
3631 buffer_info->skb = skb;
3632 buffer_info->dma = pci_map_single(pdev, skb->data,
3633 bufsz,
3634 PCI_DMA_FROMDEVICE);
3635
3636 }
3637 /* Refresh the desc even if buffer_addrs didn't change because
3638 * each write-back erases this info. */
3639 if (adapter->rx_ps_hdr_size) {
3640 rx_desc->read.pkt_addr =
3641 cpu_to_le64(buffer_info->page_dma);
3642 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
3643 } else {
3644 rx_desc->read.pkt_addr =
3645 cpu_to_le64(buffer_info->dma);
3646 rx_desc->read.hdr_addr = 0;
3647 }
3648
3649 i++;
3650 if (i == rx_ring->count)
3651 i = 0;
3652 buffer_info = &rx_ring->buffer_info[i];
3653 }
3654
3655 no_buffers:
3656 if (rx_ring->next_to_use != i) {
3657 rx_ring->next_to_use = i;
3658 if (i == 0)
3659 i = (rx_ring->count - 1);
3660 else
3661 i--;
3662
3663 /* Force memory writes to complete before letting h/w
3664 * know there are new descriptors to fetch. (Only
3665 * applicable for weak-ordered memory model archs,
3666 * such as IA-64). */
3667 wmb();
3668 writel(i, adapter->hw.hw_addr + rx_ring->tail);
3669 }
3670 }
3671
3672 /**
3673 * igb_mii_ioctl -
3674 * @netdev:
3675 * @ifreq:
3676 * @cmd:
3677 **/
3678 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3679 {
3680 struct igb_adapter *adapter = netdev_priv(netdev);
3681 struct mii_ioctl_data *data = if_mii(ifr);
3682
3683 if (adapter->hw.phy.media_type != e1000_media_type_copper)
3684 return -EOPNOTSUPP;
3685
3686 switch (cmd) {
3687 case SIOCGMIIPHY:
3688 data->phy_id = adapter->hw.phy.addr;
3689 break;
3690 case SIOCGMIIREG:
3691 if (!capable(CAP_NET_ADMIN))
3692 return -EPERM;
3693 if (adapter->hw.phy.ops.read_phy_reg(&adapter->hw,
3694 data->reg_num
3695 & 0x1F, &data->val_out))
3696 return -EIO;
3697 break;
3698 case SIOCSMIIREG:
3699 default:
3700 return -EOPNOTSUPP;
3701 }
3702 return 0;
3703 }
3704
3705 /**
3706 * igb_ioctl -
3707 * @netdev:
3708 * @ifreq:
3709 * @cmd:
3710 **/
3711 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3712 {
3713 switch (cmd) {
3714 case SIOCGMIIPHY:
3715 case SIOCGMIIREG:
3716 case SIOCSMIIREG:
3717 return igb_mii_ioctl(netdev, ifr, cmd);
3718 default:
3719 return -EOPNOTSUPP;
3720 }
3721 }
3722
3723 static void igb_vlan_rx_register(struct net_device *netdev,
3724 struct vlan_group *grp)
3725 {
3726 struct igb_adapter *adapter = netdev_priv(netdev);
3727 struct e1000_hw *hw = &adapter->hw;
3728 u32 ctrl, rctl;
3729
3730 igb_irq_disable(adapter);
3731 adapter->vlgrp = grp;
3732
3733 if (grp) {
3734 /* enable VLAN tag insert/strip */
3735 ctrl = rd32(E1000_CTRL);
3736 ctrl |= E1000_CTRL_VME;
3737 wr32(E1000_CTRL, ctrl);
3738
3739 /* enable VLAN receive filtering */
3740 rctl = rd32(E1000_RCTL);
3741 rctl |= E1000_RCTL_VFE;
3742 rctl &= ~E1000_RCTL_CFIEN;
3743 wr32(E1000_RCTL, rctl);
3744 igb_update_mng_vlan(adapter);
3745 wr32(E1000_RLPML,
3746 adapter->max_frame_size + VLAN_TAG_SIZE);
3747 } else {
3748 /* disable VLAN tag insert/strip */
3749 ctrl = rd32(E1000_CTRL);
3750 ctrl &= ~E1000_CTRL_VME;
3751 wr32(E1000_CTRL, ctrl);
3752
3753 /* disable VLAN filtering */
3754 rctl = rd32(E1000_RCTL);
3755 rctl &= ~E1000_RCTL_VFE;
3756 wr32(E1000_RCTL, rctl);
3757 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
3758 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
3759 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
3760 }
3761 wr32(E1000_RLPML,
3762 adapter->max_frame_size);
3763 }
3764
3765 if (!test_bit(__IGB_DOWN, &adapter->state))
3766 igb_irq_enable(adapter);
3767 }
3768
3769 static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3770 {
3771 struct igb_adapter *adapter = netdev_priv(netdev);
3772 struct e1000_hw *hw = &adapter->hw;
3773 u32 vfta, index;
3774
3775 if ((adapter->hw.mng_cookie.status &
3776 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
3777 (vid == adapter->mng_vlan_id))
3778 return;
3779 /* add VID to filter table */
3780 index = (vid >> 5) & 0x7F;
3781 vfta = array_rd32(E1000_VFTA, index);
3782 vfta |= (1 << (vid & 0x1F));
3783 igb_write_vfta(&adapter->hw, index, vfta);
3784 }
3785
3786 static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3787 {
3788 struct igb_adapter *adapter = netdev_priv(netdev);
3789 struct e1000_hw *hw = &adapter->hw;
3790 u32 vfta, index;
3791
3792 igb_irq_disable(adapter);
3793 vlan_group_set_device(adapter->vlgrp, vid, NULL);
3794
3795 if (!test_bit(__IGB_DOWN, &adapter->state))
3796 igb_irq_enable(adapter);
3797
3798 if ((adapter->hw.mng_cookie.status &
3799 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
3800 (vid == adapter->mng_vlan_id)) {
3801 /* release control to f/w */
3802 igb_release_hw_control(adapter);
3803 return;
3804 }
3805
3806 /* remove VID from filter table */
3807 index = (vid >> 5) & 0x7F;
3808 vfta = array_rd32(E1000_VFTA, index);
3809 vfta &= ~(1 << (vid & 0x1F));
3810 igb_write_vfta(&adapter->hw, index, vfta);
3811 }
3812
3813 static void igb_restore_vlan(struct igb_adapter *adapter)
3814 {
3815 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
3816
3817 if (adapter->vlgrp) {
3818 u16 vid;
3819 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
3820 if (!vlan_group_get_device(adapter->vlgrp, vid))
3821 continue;
3822 igb_vlan_rx_add_vid(adapter->netdev, vid);
3823 }
3824 }
3825 }
3826
3827 int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
3828 {
3829 struct e1000_mac_info *mac = &adapter->hw.mac;
3830
3831 mac->autoneg = 0;
3832
3833 /* Fiber NICs only allow 1000 gbps Full duplex */
3834 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
3835 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
3836 dev_err(&adapter->pdev->dev,
3837 "Unsupported Speed/Duplex configuration\n");
3838 return -EINVAL;
3839 }
3840
3841 switch (spddplx) {
3842 case SPEED_10 + DUPLEX_HALF:
3843 mac->forced_speed_duplex = ADVERTISE_10_HALF;
3844 break;
3845 case SPEED_10 + DUPLEX_FULL:
3846 mac->forced_speed_duplex = ADVERTISE_10_FULL;
3847 break;
3848 case SPEED_100 + DUPLEX_HALF:
3849 mac->forced_speed_duplex = ADVERTISE_100_HALF;
3850 break;
3851 case SPEED_100 + DUPLEX_FULL:
3852 mac->forced_speed_duplex = ADVERTISE_100_FULL;
3853 break;
3854 case SPEED_1000 + DUPLEX_FULL:
3855 mac->autoneg = 1;
3856 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
3857 break;
3858 case SPEED_1000 + DUPLEX_HALF: /* not supported */
3859 default:
3860 dev_err(&adapter->pdev->dev,
3861 "Unsupported Speed/Duplex configuration\n");
3862 return -EINVAL;
3863 }
3864 return 0;
3865 }
3866
3867
3868 static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
3869 {
3870 struct net_device *netdev = pci_get_drvdata(pdev);
3871 struct igb_adapter *adapter = netdev_priv(netdev);
3872 struct e1000_hw *hw = &adapter->hw;
3873 u32 ctrl, ctrl_ext, rctl, status;
3874 u32 wufc = adapter->wol;
3875 #ifdef CONFIG_PM
3876 int retval = 0;
3877 #endif
3878
3879 netif_device_detach(netdev);
3880
3881 if (netif_running(netdev)) {
3882 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
3883 igb_down(adapter);
3884 igb_free_irq(adapter);
3885 }
3886
3887 #ifdef CONFIG_PM
3888 retval = pci_save_state(pdev);
3889 if (retval)
3890 return retval;
3891 #endif
3892
3893 status = rd32(E1000_STATUS);
3894 if (status & E1000_STATUS_LU)
3895 wufc &= ~E1000_WUFC_LNKC;
3896
3897 if (wufc) {
3898 igb_setup_rctl(adapter);
3899 igb_set_multi(netdev);
3900
3901 /* turn on all-multi mode if wake on multicast is enabled */
3902 if (wufc & E1000_WUFC_MC) {
3903 rctl = rd32(E1000_RCTL);
3904 rctl |= E1000_RCTL_MPE;
3905 wr32(E1000_RCTL, rctl);
3906 }
3907
3908 ctrl = rd32(E1000_CTRL);
3909 /* advertise wake from D3Cold */
3910 #define E1000_CTRL_ADVD3WUC 0x00100000
3911 /* phy power management enable */
3912 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
3913 ctrl |= E1000_CTRL_ADVD3WUC;
3914 wr32(E1000_CTRL, ctrl);
3915
3916 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
3917 adapter->hw.phy.media_type ==
3918 e1000_media_type_internal_serdes) {
3919 /* keep the laser running in D3 */
3920 ctrl_ext = rd32(E1000_CTRL_EXT);
3921 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
3922 wr32(E1000_CTRL_EXT, ctrl_ext);
3923 }
3924
3925 /* Allow time for pending master requests to run */
3926 igb_disable_pcie_master(&adapter->hw);
3927
3928 wr32(E1000_WUC, E1000_WUC_PME_EN);
3929 wr32(E1000_WUFC, wufc);
3930 pci_enable_wake(pdev, PCI_D3hot, 1);
3931 pci_enable_wake(pdev, PCI_D3cold, 1);
3932 } else {
3933 wr32(E1000_WUC, 0);
3934 wr32(E1000_WUFC, 0);
3935 pci_enable_wake(pdev, PCI_D3hot, 0);
3936 pci_enable_wake(pdev, PCI_D3cold, 0);
3937 }
3938
3939 /* make sure adapter isn't asleep if manageability is enabled */
3940 if (adapter->en_mng_pt) {
3941 pci_enable_wake(pdev, PCI_D3hot, 1);
3942 pci_enable_wake(pdev, PCI_D3cold, 1);
3943 }
3944
3945 /* Release control of h/w to f/w. If f/w is AMT enabled, this
3946 * would have already happened in close and is redundant. */
3947 igb_release_hw_control(adapter);
3948
3949 pci_disable_device(pdev);
3950
3951 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3952
3953 return 0;
3954 }
3955
3956 #ifdef CONFIG_PM
3957 static int igb_resume(struct pci_dev *pdev)
3958 {
3959 struct net_device *netdev = pci_get_drvdata(pdev);
3960 struct igb_adapter *adapter = netdev_priv(netdev);
3961 struct e1000_hw *hw = &adapter->hw;
3962 u32 err;
3963
3964 pci_set_power_state(pdev, PCI_D0);
3965 pci_restore_state(pdev);
3966
3967 if (adapter->need_ioport)
3968 err = pci_enable_device(pdev);
3969 else
3970 err = pci_enable_device_mem(pdev);
3971 if (err) {
3972 dev_err(&pdev->dev,
3973 "igb: Cannot enable PCI device from suspend\n");
3974 return err;
3975 }
3976 pci_set_master(pdev);
3977
3978 pci_enable_wake(pdev, PCI_D3hot, 0);
3979 pci_enable_wake(pdev, PCI_D3cold, 0);
3980
3981 if (netif_running(netdev)) {
3982 err = igb_request_irq(adapter);
3983 if (err)
3984 return err;
3985 }
3986
3987 /* e1000_power_up_phy(adapter); */
3988
3989 igb_reset(adapter);
3990 wr32(E1000_WUS, ~0);
3991
3992 igb_init_manageability(adapter);
3993
3994 if (netif_running(netdev))
3995 igb_up(adapter);
3996
3997 netif_device_attach(netdev);
3998
3999 /* let the f/w know that the h/w is now under the control of the
4000 * driver. */
4001 igb_get_hw_control(adapter);
4002
4003 return 0;
4004 }
4005 #endif
4006
4007 static void igb_shutdown(struct pci_dev *pdev)
4008 {
4009 igb_suspend(pdev, PMSG_SUSPEND);
4010 }
4011
4012 #ifdef CONFIG_NET_POLL_CONTROLLER
4013 /*
4014 * Polling 'interrupt' - used by things like netconsole to send skbs
4015 * without having to re-enable interrupts. It's not called while
4016 * the interrupt routine is executing.
4017 */
4018 static void igb_netpoll(struct net_device *netdev)
4019 {
4020 struct igb_adapter *adapter = netdev_priv(netdev);
4021 int i;
4022 int work_done = 0;
4023
4024 igb_irq_disable(adapter);
4025 for (i = 0; i < adapter->num_tx_queues; i++)
4026 igb_clean_tx_irq(&adapter->tx_ring[i]);
4027
4028 for (i = 0; i < adapter->num_rx_queues; i++)
4029 igb_clean_rx_irq_adv(&adapter->rx_ring[i],
4030 &work_done,
4031 adapter->rx_ring[i].napi.weight);
4032
4033 igb_irq_enable(adapter);
4034 }
4035 #endif /* CONFIG_NET_POLL_CONTROLLER */
4036
4037 /**
4038 * igb_io_error_detected - called when PCI error is detected
4039 * @pdev: Pointer to PCI device
4040 * @state: The current pci connection state
4041 *
4042 * This function is called after a PCI bus error affecting
4043 * this device has been detected.
4044 */
4045 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4046 pci_channel_state_t state)
4047 {
4048 struct net_device *netdev = pci_get_drvdata(pdev);
4049 struct igb_adapter *adapter = netdev_priv(netdev);
4050
4051 netif_device_detach(netdev);
4052
4053 if (netif_running(netdev))
4054 igb_down(adapter);
4055 pci_disable_device(pdev);
4056
4057 /* Request a slot slot reset. */
4058 return PCI_ERS_RESULT_NEED_RESET;
4059 }
4060
4061 /**
4062 * igb_io_slot_reset - called after the pci bus has been reset.
4063 * @pdev: Pointer to PCI device
4064 *
4065 * Restart the card from scratch, as if from a cold-boot. Implementation
4066 * resembles the first-half of the igb_resume routine.
4067 */
4068 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4069 {
4070 struct net_device *netdev = pci_get_drvdata(pdev);
4071 struct igb_adapter *adapter = netdev_priv(netdev);
4072 struct e1000_hw *hw = &adapter->hw;
4073 int err;
4074
4075 if (adapter->need_ioport)
4076 err = pci_enable_device(pdev);
4077 else
4078 err = pci_enable_device_mem(pdev);
4079 if (err) {
4080 dev_err(&pdev->dev,
4081 "Cannot re-enable PCI device after reset.\n");
4082 return PCI_ERS_RESULT_DISCONNECT;
4083 }
4084 pci_set_master(pdev);
4085 pci_restore_state(pdev);
4086
4087 pci_enable_wake(pdev, PCI_D3hot, 0);
4088 pci_enable_wake(pdev, PCI_D3cold, 0);
4089
4090 igb_reset(adapter);
4091 wr32(E1000_WUS, ~0);
4092
4093 return PCI_ERS_RESULT_RECOVERED;
4094 }
4095
4096 /**
4097 * igb_io_resume - called when traffic can start flowing again.
4098 * @pdev: Pointer to PCI device
4099 *
4100 * This callback is called when the error recovery driver tells us that
4101 * its OK to resume normal operation. Implementation resembles the
4102 * second-half of the igb_resume routine.
4103 */
4104 static void igb_io_resume(struct pci_dev *pdev)
4105 {
4106 struct net_device *netdev = pci_get_drvdata(pdev);
4107 struct igb_adapter *adapter = netdev_priv(netdev);
4108
4109 igb_init_manageability(adapter);
4110
4111 if (netif_running(netdev)) {
4112 if (igb_up(adapter)) {
4113 dev_err(&pdev->dev, "igb_up failed after reset\n");
4114 return;
4115 }
4116 }
4117
4118 netif_device_attach(netdev);
4119
4120 /* let the f/w know that the h/w is now under the control of the
4121 * driver. */
4122 igb_get_hw_control(adapter);
4123
4124 }
4125
4126 /* igb_main.c */
Linux kernel - Deliverables
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