1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/module.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/vmalloc.h>
32 #include <linux/pagemap.h>
33 #include <linux/netdevice.h>
34 #include <linux/ipv6.h>
35 #include <net/checksum.h>
36 #include <net/ip6_checksum.h>
37 #include <linux/net_tstamp.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
40 #include <linux/if_vlan.h>
41 #include <linux/pci.h>
42 #include <linux/pci-aspm.h>
43 #include <linux/delay.h>
44 #include <linux/interrupt.h>
45 #include <linux/if_ether.h>
46 #include <linux/aer.h>
48 #include <linux/dca.h>
52 #define DRV_VERSION "1.3.16-k2"
53 char igb_driver_name
[] = "igb";
54 char igb_driver_version
[] = DRV_VERSION
;
55 static const char igb_driver_string
[] =
56 "Intel(R) Gigabit Ethernet Network Driver";
57 static const char igb_copyright
[] = "Copyright (c) 2007-2009 Intel Corporation.";
59 static const struct e1000_info
*igb_info_tbl
[] = {
60 [board_82575
] = &e1000_82575_info
,
63 static struct pci_device_id igb_pci_tbl
[] = {
64 { PCI_VDEVICE(INTEL
, E1000_DEV_ID_82576
), board_82575
},
65 { PCI_VDEVICE(INTEL
, E1000_DEV_ID_82576_NS
), board_82575
},
66 { PCI_VDEVICE(INTEL
, E1000_DEV_ID_82576_NS_SERDES
), board_82575
},
67 { PCI_VDEVICE(INTEL
, E1000_DEV_ID_82576_FIBER
), board_82575
},
68 { PCI_VDEVICE(INTEL
, E1000_DEV_ID_82576_SERDES
), board_82575
},
69 { PCI_VDEVICE(INTEL
, E1000_DEV_ID_82576_SERDES_QUAD
), board_82575
},
70 { PCI_VDEVICE(INTEL
, E1000_DEV_ID_82576_QUAD_COPPER
), board_82575
},
71 { PCI_VDEVICE(INTEL
, E1000_DEV_ID_82575EB_COPPER
), board_82575
},
72 { PCI_VDEVICE(INTEL
, E1000_DEV_ID_82575EB_FIBER_SERDES
), board_82575
},
73 { PCI_VDEVICE(INTEL
, E1000_DEV_ID_82575GB_QUAD_COPPER
), board_82575
},
74 /* required last entry */
78 MODULE_DEVICE_TABLE(pci
, igb_pci_tbl
);
80 void igb_reset(struct igb_adapter
*);
81 static int igb_setup_all_tx_resources(struct igb_adapter
*);
82 static int igb_setup_all_rx_resources(struct igb_adapter
*);
83 static void igb_free_all_tx_resources(struct igb_adapter
*);
84 static void igb_free_all_rx_resources(struct igb_adapter
*);
85 void igb_update_stats(struct igb_adapter
*);
86 static int igb_probe(struct pci_dev
*, const struct pci_device_id
*);
87 static void __devexit
igb_remove(struct pci_dev
*pdev
);
88 static int igb_sw_init(struct igb_adapter
*);
89 static int igb_open(struct net_device
*);
90 static int igb_close(struct net_device
*);
91 static void igb_configure_tx(struct igb_adapter
*);
92 static void igb_configure_rx(struct igb_adapter
*);
93 static void igb_setup_tctl(struct igb_adapter
*);
94 static void igb_setup_rctl(struct igb_adapter
*);
95 static void igb_clean_all_tx_rings(struct igb_adapter
*);
96 static void igb_clean_all_rx_rings(struct igb_adapter
*);
97 static void igb_clean_tx_ring(struct igb_ring
*);
98 static void igb_clean_rx_ring(struct igb_ring
*);
99 static void igb_set_rx_mode(struct net_device
*);
100 static void igb_update_phy_info(unsigned long);
101 static void igb_watchdog(unsigned long);
102 static void igb_watchdog_task(struct work_struct
*);
103 static netdev_tx_t
igb_xmit_frame_ring_adv(struct sk_buff
*,
106 static netdev_tx_t
igb_xmit_frame_adv(struct sk_buff
*skb
,
107 struct net_device
*);
108 static struct net_device_stats
*igb_get_stats(struct net_device
*);
109 static int igb_change_mtu(struct net_device
*, int);
110 static int igb_set_mac(struct net_device
*, void *);
111 static void igb_set_uta(struct igb_adapter
*adapter
);
112 static irqreturn_t
igb_intr(int irq
, void *);
113 static irqreturn_t
igb_intr_msi(int irq
, void *);
114 static irqreturn_t
igb_msix_other(int irq
, void *);
115 static irqreturn_t
igb_msix_ring(int irq
, void *);
116 #ifdef CONFIG_IGB_DCA
117 static void igb_update_dca(struct igb_q_vector
*);
118 static void igb_setup_dca(struct igb_adapter
*);
119 #endif /* CONFIG_IGB_DCA */
120 static bool igb_clean_tx_irq(struct igb_q_vector
*);
121 static int igb_poll(struct napi_struct
*, int);
122 static bool igb_clean_rx_irq_adv(struct igb_q_vector
*, int *, int);
123 static void igb_alloc_rx_buffers_adv(struct igb_ring
*, int);
124 static int igb_ioctl(struct net_device
*, struct ifreq
*, int cmd
);
125 static void igb_tx_timeout(struct net_device
*);
126 static void igb_reset_task(struct work_struct
*);
127 static void igb_vlan_rx_register(struct net_device
*, struct vlan_group
*);
128 static void igb_vlan_rx_add_vid(struct net_device
*, u16
);
129 static void igb_vlan_rx_kill_vid(struct net_device
*, u16
);
130 static void igb_restore_vlan(struct igb_adapter
*);
131 static void igb_rar_set_qsel(struct igb_adapter
*, u8
*, u32
, u8
);
132 static void igb_ping_all_vfs(struct igb_adapter
*);
133 static void igb_msg_task(struct igb_adapter
*);
134 static int igb_rcv_msg_from_vf(struct igb_adapter
*, u32
);
135 static void igb_vmm_control(struct igb_adapter
*);
136 static int igb_set_vf_mac(struct igb_adapter
*adapter
, int, unsigned char *);
137 static void igb_restore_vf_multicasts(struct igb_adapter
*adapter
);
139 static inline void igb_set_vmolr(struct e1000_hw
*hw
, int vfn
)
143 reg_data
= rd32(E1000_VMOLR(vfn
));
144 reg_data
|= E1000_VMOLR_BAM
| /* Accept broadcast */
145 E1000_VMOLR_ROMPE
| /* Accept packets matched in MTA */
146 E1000_VMOLR_AUPE
| /* Accept untagged packets */
147 E1000_VMOLR_STRVLAN
; /* Strip vlan tags */
148 wr32(E1000_VMOLR(vfn
), reg_data
);
151 static inline int igb_set_vf_rlpml(struct igb_adapter
*adapter
, int size
,
154 struct e1000_hw
*hw
= &adapter
->hw
;
157 /* if it isn't the PF check to see if VFs are enabled and
158 * increase the size to support vlan tags */
159 if (vfn
< adapter
->vfs_allocated_count
&&
160 adapter
->vf_data
[vfn
].vlans_enabled
)
161 size
+= VLAN_TAG_SIZE
;
163 vmolr
= rd32(E1000_VMOLR(vfn
));
164 vmolr
&= ~E1000_VMOLR_RLPML_MASK
;
165 vmolr
|= size
| E1000_VMOLR_LPE
;
166 wr32(E1000_VMOLR(vfn
), vmolr
);
172 static int igb_suspend(struct pci_dev
*, pm_message_t
);
173 static int igb_resume(struct pci_dev
*);
175 static void igb_shutdown(struct pci_dev
*);
176 #ifdef CONFIG_IGB_DCA
177 static int igb_notify_dca(struct notifier_block
*, unsigned long, void *);
178 static struct notifier_block dca_notifier
= {
179 .notifier_call
= igb_notify_dca
,
184 #ifdef CONFIG_NET_POLL_CONTROLLER
185 /* for netdump / net console */
186 static void igb_netpoll(struct net_device
*);
188 #ifdef CONFIG_PCI_IOV
189 static unsigned int max_vfs
= 0;
190 module_param(max_vfs
, uint
, 0);
191 MODULE_PARM_DESC(max_vfs
, "Maximum number of virtual functions to allocate "
192 "per physical function");
193 #endif /* CONFIG_PCI_IOV */
195 static pci_ers_result_t
igb_io_error_detected(struct pci_dev
*,
196 pci_channel_state_t
);
197 static pci_ers_result_t
igb_io_slot_reset(struct pci_dev
*);
198 static void igb_io_resume(struct pci_dev
*);
200 static struct pci_error_handlers igb_err_handler
= {
201 .error_detected
= igb_io_error_detected
,
202 .slot_reset
= igb_io_slot_reset
,
203 .resume
= igb_io_resume
,
207 static struct pci_driver igb_driver
= {
208 .name
= igb_driver_name
,
209 .id_table
= igb_pci_tbl
,
211 .remove
= __devexit_p(igb_remove
),
213 /* Power Managment Hooks */
214 .suspend
= igb_suspend
,
215 .resume
= igb_resume
,
217 .shutdown
= igb_shutdown
,
218 .err_handler
= &igb_err_handler
221 static int global_quad_port_a
; /* global quad port a indication */
223 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
224 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
225 MODULE_LICENSE("GPL");
226 MODULE_VERSION(DRV_VERSION
);
229 * Scale the NIC clock cycle by a large factor so that
230 * relatively small clock corrections can be added or
231 * substracted at each clock tick. The drawbacks of a
232 * large factor are a) that the clock register overflows
233 * more quickly (not such a big deal) and b) that the
234 * increment per tick has to fit into 24 bits.
237 * TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
239 * TIMINCA += TIMINCA * adjustment [ppm] / 1e9
241 * The base scale factor is intentionally a power of two
242 * so that the division in %struct timecounter can be done with
245 #define IGB_TSYNC_SHIFT (19)
246 #define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
249 * The duration of one clock cycle of the NIC.
251 * @todo This hard-coded value is part of the specification and might change
252 * in future hardware revisions. Add revision check.
254 #define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
256 #if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
257 # error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
261 * igb_read_clock - read raw cycle counter (to be used by time counter)
263 static cycle_t
igb_read_clock(const struct cyclecounter
*tc
)
265 struct igb_adapter
*adapter
=
266 container_of(tc
, struct igb_adapter
, cycles
);
267 struct e1000_hw
*hw
= &adapter
->hw
;
270 stamp
= rd32(E1000_SYSTIML
);
271 stamp
|= (u64
)rd32(E1000_SYSTIMH
) << 32ULL;
278 * igb_get_hw_dev_name - return device name string
279 * used by hardware layer to print debugging information
281 char *igb_get_hw_dev_name(struct e1000_hw
*hw
)
283 struct igb_adapter
*adapter
= hw
->back
;
284 return adapter
->netdev
->name
;
288 * igb_get_time_str - format current NIC and system time as string
290 static char *igb_get_time_str(struct igb_adapter
*adapter
,
293 cycle_t hw
= adapter
->cycles
.read(&adapter
->cycles
);
294 struct timespec nic
= ns_to_timespec(timecounter_read(&adapter
->clock
));
296 struct timespec delta
;
297 getnstimeofday(&sys
);
299 delta
= timespec_sub(nic
, sys
);
302 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
304 (long)nic
.tv_sec
, nic
.tv_nsec
,
305 (long)sys
.tv_sec
, sys
.tv_nsec
,
306 (long)delta
.tv_sec
, delta
.tv_nsec
);
313 * igb_desc_unused - calculate if we have unused descriptors
315 static int igb_desc_unused(struct igb_ring
*ring
)
317 if (ring
->next_to_clean
> ring
->next_to_use
)
318 return ring
->next_to_clean
- ring
->next_to_use
- 1;
320 return ring
->count
+ ring
->next_to_clean
- ring
->next_to_use
- 1;
324 * igb_init_module - Driver Registration Routine
326 * igb_init_module is the first routine called when the driver is
327 * loaded. All it does is register with the PCI subsystem.
329 static int __init
igb_init_module(void)
332 printk(KERN_INFO
"%s - version %s\n",
333 igb_driver_string
, igb_driver_version
);
335 printk(KERN_INFO
"%s\n", igb_copyright
);
337 global_quad_port_a
= 0;
339 #ifdef CONFIG_IGB_DCA
340 dca_register_notify(&dca_notifier
);
343 ret
= pci_register_driver(&igb_driver
);
347 module_init(igb_init_module
);
350 * igb_exit_module - Driver Exit Cleanup Routine
352 * igb_exit_module is called just before the driver is removed
355 static void __exit
igb_exit_module(void)
357 #ifdef CONFIG_IGB_DCA
358 dca_unregister_notify(&dca_notifier
);
360 pci_unregister_driver(&igb_driver
);
363 module_exit(igb_exit_module
);
365 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
367 * igb_cache_ring_register - Descriptor ring to register mapping
368 * @adapter: board private structure to initialize
370 * Once we know the feature-set enabled for the device, we'll cache
371 * the register offset the descriptor ring is assigned to.
373 static void igb_cache_ring_register(struct igb_adapter
*adapter
)
376 u32 rbase_offset
= adapter
->vfs_allocated_count
;
378 switch (adapter
->hw
.mac
.type
) {
380 /* The queues are allocated for virtualization such that VF 0
381 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
382 * In order to avoid collision we start at the first free queue
383 * and continue consuming queues in the same sequence
385 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
386 adapter
->rx_ring
[i
].reg_idx
= rbase_offset
+
388 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
389 adapter
->tx_ring
[i
].reg_idx
= rbase_offset
+
394 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
395 adapter
->rx_ring
[i
].reg_idx
= i
;
396 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
397 adapter
->tx_ring
[i
].reg_idx
= i
;
402 static void igb_free_queues(struct igb_adapter
*adapter
)
404 kfree(adapter
->tx_ring
);
405 kfree(adapter
->rx_ring
);
407 adapter
->tx_ring
= NULL
;
408 adapter
->rx_ring
= NULL
;
410 adapter
->num_rx_queues
= 0;
411 adapter
->num_tx_queues
= 0;
415 * igb_alloc_queues - Allocate memory for all rings
416 * @adapter: board private structure to initialize
418 * We allocate one ring per queue at run-time since we don't know the
419 * number of queues at compile-time.
421 static int igb_alloc_queues(struct igb_adapter
*adapter
)
425 adapter
->tx_ring
= kcalloc(adapter
->num_tx_queues
,
426 sizeof(struct igb_ring
), GFP_KERNEL
);
427 if (!adapter
->tx_ring
)
430 adapter
->rx_ring
= kcalloc(adapter
->num_rx_queues
,
431 sizeof(struct igb_ring
), GFP_KERNEL
);
432 if (!adapter
->rx_ring
)
435 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
436 struct igb_ring
*ring
= &(adapter
->tx_ring
[i
]);
437 ring
->count
= adapter
->tx_ring_count
;
438 ring
->queue_index
= i
;
439 ring
->pdev
= adapter
->pdev
;
440 /* For 82575, context index must be unique per ring. */
441 if (adapter
->hw
.mac
.type
== e1000_82575
)
442 ring
->flags
= IGB_RING_FLAG_TX_CTX_IDX
;
445 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
446 struct igb_ring
*ring
= &(adapter
->rx_ring
[i
]);
447 ring
->count
= adapter
->rx_ring_count
;
448 ring
->queue_index
= i
;
449 ring
->pdev
= adapter
->pdev
;
450 ring
->rx_buffer_len
= MAXIMUM_ETHERNET_VLAN_SIZE
;
451 ring
->flags
= IGB_RING_FLAG_RX_CSUM
; /* enable rx checksum */
452 /* set flag indicating ring supports SCTP checksum offload */
453 if (adapter
->hw
.mac
.type
>= e1000_82576
)
454 ring
->flags
|= IGB_RING_FLAG_RX_SCTP_CSUM
;
457 igb_cache_ring_register(adapter
);
462 igb_free_queues(adapter
);
467 #define IGB_N0_QUEUE -1
468 static void igb_assign_vector(struct igb_q_vector
*q_vector
, int msix_vector
)
471 struct igb_adapter
*adapter
= q_vector
->adapter
;
472 struct e1000_hw
*hw
= &adapter
->hw
;
474 int rx_queue
= IGB_N0_QUEUE
;
475 int tx_queue
= IGB_N0_QUEUE
;
477 if (q_vector
->rx_ring
)
478 rx_queue
= q_vector
->rx_ring
->reg_idx
;
479 if (q_vector
->tx_ring
)
480 tx_queue
= q_vector
->tx_ring
->reg_idx
;
482 switch (hw
->mac
.type
) {
484 /* The 82575 assigns vectors using a bitmask, which matches the
485 bitmask for the EICR/EIMS/EIMC registers. To assign one
486 or more queues to a vector, we write the appropriate bits
487 into the MSIXBM register for that vector. */
488 if (rx_queue
> IGB_N0_QUEUE
)
489 msixbm
= E1000_EICR_RX_QUEUE0
<< rx_queue
;
490 if (tx_queue
> IGB_N0_QUEUE
)
491 msixbm
|= E1000_EICR_TX_QUEUE0
<< tx_queue
;
492 array_wr32(E1000_MSIXBM(0), msix_vector
, msixbm
);
493 q_vector
->eims_value
= msixbm
;
496 /* 82576 uses a table-based method for assigning vectors.
497 Each queue has a single entry in the table to which we write
498 a vector number along with a "valid" bit. Sadly, the layout
499 of the table is somewhat counterintuitive. */
500 if (rx_queue
> IGB_N0_QUEUE
) {
501 index
= (rx_queue
& 0x7);
502 ivar
= array_rd32(E1000_IVAR0
, index
);
504 /* vector goes into low byte of register */
505 ivar
= ivar
& 0xFFFFFF00;
506 ivar
|= msix_vector
| E1000_IVAR_VALID
;
508 /* vector goes into third byte of register */
509 ivar
= ivar
& 0xFF00FFFF;
510 ivar
|= (msix_vector
| E1000_IVAR_VALID
) << 16;
512 array_wr32(E1000_IVAR0
, index
, ivar
);
514 if (tx_queue
> IGB_N0_QUEUE
) {
515 index
= (tx_queue
& 0x7);
516 ivar
= array_rd32(E1000_IVAR0
, index
);
518 /* vector goes into second byte of register */
519 ivar
= ivar
& 0xFFFF00FF;
520 ivar
|= (msix_vector
| E1000_IVAR_VALID
) << 8;
522 /* vector goes into high byte of register */
523 ivar
= ivar
& 0x00FFFFFF;
524 ivar
|= (msix_vector
| E1000_IVAR_VALID
) << 24;
526 array_wr32(E1000_IVAR0
, index
, ivar
);
528 q_vector
->eims_value
= 1 << msix_vector
;
537 * igb_configure_msix - Configure MSI-X hardware
539 * igb_configure_msix sets up the hardware to properly
540 * generate MSI-X interrupts.
542 static void igb_configure_msix(struct igb_adapter
*adapter
)
546 struct e1000_hw
*hw
= &adapter
->hw
;
548 adapter
->eims_enable_mask
= 0;
550 /* set vector for other causes, i.e. link changes */
551 switch (hw
->mac
.type
) {
553 tmp
= rd32(E1000_CTRL_EXT
);
554 /* enable MSI-X PBA support*/
555 tmp
|= E1000_CTRL_EXT_PBA_CLR
;
557 /* Auto-Mask interrupts upon ICR read. */
558 tmp
|= E1000_CTRL_EXT_EIAME
;
559 tmp
|= E1000_CTRL_EXT_IRCA
;
561 wr32(E1000_CTRL_EXT
, tmp
);
563 /* enable msix_other interrupt */
564 array_wr32(E1000_MSIXBM(0), vector
++,
566 adapter
->eims_other
= E1000_EIMS_OTHER
;
571 /* Turn on MSI-X capability first, or our settings
572 * won't stick. And it will take days to debug. */
573 wr32(E1000_GPIE
, E1000_GPIE_MSIX_MODE
|
574 E1000_GPIE_PBA
| E1000_GPIE_EIAME
|
577 /* enable msix_other interrupt */
578 adapter
->eims_other
= 1 << vector
;
579 tmp
= (vector
++ | E1000_IVAR_VALID
) << 8;
581 wr32(E1000_IVAR_MISC
, tmp
);
584 /* do nothing, since nothing else supports MSI-X */
586 } /* switch (hw->mac.type) */
588 adapter
->eims_enable_mask
|= adapter
->eims_other
;
590 for (i
= 0; i
< adapter
->num_q_vectors
; i
++) {
591 struct igb_q_vector
*q_vector
= adapter
->q_vector
[i
];
592 igb_assign_vector(q_vector
, vector
++);
593 adapter
->eims_enable_mask
|= q_vector
->eims_value
;
600 * igb_request_msix - Initialize MSI-X interrupts
602 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
605 static int igb_request_msix(struct igb_adapter
*adapter
)
607 struct net_device
*netdev
= adapter
->netdev
;
608 struct e1000_hw
*hw
= &adapter
->hw
;
609 int i
, err
= 0, vector
= 0;
611 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
612 &igb_msix_other
, 0, netdev
->name
, adapter
);
617 for (i
= 0; i
< adapter
->num_q_vectors
; i
++) {
618 struct igb_q_vector
*q_vector
= adapter
->q_vector
[i
];
620 q_vector
->itr_register
= hw
->hw_addr
+ E1000_EITR(vector
);
622 if (q_vector
->rx_ring
&& q_vector
->tx_ring
)
623 sprintf(q_vector
->name
, "%s-TxRx-%u", netdev
->name
,
624 q_vector
->rx_ring
->queue_index
);
625 else if (q_vector
->tx_ring
)
626 sprintf(q_vector
->name
, "%s-tx-%u", netdev
->name
,
627 q_vector
->tx_ring
->queue_index
);
628 else if (q_vector
->rx_ring
)
629 sprintf(q_vector
->name
, "%s-rx-%u", netdev
->name
,
630 q_vector
->rx_ring
->queue_index
);
632 sprintf(q_vector
->name
, "%s-unused", netdev
->name
);
634 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
635 &igb_msix_ring
, 0, q_vector
->name
,
642 igb_configure_msix(adapter
);
648 static void igb_reset_interrupt_capability(struct igb_adapter
*adapter
)
650 if (adapter
->msix_entries
) {
651 pci_disable_msix(adapter
->pdev
);
652 kfree(adapter
->msix_entries
);
653 adapter
->msix_entries
= NULL
;
654 } else if (adapter
->flags
& IGB_FLAG_HAS_MSI
) {
655 pci_disable_msi(adapter
->pdev
);
660 * igb_free_q_vectors - Free memory allocated for interrupt vectors
661 * @adapter: board private structure to initialize
663 * This function frees the memory allocated to the q_vectors. In addition if
664 * NAPI is enabled it will delete any references to the NAPI struct prior
665 * to freeing the q_vector.
667 static void igb_free_q_vectors(struct igb_adapter
*adapter
)
671 for (v_idx
= 0; v_idx
< adapter
->num_q_vectors
; v_idx
++) {
672 struct igb_q_vector
*q_vector
= adapter
->q_vector
[v_idx
];
673 adapter
->q_vector
[v_idx
] = NULL
;
674 netif_napi_del(&q_vector
->napi
);
677 adapter
->num_q_vectors
= 0;
681 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
683 * This function resets the device so that it has 0 rx queues, tx queues, and
684 * MSI-X interrupts allocated.
686 static void igb_clear_interrupt_scheme(struct igb_adapter
*adapter
)
688 igb_free_queues(adapter
);
689 igb_free_q_vectors(adapter
);
690 igb_reset_interrupt_capability(adapter
);
694 * igb_set_interrupt_capability - set MSI or MSI-X if supported
696 * Attempt to configure interrupts using the best available
697 * capabilities of the hardware and kernel.
699 static void igb_set_interrupt_capability(struct igb_adapter
*adapter
)
704 /* Number of supported queues. */
705 adapter
->num_rx_queues
= min_t(u32
, IGB_MAX_RX_QUEUES
, num_online_cpus());
706 adapter
->num_tx_queues
= min_t(u32
, IGB_MAX_TX_QUEUES
, num_online_cpus());
708 /* start with one vector for every rx queue */
709 numvecs
= adapter
->num_rx_queues
;
711 /* if tx handler is seperate add 1 for every tx queue */
712 numvecs
+= adapter
->num_tx_queues
;
714 /* store the number of vectors reserved for queues */
715 adapter
->num_q_vectors
= numvecs
;
717 /* add 1 vector for link status interrupts */
719 adapter
->msix_entries
= kcalloc(numvecs
, sizeof(struct msix_entry
),
721 if (!adapter
->msix_entries
)
724 for (i
= 0; i
< numvecs
; i
++)
725 adapter
->msix_entries
[i
].entry
= i
;
727 err
= pci_enable_msix(adapter
->pdev
,
728 adapter
->msix_entries
,
733 igb_reset_interrupt_capability(adapter
);
735 /* If we can't do MSI-X, try MSI */
737 #ifdef CONFIG_PCI_IOV
738 /* disable SR-IOV for non MSI-X configurations */
739 if (adapter
->vf_data
) {
740 struct e1000_hw
*hw
= &adapter
->hw
;
741 /* disable iov and allow time for transactions to clear */
742 pci_disable_sriov(adapter
->pdev
);
745 kfree(adapter
->vf_data
);
746 adapter
->vf_data
= NULL
;
747 wr32(E1000_IOVCTL
, E1000_IOVCTL_REUSE_VFQ
);
749 dev_info(&adapter
->pdev
->dev
, "IOV Disabled\n");
752 adapter
->num_rx_queues
= 1;
753 adapter
->num_tx_queues
= 1;
754 adapter
->num_q_vectors
= 1;
755 if (!pci_enable_msi(adapter
->pdev
))
756 adapter
->flags
|= IGB_FLAG_HAS_MSI
;
758 /* Notify the stack of the (possibly) reduced Tx Queue count. */
759 adapter
->netdev
->real_num_tx_queues
= adapter
->num_tx_queues
;
764 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
765 * @adapter: board private structure to initialize
767 * We allocate one q_vector per queue interrupt. If allocation fails we
770 static int igb_alloc_q_vectors(struct igb_adapter
*adapter
)
772 struct igb_q_vector
*q_vector
;
773 struct e1000_hw
*hw
= &adapter
->hw
;
776 for (v_idx
= 0; v_idx
< adapter
->num_q_vectors
; v_idx
++) {
777 q_vector
= kzalloc(sizeof(struct igb_q_vector
), GFP_KERNEL
);
780 q_vector
->adapter
= adapter
;
781 q_vector
->itr_shift
= (hw
->mac
.type
== e1000_82575
) ? 16 : 0;
782 q_vector
->itr_register
= hw
->hw_addr
+ E1000_EITR(0);
783 q_vector
->itr_val
= IGB_START_ITR
;
784 q_vector
->set_itr
= 1;
785 netif_napi_add(adapter
->netdev
, &q_vector
->napi
, igb_poll
, 64);
786 adapter
->q_vector
[v_idx
] = q_vector
;
793 q_vector
= adapter
->q_vector
[v_idx
];
794 netif_napi_del(&q_vector
->napi
);
796 adapter
->q_vector
[v_idx
] = NULL
;
801 static void igb_map_rx_ring_to_vector(struct igb_adapter
*adapter
,
802 int ring_idx
, int v_idx
)
804 struct igb_q_vector
*q_vector
;
806 q_vector
= adapter
->q_vector
[v_idx
];
807 q_vector
->rx_ring
= &adapter
->rx_ring
[ring_idx
];
808 q_vector
->rx_ring
->q_vector
= q_vector
;
809 q_vector
->itr_val
= adapter
->itr
;
812 static void igb_map_tx_ring_to_vector(struct igb_adapter
*adapter
,
813 int ring_idx
, int v_idx
)
815 struct igb_q_vector
*q_vector
;
817 q_vector
= adapter
->q_vector
[v_idx
];
818 q_vector
->tx_ring
= &adapter
->tx_ring
[ring_idx
];
819 q_vector
->tx_ring
->q_vector
= q_vector
;
820 q_vector
->itr_val
= adapter
->itr
;
824 * igb_map_ring_to_vector - maps allocated queues to vectors
826 * This function maps the recently allocated queues to vectors.
828 static int igb_map_ring_to_vector(struct igb_adapter
*adapter
)
833 if ((adapter
->num_q_vectors
< adapter
->num_rx_queues
) ||
834 (adapter
->num_q_vectors
< adapter
->num_tx_queues
))
837 if (adapter
->num_q_vectors
>=
838 (adapter
->num_rx_queues
+ adapter
->num_tx_queues
)) {
839 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
840 igb_map_rx_ring_to_vector(adapter
, i
, v_idx
++);
841 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
842 igb_map_tx_ring_to_vector(adapter
, i
, v_idx
++);
844 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
845 if (i
< adapter
->num_tx_queues
)
846 igb_map_tx_ring_to_vector(adapter
, i
, v_idx
);
847 igb_map_rx_ring_to_vector(adapter
, i
, v_idx
++);
849 for (; i
< adapter
->num_tx_queues
; i
++)
850 igb_map_tx_ring_to_vector(adapter
, i
, v_idx
++);
856 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
858 * This function initializes the interrupts and allocates all of the queues.
860 static int igb_init_interrupt_scheme(struct igb_adapter
*adapter
)
862 struct pci_dev
*pdev
= adapter
->pdev
;
865 igb_set_interrupt_capability(adapter
);
867 err
= igb_alloc_q_vectors(adapter
);
869 dev_err(&pdev
->dev
, "Unable to allocate memory for vectors\n");
870 goto err_alloc_q_vectors
;
873 err
= igb_alloc_queues(adapter
);
875 dev_err(&pdev
->dev
, "Unable to allocate memory for queues\n");
876 goto err_alloc_queues
;
879 err
= igb_map_ring_to_vector(adapter
);
881 dev_err(&pdev
->dev
, "Invalid q_vector to ring mapping\n");
888 igb_free_queues(adapter
);
890 igb_free_q_vectors(adapter
);
892 igb_reset_interrupt_capability(adapter
);
897 * igb_request_irq - initialize interrupts
899 * Attempts to configure interrupts using the best available
900 * capabilities of the hardware and kernel.
902 static int igb_request_irq(struct igb_adapter
*adapter
)
904 struct net_device
*netdev
= adapter
->netdev
;
905 struct pci_dev
*pdev
= adapter
->pdev
;
906 struct e1000_hw
*hw
= &adapter
->hw
;
909 if (adapter
->msix_entries
) {
910 err
= igb_request_msix(adapter
);
913 /* fall back to MSI */
914 igb_clear_interrupt_scheme(adapter
);
915 if (!pci_enable_msi(adapter
->pdev
))
916 adapter
->flags
|= IGB_FLAG_HAS_MSI
;
917 igb_free_all_tx_resources(adapter
);
918 igb_free_all_rx_resources(adapter
);
919 adapter
->num_tx_queues
= 1;
920 adapter
->num_rx_queues
= 1;
921 adapter
->num_q_vectors
= 1;
922 err
= igb_alloc_q_vectors(adapter
);
925 "Unable to allocate memory for vectors\n");
928 err
= igb_alloc_queues(adapter
);
931 "Unable to allocate memory for queues\n");
932 igb_free_q_vectors(adapter
);
935 igb_setup_all_tx_resources(adapter
);
936 igb_setup_all_rx_resources(adapter
);
938 switch (hw
->mac
.type
) {
940 wr32(E1000_MSIXBM(0),
941 (E1000_EICR_RX_QUEUE0
|
942 E1000_EICR_TX_QUEUE0
|
946 wr32(E1000_IVAR0
, E1000_IVAR_VALID
);
953 if (adapter
->flags
& IGB_FLAG_HAS_MSI
) {
954 err
= request_irq(adapter
->pdev
->irq
, &igb_intr_msi
, 0,
955 netdev
->name
, adapter
);
959 /* fall back to legacy interrupts */
960 igb_reset_interrupt_capability(adapter
);
961 adapter
->flags
&= ~IGB_FLAG_HAS_MSI
;
964 err
= request_irq(adapter
->pdev
->irq
, &igb_intr
, IRQF_SHARED
,
965 netdev
->name
, adapter
);
968 dev_err(&adapter
->pdev
->dev
, "Error %d getting interrupt\n",
975 static void igb_free_irq(struct igb_adapter
*adapter
)
977 if (adapter
->msix_entries
) {
980 free_irq(adapter
->msix_entries
[vector
++].vector
, adapter
);
982 for (i
= 0; i
< adapter
->num_q_vectors
; i
++) {
983 struct igb_q_vector
*q_vector
= adapter
->q_vector
[i
];
984 free_irq(adapter
->msix_entries
[vector
++].vector
,
988 free_irq(adapter
->pdev
->irq
, adapter
);
993 * igb_irq_disable - Mask off interrupt generation on the NIC
994 * @adapter: board private structure
996 static void igb_irq_disable(struct igb_adapter
*adapter
)
998 struct e1000_hw
*hw
= &adapter
->hw
;
1000 if (adapter
->msix_entries
) {
1001 u32 regval
= rd32(E1000_EIAM
);
1002 wr32(E1000_EIAM
, regval
& ~adapter
->eims_enable_mask
);
1003 wr32(E1000_EIMC
, adapter
->eims_enable_mask
);
1004 regval
= rd32(E1000_EIAC
);
1005 wr32(E1000_EIAC
, regval
& ~adapter
->eims_enable_mask
);
1009 wr32(E1000_IMC
, ~0);
1011 synchronize_irq(adapter
->pdev
->irq
);
1015 * igb_irq_enable - Enable default interrupt generation settings
1016 * @adapter: board private structure
1018 static void igb_irq_enable(struct igb_adapter
*adapter
)
1020 struct e1000_hw
*hw
= &adapter
->hw
;
1022 if (adapter
->msix_entries
) {
1023 u32 regval
= rd32(E1000_EIAC
);
1024 wr32(E1000_EIAC
, regval
| adapter
->eims_enable_mask
);
1025 regval
= rd32(E1000_EIAM
);
1026 wr32(E1000_EIAM
, regval
| adapter
->eims_enable_mask
);
1027 wr32(E1000_EIMS
, adapter
->eims_enable_mask
);
1028 if (adapter
->vfs_allocated_count
)
1029 wr32(E1000_MBVFIMR
, 0xFF);
1030 wr32(E1000_IMS
, (E1000_IMS_LSC
| E1000_IMS_VMMB
|
1031 E1000_IMS_DOUTSYNC
));
1033 wr32(E1000_IMS
, IMS_ENABLE_MASK
);
1034 wr32(E1000_IAM
, IMS_ENABLE_MASK
);
1038 static void igb_update_mng_vlan(struct igb_adapter
*adapter
)
1040 struct net_device
*netdev
= adapter
->netdev
;
1041 u16 vid
= adapter
->hw
.mng_cookie
.vlan_id
;
1042 u16 old_vid
= adapter
->mng_vlan_id
;
1043 if (adapter
->vlgrp
) {
1044 if (!vlan_group_get_device(adapter
->vlgrp
, vid
)) {
1045 if (adapter
->hw
.mng_cookie
.status
&
1046 E1000_MNG_DHCP_COOKIE_STATUS_VLAN
) {
1047 igb_vlan_rx_add_vid(netdev
, vid
);
1048 adapter
->mng_vlan_id
= vid
;
1050 adapter
->mng_vlan_id
= IGB_MNG_VLAN_NONE
;
1052 if ((old_vid
!= (u16
)IGB_MNG_VLAN_NONE
) &&
1054 !vlan_group_get_device(adapter
->vlgrp
, old_vid
))
1055 igb_vlan_rx_kill_vid(netdev
, old_vid
);
1057 adapter
->mng_vlan_id
= vid
;
1062 * igb_release_hw_control - release control of the h/w to f/w
1063 * @adapter: address of board private structure
1065 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1066 * For ASF and Pass Through versions of f/w this means that the
1067 * driver is no longer loaded.
1070 static void igb_release_hw_control(struct igb_adapter
*adapter
)
1072 struct e1000_hw
*hw
= &adapter
->hw
;
1075 /* Let firmware take over control of h/w */
1076 ctrl_ext
= rd32(E1000_CTRL_EXT
);
1077 wr32(E1000_CTRL_EXT
,
1078 ctrl_ext
& ~E1000_CTRL_EXT_DRV_LOAD
);
1083 * igb_get_hw_control - get control of the h/w from f/w
1084 * @adapter: address of board private structure
1086 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1087 * For ASF and Pass Through versions of f/w this means that
1088 * the driver is loaded.
1091 static void igb_get_hw_control(struct igb_adapter
*adapter
)
1093 struct e1000_hw
*hw
= &adapter
->hw
;
1096 /* Let firmware know the driver has taken over */
1097 ctrl_ext
= rd32(E1000_CTRL_EXT
);
1098 wr32(E1000_CTRL_EXT
,
1099 ctrl_ext
| E1000_CTRL_EXT_DRV_LOAD
);
1103 * igb_configure - configure the hardware for RX and TX
1104 * @adapter: private board structure
1106 static void igb_configure(struct igb_adapter
*adapter
)
1108 struct net_device
*netdev
= adapter
->netdev
;
1111 igb_get_hw_control(adapter
);
1112 igb_set_rx_mode(netdev
);
1114 igb_restore_vlan(adapter
);
1116 igb_setup_tctl(adapter
);
1117 igb_setup_rctl(adapter
);
1119 igb_configure_tx(adapter
);
1120 igb_configure_rx(adapter
);
1122 igb_rx_fifo_flush_82575(&adapter
->hw
);
1124 /* call igb_desc_unused which always leaves
1125 * at least 1 descriptor unused to make sure
1126 * next_to_use != next_to_clean */
1127 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
1128 struct igb_ring
*ring
= &adapter
->rx_ring
[i
];
1129 igb_alloc_rx_buffers_adv(ring
, igb_desc_unused(ring
));
1133 adapter
->tx_queue_len
= netdev
->tx_queue_len
;
1138 * igb_up - Open the interface and prepare it to handle traffic
1139 * @adapter: board private structure
1142 int igb_up(struct igb_adapter
*adapter
)
1144 struct e1000_hw
*hw
= &adapter
->hw
;
1147 /* hardware has been reset, we need to reload some things */
1148 igb_configure(adapter
);
1150 clear_bit(__IGB_DOWN
, &adapter
->state
);
1152 for (i
= 0; i
< adapter
->num_q_vectors
; i
++) {
1153 struct igb_q_vector
*q_vector
= adapter
->q_vector
[i
];
1154 napi_enable(&q_vector
->napi
);
1156 if (adapter
->msix_entries
)
1157 igb_configure_msix(adapter
);
1159 igb_vmm_control(adapter
);
1160 igb_set_vmolr(hw
, adapter
->vfs_allocated_count
);
1162 /* Clear any pending interrupts. */
1164 igb_irq_enable(adapter
);
1166 netif_tx_start_all_queues(adapter
->netdev
);
1168 /* Fire a link change interrupt to start the watchdog. */
1169 wr32(E1000_ICS
, E1000_ICS_LSC
);
1173 void igb_down(struct igb_adapter
*adapter
)
1175 struct e1000_hw
*hw
= &adapter
->hw
;
1176 struct net_device
*netdev
= adapter
->netdev
;
1180 /* signal that we're down so the interrupt handler does not
1181 * reschedule our watchdog timer */
1182 set_bit(__IGB_DOWN
, &adapter
->state
);
1184 /* disable receives in the hardware */
1185 rctl
= rd32(E1000_RCTL
);
1186 wr32(E1000_RCTL
, rctl
& ~E1000_RCTL_EN
);
1187 /* flush and sleep below */
1189 netif_tx_stop_all_queues(netdev
);
1191 /* disable transmits in the hardware */
1192 tctl
= rd32(E1000_TCTL
);
1193 tctl
&= ~E1000_TCTL_EN
;
1194 wr32(E1000_TCTL
, tctl
);
1195 /* flush both disables and wait for them to finish */
1199 for (i
= 0; i
< adapter
->num_q_vectors
; i
++) {
1200 struct igb_q_vector
*q_vector
= adapter
->q_vector
[i
];
1201 napi_disable(&q_vector
->napi
);
1204 igb_irq_disable(adapter
);
1206 del_timer_sync(&adapter
->watchdog_timer
);
1207 del_timer_sync(&adapter
->phy_info_timer
);
1209 netdev
->tx_queue_len
= adapter
->tx_queue_len
;
1210 netif_carrier_off(netdev
);
1212 /* record the stats before reset*/
1213 igb_update_stats(adapter
);
1215 adapter
->link_speed
= 0;
1216 adapter
->link_duplex
= 0;
1218 if (!pci_channel_offline(adapter
->pdev
))
1220 igb_clean_all_tx_rings(adapter
);
1221 igb_clean_all_rx_rings(adapter
);
1222 #ifdef CONFIG_IGB_DCA
1224 /* since we reset the hardware DCA settings were cleared */
1225 igb_setup_dca(adapter
);
1229 void igb_reinit_locked(struct igb_adapter
*adapter
)
1231 WARN_ON(in_interrupt());
1232 while (test_and_set_bit(__IGB_RESETTING
, &adapter
->state
))
1236 clear_bit(__IGB_RESETTING
, &adapter
->state
);
1239 void igb_reset(struct igb_adapter
*adapter
)
1241 struct e1000_hw
*hw
= &adapter
->hw
;
1242 struct e1000_mac_info
*mac
= &hw
->mac
;
1243 struct e1000_fc_info
*fc
= &hw
->fc
;
1244 u32 pba
= 0, tx_space
, min_tx_space
, min_rx_space
;
1247 /* Repartition Pba for greater than 9k mtu
1248 * To take effect CTRL.RST is required.
1250 switch (mac
->type
) {
1252 pba
= E1000_PBA_64K
;
1256 pba
= E1000_PBA_34K
;
1260 if ((adapter
->max_frame_size
> ETH_FRAME_LEN
+ ETH_FCS_LEN
) &&
1261 (mac
->type
< e1000_82576
)) {
1262 /* adjust PBA for jumbo frames */
1263 wr32(E1000_PBA
, pba
);
1265 /* To maintain wire speed transmits, the Tx FIFO should be
1266 * large enough to accommodate two full transmit packets,
1267 * rounded up to the next 1KB and expressed in KB. Likewise,
1268 * the Rx FIFO should be large enough to accommodate at least
1269 * one full receive packet and is similarly rounded up and
1270 * expressed in KB. */
1271 pba
= rd32(E1000_PBA
);
1272 /* upper 16 bits has Tx packet buffer allocation size in KB */
1273 tx_space
= pba
>> 16;
1274 /* lower 16 bits has Rx packet buffer allocation size in KB */
1276 /* the tx fifo also stores 16 bytes of information about the tx
1277 * but don't include ethernet FCS because hardware appends it */
1278 min_tx_space
= (adapter
->max_frame_size
+
1279 sizeof(union e1000_adv_tx_desc
) -
1281 min_tx_space
= ALIGN(min_tx_space
, 1024);
1282 min_tx_space
>>= 10;
1283 /* software strips receive CRC, so leave room for it */
1284 min_rx_space
= adapter
->max_frame_size
;
1285 min_rx_space
= ALIGN(min_rx_space
, 1024);
1286 min_rx_space
>>= 10;
1288 /* If current Tx allocation is less than the min Tx FIFO size,
1289 * and the min Tx FIFO size is less than the current Rx FIFO
1290 * allocation, take space away from current Rx allocation */
1291 if (tx_space
< min_tx_space
&&
1292 ((min_tx_space
- tx_space
) < pba
)) {
1293 pba
= pba
- (min_tx_space
- tx_space
);
1295 /* if short on rx space, rx wins and must trump tx
1297 if (pba
< min_rx_space
)
1300 wr32(E1000_PBA
, pba
);
1303 /* flow control settings */
1304 /* The high water mark must be low enough to fit one full frame
1305 * (or the size used for early receive) above it in the Rx FIFO.
1306 * Set it to the lower of:
1307 * - 90% of the Rx FIFO size, or
1308 * - the full Rx FIFO size minus one full frame */
1309 hwm
= min(((pba
<< 10) * 9 / 10),
1310 ((pba
<< 10) - 2 * adapter
->max_frame_size
));
1312 if (mac
->type
< e1000_82576
) {
1313 fc
->high_water
= hwm
& 0xFFF8; /* 8-byte granularity */
1314 fc
->low_water
= fc
->high_water
- 8;
1316 fc
->high_water
= hwm
& 0xFFF0; /* 16-byte granularity */
1317 fc
->low_water
= fc
->high_water
- 16;
1319 fc
->pause_time
= 0xFFFF;
1321 fc
->current_mode
= fc
->requested_mode
;
1323 /* disable receive for all VFs and wait one second */
1324 if (adapter
->vfs_allocated_count
) {
1326 for (i
= 0 ; i
< adapter
->vfs_allocated_count
; i
++)
1327 adapter
->vf_data
[i
].clear_to_send
= false;
1329 /* ping all the active vfs to let them know we are going down */
1330 igb_ping_all_vfs(adapter
);
1332 /* disable transmits and receives */
1333 wr32(E1000_VFRE
, 0);
1334 wr32(E1000_VFTE
, 0);
1337 /* Allow time for pending master requests to run */
1338 adapter
->hw
.mac
.ops
.reset_hw(&adapter
->hw
);
1341 if (adapter
->hw
.mac
.ops
.init_hw(&adapter
->hw
))
1342 dev_err(&adapter
->pdev
->dev
, "Hardware Error\n");
1344 igb_update_mng_vlan(adapter
);
1346 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1347 wr32(E1000_VET
, ETHERNET_IEEE_VLAN_TYPE
);
1349 igb_reset_adaptive(&adapter
->hw
);
1350 igb_get_phy_info(&adapter
->hw
);
1353 static const struct net_device_ops igb_netdev_ops
= {
1354 .ndo_open
= igb_open
,
1355 .ndo_stop
= igb_close
,
1356 .ndo_start_xmit
= igb_xmit_frame_adv
,
1357 .ndo_get_stats
= igb_get_stats
,
1358 .ndo_set_rx_mode
= igb_set_rx_mode
,
1359 .ndo_set_multicast_list
= igb_set_rx_mode
,
1360 .ndo_set_mac_address
= igb_set_mac
,
1361 .ndo_change_mtu
= igb_change_mtu
,
1362 .ndo_do_ioctl
= igb_ioctl
,
1363 .ndo_tx_timeout
= igb_tx_timeout
,
1364 .ndo_validate_addr
= eth_validate_addr
,
1365 .ndo_vlan_rx_register
= igb_vlan_rx_register
,
1366 .ndo_vlan_rx_add_vid
= igb_vlan_rx_add_vid
,
1367 .ndo_vlan_rx_kill_vid
= igb_vlan_rx_kill_vid
,
1368 #ifdef CONFIG_NET_POLL_CONTROLLER
1369 .ndo_poll_controller
= igb_netpoll
,
1374 * igb_probe - Device Initialization Routine
1375 * @pdev: PCI device information struct
1376 * @ent: entry in igb_pci_tbl
1378 * Returns 0 on success, negative on failure
1380 * igb_probe initializes an adapter identified by a pci_dev structure.
1381 * The OS initialization, configuring of the adapter private structure,
1382 * and a hardware reset occur.
1384 static int __devinit
igb_probe(struct pci_dev
*pdev
,
1385 const struct pci_device_id
*ent
)
1387 struct net_device
*netdev
;
1388 struct igb_adapter
*adapter
;
1389 struct e1000_hw
*hw
;
1390 const struct e1000_info
*ei
= igb_info_tbl
[ent
->driver_data
];
1391 unsigned long mmio_start
, mmio_len
;
1392 int err
, pci_using_dac
;
1393 u16 eeprom_data
= 0;
1394 u16 eeprom_apme_mask
= IGB_EEPROM_APME
;
1397 err
= pci_enable_device_mem(pdev
);
1402 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64));
1404 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
1408 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
1410 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
1412 dev_err(&pdev
->dev
, "No usable DMA "
1413 "configuration, aborting\n");
1419 err
= pci_request_selected_regions(pdev
, pci_select_bars(pdev
,
1425 pci_enable_pcie_error_reporting(pdev
);
1427 pci_set_master(pdev
);
1428 pci_save_state(pdev
);
1431 netdev
= alloc_etherdev_mq(sizeof(struct igb_adapter
),
1432 IGB_ABS_MAX_TX_QUEUES
);
1434 goto err_alloc_etherdev
;
1436 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
1438 pci_set_drvdata(pdev
, netdev
);
1439 adapter
= netdev_priv(netdev
);
1440 adapter
->netdev
= netdev
;
1441 adapter
->pdev
= pdev
;
1444 adapter
->msg_enable
= NETIF_MSG_DRV
| NETIF_MSG_PROBE
;
1446 mmio_start
= pci_resource_start(pdev
, 0);
1447 mmio_len
= pci_resource_len(pdev
, 0);
1450 hw
->hw_addr
= ioremap(mmio_start
, mmio_len
);
1454 netdev
->netdev_ops
= &igb_netdev_ops
;
1455 igb_set_ethtool_ops(netdev
);
1456 netdev
->watchdog_timeo
= 5 * HZ
;
1458 strncpy(netdev
->name
, pci_name(pdev
), sizeof(netdev
->name
) - 1);
1460 netdev
->mem_start
= mmio_start
;
1461 netdev
->mem_end
= mmio_start
+ mmio_len
;
1463 /* PCI config space info */
1464 hw
->vendor_id
= pdev
->vendor
;
1465 hw
->device_id
= pdev
->device
;
1466 hw
->revision_id
= pdev
->revision
;
1467 hw
->subsystem_vendor_id
= pdev
->subsystem_vendor
;
1468 hw
->subsystem_device_id
= pdev
->subsystem_device
;
1470 /* setup the private structure */
1472 /* Copy the default MAC, PHY and NVM function pointers */
1473 memcpy(&hw
->mac
.ops
, ei
->mac_ops
, sizeof(hw
->mac
.ops
));
1474 memcpy(&hw
->phy
.ops
, ei
->phy_ops
, sizeof(hw
->phy
.ops
));
1475 memcpy(&hw
->nvm
.ops
, ei
->nvm_ops
, sizeof(hw
->nvm
.ops
));
1476 /* Initialize skew-specific constants */
1477 err
= ei
->get_invariants(hw
);
1481 #ifdef CONFIG_PCI_IOV
1482 /* since iov functionality isn't critical to base device function we
1483 * can accept failure. If it fails we don't allow iov to be enabled */
1484 if (hw
->mac
.type
== e1000_82576
) {
1485 /* 82576 supports a maximum of 7 VFs in addition to the PF */
1486 unsigned int num_vfs
= (max_vfs
> 7) ? 7 : max_vfs
;
1488 unsigned char mac_addr
[ETH_ALEN
];
1491 adapter
->vf_data
= kcalloc(num_vfs
,
1492 sizeof(struct vf_data_storage
),
1494 if (!adapter
->vf_data
) {
1496 "Could not allocate VF private data - "
1497 "IOV enable failed\n");
1499 err
= pci_enable_sriov(pdev
, num_vfs
);
1501 adapter
->vfs_allocated_count
= num_vfs
;
1502 dev_info(&pdev
->dev
,
1503 "%d vfs allocated\n",
1506 i
< adapter
->vfs_allocated_count
;
1508 random_ether_addr(mac_addr
);
1509 igb_set_vf_mac(adapter
, i
,
1513 kfree(adapter
->vf_data
);
1514 adapter
->vf_data
= NULL
;
1521 /* setup the private structure */
1522 err
= igb_sw_init(adapter
);
1526 igb_get_bus_info_pcie(hw
);
1528 hw
->phy
.autoneg_wait_to_complete
= false;
1529 hw
->mac
.adaptive_ifs
= true;
1531 /* Copper options */
1532 if (hw
->phy
.media_type
== e1000_media_type_copper
) {
1533 hw
->phy
.mdix
= AUTO_ALL_MODES
;
1534 hw
->phy
.disable_polarity_correction
= false;
1535 hw
->phy
.ms_type
= e1000_ms_hw_default
;
1538 if (igb_check_reset_block(hw
))
1539 dev_info(&pdev
->dev
,
1540 "PHY reset is blocked due to SOL/IDER session.\n");
1542 netdev
->features
= NETIF_F_SG
|
1544 NETIF_F_HW_VLAN_TX
|
1545 NETIF_F_HW_VLAN_RX
|
1546 NETIF_F_HW_VLAN_FILTER
;
1548 netdev
->features
|= NETIF_F_IPV6_CSUM
;
1549 netdev
->features
|= NETIF_F_TSO
;
1550 netdev
->features
|= NETIF_F_TSO6
;
1552 netdev
->features
|= NETIF_F_GRO
;
1554 netdev
->vlan_features
|= NETIF_F_TSO
;
1555 netdev
->vlan_features
|= NETIF_F_TSO6
;
1556 netdev
->vlan_features
|= NETIF_F_IP_CSUM
;
1557 netdev
->vlan_features
|= NETIF_F_IPV6_CSUM
;
1558 netdev
->vlan_features
|= NETIF_F_SG
;
1561 netdev
->features
|= NETIF_F_HIGHDMA
;
1563 if (adapter
->hw
.mac
.type
== e1000_82576
)
1564 netdev
->features
|= NETIF_F_SCTP_CSUM
;
1566 adapter
->en_mng_pt
= igb_enable_mng_pass_thru(&adapter
->hw
);
1568 /* before reading the NVM, reset the controller to put the device in a
1569 * known good starting state */
1570 hw
->mac
.ops
.reset_hw(hw
);
1572 /* make sure the NVM is good */
1573 if (igb_validate_nvm_checksum(hw
) < 0) {
1574 dev_err(&pdev
->dev
, "The NVM Checksum Is Not Valid\n");
1579 /* copy the MAC address out of the NVM */
1580 if (hw
->mac
.ops
.read_mac_addr(hw
))
1581 dev_err(&pdev
->dev
, "NVM Read Error\n");
1583 memcpy(netdev
->dev_addr
, hw
->mac
.addr
, netdev
->addr_len
);
1584 memcpy(netdev
->perm_addr
, hw
->mac
.addr
, netdev
->addr_len
);
1586 if (!is_valid_ether_addr(netdev
->perm_addr
)) {
1587 dev_err(&pdev
->dev
, "Invalid MAC Address\n");
1592 setup_timer(&adapter
->watchdog_timer
, &igb_watchdog
,
1593 (unsigned long) adapter
);
1594 setup_timer(&adapter
->phy_info_timer
, &igb_update_phy_info
,
1595 (unsigned long) adapter
);
1597 INIT_WORK(&adapter
->reset_task
, igb_reset_task
);
1598 INIT_WORK(&adapter
->watchdog_task
, igb_watchdog_task
);
1600 /* Initialize link properties that are user-changeable */
1601 adapter
->fc_autoneg
= true;
1602 hw
->mac
.autoneg
= true;
1603 hw
->phy
.autoneg_advertised
= 0x2f;
1605 hw
->fc
.requested_mode
= e1000_fc_default
;
1606 hw
->fc
.current_mode
= e1000_fc_default
;
1608 adapter
->itr_setting
= IGB_DEFAULT_ITR
;
1609 adapter
->itr
= IGB_START_ITR
;
1611 igb_validate_mdi_setting(hw
);
1613 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1614 * enable the ACPI Magic Packet filter
1617 if (hw
->bus
.func
== 0)
1618 hw
->nvm
.ops
.read(hw
, NVM_INIT_CONTROL3_PORT_A
, 1, &eeprom_data
);
1619 else if (hw
->bus
.func
== 1)
1620 hw
->nvm
.ops
.read(hw
, NVM_INIT_CONTROL3_PORT_B
, 1, &eeprom_data
);
1622 if (eeprom_data
& eeprom_apme_mask
)
1623 adapter
->eeprom_wol
|= E1000_WUFC_MAG
;
1625 /* now that we have the eeprom settings, apply the special cases where
1626 * the eeprom may be wrong or the board simply won't support wake on
1627 * lan on a particular port */
1628 switch (pdev
->device
) {
1629 case E1000_DEV_ID_82575GB_QUAD_COPPER
:
1630 adapter
->eeprom_wol
= 0;
1632 case E1000_DEV_ID_82575EB_FIBER_SERDES
:
1633 case E1000_DEV_ID_82576_FIBER
:
1634 case E1000_DEV_ID_82576_SERDES
:
1635 /* Wake events only supported on port A for dual fiber
1636 * regardless of eeprom setting */
1637 if (rd32(E1000_STATUS
) & E1000_STATUS_FUNC_1
)
1638 adapter
->eeprom_wol
= 0;
1640 case E1000_DEV_ID_82576_QUAD_COPPER
:
1641 /* if quad port adapter, disable WoL on all but port A */
1642 if (global_quad_port_a
!= 0)
1643 adapter
->eeprom_wol
= 0;
1645 adapter
->flags
|= IGB_FLAG_QUAD_PORT_A
;
1646 /* Reset for multiple quad port adapters */
1647 if (++global_quad_port_a
== 4)
1648 global_quad_port_a
= 0;
1652 /* initialize the wol settings based on the eeprom settings */
1653 adapter
->wol
= adapter
->eeprom_wol
;
1654 device_set_wakeup_enable(&adapter
->pdev
->dev
, adapter
->wol
);
1656 /* reset the hardware with the new settings */
1659 /* let the f/w know that the h/w is now under the control of the
1661 igb_get_hw_control(adapter
);
1663 strcpy(netdev
->name
, "eth%d");
1664 err
= register_netdev(netdev
);
1668 /* carrier off reporting is important to ethtool even BEFORE open */
1669 netif_carrier_off(netdev
);
1671 #ifdef CONFIG_IGB_DCA
1672 if (dca_add_requester(&pdev
->dev
) == 0) {
1673 adapter
->flags
|= IGB_FLAG_DCA_ENABLED
;
1674 dev_info(&pdev
->dev
, "DCA enabled\n");
1675 igb_setup_dca(adapter
);
1680 * Initialize hardware timer: we keep it running just in case
1681 * that some program needs it later on.
1683 memset(&adapter
->cycles
, 0, sizeof(adapter
->cycles
));
1684 adapter
->cycles
.read
= igb_read_clock
;
1685 adapter
->cycles
.mask
= CLOCKSOURCE_MASK(64);
1686 adapter
->cycles
.mult
= 1;
1687 adapter
->cycles
.shift
= IGB_TSYNC_SHIFT
;
1690 IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS
* IGB_TSYNC_SCALE
);
1693 * Avoid rollover while we initialize by resetting the time counter.
1695 wr32(E1000_SYSTIML
, 0x00000000);
1696 wr32(E1000_SYSTIMH
, 0x00000000);
1699 * Set registers so that rollover occurs soon to test this.
1701 wr32(E1000_SYSTIML
, 0x00000000);
1702 wr32(E1000_SYSTIMH
, 0xFF800000);
1705 timecounter_init(&adapter
->clock
,
1707 ktime_to_ns(ktime_get_real()));
1710 * Synchronize our NIC clock against system wall clock. NIC
1711 * time stamp reading requires ~3us per sample, each sample
1712 * was pretty stable even under load => only require 10
1713 * samples for each offset comparison.
1715 memset(&adapter
->compare
, 0, sizeof(adapter
->compare
));
1716 adapter
->compare
.source
= &adapter
->clock
;
1717 adapter
->compare
.target
= ktime_get_real
;
1718 adapter
->compare
.num_samples
= 10;
1719 timecompare_update(&adapter
->compare
, 0);
1725 "igb: %s: hw %p initialized timer\n",
1726 igb_get_time_str(adapter
, buffer
),
1731 dev_info(&pdev
->dev
, "Intel(R) Gigabit Ethernet Network Connection\n");
1732 /* print bus type/speed/width info */
1733 dev_info(&pdev
->dev
, "%s: (PCIe:%s:%s) %pM\n",
1735 ((hw
->bus
.speed
== e1000_bus_speed_2500
)
1736 ? "2.5Gb/s" : "unknown"),
1737 ((hw
->bus
.width
== e1000_bus_width_pcie_x4
) ? "Width x4" :
1738 (hw
->bus
.width
== e1000_bus_width_pcie_x2
) ? "Width x2" :
1739 (hw
->bus
.width
== e1000_bus_width_pcie_x1
) ? "Width x1" :
1743 igb_read_part_num(hw
, &part_num
);
1744 dev_info(&pdev
->dev
, "%s: PBA No: %06x-%03x\n", netdev
->name
,
1745 (part_num
>> 8), (part_num
& 0xff));
1747 dev_info(&pdev
->dev
,
1748 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1749 adapter
->msix_entries
? "MSI-X" :
1750 (adapter
->flags
& IGB_FLAG_HAS_MSI
) ? "MSI" : "legacy",
1751 adapter
->num_rx_queues
, adapter
->num_tx_queues
);
1756 igb_release_hw_control(adapter
);
1758 if (!igb_check_reset_block(hw
))
1761 if (hw
->flash_address
)
1762 iounmap(hw
->flash_address
);
1764 igb_clear_interrupt_scheme(adapter
);
1765 iounmap(hw
->hw_addr
);
1767 free_netdev(netdev
);
1769 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
1773 pci_disable_device(pdev
);
1778 * igb_remove - Device Removal Routine
1779 * @pdev: PCI device information struct
1781 * igb_remove is called by the PCI subsystem to alert the driver
1782 * that it should release a PCI device. The could be caused by a
1783 * Hot-Plug event, or because the driver is going to be removed from
1786 static void __devexit
igb_remove(struct pci_dev
*pdev
)
1788 struct net_device
*netdev
= pci_get_drvdata(pdev
);
1789 struct igb_adapter
*adapter
= netdev_priv(netdev
);
1790 struct e1000_hw
*hw
= &adapter
->hw
;
1792 /* flush_scheduled work may reschedule our watchdog task, so
1793 * explicitly disable watchdog tasks from being rescheduled */
1794 set_bit(__IGB_DOWN
, &adapter
->state
);
1795 del_timer_sync(&adapter
->watchdog_timer
);
1796 del_timer_sync(&adapter
->phy_info_timer
);
1798 flush_scheduled_work();
1800 #ifdef CONFIG_IGB_DCA
1801 if (adapter
->flags
& IGB_FLAG_DCA_ENABLED
) {
1802 dev_info(&pdev
->dev
, "DCA disabled\n");
1803 dca_remove_requester(&pdev
->dev
);
1804 adapter
->flags
&= ~IGB_FLAG_DCA_ENABLED
;
1805 wr32(E1000_DCA_CTRL
, E1000_DCA_CTRL_DCA_MODE_DISABLE
);
1809 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1810 * would have already happened in close and is redundant. */
1811 igb_release_hw_control(adapter
);
1813 unregister_netdev(netdev
);
1815 if (!igb_check_reset_block(&adapter
->hw
))
1816 igb_reset_phy(&adapter
->hw
);
1818 igb_clear_interrupt_scheme(adapter
);
1820 #ifdef CONFIG_PCI_IOV
1821 /* reclaim resources allocated to VFs */
1822 if (adapter
->vf_data
) {
1823 /* disable iov and allow time for transactions to clear */
1824 pci_disable_sriov(pdev
);
1827 kfree(adapter
->vf_data
);
1828 adapter
->vf_data
= NULL
;
1829 wr32(E1000_IOVCTL
, E1000_IOVCTL_REUSE_VFQ
);
1831 dev_info(&pdev
->dev
, "IOV Disabled\n");
1834 iounmap(hw
->hw_addr
);
1835 if (hw
->flash_address
)
1836 iounmap(hw
->flash_address
);
1837 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
1840 free_netdev(netdev
);
1842 pci_disable_pcie_error_reporting(pdev
);
1844 pci_disable_device(pdev
);
1848 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1849 * @adapter: board private structure to initialize
1851 * igb_sw_init initializes the Adapter private data structure.
1852 * Fields are initialized based on PCI device information and
1853 * OS network device settings (MTU size).
1855 static int __devinit
igb_sw_init(struct igb_adapter
*adapter
)
1857 struct e1000_hw
*hw
= &adapter
->hw
;
1858 struct net_device
*netdev
= adapter
->netdev
;
1859 struct pci_dev
*pdev
= adapter
->pdev
;
1861 pci_read_config_word(pdev
, PCI_COMMAND
, &hw
->bus
.pci_cmd_word
);
1863 adapter
->tx_ring_count
= IGB_DEFAULT_TXD
;
1864 adapter
->rx_ring_count
= IGB_DEFAULT_RXD
;
1865 adapter
->max_frame_size
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
1866 adapter
->min_frame_size
= ETH_ZLEN
+ ETH_FCS_LEN
;
1868 /* This call may decrease the number of queues depending on
1869 * interrupt mode. */
1870 if (igb_init_interrupt_scheme(adapter
)) {
1871 dev_err(&pdev
->dev
, "Unable to allocate memory for queues\n");
1875 /* Explicitly disable IRQ since the NIC can be in any state. */
1876 igb_irq_disable(adapter
);
1878 set_bit(__IGB_DOWN
, &adapter
->state
);
1883 * igb_open - Called when a network interface is made active
1884 * @netdev: network interface device structure
1886 * Returns 0 on success, negative value on failure
1888 * The open entry point is called when a network interface is made
1889 * active by the system (IFF_UP). At this point all resources needed
1890 * for transmit and receive operations are allocated, the interrupt
1891 * handler is registered with the OS, the watchdog timer is started,
1892 * and the stack is notified that the interface is ready.
1894 static int igb_open(struct net_device
*netdev
)
1896 struct igb_adapter
*adapter
= netdev_priv(netdev
);
1897 struct e1000_hw
*hw
= &adapter
->hw
;
1901 /* disallow open during test */
1902 if (test_bit(__IGB_TESTING
, &adapter
->state
))
1905 netif_carrier_off(netdev
);
1907 /* allocate transmit descriptors */
1908 err
= igb_setup_all_tx_resources(adapter
);
1912 /* allocate receive descriptors */
1913 err
= igb_setup_all_rx_resources(adapter
);
1917 /* e1000_power_up_phy(adapter); */
1919 adapter
->mng_vlan_id
= IGB_MNG_VLAN_NONE
;
1920 if ((adapter
->hw
.mng_cookie
.status
&
1921 E1000_MNG_DHCP_COOKIE_STATUS_VLAN
))
1922 igb_update_mng_vlan(adapter
);
1924 /* before we allocate an interrupt, we must be ready to handle it.
1925 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1926 * as soon as we call pci_request_irq, so we have to setup our
1927 * clean_rx handler before we do so. */
1928 igb_configure(adapter
);
1930 igb_vmm_control(adapter
);
1931 igb_set_vmolr(hw
, adapter
->vfs_allocated_count
);
1933 err
= igb_request_irq(adapter
);
1937 /* From here on the code is the same as igb_up() */
1938 clear_bit(__IGB_DOWN
, &adapter
->state
);
1940 for (i
= 0; i
< adapter
->num_q_vectors
; i
++) {
1941 struct igb_q_vector
*q_vector
= adapter
->q_vector
[i
];
1942 napi_enable(&q_vector
->napi
);
1945 /* Clear any pending interrupts. */
1948 igb_irq_enable(adapter
);
1950 netif_tx_start_all_queues(netdev
);
1952 /* Fire a link status change interrupt to start the watchdog. */
1953 wr32(E1000_ICS
, E1000_ICS_LSC
);
1958 igb_release_hw_control(adapter
);
1959 /* e1000_power_down_phy(adapter); */
1960 igb_free_all_rx_resources(adapter
);
1962 igb_free_all_tx_resources(adapter
);
1970 * igb_close - Disables a network interface
1971 * @netdev: network interface device structure
1973 * Returns 0, this is not allowed to fail
1975 * The close entry point is called when an interface is de-activated
1976 * by the OS. The hardware is still under the driver's control, but
1977 * needs to be disabled. A global MAC reset is issued to stop the
1978 * hardware, and all transmit and receive resources are freed.
1980 static int igb_close(struct net_device
*netdev
)
1982 struct igb_adapter
*adapter
= netdev_priv(netdev
);
1984 WARN_ON(test_bit(__IGB_RESETTING
, &adapter
->state
));
1987 igb_free_irq(adapter
);
1989 igb_free_all_tx_resources(adapter
);
1990 igb_free_all_rx_resources(adapter
);
1992 /* kill manageability vlan ID if supported, but not if a vlan with
1993 * the same ID is registered on the host OS (let 8021q kill it) */
1994 if ((adapter
->hw
.mng_cookie
.status
&
1995 E1000_MNG_DHCP_COOKIE_STATUS_VLAN
) &&
1997 vlan_group_get_device(adapter
->vlgrp
, adapter
->mng_vlan_id
)))
1998 igb_vlan_rx_kill_vid(netdev
, adapter
->mng_vlan_id
);
2004 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
2005 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2007 * Return 0 on success, negative on failure
2009 int igb_setup_tx_resources(struct igb_ring
*tx_ring
)
2011 struct pci_dev
*pdev
= tx_ring
->pdev
;
2014 size
= sizeof(struct igb_buffer
) * tx_ring
->count
;
2015 tx_ring
->buffer_info
= vmalloc(size
);
2016 if (!tx_ring
->buffer_info
)
2018 memset(tx_ring
->buffer_info
, 0, size
);
2020 /* round up to nearest 4K */
2021 tx_ring
->size
= tx_ring
->count
* sizeof(union e1000_adv_tx_desc
);
2022 tx_ring
->size
= ALIGN(tx_ring
->size
, 4096);
2024 tx_ring
->desc
= pci_alloc_consistent(pdev
, tx_ring
->size
,
2030 tx_ring
->next_to_use
= 0;
2031 tx_ring
->next_to_clean
= 0;
2035 vfree(tx_ring
->buffer_info
);
2037 "Unable to allocate memory for the transmit descriptor ring\n");
2042 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2043 * (Descriptors) for all queues
2044 * @adapter: board private structure
2046 * Return 0 on success, negative on failure
2048 static int igb_setup_all_tx_resources(struct igb_adapter
*adapter
)
2053 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2054 err
= igb_setup_tx_resources(&adapter
->tx_ring
[i
]);
2056 dev_err(&adapter
->pdev
->dev
,
2057 "Allocation for Tx Queue %u failed\n", i
);
2058 for (i
--; i
>= 0; i
--)
2059 igb_free_tx_resources(&adapter
->tx_ring
[i
]);
2064 for (i
= 0; i
< IGB_MAX_TX_QUEUES
; i
++) {
2065 r_idx
= i
% adapter
->num_tx_queues
;
2066 adapter
->multi_tx_table
[i
] = &adapter
->tx_ring
[r_idx
];
2072 * igb_setup_tctl - configure the transmit control registers
2073 * @adapter: Board private structure
2075 static void igb_setup_tctl(struct igb_adapter
*adapter
)
2077 struct e1000_hw
*hw
= &adapter
->hw
;
2080 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2081 wr32(E1000_TXDCTL(0), 0);
2083 /* Program the Transmit Control Register */
2084 tctl
= rd32(E1000_TCTL
);
2085 tctl
&= ~E1000_TCTL_CT
;
2086 tctl
|= E1000_TCTL_PSP
| E1000_TCTL_RTLC
|
2087 (E1000_COLLISION_THRESHOLD
<< E1000_CT_SHIFT
);
2089 igb_config_collision_dist(hw
);
2091 /* Enable transmits */
2092 tctl
|= E1000_TCTL_EN
;
2094 wr32(E1000_TCTL
, tctl
);
2098 * igb_configure_tx_ring - Configure transmit ring after Reset
2099 * @adapter: board private structure
2100 * @ring: tx ring to configure
2102 * Configure a transmit ring after a reset.
2104 static void igb_configure_tx_ring(struct igb_adapter
*adapter
,
2105 struct igb_ring
*ring
)
2107 struct e1000_hw
*hw
= &adapter
->hw
;
2109 u64 tdba
= ring
->dma
;
2110 int reg_idx
= ring
->reg_idx
;
2112 /* disable the queue */
2113 txdctl
= rd32(E1000_TXDCTL(reg_idx
));
2114 wr32(E1000_TXDCTL(reg_idx
),
2115 txdctl
& ~E1000_TXDCTL_QUEUE_ENABLE
);
2119 wr32(E1000_TDLEN(reg_idx
),
2120 ring
->count
* sizeof(union e1000_adv_tx_desc
));
2121 wr32(E1000_TDBAL(reg_idx
),
2122 tdba
& 0x00000000ffffffffULL
);
2123 wr32(E1000_TDBAH(reg_idx
), tdba
>> 32);
2125 ring
->head
= hw
->hw_addr
+ E1000_TDH(reg_idx
);
2126 ring
->tail
= hw
->hw_addr
+ E1000_TDT(reg_idx
);
2127 writel(0, ring
->head
);
2128 writel(0, ring
->tail
);
2130 txdctl
|= IGB_TX_PTHRESH
;
2131 txdctl
|= IGB_TX_HTHRESH
<< 8;
2132 txdctl
|= IGB_TX_WTHRESH
<< 16;
2134 txdctl
|= E1000_TXDCTL_QUEUE_ENABLE
;
2135 wr32(E1000_TXDCTL(reg_idx
), txdctl
);
2139 * igb_configure_tx - Configure transmit Unit after Reset
2140 * @adapter: board private structure
2142 * Configure the Tx unit of the MAC after a reset.
2144 static void igb_configure_tx(struct igb_adapter
*adapter
)
2148 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
2149 igb_configure_tx_ring(adapter
, &adapter
->tx_ring
[i
]);
2153 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
2154 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2156 * Returns 0 on success, negative on failure
2158 int igb_setup_rx_resources(struct igb_ring
*rx_ring
)
2160 struct pci_dev
*pdev
= rx_ring
->pdev
;
2163 size
= sizeof(struct igb_buffer
) * rx_ring
->count
;
2164 rx_ring
->buffer_info
= vmalloc(size
);
2165 if (!rx_ring
->buffer_info
)
2167 memset(rx_ring
->buffer_info
, 0, size
);
2169 desc_len
= sizeof(union e1000_adv_rx_desc
);
2171 /* Round up to nearest 4K */
2172 rx_ring
->size
= rx_ring
->count
* desc_len
;
2173 rx_ring
->size
= ALIGN(rx_ring
->size
, 4096);
2175 rx_ring
->desc
= pci_alloc_consistent(pdev
, rx_ring
->size
,
2181 rx_ring
->next_to_clean
= 0;
2182 rx_ring
->next_to_use
= 0;
2187 vfree(rx_ring
->buffer_info
);
2188 dev_err(&pdev
->dev
, "Unable to allocate memory for "
2189 "the receive descriptor ring\n");
2194 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2195 * (Descriptors) for all queues
2196 * @adapter: board private structure
2198 * Return 0 on success, negative on failure
2200 static int igb_setup_all_rx_resources(struct igb_adapter
*adapter
)
2204 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2205 err
= igb_setup_rx_resources(&adapter
->rx_ring
[i
]);
2207 dev_err(&adapter
->pdev
->dev
,
2208 "Allocation for Rx Queue %u failed\n", i
);
2209 for (i
--; i
>= 0; i
--)
2210 igb_free_rx_resources(&adapter
->rx_ring
[i
]);
2219 * igb_setup_rctl - configure the receive control registers
2220 * @adapter: Board private structure
2222 static void igb_setup_rctl(struct igb_adapter
*adapter
)
2224 struct e1000_hw
*hw
= &adapter
->hw
;
2227 rctl
= rd32(E1000_RCTL
);
2229 rctl
&= ~(3 << E1000_RCTL_MO_SHIFT
);
2230 rctl
&= ~(E1000_RCTL_LBM_TCVR
| E1000_RCTL_LBM_MAC
);
2232 rctl
|= E1000_RCTL_EN
| E1000_RCTL_BAM
| E1000_RCTL_RDMTS_HALF
|
2233 (hw
->mac
.mc_filter_type
<< E1000_RCTL_MO_SHIFT
);
2236 * enable stripping of CRC. It's unlikely this will break BMC
2237 * redirection as it did with e1000. Newer features require
2238 * that the HW strips the CRC.
2240 rctl
|= E1000_RCTL_SECRC
;
2243 * disable store bad packets and clear size bits.
2245 rctl
&= ~(E1000_RCTL_SBP
| E1000_RCTL_SZ_256
);
2247 /* enable LPE to prevent packets larger than max_frame_size */
2248 rctl
|= E1000_RCTL_LPE
;
2250 /* disable queue 0 to prevent tail write w/o re-config */
2251 wr32(E1000_RXDCTL(0), 0);
2253 /* Attention!!! For SR-IOV PF driver operations you must enable
2254 * queue drop for all VF and PF queues to prevent head of line blocking
2255 * if an un-trusted VF does not provide descriptors to hardware.
2257 if (adapter
->vfs_allocated_count
) {
2260 /* set all queue drop enable bits */
2261 wr32(E1000_QDE
, ALL_QUEUES
);
2263 vmolr
= rd32(E1000_VMOLR(adapter
->vfs_allocated_count
));
2264 if (rctl
& E1000_RCTL_LPE
)
2265 vmolr
|= E1000_VMOLR_LPE
;
2266 if (adapter
->num_rx_queues
> 1)
2267 vmolr
|= E1000_VMOLR_RSSE
;
2268 wr32(E1000_VMOLR(adapter
->vfs_allocated_count
), vmolr
);
2271 wr32(E1000_RCTL
, rctl
);
2275 * igb_rlpml_set - set maximum receive packet size
2276 * @adapter: board private structure
2278 * Configure maximum receivable packet size.
2280 static void igb_rlpml_set(struct igb_adapter
*adapter
)
2282 u32 max_frame_size
= adapter
->max_frame_size
;
2283 struct e1000_hw
*hw
= &adapter
->hw
;
2284 u16 pf_id
= adapter
->vfs_allocated_count
;
2287 max_frame_size
+= VLAN_TAG_SIZE
;
2289 /* if vfs are enabled we set RLPML to the largest possible request
2290 * size and set the VMOLR RLPML to the size we need */
2292 igb_set_vf_rlpml(adapter
, max_frame_size
, pf_id
);
2293 max_frame_size
= MAX_STD_JUMBO_FRAME_SIZE
+ VLAN_TAG_SIZE
;
2296 wr32(E1000_RLPML
, max_frame_size
);
2300 * igb_configure_vt_default_pool - Configure VT default pool
2301 * @adapter: board private structure
2303 * Configure the default pool
2305 static void igb_configure_vt_default_pool(struct igb_adapter
*adapter
)
2307 struct e1000_hw
*hw
= &adapter
->hw
;
2308 u16 pf_id
= adapter
->vfs_allocated_count
;
2311 /* not in sr-iov mode - do nothing */
2315 vtctl
= rd32(E1000_VT_CTL
);
2316 vtctl
&= ~(E1000_VT_CTL_DEFAULT_POOL_MASK
|
2317 E1000_VT_CTL_DISABLE_DEF_POOL
);
2318 vtctl
|= pf_id
<< E1000_VT_CTL_DEFAULT_POOL_SHIFT
;
2319 wr32(E1000_VT_CTL
, vtctl
);
2323 * igb_configure_rx_ring - Configure a receive ring after Reset
2324 * @adapter: board private structure
2325 * @ring: receive ring to be configured
2327 * Configure the Rx unit of the MAC after a reset.
2329 static void igb_configure_rx_ring(struct igb_adapter
*adapter
,
2330 struct igb_ring
*ring
)
2332 struct e1000_hw
*hw
= &adapter
->hw
;
2333 u64 rdba
= ring
->dma
;
2334 int reg_idx
= ring
->reg_idx
;
2337 /* disable the queue */
2338 rxdctl
= rd32(E1000_RXDCTL(reg_idx
));
2339 wr32(E1000_RXDCTL(reg_idx
),
2340 rxdctl
& ~E1000_RXDCTL_QUEUE_ENABLE
);
2342 /* Set DMA base address registers */
2343 wr32(E1000_RDBAL(reg_idx
),
2344 rdba
& 0x00000000ffffffffULL
);
2345 wr32(E1000_RDBAH(reg_idx
), rdba
>> 32);
2346 wr32(E1000_RDLEN(reg_idx
),
2347 ring
->count
* sizeof(union e1000_adv_rx_desc
));
2349 /* initialize head and tail */
2350 ring
->head
= hw
->hw_addr
+ E1000_RDH(reg_idx
);
2351 ring
->tail
= hw
->hw_addr
+ E1000_RDT(reg_idx
);
2352 writel(0, ring
->head
);
2353 writel(0, ring
->tail
);
2355 /* set descriptor configuration */
2356 if (ring
->rx_buffer_len
< IGB_RXBUFFER_1024
) {
2357 srrctl
= ALIGN(ring
->rx_buffer_len
, 64) <<
2358 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT
;
2359 #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
2360 srrctl
|= IGB_RXBUFFER_16384
>>
2361 E1000_SRRCTL_BSIZEPKT_SHIFT
;
2363 srrctl
|= (PAGE_SIZE
/ 2) >>
2364 E1000_SRRCTL_BSIZEPKT_SHIFT
;
2366 srrctl
|= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS
;
2368 srrctl
= ALIGN(ring
->rx_buffer_len
, 1024) >>
2369 E1000_SRRCTL_BSIZEPKT_SHIFT
;
2370 srrctl
|= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF
;
2373 wr32(E1000_SRRCTL(reg_idx
), srrctl
);
2375 /* enable receive descriptor fetching */
2376 rxdctl
= rd32(E1000_RXDCTL(reg_idx
));
2377 rxdctl
|= E1000_RXDCTL_QUEUE_ENABLE
;
2378 rxdctl
&= 0xFFF00000;
2379 rxdctl
|= IGB_RX_PTHRESH
;
2380 rxdctl
|= IGB_RX_HTHRESH
<< 8;
2381 rxdctl
|= IGB_RX_WTHRESH
<< 16;
2382 wr32(E1000_RXDCTL(reg_idx
), rxdctl
);
2386 * igb_configure_rx - Configure receive Unit after Reset
2387 * @adapter: board private structure
2389 * Configure the Rx unit of the MAC after a reset.
2391 static void igb_configure_rx(struct igb_adapter
*adapter
)
2393 struct e1000_hw
*hw
= &adapter
->hw
;
2397 /* disable receives while setting up the descriptors */
2398 rctl
= rd32(E1000_RCTL
);
2399 wr32(E1000_RCTL
, rctl
& ~E1000_RCTL_EN
);
2403 if (adapter
->itr_setting
> 3)
2404 wr32(E1000_ITR
, adapter
->itr
);
2406 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2407 * the Base and Length of the Rx Descriptor Ring */
2408 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
2409 igb_configure_rx_ring(adapter
, &adapter
->rx_ring
[i
]);
2411 if (adapter
->num_rx_queues
> 1) {
2420 get_random_bytes(&random
[0], 40);
2422 if (hw
->mac
.type
>= e1000_82576
)
2426 for (j
= 0; j
< (32 * 4); j
++) {
2428 adapter
->rx_ring
[(j
% adapter
->num_rx_queues
)].reg_idx
<< shift
;
2431 hw
->hw_addr
+ E1000_RETA(0) + (j
& ~3));
2433 if (adapter
->vfs_allocated_count
)
2434 mrqc
= E1000_MRQC_ENABLE_VMDQ_RSS_2Q
;
2436 mrqc
= E1000_MRQC_ENABLE_RSS_4Q
;
2438 /* Fill out hash function seeds */
2439 for (j
= 0; j
< 10; j
++)
2440 array_wr32(E1000_RSSRK(0), j
, random
[j
]);
2442 mrqc
|= (E1000_MRQC_RSS_FIELD_IPV4
|
2443 E1000_MRQC_RSS_FIELD_IPV4_TCP
);
2444 mrqc
|= (E1000_MRQC_RSS_FIELD_IPV6
|
2445 E1000_MRQC_RSS_FIELD_IPV6_TCP
);
2446 mrqc
|= (E1000_MRQC_RSS_FIELD_IPV4_UDP
|
2447 E1000_MRQC_RSS_FIELD_IPV6_UDP
);
2448 mrqc
|= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX
|
2449 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX
);
2451 wr32(E1000_MRQC
, mrqc
);
2452 } else if (adapter
->vfs_allocated_count
) {
2453 /* Enable multi-queue for sr-iov */
2454 wr32(E1000_MRQC
, E1000_MRQC_ENABLE_VMDQ
);
2457 /* Enable Receive Checksum Offload for TCP and UDP */
2458 rxcsum
= rd32(E1000_RXCSUM
);
2459 /* Disable raw packet checksumming */
2460 rxcsum
|= E1000_RXCSUM_PCSD
;
2462 if (adapter
->hw
.mac
.type
== e1000_82576
)
2463 /* Enable Receive Checksum Offload for SCTP */
2464 rxcsum
|= E1000_RXCSUM_CRCOFL
;
2466 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2467 wr32(E1000_RXCSUM
, rxcsum
);
2469 /* Set the default pool for the PF's first queue */
2470 igb_configure_vt_default_pool(adapter
);
2472 /* set UTA to appropriate mode */
2473 igb_set_uta(adapter
);
2475 /* set the correct pool for the PF default MAC address in entry 0 */
2476 igb_rar_set_qsel(adapter
, adapter
->hw
.mac
.addr
, 0,
2477 adapter
->vfs_allocated_count
);
2479 igb_rlpml_set(adapter
);
2481 /* Enable Receives */
2482 wr32(E1000_RCTL
, rctl
);
2486 * igb_free_tx_resources - Free Tx Resources per Queue
2487 * @tx_ring: Tx descriptor ring for a specific queue
2489 * Free all transmit software resources
2491 void igb_free_tx_resources(struct igb_ring
*tx_ring
)
2493 igb_clean_tx_ring(tx_ring
);
2495 vfree(tx_ring
->buffer_info
);
2496 tx_ring
->buffer_info
= NULL
;
2498 pci_free_consistent(tx_ring
->pdev
, tx_ring
->size
,
2499 tx_ring
->desc
, tx_ring
->dma
);
2501 tx_ring
->desc
= NULL
;
2505 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2506 * @adapter: board private structure
2508 * Free all transmit software resources
2510 static void igb_free_all_tx_resources(struct igb_adapter
*adapter
)
2514 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
2515 igb_free_tx_resources(&adapter
->tx_ring
[i
]);
2518 static void igb_unmap_and_free_tx_resource(struct igb_ring
*tx_ring
,
2519 struct igb_buffer
*buffer_info
)
2521 buffer_info
->dma
= 0;
2522 if (buffer_info
->skb
) {
2523 skb_dma_unmap(&tx_ring
->pdev
->dev
,
2526 dev_kfree_skb_any(buffer_info
->skb
);
2527 buffer_info
->skb
= NULL
;
2529 buffer_info
->time_stamp
= 0;
2530 /* buffer_info must be completely set up in the transmit path */
2534 * igb_clean_tx_ring - Free Tx Buffers
2535 * @tx_ring: ring to be cleaned
2537 static void igb_clean_tx_ring(struct igb_ring
*tx_ring
)
2539 struct igb_buffer
*buffer_info
;
2543 if (!tx_ring
->buffer_info
)
2545 /* Free all the Tx ring sk_buffs */
2547 for (i
= 0; i
< tx_ring
->count
; i
++) {
2548 buffer_info
= &tx_ring
->buffer_info
[i
];
2549 igb_unmap_and_free_tx_resource(tx_ring
, buffer_info
);
2552 size
= sizeof(struct igb_buffer
) * tx_ring
->count
;
2553 memset(tx_ring
->buffer_info
, 0, size
);
2555 /* Zero out the descriptor ring */
2557 memset(tx_ring
->desc
, 0, tx_ring
->size
);
2559 tx_ring
->next_to_use
= 0;
2560 tx_ring
->next_to_clean
= 0;
2562 writel(0, tx_ring
->head
);
2563 writel(0, tx_ring
->tail
);
2567 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2568 * @adapter: board private structure
2570 static void igb_clean_all_tx_rings(struct igb_adapter
*adapter
)
2574 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
2575 igb_clean_tx_ring(&adapter
->tx_ring
[i
]);
2579 * igb_free_rx_resources - Free Rx Resources
2580 * @rx_ring: ring to clean the resources from
2582 * Free all receive software resources
2584 void igb_free_rx_resources(struct igb_ring
*rx_ring
)
2586 igb_clean_rx_ring(rx_ring
);
2588 vfree(rx_ring
->buffer_info
);
2589 rx_ring
->buffer_info
= NULL
;
2591 pci_free_consistent(rx_ring
->pdev
, rx_ring
->size
,
2592 rx_ring
->desc
, rx_ring
->dma
);
2594 rx_ring
->desc
= NULL
;
2598 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2599 * @adapter: board private structure
2601 * Free all receive software resources
2603 static void igb_free_all_rx_resources(struct igb_adapter
*adapter
)
2607 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
2608 igb_free_rx_resources(&adapter
->rx_ring
[i
]);
2612 * igb_clean_rx_ring - Free Rx Buffers per Queue
2613 * @rx_ring: ring to free buffers from
2615 static void igb_clean_rx_ring(struct igb_ring
*rx_ring
)
2617 struct igb_buffer
*buffer_info
;
2621 if (!rx_ring
->buffer_info
)
2623 /* Free all the Rx ring sk_buffs */
2624 for (i
= 0; i
< rx_ring
->count
; i
++) {
2625 buffer_info
= &rx_ring
->buffer_info
[i
];
2626 if (buffer_info
->dma
) {
2627 pci_unmap_single(rx_ring
->pdev
,
2629 rx_ring
->rx_buffer_len
,
2630 PCI_DMA_FROMDEVICE
);
2631 buffer_info
->dma
= 0;
2634 if (buffer_info
->skb
) {
2635 dev_kfree_skb(buffer_info
->skb
);
2636 buffer_info
->skb
= NULL
;
2638 if (buffer_info
->page_dma
) {
2639 pci_unmap_page(rx_ring
->pdev
,
2640 buffer_info
->page_dma
,
2642 PCI_DMA_FROMDEVICE
);
2643 buffer_info
->page_dma
= 0;
2645 if (buffer_info
->page
) {
2646 put_page(buffer_info
->page
);
2647 buffer_info
->page
= NULL
;
2648 buffer_info
->page_offset
= 0;
2652 size
= sizeof(struct igb_buffer
) * rx_ring
->count
;
2653 memset(rx_ring
->buffer_info
, 0, size
);
2655 /* Zero out the descriptor ring */
2656 memset(rx_ring
->desc
, 0, rx_ring
->size
);
2658 rx_ring
->next_to_clean
= 0;
2659 rx_ring
->next_to_use
= 0;
2661 writel(0, rx_ring
->head
);
2662 writel(0, rx_ring
->tail
);
2666 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2667 * @adapter: board private structure
2669 static void igb_clean_all_rx_rings(struct igb_adapter
*adapter
)
2673 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
2674 igb_clean_rx_ring(&adapter
->rx_ring
[i
]);
2678 * igb_set_mac - Change the Ethernet Address of the NIC
2679 * @netdev: network interface device structure
2680 * @p: pointer to an address structure
2682 * Returns 0 on success, negative on failure
2684 static int igb_set_mac(struct net_device
*netdev
, void *p
)
2686 struct igb_adapter
*adapter
= netdev_priv(netdev
);
2687 struct e1000_hw
*hw
= &adapter
->hw
;
2688 struct sockaddr
*addr
= p
;
2690 if (!is_valid_ether_addr(addr
->sa_data
))
2691 return -EADDRNOTAVAIL
;
2693 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
2694 memcpy(hw
->mac
.addr
, addr
->sa_data
, netdev
->addr_len
);
2696 /* set the correct pool for the new PF MAC address in entry 0 */
2697 igb_rar_set_qsel(adapter
, hw
->mac
.addr
, 0,
2698 adapter
->vfs_allocated_count
);
2704 * igb_write_mc_addr_list - write multicast addresses to MTA
2705 * @netdev: network interface device structure
2707 * Writes multicast address list to the MTA hash table.
2708 * Returns: -ENOMEM on failure
2709 * 0 on no addresses written
2710 * X on writing X addresses to MTA
2712 static int igb_write_mc_addr_list(struct net_device
*netdev
)
2714 struct igb_adapter
*adapter
= netdev_priv(netdev
);
2715 struct e1000_hw
*hw
= &adapter
->hw
;
2716 struct dev_mc_list
*mc_ptr
= netdev
->mc_list
;
2721 if (!netdev
->mc_count
) {
2722 /* nothing to program, so clear mc list */
2723 igb_update_mc_addr_list(hw
, NULL
, 0);
2724 igb_restore_vf_multicasts(adapter
);
2728 mta_list
= kzalloc(netdev
->mc_count
* 6, GFP_ATOMIC
);
2732 /* set vmolr receive overflow multicast bit */
2733 vmolr
|= E1000_VMOLR_ROMPE
;
2735 /* The shared function expects a packed array of only addresses. */
2736 mc_ptr
= netdev
->mc_list
;
2738 for (i
= 0; i
< netdev
->mc_count
; i
++) {
2741 memcpy(mta_list
+ (i
*ETH_ALEN
), mc_ptr
->dmi_addr
, ETH_ALEN
);
2742 mc_ptr
= mc_ptr
->next
;
2744 igb_update_mc_addr_list(hw
, mta_list
, i
);
2747 return netdev
->mc_count
;
2751 * igb_write_uc_addr_list - write unicast addresses to RAR table
2752 * @netdev: network interface device structure
2754 * Writes unicast address list to the RAR table.
2755 * Returns: -ENOMEM on failure/insufficient address space
2756 * 0 on no addresses written
2757 * X on writing X addresses to the RAR table
2759 static int igb_write_uc_addr_list(struct net_device
*netdev
)
2761 struct igb_adapter
*adapter
= netdev_priv(netdev
);
2762 struct e1000_hw
*hw
= &adapter
->hw
;
2763 unsigned int vfn
= adapter
->vfs_allocated_count
;
2764 unsigned int rar_entries
= hw
->mac
.rar_entry_count
- (vfn
+ 1);
2767 /* return ENOMEM indicating insufficient memory for addresses */
2768 if (netdev
->uc
.count
> rar_entries
)
2771 if (netdev
->uc
.count
&& rar_entries
) {
2772 struct netdev_hw_addr
*ha
;
2773 list_for_each_entry(ha
, &netdev
->uc
.list
, list
) {
2776 igb_rar_set_qsel(adapter
, ha
->addr
,
2782 /* write the addresses in reverse order to avoid write combining */
2783 for (; rar_entries
> 0 ; rar_entries
--) {
2784 wr32(E1000_RAH(rar_entries
), 0);
2785 wr32(E1000_RAL(rar_entries
), 0);
2793 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
2794 * @netdev: network interface device structure
2796 * The set_rx_mode entry point is called whenever the unicast or multicast
2797 * address lists or the network interface flags are updated. This routine is
2798 * responsible for configuring the hardware for proper unicast, multicast,
2799 * promiscuous mode, and all-multi behavior.
2801 static void igb_set_rx_mode(struct net_device
*netdev
)
2803 struct igb_adapter
*adapter
= netdev_priv(netdev
);
2804 struct e1000_hw
*hw
= &adapter
->hw
;
2805 unsigned int vfn
= adapter
->vfs_allocated_count
;
2806 u32 rctl
, vmolr
= 0;
2809 /* Check for Promiscuous and All Multicast modes */
2810 rctl
= rd32(E1000_RCTL
);
2812 /* clear the effected bits */
2813 rctl
&= ~(E1000_RCTL_UPE
| E1000_RCTL_MPE
| E1000_RCTL_VFE
);
2815 if (netdev
->flags
& IFF_PROMISC
) {
2816 rctl
|= (E1000_RCTL_UPE
| E1000_RCTL_MPE
);
2817 vmolr
|= (E1000_VMOLR_ROPE
| E1000_VMOLR_MPME
);
2819 if (netdev
->flags
& IFF_ALLMULTI
) {
2820 rctl
|= E1000_RCTL_MPE
;
2821 vmolr
|= E1000_VMOLR_MPME
;
2824 * Write addresses to the MTA, if the attempt fails
2825 * then we should just turn on promiscous mode so
2826 * that we can at least receive multicast traffic
2828 count
= igb_write_mc_addr_list(netdev
);
2830 rctl
|= E1000_RCTL_MPE
;
2831 vmolr
|= E1000_VMOLR_MPME
;
2833 vmolr
|= E1000_VMOLR_ROMPE
;
2837 * Write addresses to available RAR registers, if there is not
2838 * sufficient space to store all the addresses then enable
2839 * unicast promiscous mode
2841 count
= igb_write_uc_addr_list(netdev
);
2843 rctl
|= E1000_RCTL_UPE
;
2844 vmolr
|= E1000_VMOLR_ROPE
;
2846 rctl
|= E1000_RCTL_VFE
;
2848 wr32(E1000_RCTL
, rctl
);
2851 * In order to support SR-IOV and eventually VMDq it is necessary to set
2852 * the VMOLR to enable the appropriate modes. Without this workaround
2853 * we will have issues with VLAN tag stripping not being done for frames
2854 * that are only arriving because we are the default pool
2856 if (hw
->mac
.type
< e1000_82576
)
2859 vmolr
|= rd32(E1000_VMOLR(vfn
)) &
2860 ~(E1000_VMOLR_ROPE
| E1000_VMOLR_MPME
| E1000_VMOLR_ROMPE
);
2861 wr32(E1000_VMOLR(vfn
), vmolr
);
2862 igb_restore_vf_multicasts(adapter
);
2865 /* Need to wait a few seconds after link up to get diagnostic information from
2867 static void igb_update_phy_info(unsigned long data
)
2869 struct igb_adapter
*adapter
= (struct igb_adapter
*) data
;
2870 igb_get_phy_info(&adapter
->hw
);
2874 * igb_has_link - check shared code for link and determine up/down
2875 * @adapter: pointer to driver private info
2877 static bool igb_has_link(struct igb_adapter
*adapter
)
2879 struct e1000_hw
*hw
= &adapter
->hw
;
2880 bool link_active
= false;
2883 /* get_link_status is set on LSC (link status) interrupt or
2884 * rx sequence error interrupt. get_link_status will stay
2885 * false until the e1000_check_for_link establishes link
2886 * for copper adapters ONLY
2888 switch (hw
->phy
.media_type
) {
2889 case e1000_media_type_copper
:
2890 if (hw
->mac
.get_link_status
) {
2891 ret_val
= hw
->mac
.ops
.check_for_link(hw
);
2892 link_active
= !hw
->mac
.get_link_status
;
2897 case e1000_media_type_internal_serdes
:
2898 ret_val
= hw
->mac
.ops
.check_for_link(hw
);
2899 link_active
= hw
->mac
.serdes_has_link
;
2902 case e1000_media_type_unknown
:
2910 * igb_watchdog - Timer Call-back
2911 * @data: pointer to adapter cast into an unsigned long
2913 static void igb_watchdog(unsigned long data
)
2915 struct igb_adapter
*adapter
= (struct igb_adapter
*)data
;
2916 /* Do the rest outside of interrupt context */
2917 schedule_work(&adapter
->watchdog_task
);
2920 static void igb_watchdog_task(struct work_struct
*work
)
2922 struct igb_adapter
*adapter
= container_of(work
,
2923 struct igb_adapter
, watchdog_task
);
2924 struct e1000_hw
*hw
= &adapter
->hw
;
2925 struct net_device
*netdev
= adapter
->netdev
;
2926 struct igb_ring
*tx_ring
= adapter
->tx_ring
;
2930 link
= igb_has_link(adapter
);
2931 if ((netif_carrier_ok(netdev
)) && link
)
2935 if (!netif_carrier_ok(netdev
)) {
2937 hw
->mac
.ops
.get_speed_and_duplex(&adapter
->hw
,
2938 &adapter
->link_speed
,
2939 &adapter
->link_duplex
);
2941 ctrl
= rd32(E1000_CTRL
);
2942 /* Links status message must follow this format */
2943 printk(KERN_INFO
"igb: %s NIC Link is Up %d Mbps %s, "
2944 "Flow Control: %s\n",
2946 adapter
->link_speed
,
2947 adapter
->link_duplex
== FULL_DUPLEX
?
2948 "Full Duplex" : "Half Duplex",
2949 ((ctrl
& E1000_CTRL_TFCE
) && (ctrl
&
2950 E1000_CTRL_RFCE
)) ? "RX/TX" : ((ctrl
&
2951 E1000_CTRL_RFCE
) ? "RX" : ((ctrl
&
2952 E1000_CTRL_TFCE
) ? "TX" : "None")));
2954 /* tweak tx_queue_len according to speed/duplex and
2955 * adjust the timeout factor */
2956 netdev
->tx_queue_len
= adapter
->tx_queue_len
;
2957 adapter
->tx_timeout_factor
= 1;
2958 switch (adapter
->link_speed
) {
2960 netdev
->tx_queue_len
= 10;
2961 adapter
->tx_timeout_factor
= 14;
2964 netdev
->tx_queue_len
= 100;
2965 /* maybe add some timeout factor ? */
2969 netif_carrier_on(netdev
);
2971 igb_ping_all_vfs(adapter
);
2973 /* link state has changed, schedule phy info update */
2974 if (!test_bit(__IGB_DOWN
, &adapter
->state
))
2975 mod_timer(&adapter
->phy_info_timer
,
2976 round_jiffies(jiffies
+ 2 * HZ
));
2979 if (netif_carrier_ok(netdev
)) {
2980 adapter
->link_speed
= 0;
2981 adapter
->link_duplex
= 0;
2982 /* Links status message must follow this format */
2983 printk(KERN_INFO
"igb: %s NIC Link is Down\n",
2985 netif_carrier_off(netdev
);
2987 igb_ping_all_vfs(adapter
);
2989 /* link state has changed, schedule phy info update */
2990 if (!test_bit(__IGB_DOWN
, &adapter
->state
))
2991 mod_timer(&adapter
->phy_info_timer
,
2992 round_jiffies(jiffies
+ 2 * HZ
));
2997 igb_update_stats(adapter
);
2999 hw
->mac
.tx_packet_delta
= adapter
->stats
.tpt
- adapter
->tpt_old
;
3000 adapter
->tpt_old
= adapter
->stats
.tpt
;
3001 hw
->mac
.collision_delta
= adapter
->stats
.colc
- adapter
->colc_old
;
3002 adapter
->colc_old
= adapter
->stats
.colc
;
3004 adapter
->gorc
= adapter
->stats
.gorc
- adapter
->gorc_old
;
3005 adapter
->gorc_old
= adapter
->stats
.gorc
;
3006 adapter
->gotc
= adapter
->stats
.gotc
- adapter
->gotc_old
;
3007 adapter
->gotc_old
= adapter
->stats
.gotc
;
3009 igb_update_adaptive(&adapter
->hw
);
3011 if (!netif_carrier_ok(netdev
)) {
3012 if (igb_desc_unused(tx_ring
) + 1 < tx_ring
->count
) {
3013 /* We've lost link, so the controller stops DMA,
3014 * but we've got queued Tx work that's never going
3015 * to get done, so reset controller to flush Tx.
3016 * (Do the reset outside of interrupt context). */
3017 adapter
->tx_timeout_count
++;
3018 schedule_work(&adapter
->reset_task
);
3019 /* return immediately since reset is imminent */
3024 /* Cause software interrupt to ensure rx ring is cleaned */
3025 if (adapter
->msix_entries
) {
3027 for (i
= 0; i
< adapter
->num_q_vectors
; i
++) {
3028 struct igb_q_vector
*q_vector
= adapter
->q_vector
[i
];
3029 eics
|= q_vector
->eims_value
;
3031 wr32(E1000_EICS
, eics
);
3033 wr32(E1000_ICS
, E1000_ICS_RXDMT0
);
3036 /* Force detection of hung controller every watchdog period */
3037 tx_ring
->detect_tx_hung
= true;
3039 /* Reset the timer */
3040 if (!test_bit(__IGB_DOWN
, &adapter
->state
))
3041 mod_timer(&adapter
->watchdog_timer
,
3042 round_jiffies(jiffies
+ 2 * HZ
));
3045 enum latency_range
{
3049 latency_invalid
= 255
3054 * igb_update_ring_itr - update the dynamic ITR value based on packet size
3056 * Stores a new ITR value based on strictly on packet size. This
3057 * algorithm is less sophisticated than that used in igb_update_itr,
3058 * due to the difficulty of synchronizing statistics across multiple
3059 * receive rings. The divisors and thresholds used by this fuction
3060 * were determined based on theoretical maximum wire speed and testing
3061 * data, in order to minimize response time while increasing bulk
3063 * This functionality is controlled by the InterruptThrottleRate module
3064 * parameter (see igb_param.c)
3065 * NOTE: This function is called only when operating in a multiqueue
3066 * receive environment.
3067 * @q_vector: pointer to q_vector
3069 static void igb_update_ring_itr(struct igb_q_vector
*q_vector
)
3071 int new_val
= q_vector
->itr_val
;
3072 int avg_wire_size
= 0;
3073 struct igb_adapter
*adapter
= q_vector
->adapter
;
3075 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3076 * ints/sec - ITR timer value of 120 ticks.
3078 if (adapter
->link_speed
!= SPEED_1000
) {
3083 if (q_vector
->rx_ring
&& q_vector
->rx_ring
->total_packets
) {
3084 struct igb_ring
*ring
= q_vector
->rx_ring
;
3085 avg_wire_size
= ring
->total_bytes
/ ring
->total_packets
;
3088 if (q_vector
->tx_ring
&& q_vector
->tx_ring
->total_packets
) {
3089 struct igb_ring
*ring
= q_vector
->tx_ring
;
3090 avg_wire_size
= max_t(u32
, avg_wire_size
,
3091 (ring
->total_bytes
/
3092 ring
->total_packets
));
3095 /* if avg_wire_size isn't set no work was done */
3099 /* Add 24 bytes to size to account for CRC, preamble, and gap */
3100 avg_wire_size
+= 24;
3102 /* Don't starve jumbo frames */
3103 avg_wire_size
= min(avg_wire_size
, 3000);
3105 /* Give a little boost to mid-size frames */
3106 if ((avg_wire_size
> 300) && (avg_wire_size
< 1200))
3107 new_val
= avg_wire_size
/ 3;
3109 new_val
= avg_wire_size
/ 2;
3112 if (new_val
!= q_vector
->itr_val
) {
3113 q_vector
->itr_val
= new_val
;
3114 q_vector
->set_itr
= 1;
3117 if (q_vector
->rx_ring
) {
3118 q_vector
->rx_ring
->total_bytes
= 0;
3119 q_vector
->rx_ring
->total_packets
= 0;
3121 if (q_vector
->tx_ring
) {
3122 q_vector
->tx_ring
->total_bytes
= 0;
3123 q_vector
->tx_ring
->total_packets
= 0;
3128 * igb_update_itr - update the dynamic ITR value based on statistics
3129 * Stores a new ITR value based on packets and byte
3130 * counts during the last interrupt. The advantage of per interrupt
3131 * computation is faster updates and more accurate ITR for the current
3132 * traffic pattern. Constants in this function were computed
3133 * based on theoretical maximum wire speed and thresholds were set based
3134 * on testing data as well as attempting to minimize response time
3135 * while increasing bulk throughput.
3136 * this functionality is controlled by the InterruptThrottleRate module
3137 * parameter (see igb_param.c)
3138 * NOTE: These calculations are only valid when operating in a single-
3139 * queue environment.
3140 * @adapter: pointer to adapter
3141 * @itr_setting: current q_vector->itr_val
3142 * @packets: the number of packets during this measurement interval
3143 * @bytes: the number of bytes during this measurement interval
3145 static unsigned int igb_update_itr(struct igb_adapter
*adapter
, u16 itr_setting
,
3146 int packets
, int bytes
)
3148 unsigned int retval
= itr_setting
;
3151 goto update_itr_done
;
3153 switch (itr_setting
) {
3154 case lowest_latency
:
3155 /* handle TSO and jumbo frames */
3156 if (bytes
/packets
> 8000)
3157 retval
= bulk_latency
;
3158 else if ((packets
< 5) && (bytes
> 512))
3159 retval
= low_latency
;
3161 case low_latency
: /* 50 usec aka 20000 ints/s */
3162 if (bytes
> 10000) {
3163 /* this if handles the TSO accounting */
3164 if (bytes
/packets
> 8000) {
3165 retval
= bulk_latency
;
3166 } else if ((packets
< 10) || ((bytes
/packets
) > 1200)) {
3167 retval
= bulk_latency
;
3168 } else if ((packets
> 35)) {
3169 retval
= lowest_latency
;
3171 } else if (bytes
/packets
> 2000) {
3172 retval
= bulk_latency
;
3173 } else if (packets
<= 2 && bytes
< 512) {
3174 retval
= lowest_latency
;
3177 case bulk_latency
: /* 250 usec aka 4000 ints/s */
3178 if (bytes
> 25000) {
3180 retval
= low_latency
;
3181 } else if (bytes
< 1500) {
3182 retval
= low_latency
;
3191 static void igb_set_itr(struct igb_adapter
*adapter
)
3193 struct igb_q_vector
*q_vector
= adapter
->q_vector
[0];
3195 u32 new_itr
= q_vector
->itr_val
;
3197 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3198 if (adapter
->link_speed
!= SPEED_1000
) {
3204 adapter
->rx_itr
= igb_update_itr(adapter
,
3206 adapter
->rx_ring
->total_packets
,
3207 adapter
->rx_ring
->total_bytes
);
3209 adapter
->tx_itr
= igb_update_itr(adapter
,
3211 adapter
->tx_ring
->total_packets
,
3212 adapter
->tx_ring
->total_bytes
);
3213 current_itr
= max(adapter
->rx_itr
, adapter
->tx_itr
);
3215 /* conservative mode (itr 3) eliminates the lowest_latency setting */
3216 if (adapter
->itr_setting
== 3 && current_itr
== lowest_latency
)
3217 current_itr
= low_latency
;
3219 switch (current_itr
) {
3220 /* counts and packets in update_itr are dependent on these numbers */
3221 case lowest_latency
:
3222 new_itr
= 56; /* aka 70,000 ints/sec */
3225 new_itr
= 196; /* aka 20,000 ints/sec */
3228 new_itr
= 980; /* aka 4,000 ints/sec */
3235 adapter
->rx_ring
->total_bytes
= 0;
3236 adapter
->rx_ring
->total_packets
= 0;
3237 adapter
->tx_ring
->total_bytes
= 0;
3238 adapter
->tx_ring
->total_packets
= 0;
3240 if (new_itr
!= q_vector
->itr_val
) {
3241 /* this attempts to bias the interrupt rate towards Bulk
3242 * by adding intermediate steps when interrupt rate is
3244 new_itr
= new_itr
> q_vector
->itr_val
?
3245 max((new_itr
* q_vector
->itr_val
) /
3246 (new_itr
+ (q_vector
->itr_val
>> 2)),
3249 /* Don't write the value here; it resets the adapter's
3250 * internal timer, and causes us to delay far longer than
3251 * we should between interrupts. Instead, we write the ITR
3252 * value at the beginning of the next interrupt so the timing
3253 * ends up being correct.
3255 q_vector
->itr_val
= new_itr
;
3256 q_vector
->set_itr
= 1;
3262 #define IGB_TX_FLAGS_CSUM 0x00000001
3263 #define IGB_TX_FLAGS_VLAN 0x00000002
3264 #define IGB_TX_FLAGS_TSO 0x00000004
3265 #define IGB_TX_FLAGS_IPV4 0x00000008
3266 #define IGB_TX_FLAGS_TSTAMP 0x00000010
3267 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
3268 #define IGB_TX_FLAGS_VLAN_SHIFT 16
3270 static inline int igb_tso_adv(struct igb_ring
*tx_ring
,
3271 struct sk_buff
*skb
, u32 tx_flags
, u8
*hdr_len
)
3273 struct e1000_adv_tx_context_desc
*context_desc
;
3276 struct igb_buffer
*buffer_info
;
3277 u32 info
= 0, tu_cmd
= 0;
3278 u32 mss_l4len_idx
, l4len
;
3281 if (skb_header_cloned(skb
)) {
3282 err
= pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
);
3287 l4len
= tcp_hdrlen(skb
);
3290 if (skb
->protocol
== htons(ETH_P_IP
)) {
3291 struct iphdr
*iph
= ip_hdr(skb
);
3294 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
3298 } else if (skb_shinfo(skb
)->gso_type
== SKB_GSO_TCPV6
) {
3299 ipv6_hdr(skb
)->payload_len
= 0;
3300 tcp_hdr(skb
)->check
= ~csum_ipv6_magic(&ipv6_hdr(skb
)->saddr
,
3301 &ipv6_hdr(skb
)->daddr
,
3305 i
= tx_ring
->next_to_use
;
3307 buffer_info
= &tx_ring
->buffer_info
[i
];
3308 context_desc
= E1000_TX_CTXTDESC_ADV(*tx_ring
, i
);
3309 /* VLAN MACLEN IPLEN */
3310 if (tx_flags
& IGB_TX_FLAGS_VLAN
)
3311 info
|= (tx_flags
& IGB_TX_FLAGS_VLAN_MASK
);
3312 info
|= (skb_network_offset(skb
) << E1000_ADVTXD_MACLEN_SHIFT
);
3313 *hdr_len
+= skb_network_offset(skb
);
3314 info
|= skb_network_header_len(skb
);
3315 *hdr_len
+= skb_network_header_len(skb
);
3316 context_desc
->vlan_macip_lens
= cpu_to_le32(info
);
3318 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3319 tu_cmd
|= (E1000_TXD_CMD_DEXT
| E1000_ADVTXD_DTYP_CTXT
);
3321 if (skb
->protocol
== htons(ETH_P_IP
))
3322 tu_cmd
|= E1000_ADVTXD_TUCMD_IPV4
;
3323 tu_cmd
|= E1000_ADVTXD_TUCMD_L4T_TCP
;
3325 context_desc
->type_tucmd_mlhl
= cpu_to_le32(tu_cmd
);
3328 mss_l4len_idx
= (skb_shinfo(skb
)->gso_size
<< E1000_ADVTXD_MSS_SHIFT
);
3329 mss_l4len_idx
|= (l4len
<< E1000_ADVTXD_L4LEN_SHIFT
);
3331 /* For 82575, context index must be unique per ring. */
3332 if (tx_ring
->flags
& IGB_RING_FLAG_TX_CTX_IDX
)
3333 mss_l4len_idx
|= tx_ring
->reg_idx
<< 4;
3335 context_desc
->mss_l4len_idx
= cpu_to_le32(mss_l4len_idx
);
3336 context_desc
->seqnum_seed
= 0;
3338 buffer_info
->time_stamp
= jiffies
;
3339 buffer_info
->next_to_watch
= i
;
3340 buffer_info
->dma
= 0;
3342 if (i
== tx_ring
->count
)
3345 tx_ring
->next_to_use
= i
;
3350 static inline bool igb_tx_csum_adv(struct igb_ring
*tx_ring
,
3351 struct sk_buff
*skb
, u32 tx_flags
)
3353 struct e1000_adv_tx_context_desc
*context_desc
;
3354 struct pci_dev
*pdev
= tx_ring
->pdev
;
3355 struct igb_buffer
*buffer_info
;
3356 u32 info
= 0, tu_cmd
= 0;
3359 if ((skb
->ip_summed
== CHECKSUM_PARTIAL
) ||
3360 (tx_flags
& IGB_TX_FLAGS_VLAN
)) {
3361 i
= tx_ring
->next_to_use
;
3362 buffer_info
= &tx_ring
->buffer_info
[i
];
3363 context_desc
= E1000_TX_CTXTDESC_ADV(*tx_ring
, i
);
3365 if (tx_flags
& IGB_TX_FLAGS_VLAN
)
3366 info
|= (tx_flags
& IGB_TX_FLAGS_VLAN_MASK
);
3367 info
|= (skb_network_offset(skb
) << E1000_ADVTXD_MACLEN_SHIFT
);
3368 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
3369 info
|= skb_network_header_len(skb
);
3371 context_desc
->vlan_macip_lens
= cpu_to_le32(info
);
3373 tu_cmd
|= (E1000_TXD_CMD_DEXT
| E1000_ADVTXD_DTYP_CTXT
);
3375 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
3378 if (skb
->protocol
== cpu_to_be16(ETH_P_8021Q
)) {
3379 const struct vlan_ethhdr
*vhdr
=
3380 (const struct vlan_ethhdr
*)skb
->data
;
3382 protocol
= vhdr
->h_vlan_encapsulated_proto
;
3384 protocol
= skb
->protocol
;
3388 case cpu_to_be16(ETH_P_IP
):
3389 tu_cmd
|= E1000_ADVTXD_TUCMD_IPV4
;
3390 if (ip_hdr(skb
)->protocol
== IPPROTO_TCP
)
3391 tu_cmd
|= E1000_ADVTXD_TUCMD_L4T_TCP
;
3392 else if (ip_hdr(skb
)->protocol
== IPPROTO_SCTP
)
3393 tu_cmd
|= E1000_ADVTXD_TUCMD_L4T_SCTP
;
3395 case cpu_to_be16(ETH_P_IPV6
):
3396 /* XXX what about other V6 headers?? */
3397 if (ipv6_hdr(skb
)->nexthdr
== IPPROTO_TCP
)
3398 tu_cmd
|= E1000_ADVTXD_TUCMD_L4T_TCP
;
3399 else if (ipv6_hdr(skb
)->nexthdr
== IPPROTO_SCTP
)
3400 tu_cmd
|= E1000_ADVTXD_TUCMD_L4T_SCTP
;
3403 if (unlikely(net_ratelimit()))
3404 dev_warn(&pdev
->dev
,
3405 "partial checksum but proto=%x!\n",
3411 context_desc
->type_tucmd_mlhl
= cpu_to_le32(tu_cmd
);
3412 context_desc
->seqnum_seed
= 0;
3413 if (tx_ring
->flags
& IGB_RING_FLAG_TX_CTX_IDX
)
3414 context_desc
->mss_l4len_idx
=
3415 cpu_to_le32(tx_ring
->reg_idx
<< 4);
3417 buffer_info
->time_stamp
= jiffies
;
3418 buffer_info
->next_to_watch
= i
;
3419 buffer_info
->dma
= 0;
3422 if (i
== tx_ring
->count
)
3424 tx_ring
->next_to_use
= i
;
3431 #define IGB_MAX_TXD_PWR 16
3432 #define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
3434 static inline int igb_tx_map_adv(struct igb_ring
*tx_ring
, struct sk_buff
*skb
,
3437 struct igb_buffer
*buffer_info
;
3438 struct pci_dev
*pdev
= tx_ring
->pdev
;
3439 unsigned int len
= skb_headlen(skb
);
3440 unsigned int count
= 0, i
;
3444 i
= tx_ring
->next_to_use
;
3446 if (skb_dma_map(&pdev
->dev
, skb
, DMA_TO_DEVICE
)) {
3447 dev_err(&pdev
->dev
, "TX DMA map failed\n");
3451 map
= skb_shinfo(skb
)->dma_maps
;
3453 buffer_info
= &tx_ring
->buffer_info
[i
];
3454 BUG_ON(len
>= IGB_MAX_DATA_PER_TXD
);
3455 buffer_info
->length
= len
;
3456 /* set time_stamp *before* dma to help avoid a possible race */
3457 buffer_info
->time_stamp
= jiffies
;
3458 buffer_info
->next_to_watch
= i
;
3459 buffer_info
->dma
= skb_shinfo(skb
)->dma_head
;
3461 for (f
= 0; f
< skb_shinfo(skb
)->nr_frags
; f
++) {
3462 struct skb_frag_struct
*frag
;
3465 if (i
== tx_ring
->count
)
3468 frag
= &skb_shinfo(skb
)->frags
[f
];
3471 buffer_info
= &tx_ring
->buffer_info
[i
];
3472 BUG_ON(len
>= IGB_MAX_DATA_PER_TXD
);
3473 buffer_info
->length
= len
;
3474 buffer_info
->time_stamp
= jiffies
;
3475 buffer_info
->next_to_watch
= i
;
3476 buffer_info
->dma
= map
[count
];
3480 tx_ring
->buffer_info
[i
].skb
= skb
;
3481 tx_ring
->buffer_info
[first
].next_to_watch
= i
;
3486 static inline void igb_tx_queue_adv(struct igb_ring
*tx_ring
,
3487 int tx_flags
, int count
, u32 paylen
,
3490 union e1000_adv_tx_desc
*tx_desc
= NULL
;
3491 struct igb_buffer
*buffer_info
;
3492 u32 olinfo_status
= 0, cmd_type_len
;
3495 cmd_type_len
= (E1000_ADVTXD_DTYP_DATA
| E1000_ADVTXD_DCMD_IFCS
|
3496 E1000_ADVTXD_DCMD_DEXT
);
3498 if (tx_flags
& IGB_TX_FLAGS_VLAN
)
3499 cmd_type_len
|= E1000_ADVTXD_DCMD_VLE
;
3501 if (tx_flags
& IGB_TX_FLAGS_TSTAMP
)
3502 cmd_type_len
|= E1000_ADVTXD_MAC_TSTAMP
;
3504 if (tx_flags
& IGB_TX_FLAGS_TSO
) {
3505 cmd_type_len
|= E1000_ADVTXD_DCMD_TSE
;
3507 /* insert tcp checksum */
3508 olinfo_status
|= E1000_TXD_POPTS_TXSM
<< 8;
3510 /* insert ip checksum */
3511 if (tx_flags
& IGB_TX_FLAGS_IPV4
)
3512 olinfo_status
|= E1000_TXD_POPTS_IXSM
<< 8;
3514 } else if (tx_flags
& IGB_TX_FLAGS_CSUM
) {
3515 olinfo_status
|= E1000_TXD_POPTS_TXSM
<< 8;
3518 if ((tx_ring
->flags
& IGB_RING_FLAG_TX_CTX_IDX
) &&
3519 (tx_flags
& (IGB_TX_FLAGS_CSUM
|
3521 IGB_TX_FLAGS_VLAN
)))
3522 olinfo_status
|= tx_ring
->reg_idx
<< 4;
3524 olinfo_status
|= ((paylen
- hdr_len
) << E1000_ADVTXD_PAYLEN_SHIFT
);
3526 i
= tx_ring
->next_to_use
;
3528 buffer_info
= &tx_ring
->buffer_info
[i
];
3529 tx_desc
= E1000_TX_DESC_ADV(*tx_ring
, i
);
3530 tx_desc
->read
.buffer_addr
= cpu_to_le64(buffer_info
->dma
);
3531 tx_desc
->read
.cmd_type_len
=
3532 cpu_to_le32(cmd_type_len
| buffer_info
->length
);
3533 tx_desc
->read
.olinfo_status
= cpu_to_le32(olinfo_status
);
3535 if (i
== tx_ring
->count
)
3539 tx_desc
->read
.cmd_type_len
|= cpu_to_le32(IGB_ADVTXD_DCMD
);
3540 /* Force memory writes to complete before letting h/w
3541 * know there are new descriptors to fetch. (Only
3542 * applicable for weak-ordered memory model archs,
3543 * such as IA-64). */
3546 tx_ring
->next_to_use
= i
;
3547 writel(i
, tx_ring
->tail
);
3548 /* we need this if more than one processor can write to our tail
3549 * at a time, it syncronizes IO on IA64/Altix systems */
3553 static int __igb_maybe_stop_tx(struct net_device
*netdev
,
3554 struct igb_ring
*tx_ring
, int size
)
3556 netif_stop_subqueue(netdev
, tx_ring
->queue_index
);
3558 /* Herbert's original patch had:
3559 * smp_mb__after_netif_stop_queue();
3560 * but since that doesn't exist yet, just open code it. */
3563 /* We need to check again in a case another CPU has just
3564 * made room available. */
3565 if (igb_desc_unused(tx_ring
) < size
)
3569 netif_wake_subqueue(netdev
, tx_ring
->queue_index
);
3570 tx_ring
->tx_stats
.restart_queue
++;
3574 static int igb_maybe_stop_tx(struct net_device
*netdev
,
3575 struct igb_ring
*tx_ring
, int size
)
3577 if (igb_desc_unused(tx_ring
) >= size
)
3579 return __igb_maybe_stop_tx(netdev
, tx_ring
, size
);
3582 static netdev_tx_t
igb_xmit_frame_ring_adv(struct sk_buff
*skb
,
3583 struct net_device
*netdev
,
3584 struct igb_ring
*tx_ring
)
3586 struct igb_adapter
*adapter
= netdev_priv(netdev
);
3588 unsigned int tx_flags
= 0;
3592 union skb_shared_tx
*shtx
;
3594 if (test_bit(__IGB_DOWN
, &adapter
->state
)) {
3595 dev_kfree_skb_any(skb
);
3596 return NETDEV_TX_OK
;
3599 if (skb
->len
<= 0) {
3600 dev_kfree_skb_any(skb
);
3601 return NETDEV_TX_OK
;
3604 /* need: 1 descriptor per page,
3605 * + 2 desc gap to keep tail from touching head,
3606 * + 1 desc for skb->data,
3607 * + 1 desc for context descriptor,
3608 * otherwise try next time */
3609 if (igb_maybe_stop_tx(netdev
, tx_ring
, skb_shinfo(skb
)->nr_frags
+ 4)) {
3610 /* this is a hard error */
3611 return NETDEV_TX_BUSY
;
3615 * TODO: check that there currently is no other packet with
3616 * time stamping in the queue
3618 * When doing time stamping, keep the connection to the socket
3619 * a while longer: it is still needed by skb_hwtstamp_tx(),
3620 * called either in igb_tx_hwtstamp() or by our caller when
3621 * doing software time stamping.
3624 if (unlikely(shtx
->hardware
)) {
3625 shtx
->in_progress
= 1;
3626 tx_flags
|= IGB_TX_FLAGS_TSTAMP
;
3629 if (adapter
->vlgrp
&& vlan_tx_tag_present(skb
)) {
3630 tx_flags
|= IGB_TX_FLAGS_VLAN
;
3631 tx_flags
|= (vlan_tx_tag_get(skb
) << IGB_TX_FLAGS_VLAN_SHIFT
);
3634 if (skb
->protocol
== htons(ETH_P_IP
))
3635 tx_flags
|= IGB_TX_FLAGS_IPV4
;
3637 first
= tx_ring
->next_to_use
;
3638 if (skb_is_gso(skb
)) {
3639 tso
= igb_tso_adv(tx_ring
, skb
, tx_flags
, &hdr_len
);
3641 dev_kfree_skb_any(skb
);
3642 return NETDEV_TX_OK
;
3647 tx_flags
|= IGB_TX_FLAGS_TSO
;
3648 else if (igb_tx_csum_adv(tx_ring
, skb
, tx_flags
) &&
3649 (skb
->ip_summed
== CHECKSUM_PARTIAL
))
3650 tx_flags
|= IGB_TX_FLAGS_CSUM
;
3653 * count reflects descriptors mapped, if 0 then mapping error
3654 * has occured and we need to rewind the descriptor queue
3656 count
= igb_tx_map_adv(tx_ring
, skb
, first
);
3659 dev_kfree_skb_any(skb
);
3660 tx_ring
->buffer_info
[first
].time_stamp
= 0;
3661 tx_ring
->next_to_use
= first
;
3662 return NETDEV_TX_OK
;
3665 igb_tx_queue_adv(tx_ring
, tx_flags
, count
, skb
->len
, hdr_len
);
3667 /* Make sure there is space in the ring for the next send. */
3668 igb_maybe_stop_tx(netdev
, tx_ring
, MAX_SKB_FRAGS
+ 4);
3670 return NETDEV_TX_OK
;
3673 static netdev_tx_t
igb_xmit_frame_adv(struct sk_buff
*skb
,
3674 struct net_device
*netdev
)
3676 struct igb_adapter
*adapter
= netdev_priv(netdev
);
3677 struct igb_ring
*tx_ring
;
3680 r_idx
= skb
->queue_mapping
& (IGB_ABS_MAX_TX_QUEUES
- 1);
3681 tx_ring
= adapter
->multi_tx_table
[r_idx
];
3683 /* This goes back to the question of how to logically map a tx queue
3684 * to a flow. Right now, performance is impacted slightly negatively
3685 * if using multiple tx queues. If the stack breaks away from a
3686 * single qdisc implementation, we can look at this again. */
3687 return igb_xmit_frame_ring_adv(skb
, netdev
, tx_ring
);
3691 * igb_tx_timeout - Respond to a Tx Hang
3692 * @netdev: network interface device structure
3694 static void igb_tx_timeout(struct net_device
*netdev
)
3696 struct igb_adapter
*adapter
= netdev_priv(netdev
);
3697 struct e1000_hw
*hw
= &adapter
->hw
;
3699 /* Do the reset outside of interrupt context */
3700 adapter
->tx_timeout_count
++;
3701 schedule_work(&adapter
->reset_task
);
3703 (adapter
->eims_enable_mask
& ~adapter
->eims_other
));
3706 static void igb_reset_task(struct work_struct
*work
)
3708 struct igb_adapter
*adapter
;
3709 adapter
= container_of(work
, struct igb_adapter
, reset_task
);
3711 igb_reinit_locked(adapter
);
3715 * igb_get_stats - Get System Network Statistics
3716 * @netdev: network interface device structure
3718 * Returns the address of the device statistics structure.
3719 * The statistics are actually updated from the timer callback.
3721 static struct net_device_stats
*igb_get_stats(struct net_device
*netdev
)
3723 /* only return the current stats */
3724 return &netdev
->stats
;
3728 * igb_change_mtu - Change the Maximum Transfer Unit
3729 * @netdev: network interface device structure
3730 * @new_mtu: new value for maximum frame size
3732 * Returns 0 on success, negative on failure
3734 static int igb_change_mtu(struct net_device
*netdev
, int new_mtu
)
3736 struct igb_adapter
*adapter
= netdev_priv(netdev
);
3737 int max_frame
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
3738 u32 rx_buffer_len
, i
;
3740 if ((max_frame
< ETH_ZLEN
+ ETH_FCS_LEN
) ||
3741 (max_frame
> MAX_JUMBO_FRAME_SIZE
)) {
3742 dev_err(&adapter
->pdev
->dev
, "Invalid MTU setting\n");
3746 if (max_frame
> MAX_STD_JUMBO_FRAME_SIZE
) {
3747 dev_err(&adapter
->pdev
->dev
, "MTU > 9216 not supported.\n");
3751 while (test_and_set_bit(__IGB_RESETTING
, &adapter
->state
))
3754 /* igb_down has a dependency on max_frame_size */
3755 adapter
->max_frame_size
= max_frame
;
3756 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3757 * means we reserve 2 more, this pushes us to allocate from the next
3759 * i.e. RXBUFFER_2048 --> size-4096 slab
3762 if (max_frame
<= IGB_RXBUFFER_1024
)
3763 rx_buffer_len
= IGB_RXBUFFER_1024
;
3764 else if (max_frame
<= MAXIMUM_ETHERNET_VLAN_SIZE
)
3765 rx_buffer_len
= MAXIMUM_ETHERNET_VLAN_SIZE
;
3767 rx_buffer_len
= IGB_RXBUFFER_128
;
3769 if (netif_running(netdev
))
3772 dev_info(&adapter
->pdev
->dev
, "changing MTU from %d to %d\n",
3773 netdev
->mtu
, new_mtu
);
3774 netdev
->mtu
= new_mtu
;
3776 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3777 adapter
->rx_ring
[i
].rx_buffer_len
= rx_buffer_len
;
3779 if (netif_running(netdev
))
3784 clear_bit(__IGB_RESETTING
, &adapter
->state
);
3790 * igb_update_stats - Update the board statistics counters
3791 * @adapter: board private structure
3794 void igb_update_stats(struct igb_adapter
*adapter
)
3796 struct net_device
*netdev
= adapter
->netdev
;
3797 struct e1000_hw
*hw
= &adapter
->hw
;
3798 struct pci_dev
*pdev
= adapter
->pdev
;
3801 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3804 * Prevent stats update while adapter is being reset, or if the pci
3805 * connection is down.
3807 if (adapter
->link_speed
== 0)
3809 if (pci_channel_offline(pdev
))
3812 adapter
->stats
.crcerrs
+= rd32(E1000_CRCERRS
);
3813 adapter
->stats
.gprc
+= rd32(E1000_GPRC
);
3814 adapter
->stats
.gorc
+= rd32(E1000_GORCL
);
3815 rd32(E1000_GORCH
); /* clear GORCL */
3816 adapter
->stats
.bprc
+= rd32(E1000_BPRC
);
3817 adapter
->stats
.mprc
+= rd32(E1000_MPRC
);
3818 adapter
->stats
.roc
+= rd32(E1000_ROC
);
3820 adapter
->stats
.prc64
+= rd32(E1000_PRC64
);
3821 adapter
->stats
.prc127
+= rd32(E1000_PRC127
);
3822 adapter
->stats
.prc255
+= rd32(E1000_PRC255
);
3823 adapter
->stats
.prc511
+= rd32(E1000_PRC511
);
3824 adapter
->stats
.prc1023
+= rd32(E1000_PRC1023
);
3825 adapter
->stats
.prc1522
+= rd32(E1000_PRC1522
);
3826 adapter
->stats
.symerrs
+= rd32(E1000_SYMERRS
);
3827 adapter
->stats
.sec
+= rd32(E1000_SEC
);
3829 adapter
->stats
.mpc
+= rd32(E1000_MPC
);
3830 adapter
->stats
.scc
+= rd32(E1000_SCC
);
3831 adapter
->stats
.ecol
+= rd32(E1000_ECOL
);
3832 adapter
->stats
.mcc
+= rd32(E1000_MCC
);
3833 adapter
->stats
.latecol
+= rd32(E1000_LATECOL
);
3834 adapter
->stats
.dc
+= rd32(E1000_DC
);
3835 adapter
->stats
.rlec
+= rd32(E1000_RLEC
);
3836 adapter
->stats
.xonrxc
+= rd32(E1000_XONRXC
);
3837 adapter
->stats
.xontxc
+= rd32(E1000_XONTXC
);
3838 adapter
->stats
.xoffrxc
+= rd32(E1000_XOFFRXC
);
3839 adapter
->stats
.xofftxc
+= rd32(E1000_XOFFTXC
);
3840 adapter
->stats
.fcruc
+= rd32(E1000_FCRUC
);
3841 adapter
->stats
.gptc
+= rd32(E1000_GPTC
);
3842 adapter
->stats
.gotc
+= rd32(E1000_GOTCL
);
3843 rd32(E1000_GOTCH
); /* clear GOTCL */
3844 adapter
->stats
.rnbc
+= rd32(E1000_RNBC
);
3845 adapter
->stats
.ruc
+= rd32(E1000_RUC
);
3846 adapter
->stats
.rfc
+= rd32(E1000_RFC
);
3847 adapter
->stats
.rjc
+= rd32(E1000_RJC
);
3848 adapter
->stats
.tor
+= rd32(E1000_TORH
);
3849 adapter
->stats
.tot
+= rd32(E1000_TOTH
);
3850 adapter
->stats
.tpr
+= rd32(E1000_TPR
);
3852 adapter
->stats
.ptc64
+= rd32(E1000_PTC64
);
3853 adapter
->stats
.ptc127
+= rd32(E1000_PTC127
);
3854 adapter
->stats
.ptc255
+= rd32(E1000_PTC255
);
3855 adapter
->stats
.ptc511
+= rd32(E1000_PTC511
);
3856 adapter
->stats
.ptc1023
+= rd32(E1000_PTC1023
);
3857 adapter
->stats
.ptc1522
+= rd32(E1000_PTC1522
);
3859 adapter
->stats
.mptc
+= rd32(E1000_MPTC
);
3860 adapter
->stats
.bptc
+= rd32(E1000_BPTC
);
3862 /* used for adaptive IFS */
3864 hw
->mac
.tx_packet_delta
= rd32(E1000_TPT
);
3865 adapter
->stats
.tpt
+= hw
->mac
.tx_packet_delta
;
3866 hw
->mac
.collision_delta
= rd32(E1000_COLC
);
3867 adapter
->stats
.colc
+= hw
->mac
.collision_delta
;
3869 adapter
->stats
.algnerrc
+= rd32(E1000_ALGNERRC
);
3870 adapter
->stats
.rxerrc
+= rd32(E1000_RXERRC
);
3871 adapter
->stats
.tncrs
+= rd32(E1000_TNCRS
);
3872 adapter
->stats
.tsctc
+= rd32(E1000_TSCTC
);
3873 adapter
->stats
.tsctfc
+= rd32(E1000_TSCTFC
);
3875 adapter
->stats
.iac
+= rd32(E1000_IAC
);
3876 adapter
->stats
.icrxoc
+= rd32(E1000_ICRXOC
);
3877 adapter
->stats
.icrxptc
+= rd32(E1000_ICRXPTC
);
3878 adapter
->stats
.icrxatc
+= rd32(E1000_ICRXATC
);
3879 adapter
->stats
.ictxptc
+= rd32(E1000_ICTXPTC
);
3880 adapter
->stats
.ictxatc
+= rd32(E1000_ICTXATC
);
3881 adapter
->stats
.ictxqec
+= rd32(E1000_ICTXQEC
);
3882 adapter
->stats
.ictxqmtc
+= rd32(E1000_ICTXQMTC
);
3883 adapter
->stats
.icrxdmtc
+= rd32(E1000_ICRXDMTC
);
3885 /* Fill out the OS statistics structure */
3886 netdev
->stats
.multicast
= adapter
->stats
.mprc
;
3887 netdev
->stats
.collisions
= adapter
->stats
.colc
;
3891 if (hw
->mac
.type
!= e1000_82575
) {
3893 u64 rqdpc_total
= 0;
3895 /* Read out drops stats per RX queue. Notice RQDPC (Receive
3896 * Queue Drop Packet Count) stats only gets incremented, if
3897 * the DROP_EN but it set (in the SRRCTL register for that
3898 * queue). If DROP_EN bit is NOT set, then the some what
3899 * equivalent count is stored in RNBC (not per queue basis).
3900 * Also note the drop count is due to lack of available
3903 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3904 rqdpc_tmp
= rd32(E1000_RQDPC(i
)) & 0xFFF;
3905 adapter
->rx_ring
[i
].rx_stats
.drops
+= rqdpc_tmp
;
3906 rqdpc_total
+= adapter
->rx_ring
[i
].rx_stats
.drops
;
3908 netdev
->stats
.rx_fifo_errors
= rqdpc_total
;
3911 /* Note RNBC (Receive No Buffers Count) is an not an exact
3912 * drop count as the hardware FIFO might save the day. Thats
3913 * one of the reason for saving it in rx_fifo_errors, as its
3914 * potentially not a true drop.
3916 netdev
->stats
.rx_fifo_errors
+= adapter
->stats
.rnbc
;
3918 /* RLEC on some newer hardware can be incorrect so build
3919 * our own version based on RUC and ROC */
3920 netdev
->stats
.rx_errors
= adapter
->stats
.rxerrc
+
3921 adapter
->stats
.crcerrs
+ adapter
->stats
.algnerrc
+
3922 adapter
->stats
.ruc
+ adapter
->stats
.roc
+
3923 adapter
->stats
.cexterr
;
3924 netdev
->stats
.rx_length_errors
= adapter
->stats
.ruc
+
3926 netdev
->stats
.rx_crc_errors
= adapter
->stats
.crcerrs
;
3927 netdev
->stats
.rx_frame_errors
= adapter
->stats
.algnerrc
;
3928 netdev
->stats
.rx_missed_errors
= adapter
->stats
.mpc
;
3931 netdev
->stats
.tx_errors
= adapter
->stats
.ecol
+
3932 adapter
->stats
.latecol
;
3933 netdev
->stats
.tx_aborted_errors
= adapter
->stats
.ecol
;
3934 netdev
->stats
.tx_window_errors
= adapter
->stats
.latecol
;
3935 netdev
->stats
.tx_carrier_errors
= adapter
->stats
.tncrs
;
3937 /* Tx Dropped needs to be maintained elsewhere */
3940 if (hw
->phy
.media_type
== e1000_media_type_copper
) {
3941 if ((adapter
->link_speed
== SPEED_1000
) &&
3942 (!igb_read_phy_reg(hw
, PHY_1000T_STATUS
, &phy_tmp
))) {
3943 phy_tmp
&= PHY_IDLE_ERROR_COUNT_MASK
;
3944 adapter
->phy_stats
.idle_errors
+= phy_tmp
;
3948 /* Management Stats */
3949 adapter
->stats
.mgptc
+= rd32(E1000_MGTPTC
);
3950 adapter
->stats
.mgprc
+= rd32(E1000_MGTPRC
);
3951 adapter
->stats
.mgpdc
+= rd32(E1000_MGTPDC
);
3954 static irqreturn_t
igb_msix_other(int irq
, void *data
)
3956 struct igb_adapter
*adapter
= data
;
3957 struct e1000_hw
*hw
= &adapter
->hw
;
3958 u32 icr
= rd32(E1000_ICR
);
3959 /* reading ICR causes bit 31 of EICR to be cleared */
3961 if (icr
& E1000_ICR_DOUTSYNC
) {
3962 /* HW is reporting DMA is out of sync */
3963 adapter
->stats
.doosync
++;
3966 /* Check for a mailbox event */
3967 if (icr
& E1000_ICR_VMMB
)
3968 igb_msg_task(adapter
);
3970 if (icr
& E1000_ICR_LSC
) {
3971 hw
->mac
.get_link_status
= 1;
3972 /* guard against interrupt when we're going down */
3973 if (!test_bit(__IGB_DOWN
, &adapter
->state
))
3974 mod_timer(&adapter
->watchdog_timer
, jiffies
+ 1);
3977 wr32(E1000_IMS
, E1000_IMS_LSC
| E1000_IMS_DOUTSYNC
| E1000_IMS_VMMB
);
3978 wr32(E1000_EIMS
, adapter
->eims_other
);
3983 static void igb_write_itr(struct igb_q_vector
*q_vector
)
3985 u32 itr_val
= q_vector
->itr_val
& 0x7FFC;
3987 if (!q_vector
->set_itr
)
3993 if (q_vector
->itr_shift
)
3994 itr_val
|= itr_val
<< q_vector
->itr_shift
;
3996 itr_val
|= 0x8000000;
3998 writel(itr_val
, q_vector
->itr_register
);
3999 q_vector
->set_itr
= 0;
4002 static irqreturn_t
igb_msix_ring(int irq
, void *data
)
4004 struct igb_q_vector
*q_vector
= data
;
4006 /* Write the ITR value calculated from the previous interrupt. */
4007 igb_write_itr(q_vector
);
4009 napi_schedule(&q_vector
->napi
);
4014 #ifdef CONFIG_IGB_DCA
4015 static void igb_update_dca(struct igb_q_vector
*q_vector
)
4017 struct igb_adapter
*adapter
= q_vector
->adapter
;
4018 struct e1000_hw
*hw
= &adapter
->hw
;
4019 int cpu
= get_cpu();
4021 if (q_vector
->cpu
== cpu
)
4024 if (q_vector
->tx_ring
) {
4025 int q
= q_vector
->tx_ring
->reg_idx
;
4026 u32 dca_txctrl
= rd32(E1000_DCA_TXCTRL(q
));
4027 if (hw
->mac
.type
== e1000_82575
) {
4028 dca_txctrl
&= ~E1000_DCA_TXCTRL_CPUID_MASK
;
4029 dca_txctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
4031 dca_txctrl
&= ~E1000_DCA_TXCTRL_CPUID_MASK_82576
;
4032 dca_txctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
4033 E1000_DCA_TXCTRL_CPUID_SHIFT
;
4035 dca_txctrl
|= E1000_DCA_TXCTRL_DESC_DCA_EN
;
4036 wr32(E1000_DCA_TXCTRL(q
), dca_txctrl
);
4038 if (q_vector
->rx_ring
) {
4039 int q
= q_vector
->rx_ring
->reg_idx
;
4040 u32 dca_rxctrl
= rd32(E1000_DCA_RXCTRL(q
));
4041 if (hw
->mac
.type
== e1000_82575
) {
4042 dca_rxctrl
&= ~E1000_DCA_RXCTRL_CPUID_MASK
;
4043 dca_rxctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
4045 dca_rxctrl
&= ~E1000_DCA_RXCTRL_CPUID_MASK_82576
;
4046 dca_rxctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
4047 E1000_DCA_RXCTRL_CPUID_SHIFT
;
4049 dca_rxctrl
|= E1000_DCA_RXCTRL_DESC_DCA_EN
;
4050 dca_rxctrl
|= E1000_DCA_RXCTRL_HEAD_DCA_EN
;
4051 dca_rxctrl
|= E1000_DCA_RXCTRL_DATA_DCA_EN
;
4052 wr32(E1000_DCA_RXCTRL(q
), dca_rxctrl
);
4054 q_vector
->cpu
= cpu
;
4059 static void igb_setup_dca(struct igb_adapter
*adapter
)
4061 struct e1000_hw
*hw
= &adapter
->hw
;
4064 if (!(adapter
->flags
& IGB_FLAG_DCA_ENABLED
))
4067 /* Always use CB2 mode, difference is masked in the CB driver. */
4068 wr32(E1000_DCA_CTRL
, E1000_DCA_CTRL_DCA_MODE_CB2
);
4070 for (i
= 0; i
< adapter
->num_q_vectors
; i
++) {
4071 struct igb_q_vector
*q_vector
= adapter
->q_vector
[i
];
4073 igb_update_dca(q_vector
);
4077 static int __igb_notify_dca(struct device
*dev
, void *data
)
4079 struct net_device
*netdev
= dev_get_drvdata(dev
);
4080 struct igb_adapter
*adapter
= netdev_priv(netdev
);
4081 struct e1000_hw
*hw
= &adapter
->hw
;
4082 unsigned long event
= *(unsigned long *)data
;
4085 case DCA_PROVIDER_ADD
:
4086 /* if already enabled, don't do it again */
4087 if (adapter
->flags
& IGB_FLAG_DCA_ENABLED
)
4089 /* Always use CB2 mode, difference is masked
4090 * in the CB driver. */
4091 wr32(E1000_DCA_CTRL
, E1000_DCA_CTRL_DCA_MODE_CB2
);
4092 if (dca_add_requester(dev
) == 0) {
4093 adapter
->flags
|= IGB_FLAG_DCA_ENABLED
;
4094 dev_info(&adapter
->pdev
->dev
, "DCA enabled\n");
4095 igb_setup_dca(adapter
);
4098 /* Fall Through since DCA is disabled. */
4099 case DCA_PROVIDER_REMOVE
:
4100 if (adapter
->flags
& IGB_FLAG_DCA_ENABLED
) {
4101 /* without this a class_device is left
4102 * hanging around in the sysfs model */
4103 dca_remove_requester(dev
);
4104 dev_info(&adapter
->pdev
->dev
, "DCA disabled\n");
4105 adapter
->flags
&= ~IGB_FLAG_DCA_ENABLED
;
4106 wr32(E1000_DCA_CTRL
, E1000_DCA_CTRL_DCA_MODE_DISABLE
);
4114 static int igb_notify_dca(struct notifier_block
*nb
, unsigned long event
,
4119 ret_val
= driver_for_each_device(&igb_driver
.driver
, NULL
, &event
,
4122 return ret_val
? NOTIFY_BAD
: NOTIFY_DONE
;
4124 #endif /* CONFIG_IGB_DCA */
4126 static void igb_ping_all_vfs(struct igb_adapter
*adapter
)
4128 struct e1000_hw
*hw
= &adapter
->hw
;
4132 for (i
= 0 ; i
< adapter
->vfs_allocated_count
; i
++) {
4133 ping
= E1000_PF_CONTROL_MSG
;
4134 if (adapter
->vf_data
[i
].clear_to_send
)
4135 ping
|= E1000_VT_MSGTYPE_CTS
;
4136 igb_write_mbx(hw
, &ping
, 1, i
);
4140 static int igb_set_vf_multicasts(struct igb_adapter
*adapter
,
4141 u32
*msgbuf
, u32 vf
)
4143 int n
= (msgbuf
[0] & E1000_VT_MSGINFO_MASK
) >> E1000_VT_MSGINFO_SHIFT
;
4144 u16
*hash_list
= (u16
*)&msgbuf
[1];
4145 struct vf_data_storage
*vf_data
= &adapter
->vf_data
[vf
];
4148 /* only up to 30 hash values supported */
4152 /* salt away the number of multi cast addresses assigned
4153 * to this VF for later use to restore when the PF multi cast
4156 vf_data
->num_vf_mc_hashes
= n
;
4158 /* VFs are limited to using the MTA hash table for their multicast
4160 for (i
= 0; i
< n
; i
++)
4161 vf_data
->vf_mc_hashes
[i
] = hash_list
[i
];
4163 /* Flush and reset the mta with the new values */
4164 igb_set_rx_mode(adapter
->netdev
);
4169 static void igb_restore_vf_multicasts(struct igb_adapter
*adapter
)
4171 struct e1000_hw
*hw
= &adapter
->hw
;
4172 struct vf_data_storage
*vf_data
;
4175 for (i
= 0; i
< adapter
->vfs_allocated_count
; i
++) {
4176 vf_data
= &adapter
->vf_data
[i
];
4177 for (j
= 0; j
< vf_data
->num_vf_mc_hashes
; j
++)
4178 igb_mta_set(hw
, vf_data
->vf_mc_hashes
[j
]);
4182 static void igb_clear_vf_vfta(struct igb_adapter
*adapter
, u32 vf
)
4184 struct e1000_hw
*hw
= &adapter
->hw
;
4185 u32 pool_mask
, reg
, vid
;
4188 pool_mask
= 1 << (E1000_VLVF_POOLSEL_SHIFT
+ vf
);
4190 /* Find the vlan filter for this id */
4191 for (i
= 0; i
< E1000_VLVF_ARRAY_SIZE
; i
++) {
4192 reg
= rd32(E1000_VLVF(i
));
4194 /* remove the vf from the pool */
4197 /* if pool is empty then remove entry from vfta */
4198 if (!(reg
& E1000_VLVF_POOLSEL_MASK
) &&
4199 (reg
& E1000_VLVF_VLANID_ENABLE
)) {
4201 vid
= reg
& E1000_VLVF_VLANID_MASK
;
4202 igb_vfta_set(hw
, vid
, false);
4205 wr32(E1000_VLVF(i
), reg
);
4208 adapter
->vf_data
[vf
].vlans_enabled
= 0;
4211 static s32
igb_vlvf_set(struct igb_adapter
*adapter
, u32 vid
, bool add
, u32 vf
)
4213 struct e1000_hw
*hw
= &adapter
->hw
;
4216 /* It is an error to call this function when VFs are not enabled */
4217 if (!adapter
->vfs_allocated_count
)
4220 /* Find the vlan filter for this id */
4221 for (i
= 0; i
< E1000_VLVF_ARRAY_SIZE
; i
++) {
4222 reg
= rd32(E1000_VLVF(i
));
4223 if ((reg
& E1000_VLVF_VLANID_ENABLE
) &&
4224 vid
== (reg
& E1000_VLVF_VLANID_MASK
))
4229 if (i
== E1000_VLVF_ARRAY_SIZE
) {
4230 /* Did not find a matching VLAN ID entry that was
4231 * enabled. Search for a free filter entry, i.e.
4232 * one without the enable bit set
4234 for (i
= 0; i
< E1000_VLVF_ARRAY_SIZE
; i
++) {
4235 reg
= rd32(E1000_VLVF(i
));
4236 if (!(reg
& E1000_VLVF_VLANID_ENABLE
))
4240 if (i
< E1000_VLVF_ARRAY_SIZE
) {
4241 /* Found an enabled/available entry */
4242 reg
|= 1 << (E1000_VLVF_POOLSEL_SHIFT
+ vf
);
4244 /* if !enabled we need to set this up in vfta */
4245 if (!(reg
& E1000_VLVF_VLANID_ENABLE
)) {
4246 /* add VID to filter table, if bit already set
4247 * PF must have added it outside of table */
4248 if (igb_vfta_set(hw
, vid
, true))
4249 reg
|= 1 << (E1000_VLVF_POOLSEL_SHIFT
+
4250 adapter
->vfs_allocated_count
);
4251 reg
|= E1000_VLVF_VLANID_ENABLE
;
4253 reg
&= ~E1000_VLVF_VLANID_MASK
;
4256 wr32(E1000_VLVF(i
), reg
);
4258 /* do not modify RLPML for PF devices */
4259 if (vf
>= adapter
->vfs_allocated_count
)
4262 if (!adapter
->vf_data
[vf
].vlans_enabled
) {
4264 reg
= rd32(E1000_VMOLR(vf
));
4265 size
= reg
& E1000_VMOLR_RLPML_MASK
;
4267 reg
&= ~E1000_VMOLR_RLPML_MASK
;
4269 wr32(E1000_VMOLR(vf
), reg
);
4271 adapter
->vf_data
[vf
].vlans_enabled
++;
4276 if (i
< E1000_VLVF_ARRAY_SIZE
) {
4277 /* remove vf from the pool */
4278 reg
&= ~(1 << (E1000_VLVF_POOLSEL_SHIFT
+ vf
));
4279 /* if pool is empty then remove entry from vfta */
4280 if (!(reg
& E1000_VLVF_POOLSEL_MASK
)) {
4282 igb_vfta_set(hw
, vid
, false);
4284 wr32(E1000_VLVF(i
), reg
);
4286 /* do not modify RLPML for PF devices */
4287 if (vf
>= adapter
->vfs_allocated_count
)
4290 adapter
->vf_data
[vf
].vlans_enabled
--;
4291 if (!adapter
->vf_data
[vf
].vlans_enabled
) {
4293 reg
= rd32(E1000_VMOLR(vf
));
4294 size
= reg
& E1000_VMOLR_RLPML_MASK
;
4296 reg
&= ~E1000_VMOLR_RLPML_MASK
;
4298 wr32(E1000_VMOLR(vf
), reg
);
4306 static int igb_set_vf_vlan(struct igb_adapter
*adapter
, u32
*msgbuf
, u32 vf
)
4308 int add
= (msgbuf
[0] & E1000_VT_MSGINFO_MASK
) >> E1000_VT_MSGINFO_SHIFT
;
4309 int vid
= (msgbuf
[1] & E1000_VLVF_VLANID_MASK
);
4311 return igb_vlvf_set(adapter
, vid
, add
, vf
);
4314 static inline void igb_vf_reset_event(struct igb_adapter
*adapter
, u32 vf
)
4316 struct e1000_hw
*hw
= &adapter
->hw
;
4318 /* disable mailbox functionality for vf */
4319 adapter
->vf_data
[vf
].clear_to_send
= false;
4321 /* reset offloads to defaults */
4322 igb_set_vmolr(hw
, vf
);
4324 /* reset vlans for device */
4325 igb_clear_vf_vfta(adapter
, vf
);
4327 /* reset multicast table array for vf */
4328 adapter
->vf_data
[vf
].num_vf_mc_hashes
= 0;
4330 /* Flush and reset the mta with the new values */
4331 igb_set_rx_mode(adapter
->netdev
);
4334 static inline void igb_vf_reset_msg(struct igb_adapter
*adapter
, u32 vf
)
4336 struct e1000_hw
*hw
= &adapter
->hw
;
4337 unsigned char *vf_mac
= adapter
->vf_data
[vf
].vf_mac_addresses
;
4338 int rar_entry
= hw
->mac
.rar_entry_count
- (vf
+ 1);
4340 u8
*addr
= (u8
*)(&msgbuf
[1]);
4342 /* process all the same items cleared in a function level reset */
4343 igb_vf_reset_event(adapter
, vf
);
4345 /* set vf mac address */
4346 igb_rar_set_qsel(adapter
, vf_mac
, rar_entry
, vf
);
4348 /* enable transmit and receive for vf */
4349 reg
= rd32(E1000_VFTE
);
4350 wr32(E1000_VFTE
, reg
| (1 << vf
));
4351 reg
= rd32(E1000_VFRE
);
4352 wr32(E1000_VFRE
, reg
| (1 << vf
));
4354 /* enable mailbox functionality for vf */
4355 adapter
->vf_data
[vf
].clear_to_send
= true;
4357 /* reply to reset with ack and vf mac address */
4358 msgbuf
[0] = E1000_VF_RESET
| E1000_VT_MSGTYPE_ACK
;
4359 memcpy(addr
, vf_mac
, 6);
4360 igb_write_mbx(hw
, msgbuf
, 3, vf
);
4363 static int igb_set_vf_mac_addr(struct igb_adapter
*adapter
, u32
*msg
, int vf
)
4365 unsigned char *addr
= (char *)&msg
[1];
4368 if (is_valid_ether_addr(addr
))
4369 err
= igb_set_vf_mac(adapter
, vf
, addr
);
4375 static void igb_rcv_ack_from_vf(struct igb_adapter
*adapter
, u32 vf
)
4377 struct e1000_hw
*hw
= &adapter
->hw
;
4378 u32 msg
= E1000_VT_MSGTYPE_NACK
;
4380 /* if device isn't clear to send it shouldn't be reading either */
4381 if (!adapter
->vf_data
[vf
].clear_to_send
)
4382 igb_write_mbx(hw
, &msg
, 1, vf
);
4386 static void igb_msg_task(struct igb_adapter
*adapter
)
4388 struct e1000_hw
*hw
= &adapter
->hw
;
4391 for (vf
= 0; vf
< adapter
->vfs_allocated_count
; vf
++) {
4392 /* process any reset requests */
4393 if (!igb_check_for_rst(hw
, vf
)) {
4394 adapter
->vf_data
[vf
].clear_to_send
= false;
4395 igb_vf_reset_event(adapter
, vf
);
4398 /* process any messages pending */
4399 if (!igb_check_for_msg(hw
, vf
))
4400 igb_rcv_msg_from_vf(adapter
, vf
);
4402 /* process any acks */
4403 if (!igb_check_for_ack(hw
, vf
))
4404 igb_rcv_ack_from_vf(adapter
, vf
);
4409 static int igb_rcv_msg_from_vf(struct igb_adapter
*adapter
, u32 vf
)
4411 u32 mbx_size
= E1000_VFMAILBOX_SIZE
;
4412 u32 msgbuf
[mbx_size
];
4413 struct e1000_hw
*hw
= &adapter
->hw
;
4416 retval
= igb_read_mbx(hw
, msgbuf
, mbx_size
, vf
);
4419 dev_err(&adapter
->pdev
->dev
,
4420 "Error receiving message from VF\n");
4422 /* this is a message we already processed, do nothing */
4423 if (msgbuf
[0] & (E1000_VT_MSGTYPE_ACK
| E1000_VT_MSGTYPE_NACK
))
4427 * until the vf completes a reset it should not be
4428 * allowed to start any configuration.
4431 if (msgbuf
[0] == E1000_VF_RESET
) {
4432 igb_vf_reset_msg(adapter
, vf
);
4437 if (!adapter
->vf_data
[vf
].clear_to_send
) {
4438 msgbuf
[0] |= E1000_VT_MSGTYPE_NACK
;
4439 igb_write_mbx(hw
, msgbuf
, 1, vf
);
4443 switch ((msgbuf
[0] & 0xFFFF)) {
4444 case E1000_VF_SET_MAC_ADDR
:
4445 retval
= igb_set_vf_mac_addr(adapter
, msgbuf
, vf
);
4447 case E1000_VF_SET_MULTICAST
:
4448 retval
= igb_set_vf_multicasts(adapter
, msgbuf
, vf
);
4450 case E1000_VF_SET_LPE
:
4451 retval
= igb_set_vf_rlpml(adapter
, msgbuf
[1], vf
);
4453 case E1000_VF_SET_VLAN
:
4454 retval
= igb_set_vf_vlan(adapter
, msgbuf
, vf
);
4457 dev_err(&adapter
->pdev
->dev
, "Unhandled Msg %08x\n", msgbuf
[0]);
4462 /* notify the VF of the results of what it sent us */
4464 msgbuf
[0] |= E1000_VT_MSGTYPE_NACK
;
4466 msgbuf
[0] |= E1000_VT_MSGTYPE_ACK
;
4468 msgbuf
[0] |= E1000_VT_MSGTYPE_CTS
;
4470 igb_write_mbx(hw
, msgbuf
, 1, vf
);
4476 * igb_set_uta - Set unicast filter table address
4477 * @adapter: board private structure
4479 * The unicast table address is a register array of 32-bit registers.
4480 * The table is meant to be used in a way similar to how the MTA is used
4481 * however due to certain limitations in the hardware it is necessary to
4482 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscous
4483 * enable bit to allow vlan tag stripping when promiscous mode is enabled
4485 static void igb_set_uta(struct igb_adapter
*adapter
)
4487 struct e1000_hw
*hw
= &adapter
->hw
;
4490 /* The UTA table only exists on 82576 hardware and newer */
4491 if (hw
->mac
.type
< e1000_82576
)
4494 /* we only need to do this if VMDq is enabled */
4495 if (!adapter
->vfs_allocated_count
)
4498 for (i
= 0; i
< hw
->mac
.uta_reg_count
; i
++)
4499 array_wr32(E1000_UTA
, i
, ~0);
4503 * igb_intr_msi - Interrupt Handler
4504 * @irq: interrupt number
4505 * @data: pointer to a network interface device structure
4507 static irqreturn_t
igb_intr_msi(int irq
, void *data
)
4509 struct igb_adapter
*adapter
= data
;
4510 struct igb_q_vector
*q_vector
= adapter
->q_vector
[0];
4511 struct e1000_hw
*hw
= &adapter
->hw
;
4512 /* read ICR disables interrupts using IAM */
4513 u32 icr
= rd32(E1000_ICR
);
4515 igb_write_itr(q_vector
);
4517 if (icr
& E1000_ICR_DOUTSYNC
) {
4518 /* HW is reporting DMA is out of sync */
4519 adapter
->stats
.doosync
++;
4522 if (icr
& (E1000_ICR_RXSEQ
| E1000_ICR_LSC
)) {
4523 hw
->mac
.get_link_status
= 1;
4524 if (!test_bit(__IGB_DOWN
, &adapter
->state
))
4525 mod_timer(&adapter
->watchdog_timer
, jiffies
+ 1);
4528 napi_schedule(&q_vector
->napi
);
4534 * igb_intr - Legacy Interrupt Handler
4535 * @irq: interrupt number
4536 * @data: pointer to a network interface device structure
4538 static irqreturn_t
igb_intr(int irq
, void *data
)
4540 struct igb_adapter
*adapter
= data
;
4541 struct igb_q_vector
*q_vector
= adapter
->q_vector
[0];
4542 struct e1000_hw
*hw
= &adapter
->hw
;
4543 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
4544 * need for the IMC write */
4545 u32 icr
= rd32(E1000_ICR
);
4547 return IRQ_NONE
; /* Not our interrupt */
4549 igb_write_itr(q_vector
);
4551 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4552 * not set, then the adapter didn't send an interrupt */
4553 if (!(icr
& E1000_ICR_INT_ASSERTED
))
4556 if (icr
& E1000_ICR_DOUTSYNC
) {
4557 /* HW is reporting DMA is out of sync */
4558 adapter
->stats
.doosync
++;
4561 if (icr
& (E1000_ICR_RXSEQ
| E1000_ICR_LSC
)) {
4562 hw
->mac
.get_link_status
= 1;
4563 /* guard against interrupt when we're going down */
4564 if (!test_bit(__IGB_DOWN
, &adapter
->state
))
4565 mod_timer(&adapter
->watchdog_timer
, jiffies
+ 1);
4568 napi_schedule(&q_vector
->napi
);
4573 static inline void igb_ring_irq_enable(struct igb_q_vector
*q_vector
)
4575 struct igb_adapter
*adapter
= q_vector
->adapter
;
4576 struct e1000_hw
*hw
= &adapter
->hw
;
4578 if (adapter
->itr_setting
& 3) {
4579 if (!adapter
->msix_entries
)
4580 igb_set_itr(adapter
);
4582 igb_update_ring_itr(q_vector
);
4585 if (!test_bit(__IGB_DOWN
, &adapter
->state
)) {
4586 if (adapter
->msix_entries
)
4587 wr32(E1000_EIMS
, q_vector
->eims_value
);
4589 igb_irq_enable(adapter
);
4594 * igb_poll - NAPI Rx polling callback
4595 * @napi: napi polling structure
4596 * @budget: count of how many packets we should handle
4598 static int igb_poll(struct napi_struct
*napi
, int budget
)
4600 struct igb_q_vector
*q_vector
= container_of(napi
,
4601 struct igb_q_vector
,
4603 int tx_clean_complete
= 1, work_done
= 0;
4605 #ifdef CONFIG_IGB_DCA
4606 if (q_vector
->adapter
->flags
& IGB_FLAG_DCA_ENABLED
)
4607 igb_update_dca(q_vector
);
4609 if (q_vector
->tx_ring
)
4610 tx_clean_complete
= igb_clean_tx_irq(q_vector
);
4612 if (q_vector
->rx_ring
)
4613 igb_clean_rx_irq_adv(q_vector
, &work_done
, budget
);
4615 if (!tx_clean_complete
)
4618 /* If not enough Rx work done, exit the polling mode */
4619 if (work_done
< budget
) {
4620 napi_complete(napi
);
4621 igb_ring_irq_enable(q_vector
);
4628 * igb_hwtstamp - utility function which checks for TX time stamp
4629 * @adapter: board private structure
4630 * @skb: packet that was just sent
4632 * If we were asked to do hardware stamping and such a time stamp is
4633 * available, then it must have been for this skb here because we only
4634 * allow only one such packet into the queue.
4636 static void igb_tx_hwtstamp(struct igb_adapter
*adapter
, struct sk_buff
*skb
)
4638 union skb_shared_tx
*shtx
= skb_tx(skb
);
4639 struct e1000_hw
*hw
= &adapter
->hw
;
4641 if (unlikely(shtx
->hardware
)) {
4642 u32 valid
= rd32(E1000_TSYNCTXCTL
) & E1000_TSYNCTXCTL_VALID
;
4644 u64 regval
= rd32(E1000_TXSTMPL
);
4646 struct skb_shared_hwtstamps shhwtstamps
;
4648 memset(&shhwtstamps
, 0, sizeof(shhwtstamps
));
4649 regval
|= (u64
)rd32(E1000_TXSTMPH
) << 32;
4650 ns
= timecounter_cyc2time(&adapter
->clock
,
4652 timecompare_update(&adapter
->compare
, ns
);
4653 shhwtstamps
.hwtstamp
= ns_to_ktime(ns
);
4654 shhwtstamps
.syststamp
=
4655 timecompare_transform(&adapter
->compare
, ns
);
4656 skb_tstamp_tx(skb
, &shhwtstamps
);
4662 * igb_clean_tx_irq - Reclaim resources after transmit completes
4663 * @q_vector: pointer to q_vector containing needed info
4664 * returns true if ring is completely cleaned
4666 static bool igb_clean_tx_irq(struct igb_q_vector
*q_vector
)
4668 struct igb_adapter
*adapter
= q_vector
->adapter
;
4669 struct igb_ring
*tx_ring
= q_vector
->tx_ring
;
4670 struct net_device
*netdev
= adapter
->netdev
;
4671 struct e1000_hw
*hw
= &adapter
->hw
;
4672 struct igb_buffer
*buffer_info
;
4673 struct sk_buff
*skb
;
4674 union e1000_adv_tx_desc
*tx_desc
, *eop_desc
;
4675 unsigned int total_bytes
= 0, total_packets
= 0;
4676 unsigned int i
, eop
, count
= 0;
4677 bool cleaned
= false;
4679 i
= tx_ring
->next_to_clean
;
4680 eop
= tx_ring
->buffer_info
[i
].next_to_watch
;
4681 eop_desc
= E1000_TX_DESC_ADV(*tx_ring
, eop
);
4683 while ((eop_desc
->wb
.status
& cpu_to_le32(E1000_TXD_STAT_DD
)) &&
4684 (count
< tx_ring
->count
)) {
4685 for (cleaned
= false; !cleaned
; count
++) {
4686 tx_desc
= E1000_TX_DESC_ADV(*tx_ring
, i
);
4687 buffer_info
= &tx_ring
->buffer_info
[i
];
4688 cleaned
= (i
== eop
);
4689 skb
= buffer_info
->skb
;
4692 unsigned int segs
, bytecount
;
4693 /* gso_segs is currently only valid for tcp */
4694 segs
= skb_shinfo(skb
)->gso_segs
?: 1;
4695 /* multiply data chunks by size of headers */
4696 bytecount
= ((segs
- 1) * skb_headlen(skb
)) +
4698 total_packets
+= segs
;
4699 total_bytes
+= bytecount
;
4701 igb_tx_hwtstamp(adapter
, skb
);
4704 igb_unmap_and_free_tx_resource(tx_ring
, buffer_info
);
4705 tx_desc
->wb
.status
= 0;
4708 if (i
== tx_ring
->count
)
4711 eop
= tx_ring
->buffer_info
[i
].next_to_watch
;
4712 eop_desc
= E1000_TX_DESC_ADV(*tx_ring
, eop
);
4715 tx_ring
->next_to_clean
= i
;
4717 if (unlikely(count
&&
4718 netif_carrier_ok(netdev
) &&
4719 igb_desc_unused(tx_ring
) >= IGB_TX_QUEUE_WAKE
)) {
4720 /* Make sure that anybody stopping the queue after this
4721 * sees the new next_to_clean.
4724 if (__netif_subqueue_stopped(netdev
, tx_ring
->queue_index
) &&
4725 !(test_bit(__IGB_DOWN
, &adapter
->state
))) {
4726 netif_wake_subqueue(netdev
, tx_ring
->queue_index
);
4727 tx_ring
->tx_stats
.restart_queue
++;
4731 if (tx_ring
->detect_tx_hung
) {
4732 /* Detect a transmit hang in hardware, this serializes the
4733 * check with the clearing of time_stamp and movement of i */
4734 tx_ring
->detect_tx_hung
= false;
4735 if (tx_ring
->buffer_info
[i
].time_stamp
&&
4736 time_after(jiffies
, tx_ring
->buffer_info
[i
].time_stamp
+
4737 (adapter
->tx_timeout_factor
* HZ
))
4738 && !(rd32(E1000_STATUS
) &
4739 E1000_STATUS_TXOFF
)) {
4741 /* detected Tx unit hang */
4742 dev_err(&tx_ring
->pdev
->dev
,
4743 "Detected Tx Unit Hang\n"
4747 " next_to_use <%x>\n"
4748 " next_to_clean <%x>\n"
4749 "buffer_info[next_to_clean]\n"
4750 " time_stamp <%lx>\n"
4751 " next_to_watch <%x>\n"
4753 " desc.status <%x>\n",
4754 tx_ring
->queue_index
,
4755 readl(tx_ring
->head
),
4756 readl(tx_ring
->tail
),
4757 tx_ring
->next_to_use
,
4758 tx_ring
->next_to_clean
,
4759 tx_ring
->buffer_info
[i
].time_stamp
,
4762 eop_desc
->wb
.status
);
4763 netif_stop_subqueue(netdev
, tx_ring
->queue_index
);
4766 tx_ring
->total_bytes
+= total_bytes
;
4767 tx_ring
->total_packets
+= total_packets
;
4768 tx_ring
->tx_stats
.bytes
+= total_bytes
;
4769 tx_ring
->tx_stats
.packets
+= total_packets
;
4770 netdev
->stats
.tx_bytes
+= total_bytes
;
4771 netdev
->stats
.tx_packets
+= total_packets
;
4772 return (count
< tx_ring
->count
);
4776 * igb_receive_skb - helper function to handle rx indications
4777 * @q_vector: structure containing interrupt and ring information
4778 * @skb: packet to send up
4779 * @vlan_tag: vlan tag for packet
4781 static void igb_receive_skb(struct igb_q_vector
*q_vector
,
4782 struct sk_buff
*skb
,
4785 struct igb_adapter
*adapter
= q_vector
->adapter
;
4788 vlan_gro_receive(&q_vector
->napi
, adapter
->vlgrp
,
4791 napi_gro_receive(&q_vector
->napi
, skb
);
4794 static inline void igb_rx_checksum_adv(struct igb_ring
*ring
,
4795 u32 status_err
, struct sk_buff
*skb
)
4797 skb
->ip_summed
= CHECKSUM_NONE
;
4799 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
4800 if (!(ring
->flags
& IGB_RING_FLAG_RX_CSUM
) ||
4801 (status_err
& E1000_RXD_STAT_IXSM
))
4804 /* TCP/UDP checksum error bit is set */
4806 (E1000_RXDEXT_STATERR_TCPE
| E1000_RXDEXT_STATERR_IPE
)) {
4808 * work around errata with sctp packets where the TCPE aka
4809 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
4810 * packets, (aka let the stack check the crc32c)
4812 if ((skb
->len
== 60) &&
4813 (ring
->flags
& IGB_RING_FLAG_RX_SCTP_CSUM
))
4814 ring
->rx_stats
.csum_err
++;
4816 /* let the stack verify checksum errors */
4819 /* It must be a TCP or UDP packet with a valid checksum */
4820 if (status_err
& (E1000_RXD_STAT_TCPCS
| E1000_RXD_STAT_UDPCS
))
4821 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
4823 dev_dbg(&ring
->pdev
->dev
, "cksum success: bits %08X\n", status_err
);
4826 static inline u16
igb_get_hlen(struct igb_ring
*rx_ring
,
4827 union e1000_adv_rx_desc
*rx_desc
)
4829 /* HW will not DMA in data larger than the given buffer, even if it
4830 * parses the (NFS, of course) header to be larger. In that case, it
4831 * fills the header buffer and spills the rest into the page.
4833 u16 hlen
= (le16_to_cpu(rx_desc
->wb
.lower
.lo_dword
.hdr_info
) &
4834 E1000_RXDADV_HDRBUFLEN_MASK
) >> E1000_RXDADV_HDRBUFLEN_SHIFT
;
4835 if (hlen
> rx_ring
->rx_buffer_len
)
4836 hlen
= rx_ring
->rx_buffer_len
;
4840 static bool igb_clean_rx_irq_adv(struct igb_q_vector
*q_vector
,
4841 int *work_done
, int budget
)
4843 struct igb_adapter
*adapter
= q_vector
->adapter
;
4844 struct net_device
*netdev
= adapter
->netdev
;
4845 struct igb_ring
*rx_ring
= q_vector
->rx_ring
;
4846 struct e1000_hw
*hw
= &adapter
->hw
;
4847 struct pci_dev
*pdev
= rx_ring
->pdev
;
4848 union e1000_adv_rx_desc
*rx_desc
, *next_rxd
;
4849 struct igb_buffer
*buffer_info
, *next_buffer
;
4850 struct sk_buff
*skb
;
4851 bool cleaned
= false;
4852 int cleaned_count
= 0;
4853 unsigned int total_bytes
= 0, total_packets
= 0;
4859 i
= rx_ring
->next_to_clean
;
4860 buffer_info
= &rx_ring
->buffer_info
[i
];
4861 rx_desc
= E1000_RX_DESC_ADV(*rx_ring
, i
);
4862 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
4864 while (staterr
& E1000_RXD_STAT_DD
) {
4865 if (*work_done
>= budget
)
4869 skb
= buffer_info
->skb
;
4870 prefetch(skb
->data
- NET_IP_ALIGN
);
4871 buffer_info
->skb
= NULL
;
4874 if (i
== rx_ring
->count
)
4876 next_rxd
= E1000_RX_DESC_ADV(*rx_ring
, i
);
4878 next_buffer
= &rx_ring
->buffer_info
[i
];
4880 length
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
4884 if (buffer_info
->dma
) {
4885 pci_unmap_single(pdev
, buffer_info
->dma
,
4886 rx_ring
->rx_buffer_len
,
4887 PCI_DMA_FROMDEVICE
);
4888 buffer_info
->dma
= 0;
4889 if (rx_ring
->rx_buffer_len
>= IGB_RXBUFFER_1024
) {
4890 skb_put(skb
, length
);
4893 skb_put(skb
, igb_get_hlen(rx_ring
, rx_desc
));
4897 pci_unmap_page(pdev
, buffer_info
->page_dma
,
4898 PAGE_SIZE
/ 2, PCI_DMA_FROMDEVICE
);
4899 buffer_info
->page_dma
= 0;
4901 skb_fill_page_desc(skb
, skb_shinfo(skb
)->nr_frags
++,
4903 buffer_info
->page_offset
,
4906 if (page_count(buffer_info
->page
) != 1)
4907 buffer_info
->page
= NULL
;
4909 get_page(buffer_info
->page
);
4912 skb
->data_len
+= length
;
4914 skb
->truesize
+= length
;
4917 if (!(staterr
& E1000_RXD_STAT_EOP
)) {
4918 buffer_info
->skb
= next_buffer
->skb
;
4919 buffer_info
->dma
= next_buffer
->dma
;
4920 next_buffer
->skb
= skb
;
4921 next_buffer
->dma
= 0;
4926 * If this bit is set, then the RX registers contain
4927 * the time stamp. No other packet will be time
4928 * stamped until we read these registers, so read the
4929 * registers to make them available again. Because
4930 * only one packet can be time stamped at a time, we
4931 * know that the register values must belong to this
4932 * one here and therefore we don't need to compare
4933 * any of the additional attributes stored for it.
4935 * If nothing went wrong, then it should have a
4936 * skb_shared_tx that we can turn into a
4937 * skb_shared_hwtstamps.
4939 * TODO: can time stamping be triggered (thus locking
4940 * the registers) without the packet reaching this point
4941 * here? In that case RX time stamping would get stuck.
4943 * TODO: in "time stamp all packets" mode this bit is
4944 * not set. Need a global flag for this mode and then
4945 * always read the registers. Cannot be done without
4948 if (unlikely(staterr
& E1000_RXD_STAT_TS
)) {
4951 struct skb_shared_hwtstamps
*shhwtstamps
=
4954 WARN(!(rd32(E1000_TSYNCRXCTL
) & E1000_TSYNCRXCTL_VALID
),
4955 "igb: no RX time stamp available for time stamped packet");
4956 regval
= rd32(E1000_RXSTMPL
);
4957 regval
|= (u64
)rd32(E1000_RXSTMPH
) << 32;
4958 ns
= timecounter_cyc2time(&adapter
->clock
, regval
);
4959 timecompare_update(&adapter
->compare
, ns
);
4960 memset(shhwtstamps
, 0, sizeof(*shhwtstamps
));
4961 shhwtstamps
->hwtstamp
= ns_to_ktime(ns
);
4962 shhwtstamps
->syststamp
=
4963 timecompare_transform(&adapter
->compare
, ns
);
4966 if (staterr
& E1000_RXDEXT_ERR_FRAME_ERR_MASK
) {
4967 dev_kfree_skb_irq(skb
);
4971 total_bytes
+= skb
->len
;
4974 igb_rx_checksum_adv(rx_ring
, staterr
, skb
);
4976 skb
->protocol
= eth_type_trans(skb
, netdev
);
4977 skb_record_rx_queue(skb
, rx_ring
->queue_index
);
4979 vlan_tag
= ((staterr
& E1000_RXD_STAT_VP
) ?
4980 le16_to_cpu(rx_desc
->wb
.upper
.vlan
) : 0);
4982 igb_receive_skb(q_vector
, skb
, vlan_tag
);
4985 rx_desc
->wb
.upper
.status_error
= 0;
4987 /* return some buffers to hardware, one at a time is too slow */
4988 if (cleaned_count
>= IGB_RX_BUFFER_WRITE
) {
4989 igb_alloc_rx_buffers_adv(rx_ring
, cleaned_count
);
4993 /* use prefetched values */
4995 buffer_info
= next_buffer
;
4996 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
4999 rx_ring
->next_to_clean
= i
;
5000 cleaned_count
= igb_desc_unused(rx_ring
);
5003 igb_alloc_rx_buffers_adv(rx_ring
, cleaned_count
);
5005 rx_ring
->total_packets
+= total_packets
;
5006 rx_ring
->total_bytes
+= total_bytes
;
5007 rx_ring
->rx_stats
.packets
+= total_packets
;
5008 rx_ring
->rx_stats
.bytes
+= total_bytes
;
5009 netdev
->stats
.rx_bytes
+= total_bytes
;
5010 netdev
->stats
.rx_packets
+= total_packets
;
5015 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
5016 * @adapter: address of board private structure
5018 static void igb_alloc_rx_buffers_adv(struct igb_ring
*rx_ring
,
5021 struct igb_adapter
*adapter
= rx_ring
->q_vector
->adapter
;
5022 struct net_device
*netdev
= adapter
->netdev
;
5023 union e1000_adv_rx_desc
*rx_desc
;
5024 struct igb_buffer
*buffer_info
;
5025 struct sk_buff
*skb
;
5029 i
= rx_ring
->next_to_use
;
5030 buffer_info
= &rx_ring
->buffer_info
[i
];
5032 bufsz
= rx_ring
->rx_buffer_len
;
5034 while (cleaned_count
--) {
5035 rx_desc
= E1000_RX_DESC_ADV(*rx_ring
, i
);
5037 if ((bufsz
< IGB_RXBUFFER_1024
) && !buffer_info
->page_dma
) {
5038 if (!buffer_info
->page
) {
5039 buffer_info
->page
= alloc_page(GFP_ATOMIC
);
5040 if (!buffer_info
->page
) {
5041 rx_ring
->rx_stats
.alloc_failed
++;
5044 buffer_info
->page_offset
= 0;
5046 buffer_info
->page_offset
^= PAGE_SIZE
/ 2;
5048 buffer_info
->page_dma
=
5049 pci_map_page(rx_ring
->pdev
, buffer_info
->page
,
5050 buffer_info
->page_offset
,
5052 PCI_DMA_FROMDEVICE
);
5055 if (!buffer_info
->skb
) {
5056 skb
= netdev_alloc_skb_ip_align(netdev
, bufsz
);
5058 rx_ring
->rx_stats
.alloc_failed
++;
5062 buffer_info
->skb
= skb
;
5063 buffer_info
->dma
= pci_map_single(rx_ring
->pdev
,
5066 PCI_DMA_FROMDEVICE
);
5068 /* Refresh the desc even if buffer_addrs didn't change because
5069 * each write-back erases this info. */
5070 if (bufsz
< IGB_RXBUFFER_1024
) {
5071 rx_desc
->read
.pkt_addr
=
5072 cpu_to_le64(buffer_info
->page_dma
);
5073 rx_desc
->read
.hdr_addr
= cpu_to_le64(buffer_info
->dma
);
5075 rx_desc
->read
.pkt_addr
=
5076 cpu_to_le64(buffer_info
->dma
);
5077 rx_desc
->read
.hdr_addr
= 0;
5081 if (i
== rx_ring
->count
)
5083 buffer_info
= &rx_ring
->buffer_info
[i
];
5087 if (rx_ring
->next_to_use
!= i
) {
5088 rx_ring
->next_to_use
= i
;
5090 i
= (rx_ring
->count
- 1);
5094 /* Force memory writes to complete before letting h/w
5095 * know there are new descriptors to fetch. (Only
5096 * applicable for weak-ordered memory model archs,
5097 * such as IA-64). */
5099 writel(i
, rx_ring
->tail
);
5109 static int igb_mii_ioctl(struct net_device
*netdev
, struct ifreq
*ifr
, int cmd
)
5111 struct igb_adapter
*adapter
= netdev_priv(netdev
);
5112 struct mii_ioctl_data
*data
= if_mii(ifr
);
5114 if (adapter
->hw
.phy
.media_type
!= e1000_media_type_copper
)
5119 data
->phy_id
= adapter
->hw
.phy
.addr
;
5122 if (igb_read_phy_reg(&adapter
->hw
, data
->reg_num
& 0x1F,
5134 * igb_hwtstamp_ioctl - control hardware time stamping
5139 * Outgoing time stamping can be enabled and disabled. Play nice and
5140 * disable it when requested, although it shouldn't case any overhead
5141 * when no packet needs it. At most one packet in the queue may be
5142 * marked for time stamping, otherwise it would be impossible to tell
5143 * for sure to which packet the hardware time stamp belongs.
5145 * Incoming time stamping has to be configured via the hardware
5146 * filters. Not all combinations are supported, in particular event
5147 * type has to be specified. Matching the kind of event packet is
5148 * not supported, with the exception of "all V2 events regardless of
5152 static int igb_hwtstamp_ioctl(struct net_device
*netdev
,
5153 struct ifreq
*ifr
, int cmd
)
5155 struct igb_adapter
*adapter
= netdev_priv(netdev
);
5156 struct e1000_hw
*hw
= &adapter
->hw
;
5157 struct hwtstamp_config config
;
5158 u32 tsync_tx_ctl_bit
= E1000_TSYNCTXCTL_ENABLED
;
5159 u32 tsync_rx_ctl_bit
= E1000_TSYNCRXCTL_ENABLED
;
5160 u32 tsync_rx_ctl_type
= 0;
5161 u32 tsync_rx_cfg
= 0;
5164 short port
= 319; /* PTP */
5167 if (copy_from_user(&config
, ifr
->ifr_data
, sizeof(config
)))
5170 /* reserved for future extensions */
5174 switch (config
.tx_type
) {
5175 case HWTSTAMP_TX_OFF
:
5176 tsync_tx_ctl_bit
= 0;
5178 case HWTSTAMP_TX_ON
:
5179 tsync_tx_ctl_bit
= E1000_TSYNCTXCTL_ENABLED
;
5185 switch (config
.rx_filter
) {
5186 case HWTSTAMP_FILTER_NONE
:
5187 tsync_rx_ctl_bit
= 0;
5189 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
5190 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
5191 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT
:
5192 case HWTSTAMP_FILTER_ALL
:
5194 * register TSYNCRXCFG must be set, therefore it is not
5195 * possible to time stamp both Sync and Delay_Req messages
5196 * => fall back to time stamping all packets
5198 tsync_rx_ctl_type
= E1000_TSYNCRXCTL_TYPE_ALL
;
5199 config
.rx_filter
= HWTSTAMP_FILTER_ALL
;
5201 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
5202 tsync_rx_ctl_type
= E1000_TSYNCRXCTL_TYPE_L4_V1
;
5203 tsync_rx_cfg
= E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE
;
5206 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
5207 tsync_rx_ctl_type
= E1000_TSYNCRXCTL_TYPE_L4_V1
;
5208 tsync_rx_cfg
= E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE
;
5211 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC
:
5212 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
5213 tsync_rx_ctl_type
= E1000_TSYNCRXCTL_TYPE_L2_L4_V2
;
5214 tsync_rx_cfg
= E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE
;
5217 config
.rx_filter
= HWTSTAMP_FILTER_SOME
;
5219 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ
:
5220 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
5221 tsync_rx_ctl_type
= E1000_TSYNCRXCTL_TYPE_L2_L4_V2
;
5222 tsync_rx_cfg
= E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE
;
5225 config
.rx_filter
= HWTSTAMP_FILTER_SOME
;
5227 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
5228 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
5229 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
5230 tsync_rx_ctl_type
= E1000_TSYNCRXCTL_TYPE_EVENT_V2
;
5231 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_EVENT
;
5238 /* enable/disable TX */
5239 regval
= rd32(E1000_TSYNCTXCTL
);
5240 regval
= (regval
& ~E1000_TSYNCTXCTL_ENABLED
) | tsync_tx_ctl_bit
;
5241 wr32(E1000_TSYNCTXCTL
, regval
);
5243 /* enable/disable RX, define which PTP packets are time stamped */
5244 regval
= rd32(E1000_TSYNCRXCTL
);
5245 regval
= (regval
& ~E1000_TSYNCRXCTL_ENABLED
) | tsync_rx_ctl_bit
;
5246 regval
= (regval
& ~0xE) | tsync_rx_ctl_type
;
5247 wr32(E1000_TSYNCRXCTL
, regval
);
5248 wr32(E1000_TSYNCRXCFG
, tsync_rx_cfg
);
5251 * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
5252 * (Ethertype to filter on)
5253 * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
5254 * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
5256 wr32(E1000_ETQF0
, is_l2
? 0x440088f7 : 0);
5258 /* L4 Queue Filter[0]: only filter by source and destination port */
5259 wr32(E1000_SPQF0
, htons(port
));
5260 wr32(E1000_IMIREXT(0), is_l4
?
5261 ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
5262 wr32(E1000_IMIR(0), is_l4
?
5264 | (0<<16) /* immediate interrupt disabled */
5265 | 0 /* (1<<17) bit cleared: do not bypass
5266 destination port check */)
5268 wr32(E1000_FTQF0
, is_l4
?
5270 | (1<<15) /* VF not compared */
5271 | (1<<27) /* Enable Timestamping */
5272 | (7<<28) /* only source port filter enabled,
5273 source/target address and protocol
5275 : ((1<<15) | (15<<28) /* all mask bits set = filter not
5280 adapter
->hwtstamp_config
= config
;
5282 /* clear TX/RX time stamp registers, just to be sure */
5283 regval
= rd32(E1000_TXSTMPH
);
5284 regval
= rd32(E1000_RXSTMPH
);
5286 return copy_to_user(ifr
->ifr_data
, &config
, sizeof(config
)) ?
5296 static int igb_ioctl(struct net_device
*netdev
, struct ifreq
*ifr
, int cmd
)
5302 return igb_mii_ioctl(netdev
, ifr
, cmd
);
5304 return igb_hwtstamp_ioctl(netdev
, ifr
, cmd
);
5310 s32
igb_read_pcie_cap_reg(struct e1000_hw
*hw
, u32 reg
, u16
*value
)
5312 struct igb_adapter
*adapter
= hw
->back
;
5315 cap_offset
= pci_find_capability(adapter
->pdev
, PCI_CAP_ID_EXP
);
5317 return -E1000_ERR_CONFIG
;
5319 pci_read_config_word(adapter
->pdev
, cap_offset
+ reg
, value
);
5324 s32
igb_write_pcie_cap_reg(struct e1000_hw
*hw
, u32 reg
, u16
*value
)
5326 struct igb_adapter
*adapter
= hw
->back
;
5329 cap_offset
= pci_find_capability(adapter
->pdev
, PCI_CAP_ID_EXP
);
5331 return -E1000_ERR_CONFIG
;
5333 pci_write_config_word(adapter
->pdev
, cap_offset
+ reg
, *value
);
5338 static void igb_vlan_rx_register(struct net_device
*netdev
,
5339 struct vlan_group
*grp
)
5341 struct igb_adapter
*adapter
= netdev_priv(netdev
);
5342 struct e1000_hw
*hw
= &adapter
->hw
;
5345 igb_irq_disable(adapter
);
5346 adapter
->vlgrp
= grp
;
5349 /* enable VLAN tag insert/strip */
5350 ctrl
= rd32(E1000_CTRL
);
5351 ctrl
|= E1000_CTRL_VME
;
5352 wr32(E1000_CTRL
, ctrl
);
5354 /* enable VLAN receive filtering */
5355 rctl
= rd32(E1000_RCTL
);
5356 rctl
&= ~E1000_RCTL_CFIEN
;
5357 wr32(E1000_RCTL
, rctl
);
5358 igb_update_mng_vlan(adapter
);
5360 /* disable VLAN tag insert/strip */
5361 ctrl
= rd32(E1000_CTRL
);
5362 ctrl
&= ~E1000_CTRL_VME
;
5363 wr32(E1000_CTRL
, ctrl
);
5365 if (adapter
->mng_vlan_id
!= (u16
)IGB_MNG_VLAN_NONE
) {
5366 igb_vlan_rx_kill_vid(netdev
, adapter
->mng_vlan_id
);
5367 adapter
->mng_vlan_id
= IGB_MNG_VLAN_NONE
;
5371 igb_rlpml_set(adapter
);
5373 if (!test_bit(__IGB_DOWN
, &adapter
->state
))
5374 igb_irq_enable(adapter
);
5377 static void igb_vlan_rx_add_vid(struct net_device
*netdev
, u16 vid
)
5379 struct igb_adapter
*adapter
= netdev_priv(netdev
);
5380 struct e1000_hw
*hw
= &adapter
->hw
;
5381 int pf_id
= adapter
->vfs_allocated_count
;
5383 if ((hw
->mng_cookie
.status
&
5384 E1000_MNG_DHCP_COOKIE_STATUS_VLAN
) &&
5385 (vid
== adapter
->mng_vlan_id
))
5388 /* add vid to vlvf if sr-iov is enabled,
5389 * if that fails add directly to filter table */
5390 if (igb_vlvf_set(adapter
, vid
, true, pf_id
))
5391 igb_vfta_set(hw
, vid
, true);
5395 static void igb_vlan_rx_kill_vid(struct net_device
*netdev
, u16 vid
)
5397 struct igb_adapter
*adapter
= netdev_priv(netdev
);
5398 struct e1000_hw
*hw
= &adapter
->hw
;
5399 int pf_id
= adapter
->vfs_allocated_count
;
5401 igb_irq_disable(adapter
);
5402 vlan_group_set_device(adapter
->vlgrp
, vid
, NULL
);
5404 if (!test_bit(__IGB_DOWN
, &adapter
->state
))
5405 igb_irq_enable(adapter
);
5407 if ((adapter
->hw
.mng_cookie
.status
&
5408 E1000_MNG_DHCP_COOKIE_STATUS_VLAN
) &&
5409 (vid
== adapter
->mng_vlan_id
)) {
5410 /* release control to f/w */
5411 igb_release_hw_control(adapter
);
5415 /* remove vid from vlvf if sr-iov is enabled,
5416 * if not in vlvf remove from vfta */
5417 if (igb_vlvf_set(adapter
, vid
, false, pf_id
))
5418 igb_vfta_set(hw
, vid
, false);
5421 static void igb_restore_vlan(struct igb_adapter
*adapter
)
5423 igb_vlan_rx_register(adapter
->netdev
, adapter
->vlgrp
);
5425 if (adapter
->vlgrp
) {
5427 for (vid
= 0; vid
< VLAN_GROUP_ARRAY_LEN
; vid
++) {
5428 if (!vlan_group_get_device(adapter
->vlgrp
, vid
))
5430 igb_vlan_rx_add_vid(adapter
->netdev
, vid
);
5435 int igb_set_spd_dplx(struct igb_adapter
*adapter
, u16 spddplx
)
5437 struct e1000_mac_info
*mac
= &adapter
->hw
.mac
;
5442 case SPEED_10
+ DUPLEX_HALF
:
5443 mac
->forced_speed_duplex
= ADVERTISE_10_HALF
;
5445 case SPEED_10
+ DUPLEX_FULL
:
5446 mac
->forced_speed_duplex
= ADVERTISE_10_FULL
;
5448 case SPEED_100
+ DUPLEX_HALF
:
5449 mac
->forced_speed_duplex
= ADVERTISE_100_HALF
;
5451 case SPEED_100
+ DUPLEX_FULL
:
5452 mac
->forced_speed_duplex
= ADVERTISE_100_FULL
;
5454 case SPEED_1000
+ DUPLEX_FULL
:
5456 adapter
->hw
.phy
.autoneg_advertised
= ADVERTISE_1000_FULL
;
5458 case SPEED_1000
+ DUPLEX_HALF
: /* not supported */
5460 dev_err(&adapter
->pdev
->dev
,
5461 "Unsupported Speed/Duplex configuration\n");
5467 static int __igb_shutdown(struct pci_dev
*pdev
, bool *enable_wake
)
5469 struct net_device
*netdev
= pci_get_drvdata(pdev
);
5470 struct igb_adapter
*adapter
= netdev_priv(netdev
);
5471 struct e1000_hw
*hw
= &adapter
->hw
;
5472 u32 ctrl
, rctl
, status
;
5473 u32 wufc
= adapter
->wol
;
5478 netif_device_detach(netdev
);
5480 if (netif_running(netdev
))
5483 igb_clear_interrupt_scheme(adapter
);
5486 retval
= pci_save_state(pdev
);
5491 status
= rd32(E1000_STATUS
);
5492 if (status
& E1000_STATUS_LU
)
5493 wufc
&= ~E1000_WUFC_LNKC
;
5496 igb_setup_rctl(adapter
);
5497 igb_set_rx_mode(netdev
);
5499 /* turn on all-multi mode if wake on multicast is enabled */
5500 if (wufc
& E1000_WUFC_MC
) {
5501 rctl
= rd32(E1000_RCTL
);
5502 rctl
|= E1000_RCTL_MPE
;
5503 wr32(E1000_RCTL
, rctl
);
5506 ctrl
= rd32(E1000_CTRL
);
5507 /* advertise wake from D3Cold */
5508 #define E1000_CTRL_ADVD3WUC 0x00100000
5509 /* phy power management enable */
5510 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5511 ctrl
|= E1000_CTRL_ADVD3WUC
;
5512 wr32(E1000_CTRL
, ctrl
);
5514 /* Allow time for pending master requests to run */
5515 igb_disable_pcie_master(&adapter
->hw
);
5517 wr32(E1000_WUC
, E1000_WUC_PME_EN
);
5518 wr32(E1000_WUFC
, wufc
);
5521 wr32(E1000_WUFC
, 0);
5524 *enable_wake
= wufc
|| adapter
->en_mng_pt
;
5526 igb_shutdown_serdes_link_82575(hw
);
5528 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5529 * would have already happened in close and is redundant. */
5530 igb_release_hw_control(adapter
);
5532 pci_disable_device(pdev
);
5538 static int igb_suspend(struct pci_dev
*pdev
, pm_message_t state
)
5543 retval
= __igb_shutdown(pdev
, &wake
);
5548 pci_prepare_to_sleep(pdev
);
5550 pci_wake_from_d3(pdev
, false);
5551 pci_set_power_state(pdev
, PCI_D3hot
);
5557 static int igb_resume(struct pci_dev
*pdev
)
5559 struct net_device
*netdev
= pci_get_drvdata(pdev
);
5560 struct igb_adapter
*adapter
= netdev_priv(netdev
);
5561 struct e1000_hw
*hw
= &adapter
->hw
;
5564 pci_set_power_state(pdev
, PCI_D0
);
5565 pci_restore_state(pdev
);
5567 err
= pci_enable_device_mem(pdev
);
5570 "igb: Cannot enable PCI device from suspend\n");
5573 pci_set_master(pdev
);
5575 pci_enable_wake(pdev
, PCI_D3hot
, 0);
5576 pci_enable_wake(pdev
, PCI_D3cold
, 0);
5578 if (igb_init_interrupt_scheme(adapter
)) {
5579 dev_err(&pdev
->dev
, "Unable to allocate memory for queues\n");
5583 /* e1000_power_up_phy(adapter); */
5587 /* let the f/w know that the h/w is now under the control of the
5589 igb_get_hw_control(adapter
);
5591 wr32(E1000_WUS
, ~0);
5593 if (netif_running(netdev
)) {
5594 err
= igb_open(netdev
);
5599 netif_device_attach(netdev
);
5605 static void igb_shutdown(struct pci_dev
*pdev
)
5609 __igb_shutdown(pdev
, &wake
);
5611 if (system_state
== SYSTEM_POWER_OFF
) {
5612 pci_wake_from_d3(pdev
, wake
);
5613 pci_set_power_state(pdev
, PCI_D3hot
);
5617 #ifdef CONFIG_NET_POLL_CONTROLLER
5619 * Polling 'interrupt' - used by things like netconsole to send skbs
5620 * without having to re-enable interrupts. It's not called while
5621 * the interrupt routine is executing.
5623 static void igb_netpoll(struct net_device
*netdev
)
5625 struct igb_adapter
*adapter
= netdev_priv(netdev
);
5626 struct e1000_hw
*hw
= &adapter
->hw
;
5629 if (!adapter
->msix_entries
) {
5630 struct igb_q_vector
*q_vector
= adapter
->q_vector
[0];
5631 igb_irq_disable(adapter
);
5632 napi_schedule(&q_vector
->napi
);
5636 for (i
= 0; i
< adapter
->num_q_vectors
; i
++) {
5637 struct igb_q_vector
*q_vector
= adapter
->q_vector
[i
];
5638 wr32(E1000_EIMC
, q_vector
->eims_value
);
5639 napi_schedule(&q_vector
->napi
);
5642 #endif /* CONFIG_NET_POLL_CONTROLLER */
5645 * igb_io_error_detected - called when PCI error is detected
5646 * @pdev: Pointer to PCI device
5647 * @state: The current pci connection state
5649 * This function is called after a PCI bus error affecting
5650 * this device has been detected.
5652 static pci_ers_result_t
igb_io_error_detected(struct pci_dev
*pdev
,
5653 pci_channel_state_t state
)
5655 struct net_device
*netdev
= pci_get_drvdata(pdev
);
5656 struct igb_adapter
*adapter
= netdev_priv(netdev
);
5658 netif_device_detach(netdev
);
5660 if (state
== pci_channel_io_perm_failure
)
5661 return PCI_ERS_RESULT_DISCONNECT
;
5663 if (netif_running(netdev
))
5665 pci_disable_device(pdev
);
5667 /* Request a slot slot reset. */
5668 return PCI_ERS_RESULT_NEED_RESET
;
5672 * igb_io_slot_reset - called after the pci bus has been reset.
5673 * @pdev: Pointer to PCI device
5675 * Restart the card from scratch, as if from a cold-boot. Implementation
5676 * resembles the first-half of the igb_resume routine.
5678 static pci_ers_result_t
igb_io_slot_reset(struct pci_dev
*pdev
)
5680 struct net_device
*netdev
= pci_get_drvdata(pdev
);
5681 struct igb_adapter
*adapter
= netdev_priv(netdev
);
5682 struct e1000_hw
*hw
= &adapter
->hw
;
5683 pci_ers_result_t result
;
5686 if (pci_enable_device_mem(pdev
)) {
5688 "Cannot re-enable PCI device after reset.\n");
5689 result
= PCI_ERS_RESULT_DISCONNECT
;
5691 pci_set_master(pdev
);
5692 pci_restore_state(pdev
);
5694 pci_enable_wake(pdev
, PCI_D3hot
, 0);
5695 pci_enable_wake(pdev
, PCI_D3cold
, 0);
5698 wr32(E1000_WUS
, ~0);
5699 result
= PCI_ERS_RESULT_RECOVERED
;
5702 err
= pci_cleanup_aer_uncorrect_error_status(pdev
);
5704 dev_err(&pdev
->dev
, "pci_cleanup_aer_uncorrect_error_status "
5705 "failed 0x%0x\n", err
);
5706 /* non-fatal, continue */
5713 * igb_io_resume - called when traffic can start flowing again.
5714 * @pdev: Pointer to PCI device
5716 * This callback is called when the error recovery driver tells us that
5717 * its OK to resume normal operation. Implementation resembles the
5718 * second-half of the igb_resume routine.
5720 static void igb_io_resume(struct pci_dev
*pdev
)
5722 struct net_device
*netdev
= pci_get_drvdata(pdev
);
5723 struct igb_adapter
*adapter
= netdev_priv(netdev
);
5725 if (netif_running(netdev
)) {
5726 if (igb_up(adapter
)) {
5727 dev_err(&pdev
->dev
, "igb_up failed after reset\n");
5732 netif_device_attach(netdev
);
5734 /* let the f/w know that the h/w is now under the control of the
5736 igb_get_hw_control(adapter
);
5739 static void igb_rar_set_qsel(struct igb_adapter
*adapter
, u8
*addr
, u32 index
,
5742 u32 rar_low
, rar_high
;
5743 struct e1000_hw
*hw
= &adapter
->hw
;
5745 /* HW expects these in little endian so we reverse the byte order
5746 * from network order (big endian) to little endian
5748 rar_low
= ((u32
) addr
[0] | ((u32
) addr
[1] << 8) |
5749 ((u32
) addr
[2] << 16) | ((u32
) addr
[3] << 24));
5750 rar_high
= ((u32
) addr
[4] | ((u32
) addr
[5] << 8));
5752 /* Indicate to hardware the Address is Valid. */
5753 rar_high
|= E1000_RAH_AV
;
5755 if (hw
->mac
.type
== e1000_82575
)
5756 rar_high
|= E1000_RAH_POOL_1
* qsel
;
5758 rar_high
|= E1000_RAH_POOL_1
<< qsel
;
5760 wr32(E1000_RAL(index
), rar_low
);
5762 wr32(E1000_RAH(index
), rar_high
);
5766 static int igb_set_vf_mac(struct igb_adapter
*adapter
,
5767 int vf
, unsigned char *mac_addr
)
5769 struct e1000_hw
*hw
= &adapter
->hw
;
5770 /* VF MAC addresses start at end of receive addresses and moves
5771 * torwards the first, as a result a collision should not be possible */
5772 int rar_entry
= hw
->mac
.rar_entry_count
- (vf
+ 1);
5774 memcpy(adapter
->vf_data
[vf
].vf_mac_addresses
, mac_addr
, ETH_ALEN
);
5776 igb_rar_set_qsel(adapter
, mac_addr
, rar_entry
, vf
);
5781 static void igb_vmm_control(struct igb_adapter
*adapter
)
5783 struct e1000_hw
*hw
= &adapter
->hw
;
5786 if (!adapter
->vfs_allocated_count
)
5789 /* VF's need PF reset indication before they
5790 * can send/receive mail */
5791 reg_data
= rd32(E1000_CTRL_EXT
);
5792 reg_data
|= E1000_CTRL_EXT_PFRSTD
;
5793 wr32(E1000_CTRL_EXT
, reg_data
);
5795 igb_vmdq_set_loopback_pf(hw
, true);
5796 igb_vmdq_set_replication_pf(hw
, true);