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Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[deliverable/linux.git] / drivers / net / igb / igb_main.c
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/module.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/vmalloc.h>
32 #include <linux/pagemap.h>
33 #include <linux/netdevice.h>
34 #include <linux/ipv6.h>
35 #include <net/checksum.h>
36 #include <net/ip6_checksum.h>
37 #include <linux/mii.h>
38 #include <linux/ethtool.h>
39 #include <linux/if_vlan.h>
40 #include <linux/pci.h>
41 #include <linux/delay.h>
42 #include <linux/interrupt.h>
43 #include <linux/if_ether.h>
44
45 #include "igb.h"
46
47 #define DRV_VERSION "1.0.8-k2"
48 char igb_driver_name[] = "igb";
49 char igb_driver_version[] = DRV_VERSION;
50 static const char igb_driver_string[] =
51 "Intel(R) Gigabit Ethernet Network Driver";
52 static const char igb_copyright[] = "Copyright (c) 2007 Intel Corporation.";
53
54
55 static const struct e1000_info *igb_info_tbl[] = {
56 [board_82575] = &e1000_82575_info,
57 };
58
59 static struct pci_device_id igb_pci_tbl[] = {
60 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
61 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
62 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
63 /* required last entry */
64 {0, }
65 };
66
67 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
68
69 void igb_reset(struct igb_adapter *);
70 static int igb_setup_all_tx_resources(struct igb_adapter *);
71 static int igb_setup_all_rx_resources(struct igb_adapter *);
72 static void igb_free_all_tx_resources(struct igb_adapter *);
73 static void igb_free_all_rx_resources(struct igb_adapter *);
74 static void igb_free_tx_resources(struct igb_adapter *, struct igb_ring *);
75 static void igb_free_rx_resources(struct igb_adapter *, struct igb_ring *);
76 void igb_update_stats(struct igb_adapter *);
77 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
78 static void __devexit igb_remove(struct pci_dev *pdev);
79 static int igb_sw_init(struct igb_adapter *);
80 static int igb_open(struct net_device *);
81 static int igb_close(struct net_device *);
82 static void igb_configure_tx(struct igb_adapter *);
83 static void igb_configure_rx(struct igb_adapter *);
84 static void igb_setup_rctl(struct igb_adapter *);
85 static void igb_clean_all_tx_rings(struct igb_adapter *);
86 static void igb_clean_all_rx_rings(struct igb_adapter *);
87 static void igb_clean_tx_ring(struct igb_adapter *, struct igb_ring *);
88 static void igb_clean_rx_ring(struct igb_adapter *, struct igb_ring *);
89 static void igb_set_multi(struct net_device *);
90 static void igb_update_phy_info(unsigned long);
91 static void igb_watchdog(unsigned long);
92 static void igb_watchdog_task(struct work_struct *);
93 static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
94 struct igb_ring *);
95 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
96 static struct net_device_stats *igb_get_stats(struct net_device *);
97 static int igb_change_mtu(struct net_device *, int);
98 static int igb_set_mac(struct net_device *, void *);
99 static irqreturn_t igb_intr(int irq, void *);
100 static irqreturn_t igb_intr_msi(int irq, void *);
101 static irqreturn_t igb_msix_other(int irq, void *);
102 static irqreturn_t igb_msix_rx(int irq, void *);
103 static irqreturn_t igb_msix_tx(int irq, void *);
104 static int igb_clean_rx_ring_msix(struct napi_struct *, int);
105 static bool igb_clean_tx_irq(struct igb_adapter *, struct igb_ring *);
106 static int igb_clean(struct napi_struct *, int);
107 static bool igb_clean_rx_irq_adv(struct igb_adapter *,
108 struct igb_ring *, int *, int);
109 static void igb_alloc_rx_buffers_adv(struct igb_adapter *,
110 struct igb_ring *, int);
111 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
112 static void igb_tx_timeout(struct net_device *);
113 static void igb_reset_task(struct work_struct *);
114 static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
115 static void igb_vlan_rx_add_vid(struct net_device *, u16);
116 static void igb_vlan_rx_kill_vid(struct net_device *, u16);
117 static void igb_restore_vlan(struct igb_adapter *);
118
119 static int igb_suspend(struct pci_dev *, pm_message_t);
120 #ifdef CONFIG_PM
121 static int igb_resume(struct pci_dev *);
122 #endif
123 static void igb_shutdown(struct pci_dev *);
124
125 #ifdef CONFIG_NET_POLL_CONTROLLER
126 /* for netdump / net console */
127 static void igb_netpoll(struct net_device *);
128 #endif
129
130 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
131 pci_channel_state_t);
132 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
133 static void igb_io_resume(struct pci_dev *);
134
135 static struct pci_error_handlers igb_err_handler = {
136 .error_detected = igb_io_error_detected,
137 .slot_reset = igb_io_slot_reset,
138 .resume = igb_io_resume,
139 };
140
141
142 static struct pci_driver igb_driver = {
143 .name = igb_driver_name,
144 .id_table = igb_pci_tbl,
145 .probe = igb_probe,
146 .remove = __devexit_p(igb_remove),
147 #ifdef CONFIG_PM
148 /* Power Managment Hooks */
149 .suspend = igb_suspend,
150 .resume = igb_resume,
151 #endif
152 .shutdown = igb_shutdown,
153 .err_handler = &igb_err_handler
154 };
155
156 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
157 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
158 MODULE_LICENSE("GPL");
159 MODULE_VERSION(DRV_VERSION);
160
161 #ifdef DEBUG
162 /**
163 * igb_get_hw_dev_name - return device name string
164 * used by hardware layer to print debugging information
165 **/
166 char *igb_get_hw_dev_name(struct e1000_hw *hw)
167 {
168 struct igb_adapter *adapter = hw->back;
169 return adapter->netdev->name;
170 }
171 #endif
172
173 /**
174 * igb_init_module - Driver Registration Routine
175 *
176 * igb_init_module is the first routine called when the driver is
177 * loaded. All it does is register with the PCI subsystem.
178 **/
179 static int __init igb_init_module(void)
180 {
181 int ret;
182 printk(KERN_INFO "%s - version %s\n",
183 igb_driver_string, igb_driver_version);
184
185 printk(KERN_INFO "%s\n", igb_copyright);
186
187 ret = pci_register_driver(&igb_driver);
188 return ret;
189 }
190
191 module_init(igb_init_module);
192
193 /**
194 * igb_exit_module - Driver Exit Cleanup Routine
195 *
196 * igb_exit_module is called just before the driver is removed
197 * from memory.
198 **/
199 static void __exit igb_exit_module(void)
200 {
201 pci_unregister_driver(&igb_driver);
202 }
203
204 module_exit(igb_exit_module);
205
206 /**
207 * igb_alloc_queues - Allocate memory for all rings
208 * @adapter: board private structure to initialize
209 *
210 * We allocate one ring per queue at run-time since we don't know the
211 * number of queues at compile-time.
212 **/
213 static int igb_alloc_queues(struct igb_adapter *adapter)
214 {
215 int i;
216
217 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
218 sizeof(struct igb_ring), GFP_KERNEL);
219 if (!adapter->tx_ring)
220 return -ENOMEM;
221
222 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
223 sizeof(struct igb_ring), GFP_KERNEL);
224 if (!adapter->rx_ring) {
225 kfree(adapter->tx_ring);
226 return -ENOMEM;
227 }
228
229 for (i = 0; i < adapter->num_rx_queues; i++) {
230 struct igb_ring *ring = &(adapter->rx_ring[i]);
231 ring->adapter = adapter;
232 ring->itr_register = E1000_ITR;
233
234 if (!ring->napi.poll)
235 netif_napi_add(adapter->netdev, &ring->napi, igb_clean,
236 adapter->napi.weight /
237 adapter->num_rx_queues);
238 }
239 return 0;
240 }
241
242 #define IGB_N0_QUEUE -1
243 static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
244 int tx_queue, int msix_vector)
245 {
246 u32 msixbm = 0;
247 struct e1000_hw *hw = &adapter->hw;
248 /* The 82575 assigns vectors using a bitmask, which matches the
249 bitmask for the EICR/EIMS/EIMC registers. To assign one
250 or more queues to a vector, we write the appropriate bits
251 into the MSIXBM register for that vector. */
252 if (rx_queue > IGB_N0_QUEUE) {
253 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
254 adapter->rx_ring[rx_queue].eims_value = msixbm;
255 }
256 if (tx_queue > IGB_N0_QUEUE) {
257 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
258 adapter->tx_ring[tx_queue].eims_value =
259 E1000_EICR_TX_QUEUE0 << tx_queue;
260 }
261 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
262 }
263
264 /**
265 * igb_configure_msix - Configure MSI-X hardware
266 *
267 * igb_configure_msix sets up the hardware to properly
268 * generate MSI-X interrupts.
269 **/
270 static void igb_configure_msix(struct igb_adapter *adapter)
271 {
272 u32 tmp;
273 int i, vector = 0;
274 struct e1000_hw *hw = &adapter->hw;
275
276 adapter->eims_enable_mask = 0;
277
278 for (i = 0; i < adapter->num_tx_queues; i++) {
279 struct igb_ring *tx_ring = &adapter->tx_ring[i];
280 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
281 adapter->eims_enable_mask |= tx_ring->eims_value;
282 if (tx_ring->itr_val)
283 writel(1000000000 / (tx_ring->itr_val * 256),
284 hw->hw_addr + tx_ring->itr_register);
285 else
286 writel(1, hw->hw_addr + tx_ring->itr_register);
287 }
288
289 for (i = 0; i < adapter->num_rx_queues; i++) {
290 struct igb_ring *rx_ring = &adapter->rx_ring[i];
291 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
292 adapter->eims_enable_mask |= rx_ring->eims_value;
293 if (rx_ring->itr_val)
294 writel(1000000000 / (rx_ring->itr_val * 256),
295 hw->hw_addr + rx_ring->itr_register);
296 else
297 writel(1, hw->hw_addr + rx_ring->itr_register);
298 }
299
300
301 /* set vector for other causes, i.e. link changes */
302 array_wr32(E1000_MSIXBM(0), vector++,
303 E1000_EIMS_OTHER);
304
305 /* disable IAM for ICR interrupt bits */
306 wr32(E1000_IAM, 0);
307
308 tmp = rd32(E1000_CTRL_EXT);
309 /* enable MSI-X PBA support*/
310 tmp |= E1000_CTRL_EXT_PBA_CLR;
311
312 /* Auto-Mask interrupts upon ICR read. */
313 tmp |= E1000_CTRL_EXT_EIAME;
314 tmp |= E1000_CTRL_EXT_IRCA;
315
316 wr32(E1000_CTRL_EXT, tmp);
317 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
318
319 wrfl();
320 }
321
322 /**
323 * igb_request_msix - Initialize MSI-X interrupts
324 *
325 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
326 * kernel.
327 **/
328 static int igb_request_msix(struct igb_adapter *adapter)
329 {
330 struct net_device *netdev = adapter->netdev;
331 int i, err = 0, vector = 0;
332
333 vector = 0;
334
335 for (i = 0; i < adapter->num_tx_queues; i++) {
336 struct igb_ring *ring = &(adapter->tx_ring[i]);
337 sprintf(ring->name, "%s-tx%d", netdev->name, i);
338 err = request_irq(adapter->msix_entries[vector].vector,
339 &igb_msix_tx, 0, ring->name,
340 &(adapter->tx_ring[i]));
341 if (err)
342 goto out;
343 ring->itr_register = E1000_EITR(0) + (vector << 2);
344 ring->itr_val = adapter->itr;
345 vector++;
346 }
347 for (i = 0; i < adapter->num_rx_queues; i++) {
348 struct igb_ring *ring = &(adapter->rx_ring[i]);
349 if (strlen(netdev->name) < (IFNAMSIZ - 5))
350 sprintf(ring->name, "%s-rx%d", netdev->name, i);
351 else
352 memcpy(ring->name, netdev->name, IFNAMSIZ);
353 err = request_irq(adapter->msix_entries[vector].vector,
354 &igb_msix_rx, 0, ring->name,
355 &(adapter->rx_ring[i]));
356 if (err)
357 goto out;
358 ring->itr_register = E1000_EITR(0) + (vector << 2);
359 ring->itr_val = adapter->itr;
360 vector++;
361 }
362
363 err = request_irq(adapter->msix_entries[vector].vector,
364 &igb_msix_other, 0, netdev->name, netdev);
365 if (err)
366 goto out;
367
368 adapter->napi.poll = igb_clean_rx_ring_msix;
369 for (i = 0; i < adapter->num_rx_queues; i++)
370 adapter->rx_ring[i].napi.poll = adapter->napi.poll;
371 igb_configure_msix(adapter);
372 return 0;
373 out:
374 return err;
375 }
376
377 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
378 {
379 if (adapter->msix_entries) {
380 pci_disable_msix(adapter->pdev);
381 kfree(adapter->msix_entries);
382 adapter->msix_entries = NULL;
383 } else if (adapter->msi_enabled)
384 pci_disable_msi(adapter->pdev);
385 return;
386 }
387
388
389 /**
390 * igb_set_interrupt_capability - set MSI or MSI-X if supported
391 *
392 * Attempt to configure interrupts using the best available
393 * capabilities of the hardware and kernel.
394 **/
395 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
396 {
397 int err;
398 int numvecs, i;
399
400 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
401 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
402 GFP_KERNEL);
403 if (!adapter->msix_entries)
404 goto msi_only;
405
406 for (i = 0; i < numvecs; i++)
407 adapter->msix_entries[i].entry = i;
408
409 err = pci_enable_msix(adapter->pdev,
410 adapter->msix_entries,
411 numvecs);
412 if (err == 0)
413 return;
414
415 igb_reset_interrupt_capability(adapter);
416
417 /* If we can't do MSI-X, try MSI */
418 msi_only:
419 adapter->num_rx_queues = 1;
420 if (!pci_enable_msi(adapter->pdev))
421 adapter->msi_enabled = 1;
422 return;
423 }
424
425 /**
426 * igb_request_irq - initialize interrupts
427 *
428 * Attempts to configure interrupts using the best available
429 * capabilities of the hardware and kernel.
430 **/
431 static int igb_request_irq(struct igb_adapter *adapter)
432 {
433 struct net_device *netdev = adapter->netdev;
434 struct e1000_hw *hw = &adapter->hw;
435 int err = 0;
436
437 if (adapter->msix_entries) {
438 err = igb_request_msix(adapter);
439 if (!err) {
440 /* enable IAM, auto-mask,
441 * DO NOT USE EIAM or IAM in legacy mode */
442 wr32(E1000_IAM, IMS_ENABLE_MASK);
443 goto request_done;
444 }
445 /* fall back to MSI */
446 igb_reset_interrupt_capability(adapter);
447 if (!pci_enable_msi(adapter->pdev))
448 adapter->msi_enabled = 1;
449 igb_free_all_tx_resources(adapter);
450 igb_free_all_rx_resources(adapter);
451 adapter->num_rx_queues = 1;
452 igb_alloc_queues(adapter);
453 }
454 if (adapter->msi_enabled) {
455 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
456 netdev->name, netdev);
457 if (!err)
458 goto request_done;
459 /* fall back to legacy interrupts */
460 igb_reset_interrupt_capability(adapter);
461 adapter->msi_enabled = 0;
462 }
463
464 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
465 netdev->name, netdev);
466
467 if (err)
468 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
469 err);
470
471 request_done:
472 return err;
473 }
474
475 static void igb_free_irq(struct igb_adapter *adapter)
476 {
477 struct net_device *netdev = adapter->netdev;
478
479 if (adapter->msix_entries) {
480 int vector = 0, i;
481
482 for (i = 0; i < adapter->num_tx_queues; i++)
483 free_irq(adapter->msix_entries[vector++].vector,
484 &(adapter->tx_ring[i]));
485 for (i = 0; i < adapter->num_rx_queues; i++)
486 free_irq(adapter->msix_entries[vector++].vector,
487 &(adapter->rx_ring[i]));
488
489 free_irq(adapter->msix_entries[vector++].vector, netdev);
490 return;
491 }
492
493 free_irq(adapter->pdev->irq, netdev);
494 }
495
496 /**
497 * igb_irq_disable - Mask off interrupt generation on the NIC
498 * @adapter: board private structure
499 **/
500 static void igb_irq_disable(struct igb_adapter *adapter)
501 {
502 struct e1000_hw *hw = &adapter->hw;
503
504 if (adapter->msix_entries) {
505 wr32(E1000_EIMC, ~0);
506 wr32(E1000_EIAC, 0);
507 }
508 wr32(E1000_IMC, ~0);
509 wrfl();
510 synchronize_irq(adapter->pdev->irq);
511 }
512
513 /**
514 * igb_irq_enable - Enable default interrupt generation settings
515 * @adapter: board private structure
516 **/
517 static void igb_irq_enable(struct igb_adapter *adapter)
518 {
519 struct e1000_hw *hw = &adapter->hw;
520
521 if (adapter->msix_entries) {
522 wr32(E1000_EIMS,
523 adapter->eims_enable_mask);
524 wr32(E1000_EIAC,
525 adapter->eims_enable_mask);
526 wr32(E1000_IMS, E1000_IMS_LSC);
527 } else
528 wr32(E1000_IMS, IMS_ENABLE_MASK);
529 }
530
531 static void igb_update_mng_vlan(struct igb_adapter *adapter)
532 {
533 struct net_device *netdev = adapter->netdev;
534 u16 vid = adapter->hw.mng_cookie.vlan_id;
535 u16 old_vid = adapter->mng_vlan_id;
536 if (adapter->vlgrp) {
537 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
538 if (adapter->hw.mng_cookie.status &
539 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
540 igb_vlan_rx_add_vid(netdev, vid);
541 adapter->mng_vlan_id = vid;
542 } else
543 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
544
545 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
546 (vid != old_vid) &&
547 !vlan_group_get_device(adapter->vlgrp, old_vid))
548 igb_vlan_rx_kill_vid(netdev, old_vid);
549 } else
550 adapter->mng_vlan_id = vid;
551 }
552 }
553
554 /**
555 * igb_release_hw_control - release control of the h/w to f/w
556 * @adapter: address of board private structure
557 *
558 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
559 * For ASF and Pass Through versions of f/w this means that the
560 * driver is no longer loaded.
561 *
562 **/
563 static void igb_release_hw_control(struct igb_adapter *adapter)
564 {
565 struct e1000_hw *hw = &adapter->hw;
566 u32 ctrl_ext;
567
568 /* Let firmware take over control of h/w */
569 ctrl_ext = rd32(E1000_CTRL_EXT);
570 wr32(E1000_CTRL_EXT,
571 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
572 }
573
574
575 /**
576 * igb_get_hw_control - get control of the h/w from f/w
577 * @adapter: address of board private structure
578 *
579 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
580 * For ASF and Pass Through versions of f/w this means that
581 * the driver is loaded.
582 *
583 **/
584 static void igb_get_hw_control(struct igb_adapter *adapter)
585 {
586 struct e1000_hw *hw = &adapter->hw;
587 u32 ctrl_ext;
588
589 /* Let firmware know the driver has taken over */
590 ctrl_ext = rd32(E1000_CTRL_EXT);
591 wr32(E1000_CTRL_EXT,
592 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
593 }
594
595 static void igb_init_manageability(struct igb_adapter *adapter)
596 {
597 struct e1000_hw *hw = &adapter->hw;
598
599 if (adapter->en_mng_pt) {
600 u32 manc2h = rd32(E1000_MANC2H);
601 u32 manc = rd32(E1000_MANC);
602
603 /* enable receiving management packets to the host */
604 /* this will probably generate destination unreachable messages
605 * from the host OS, but the packets will be handled on SMBUS */
606 manc |= E1000_MANC_EN_MNG2HOST;
607 #define E1000_MNG2HOST_PORT_623 (1 << 5)
608 #define E1000_MNG2HOST_PORT_664 (1 << 6)
609 manc2h |= E1000_MNG2HOST_PORT_623;
610 manc2h |= E1000_MNG2HOST_PORT_664;
611 wr32(E1000_MANC2H, manc2h);
612
613 wr32(E1000_MANC, manc);
614 }
615 }
616
617 /**
618 * igb_configure - configure the hardware for RX and TX
619 * @adapter: private board structure
620 **/
621 static void igb_configure(struct igb_adapter *adapter)
622 {
623 struct net_device *netdev = adapter->netdev;
624 int i;
625
626 igb_get_hw_control(adapter);
627 igb_set_multi(netdev);
628
629 igb_restore_vlan(adapter);
630 igb_init_manageability(adapter);
631
632 igb_configure_tx(adapter);
633 igb_setup_rctl(adapter);
634 igb_configure_rx(adapter);
635 /* call IGB_DESC_UNUSED which always leaves
636 * at least 1 descriptor unused to make sure
637 * next_to_use != next_to_clean */
638 for (i = 0; i < adapter->num_rx_queues; i++) {
639 struct igb_ring *ring = &adapter->rx_ring[i];
640 igb_alloc_rx_buffers_adv(adapter, ring, IGB_DESC_UNUSED(ring));
641 }
642
643
644 adapter->tx_queue_len = netdev->tx_queue_len;
645 }
646
647
648 /**
649 * igb_up - Open the interface and prepare it to handle traffic
650 * @adapter: board private structure
651 **/
652
653 int igb_up(struct igb_adapter *adapter)
654 {
655 struct e1000_hw *hw = &adapter->hw;
656 int i;
657
658 /* hardware has been reset, we need to reload some things */
659 igb_configure(adapter);
660
661 clear_bit(__IGB_DOWN, &adapter->state);
662
663 napi_enable(&adapter->napi);
664
665 if (adapter->msix_entries) {
666 for (i = 0; i < adapter->num_rx_queues; i++)
667 napi_enable(&adapter->rx_ring[i].napi);
668 igb_configure_msix(adapter);
669 }
670
671 /* Clear any pending interrupts. */
672 rd32(E1000_ICR);
673 igb_irq_enable(adapter);
674
675 /* Fire a link change interrupt to start the watchdog. */
676 wr32(E1000_ICS, E1000_ICS_LSC);
677 return 0;
678 }
679
680 void igb_down(struct igb_adapter *adapter)
681 {
682 struct e1000_hw *hw = &adapter->hw;
683 struct net_device *netdev = adapter->netdev;
684 u32 tctl, rctl;
685 int i;
686
687 /* signal that we're down so the interrupt handler does not
688 * reschedule our watchdog timer */
689 set_bit(__IGB_DOWN, &adapter->state);
690
691 /* disable receives in the hardware */
692 rctl = rd32(E1000_RCTL);
693 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
694 /* flush and sleep below */
695
696 netif_stop_queue(netdev);
697
698 /* disable transmits in the hardware */
699 tctl = rd32(E1000_TCTL);
700 tctl &= ~E1000_TCTL_EN;
701 wr32(E1000_TCTL, tctl);
702 /* flush both disables and wait for them to finish */
703 wrfl();
704 msleep(10);
705
706 napi_disable(&adapter->napi);
707
708 if (adapter->msix_entries)
709 for (i = 0; i < adapter->num_rx_queues; i++)
710 napi_disable(&adapter->rx_ring[i].napi);
711 igb_irq_disable(adapter);
712
713 del_timer_sync(&adapter->watchdog_timer);
714 del_timer_sync(&adapter->phy_info_timer);
715
716 netdev->tx_queue_len = adapter->tx_queue_len;
717 netif_carrier_off(netdev);
718 adapter->link_speed = 0;
719 adapter->link_duplex = 0;
720
721 igb_reset(adapter);
722 igb_clean_all_tx_rings(adapter);
723 igb_clean_all_rx_rings(adapter);
724 }
725
726 void igb_reinit_locked(struct igb_adapter *adapter)
727 {
728 WARN_ON(in_interrupt());
729 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
730 msleep(1);
731 igb_down(adapter);
732 igb_up(adapter);
733 clear_bit(__IGB_RESETTING, &adapter->state);
734 }
735
736 void igb_reset(struct igb_adapter *adapter)
737 {
738 struct e1000_hw *hw = &adapter->hw;
739 struct e1000_fc_info *fc = &adapter->hw.fc;
740 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
741 u16 hwm;
742
743 /* Repartition Pba for greater than 9k mtu
744 * To take effect CTRL.RST is required.
745 */
746 pba = E1000_PBA_34K;
747
748 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
749 /* adjust PBA for jumbo frames */
750 wr32(E1000_PBA, pba);
751
752 /* To maintain wire speed transmits, the Tx FIFO should be
753 * large enough to accommodate two full transmit packets,
754 * rounded up to the next 1KB and expressed in KB. Likewise,
755 * the Rx FIFO should be large enough to accommodate at least
756 * one full receive packet and is similarly rounded up and
757 * expressed in KB. */
758 pba = rd32(E1000_PBA);
759 /* upper 16 bits has Tx packet buffer allocation size in KB */
760 tx_space = pba >> 16;
761 /* lower 16 bits has Rx packet buffer allocation size in KB */
762 pba &= 0xffff;
763 /* the tx fifo also stores 16 bytes of information about the tx
764 * but don't include ethernet FCS because hardware appends it */
765 min_tx_space = (adapter->max_frame_size +
766 sizeof(struct e1000_tx_desc) -
767 ETH_FCS_LEN) * 2;
768 min_tx_space = ALIGN(min_tx_space, 1024);
769 min_tx_space >>= 10;
770 /* software strips receive CRC, so leave room for it */
771 min_rx_space = adapter->max_frame_size;
772 min_rx_space = ALIGN(min_rx_space, 1024);
773 min_rx_space >>= 10;
774
775 /* If current Tx allocation is less than the min Tx FIFO size,
776 * and the min Tx FIFO size is less than the current Rx FIFO
777 * allocation, take space away from current Rx allocation */
778 if (tx_space < min_tx_space &&
779 ((min_tx_space - tx_space) < pba)) {
780 pba = pba - (min_tx_space - tx_space);
781
782 /* if short on rx space, rx wins and must trump tx
783 * adjustment */
784 if (pba < min_rx_space)
785 pba = min_rx_space;
786 }
787 }
788 wr32(E1000_PBA, pba);
789
790 /* flow control settings */
791 /* The high water mark must be low enough to fit one full frame
792 * (or the size used for early receive) above it in the Rx FIFO.
793 * Set it to the lower of:
794 * - 90% of the Rx FIFO size, or
795 * - the full Rx FIFO size minus one full frame */
796 hwm = min(((pba << 10) * 9 / 10),
797 ((pba << 10) - adapter->max_frame_size));
798
799 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
800 fc->low_water = fc->high_water - 8;
801 fc->pause_time = 0xFFFF;
802 fc->send_xon = 1;
803 fc->type = fc->original_type;
804
805 /* Allow time for pending master requests to run */
806 adapter->hw.mac.ops.reset_hw(&adapter->hw);
807 wr32(E1000_WUC, 0);
808
809 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
810 dev_err(&adapter->pdev->dev, "Hardware Error\n");
811
812 igb_update_mng_vlan(adapter);
813
814 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
815 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
816
817 igb_reset_adaptive(&adapter->hw);
818 if (adapter->hw.phy.ops.get_phy_info)
819 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
820 }
821
822 /**
823 * igb_probe - Device Initialization Routine
824 * @pdev: PCI device information struct
825 * @ent: entry in igb_pci_tbl
826 *
827 * Returns 0 on success, negative on failure
828 *
829 * igb_probe initializes an adapter identified by a pci_dev structure.
830 * The OS initialization, configuring of the adapter private structure,
831 * and a hardware reset occur.
832 **/
833 static int __devinit igb_probe(struct pci_dev *pdev,
834 const struct pci_device_id *ent)
835 {
836 struct net_device *netdev;
837 struct igb_adapter *adapter;
838 struct e1000_hw *hw;
839 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
840 unsigned long mmio_start, mmio_len;
841 static int cards_found;
842 int i, err, pci_using_dac;
843 u16 eeprom_data = 0;
844 u16 eeprom_apme_mask = IGB_EEPROM_APME;
845 u32 part_num;
846
847 err = pci_enable_device(pdev);
848 if (err)
849 return err;
850
851 pci_using_dac = 0;
852 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
853 if (!err) {
854 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
855 if (!err)
856 pci_using_dac = 1;
857 } else {
858 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
859 if (err) {
860 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
861 if (err) {
862 dev_err(&pdev->dev, "No usable DMA "
863 "configuration, aborting\n");
864 goto err_dma;
865 }
866 }
867 }
868
869 err = pci_request_regions(pdev, igb_driver_name);
870 if (err)
871 goto err_pci_reg;
872
873 pci_set_master(pdev);
874 pci_save_state(pdev);
875
876 err = -ENOMEM;
877 netdev = alloc_etherdev(sizeof(struct igb_adapter));
878 if (!netdev)
879 goto err_alloc_etherdev;
880
881 SET_NETDEV_DEV(netdev, &pdev->dev);
882
883 pci_set_drvdata(pdev, netdev);
884 adapter = netdev_priv(netdev);
885 adapter->netdev = netdev;
886 adapter->pdev = pdev;
887 hw = &adapter->hw;
888 hw->back = adapter;
889 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
890
891 mmio_start = pci_resource_start(pdev, 0);
892 mmio_len = pci_resource_len(pdev, 0);
893
894 err = -EIO;
895 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
896 if (!adapter->hw.hw_addr)
897 goto err_ioremap;
898
899 netdev->open = &igb_open;
900 netdev->stop = &igb_close;
901 netdev->get_stats = &igb_get_stats;
902 netdev->set_multicast_list = &igb_set_multi;
903 netdev->set_mac_address = &igb_set_mac;
904 netdev->change_mtu = &igb_change_mtu;
905 netdev->do_ioctl = &igb_ioctl;
906 igb_set_ethtool_ops(netdev);
907 netdev->tx_timeout = &igb_tx_timeout;
908 netdev->watchdog_timeo = 5 * HZ;
909 netif_napi_add(netdev, &adapter->napi, igb_clean, 64);
910 netdev->vlan_rx_register = igb_vlan_rx_register;
911 netdev->vlan_rx_add_vid = igb_vlan_rx_add_vid;
912 netdev->vlan_rx_kill_vid = igb_vlan_rx_kill_vid;
913 #ifdef CONFIG_NET_POLL_CONTROLLER
914 netdev->poll_controller = igb_netpoll;
915 #endif
916 netdev->hard_start_xmit = &igb_xmit_frame_adv;
917
918 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
919
920 netdev->mem_start = mmio_start;
921 netdev->mem_end = mmio_start + mmio_len;
922
923 adapter->bd_number = cards_found;
924
925 /* PCI config space info */
926 hw->vendor_id = pdev->vendor;
927 hw->device_id = pdev->device;
928 hw->revision_id = pdev->revision;
929 hw->subsystem_vendor_id = pdev->subsystem_vendor;
930 hw->subsystem_device_id = pdev->subsystem_device;
931
932 /* setup the private structure */
933 hw->back = adapter;
934 /* Copy the default MAC, PHY and NVM function pointers */
935 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
936 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
937 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
938 /* Initialize skew-specific constants */
939 err = ei->get_invariants(hw);
940 if (err)
941 goto err_hw_init;
942
943 err = igb_sw_init(adapter);
944 if (err)
945 goto err_sw_init;
946
947 igb_get_bus_info_pcie(hw);
948
949 hw->phy.autoneg_wait_to_complete = false;
950 hw->mac.adaptive_ifs = true;
951
952 /* Copper options */
953 if (hw->phy.media_type == e1000_media_type_copper) {
954 hw->phy.mdix = AUTO_ALL_MODES;
955 hw->phy.disable_polarity_correction = false;
956 hw->phy.ms_type = e1000_ms_hw_default;
957 }
958
959 if (igb_check_reset_block(hw))
960 dev_info(&pdev->dev,
961 "PHY reset is blocked due to SOL/IDER session.\n");
962
963 netdev->features = NETIF_F_SG |
964 NETIF_F_HW_CSUM |
965 NETIF_F_HW_VLAN_TX |
966 NETIF_F_HW_VLAN_RX |
967 NETIF_F_HW_VLAN_FILTER;
968
969 netdev->features |= NETIF_F_TSO;
970 netdev->features |= NETIF_F_TSO6;
971
972 netdev->vlan_features |= NETIF_F_TSO;
973 netdev->vlan_features |= NETIF_F_TSO6;
974 netdev->vlan_features |= NETIF_F_HW_CSUM;
975 netdev->vlan_features |= NETIF_F_SG;
976
977 if (pci_using_dac)
978 netdev->features |= NETIF_F_HIGHDMA;
979
980 netdev->features |= NETIF_F_LLTX;
981 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
982
983 /* before reading the NVM, reset the controller to put the device in a
984 * known good starting state */
985 hw->mac.ops.reset_hw(hw);
986
987 /* make sure the NVM is good */
988 if (igb_validate_nvm_checksum(hw) < 0) {
989 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
990 err = -EIO;
991 goto err_eeprom;
992 }
993
994 /* copy the MAC address out of the NVM */
995 if (hw->mac.ops.read_mac_addr(hw))
996 dev_err(&pdev->dev, "NVM Read Error\n");
997
998 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
999 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1000
1001 if (!is_valid_ether_addr(netdev->perm_addr)) {
1002 dev_err(&pdev->dev, "Invalid MAC Address\n");
1003 err = -EIO;
1004 goto err_eeprom;
1005 }
1006
1007 init_timer(&adapter->watchdog_timer);
1008 adapter->watchdog_timer.function = &igb_watchdog;
1009 adapter->watchdog_timer.data = (unsigned long) adapter;
1010
1011 init_timer(&adapter->phy_info_timer);
1012 adapter->phy_info_timer.function = &igb_update_phy_info;
1013 adapter->phy_info_timer.data = (unsigned long) adapter;
1014
1015 INIT_WORK(&adapter->reset_task, igb_reset_task);
1016 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1017
1018 /* Initialize link & ring properties that are user-changeable */
1019 adapter->tx_ring->count = 256;
1020 for (i = 0; i < adapter->num_tx_queues; i++)
1021 adapter->tx_ring[i].count = adapter->tx_ring->count;
1022 adapter->rx_ring->count = 256;
1023 for (i = 0; i < adapter->num_rx_queues; i++)
1024 adapter->rx_ring[i].count = adapter->rx_ring->count;
1025
1026 adapter->fc_autoneg = true;
1027 hw->mac.autoneg = true;
1028 hw->phy.autoneg_advertised = 0x2f;
1029
1030 hw->fc.original_type = e1000_fc_default;
1031 hw->fc.type = e1000_fc_default;
1032
1033 adapter->itr_setting = 3;
1034 adapter->itr = IGB_START_ITR;
1035
1036 igb_validate_mdi_setting(hw);
1037
1038 adapter->rx_csum = 1;
1039
1040 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1041 * enable the ACPI Magic Packet filter
1042 */
1043
1044 if (hw->bus.func == 0 ||
1045 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
1046 hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL3_PORT_A, 1,
1047 &eeprom_data);
1048
1049 if (eeprom_data & eeprom_apme_mask)
1050 adapter->eeprom_wol |= E1000_WUFC_MAG;
1051
1052 /* now that we have the eeprom settings, apply the special cases where
1053 * the eeprom may be wrong or the board simply won't support wake on
1054 * lan on a particular port */
1055 switch (pdev->device) {
1056 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1057 adapter->eeprom_wol = 0;
1058 break;
1059 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1060 /* Wake events only supported on port A for dual fiber
1061 * regardless of eeprom setting */
1062 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1063 adapter->eeprom_wol = 0;
1064 break;
1065 }
1066
1067 /* initialize the wol settings based on the eeprom settings */
1068 adapter->wol = adapter->eeprom_wol;
1069
1070 /* reset the hardware with the new settings */
1071 igb_reset(adapter);
1072
1073 /* let the f/w know that the h/w is now under the control of the
1074 * driver. */
1075 igb_get_hw_control(adapter);
1076
1077 /* tell the stack to leave us alone until igb_open() is called */
1078 netif_carrier_off(netdev);
1079 netif_stop_queue(netdev);
1080
1081 strcpy(netdev->name, "eth%d");
1082 err = register_netdev(netdev);
1083 if (err)
1084 goto err_register;
1085
1086 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1087 /* print bus type/speed/width info */
1088 dev_info(&pdev->dev,
1089 "%s: (PCIe:%s:%s) %02x:%02x:%02x:%02x:%02x:%02x\n",
1090 netdev->name,
1091 ((hw->bus.speed == e1000_bus_speed_2500)
1092 ? "2.5Gb/s" : "unknown"),
1093 ((hw->bus.width == e1000_bus_width_pcie_x4)
1094 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1095 ? "Width x1" : "unknown"),
1096 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
1097 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
1098
1099 igb_read_part_num(hw, &part_num);
1100 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1101 (part_num >> 8), (part_num & 0xff));
1102
1103 dev_info(&pdev->dev,
1104 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1105 adapter->msix_entries ? "MSI-X" :
1106 adapter->msi_enabled ? "MSI" : "legacy",
1107 adapter->num_rx_queues, adapter->num_tx_queues);
1108
1109 cards_found++;
1110 return 0;
1111
1112 err_register:
1113 igb_release_hw_control(adapter);
1114 err_eeprom:
1115 if (!igb_check_reset_block(hw))
1116 hw->phy.ops.reset_phy(hw);
1117
1118 if (hw->flash_address)
1119 iounmap(hw->flash_address);
1120
1121 igb_remove_device(hw);
1122 kfree(adapter->tx_ring);
1123 kfree(adapter->rx_ring);
1124 err_sw_init:
1125 err_hw_init:
1126 iounmap(hw->hw_addr);
1127 err_ioremap:
1128 free_netdev(netdev);
1129 err_alloc_etherdev:
1130 pci_release_regions(pdev);
1131 err_pci_reg:
1132 err_dma:
1133 pci_disable_device(pdev);
1134 return err;
1135 }
1136
1137 /**
1138 * igb_remove - Device Removal Routine
1139 * @pdev: PCI device information struct
1140 *
1141 * igb_remove is called by the PCI subsystem to alert the driver
1142 * that it should release a PCI device. The could be caused by a
1143 * Hot-Plug event, or because the driver is going to be removed from
1144 * memory.
1145 **/
1146 static void __devexit igb_remove(struct pci_dev *pdev)
1147 {
1148 struct net_device *netdev = pci_get_drvdata(pdev);
1149 struct igb_adapter *adapter = netdev_priv(netdev);
1150
1151 /* flush_scheduled work may reschedule our watchdog task, so
1152 * explicitly disable watchdog tasks from being rescheduled */
1153 set_bit(__IGB_DOWN, &adapter->state);
1154 del_timer_sync(&adapter->watchdog_timer);
1155 del_timer_sync(&adapter->phy_info_timer);
1156
1157 flush_scheduled_work();
1158
1159 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1160 * would have already happened in close and is redundant. */
1161 igb_release_hw_control(adapter);
1162
1163 unregister_netdev(netdev);
1164
1165 if (!igb_check_reset_block(&adapter->hw))
1166 adapter->hw.phy.ops.reset_phy(&adapter->hw);
1167
1168 igb_remove_device(&adapter->hw);
1169 igb_reset_interrupt_capability(adapter);
1170
1171 kfree(adapter->tx_ring);
1172 kfree(adapter->rx_ring);
1173
1174 iounmap(adapter->hw.hw_addr);
1175 if (adapter->hw.flash_address)
1176 iounmap(adapter->hw.flash_address);
1177 pci_release_regions(pdev);
1178
1179 free_netdev(netdev);
1180
1181 pci_disable_device(pdev);
1182 }
1183
1184 /**
1185 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1186 * @adapter: board private structure to initialize
1187 *
1188 * igb_sw_init initializes the Adapter private data structure.
1189 * Fields are initialized based on PCI device information and
1190 * OS network device settings (MTU size).
1191 **/
1192 static int __devinit igb_sw_init(struct igb_adapter *adapter)
1193 {
1194 struct e1000_hw *hw = &adapter->hw;
1195 struct net_device *netdev = adapter->netdev;
1196 struct pci_dev *pdev = adapter->pdev;
1197
1198 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1199
1200 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1201 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1202 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1203 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1204
1205 /* Number of supported queues. */
1206 /* Having more queues than CPUs doesn't make sense. */
1207 adapter->num_tx_queues = 1;
1208 adapter->num_rx_queues = min(IGB_MAX_RX_QUEUES, num_online_cpus());
1209
1210 igb_set_interrupt_capability(adapter);
1211
1212 if (igb_alloc_queues(adapter)) {
1213 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1214 return -ENOMEM;
1215 }
1216
1217 /* Explicitly disable IRQ since the NIC can be in any state. */
1218 igb_irq_disable(adapter);
1219
1220 set_bit(__IGB_DOWN, &adapter->state);
1221 return 0;
1222 }
1223
1224 /**
1225 * igb_open - Called when a network interface is made active
1226 * @netdev: network interface device structure
1227 *
1228 * Returns 0 on success, negative value on failure
1229 *
1230 * The open entry point is called when a network interface is made
1231 * active by the system (IFF_UP). At this point all resources needed
1232 * for transmit and receive operations are allocated, the interrupt
1233 * handler is registered with the OS, the watchdog timer is started,
1234 * and the stack is notified that the interface is ready.
1235 **/
1236 static int igb_open(struct net_device *netdev)
1237 {
1238 struct igb_adapter *adapter = netdev_priv(netdev);
1239 struct e1000_hw *hw = &adapter->hw;
1240 int err;
1241 int i;
1242
1243 /* disallow open during test */
1244 if (test_bit(__IGB_TESTING, &adapter->state))
1245 return -EBUSY;
1246
1247 /* allocate transmit descriptors */
1248 err = igb_setup_all_tx_resources(adapter);
1249 if (err)
1250 goto err_setup_tx;
1251
1252 /* allocate receive descriptors */
1253 err = igb_setup_all_rx_resources(adapter);
1254 if (err)
1255 goto err_setup_rx;
1256
1257 /* e1000_power_up_phy(adapter); */
1258
1259 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1260 if ((adapter->hw.mng_cookie.status &
1261 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1262 igb_update_mng_vlan(adapter);
1263
1264 /* before we allocate an interrupt, we must be ready to handle it.
1265 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1266 * as soon as we call pci_request_irq, so we have to setup our
1267 * clean_rx handler before we do so. */
1268 igb_configure(adapter);
1269
1270 err = igb_request_irq(adapter);
1271 if (err)
1272 goto err_req_irq;
1273
1274 /* From here on the code is the same as igb_up() */
1275 clear_bit(__IGB_DOWN, &adapter->state);
1276
1277 napi_enable(&adapter->napi);
1278 if (adapter->msix_entries)
1279 for (i = 0; i < adapter->num_rx_queues; i++)
1280 napi_enable(&adapter->rx_ring[i].napi);
1281
1282 igb_irq_enable(adapter);
1283
1284 /* Clear any pending interrupts. */
1285 rd32(E1000_ICR);
1286 /* Fire a link status change interrupt to start the watchdog. */
1287 wr32(E1000_ICS, E1000_ICS_LSC);
1288
1289 return 0;
1290
1291 err_req_irq:
1292 igb_release_hw_control(adapter);
1293 /* e1000_power_down_phy(adapter); */
1294 igb_free_all_rx_resources(adapter);
1295 err_setup_rx:
1296 igb_free_all_tx_resources(adapter);
1297 err_setup_tx:
1298 igb_reset(adapter);
1299
1300 return err;
1301 }
1302
1303 /**
1304 * igb_close - Disables a network interface
1305 * @netdev: network interface device structure
1306 *
1307 * Returns 0, this is not allowed to fail
1308 *
1309 * The close entry point is called when an interface is de-activated
1310 * by the OS. The hardware is still under the driver's control, but
1311 * needs to be disabled. A global MAC reset is issued to stop the
1312 * hardware, and all transmit and receive resources are freed.
1313 **/
1314 static int igb_close(struct net_device *netdev)
1315 {
1316 struct igb_adapter *adapter = netdev_priv(netdev);
1317
1318 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1319 igb_down(adapter);
1320
1321 igb_free_irq(adapter);
1322
1323 igb_free_all_tx_resources(adapter);
1324 igb_free_all_rx_resources(adapter);
1325
1326 /* kill manageability vlan ID if supported, but not if a vlan with
1327 * the same ID is registered on the host OS (let 8021q kill it) */
1328 if ((adapter->hw.mng_cookie.status &
1329 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1330 !(adapter->vlgrp &&
1331 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1332 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1333
1334 return 0;
1335 }
1336
1337 /**
1338 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1339 * @adapter: board private structure
1340 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1341 *
1342 * Return 0 on success, negative on failure
1343 **/
1344
1345 int igb_setup_tx_resources(struct igb_adapter *adapter,
1346 struct igb_ring *tx_ring)
1347 {
1348 struct pci_dev *pdev = adapter->pdev;
1349 int size;
1350
1351 size = sizeof(struct igb_buffer) * tx_ring->count;
1352 tx_ring->buffer_info = vmalloc(size);
1353 if (!tx_ring->buffer_info)
1354 goto err;
1355 memset(tx_ring->buffer_info, 0, size);
1356
1357 /* round up to nearest 4K */
1358 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc)
1359 + sizeof(u32);
1360 tx_ring->size = ALIGN(tx_ring->size, 4096);
1361
1362 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1363 &tx_ring->dma);
1364
1365 if (!tx_ring->desc)
1366 goto err;
1367
1368 tx_ring->adapter = adapter;
1369 tx_ring->next_to_use = 0;
1370 tx_ring->next_to_clean = 0;
1371 spin_lock_init(&tx_ring->tx_clean_lock);
1372 spin_lock_init(&tx_ring->tx_lock);
1373 return 0;
1374
1375 err:
1376 vfree(tx_ring->buffer_info);
1377 dev_err(&adapter->pdev->dev,
1378 "Unable to allocate memory for the transmit descriptor ring\n");
1379 return -ENOMEM;
1380 }
1381
1382 /**
1383 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1384 * (Descriptors) for all queues
1385 * @adapter: board private structure
1386 *
1387 * Return 0 on success, negative on failure
1388 **/
1389 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1390 {
1391 int i, err = 0;
1392
1393 for (i = 0; i < adapter->num_tx_queues; i++) {
1394 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1395 if (err) {
1396 dev_err(&adapter->pdev->dev,
1397 "Allocation for Tx Queue %u failed\n", i);
1398 for (i--; i >= 0; i--)
1399 igb_free_tx_resources(adapter,
1400 &adapter->tx_ring[i]);
1401 break;
1402 }
1403 }
1404
1405 return err;
1406 }
1407
1408 /**
1409 * igb_configure_tx - Configure transmit Unit after Reset
1410 * @adapter: board private structure
1411 *
1412 * Configure the Tx unit of the MAC after a reset.
1413 **/
1414 static void igb_configure_tx(struct igb_adapter *adapter)
1415 {
1416 u64 tdba, tdwba;
1417 struct e1000_hw *hw = &adapter->hw;
1418 u32 tctl;
1419 u32 txdctl, txctrl;
1420 int i;
1421
1422 for (i = 0; i < adapter->num_tx_queues; i++) {
1423 struct igb_ring *ring = &(adapter->tx_ring[i]);
1424
1425 wr32(E1000_TDLEN(i),
1426 ring->count * sizeof(struct e1000_tx_desc));
1427 tdba = ring->dma;
1428 wr32(E1000_TDBAL(i),
1429 tdba & 0x00000000ffffffffULL);
1430 wr32(E1000_TDBAH(i), tdba >> 32);
1431
1432 tdwba = ring->dma + ring->count * sizeof(struct e1000_tx_desc);
1433 tdwba |= 1; /* enable head wb */
1434 wr32(E1000_TDWBAL(i),
1435 tdwba & 0x00000000ffffffffULL);
1436 wr32(E1000_TDWBAH(i), tdwba >> 32);
1437
1438 ring->head = E1000_TDH(i);
1439 ring->tail = E1000_TDT(i);
1440 writel(0, hw->hw_addr + ring->tail);
1441 writel(0, hw->hw_addr + ring->head);
1442 txdctl = rd32(E1000_TXDCTL(i));
1443 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1444 wr32(E1000_TXDCTL(i), txdctl);
1445
1446 /* Turn off Relaxed Ordering on head write-backs. The
1447 * writebacks MUST be delivered in order or it will
1448 * completely screw up our bookeeping.
1449 */
1450 txctrl = rd32(E1000_DCA_TXCTRL(i));
1451 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1452 wr32(E1000_DCA_TXCTRL(i), txctrl);
1453 }
1454
1455
1456
1457 /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1458
1459 /* Program the Transmit Control Register */
1460
1461 tctl = rd32(E1000_TCTL);
1462 tctl &= ~E1000_TCTL_CT;
1463 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1464 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1465
1466 igb_config_collision_dist(hw);
1467
1468 /* Setup Transmit Descriptor Settings for eop descriptor */
1469 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1470
1471 /* Enable transmits */
1472 tctl |= E1000_TCTL_EN;
1473
1474 wr32(E1000_TCTL, tctl);
1475 }
1476
1477 /**
1478 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1479 * @adapter: board private structure
1480 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1481 *
1482 * Returns 0 on success, negative on failure
1483 **/
1484
1485 int igb_setup_rx_resources(struct igb_adapter *adapter,
1486 struct igb_ring *rx_ring)
1487 {
1488 struct pci_dev *pdev = adapter->pdev;
1489 int size, desc_len;
1490
1491 size = sizeof(struct igb_buffer) * rx_ring->count;
1492 rx_ring->buffer_info = vmalloc(size);
1493 if (!rx_ring->buffer_info)
1494 goto err;
1495 memset(rx_ring->buffer_info, 0, size);
1496
1497 desc_len = sizeof(union e1000_adv_rx_desc);
1498
1499 /* Round up to nearest 4K */
1500 rx_ring->size = rx_ring->count * desc_len;
1501 rx_ring->size = ALIGN(rx_ring->size, 4096);
1502
1503 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1504 &rx_ring->dma);
1505
1506 if (!rx_ring->desc)
1507 goto err;
1508
1509 rx_ring->next_to_clean = 0;
1510 rx_ring->next_to_use = 0;
1511 rx_ring->pending_skb = NULL;
1512
1513 rx_ring->adapter = adapter;
1514 /* FIXME: do we want to setup ring->napi->poll here? */
1515 rx_ring->napi.poll = adapter->napi.poll;
1516
1517 return 0;
1518
1519 err:
1520 vfree(rx_ring->buffer_info);
1521 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1522 "the receive descriptor ring\n");
1523 return -ENOMEM;
1524 }
1525
1526 /**
1527 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1528 * (Descriptors) for all queues
1529 * @adapter: board private structure
1530 *
1531 * Return 0 on success, negative on failure
1532 **/
1533 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1534 {
1535 int i, err = 0;
1536
1537 for (i = 0; i < adapter->num_rx_queues; i++) {
1538 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1539 if (err) {
1540 dev_err(&adapter->pdev->dev,
1541 "Allocation for Rx Queue %u failed\n", i);
1542 for (i--; i >= 0; i--)
1543 igb_free_rx_resources(adapter,
1544 &adapter->rx_ring[i]);
1545 break;
1546 }
1547 }
1548
1549 return err;
1550 }
1551
1552 /**
1553 * igb_setup_rctl - configure the receive control registers
1554 * @adapter: Board private structure
1555 **/
1556 static void igb_setup_rctl(struct igb_adapter *adapter)
1557 {
1558 struct e1000_hw *hw = &adapter->hw;
1559 u32 rctl;
1560 u32 srrctl = 0;
1561 int i;
1562
1563 rctl = rd32(E1000_RCTL);
1564
1565 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1566
1567 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1568 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1569 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1570
1571 /* disable the stripping of CRC because it breaks
1572 * BMC firmware connected over SMBUS
1573 rctl |= E1000_RCTL_SECRC;
1574 */
1575
1576 rctl &= ~E1000_RCTL_SBP;
1577
1578 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1579 rctl &= ~E1000_RCTL_LPE;
1580 else
1581 rctl |= E1000_RCTL_LPE;
1582 if (adapter->rx_buffer_len <= IGB_RXBUFFER_2048) {
1583 /* Setup buffer sizes */
1584 rctl &= ~E1000_RCTL_SZ_4096;
1585 rctl |= E1000_RCTL_BSEX;
1586 switch (adapter->rx_buffer_len) {
1587 case IGB_RXBUFFER_256:
1588 rctl |= E1000_RCTL_SZ_256;
1589 rctl &= ~E1000_RCTL_BSEX;
1590 break;
1591 case IGB_RXBUFFER_512:
1592 rctl |= E1000_RCTL_SZ_512;
1593 rctl &= ~E1000_RCTL_BSEX;
1594 break;
1595 case IGB_RXBUFFER_1024:
1596 rctl |= E1000_RCTL_SZ_1024;
1597 rctl &= ~E1000_RCTL_BSEX;
1598 break;
1599 case IGB_RXBUFFER_2048:
1600 default:
1601 rctl |= E1000_RCTL_SZ_2048;
1602 rctl &= ~E1000_RCTL_BSEX;
1603 break;
1604 case IGB_RXBUFFER_4096:
1605 rctl |= E1000_RCTL_SZ_4096;
1606 break;
1607 case IGB_RXBUFFER_8192:
1608 rctl |= E1000_RCTL_SZ_8192;
1609 break;
1610 case IGB_RXBUFFER_16384:
1611 rctl |= E1000_RCTL_SZ_16384;
1612 break;
1613 }
1614 } else {
1615 rctl &= ~E1000_RCTL_BSEX;
1616 srrctl = adapter->rx_buffer_len >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1617 }
1618
1619 /* 82575 and greater support packet-split where the protocol
1620 * header is placed in skb->data and the packet data is
1621 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1622 * In the case of a non-split, skb->data is linearly filled,
1623 * followed by the page buffers. Therefore, skb->data is
1624 * sized to hold the largest protocol header.
1625 */
1626 /* allocations using alloc_page take too long for regular MTU
1627 * so only enable packet split for jumbo frames */
1628 if (rctl & E1000_RCTL_LPE) {
1629 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
1630 srrctl = adapter->rx_ps_hdr_size <<
1631 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
1632 /* buffer size is ALWAYS one page */
1633 srrctl |= PAGE_SIZE >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1634 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1635 } else {
1636 adapter->rx_ps_hdr_size = 0;
1637 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1638 }
1639
1640 for (i = 0; i < adapter->num_rx_queues; i++)
1641 wr32(E1000_SRRCTL(i), srrctl);
1642
1643 wr32(E1000_RCTL, rctl);
1644 }
1645
1646 /**
1647 * igb_configure_rx - Configure receive Unit after Reset
1648 * @adapter: board private structure
1649 *
1650 * Configure the Rx unit of the MAC after a reset.
1651 **/
1652 static void igb_configure_rx(struct igb_adapter *adapter)
1653 {
1654 u64 rdba;
1655 struct e1000_hw *hw = &adapter->hw;
1656 u32 rctl, rxcsum;
1657 u32 rxdctl;
1658 int i;
1659
1660 /* disable receives while setting up the descriptors */
1661 rctl = rd32(E1000_RCTL);
1662 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1663 wrfl();
1664 mdelay(10);
1665
1666 if (adapter->itr_setting > 3)
1667 wr32(E1000_ITR,
1668 1000000000 / (adapter->itr * 256));
1669
1670 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1671 * the Base and Length of the Rx Descriptor Ring */
1672 for (i = 0; i < adapter->num_rx_queues; i++) {
1673 struct igb_ring *ring = &(adapter->rx_ring[i]);
1674 rdba = ring->dma;
1675 wr32(E1000_RDBAL(i),
1676 rdba & 0x00000000ffffffffULL);
1677 wr32(E1000_RDBAH(i), rdba >> 32);
1678 wr32(E1000_RDLEN(i),
1679 ring->count * sizeof(union e1000_adv_rx_desc));
1680
1681 ring->head = E1000_RDH(i);
1682 ring->tail = E1000_RDT(i);
1683 writel(0, hw->hw_addr + ring->tail);
1684 writel(0, hw->hw_addr + ring->head);
1685
1686 rxdctl = rd32(E1000_RXDCTL(i));
1687 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1688 rxdctl &= 0xFFF00000;
1689 rxdctl |= IGB_RX_PTHRESH;
1690 rxdctl |= IGB_RX_HTHRESH << 8;
1691 rxdctl |= IGB_RX_WTHRESH << 16;
1692 wr32(E1000_RXDCTL(i), rxdctl);
1693 }
1694
1695 if (adapter->num_rx_queues > 1) {
1696 u32 random[10];
1697 u32 mrqc;
1698 u32 j, shift;
1699 union e1000_reta {
1700 u32 dword;
1701 u8 bytes[4];
1702 } reta;
1703
1704 get_random_bytes(&random[0], 40);
1705
1706 shift = 6;
1707 for (j = 0; j < (32 * 4); j++) {
1708 reta.bytes[j & 3] =
1709 (j % adapter->num_rx_queues) << shift;
1710 if ((j & 3) == 3)
1711 writel(reta.dword,
1712 hw->hw_addr + E1000_RETA(0) + (j & ~3));
1713 }
1714 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
1715
1716 /* Fill out hash function seeds */
1717 for (j = 0; j < 10; j++)
1718 array_wr32(E1000_RSSRK(0), j, random[j]);
1719
1720 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1721 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1722 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
1723 E1000_MRQC_RSS_FIELD_IPV6_TCP);
1724 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
1725 E1000_MRQC_RSS_FIELD_IPV6_UDP);
1726 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
1727 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
1728
1729
1730 wr32(E1000_MRQC, mrqc);
1731
1732 /* Multiqueue and raw packet checksumming are mutually
1733 * exclusive. Note that this not the same as TCP/IP
1734 * checksumming, which works fine. */
1735 rxcsum = rd32(E1000_RXCSUM);
1736 rxcsum |= E1000_RXCSUM_PCSD;
1737 wr32(E1000_RXCSUM, rxcsum);
1738 } else {
1739 /* Enable Receive Checksum Offload for TCP and UDP */
1740 rxcsum = rd32(E1000_RXCSUM);
1741 if (adapter->rx_csum) {
1742 rxcsum |= E1000_RXCSUM_TUOFL;
1743
1744 /* Enable IPv4 payload checksum for UDP fragments
1745 * Must be used in conjunction with packet-split. */
1746 if (adapter->rx_ps_hdr_size)
1747 rxcsum |= E1000_RXCSUM_IPPCSE;
1748 } else {
1749 rxcsum &= ~E1000_RXCSUM_TUOFL;
1750 /* don't need to clear IPPCSE as it defaults to 0 */
1751 }
1752 wr32(E1000_RXCSUM, rxcsum);
1753 }
1754
1755 if (adapter->vlgrp)
1756 wr32(E1000_RLPML,
1757 adapter->max_frame_size + VLAN_TAG_SIZE);
1758 else
1759 wr32(E1000_RLPML, adapter->max_frame_size);
1760
1761 /* Enable Receives */
1762 wr32(E1000_RCTL, rctl);
1763 }
1764
1765 /**
1766 * igb_free_tx_resources - Free Tx Resources per Queue
1767 * @adapter: board private structure
1768 * @tx_ring: Tx descriptor ring for a specific queue
1769 *
1770 * Free all transmit software resources
1771 **/
1772 static void igb_free_tx_resources(struct igb_adapter *adapter,
1773 struct igb_ring *tx_ring)
1774 {
1775 struct pci_dev *pdev = adapter->pdev;
1776
1777 igb_clean_tx_ring(adapter, tx_ring);
1778
1779 vfree(tx_ring->buffer_info);
1780 tx_ring->buffer_info = NULL;
1781
1782 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1783
1784 tx_ring->desc = NULL;
1785 }
1786
1787 /**
1788 * igb_free_all_tx_resources - Free Tx Resources for All Queues
1789 * @adapter: board private structure
1790 *
1791 * Free all transmit software resources
1792 **/
1793 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
1794 {
1795 int i;
1796
1797 for (i = 0; i < adapter->num_tx_queues; i++)
1798 igb_free_tx_resources(adapter, &adapter->tx_ring[i]);
1799 }
1800
1801 static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
1802 struct igb_buffer *buffer_info)
1803 {
1804 if (buffer_info->dma) {
1805 pci_unmap_page(adapter->pdev,
1806 buffer_info->dma,
1807 buffer_info->length,
1808 PCI_DMA_TODEVICE);
1809 buffer_info->dma = 0;
1810 }
1811 if (buffer_info->skb) {
1812 dev_kfree_skb_any(buffer_info->skb);
1813 buffer_info->skb = NULL;
1814 }
1815 buffer_info->time_stamp = 0;
1816 /* buffer_info must be completely set up in the transmit path */
1817 }
1818
1819 /**
1820 * igb_clean_tx_ring - Free Tx Buffers
1821 * @adapter: board private structure
1822 * @tx_ring: ring to be cleaned
1823 **/
1824 static void igb_clean_tx_ring(struct igb_adapter *adapter,
1825 struct igb_ring *tx_ring)
1826 {
1827 struct igb_buffer *buffer_info;
1828 unsigned long size;
1829 unsigned int i;
1830
1831 if (!tx_ring->buffer_info)
1832 return;
1833 /* Free all the Tx ring sk_buffs */
1834
1835 for (i = 0; i < tx_ring->count; i++) {
1836 buffer_info = &tx_ring->buffer_info[i];
1837 igb_unmap_and_free_tx_resource(adapter, buffer_info);
1838 }
1839
1840 size = sizeof(struct igb_buffer) * tx_ring->count;
1841 memset(tx_ring->buffer_info, 0, size);
1842
1843 /* Zero out the descriptor ring */
1844
1845 memset(tx_ring->desc, 0, tx_ring->size);
1846
1847 tx_ring->next_to_use = 0;
1848 tx_ring->next_to_clean = 0;
1849
1850 writel(0, adapter->hw.hw_addr + tx_ring->head);
1851 writel(0, adapter->hw.hw_addr + tx_ring->tail);
1852 }
1853
1854 /**
1855 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
1856 * @adapter: board private structure
1857 **/
1858 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
1859 {
1860 int i;
1861
1862 for (i = 0; i < adapter->num_tx_queues; i++)
1863 igb_clean_tx_ring(adapter, &adapter->tx_ring[i]);
1864 }
1865
1866 /**
1867 * igb_free_rx_resources - Free Rx Resources
1868 * @adapter: board private structure
1869 * @rx_ring: ring to clean the resources from
1870 *
1871 * Free all receive software resources
1872 **/
1873 static void igb_free_rx_resources(struct igb_adapter *adapter,
1874 struct igb_ring *rx_ring)
1875 {
1876 struct pci_dev *pdev = adapter->pdev;
1877
1878 igb_clean_rx_ring(adapter, rx_ring);
1879
1880 vfree(rx_ring->buffer_info);
1881 rx_ring->buffer_info = NULL;
1882
1883 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1884
1885 rx_ring->desc = NULL;
1886 }
1887
1888 /**
1889 * igb_free_all_rx_resources - Free Rx Resources for All Queues
1890 * @adapter: board private structure
1891 *
1892 * Free all receive software resources
1893 **/
1894 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
1895 {
1896 int i;
1897
1898 for (i = 0; i < adapter->num_rx_queues; i++)
1899 igb_free_rx_resources(adapter, &adapter->rx_ring[i]);
1900 }
1901
1902 /**
1903 * igb_clean_rx_ring - Free Rx Buffers per Queue
1904 * @adapter: board private structure
1905 * @rx_ring: ring to free buffers from
1906 **/
1907 static void igb_clean_rx_ring(struct igb_adapter *adapter,
1908 struct igb_ring *rx_ring)
1909 {
1910 struct igb_buffer *buffer_info;
1911 struct pci_dev *pdev = adapter->pdev;
1912 unsigned long size;
1913 unsigned int i;
1914
1915 if (!rx_ring->buffer_info)
1916 return;
1917 /* Free all the Rx ring sk_buffs */
1918 for (i = 0; i < rx_ring->count; i++) {
1919 buffer_info = &rx_ring->buffer_info[i];
1920 if (buffer_info->dma) {
1921 if (adapter->rx_ps_hdr_size)
1922 pci_unmap_single(pdev, buffer_info->dma,
1923 adapter->rx_ps_hdr_size,
1924 PCI_DMA_FROMDEVICE);
1925 else
1926 pci_unmap_single(pdev, buffer_info->dma,
1927 adapter->rx_buffer_len,
1928 PCI_DMA_FROMDEVICE);
1929 buffer_info->dma = 0;
1930 }
1931
1932 if (buffer_info->skb) {
1933 dev_kfree_skb(buffer_info->skb);
1934 buffer_info->skb = NULL;
1935 }
1936 if (buffer_info->page) {
1937 pci_unmap_page(pdev, buffer_info->page_dma,
1938 PAGE_SIZE, PCI_DMA_FROMDEVICE);
1939 put_page(buffer_info->page);
1940 buffer_info->page = NULL;
1941 buffer_info->page_dma = 0;
1942 }
1943 }
1944
1945 /* there also may be some cached data from a chained receive */
1946 if (rx_ring->pending_skb) {
1947 dev_kfree_skb(rx_ring->pending_skb);
1948 rx_ring->pending_skb = NULL;
1949 }
1950
1951 size = sizeof(struct igb_buffer) * rx_ring->count;
1952 memset(rx_ring->buffer_info, 0, size);
1953
1954 /* Zero out the descriptor ring */
1955 memset(rx_ring->desc, 0, rx_ring->size);
1956
1957 rx_ring->next_to_clean = 0;
1958 rx_ring->next_to_use = 0;
1959
1960 writel(0, adapter->hw.hw_addr + rx_ring->head);
1961 writel(0, adapter->hw.hw_addr + rx_ring->tail);
1962 }
1963
1964 /**
1965 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
1966 * @adapter: board private structure
1967 **/
1968 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
1969 {
1970 int i;
1971
1972 for (i = 0; i < adapter->num_rx_queues; i++)
1973 igb_clean_rx_ring(adapter, &adapter->rx_ring[i]);
1974 }
1975
1976 /**
1977 * igb_set_mac - Change the Ethernet Address of the NIC
1978 * @netdev: network interface device structure
1979 * @p: pointer to an address structure
1980 *
1981 * Returns 0 on success, negative on failure
1982 **/
1983 static int igb_set_mac(struct net_device *netdev, void *p)
1984 {
1985 struct igb_adapter *adapter = netdev_priv(netdev);
1986 struct sockaddr *addr = p;
1987
1988 if (!is_valid_ether_addr(addr->sa_data))
1989 return -EADDRNOTAVAIL;
1990
1991 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1992 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
1993
1994 adapter->hw.mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1995
1996 return 0;
1997 }
1998
1999 /**
2000 * igb_set_multi - Multicast and Promiscuous mode set
2001 * @netdev: network interface device structure
2002 *
2003 * The set_multi entry point is called whenever the multicast address
2004 * list or the network interface flags are updated. This routine is
2005 * responsible for configuring the hardware for proper multicast,
2006 * promiscuous mode, and all-multi behavior.
2007 **/
2008 static void igb_set_multi(struct net_device *netdev)
2009 {
2010 struct igb_adapter *adapter = netdev_priv(netdev);
2011 struct e1000_hw *hw = &adapter->hw;
2012 struct e1000_mac_info *mac = &hw->mac;
2013 struct dev_mc_list *mc_ptr;
2014 u8 *mta_list;
2015 u32 rctl;
2016 int i;
2017
2018 /* Check for Promiscuous and All Multicast modes */
2019
2020 rctl = rd32(E1000_RCTL);
2021
2022 if (netdev->flags & IFF_PROMISC)
2023 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2024 else if (netdev->flags & IFF_ALLMULTI) {
2025 rctl |= E1000_RCTL_MPE;
2026 rctl &= ~E1000_RCTL_UPE;
2027 } else
2028 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2029
2030 wr32(E1000_RCTL, rctl);
2031
2032 if (!netdev->mc_count) {
2033 /* nothing to program, so clear mc list */
2034 igb_update_mc_addr_list(hw, NULL, 0, 1,
2035 mac->rar_entry_count);
2036 return;
2037 }
2038
2039 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2040 if (!mta_list)
2041 return;
2042
2043 /* The shared function expects a packed array of only addresses. */
2044 mc_ptr = netdev->mc_list;
2045
2046 for (i = 0; i < netdev->mc_count; i++) {
2047 if (!mc_ptr)
2048 break;
2049 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2050 mc_ptr = mc_ptr->next;
2051 }
2052 igb_update_mc_addr_list(hw, mta_list, i, 1, mac->rar_entry_count);
2053 kfree(mta_list);
2054 }
2055
2056 /* Need to wait a few seconds after link up to get diagnostic information from
2057 * the phy */
2058 static void igb_update_phy_info(unsigned long data)
2059 {
2060 struct igb_adapter *adapter = (struct igb_adapter *) data;
2061 if (adapter->hw.phy.ops.get_phy_info)
2062 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
2063 }
2064
2065 /**
2066 * igb_watchdog - Timer Call-back
2067 * @data: pointer to adapter cast into an unsigned long
2068 **/
2069 static void igb_watchdog(unsigned long data)
2070 {
2071 struct igb_adapter *adapter = (struct igb_adapter *)data;
2072 /* Do the rest outside of interrupt context */
2073 schedule_work(&adapter->watchdog_task);
2074 }
2075
2076 static void igb_watchdog_task(struct work_struct *work)
2077 {
2078 struct igb_adapter *adapter = container_of(work,
2079 struct igb_adapter, watchdog_task);
2080 struct e1000_hw *hw = &adapter->hw;
2081
2082 struct net_device *netdev = adapter->netdev;
2083 struct igb_ring *tx_ring = adapter->tx_ring;
2084 struct e1000_mac_info *mac = &adapter->hw.mac;
2085 u32 link;
2086 s32 ret_val;
2087
2088 if ((netif_carrier_ok(netdev)) &&
2089 (rd32(E1000_STATUS) & E1000_STATUS_LU))
2090 goto link_up;
2091
2092 ret_val = hw->mac.ops.check_for_link(&adapter->hw);
2093 if ((ret_val == E1000_ERR_PHY) &&
2094 (hw->phy.type == e1000_phy_igp_3) &&
2095 (rd32(E1000_CTRL) &
2096 E1000_PHY_CTRL_GBE_DISABLE))
2097 dev_info(&adapter->pdev->dev,
2098 "Gigabit has been disabled, downgrading speed\n");
2099
2100 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
2101 !(rd32(E1000_TXCW) & E1000_TXCW_ANE))
2102 link = mac->serdes_has_link;
2103 else
2104 link = rd32(E1000_STATUS) &
2105 E1000_STATUS_LU;
2106
2107 if (link) {
2108 if (!netif_carrier_ok(netdev)) {
2109 u32 ctrl;
2110 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2111 &adapter->link_speed,
2112 &adapter->link_duplex);
2113
2114 ctrl = rd32(E1000_CTRL);
2115 dev_info(&adapter->pdev->dev,
2116 "NIC Link is Up %d Mbps %s, "
2117 "Flow Control: %s\n",
2118 adapter->link_speed,
2119 adapter->link_duplex == FULL_DUPLEX ?
2120 "Full Duplex" : "Half Duplex",
2121 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2122 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2123 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2124 E1000_CTRL_TFCE) ? "TX" : "None")));
2125
2126 /* tweak tx_queue_len according to speed/duplex and
2127 * adjust the timeout factor */
2128 netdev->tx_queue_len = adapter->tx_queue_len;
2129 adapter->tx_timeout_factor = 1;
2130 switch (adapter->link_speed) {
2131 case SPEED_10:
2132 netdev->tx_queue_len = 10;
2133 adapter->tx_timeout_factor = 14;
2134 break;
2135 case SPEED_100:
2136 netdev->tx_queue_len = 100;
2137 /* maybe add some timeout factor ? */
2138 break;
2139 }
2140
2141 netif_carrier_on(netdev);
2142 netif_wake_queue(netdev);
2143
2144 if (!test_bit(__IGB_DOWN, &adapter->state))
2145 mod_timer(&adapter->phy_info_timer,
2146 round_jiffies(jiffies + 2 * HZ));
2147 }
2148 } else {
2149 if (netif_carrier_ok(netdev)) {
2150 adapter->link_speed = 0;
2151 adapter->link_duplex = 0;
2152 dev_info(&adapter->pdev->dev, "NIC Link is Down\n");
2153 netif_carrier_off(netdev);
2154 netif_stop_queue(netdev);
2155 if (!test_bit(__IGB_DOWN, &adapter->state))
2156 mod_timer(&adapter->phy_info_timer,
2157 round_jiffies(jiffies + 2 * HZ));
2158 }
2159 }
2160
2161 link_up:
2162 igb_update_stats(adapter);
2163
2164 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2165 adapter->tpt_old = adapter->stats.tpt;
2166 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
2167 adapter->colc_old = adapter->stats.colc;
2168
2169 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2170 adapter->gorc_old = adapter->stats.gorc;
2171 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2172 adapter->gotc_old = adapter->stats.gotc;
2173
2174 igb_update_adaptive(&adapter->hw);
2175
2176 if (!netif_carrier_ok(netdev)) {
2177 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2178 /* We've lost link, so the controller stops DMA,
2179 * but we've got queued Tx work that's never going
2180 * to get done, so reset controller to flush Tx.
2181 * (Do the reset outside of interrupt context). */
2182 adapter->tx_timeout_count++;
2183 schedule_work(&adapter->reset_task);
2184 }
2185 }
2186
2187 /* Cause software interrupt to ensure rx ring is cleaned */
2188 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2189
2190 /* Force detection of hung controller every watchdog period */
2191 tx_ring->detect_tx_hung = true;
2192
2193 /* Reset the timer */
2194 if (!test_bit(__IGB_DOWN, &adapter->state))
2195 mod_timer(&adapter->watchdog_timer,
2196 round_jiffies(jiffies + 2 * HZ));
2197 }
2198
2199 enum latency_range {
2200 lowest_latency = 0,
2201 low_latency = 1,
2202 bulk_latency = 2,
2203 latency_invalid = 255
2204 };
2205
2206
2207 static void igb_lower_rx_eitr(struct igb_adapter *adapter,
2208 struct igb_ring *rx_ring)
2209 {
2210 struct e1000_hw *hw = &adapter->hw;
2211 int new_val;
2212
2213 new_val = rx_ring->itr_val / 2;
2214 if (new_val < IGB_MIN_DYN_ITR)
2215 new_val = IGB_MIN_DYN_ITR;
2216
2217 if (new_val != rx_ring->itr_val) {
2218 rx_ring->itr_val = new_val;
2219 wr32(rx_ring->itr_register,
2220 1000000000 / (new_val * 256));
2221 }
2222 }
2223
2224 static void igb_raise_rx_eitr(struct igb_adapter *adapter,
2225 struct igb_ring *rx_ring)
2226 {
2227 struct e1000_hw *hw = &adapter->hw;
2228 int new_val;
2229
2230 new_val = rx_ring->itr_val * 2;
2231 if (new_val > IGB_MAX_DYN_ITR)
2232 new_val = IGB_MAX_DYN_ITR;
2233
2234 if (new_val != rx_ring->itr_val) {
2235 rx_ring->itr_val = new_val;
2236 wr32(rx_ring->itr_register,
2237 1000000000 / (new_val * 256));
2238 }
2239 }
2240
2241 /**
2242 * igb_update_itr - update the dynamic ITR value based on statistics
2243 * Stores a new ITR value based on packets and byte
2244 * counts during the last interrupt. The advantage of per interrupt
2245 * computation is faster updates and more accurate ITR for the current
2246 * traffic pattern. Constants in this function were computed
2247 * based on theoretical maximum wire speed and thresholds were set based
2248 * on testing data as well as attempting to minimize response time
2249 * while increasing bulk throughput.
2250 * this functionality is controlled by the InterruptThrottleRate module
2251 * parameter (see igb_param.c)
2252 * NOTE: These calculations are only valid when operating in a single-
2253 * queue environment.
2254 * @adapter: pointer to adapter
2255 * @itr_setting: current adapter->itr
2256 * @packets: the number of packets during this measurement interval
2257 * @bytes: the number of bytes during this measurement interval
2258 **/
2259 static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2260 int packets, int bytes)
2261 {
2262 unsigned int retval = itr_setting;
2263
2264 if (packets == 0)
2265 goto update_itr_done;
2266
2267 switch (itr_setting) {
2268 case lowest_latency:
2269 /* handle TSO and jumbo frames */
2270 if (bytes/packets > 8000)
2271 retval = bulk_latency;
2272 else if ((packets < 5) && (bytes > 512))
2273 retval = low_latency;
2274 break;
2275 case low_latency: /* 50 usec aka 20000 ints/s */
2276 if (bytes > 10000) {
2277 /* this if handles the TSO accounting */
2278 if (bytes/packets > 8000) {
2279 retval = bulk_latency;
2280 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2281 retval = bulk_latency;
2282 } else if ((packets > 35)) {
2283 retval = lowest_latency;
2284 }
2285 } else if (bytes/packets > 2000) {
2286 retval = bulk_latency;
2287 } else if (packets <= 2 && bytes < 512) {
2288 retval = lowest_latency;
2289 }
2290 break;
2291 case bulk_latency: /* 250 usec aka 4000 ints/s */
2292 if (bytes > 25000) {
2293 if (packets > 35)
2294 retval = low_latency;
2295 } else if (bytes < 6000) {
2296 retval = low_latency;
2297 }
2298 break;
2299 }
2300
2301 update_itr_done:
2302 return retval;
2303 }
2304
2305 static void igb_set_itr(struct igb_adapter *adapter, u16 itr_register,
2306 int rx_only)
2307 {
2308 u16 current_itr;
2309 u32 new_itr = adapter->itr;
2310
2311 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2312 if (adapter->link_speed != SPEED_1000) {
2313 current_itr = 0;
2314 new_itr = 4000;
2315 goto set_itr_now;
2316 }
2317
2318 adapter->rx_itr = igb_update_itr(adapter,
2319 adapter->rx_itr,
2320 adapter->rx_ring->total_packets,
2321 adapter->rx_ring->total_bytes);
2322 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2323 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2324 adapter->rx_itr = low_latency;
2325
2326 if (!rx_only) {
2327 adapter->tx_itr = igb_update_itr(adapter,
2328 adapter->tx_itr,
2329 adapter->tx_ring->total_packets,
2330 adapter->tx_ring->total_bytes);
2331 /* conservative mode (itr 3) eliminates the
2332 * lowest_latency setting */
2333 if (adapter->itr_setting == 3 &&
2334 adapter->tx_itr == lowest_latency)
2335 adapter->tx_itr = low_latency;
2336
2337 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2338 } else {
2339 current_itr = adapter->rx_itr;
2340 }
2341
2342 switch (current_itr) {
2343 /* counts and packets in update_itr are dependent on these numbers */
2344 case lowest_latency:
2345 new_itr = 70000;
2346 break;
2347 case low_latency:
2348 new_itr = 20000; /* aka hwitr = ~200 */
2349 break;
2350 case bulk_latency:
2351 new_itr = 4000;
2352 break;
2353 default:
2354 break;
2355 }
2356
2357 set_itr_now:
2358 if (new_itr != adapter->itr) {
2359 /* this attempts to bias the interrupt rate towards Bulk
2360 * by adding intermediate steps when interrupt rate is
2361 * increasing */
2362 new_itr = new_itr > adapter->itr ?
2363 min(adapter->itr + (new_itr >> 2), new_itr) :
2364 new_itr;
2365 /* Don't write the value here; it resets the adapter's
2366 * internal timer, and causes us to delay far longer than
2367 * we should between interrupts. Instead, we write the ITR
2368 * value at the beginning of the next interrupt so the timing
2369 * ends up being correct.
2370 */
2371 adapter->itr = new_itr;
2372 adapter->set_itr = 1;
2373 }
2374
2375 return;
2376 }
2377
2378
2379 #define IGB_TX_FLAGS_CSUM 0x00000001
2380 #define IGB_TX_FLAGS_VLAN 0x00000002
2381 #define IGB_TX_FLAGS_TSO 0x00000004
2382 #define IGB_TX_FLAGS_IPV4 0x00000008
2383 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2384 #define IGB_TX_FLAGS_VLAN_SHIFT 16
2385
2386 static inline int igb_tso_adv(struct igb_adapter *adapter,
2387 struct igb_ring *tx_ring,
2388 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2389 {
2390 struct e1000_adv_tx_context_desc *context_desc;
2391 unsigned int i;
2392 int err;
2393 struct igb_buffer *buffer_info;
2394 u32 info = 0, tu_cmd = 0;
2395 u32 mss_l4len_idx, l4len;
2396 *hdr_len = 0;
2397
2398 if (skb_header_cloned(skb)) {
2399 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2400 if (err)
2401 return err;
2402 }
2403
2404 l4len = tcp_hdrlen(skb);
2405 *hdr_len += l4len;
2406
2407 if (skb->protocol == htons(ETH_P_IP)) {
2408 struct iphdr *iph = ip_hdr(skb);
2409 iph->tot_len = 0;
2410 iph->check = 0;
2411 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2412 iph->daddr, 0,
2413 IPPROTO_TCP,
2414 0);
2415 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2416 ipv6_hdr(skb)->payload_len = 0;
2417 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2418 &ipv6_hdr(skb)->daddr,
2419 0, IPPROTO_TCP, 0);
2420 }
2421
2422 i = tx_ring->next_to_use;
2423
2424 buffer_info = &tx_ring->buffer_info[i];
2425 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2426 /* VLAN MACLEN IPLEN */
2427 if (tx_flags & IGB_TX_FLAGS_VLAN)
2428 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2429 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2430 *hdr_len += skb_network_offset(skb);
2431 info |= skb_network_header_len(skb);
2432 *hdr_len += skb_network_header_len(skb);
2433 context_desc->vlan_macip_lens = cpu_to_le32(info);
2434
2435 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2436 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2437
2438 if (skb->protocol == htons(ETH_P_IP))
2439 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2440 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2441
2442 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2443
2444 /* MSS L4LEN IDX */
2445 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2446 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2447
2448 /* Context index must be unique per ring. Luckily, so is the interrupt
2449 * mask value. */
2450 mss_l4len_idx |= tx_ring->eims_value >> 4;
2451
2452 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2453 context_desc->seqnum_seed = 0;
2454
2455 buffer_info->time_stamp = jiffies;
2456 buffer_info->dma = 0;
2457 i++;
2458 if (i == tx_ring->count)
2459 i = 0;
2460
2461 tx_ring->next_to_use = i;
2462
2463 return true;
2464 }
2465
2466 static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2467 struct igb_ring *tx_ring,
2468 struct sk_buff *skb, u32 tx_flags)
2469 {
2470 struct e1000_adv_tx_context_desc *context_desc;
2471 unsigned int i;
2472 struct igb_buffer *buffer_info;
2473 u32 info = 0, tu_cmd = 0;
2474
2475 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2476 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2477 i = tx_ring->next_to_use;
2478 buffer_info = &tx_ring->buffer_info[i];
2479 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2480
2481 if (tx_flags & IGB_TX_FLAGS_VLAN)
2482 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2483 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2484 if (skb->ip_summed == CHECKSUM_PARTIAL)
2485 info |= skb_network_header_len(skb);
2486
2487 context_desc->vlan_macip_lens = cpu_to_le32(info);
2488
2489 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2490
2491 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2492 switch (skb->protocol) {
2493 case __constant_htons(ETH_P_IP):
2494 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2495 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2496 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2497 break;
2498 case __constant_htons(ETH_P_IPV6):
2499 /* XXX what about other V6 headers?? */
2500 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2501 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2502 break;
2503 default:
2504 if (unlikely(net_ratelimit()))
2505 dev_warn(&adapter->pdev->dev,
2506 "partial checksum but proto=%x!\n",
2507 skb->protocol);
2508 break;
2509 }
2510 }
2511
2512 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2513 context_desc->seqnum_seed = 0;
2514 context_desc->mss_l4len_idx =
2515 cpu_to_le32(tx_ring->eims_value >> 4);
2516
2517 buffer_info->time_stamp = jiffies;
2518 buffer_info->dma = 0;
2519
2520 i++;
2521 if (i == tx_ring->count)
2522 i = 0;
2523 tx_ring->next_to_use = i;
2524
2525 return true;
2526 }
2527
2528
2529 return false;
2530 }
2531
2532 #define IGB_MAX_TXD_PWR 16
2533 #define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
2534
2535 static inline int igb_tx_map_adv(struct igb_adapter *adapter,
2536 struct igb_ring *tx_ring,
2537 struct sk_buff *skb)
2538 {
2539 struct igb_buffer *buffer_info;
2540 unsigned int len = skb_headlen(skb);
2541 unsigned int count = 0, i;
2542 unsigned int f;
2543
2544 i = tx_ring->next_to_use;
2545
2546 buffer_info = &tx_ring->buffer_info[i];
2547 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2548 buffer_info->length = len;
2549 /* set time_stamp *before* dma to help avoid a possible race */
2550 buffer_info->time_stamp = jiffies;
2551 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2552 PCI_DMA_TODEVICE);
2553 count++;
2554 i++;
2555 if (i == tx_ring->count)
2556 i = 0;
2557
2558 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2559 struct skb_frag_struct *frag;
2560
2561 frag = &skb_shinfo(skb)->frags[f];
2562 len = frag->size;
2563
2564 buffer_info = &tx_ring->buffer_info[i];
2565 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2566 buffer_info->length = len;
2567 buffer_info->time_stamp = jiffies;
2568 buffer_info->dma = pci_map_page(adapter->pdev,
2569 frag->page,
2570 frag->page_offset,
2571 len,
2572 PCI_DMA_TODEVICE);
2573
2574 count++;
2575 i++;
2576 if (i == tx_ring->count)
2577 i = 0;
2578 }
2579
2580 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2581 tx_ring->buffer_info[i].skb = skb;
2582
2583 return count;
2584 }
2585
2586 static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2587 struct igb_ring *tx_ring,
2588 int tx_flags, int count, u32 paylen,
2589 u8 hdr_len)
2590 {
2591 union e1000_adv_tx_desc *tx_desc = NULL;
2592 struct igb_buffer *buffer_info;
2593 u32 olinfo_status = 0, cmd_type_len;
2594 unsigned int i;
2595
2596 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2597 E1000_ADVTXD_DCMD_DEXT);
2598
2599 if (tx_flags & IGB_TX_FLAGS_VLAN)
2600 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2601
2602 if (tx_flags & IGB_TX_FLAGS_TSO) {
2603 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2604
2605 /* insert tcp checksum */
2606 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2607
2608 /* insert ip checksum */
2609 if (tx_flags & IGB_TX_FLAGS_IPV4)
2610 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2611
2612 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2613 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2614 }
2615
2616 if (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2617 IGB_TX_FLAGS_VLAN))
2618 olinfo_status |= tx_ring->eims_value >> 4;
2619
2620 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2621
2622 i = tx_ring->next_to_use;
2623 while (count--) {
2624 buffer_info = &tx_ring->buffer_info[i];
2625 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
2626 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
2627 tx_desc->read.cmd_type_len =
2628 cpu_to_le32(cmd_type_len | buffer_info->length);
2629 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2630 i++;
2631 if (i == tx_ring->count)
2632 i = 0;
2633 }
2634
2635 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
2636 /* Force memory writes to complete before letting h/w
2637 * know there are new descriptors to fetch. (Only
2638 * applicable for weak-ordered memory model archs,
2639 * such as IA-64). */
2640 wmb();
2641
2642 tx_ring->next_to_use = i;
2643 writel(i, adapter->hw.hw_addr + tx_ring->tail);
2644 /* we need this if more than one processor can write to our tail
2645 * at a time, it syncronizes IO on IA64/Altix systems */
2646 mmiowb();
2647 }
2648
2649 static int __igb_maybe_stop_tx(struct net_device *netdev,
2650 struct igb_ring *tx_ring, int size)
2651 {
2652 struct igb_adapter *adapter = netdev_priv(netdev);
2653
2654 netif_stop_queue(netdev);
2655 /* Herbert's original patch had:
2656 * smp_mb__after_netif_stop_queue();
2657 * but since that doesn't exist yet, just open code it. */
2658 smp_mb();
2659
2660 /* We need to check again in a case another CPU has just
2661 * made room available. */
2662 if (IGB_DESC_UNUSED(tx_ring) < size)
2663 return -EBUSY;
2664
2665 /* A reprieve! */
2666 netif_start_queue(netdev);
2667 ++adapter->restart_queue;
2668 return 0;
2669 }
2670
2671 static int igb_maybe_stop_tx(struct net_device *netdev,
2672 struct igb_ring *tx_ring, int size)
2673 {
2674 if (IGB_DESC_UNUSED(tx_ring) >= size)
2675 return 0;
2676 return __igb_maybe_stop_tx(netdev, tx_ring, size);
2677 }
2678
2679 #define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
2680
2681 static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2682 struct net_device *netdev,
2683 struct igb_ring *tx_ring)
2684 {
2685 struct igb_adapter *adapter = netdev_priv(netdev);
2686 unsigned int tx_flags = 0;
2687 unsigned int len;
2688 unsigned long irq_flags;
2689 u8 hdr_len = 0;
2690 int tso = 0;
2691
2692 len = skb_headlen(skb);
2693
2694 if (test_bit(__IGB_DOWN, &adapter->state)) {
2695 dev_kfree_skb_any(skb);
2696 return NETDEV_TX_OK;
2697 }
2698
2699 if (skb->len <= 0) {
2700 dev_kfree_skb_any(skb);
2701 return NETDEV_TX_OK;
2702 }
2703
2704 if (!spin_trylock_irqsave(&tx_ring->tx_lock, irq_flags))
2705 /* Collision - tell upper layer to requeue */
2706 return NETDEV_TX_LOCKED;
2707
2708 /* need: 1 descriptor per page,
2709 * + 2 desc gap to keep tail from touching head,
2710 * + 1 desc for skb->data,
2711 * + 1 desc for context descriptor,
2712 * otherwise try next time */
2713 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2714 /* this is a hard error */
2715 spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags);
2716 return NETDEV_TX_BUSY;
2717 }
2718
2719 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2720 tx_flags |= IGB_TX_FLAGS_VLAN;
2721 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2722 }
2723
2724 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
2725 &hdr_len) : 0;
2726
2727 if (tso < 0) {
2728 dev_kfree_skb_any(skb);
2729 spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags);
2730 return NETDEV_TX_OK;
2731 }
2732
2733 if (tso)
2734 tx_flags |= IGB_TX_FLAGS_TSO;
2735 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
2736 if (skb->ip_summed == CHECKSUM_PARTIAL)
2737 tx_flags |= IGB_TX_FLAGS_CSUM;
2738
2739 if (skb->protocol == htons(ETH_P_IP))
2740 tx_flags |= IGB_TX_FLAGS_IPV4;
2741
2742 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
2743 igb_tx_map_adv(adapter, tx_ring, skb),
2744 skb->len, hdr_len);
2745
2746 netdev->trans_start = jiffies;
2747
2748 /* Make sure there is space in the ring for the next send. */
2749 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
2750
2751 spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags);
2752 return NETDEV_TX_OK;
2753 }
2754
2755 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
2756 {
2757 struct igb_adapter *adapter = netdev_priv(netdev);
2758 struct igb_ring *tx_ring = &adapter->tx_ring[0];
2759
2760 /* This goes back to the question of how to logically map a tx queue
2761 * to a flow. Right now, performance is impacted slightly negatively
2762 * if using multiple tx queues. If the stack breaks away from a
2763 * single qdisc implementation, we can look at this again. */
2764 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
2765 }
2766
2767 /**
2768 * igb_tx_timeout - Respond to a Tx Hang
2769 * @netdev: network interface device structure
2770 **/
2771 static void igb_tx_timeout(struct net_device *netdev)
2772 {
2773 struct igb_adapter *adapter = netdev_priv(netdev);
2774 struct e1000_hw *hw = &adapter->hw;
2775
2776 /* Do the reset outside of interrupt context */
2777 adapter->tx_timeout_count++;
2778 schedule_work(&adapter->reset_task);
2779 wr32(E1000_EICS, adapter->eims_enable_mask &
2780 ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER));
2781 }
2782
2783 static void igb_reset_task(struct work_struct *work)
2784 {
2785 struct igb_adapter *adapter;
2786 adapter = container_of(work, struct igb_adapter, reset_task);
2787
2788 igb_reinit_locked(adapter);
2789 }
2790
2791 /**
2792 * igb_get_stats - Get System Network Statistics
2793 * @netdev: network interface device structure
2794 *
2795 * Returns the address of the device statistics structure.
2796 * The statistics are actually updated from the timer callback.
2797 **/
2798 static struct net_device_stats *
2799 igb_get_stats(struct net_device *netdev)
2800 {
2801 struct igb_adapter *adapter = netdev_priv(netdev);
2802
2803 /* only return the current stats */
2804 return &adapter->net_stats;
2805 }
2806
2807 /**
2808 * igb_change_mtu - Change the Maximum Transfer Unit
2809 * @netdev: network interface device structure
2810 * @new_mtu: new value for maximum frame size
2811 *
2812 * Returns 0 on success, negative on failure
2813 **/
2814 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
2815 {
2816 struct igb_adapter *adapter = netdev_priv(netdev);
2817 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2818
2819 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2820 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
2821 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
2822 return -EINVAL;
2823 }
2824
2825 #define MAX_STD_JUMBO_FRAME_SIZE 9234
2826 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
2827 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
2828 return -EINVAL;
2829 }
2830
2831 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
2832 msleep(1);
2833 /* igb_down has a dependency on max_frame_size */
2834 adapter->max_frame_size = max_frame;
2835 if (netif_running(netdev))
2836 igb_down(adapter);
2837
2838 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
2839 * means we reserve 2 more, this pushes us to allocate from the next
2840 * larger slab size.
2841 * i.e. RXBUFFER_2048 --> size-4096 slab
2842 */
2843
2844 if (max_frame <= IGB_RXBUFFER_256)
2845 adapter->rx_buffer_len = IGB_RXBUFFER_256;
2846 else if (max_frame <= IGB_RXBUFFER_512)
2847 adapter->rx_buffer_len = IGB_RXBUFFER_512;
2848 else if (max_frame <= IGB_RXBUFFER_1024)
2849 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
2850 else if (max_frame <= IGB_RXBUFFER_2048)
2851 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
2852 else
2853 adapter->rx_buffer_len = IGB_RXBUFFER_4096;
2854 /* adjust allocation if LPE protects us, and we aren't using SBP */
2855 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
2856 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
2857 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2858
2859 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
2860 netdev->mtu, new_mtu);
2861 netdev->mtu = new_mtu;
2862
2863 if (netif_running(netdev))
2864 igb_up(adapter);
2865 else
2866 igb_reset(adapter);
2867
2868 clear_bit(__IGB_RESETTING, &adapter->state);
2869
2870 return 0;
2871 }
2872
2873 /**
2874 * igb_update_stats - Update the board statistics counters
2875 * @adapter: board private structure
2876 **/
2877
2878 void igb_update_stats(struct igb_adapter *adapter)
2879 {
2880 struct e1000_hw *hw = &adapter->hw;
2881 struct pci_dev *pdev = adapter->pdev;
2882 u16 phy_tmp;
2883
2884 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
2885
2886 /*
2887 * Prevent stats update while adapter is being reset, or if the pci
2888 * connection is down.
2889 */
2890 if (adapter->link_speed == 0)
2891 return;
2892 if (pci_channel_offline(pdev))
2893 return;
2894
2895 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
2896 adapter->stats.gprc += rd32(E1000_GPRC);
2897 adapter->stats.gorc += rd32(E1000_GORCL);
2898 rd32(E1000_GORCH); /* clear GORCL */
2899 adapter->stats.bprc += rd32(E1000_BPRC);
2900 adapter->stats.mprc += rd32(E1000_MPRC);
2901 adapter->stats.roc += rd32(E1000_ROC);
2902
2903 adapter->stats.prc64 += rd32(E1000_PRC64);
2904 adapter->stats.prc127 += rd32(E1000_PRC127);
2905 adapter->stats.prc255 += rd32(E1000_PRC255);
2906 adapter->stats.prc511 += rd32(E1000_PRC511);
2907 adapter->stats.prc1023 += rd32(E1000_PRC1023);
2908 adapter->stats.prc1522 += rd32(E1000_PRC1522);
2909 adapter->stats.symerrs += rd32(E1000_SYMERRS);
2910 adapter->stats.sec += rd32(E1000_SEC);
2911
2912 adapter->stats.mpc += rd32(E1000_MPC);
2913 adapter->stats.scc += rd32(E1000_SCC);
2914 adapter->stats.ecol += rd32(E1000_ECOL);
2915 adapter->stats.mcc += rd32(E1000_MCC);
2916 adapter->stats.latecol += rd32(E1000_LATECOL);
2917 adapter->stats.dc += rd32(E1000_DC);
2918 adapter->stats.rlec += rd32(E1000_RLEC);
2919 adapter->stats.xonrxc += rd32(E1000_XONRXC);
2920 adapter->stats.xontxc += rd32(E1000_XONTXC);
2921 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
2922 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
2923 adapter->stats.fcruc += rd32(E1000_FCRUC);
2924 adapter->stats.gptc += rd32(E1000_GPTC);
2925 adapter->stats.gotc += rd32(E1000_GOTCL);
2926 rd32(E1000_GOTCH); /* clear GOTCL */
2927 adapter->stats.rnbc += rd32(E1000_RNBC);
2928 adapter->stats.ruc += rd32(E1000_RUC);
2929 adapter->stats.rfc += rd32(E1000_RFC);
2930 adapter->stats.rjc += rd32(E1000_RJC);
2931 adapter->stats.tor += rd32(E1000_TORH);
2932 adapter->stats.tot += rd32(E1000_TOTH);
2933 adapter->stats.tpr += rd32(E1000_TPR);
2934
2935 adapter->stats.ptc64 += rd32(E1000_PTC64);
2936 adapter->stats.ptc127 += rd32(E1000_PTC127);
2937 adapter->stats.ptc255 += rd32(E1000_PTC255);
2938 adapter->stats.ptc511 += rd32(E1000_PTC511);
2939 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
2940 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
2941
2942 adapter->stats.mptc += rd32(E1000_MPTC);
2943 adapter->stats.bptc += rd32(E1000_BPTC);
2944
2945 /* used for adaptive IFS */
2946
2947 hw->mac.tx_packet_delta = rd32(E1000_TPT);
2948 adapter->stats.tpt += hw->mac.tx_packet_delta;
2949 hw->mac.collision_delta = rd32(E1000_COLC);
2950 adapter->stats.colc += hw->mac.collision_delta;
2951
2952 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
2953 adapter->stats.rxerrc += rd32(E1000_RXERRC);
2954 adapter->stats.tncrs += rd32(E1000_TNCRS);
2955 adapter->stats.tsctc += rd32(E1000_TSCTC);
2956 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
2957
2958 adapter->stats.iac += rd32(E1000_IAC);
2959 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
2960 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
2961 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
2962 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
2963 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
2964 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
2965 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
2966 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
2967
2968 /* Fill out the OS statistics structure */
2969 adapter->net_stats.multicast = adapter->stats.mprc;
2970 adapter->net_stats.collisions = adapter->stats.colc;
2971
2972 /* Rx Errors */
2973
2974 /* RLEC on some newer hardware can be incorrect so build
2975 * our own version based on RUC and ROC */
2976 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
2977 adapter->stats.crcerrs + adapter->stats.algnerrc +
2978 adapter->stats.ruc + adapter->stats.roc +
2979 adapter->stats.cexterr;
2980 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
2981 adapter->stats.roc;
2982 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
2983 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
2984 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
2985
2986 /* Tx Errors */
2987 adapter->net_stats.tx_errors = adapter->stats.ecol +
2988 adapter->stats.latecol;
2989 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
2990 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
2991 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
2992
2993 /* Tx Dropped needs to be maintained elsewhere */
2994
2995 /* Phy Stats */
2996 if (hw->phy.media_type == e1000_media_type_copper) {
2997 if ((adapter->link_speed == SPEED_1000) &&
2998 (!hw->phy.ops.read_phy_reg(hw, PHY_1000T_STATUS,
2999 &phy_tmp))) {
3000 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3001 adapter->phy_stats.idle_errors += phy_tmp;
3002 }
3003 }
3004
3005 /* Management Stats */
3006 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3007 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3008 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3009 }
3010
3011
3012 static irqreturn_t igb_msix_other(int irq, void *data)
3013 {
3014 struct net_device *netdev = data;
3015 struct igb_adapter *adapter = netdev_priv(netdev);
3016 struct e1000_hw *hw = &adapter->hw;
3017 u32 eicr;
3018 /* disable interrupts from the "other" bit, avoid re-entry */
3019 wr32(E1000_EIMC, E1000_EIMS_OTHER);
3020
3021 eicr = rd32(E1000_EICR);
3022
3023 if (eicr & E1000_EIMS_OTHER) {
3024 u32 icr = rd32(E1000_ICR);
3025 /* reading ICR causes bit 31 of EICR to be cleared */
3026 if (!(icr & E1000_ICR_LSC))
3027 goto no_link_interrupt;
3028 hw->mac.get_link_status = 1;
3029 /* guard against interrupt when we're going down */
3030 if (!test_bit(__IGB_DOWN, &adapter->state))
3031 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3032 }
3033
3034 no_link_interrupt:
3035 wr32(E1000_IMS, E1000_IMS_LSC);
3036 wr32(E1000_EIMS, E1000_EIMS_OTHER);
3037
3038 return IRQ_HANDLED;
3039 }
3040
3041 static irqreturn_t igb_msix_tx(int irq, void *data)
3042 {
3043 struct igb_ring *tx_ring = data;
3044 struct igb_adapter *adapter = tx_ring->adapter;
3045 struct e1000_hw *hw = &adapter->hw;
3046
3047 if (!tx_ring->itr_val)
3048 wr32(E1000_EIMC, tx_ring->eims_value);
3049
3050 tx_ring->total_bytes = 0;
3051 tx_ring->total_packets = 0;
3052 if (!igb_clean_tx_irq(adapter, tx_ring))
3053 /* Ring was not completely cleaned, so fire another interrupt */
3054 wr32(E1000_EICS, tx_ring->eims_value);
3055
3056 if (!tx_ring->itr_val)
3057 wr32(E1000_EIMS, tx_ring->eims_value);
3058 return IRQ_HANDLED;
3059 }
3060
3061 static irqreturn_t igb_msix_rx(int irq, void *data)
3062 {
3063 struct igb_ring *rx_ring = data;
3064 struct igb_adapter *adapter = rx_ring->adapter;
3065 struct e1000_hw *hw = &adapter->hw;
3066
3067 if (!rx_ring->itr_val)
3068 wr32(E1000_EIMC, rx_ring->eims_value);
3069
3070 if (netif_rx_schedule_prep(adapter->netdev, &rx_ring->napi)) {
3071 rx_ring->total_bytes = 0;
3072 rx_ring->total_packets = 0;
3073 rx_ring->no_itr_adjust = 0;
3074 __netif_rx_schedule(adapter->netdev, &rx_ring->napi);
3075 } else {
3076 if (!rx_ring->no_itr_adjust) {
3077 igb_lower_rx_eitr(adapter, rx_ring);
3078 rx_ring->no_itr_adjust = 1;
3079 }
3080 }
3081
3082 return IRQ_HANDLED;
3083 }
3084
3085
3086 /**
3087 * igb_intr_msi - Interrupt Handler
3088 * @irq: interrupt number
3089 * @data: pointer to a network interface device structure
3090 **/
3091 static irqreturn_t igb_intr_msi(int irq, void *data)
3092 {
3093 struct net_device *netdev = data;
3094 struct igb_adapter *adapter = netdev_priv(netdev);
3095 struct napi_struct *napi = &adapter->napi;
3096 struct e1000_hw *hw = &adapter->hw;
3097 /* read ICR disables interrupts using IAM */
3098 u32 icr = rd32(E1000_ICR);
3099
3100 /* Write the ITR value calculated at the end of the
3101 * previous interrupt.
3102 */
3103 if (adapter->set_itr) {
3104 wr32(E1000_ITR,
3105 1000000000 / (adapter->itr * 256));
3106 adapter->set_itr = 0;
3107 }
3108
3109 /* read ICR disables interrupts using IAM */
3110 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3111 hw->mac.get_link_status = 1;
3112 if (!test_bit(__IGB_DOWN, &adapter->state))
3113 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3114 }
3115
3116 if (netif_rx_schedule_prep(netdev, napi)) {
3117 adapter->tx_ring->total_bytes = 0;
3118 adapter->tx_ring->total_packets = 0;
3119 adapter->rx_ring->total_bytes = 0;
3120 adapter->rx_ring->total_packets = 0;
3121 __netif_rx_schedule(netdev, napi);
3122 }
3123
3124 return IRQ_HANDLED;
3125 }
3126
3127 /**
3128 * igb_intr - Interrupt Handler
3129 * @irq: interrupt number
3130 * @data: pointer to a network interface device structure
3131 **/
3132 static irqreturn_t igb_intr(int irq, void *data)
3133 {
3134 struct net_device *netdev = data;
3135 struct igb_adapter *adapter = netdev_priv(netdev);
3136 struct napi_struct *napi = &adapter->napi;
3137 struct e1000_hw *hw = &adapter->hw;
3138 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3139 * need for the IMC write */
3140 u32 icr = rd32(E1000_ICR);
3141 u32 eicr = 0;
3142 if (!icr)
3143 return IRQ_NONE; /* Not our interrupt */
3144
3145 /* Write the ITR value calculated at the end of the
3146 * previous interrupt.
3147 */
3148 if (adapter->set_itr) {
3149 wr32(E1000_ITR,
3150 1000000000 / (adapter->itr * 256));
3151 adapter->set_itr = 0;
3152 }
3153
3154 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3155 * not set, then the adapter didn't send an interrupt */
3156 if (!(icr & E1000_ICR_INT_ASSERTED))
3157 return IRQ_NONE;
3158
3159 eicr = rd32(E1000_EICR);
3160
3161 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3162 hw->mac.get_link_status = 1;
3163 /* guard against interrupt when we're going down */
3164 if (!test_bit(__IGB_DOWN, &adapter->state))
3165 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3166 }
3167
3168 if (netif_rx_schedule_prep(netdev, napi)) {
3169 adapter->tx_ring->total_bytes = 0;
3170 adapter->rx_ring->total_bytes = 0;
3171 adapter->tx_ring->total_packets = 0;
3172 adapter->rx_ring->total_packets = 0;
3173 __netif_rx_schedule(netdev, napi);
3174 }
3175
3176 return IRQ_HANDLED;
3177 }
3178
3179 /**
3180 * igb_clean - NAPI Rx polling callback
3181 * @adapter: board private structure
3182 **/
3183 static int igb_clean(struct napi_struct *napi, int budget)
3184 {
3185 struct igb_adapter *adapter = container_of(napi, struct igb_adapter,
3186 napi);
3187 struct net_device *netdev = adapter->netdev;
3188 int tx_clean_complete = 1, work_done = 0;
3189 int i;
3190
3191 /* Must NOT use netdev_priv macro here. */
3192 adapter = netdev->priv;
3193
3194 /* Keep link state information with original netdev */
3195 if (!netif_carrier_ok(netdev))
3196 goto quit_polling;
3197
3198 /* igb_clean is called per-cpu. This lock protects tx_ring[i] from
3199 * being cleaned by multiple cpus simultaneously. A failure obtaining
3200 * the lock means tx_ring[i] is currently being cleaned anyway. */
3201 for (i = 0; i < adapter->num_tx_queues; i++) {
3202 if (spin_trylock(&adapter->tx_ring[i].tx_clean_lock)) {
3203 tx_clean_complete &= igb_clean_tx_irq(adapter,
3204 &adapter->tx_ring[i]);
3205 spin_unlock(&adapter->tx_ring[i].tx_clean_lock);
3206 }
3207 }
3208
3209 for (i = 0; i < adapter->num_rx_queues; i++)
3210 igb_clean_rx_irq_adv(adapter, &adapter->rx_ring[i], &work_done,
3211 adapter->rx_ring[i].napi.weight);
3212
3213 /* If no Tx and not enough Rx work done, exit the polling mode */
3214 if ((tx_clean_complete && (work_done < budget)) ||
3215 !netif_running(netdev)) {
3216 quit_polling:
3217 if (adapter->itr_setting & 3)
3218 igb_set_itr(adapter, E1000_ITR, false);
3219 netif_rx_complete(netdev, napi);
3220 if (!test_bit(__IGB_DOWN, &adapter->state))
3221 igb_irq_enable(adapter);
3222 return 0;
3223 }
3224
3225 return 1;
3226 }
3227
3228 static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3229 {
3230 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3231 struct igb_adapter *adapter = rx_ring->adapter;
3232 struct e1000_hw *hw = &adapter->hw;
3233 struct net_device *netdev = adapter->netdev;
3234 int work_done = 0;
3235
3236 /* Keep link state information with original netdev */
3237 if (!netif_carrier_ok(netdev))
3238 goto quit_polling;
3239
3240 igb_clean_rx_irq_adv(adapter, rx_ring, &work_done, budget);
3241
3242
3243 /* If not enough Rx work done, exit the polling mode */
3244 if ((work_done == 0) || !netif_running(netdev)) {
3245 quit_polling:
3246 netif_rx_complete(netdev, napi);
3247
3248 wr32(E1000_EIMS, rx_ring->eims_value);
3249 if ((adapter->itr_setting & 3) && !rx_ring->no_itr_adjust &&
3250 (rx_ring->total_packets > IGB_DYN_ITR_PACKET_THRESHOLD)) {
3251 int mean_size = rx_ring->total_bytes /
3252 rx_ring->total_packets;
3253 if (mean_size < IGB_DYN_ITR_LENGTH_LOW)
3254 igb_raise_rx_eitr(adapter, rx_ring);
3255 else if (mean_size > IGB_DYN_ITR_LENGTH_HIGH)
3256 igb_lower_rx_eitr(adapter, rx_ring);
3257 }
3258 return 0;
3259 }
3260
3261 return 1;
3262 }
3263
3264 static inline u32 get_head(struct igb_ring *tx_ring)
3265 {
3266 void *end = (struct e1000_tx_desc *)tx_ring->desc + tx_ring->count;
3267 return le32_to_cpu(*(volatile __le32 *)end);
3268 }
3269
3270 /**
3271 * igb_clean_tx_irq - Reclaim resources after transmit completes
3272 * @adapter: board private structure
3273 * returns true if ring is completely cleaned
3274 **/
3275 static bool igb_clean_tx_irq(struct igb_adapter *adapter,
3276 struct igb_ring *tx_ring)
3277 {
3278 struct net_device *netdev = adapter->netdev;
3279 struct e1000_hw *hw = &adapter->hw;
3280 struct e1000_tx_desc *tx_desc;
3281 struct igb_buffer *buffer_info;
3282 struct sk_buff *skb;
3283 unsigned int i;
3284 u32 head, oldhead;
3285 unsigned int count = 0;
3286 bool cleaned = false;
3287 bool retval = true;
3288 unsigned int total_bytes = 0, total_packets = 0;
3289
3290 rmb();
3291 head = get_head(tx_ring);
3292 i = tx_ring->next_to_clean;
3293 while (1) {
3294 while (i != head) {
3295 cleaned = true;
3296 tx_desc = E1000_TX_DESC(*tx_ring, i);
3297 buffer_info = &tx_ring->buffer_info[i];
3298 skb = buffer_info->skb;
3299
3300 if (skb) {
3301 unsigned int segs, bytecount;
3302 /* gso_segs is currently only valid for tcp */
3303 segs = skb_shinfo(skb)->gso_segs ?: 1;
3304 /* multiply data chunks by size of headers */
3305 bytecount = ((segs - 1) * skb_headlen(skb)) +
3306 skb->len;
3307 total_packets += segs;
3308 total_bytes += bytecount;
3309 }
3310
3311 igb_unmap_and_free_tx_resource(adapter, buffer_info);
3312 tx_desc->upper.data = 0;
3313
3314 i++;
3315 if (i == tx_ring->count)
3316 i = 0;
3317
3318 count++;
3319 if (count == IGB_MAX_TX_CLEAN) {
3320 retval = false;
3321 goto done_cleaning;
3322 }
3323 }
3324 oldhead = head;
3325 rmb();
3326 head = get_head(tx_ring);
3327 if (head == oldhead)
3328 goto done_cleaning;
3329 } /* while (1) */
3330
3331 done_cleaning:
3332 tx_ring->next_to_clean = i;
3333
3334 if (unlikely(cleaned &&
3335 netif_carrier_ok(netdev) &&
3336 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3337 /* Make sure that anybody stopping the queue after this
3338 * sees the new next_to_clean.
3339 */
3340 smp_mb();
3341 if (netif_queue_stopped(netdev) &&
3342 !(test_bit(__IGB_DOWN, &adapter->state))) {
3343 netif_wake_queue(netdev);
3344 ++adapter->restart_queue;
3345 }
3346 }
3347
3348 if (tx_ring->detect_tx_hung) {
3349 /* Detect a transmit hang in hardware, this serializes the
3350 * check with the clearing of time_stamp and movement of i */
3351 tx_ring->detect_tx_hung = false;
3352 if (tx_ring->buffer_info[i].time_stamp &&
3353 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3354 (adapter->tx_timeout_factor * HZ))
3355 && !(rd32(E1000_STATUS) &
3356 E1000_STATUS_TXOFF)) {
3357
3358 tx_desc = E1000_TX_DESC(*tx_ring, i);
3359 /* detected Tx unit hang */
3360 dev_err(&adapter->pdev->dev,
3361 "Detected Tx Unit Hang\n"
3362 " Tx Queue <%lu>\n"
3363 " TDH <%x>\n"
3364 " TDT <%x>\n"
3365 " next_to_use <%x>\n"
3366 " next_to_clean <%x>\n"
3367 " head (WB) <%x>\n"
3368 "buffer_info[next_to_clean]\n"
3369 " time_stamp <%lx>\n"
3370 " jiffies <%lx>\n"
3371 " desc.status <%x>\n",
3372 (unsigned long)((tx_ring - adapter->tx_ring) /
3373 sizeof(struct igb_ring)),
3374 readl(adapter->hw.hw_addr + tx_ring->head),
3375 readl(adapter->hw.hw_addr + tx_ring->tail),
3376 tx_ring->next_to_use,
3377 tx_ring->next_to_clean,
3378 head,
3379 tx_ring->buffer_info[i].time_stamp,
3380 jiffies,
3381 tx_desc->upper.fields.status);
3382 netif_stop_queue(netdev);
3383 }
3384 }
3385 tx_ring->total_bytes += total_bytes;
3386 tx_ring->total_packets += total_packets;
3387 adapter->net_stats.tx_bytes += total_bytes;
3388 adapter->net_stats.tx_packets += total_packets;
3389 return retval;
3390 }
3391
3392
3393 /**
3394 * igb_receive_skb - helper function to handle rx indications
3395 * @adapter: board private structure
3396 * @status: descriptor status field as written by hardware
3397 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3398 * @skb: pointer to sk_buff to be indicated to stack
3399 **/
3400 static void igb_receive_skb(struct igb_adapter *adapter, u8 status, __le16 vlan,
3401 struct sk_buff *skb)
3402 {
3403 if (adapter->vlgrp && (status & E1000_RXD_STAT_VP))
3404 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3405 le16_to_cpu(vlan) &
3406 E1000_RXD_SPC_VLAN_MASK);
3407 else
3408 netif_receive_skb(skb);
3409 }
3410
3411
3412 static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3413 u32 status_err, struct sk_buff *skb)
3414 {
3415 skb->ip_summed = CHECKSUM_NONE;
3416
3417 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3418 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3419 return;
3420 /* TCP/UDP checksum error bit is set */
3421 if (status_err &
3422 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3423 /* let the stack verify checksum errors */
3424 adapter->hw_csum_err++;
3425 return;
3426 }
3427 /* It must be a TCP or UDP packet with a valid checksum */
3428 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3429 skb->ip_summed = CHECKSUM_UNNECESSARY;
3430
3431 adapter->hw_csum_good++;
3432 }
3433
3434 static bool igb_clean_rx_irq_adv(struct igb_adapter *adapter,
3435 struct igb_ring *rx_ring,
3436 int *work_done, int budget)
3437 {
3438 struct net_device *netdev = adapter->netdev;
3439 struct pci_dev *pdev = adapter->pdev;
3440 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3441 struct igb_buffer *buffer_info , *next_buffer;
3442 struct sk_buff *skb;
3443 unsigned int i, j;
3444 u32 length, hlen, staterr;
3445 bool cleaned = false;
3446 int cleaned_count = 0;
3447 unsigned int total_bytes = 0, total_packets = 0;
3448
3449 i = rx_ring->next_to_clean;
3450 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3451 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3452
3453 while (staterr & E1000_RXD_STAT_DD) {
3454 if (*work_done >= budget)
3455 break;
3456 (*work_done)++;
3457 buffer_info = &rx_ring->buffer_info[i];
3458
3459 /* HW will not DMA in data larger than the given buffer, even
3460 * if it parses the (NFS, of course) header to be larger. In
3461 * that case, it fills the header buffer and spills the rest
3462 * into the page.
3463 */
3464 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
3465 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
3466 if (hlen > adapter->rx_ps_hdr_size)
3467 hlen = adapter->rx_ps_hdr_size;
3468
3469 length = le16_to_cpu(rx_desc->wb.upper.length);
3470 cleaned = true;
3471 cleaned_count++;
3472
3473 if (rx_ring->pending_skb != NULL) {
3474 skb = rx_ring->pending_skb;
3475 rx_ring->pending_skb = NULL;
3476 j = rx_ring->pending_skb_page;
3477 } else {
3478 skb = buffer_info->skb;
3479 prefetch(skb->data - NET_IP_ALIGN);
3480 buffer_info->skb = NULL;
3481 if (hlen) {
3482 pci_unmap_single(pdev, buffer_info->dma,
3483 adapter->rx_ps_hdr_size +
3484 NET_IP_ALIGN,
3485 PCI_DMA_FROMDEVICE);
3486 skb_put(skb, hlen);
3487 } else {
3488 pci_unmap_single(pdev, buffer_info->dma,
3489 adapter->rx_buffer_len +
3490 NET_IP_ALIGN,
3491 PCI_DMA_FROMDEVICE);
3492 skb_put(skb, length);
3493 goto send_up;
3494 }
3495 j = 0;
3496 }
3497
3498 while (length) {
3499 pci_unmap_page(pdev, buffer_info->page_dma,
3500 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3501 buffer_info->page_dma = 0;
3502 skb_fill_page_desc(skb, j, buffer_info->page,
3503 0, length);
3504 buffer_info->page = NULL;
3505
3506 skb->len += length;
3507 skb->data_len += length;
3508 skb->truesize += length;
3509 rx_desc->wb.upper.status_error = 0;
3510 if (staterr & E1000_RXD_STAT_EOP)
3511 break;
3512
3513 j++;
3514 cleaned_count++;
3515 i++;
3516 if (i == rx_ring->count)
3517 i = 0;
3518
3519 buffer_info = &rx_ring->buffer_info[i];
3520 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3521 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3522 length = le16_to_cpu(rx_desc->wb.upper.length);
3523 if (!(staterr & E1000_RXD_STAT_DD)) {
3524 rx_ring->pending_skb = skb;
3525 rx_ring->pending_skb_page = j;
3526 goto out;
3527 }
3528 }
3529 send_up:
3530 pskb_trim(skb, skb->len - 4);
3531 i++;
3532 if (i == rx_ring->count)
3533 i = 0;
3534 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3535 prefetch(next_rxd);
3536 next_buffer = &rx_ring->buffer_info[i];
3537
3538 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3539 dev_kfree_skb_irq(skb);
3540 goto next_desc;
3541 }
3542 rx_ring->no_itr_adjust |= (staterr & E1000_RXD_STAT_DYNINT);
3543
3544 total_bytes += skb->len;
3545 total_packets++;
3546
3547 igb_rx_checksum_adv(adapter, staterr, skb);
3548
3549 skb->protocol = eth_type_trans(skb, netdev);
3550
3551 igb_receive_skb(adapter, staterr, rx_desc->wb.upper.vlan, skb);
3552
3553 netdev->last_rx = jiffies;
3554
3555 next_desc:
3556 rx_desc->wb.upper.status_error = 0;
3557
3558 /* return some buffers to hardware, one at a time is too slow */
3559 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3560 igb_alloc_rx_buffers_adv(adapter, rx_ring,
3561 cleaned_count);
3562 cleaned_count = 0;
3563 }
3564
3565 /* use prefetched values */
3566 rx_desc = next_rxd;
3567 buffer_info = next_buffer;
3568
3569 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3570 }
3571 out:
3572 rx_ring->next_to_clean = i;
3573 cleaned_count = IGB_DESC_UNUSED(rx_ring);
3574
3575 if (cleaned_count)
3576 igb_alloc_rx_buffers_adv(adapter, rx_ring, cleaned_count);
3577
3578 rx_ring->total_packets += total_packets;
3579 rx_ring->total_bytes += total_bytes;
3580 rx_ring->rx_stats.packets += total_packets;
3581 rx_ring->rx_stats.bytes += total_bytes;
3582 adapter->net_stats.rx_bytes += total_bytes;
3583 adapter->net_stats.rx_packets += total_packets;
3584 return cleaned;
3585 }
3586
3587
3588 /**
3589 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
3590 * @adapter: address of board private structure
3591 **/
3592 static void igb_alloc_rx_buffers_adv(struct igb_adapter *adapter,
3593 struct igb_ring *rx_ring,
3594 int cleaned_count)
3595 {
3596 struct net_device *netdev = adapter->netdev;
3597 struct pci_dev *pdev = adapter->pdev;
3598 union e1000_adv_rx_desc *rx_desc;
3599 struct igb_buffer *buffer_info;
3600 struct sk_buff *skb;
3601 unsigned int i;
3602
3603 i = rx_ring->next_to_use;
3604 buffer_info = &rx_ring->buffer_info[i];
3605
3606 while (cleaned_count--) {
3607 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3608
3609 if (adapter->rx_ps_hdr_size && !buffer_info->page) {
3610 buffer_info->page = alloc_page(GFP_ATOMIC);
3611 if (!buffer_info->page) {
3612 adapter->alloc_rx_buff_failed++;
3613 goto no_buffers;
3614 }
3615 buffer_info->page_dma =
3616 pci_map_page(pdev,
3617 buffer_info->page,
3618 0, PAGE_SIZE,
3619 PCI_DMA_FROMDEVICE);
3620 }
3621
3622 if (!buffer_info->skb) {
3623 int bufsz;
3624
3625 if (adapter->rx_ps_hdr_size)
3626 bufsz = adapter->rx_ps_hdr_size;
3627 else
3628 bufsz = adapter->rx_buffer_len;
3629 bufsz += NET_IP_ALIGN;
3630 skb = netdev_alloc_skb(netdev, bufsz);
3631
3632 if (!skb) {
3633 adapter->alloc_rx_buff_failed++;
3634 goto no_buffers;
3635 }
3636
3637 /* Make buffer alignment 2 beyond a 16 byte boundary
3638 * this will result in a 16 byte aligned IP header after
3639 * the 14 byte MAC header is removed
3640 */
3641 skb_reserve(skb, NET_IP_ALIGN);
3642
3643 buffer_info->skb = skb;
3644 buffer_info->dma = pci_map_single(pdev, skb->data,
3645 bufsz,
3646 PCI_DMA_FROMDEVICE);
3647
3648 }
3649 /* Refresh the desc even if buffer_addrs didn't change because
3650 * each write-back erases this info. */
3651 if (adapter->rx_ps_hdr_size) {
3652 rx_desc->read.pkt_addr =
3653 cpu_to_le64(buffer_info->page_dma);
3654 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
3655 } else {
3656 rx_desc->read.pkt_addr =
3657 cpu_to_le64(buffer_info->dma);
3658 rx_desc->read.hdr_addr = 0;
3659 }
3660
3661 i++;
3662 if (i == rx_ring->count)
3663 i = 0;
3664 buffer_info = &rx_ring->buffer_info[i];
3665 }
3666
3667 no_buffers:
3668 if (rx_ring->next_to_use != i) {
3669 rx_ring->next_to_use = i;
3670 if (i == 0)
3671 i = (rx_ring->count - 1);
3672 else
3673 i--;
3674
3675 /* Force memory writes to complete before letting h/w
3676 * know there are new descriptors to fetch. (Only
3677 * applicable for weak-ordered memory model archs,
3678 * such as IA-64). */
3679 wmb();
3680 writel(i, adapter->hw.hw_addr + rx_ring->tail);
3681 }
3682 }
3683
3684 /**
3685 * igb_mii_ioctl -
3686 * @netdev:
3687 * @ifreq:
3688 * @cmd:
3689 **/
3690 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3691 {
3692 struct igb_adapter *adapter = netdev_priv(netdev);
3693 struct mii_ioctl_data *data = if_mii(ifr);
3694
3695 if (adapter->hw.phy.media_type != e1000_media_type_copper)
3696 return -EOPNOTSUPP;
3697
3698 switch (cmd) {
3699 case SIOCGMIIPHY:
3700 data->phy_id = adapter->hw.phy.addr;
3701 break;
3702 case SIOCGMIIREG:
3703 if (!capable(CAP_NET_ADMIN))
3704 return -EPERM;
3705 if (adapter->hw.phy.ops.read_phy_reg(&adapter->hw,
3706 data->reg_num
3707 & 0x1F, &data->val_out))
3708 return -EIO;
3709 break;
3710 case SIOCSMIIREG:
3711 default:
3712 return -EOPNOTSUPP;
3713 }
3714 return 0;
3715 }
3716
3717 /**
3718 * igb_ioctl -
3719 * @netdev:
3720 * @ifreq:
3721 * @cmd:
3722 **/
3723 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3724 {
3725 switch (cmd) {
3726 case SIOCGMIIPHY:
3727 case SIOCGMIIREG:
3728 case SIOCSMIIREG:
3729 return igb_mii_ioctl(netdev, ifr, cmd);
3730 default:
3731 return -EOPNOTSUPP;
3732 }
3733 }
3734
3735 static void igb_vlan_rx_register(struct net_device *netdev,
3736 struct vlan_group *grp)
3737 {
3738 struct igb_adapter *adapter = netdev_priv(netdev);
3739 struct e1000_hw *hw = &adapter->hw;
3740 u32 ctrl, rctl;
3741
3742 igb_irq_disable(adapter);
3743 adapter->vlgrp = grp;
3744
3745 if (grp) {
3746 /* enable VLAN tag insert/strip */
3747 ctrl = rd32(E1000_CTRL);
3748 ctrl |= E1000_CTRL_VME;
3749 wr32(E1000_CTRL, ctrl);
3750
3751 /* enable VLAN receive filtering */
3752 rctl = rd32(E1000_RCTL);
3753 rctl |= E1000_RCTL_VFE;
3754 rctl &= ~E1000_RCTL_CFIEN;
3755 wr32(E1000_RCTL, rctl);
3756 igb_update_mng_vlan(adapter);
3757 wr32(E1000_RLPML,
3758 adapter->max_frame_size + VLAN_TAG_SIZE);
3759 } else {
3760 /* disable VLAN tag insert/strip */
3761 ctrl = rd32(E1000_CTRL);
3762 ctrl &= ~E1000_CTRL_VME;
3763 wr32(E1000_CTRL, ctrl);
3764
3765 /* disable VLAN filtering */
3766 rctl = rd32(E1000_RCTL);
3767 rctl &= ~E1000_RCTL_VFE;
3768 wr32(E1000_RCTL, rctl);
3769 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
3770 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
3771 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
3772 }
3773 wr32(E1000_RLPML,
3774 adapter->max_frame_size);
3775 }
3776
3777 if (!test_bit(__IGB_DOWN, &adapter->state))
3778 igb_irq_enable(adapter);
3779 }
3780
3781 static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3782 {
3783 struct igb_adapter *adapter = netdev_priv(netdev);
3784 struct e1000_hw *hw = &adapter->hw;
3785 u32 vfta, index;
3786
3787 if ((adapter->hw.mng_cookie.status &
3788 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
3789 (vid == adapter->mng_vlan_id))
3790 return;
3791 /* add VID to filter table */
3792 index = (vid >> 5) & 0x7F;
3793 vfta = array_rd32(E1000_VFTA, index);
3794 vfta |= (1 << (vid & 0x1F));
3795 igb_write_vfta(&adapter->hw, index, vfta);
3796 }
3797
3798 static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3799 {
3800 struct igb_adapter *adapter = netdev_priv(netdev);
3801 struct e1000_hw *hw = &adapter->hw;
3802 u32 vfta, index;
3803
3804 igb_irq_disable(adapter);
3805 vlan_group_set_device(adapter->vlgrp, vid, NULL);
3806
3807 if (!test_bit(__IGB_DOWN, &adapter->state))
3808 igb_irq_enable(adapter);
3809
3810 if ((adapter->hw.mng_cookie.status &
3811 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
3812 (vid == adapter->mng_vlan_id)) {
3813 /* release control to f/w */
3814 igb_release_hw_control(adapter);
3815 return;
3816 }
3817
3818 /* remove VID from filter table */
3819 index = (vid >> 5) & 0x7F;
3820 vfta = array_rd32(E1000_VFTA, index);
3821 vfta &= ~(1 << (vid & 0x1F));
3822 igb_write_vfta(&adapter->hw, index, vfta);
3823 }
3824
3825 static void igb_restore_vlan(struct igb_adapter *adapter)
3826 {
3827 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
3828
3829 if (adapter->vlgrp) {
3830 u16 vid;
3831 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
3832 if (!vlan_group_get_device(adapter->vlgrp, vid))
3833 continue;
3834 igb_vlan_rx_add_vid(adapter->netdev, vid);
3835 }
3836 }
3837 }
3838
3839 int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
3840 {
3841 struct e1000_mac_info *mac = &adapter->hw.mac;
3842
3843 mac->autoneg = 0;
3844
3845 /* Fiber NICs only allow 1000 gbps Full duplex */
3846 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
3847 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
3848 dev_err(&adapter->pdev->dev,
3849 "Unsupported Speed/Duplex configuration\n");
3850 return -EINVAL;
3851 }
3852
3853 switch (spddplx) {
3854 case SPEED_10 + DUPLEX_HALF:
3855 mac->forced_speed_duplex = ADVERTISE_10_HALF;
3856 break;
3857 case SPEED_10 + DUPLEX_FULL:
3858 mac->forced_speed_duplex = ADVERTISE_10_FULL;
3859 break;
3860 case SPEED_100 + DUPLEX_HALF:
3861 mac->forced_speed_duplex = ADVERTISE_100_HALF;
3862 break;
3863 case SPEED_100 + DUPLEX_FULL:
3864 mac->forced_speed_duplex = ADVERTISE_100_FULL;
3865 break;
3866 case SPEED_1000 + DUPLEX_FULL:
3867 mac->autoneg = 1;
3868 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
3869 break;
3870 case SPEED_1000 + DUPLEX_HALF: /* not supported */
3871 default:
3872 dev_err(&adapter->pdev->dev,
3873 "Unsupported Speed/Duplex configuration\n");
3874 return -EINVAL;
3875 }
3876 return 0;
3877 }
3878
3879
3880 static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
3881 {
3882 struct net_device *netdev = pci_get_drvdata(pdev);
3883 struct igb_adapter *adapter = netdev_priv(netdev);
3884 struct e1000_hw *hw = &adapter->hw;
3885 u32 ctrl, ctrl_ext, rctl, status;
3886 u32 wufc = adapter->wol;
3887 #ifdef CONFIG_PM
3888 int retval = 0;
3889 #endif
3890
3891 netif_device_detach(netdev);
3892
3893 if (netif_running(netdev)) {
3894 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
3895 igb_down(adapter);
3896 igb_free_irq(adapter);
3897 }
3898
3899 #ifdef CONFIG_PM
3900 retval = pci_save_state(pdev);
3901 if (retval)
3902 return retval;
3903 #endif
3904
3905 status = rd32(E1000_STATUS);
3906 if (status & E1000_STATUS_LU)
3907 wufc &= ~E1000_WUFC_LNKC;
3908
3909 if (wufc) {
3910 igb_setup_rctl(adapter);
3911 igb_set_multi(netdev);
3912
3913 /* turn on all-multi mode if wake on multicast is enabled */
3914 if (wufc & E1000_WUFC_MC) {
3915 rctl = rd32(E1000_RCTL);
3916 rctl |= E1000_RCTL_MPE;
3917 wr32(E1000_RCTL, rctl);
3918 }
3919
3920 ctrl = rd32(E1000_CTRL);
3921 /* advertise wake from D3Cold */
3922 #define E1000_CTRL_ADVD3WUC 0x00100000
3923 /* phy power management enable */
3924 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
3925 ctrl |= E1000_CTRL_ADVD3WUC;
3926 wr32(E1000_CTRL, ctrl);
3927
3928 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
3929 adapter->hw.phy.media_type ==
3930 e1000_media_type_internal_serdes) {
3931 /* keep the laser running in D3 */
3932 ctrl_ext = rd32(E1000_CTRL_EXT);
3933 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
3934 wr32(E1000_CTRL_EXT, ctrl_ext);
3935 }
3936
3937 /* Allow time for pending master requests to run */
3938 igb_disable_pcie_master(&adapter->hw);
3939
3940 wr32(E1000_WUC, E1000_WUC_PME_EN);
3941 wr32(E1000_WUFC, wufc);
3942 pci_enable_wake(pdev, PCI_D3hot, 1);
3943 pci_enable_wake(pdev, PCI_D3cold, 1);
3944 } else {
3945 wr32(E1000_WUC, 0);
3946 wr32(E1000_WUFC, 0);
3947 pci_enable_wake(pdev, PCI_D3hot, 0);
3948 pci_enable_wake(pdev, PCI_D3cold, 0);
3949 }
3950
3951 /* make sure adapter isn't asleep if manageability is enabled */
3952 if (adapter->en_mng_pt) {
3953 pci_enable_wake(pdev, PCI_D3hot, 1);
3954 pci_enable_wake(pdev, PCI_D3cold, 1);
3955 }
3956
3957 /* Release control of h/w to f/w. If f/w is AMT enabled, this
3958 * would have already happened in close and is redundant. */
3959 igb_release_hw_control(adapter);
3960
3961 pci_disable_device(pdev);
3962
3963 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3964
3965 return 0;
3966 }
3967
3968 #ifdef CONFIG_PM
3969 static int igb_resume(struct pci_dev *pdev)
3970 {
3971 struct net_device *netdev = pci_get_drvdata(pdev);
3972 struct igb_adapter *adapter = netdev_priv(netdev);
3973 struct e1000_hw *hw = &adapter->hw;
3974 u32 err;
3975
3976 pci_set_power_state(pdev, PCI_D0);
3977 pci_restore_state(pdev);
3978 err = pci_enable_device(pdev);
3979 if (err) {
3980 dev_err(&pdev->dev,
3981 "igb: Cannot enable PCI device from suspend\n");
3982 return err;
3983 }
3984 pci_set_master(pdev);
3985
3986 pci_enable_wake(pdev, PCI_D3hot, 0);
3987 pci_enable_wake(pdev, PCI_D3cold, 0);
3988
3989 if (netif_running(netdev)) {
3990 err = igb_request_irq(adapter);
3991 if (err)
3992 return err;
3993 }
3994
3995 /* e1000_power_up_phy(adapter); */
3996
3997 igb_reset(adapter);
3998 wr32(E1000_WUS, ~0);
3999
4000 igb_init_manageability(adapter);
4001
4002 if (netif_running(netdev))
4003 igb_up(adapter);
4004
4005 netif_device_attach(netdev);
4006
4007 /* let the f/w know that the h/w is now under the control of the
4008 * driver. */
4009 igb_get_hw_control(adapter);
4010
4011 return 0;
4012 }
4013 #endif
4014
4015 static void igb_shutdown(struct pci_dev *pdev)
4016 {
4017 igb_suspend(pdev, PMSG_SUSPEND);
4018 }
4019
4020 #ifdef CONFIG_NET_POLL_CONTROLLER
4021 /*
4022 * Polling 'interrupt' - used by things like netconsole to send skbs
4023 * without having to re-enable interrupts. It's not called while
4024 * the interrupt routine is executing.
4025 */
4026 static void igb_netpoll(struct net_device *netdev)
4027 {
4028 struct igb_adapter *adapter = netdev_priv(netdev);
4029 int i;
4030 int work_done = 0;
4031
4032 igb_irq_disable(adapter);
4033 for (i = 0; i < adapter->num_tx_queues; i++)
4034 igb_clean_tx_irq(adapter, &adapter->tx_ring[i]);
4035
4036 for (i = 0; i < adapter->num_rx_queues; i++)
4037 igb_clean_rx_irq_adv(adapter, &adapter->rx_ring[i],
4038 &work_done,
4039 adapter->rx_ring[i].napi.weight);
4040
4041 igb_irq_enable(adapter);
4042 }
4043 #endif /* CONFIG_NET_POLL_CONTROLLER */
4044
4045 /**
4046 * igb_io_error_detected - called when PCI error is detected
4047 * @pdev: Pointer to PCI device
4048 * @state: The current pci connection state
4049 *
4050 * This function is called after a PCI bus error affecting
4051 * this device has been detected.
4052 */
4053 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4054 pci_channel_state_t state)
4055 {
4056 struct net_device *netdev = pci_get_drvdata(pdev);
4057 struct igb_adapter *adapter = netdev_priv(netdev);
4058
4059 netif_device_detach(netdev);
4060
4061 if (netif_running(netdev))
4062 igb_down(adapter);
4063 pci_disable_device(pdev);
4064
4065 /* Request a slot slot reset. */
4066 return PCI_ERS_RESULT_NEED_RESET;
4067 }
4068
4069 /**
4070 * igb_io_slot_reset - called after the pci bus has been reset.
4071 * @pdev: Pointer to PCI device
4072 *
4073 * Restart the card from scratch, as if from a cold-boot. Implementation
4074 * resembles the first-half of the igb_resume routine.
4075 */
4076 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4077 {
4078 struct net_device *netdev = pci_get_drvdata(pdev);
4079 struct igb_adapter *adapter = netdev_priv(netdev);
4080 struct e1000_hw *hw = &adapter->hw;
4081
4082 if (pci_enable_device(pdev)) {
4083 dev_err(&pdev->dev,
4084 "Cannot re-enable PCI device after reset.\n");
4085 return PCI_ERS_RESULT_DISCONNECT;
4086 }
4087 pci_set_master(pdev);
4088 pci_restore_state(pdev);
4089
4090 pci_enable_wake(pdev, PCI_D3hot, 0);
4091 pci_enable_wake(pdev, PCI_D3cold, 0);
4092
4093 igb_reset(adapter);
4094 wr32(E1000_WUS, ~0);
4095
4096 return PCI_ERS_RESULT_RECOVERED;
4097 }
4098
4099 /**
4100 * igb_io_resume - called when traffic can start flowing again.
4101 * @pdev: Pointer to PCI device
4102 *
4103 * This callback is called when the error recovery driver tells us that
4104 * its OK to resume normal operation. Implementation resembles the
4105 * second-half of the igb_resume routine.
4106 */
4107 static void igb_io_resume(struct pci_dev *pdev)
4108 {
4109 struct net_device *netdev = pci_get_drvdata(pdev);
4110 struct igb_adapter *adapter = netdev_priv(netdev);
4111
4112 igb_init_manageability(adapter);
4113
4114 if (netif_running(netdev)) {
4115 if (igb_up(adapter)) {
4116 dev_err(&pdev->dev, "igb_up failed after reset\n");
4117 return;
4118 }
4119 }
4120
4121 netif_device_attach(netdev);
4122
4123 /* let the f/w know that the h/w is now under the control of the
4124 * driver. */
4125 igb_get_hw_control(adapter);
4126
4127 }
4128
4129 /* igb_main.c */
Linux kernel - Deliverables
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