2 * ipg.c: Device Driver for the IP1000 Gigabit Ethernet Adapter
4 * Copyright (C) 2003, 2007 IC Plus Corp
9 * Sundance Technology, Inc.
11 * craig_rich@sundanceti.com
16 * http://www.icplus.com.tw
17 * sorbica@icplus.com.tw
20 * http://www.icplus.com.tw
23 #include <linux/crc32.h>
24 #include <linux/ethtool.h>
25 #include <linux/mii.h>
26 #include <linux/mutex.h>
28 #include <asm/div64.h>
30 #define IPG_RX_RING_BYTES (sizeof(struct ipg_rx) * IPG_RFDLIST_LENGTH)
31 #define IPG_TX_RING_BYTES (sizeof(struct ipg_tx) * IPG_TFDLIST_LENGTH)
32 #define IPG_RESET_MASK \
33 (IPG_AC_GLOBAL_RESET | IPG_AC_RX_RESET | IPG_AC_TX_RESET | \
34 IPG_AC_DMA | IPG_AC_FIFO | IPG_AC_NETWORK | IPG_AC_HOST | \
37 #define ipg_w32(val32,reg) iowrite32((val32), ioaddr + (reg))
38 #define ipg_w16(val16,reg) iowrite16((val16), ioaddr + (reg))
39 #define ipg_w8(val8,reg) iowrite8((val8), ioaddr + (reg))
41 #define ipg_r32(reg) ioread32(ioaddr + (reg))
42 #define ipg_r16(reg) ioread16(ioaddr + (reg))
43 #define ipg_r8(reg) ioread8(ioaddr + (reg))
45 #define JUMBO_FRAME_4k_ONLY
51 #define DRV_NAME "ipg"
53 MODULE_AUTHOR("IC Plus Corp. 2003");
54 MODULE_DESCRIPTION("IC Plus IP1000 Gigabit Ethernet Adapter Linux Driver");
55 MODULE_LICENSE("GPL");
57 //variable record -- index by leading revision/length
58 //Revision/Length(=N*4), Address1, Data1, Address2, Data2,...,AddressN,DataN
59 static unsigned short DefaultPhyParam
[] = {
60 // 11/12/03 IP1000A v1-3 rev=0x40
61 /*--------------------------------------------------------------------------
62 (0x4000|(15*4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 22, 0x85bd, 24, 0xfff2,
63 27, 0x0c10, 28, 0x0c10, 29, 0x2c10, 31, 0x0003, 23, 0x92f6,
64 31, 0x0000, 23, 0x003d, 30, 0x00de, 20, 0x20e7, 9, 0x0700,
65 --------------------------------------------------------------------------*/
66 // 12/17/03 IP1000A v1-4 rev=0x40
67 (0x4000 | (07 * 4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31,
69 30, 0x005e, 9, 0x0700,
70 // 01/09/04 IP1000A v1-5 rev=0x41
71 (0x4100 | (07 * 4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31,
73 30, 0x005e, 9, 0x0700,
77 static const char *ipg_brand_name
[] = {
78 "IC PLUS IP1000 1000/100/10 based NIC",
79 "Sundance Technology ST2021 based NIC",
80 "Tamarack Microelectronics TC9020/9021 based NIC",
81 "Tamarack Microelectronics TC9020/9021 based NIC",
86 static struct pci_device_id ipg_pci_tbl
[] __devinitdata
= {
87 { PCI_VDEVICE(SUNDANCE
, 0x1023), 0 },
88 { PCI_VDEVICE(SUNDANCE
, 0x2021), 1 },
89 { PCI_VDEVICE(SUNDANCE
, 0x1021), 2 },
90 { PCI_VDEVICE(DLINK
, 0x9021), 3 },
91 { PCI_VDEVICE(DLINK
, 0x4000), 4 },
92 { PCI_VDEVICE(DLINK
, 0x4020), 5 },
96 MODULE_DEVICE_TABLE(pci
, ipg_pci_tbl
);
98 static inline void __iomem
*ipg_ioaddr(struct net_device
*dev
)
100 struct ipg_nic_private
*sp
= netdev_priv(dev
);
105 static void ipg_dump_rfdlist(struct net_device
*dev
)
107 struct ipg_nic_private
*sp
= netdev_priv(dev
);
108 void __iomem
*ioaddr
= sp
->ioaddr
;
112 IPG_DEBUG_MSG("_dump_rfdlist\n");
114 printk(KERN_INFO
"rx_current = %2.2x\n", sp
->rx_current
);
115 printk(KERN_INFO
"rx_dirty = %2.2x\n", sp
->rx_dirty
);
116 printk(KERN_INFO
"RFDList start address = %16.16lx\n",
117 (unsigned long) sp
->rxd_map
);
118 printk(KERN_INFO
"RFDListPtr register = %8.8x%8.8x\n",
119 ipg_r32(IPG_RFDLISTPTR1
), ipg_r32(IPG_RFDLISTPTR0
));
121 for (i
= 0; i
< IPG_RFDLIST_LENGTH
; i
++) {
122 offset
= (u32
) &sp
->rxd
[i
].next_desc
- (u32
) sp
->rxd
;
123 printk(KERN_INFO
"%2.2x %4.4x RFDNextPtr = %16.16lx\n", i
,
124 offset
, (unsigned long) sp
->rxd
[i
].next_desc
);
125 offset
= (u32
) &sp
->rxd
[i
].rfs
- (u32
) sp
->rxd
;
126 printk(KERN_INFO
"%2.2x %4.4x RFS = %16.16lx\n", i
,
127 offset
, (unsigned long) sp
->rxd
[i
].rfs
);
128 offset
= (u32
) &sp
->rxd
[i
].frag_info
- (u32
) sp
->rxd
;
129 printk(KERN_INFO
"%2.2x %4.4x frag_info = %16.16lx\n", i
,
130 offset
, (unsigned long) sp
->rxd
[i
].frag_info
);
134 static void ipg_dump_tfdlist(struct net_device
*dev
)
136 struct ipg_nic_private
*sp
= netdev_priv(dev
);
137 void __iomem
*ioaddr
= sp
->ioaddr
;
141 IPG_DEBUG_MSG("_dump_tfdlist\n");
143 printk(KERN_INFO
"tx_current = %2.2x\n", sp
->tx_current
);
144 printk(KERN_INFO
"tx_dirty = %2.2x\n", sp
->tx_dirty
);
145 printk(KERN_INFO
"TFDList start address = %16.16lx\n",
146 (unsigned long) sp
->txd_map
);
147 printk(KERN_INFO
"TFDListPtr register = %8.8x%8.8x\n",
148 ipg_r32(IPG_TFDLISTPTR1
), ipg_r32(IPG_TFDLISTPTR0
));
150 for (i
= 0; i
< IPG_TFDLIST_LENGTH
; i
++) {
151 offset
= (u32
) &sp
->txd
[i
].next_desc
- (u32
) sp
->txd
;
152 printk(KERN_INFO
"%2.2x %4.4x TFDNextPtr = %16.16lx\n", i
,
153 offset
, (unsigned long) sp
->txd
[i
].next_desc
);
155 offset
= (u32
) &sp
->txd
[i
].tfc
- (u32
) sp
->txd
;
156 printk(KERN_INFO
"%2.2x %4.4x TFC = %16.16lx\n", i
,
157 offset
, (unsigned long) sp
->txd
[i
].tfc
);
158 offset
= (u32
) &sp
->txd
[i
].frag_info
- (u32
) sp
->txd
;
159 printk(KERN_INFO
"%2.2x %4.4x frag_info = %16.16lx\n", i
,
160 offset
, (unsigned long) sp
->txd
[i
].frag_info
);
165 static void ipg_write_phy_ctl(void __iomem
*ioaddr
, u8 data
)
167 ipg_w8(IPG_PC_RSVD_MASK
& data
, PHY_CTRL
);
168 ndelay(IPG_PC_PHYCTRLWAIT_NS
);
171 static void ipg_drive_phy_ctl_low_high(void __iomem
*ioaddr
, u8 data
)
173 ipg_write_phy_ctl(ioaddr
, IPG_PC_MGMTCLK_LO
| data
);
174 ipg_write_phy_ctl(ioaddr
, IPG_PC_MGMTCLK_HI
| data
);
177 static void send_three_state(void __iomem
*ioaddr
, u8 phyctrlpolarity
)
179 phyctrlpolarity
|= (IPG_PC_MGMTDATA
& 0) | IPG_PC_MGMTDIR
;
181 ipg_drive_phy_ctl_low_high(ioaddr
, phyctrlpolarity
);
184 static void send_end(void __iomem
*ioaddr
, u8 phyctrlpolarity
)
186 ipg_w8((IPG_PC_MGMTCLK_LO
| (IPG_PC_MGMTDATA
& 0) | IPG_PC_MGMTDIR
|
187 phyctrlpolarity
) & IPG_PC_RSVD_MASK
, PHY_CTRL
);
190 static u16
read_phy_bit(void __iomem
* ioaddr
, u8 phyctrlpolarity
)
194 ipg_write_phy_ctl(ioaddr
, IPG_PC_MGMTCLK_LO
| phyctrlpolarity
);
196 bit_data
= ((ipg_r8(PHY_CTRL
) & IPG_PC_MGMTDATA
) >> 1) & 1;
198 ipg_write_phy_ctl(ioaddr
, IPG_PC_MGMTCLK_HI
| phyctrlpolarity
);
204 * Read a register from the Physical Layer device located
205 * on the IPG NIC, using the IPG PHYCTRL register.
207 static int mdio_read(struct net_device
* dev
, int phy_id
, int phy_reg
)
209 void __iomem
*ioaddr
= ipg_ioaddr(dev
);
211 * The GMII mangement frame structure for a read is as follows:
213 * |Preamble|st|op|phyad|regad|ta| data |idle|
214 * |< 32 1s>|01|10|AAAAA|RRRRR|z0|DDDDDDDDDDDDDDDD|z |
216 * <32 1s> = 32 consecutive logic 1 values
217 * A = bit of Physical Layer device address (MSB first)
218 * R = bit of register address (MSB first)
219 * z = High impedance state
220 * D = bit of read data (MSB first)
222 * Transmission order is 'Preamble' field first, bits transmitted
223 * left to right (first to last).
229 { GMII_PREAMBLE
, 32 }, /* Preamble */
230 { GMII_ST
, 2 }, /* ST */
231 { GMII_READ
, 2 }, /* OP */
232 { phy_id
, 5 }, /* PHYAD */
233 { phy_reg
, 5 }, /* REGAD */
234 { 0x0000, 2 }, /* TA */
235 { 0x0000, 16 }, /* DATA */
236 { 0x0000, 1 } /* IDLE */
241 polarity
= ipg_r8(PHY_CTRL
);
242 polarity
&= (IPG_PC_DUPLEX_POLARITY
| IPG_PC_LINK_POLARITY
);
244 /* Create the Preamble, ST, OP, PHYAD, and REGAD field. */
245 for (j
= 0; j
< 5; j
++) {
246 for (i
= 0; i
< p
[j
].len
; i
++) {
247 /* For each variable length field, the MSB must be
248 * transmitted first. Rotate through the field bits,
249 * starting with the MSB, and move each bit into the
250 * the 1st (2^1) bit position (this is the bit position
251 * corresponding to the MgmtData bit of the PhyCtrl
252 * register for the IPG).
256 * First write a '0' to bit 1 of the PhyCtrl
257 * register, then write a '1' to bit 1 of the
260 * To do this, right shift the MSB of ST by the value:
261 * [field length - 1 - #ST bits already written]
262 * then left shift this result by 1.
264 data
= (p
[j
].field
>> (p
[j
].len
- 1 - i
)) << 1;
265 data
&= IPG_PC_MGMTDATA
;
266 data
|= polarity
| IPG_PC_MGMTDIR
;
268 ipg_drive_phy_ctl_low_high(ioaddr
, data
);
272 send_three_state(ioaddr
, polarity
);
274 read_phy_bit(ioaddr
, polarity
);
277 * For a read cycle, the bits for the next two fields (TA and
278 * DATA) are driven by the PHY (the IPG reads these bits).
280 for (i
= 0; i
< p
[6].len
; i
++) {
282 (read_phy_bit(ioaddr
, polarity
) << (p
[6].len
- 1 - i
));
285 send_three_state(ioaddr
, polarity
);
286 send_three_state(ioaddr
, polarity
);
287 send_three_state(ioaddr
, polarity
);
288 send_end(ioaddr
, polarity
);
290 /* Return the value of the DATA field. */
295 * Write to a register from the Physical Layer device located
296 * on the IPG NIC, using the IPG PHYCTRL register.
298 static void mdio_write(struct net_device
*dev
, int phy_id
, int phy_reg
, int val
)
300 void __iomem
*ioaddr
= ipg_ioaddr(dev
);
302 * The GMII mangement frame structure for a read is as follows:
304 * |Preamble|st|op|phyad|regad|ta| data |idle|
305 * |< 32 1s>|01|10|AAAAA|RRRRR|z0|DDDDDDDDDDDDDDDD|z |
307 * <32 1s> = 32 consecutive logic 1 values
308 * A = bit of Physical Layer device address (MSB first)
309 * R = bit of register address (MSB first)
310 * z = High impedance state
311 * D = bit of write data (MSB first)
313 * Transmission order is 'Preamble' field first, bits transmitted
314 * left to right (first to last).
320 { GMII_PREAMBLE
, 32 }, /* Preamble */
321 { GMII_ST
, 2 }, /* ST */
322 { GMII_WRITE
, 2 }, /* OP */
323 { phy_id
, 5 }, /* PHYAD */
324 { phy_reg
, 5 }, /* REGAD */
325 { 0x0002, 2 }, /* TA */
326 { val
& 0xffff, 16 }, /* DATA */
327 { 0x0000, 1 } /* IDLE */
332 polarity
= ipg_r8(PHY_CTRL
);
333 polarity
&= (IPG_PC_DUPLEX_POLARITY
| IPG_PC_LINK_POLARITY
);
335 /* Create the Preamble, ST, OP, PHYAD, and REGAD field. */
336 for (j
= 0; j
< 7; j
++) {
337 for (i
= 0; i
< p
[j
].len
; i
++) {
338 /* For each variable length field, the MSB must be
339 * transmitted first. Rotate through the field bits,
340 * starting with the MSB, and move each bit into the
341 * the 1st (2^1) bit position (this is the bit position
342 * corresponding to the MgmtData bit of the PhyCtrl
343 * register for the IPG).
347 * First write a '0' to bit 1 of the PhyCtrl
348 * register, then write a '1' to bit 1 of the
351 * To do this, right shift the MSB of ST by the value:
352 * [field length - 1 - #ST bits already written]
353 * then left shift this result by 1.
355 data
= (p
[j
].field
>> (p
[j
].len
- 1 - i
)) << 1;
356 data
&= IPG_PC_MGMTDATA
;
357 data
|= polarity
| IPG_PC_MGMTDIR
;
359 ipg_drive_phy_ctl_low_high(ioaddr
, data
);
363 /* The last cycle is a tri-state, so read from the PHY. */
364 for (j
= 7; j
< 8; j
++) {
365 for (i
= 0; i
< p
[j
].len
; i
++) {
366 ipg_write_phy_ctl(ioaddr
, IPG_PC_MGMTCLK_LO
| polarity
);
368 p
[j
].field
|= ((ipg_r8(PHY_CTRL
) &
369 IPG_PC_MGMTDATA
) >> 1) << (p
[j
].len
- 1 - i
);
371 ipg_write_phy_ctl(ioaddr
, IPG_PC_MGMTCLK_HI
| polarity
);
376 /* Set LED_Mode JES20040127EEPROM */
377 static void ipg_set_led_mode(struct net_device
*dev
)
379 struct ipg_nic_private
*sp
= netdev_priv(dev
);
380 void __iomem
*ioaddr
= sp
->ioaddr
;
383 mode
= ipg_r32(ASIC_CTRL
);
384 mode
&= ~(IPG_AC_LED_MODE_BIT_1
| IPG_AC_LED_MODE
| IPG_AC_LED_SPEED
);
386 if ((sp
->LED_Mode
& 0x03) > 1)
387 mode
|= IPG_AC_LED_MODE_BIT_1
; /* Write Asic Control Bit 29 */
389 if ((sp
->LED_Mode
& 0x01) == 1)
390 mode
|= IPG_AC_LED_MODE
; /* Write Asic Control Bit 14 */
392 if ((sp
->LED_Mode
& 0x08) == 8)
393 mode
|= IPG_AC_LED_SPEED
; /* Write Asic Control Bit 27 */
395 ipg_w32(mode
, ASIC_CTRL
);
398 /* Set PHYSet JES20040127EEPROM */
399 static void ipg_set_phy_set(struct net_device
*dev
)
401 struct ipg_nic_private
*sp
= netdev_priv(dev
);
402 void __iomem
*ioaddr
= sp
->ioaddr
;
405 physet
= ipg_r8(PHY_SET
);
406 physet
&= ~(IPG_PS_MEM_LENB9B
| IPG_PS_MEM_LEN9
| IPG_PS_NON_COMPDET
);
407 physet
|= ((sp
->LED_Mode
& 0x70) >> 4);
408 ipg_w8(physet
, PHY_SET
);
411 static int ipg_reset(struct net_device
*dev
, u32 resetflags
)
413 /* Assert functional resets via the IPG AsicCtrl
414 * register as specified by the 'resetflags' input
417 void __iomem
*ioaddr
= ipg_ioaddr(dev
); //JES20040127EEPROM:
418 unsigned int timeout_count
= 0;
420 IPG_DEBUG_MSG("_reset\n");
422 ipg_w32(ipg_r32(ASIC_CTRL
) | resetflags
, ASIC_CTRL
);
424 /* Delay added to account for problem with 10Mbps reset. */
425 mdelay(IPG_AC_RESETWAIT
);
427 while (IPG_AC_RESET_BUSY
& ipg_r32(ASIC_CTRL
)) {
428 mdelay(IPG_AC_RESETWAIT
);
429 if (++timeout_count
> IPG_AC_RESET_TIMEOUT
)
432 /* Set LED Mode in Asic Control JES20040127EEPROM */
433 ipg_set_led_mode(dev
);
435 /* Set PHYSet Register Value JES20040127EEPROM */
436 ipg_set_phy_set(dev
);
440 /* Find the GMII PHY address. */
441 static int ipg_find_phyaddr(struct net_device
*dev
)
443 unsigned int phyaddr
, i
;
445 for (i
= 0; i
< 32; i
++) {
448 /* Search for the correct PHY address among 32 possible. */
449 phyaddr
= (IPG_NIC_PHY_ADDRESS
+ i
) % 32;
451 /* 10/22/03 Grace change verify from GMII_PHY_STATUS to
455 status
= mdio_read(dev
, phyaddr
, MII_BMSR
);
457 if ((status
!= 0xFFFF) && (status
!= 0))
465 * Configure IPG based on result of IEEE 802.3 PHY
468 static int ipg_config_autoneg(struct net_device
*dev
)
470 struct ipg_nic_private
*sp
= netdev_priv(dev
);
471 void __iomem
*ioaddr
= sp
->ioaddr
;
472 unsigned int txflowcontrol
;
473 unsigned int rxflowcontrol
;
474 unsigned int fullduplex
;
480 IPG_DEBUG_MSG("_config_autoneg\n");
482 asicctrl
= ipg_r32(ASIC_CTRL
);
483 phyctrl
= ipg_r8(PHY_CTRL
);
484 mac_ctrl_val
= ipg_r32(MAC_CTRL
);
486 /* Set flags for use in resolving auto-negotation, assuming
487 * non-1000Mbps, half duplex, no flow control.
494 /* To accomodate a problem in 10Mbps operation,
495 * set a global flag if PHY running in 10Mbps mode.
499 printk(KERN_INFO
"%s: Link speed = ", dev
->name
);
501 /* Determine actual speed of operation. */
502 switch (phyctrl
& IPG_PC_LINK_SPEED
) {
503 case IPG_PC_LINK_SPEED_10MBPS
:
505 printk(KERN_INFO
"%s: 10Mbps operational mode enabled.\n",
509 case IPG_PC_LINK_SPEED_100MBPS
:
510 printk("100Mbps.\n");
512 case IPG_PC_LINK_SPEED_1000MBPS
:
513 printk("1000Mbps.\n");
517 printk("undefined!\n");
521 if (phyctrl
& IPG_PC_DUPLEX_STATUS
) {
527 /* Configure full duplex, and flow control. */
528 if (fullduplex
== 1) {
529 /* Configure IPG for full duplex operation. */
530 printk(KERN_INFO
"%s: setting full duplex, ", dev
->name
);
532 mac_ctrl_val
|= IPG_MC_DUPLEX_SELECT_FD
;
534 if (txflowcontrol
== 1) {
535 printk("TX flow control");
536 mac_ctrl_val
|= IPG_MC_TX_FLOW_CONTROL_ENABLE
;
538 printk("no TX flow control");
539 mac_ctrl_val
&= ~IPG_MC_TX_FLOW_CONTROL_ENABLE
;
542 if (rxflowcontrol
== 1) {
543 printk(", RX flow control.");
544 mac_ctrl_val
|= IPG_MC_RX_FLOW_CONTROL_ENABLE
;
546 printk(", no RX flow control.");
547 mac_ctrl_val
&= ~IPG_MC_RX_FLOW_CONTROL_ENABLE
;
552 /* Configure IPG for half duplex operation. */
553 printk(KERN_INFO
"%s: setting half duplex, "
554 "no TX flow control, no RX flow control.\n", dev
->name
);
556 mac_ctrl_val
&= ~IPG_MC_DUPLEX_SELECT_FD
&
557 ~IPG_MC_TX_FLOW_CONTROL_ENABLE
&
558 ~IPG_MC_RX_FLOW_CONTROL_ENABLE
;
560 ipg_w32(mac_ctrl_val
, MAC_CTRL
);
564 /* Determine and configure multicast operation and set
565 * receive mode for IPG.
567 static void ipg_nic_set_multicast_list(struct net_device
*dev
)
569 void __iomem
*ioaddr
= ipg_ioaddr(dev
);
570 struct dev_mc_list
*mc_list_ptr
;
571 unsigned int hashindex
;
575 IPG_DEBUG_MSG("_nic_set_multicast_list\n");
577 receivemode
= IPG_RM_RECEIVEUNICAST
| IPG_RM_RECEIVEBROADCAST
;
579 if (dev
->flags
& IFF_PROMISC
) {
580 /* NIC to be configured in promiscuous mode. */
581 receivemode
= IPG_RM_RECEIVEALLFRAMES
;
582 } else if ((dev
->flags
& IFF_ALLMULTI
) ||
583 (dev
->flags
& IFF_MULTICAST
&
584 (dev
->mc_count
> IPG_MULTICAST_HASHTABLE_SIZE
))) {
585 /* NIC to be configured to receive all multicast
587 receivemode
|= IPG_RM_RECEIVEMULTICAST
;
588 } else if (dev
->flags
& IFF_MULTICAST
& (dev
->mc_count
> 0)) {
589 /* NIC to be configured to receive selected
590 * multicast addresses. */
591 receivemode
|= IPG_RM_RECEIVEMULTICASTHASH
;
594 /* Calculate the bits to set for the 64 bit, IPG HASHTABLE.
595 * The IPG applies a cyclic-redundancy-check (the same CRC
596 * used to calculate the frame data FCS) to the destination
597 * address all incoming multicast frames whose destination
598 * address has the multicast bit set. The least significant
599 * 6 bits of the CRC result are used as an addressing index
600 * into the hash table. If the value of the bit addressed by
601 * this index is a 1, the frame is passed to the host system.
604 /* Clear hashtable. */
605 hashtable
[0] = 0x00000000;
606 hashtable
[1] = 0x00000000;
608 /* Cycle through all multicast addresses to filter. */
609 for (mc_list_ptr
= dev
->mc_list
;
610 mc_list_ptr
!= NULL
; mc_list_ptr
= mc_list_ptr
->next
) {
611 /* Calculate CRC result for each multicast address. */
612 hashindex
= crc32_le(0xffffffff, mc_list_ptr
->dmi_addr
,
615 /* Use only the least significant 6 bits. */
616 hashindex
= hashindex
& 0x3F;
618 /* Within "hashtable", set bit number "hashindex"
621 set_bit(hashindex
, (void *)hashtable
);
624 /* Write the value of the hashtable, to the 4, 16 bit
625 * HASHTABLE IPG registers.
627 ipg_w32(hashtable
[0], HASHTABLE_0
);
628 ipg_w32(hashtable
[1], HASHTABLE_1
);
630 ipg_w8(IPG_RM_RSVD_MASK
& receivemode
, RECEIVE_MODE
);
632 IPG_DEBUG_MSG("ReceiveMode = %x\n", ipg_r8(RECEIVE_MODE
));
635 static int ipg_io_config(struct net_device
*dev
)
637 void __iomem
*ioaddr
= ipg_ioaddr(dev
);
641 IPG_DEBUG_MSG("_io_config\n");
643 origmacctrl
= ipg_r32(MAC_CTRL
);
645 restoremacctrl
= origmacctrl
| IPG_MC_STATISTICS_ENABLE
;
647 /* Based on compilation option, determine if FCS is to be
648 * stripped on receive frames by IPG.
650 if (!IPG_STRIP_FCS_ON_RX
)
651 restoremacctrl
|= IPG_MC_RCV_FCS
;
653 /* Determine if transmitter and/or receiver are
654 * enabled so we may restore MACCTRL correctly.
656 if (origmacctrl
& IPG_MC_TX_ENABLED
)
657 restoremacctrl
|= IPG_MC_TX_ENABLE
;
659 if (origmacctrl
& IPG_MC_RX_ENABLED
)
660 restoremacctrl
|= IPG_MC_RX_ENABLE
;
662 /* Transmitter and receiver must be disabled before setting
665 ipg_w32((origmacctrl
& (IPG_MC_RX_DISABLE
| IPG_MC_TX_DISABLE
)) &
666 IPG_MC_RSVD_MASK
, MAC_CTRL
);
668 /* Now that transmitter and receiver are disabled, write
671 ipg_w32((origmacctrl
& IPG_MC_IFS_96BIT
) & IPG_MC_RSVD_MASK
, MAC_CTRL
);
673 /* Set RECEIVEMODE register. */
674 ipg_nic_set_multicast_list(dev
);
676 ipg_w16(IPG_MAX_RXFRAME_SIZE
, MAX_FRAME_SIZE
);
678 ipg_w8(IPG_RXDMAPOLLPERIOD_VALUE
, RX_DMA_POLL_PERIOD
);
679 ipg_w8(IPG_RXDMAURGENTTHRESH_VALUE
, RX_DMA_URGENT_THRESH
);
680 ipg_w8(IPG_RXDMABURSTTHRESH_VALUE
, RX_DMA_BURST_THRESH
);
681 ipg_w8(IPG_TXDMAPOLLPERIOD_VALUE
, TX_DMA_POLL_PERIOD
);
682 ipg_w8(IPG_TXDMAURGENTTHRESH_VALUE
, TX_DMA_URGENT_THRESH
);
683 ipg_w8(IPG_TXDMABURSTTHRESH_VALUE
, TX_DMA_BURST_THRESH
);
684 ipg_w16((IPG_IE_HOST_ERROR
| IPG_IE_TX_DMA_COMPLETE
|
685 IPG_IE_TX_COMPLETE
| IPG_IE_INT_REQUESTED
|
686 IPG_IE_UPDATE_STATS
| IPG_IE_LINK_EVENT
|
687 IPG_IE_RX_DMA_COMPLETE
| IPG_IE_RX_DMA_PRIORITY
), INT_ENABLE
);
688 ipg_w16(IPG_FLOWONTHRESH_VALUE
, FLOW_ON_THRESH
);
689 ipg_w16(IPG_FLOWOFFTHRESH_VALUE
, FLOW_OFF_THRESH
);
691 /* IPG multi-frag frame bug workaround.
692 * Per silicon revision B3 eratta.
694 ipg_w16(ipg_r16(DEBUG_CTRL
) | 0x0200, DEBUG_CTRL
);
696 /* IPG TX poll now bug workaround.
697 * Per silicon revision B3 eratta.
699 ipg_w16(ipg_r16(DEBUG_CTRL
) | 0x0010, DEBUG_CTRL
);
701 /* IPG RX poll now bug workaround.
702 * Per silicon revision B3 eratta.
704 ipg_w16(ipg_r16(DEBUG_CTRL
) | 0x0020, DEBUG_CTRL
);
706 /* Now restore MACCTRL to original setting. */
707 ipg_w32(IPG_MC_RSVD_MASK
& restoremacctrl
, MAC_CTRL
);
709 /* Disable unused RMON statistics. */
710 ipg_w32(IPG_RZ_ALL
, RMON_STATISTICS_MASK
);
712 /* Disable unused MIB statistics. */
713 ipg_w32(IPG_SM_MACCONTROLFRAMESXMTD
| IPG_SM_MACCONTROLFRAMESRCVD
|
714 IPG_SM_BCSTOCTETXMTOK_BCSTFRAMESXMTDOK
| IPG_SM_TXJUMBOFRAMES
|
715 IPG_SM_MCSTOCTETXMTOK_MCSTFRAMESXMTDOK
| IPG_SM_RXJUMBOFRAMES
|
716 IPG_SM_BCSTOCTETRCVDOK_BCSTFRAMESRCVDOK
|
717 IPG_SM_UDPCHECKSUMERRORS
| IPG_SM_TCPCHECKSUMERRORS
|
718 IPG_SM_IPCHECKSUMERRORS
, STATISTICS_MASK
);
724 * Create a receive buffer within system memory and update
725 * NIC private structure appropriately.
727 static int ipg_get_rxbuff(struct net_device
*dev
, int entry
)
729 struct ipg_nic_private
*sp
= netdev_priv(dev
);
730 struct ipg_rx
*rxfd
= sp
->rxd
+ entry
;
734 IPG_DEBUG_MSG("_get_rxbuff\n");
736 skb
= netdev_alloc_skb(dev
, IPG_RXSUPPORT_SIZE
+ NET_IP_ALIGN
);
738 sp
->RxBuff
[entry
] = NULL
;
742 /* Adjust the data start location within the buffer to
743 * align IP address field to a 16 byte boundary.
745 skb_reserve(skb
, NET_IP_ALIGN
);
747 /* Associate the receive buffer with the IPG NIC. */
750 /* Save the address of the sk_buff structure. */
751 sp
->RxBuff
[entry
] = skb
;
753 rxfd
->frag_info
= cpu_to_le64(pci_map_single(sp
->pdev
, skb
->data
,
754 sp
->rx_buf_sz
, PCI_DMA_FROMDEVICE
));
756 /* Set the RFD fragment length. */
757 rxfragsize
= IPG_RXFRAG_SIZE
;
758 rxfd
->frag_info
|= cpu_to_le64((rxfragsize
<< 48) & IPG_RFI_FRAGLEN
);
763 static int init_rfdlist(struct net_device
*dev
)
765 struct ipg_nic_private
*sp
= netdev_priv(dev
);
766 void __iomem
*ioaddr
= sp
->ioaddr
;
769 IPG_DEBUG_MSG("_init_rfdlist\n");
771 for (i
= 0; i
< IPG_RFDLIST_LENGTH
; i
++) {
772 struct ipg_rx
*rxfd
= sp
->rxd
+ i
;
775 pci_unmap_single(sp
->pdev
,
776 le64_to_cpu(rxfd
->frag_info
) & ~IPG_RFI_FRAGLEN
,
777 sp
->rx_buf_sz
, PCI_DMA_FROMDEVICE
);
778 dev_kfree_skb_irq(sp
->RxBuff
[i
]);
779 sp
->RxBuff
[i
] = NULL
;
782 /* Clear out the RFS field. */
783 rxfd
->rfs
= 0x0000000000000000;
785 if (ipg_get_rxbuff(dev
, i
) < 0) {
787 * A receive buffer was not ready, break the
790 IPG_DEBUG_MSG("Cannot allocate Rx buffer.\n");
792 /* Just in case we cannot allocate a single RFD.
796 printk(KERN_ERR
"%s: No memory available"
797 " for RFD list.\n", dev
->name
);
802 rxfd
->next_desc
= cpu_to_le64(sp
->rxd_map
+
803 sizeof(struct ipg_rx
)*(i
+ 1));
805 sp
->rxd
[i
- 1].next_desc
= cpu_to_le64(sp
->rxd_map
);
810 /* Write the location of the RFDList to the IPG. */
811 ipg_w32((u32
) sp
->rxd_map
, RFD_LIST_PTR_0
);
812 ipg_w32(0x00000000, RFD_LIST_PTR_1
);
817 static void init_tfdlist(struct net_device
*dev
)
819 struct ipg_nic_private
*sp
= netdev_priv(dev
);
820 void __iomem
*ioaddr
= sp
->ioaddr
;
823 IPG_DEBUG_MSG("_init_tfdlist\n");
825 for (i
= 0; i
< IPG_TFDLIST_LENGTH
; i
++) {
826 struct ipg_tx
*txfd
= sp
->txd
+ i
;
828 txfd
->tfc
= cpu_to_le64(IPG_TFC_TFDDONE
);
831 dev_kfree_skb_irq(sp
->TxBuff
[i
]);
832 sp
->TxBuff
[i
] = NULL
;
835 txfd
->next_desc
= cpu_to_le64(sp
->txd_map
+
836 sizeof(struct ipg_tx
)*(i
+ 1));
838 sp
->txd
[i
- 1].next_desc
= cpu_to_le64(sp
->txd_map
);
843 /* Write the location of the TFDList to the IPG. */
844 IPG_DDEBUG_MSG("Starting TFDListPtr = %8.8x\n",
846 ipg_w32((u32
) sp
->txd_map
, TFD_LIST_PTR_0
);
847 ipg_w32(0x00000000, TFD_LIST_PTR_1
);
849 sp
->ResetCurrentTFD
= 1;
853 * Free all transmit buffers which have already been transfered
854 * via DMA to the IPG.
856 static void ipg_nic_txfree(struct net_device
*dev
)
858 struct ipg_nic_private
*sp
= netdev_priv(dev
);
859 unsigned int released
, pending
, dirty
;
861 IPG_DEBUG_MSG("_nic_txfree\n");
863 pending
= sp
->tx_current
- sp
->tx_dirty
;
864 dirty
= sp
->tx_dirty
% IPG_TFDLIST_LENGTH
;
866 for (released
= 0; released
< pending
; released
++) {
867 struct sk_buff
*skb
= sp
->TxBuff
[dirty
];
868 struct ipg_tx
*txfd
= sp
->txd
+ dirty
;
870 IPG_DEBUG_MSG("TFC = %16.16lx\n", (unsigned long) txfd
->tfc
);
872 /* Look at each TFD's TFC field beginning
873 * at the last freed TFD up to the current TFD.
874 * If the TFDDone bit is set, free the associated
877 if (!(txfd
->tfc
& cpu_to_le64(IPG_TFC_TFDDONE
)))
880 /* Free the transmit buffer. */
882 pci_unmap_single(sp
->pdev
,
883 le64_to_cpu(txfd
->frag_info
) & ~IPG_TFI_FRAGLEN
,
884 skb
->len
, PCI_DMA_TODEVICE
);
886 dev_kfree_skb_irq(skb
);
888 sp
->TxBuff
[dirty
] = NULL
;
890 dirty
= (dirty
+ 1) % IPG_TFDLIST_LENGTH
;
893 sp
->tx_dirty
+= released
;
895 if (netif_queue_stopped(dev
) &&
896 (sp
->tx_current
!= (sp
->tx_dirty
+ IPG_TFDLIST_LENGTH
))) {
897 netif_wake_queue(dev
);
901 static void ipg_tx_timeout(struct net_device
*dev
)
903 struct ipg_nic_private
*sp
= netdev_priv(dev
);
904 void __iomem
*ioaddr
= sp
->ioaddr
;
906 ipg_reset(dev
, IPG_AC_TX_RESET
| IPG_AC_DMA
| IPG_AC_NETWORK
|
909 spin_lock_irq(&sp
->lock
);
911 /* Re-configure after DMA reset. */
912 if (ipg_io_config(dev
) < 0) {
913 printk(KERN_INFO
"%s: Error during re-configuration.\n",
919 spin_unlock_irq(&sp
->lock
);
921 ipg_w32((ipg_r32(MAC_CTRL
) | IPG_MC_TX_ENABLE
) & IPG_MC_RSVD_MASK
,
926 * For TxComplete interrupts, free all transmit
927 * buffers which have already been transfered via DMA
930 static void ipg_nic_txcleanup(struct net_device
*dev
)
932 struct ipg_nic_private
*sp
= netdev_priv(dev
);
933 void __iomem
*ioaddr
= sp
->ioaddr
;
936 IPG_DEBUG_MSG("_nic_txcleanup\n");
938 for (i
= 0; i
< IPG_TFDLIST_LENGTH
; i
++) {
939 /* Reading the TXSTATUS register clears the
940 * TX_COMPLETE interrupt.
942 u32 txstatusdword
= ipg_r32(TX_STATUS
);
944 IPG_DEBUG_MSG("TxStatus = %8.8x\n", txstatusdword
);
946 /* Check for Transmit errors. Error bits only valid if
947 * TX_COMPLETE bit in the TXSTATUS register is a 1.
949 if (!(txstatusdword
& IPG_TS_TX_COMPLETE
))
952 /* If in 10Mbps mode, indicate transmit is ready. */
953 if (sp
->tenmbpsmode
) {
954 netif_wake_queue(dev
);
957 /* Transmit error, increment stat counters. */
958 if (txstatusdword
& IPG_TS_TX_ERROR
) {
959 IPG_DEBUG_MSG("Transmit error.\n");
960 sp
->stats
.tx_errors
++;
963 /* Late collision, re-enable transmitter. */
964 if (txstatusdword
& IPG_TS_LATE_COLLISION
) {
965 IPG_DEBUG_MSG("Late collision on transmit.\n");
966 ipg_w32((ipg_r32(MAC_CTRL
) | IPG_MC_TX_ENABLE
) &
967 IPG_MC_RSVD_MASK
, MAC_CTRL
);
970 /* Maximum collisions, re-enable transmitter. */
971 if (txstatusdword
& IPG_TS_TX_MAX_COLL
) {
972 IPG_DEBUG_MSG("Maximum collisions on transmit.\n");
973 ipg_w32((ipg_r32(MAC_CTRL
) | IPG_MC_TX_ENABLE
) &
974 IPG_MC_RSVD_MASK
, MAC_CTRL
);
977 /* Transmit underrun, reset and re-enable
980 if (txstatusdword
& IPG_TS_TX_UNDERRUN
) {
981 IPG_DEBUG_MSG("Transmitter underrun.\n");
982 sp
->stats
.tx_fifo_errors
++;
983 ipg_reset(dev
, IPG_AC_TX_RESET
| IPG_AC_DMA
|
984 IPG_AC_NETWORK
| IPG_AC_FIFO
);
986 /* Re-configure after DMA reset. */
987 if (ipg_io_config(dev
) < 0) {
989 "%s: Error during re-configuration.\n",
994 ipg_w32((ipg_r32(MAC_CTRL
) | IPG_MC_TX_ENABLE
) &
995 IPG_MC_RSVD_MASK
, MAC_CTRL
);
1002 /* Provides statistical information about the IPG NIC. */
1003 static struct net_device_stats
*ipg_nic_get_stats(struct net_device
*dev
)
1005 struct ipg_nic_private
*sp
= netdev_priv(dev
);
1006 void __iomem
*ioaddr
= sp
->ioaddr
;
1010 IPG_DEBUG_MSG("_nic_get_stats\n");
1012 /* Check to see if the NIC has been initialized via nic_open,
1013 * before trying to read statistic registers.
1015 if (!test_bit(__LINK_STATE_START
, &dev
->state
))
1018 sp
->stats
.rx_packets
+= ipg_r32(IPG_FRAMESRCVDOK
);
1019 sp
->stats
.tx_packets
+= ipg_r32(IPG_FRAMESXMTDOK
);
1020 sp
->stats
.rx_bytes
+= ipg_r32(IPG_OCTETRCVOK
);
1021 sp
->stats
.tx_bytes
+= ipg_r32(IPG_OCTETXMTOK
);
1022 temp1
= ipg_r16(IPG_FRAMESLOSTRXERRORS
);
1023 sp
->stats
.rx_errors
+= temp1
;
1024 sp
->stats
.rx_missed_errors
+= temp1
;
1025 temp1
= ipg_r32(IPG_SINGLECOLFRAMES
) + ipg_r32(IPG_MULTICOLFRAMES
) +
1026 ipg_r32(IPG_LATECOLLISIONS
);
1027 temp2
= ipg_r16(IPG_CARRIERSENSEERRORS
);
1028 sp
->stats
.collisions
+= temp1
;
1029 sp
->stats
.tx_dropped
+= ipg_r16(IPG_FRAMESABORTXSCOLLS
);
1030 sp
->stats
.tx_errors
+= ipg_r16(IPG_FRAMESWEXDEFERRAL
) +
1031 ipg_r32(IPG_FRAMESWDEFERREDXMT
) + temp1
+ temp2
;
1032 sp
->stats
.multicast
+= ipg_r32(IPG_MCSTOCTETRCVDOK
);
1034 /* detailed tx_errors */
1035 sp
->stats
.tx_carrier_errors
+= temp2
;
1037 /* detailed rx_errors */
1038 sp
->stats
.rx_length_errors
+= ipg_r16(IPG_INRANGELENGTHERRORS
) +
1039 ipg_r16(IPG_FRAMETOOLONGERRRORS
);
1040 sp
->stats
.rx_crc_errors
+= ipg_r16(IPG_FRAMECHECKSEQERRORS
);
1042 /* Unutilized IPG statistic registers. */
1043 ipg_r32(IPG_MCSTFRAMESRCVDOK
);
1048 /* Restore used receive buffers. */
1049 static int ipg_nic_rxrestore(struct net_device
*dev
)
1051 struct ipg_nic_private
*sp
= netdev_priv(dev
);
1052 const unsigned int curr
= sp
->rx_current
;
1053 unsigned int dirty
= sp
->rx_dirty
;
1055 IPG_DEBUG_MSG("_nic_rxrestore\n");
1057 for (dirty
= sp
->rx_dirty
; curr
- dirty
> 0; dirty
++) {
1058 unsigned int entry
= dirty
% IPG_RFDLIST_LENGTH
;
1060 /* rx_copybreak may poke hole here and there. */
1061 if (sp
->RxBuff
[entry
])
1064 /* Generate a new receive buffer to replace the
1065 * current buffer (which will be released by the
1068 if (ipg_get_rxbuff(dev
, entry
) < 0) {
1069 IPG_DEBUG_MSG("Cannot allocate new Rx buffer.\n");
1074 /* Reset the RFS field. */
1075 sp
->rxd
[entry
].rfs
= 0x0000000000000000;
1077 sp
->rx_dirty
= dirty
;
1084 /* use jumboindex and jumbosize to control jumbo frame status
1085 initial status is jumboindex=-1 and jumbosize=0
1086 1. jumboindex = -1 and jumbosize=0 : previous jumbo frame has been done.
1087 2. jumboindex != -1 and jumbosize != 0 : jumbo frame is not over size and receiving
1088 3. jumboindex = -1 and jumbosize != 0 : jumbo frame is over size, already dump
1089 previous receiving and need to continue dumping the current one
1097 Frame_NoStart_NoEnd
= 0,
1098 Frame_WithStart
= 1,
1100 Frame_WithStart_WithEnd
= 11
1103 inline void ipg_nic_rx_free_skb(struct net_device
*dev
)
1105 struct ipg_nic_private
*sp
= netdev_priv(dev
);
1106 unsigned int entry
= sp
->rx_current
% IPG_RFDLIST_LENGTH
;
1108 if (sp
->RxBuff
[entry
]) {
1109 struct ipg_rx
*rxfd
= sp
->rxd
+ entry
;
1111 pci_unmap_single(sp
->pdev
,
1112 le64_to_cpu(rxfd
->frag_info
& ~IPG_RFI_FRAGLEN
),
1113 sp
->rx_buf_sz
, PCI_DMA_FROMDEVICE
);
1114 dev_kfree_skb_irq(sp
->RxBuff
[entry
]);
1115 sp
->RxBuff
[entry
] = NULL
;
1119 inline int ipg_nic_rx_check_frame_type(struct net_device
*dev
)
1121 struct ipg_nic_private
*sp
= netdev_priv(dev
);
1122 struct ipg_rx
*rxfd
= sp
->rxd
+ (sp
->rx_current
% IPG_RFDLIST_LENGTH
);
1123 int type
= Frame_NoStart_NoEnd
;
1125 if (le64_to_cpu(rxfd
->rfs
) & IPG_RFS_FRAMESTART
)
1126 type
+= Frame_WithStart
;
1127 if (le64_to_cpu(rxfd
->rfs
) & IPG_RFS_FRAMEEND
)
1128 type
+= Frame_WithEnd
;
1132 inline int ipg_nic_rx_check_error(struct net_device
*dev
)
1134 struct ipg_nic_private
*sp
= netdev_priv(dev
);
1135 unsigned int entry
= sp
->rx_current
% IPG_RFDLIST_LENGTH
;
1136 struct ipg_rx
*rxfd
= sp
->rxd
+ entry
;
1138 if (IPG_DROP_ON_RX_ETH_ERRORS
&& (le64_to_cpu(rxfd
->rfs
) &
1139 (IPG_RFS_RXFIFOOVERRUN
| IPG_RFS_RXRUNTFRAME
|
1140 IPG_RFS_RXALIGNMENTERROR
| IPG_RFS_RXFCSERROR
|
1141 IPG_RFS_RXOVERSIZEDFRAME
| IPG_RFS_RXLENGTHERROR
))) {
1142 IPG_DEBUG_MSG("Rx error, RFS = %16.16lx\n",
1143 (unsigned long) rxfd
->rfs
);
1145 /* Increment general receive error statistic. */
1146 sp
->stats
.rx_errors
++;
1148 /* Increment detailed receive error statistics. */
1149 if (le64_to_cpu(rxfd
->rfs
) & IPG_RFS_RXFIFOOVERRUN
) {
1150 IPG_DEBUG_MSG("RX FIFO overrun occured.\n");
1152 sp
->stats
.rx_fifo_errors
++;
1155 if (le64_to_cpu(rxfd
->rfs
) & IPG_RFS_RXRUNTFRAME
) {
1156 IPG_DEBUG_MSG("RX runt occured.\n");
1157 sp
->stats
.rx_length_errors
++;
1160 /* Do nothing for IPG_RFS_RXOVERSIZEDFRAME,
1161 * error count handled by a IPG statistic register.
1164 if (le64_to_cpu(rxfd
->rfs
) & IPG_RFS_RXALIGNMENTERROR
) {
1165 IPG_DEBUG_MSG("RX alignment error occured.\n");
1166 sp
->stats
.rx_frame_errors
++;
1169 /* Do nothing for IPG_RFS_RXFCSERROR, error count
1170 * handled by a IPG statistic register.
1173 /* Free the memory associated with the RX
1174 * buffer since it is erroneous and we will
1175 * not pass it to higher layer processes.
1177 if (sp
->RxBuff
[entry
]) {
1178 pci_unmap_single(sp
->pdev
,
1179 le64_to_cpu(rxfd
->frag_info
& ~IPG_RFI_FRAGLEN
),
1180 sp
->rx_buf_sz
, PCI_DMA_FROMDEVICE
);
1182 dev_kfree_skb_irq(sp
->RxBuff
[entry
]);
1183 sp
->RxBuff
[entry
] = NULL
;
1187 return NormalPacket
;
1190 static void ipg_nic_rx_with_start_and_end(struct net_device
*dev
,
1191 struct ipg_nic_private
*sp
,
1192 struct ipg_rx
*rxfd
, unsigned entry
)
1194 struct SJumbo
*jumbo
= &sp
->Jumbo
;
1195 struct sk_buff
*skb
;
1198 if (jumbo
->FoundStart
) {
1199 dev_kfree_skb_irq(jumbo
->skb
);
1200 jumbo
->FoundStart
= 0;
1201 jumbo
->CurrentSize
= 0;
1205 // 1: found error, 0 no error
1206 if (ipg_nic_rx_check_error(dev
) != NormalPacket
)
1209 skb
= sp
->RxBuff
[entry
];
1213 // accept this frame and send to upper layer
1214 framelen
= le64_to_cpu(rxfd
->rfs
) & IPG_RFS_RXFRAMELEN
;
1215 if (framelen
> IPG_RXFRAG_SIZE
)
1216 framelen
= IPG_RXFRAG_SIZE
;
1218 skb_put(skb
, framelen
);
1219 skb
->protocol
= eth_type_trans(skb
, dev
);
1220 skb
->ip_summed
= CHECKSUM_NONE
;
1222 dev
->last_rx
= jiffies
;
1223 sp
->RxBuff
[entry
] = NULL
;
1226 static void ipg_nic_rx_with_start(struct net_device
*dev
,
1227 struct ipg_nic_private
*sp
,
1228 struct ipg_rx
*rxfd
, unsigned entry
)
1230 struct SJumbo
*jumbo
= &sp
->Jumbo
;
1231 struct pci_dev
*pdev
= sp
->pdev
;
1232 struct sk_buff
*skb
;
1234 // 1: found error, 0 no error
1235 if (ipg_nic_rx_check_error(dev
) != NormalPacket
)
1238 // accept this frame and send to upper layer
1239 skb
= sp
->RxBuff
[entry
];
1243 if (jumbo
->FoundStart
)
1244 dev_kfree_skb_irq(jumbo
->skb
);
1246 pci_unmap_single(pdev
, le64_to_cpu(rxfd
->frag_info
& ~IPG_RFI_FRAGLEN
),
1247 sp
->rx_buf_sz
, PCI_DMA_FROMDEVICE
);
1249 skb_put(skb
, IPG_RXFRAG_SIZE
);
1251 jumbo
->FoundStart
= 1;
1252 jumbo
->CurrentSize
= IPG_RXFRAG_SIZE
;
1255 sp
->RxBuff
[entry
] = NULL
;
1256 dev
->last_rx
= jiffies
;
1259 static void ipg_nic_rx_with_end(struct net_device
*dev
,
1260 struct ipg_nic_private
*sp
,
1261 struct ipg_rx
*rxfd
, unsigned entry
)
1263 struct SJumbo
*jumbo
= &sp
->Jumbo
;
1265 //1: found error, 0 no error
1266 if (ipg_nic_rx_check_error(dev
) == NormalPacket
) {
1267 struct sk_buff
*skb
= sp
->RxBuff
[entry
];
1272 if (jumbo
->FoundStart
) {
1273 int framelen
, endframelen
;
1275 framelen
= le64_to_cpu(rxfd
->rfs
) & IPG_RFS_RXFRAMELEN
;
1277 endframeLen
= framelen
- jumbo
->CurrentSize
;
1279 if (framelen > IPG_RXFRAG_SIZE)
1280 framelen=IPG_RXFRAG_SIZE;
1282 if (framelen
> IPG_RXSUPPORT_SIZE
)
1283 dev_kfree_skb_irq(jumbo
->skb
);
1285 memcpy(skb_put(jumbo
->skb
, endframeLen
),
1286 skb
->data
, endframeLen
);
1288 jumbo
->skb
->protocol
=
1289 eth_type_trans(jumbo
->skb
, dev
);
1291 jumbo
->skb
->ip_summed
= CHECKSUM_NONE
;
1292 netif_rx(jumbo
->skb
);
1296 dev
->last_rx
= jiffies
;
1297 jumbo
->FoundStart
= 0;
1298 jumbo
->CurrentSize
= 0;
1301 ipg_nic_rx_free_skb(dev
);
1303 dev_kfree_skb_irq(jumbo
->skb
);
1304 jumbo
->FoundStart
= 0;
1305 jumbo
->CurrentSize
= 0;
1310 static void ipg_nic_rx_no_start_no_end(struct net_device
*dev
,
1311 struct ipg_nic_private
*sp
,
1312 struct ipg_rx
*rxfd
, unsigned entry
)
1314 struct SJumbo
*jumbo
= &sp
->Jumbo
;
1316 //1: found error, 0 no error
1317 if (ipg_nic_rx_check_error(dev
) == NormalPacket
) {
1318 struct sk_buff
*skb
= sp
->RxBuff
[entry
];
1321 if (jumbo
->FoundStart
) {
1322 jumbo
->CurrentSize
+= IPG_RXFRAG_SIZE
;
1323 if (jumbo
->CurrentSize
<= IPG_RXSUPPORT_SIZE
) {
1324 memcpy(skb_put(jumbo
->skb
,
1326 skb
->data
, IPG_RXFRAG_SIZE
);
1329 dev
->last_rx
= jiffies
;
1330 ipg_nic_rx_free_skb(dev
);
1333 dev_kfree_skb_irq(jumbo
->skb
);
1334 jumbo
->FoundStart
= 0;
1335 jumbo
->CurrentSize
= 0;
1340 static int ipg_nic_rx(struct net_device
*dev
)
1342 struct ipg_nic_private
*sp
= netdev_priv(dev
);
1343 unsigned int curr
= sp
->rx_current
;
1344 void __iomem
*ioaddr
= sp
->ioaddr
;
1347 IPG_DEBUG_MSG("_nic_rx\n");
1349 for (i
= 0; i
< IPG_MAXRFDPROCESS_COUNT
; i
++, curr
++) {
1350 unsigned int entry
= curr
% IPG_RFDLIST_LENGTH
;
1351 struct ipg_rx
*rxfd
= sp
->rxd
+ entry
;
1353 if (!(rxfd
->rfs
& le64_to_cpu(IPG_RFS_RFDDONE
)))
1356 switch (ipg_nic_rx_check_frame_type(dev
)) {
1357 case Frame_WithStart_WithEnd
:
1358 ipg_nic_rx_with_start_and_end(dev
, tp
, rxfd
, entry
);
1360 case Frame_WithStart
:
1361 ipg_nic_rx_with_start(dev
, tp
, rxfd
, entry
);
1364 ipg_nic_rx_with_end(dev
, tp
, rxfd
, entry
);
1366 case Frame_NoStart_NoEnd
:
1367 ipg_nic_rx_no_start_no_end(dev
, tp
, rxfd
, entry
);
1372 sp
->rx_current
= curr
;
1374 if (i
== IPG_MAXRFDPROCESS_COUNT
) {
1375 /* There are more RFDs to process, however the
1376 * allocated amount of RFD processing time has
1377 * expired. Assert Interrupt Requested to make
1378 * sure we come back to process the remaining RFDs.
1380 ipg_w32(ipg_r32(ASIC_CTRL
) | IPG_AC_INT_REQUEST
, ASIC_CTRL
);
1383 ipg_nic_rxrestore(dev
);
1389 static int ipg_nic_rx(struct net_device
*dev
)
1391 /* Transfer received Ethernet frames to higher network layers. */
1392 struct ipg_nic_private
*sp
= netdev_priv(dev
);
1393 unsigned int curr
= sp
->rx_current
;
1394 void __iomem
*ioaddr
= sp
->ioaddr
;
1395 struct ipg_rx
*rxfd
;
1398 IPG_DEBUG_MSG("_nic_rx\n");
1400 #define __RFS_MASK \
1401 cpu_to_le64(IPG_RFS_RFDDONE | IPG_RFS_FRAMESTART | IPG_RFS_FRAMEEND)
1403 for (i
= 0; i
< IPG_MAXRFDPROCESS_COUNT
; i
++, curr
++) {
1404 unsigned int entry
= curr
% IPG_RFDLIST_LENGTH
;
1405 struct sk_buff
*skb
= sp
->RxBuff
[entry
];
1406 unsigned int framelen
;
1408 rxfd
= sp
->rxd
+ entry
;
1410 if (((rxfd
->rfs
& __RFS_MASK
) != __RFS_MASK
) || !skb
)
1413 /* Get received frame length. */
1414 framelen
= le64_to_cpu(rxfd
->rfs
) & IPG_RFS_RXFRAMELEN
;
1416 /* Check for jumbo frame arrival with too small
1419 if (framelen
> IPG_RXFRAG_SIZE
) {
1421 ("RFS FrameLen > allocated fragment size.\n");
1423 framelen
= IPG_RXFRAG_SIZE
;
1426 if ((IPG_DROP_ON_RX_ETH_ERRORS
&& (le64_to_cpu(rxfd
->rfs
) &
1427 (IPG_RFS_RXFIFOOVERRUN
| IPG_RFS_RXRUNTFRAME
|
1428 IPG_RFS_RXALIGNMENTERROR
| IPG_RFS_RXFCSERROR
|
1429 IPG_RFS_RXOVERSIZEDFRAME
| IPG_RFS_RXLENGTHERROR
)))) {
1431 IPG_DEBUG_MSG("Rx error, RFS = %16.16lx\n",
1432 (unsigned long int) rxfd
->rfs
);
1434 /* Increment general receive error statistic. */
1435 sp
->stats
.rx_errors
++;
1437 /* Increment detailed receive error statistics. */
1438 if (le64_to_cpu(rxfd
->rfs
) & IPG_RFS_RXFIFOOVERRUN
) {
1439 IPG_DEBUG_MSG("RX FIFO overrun occured.\n");
1440 sp
->stats
.rx_fifo_errors
++;
1443 if (le64_to_cpu(rxfd
->rfs
) & IPG_RFS_RXRUNTFRAME
) {
1444 IPG_DEBUG_MSG("RX runt occured.\n");
1445 sp
->stats
.rx_length_errors
++;
1448 if (le64_to_cpu(rxfd
->rfs
) & IPG_RFS_RXOVERSIZEDFRAME
) ;
1449 /* Do nothing, error count handled by a IPG
1450 * statistic register.
1453 if (le64_to_cpu(rxfd
->rfs
) & IPG_RFS_RXALIGNMENTERROR
) {
1454 IPG_DEBUG_MSG("RX alignment error occured.\n");
1455 sp
->stats
.rx_frame_errors
++;
1458 if (le64_to_cpu(rxfd
->rfs
) & IPG_RFS_RXFCSERROR
) ;
1459 /* Do nothing, error count handled by a IPG
1460 * statistic register.
1463 /* Free the memory associated with the RX
1464 * buffer since it is erroneous and we will
1465 * not pass it to higher layer processes.
1468 __le64 info
= rxfd
->frag_info
;
1470 pci_unmap_single(sp
->pdev
,
1471 le64_to_cpu(info
) & ~IPG_RFI_FRAGLEN
,
1472 sp
->rx_buf_sz
, PCI_DMA_FROMDEVICE
);
1474 dev_kfree_skb_irq(skb
);
1478 /* Adjust the new buffer length to accomodate the size
1479 * of the received frame.
1481 skb_put(skb
, framelen
);
1483 /* Set the buffer's protocol field to Ethernet. */
1484 skb
->protocol
= eth_type_trans(skb
, dev
);
1486 /* If the frame contains an IP/TCP/UDP frame,
1487 * determine if upper layer must check IP/TCP/UDP
1490 * NOTE: DO NOT RELY ON THE TCP/UDP CHECKSUM
1491 * VERIFICATION FOR SILICON REVISIONS B3
1494 if ((le64_to_cpu(rxfd->rfs &
1495 (IPG_RFS_TCPDETECTED | IPG_RFS_UDPDETECTED |
1496 IPG_RFS_IPDETECTED))) &&
1497 !(le64_to_cpu(rxfd->rfs &
1498 (IPG_RFS_TCPERROR | IPG_RFS_UDPERROR |
1499 IPG_RFS_IPERROR)))) {
1500 * Indicate IP checksums were performed
1503 skb->ip_summed = CHECKSUM_UNNECESSARY;
1507 /* The IPG encountered an error with (or
1508 * there were no) IP/TCP/UDP checksums.
1509 * This may or may not indicate an invalid
1510 * IP/TCP/UDP frame was received. Let the
1511 * upper layer decide.
1513 skb
->ip_summed
= CHECKSUM_NONE
;
1516 /* Hand off frame for higher layer processing.
1517 * The function netif_rx() releases the sk_buff
1518 * when processing completes.
1522 /* Record frame receive time (jiffies = Linux
1523 * kernel current time stamp).
1525 dev
->last_rx
= jiffies
;
1528 /* Assure RX buffer is not reused by IPG. */
1529 sp
->RxBuff
[entry
] = NULL
;
1533 * If there are more RFDs to proces and the allocated amount of RFD
1534 * processing time has expired, assert Interrupt Requested to make
1535 * sure we come back to process the remaining RFDs.
1537 if (i
== IPG_MAXRFDPROCESS_COUNT
)
1538 ipg_w32(ipg_r32(ASIC_CTRL
) | IPG_AC_INT_REQUEST
, ASIC_CTRL
);
1541 /* Check if the RFD list contained no receive frame data. */
1543 sp
->EmptyRFDListCount
++;
1545 while ((le64_to_cpu(rxfd
->rfs
) & IPG_RFS_RFDDONE
) &&
1546 !((le64_to_cpu(rxfd
->rfs
) & IPG_RFS_FRAMESTART
) &&
1547 (le64_to_cpu(rxfd
->rfs
) & IPG_RFS_FRAMEEND
))) {
1548 unsigned int entry
= curr
++ % IPG_RFDLIST_LENGTH
;
1550 rxfd
= sp
->rxd
+ entry
;
1552 IPG_DEBUG_MSG("Frame requires multiple RFDs.\n");
1554 /* An unexpected event, additional code needed to handle
1555 * properly. So for the time being, just disregard the
1559 /* Free the memory associated with the RX
1560 * buffer since it is erroneous and we will
1561 * not pass it to higher layer processes.
1563 if (sp
->RxBuff
[entry
]) {
1564 pci_unmap_single(sp
->pdev
,
1565 le64_to_cpu(rxfd
->frag_info
) & ~IPG_RFI_FRAGLEN
,
1566 sp
->rx_buf_sz
, PCI_DMA_FROMDEVICE
);
1567 dev_kfree_skb_irq(sp
->RxBuff
[entry
]);
1570 /* Assure RX buffer is not reused by IPG. */
1571 sp
->RxBuff
[entry
] = NULL
;
1574 sp
->rx_current
= curr
;
1576 /* Check to see if there are a minimum number of used
1577 * RFDs before restoring any (should improve performance.)
1579 if ((curr
- sp
->rx_dirty
) >= IPG_MINUSEDRFDSTOFREE
)
1580 ipg_nic_rxrestore(dev
);
1586 static void ipg_reset_after_host_error(struct work_struct
*work
)
1588 struct ipg_nic_private
*sp
=
1589 container_of(work
, struct ipg_nic_private
, task
.work
);
1590 struct net_device
*dev
= sp
->dev
;
1592 IPG_DDEBUG_MSG("DMACtrl = %8.8x\n", ioread32(sp
->ioaddr
+ IPG_DMACTRL
));
1595 * Acknowledge HostError interrupt by resetting
1598 ipg_reset(dev
, IPG_AC_GLOBAL_RESET
| IPG_AC_HOST
| IPG_AC_DMA
);
1603 if (ipg_io_config(dev
) < 0) {
1604 printk(KERN_INFO
"%s: Cannot recover from PCI error.\n",
1606 schedule_delayed_work(&sp
->task
, HZ
);
1610 static irqreturn_t
ipg_interrupt_handler(int irq
, void *dev_inst
)
1612 struct net_device
*dev
= dev_inst
;
1613 struct ipg_nic_private
*sp
= netdev_priv(dev
);
1614 void __iomem
*ioaddr
= sp
->ioaddr
;
1615 unsigned int handled
= 0;
1618 IPG_DEBUG_MSG("_interrupt_handler\n");
1621 ipg_nic_rxrestore(dev
);
1623 spin_lock(&sp
->lock
);
1625 /* Get interrupt source information, and acknowledge
1626 * some (i.e. TxDMAComplete, RxDMAComplete, RxEarly,
1627 * IntRequested, MacControlFrame, LinkEvent) interrupts
1628 * if issued. Also, all IPG interrupts are disabled by
1629 * reading IntStatusAck.
1631 status
= ipg_r16(INT_STATUS_ACK
);
1633 IPG_DEBUG_MSG("IntStatusAck = %4.4x\n", status
);
1635 /* Shared IRQ of remove event. */
1636 if (!(status
& IPG_IS_RSVD_MASK
))
1641 if (unlikely(!netif_running(dev
)))
1644 /* If RFDListEnd interrupt, restore all used RFDs. */
1645 if (status
& IPG_IS_RFD_LIST_END
) {
1646 IPG_DEBUG_MSG("RFDListEnd Interrupt.\n");
1648 /* The RFD list end indicates an RFD was encountered
1649 * with a 0 NextPtr, or with an RFDDone bit set to 1
1650 * (indicating the RFD is not read for use by the
1651 * IPG.) Try to restore all RFDs.
1653 ipg_nic_rxrestore(dev
);
1656 /* Increment the RFDlistendCount counter. */
1657 sp
->RFDlistendCount
++;
1661 /* If RFDListEnd, RxDMAPriority, RxDMAComplete, or
1662 * IntRequested interrupt, process received frames. */
1663 if ((status
& IPG_IS_RX_DMA_PRIORITY
) ||
1664 (status
& IPG_IS_RFD_LIST_END
) ||
1665 (status
& IPG_IS_RX_DMA_COMPLETE
) ||
1666 (status
& IPG_IS_INT_REQUESTED
)) {
1668 /* Increment the RFD list checked counter if interrupted
1669 * only to check the RFD list. */
1670 if (status
& (~(IPG_IS_RX_DMA_PRIORITY
| IPG_IS_RFD_LIST_END
|
1671 IPG_IS_RX_DMA_COMPLETE
| IPG_IS_INT_REQUESTED
) &
1672 (IPG_IS_HOST_ERROR
| IPG_IS_TX_DMA_COMPLETE
|
1673 IPG_IS_LINK_EVENT
| IPG_IS_TX_COMPLETE
|
1674 IPG_IS_UPDATE_STATS
)))
1675 sp
->RFDListCheckedCount
++;
1681 /* If TxDMAComplete interrupt, free used TFDs. */
1682 if (status
& IPG_IS_TX_DMA_COMPLETE
)
1683 ipg_nic_txfree(dev
);
1685 /* TxComplete interrupts indicate one of numerous actions.
1686 * Determine what action to take based on TXSTATUS register.
1688 if (status
& IPG_IS_TX_COMPLETE
)
1689 ipg_nic_txcleanup(dev
);
1691 /* If UpdateStats interrupt, update Linux Ethernet statistics */
1692 if (status
& IPG_IS_UPDATE_STATS
)
1693 ipg_nic_get_stats(dev
);
1695 /* If HostError interrupt, reset IPG. */
1696 if (status
& IPG_IS_HOST_ERROR
) {
1697 IPG_DDEBUG_MSG("HostError Interrupt\n");
1699 schedule_delayed_work(&sp
->task
, 0);
1702 /* If LinkEvent interrupt, resolve autonegotiation. */
1703 if (status
& IPG_IS_LINK_EVENT
) {
1704 if (ipg_config_autoneg(dev
) < 0)
1705 printk(KERN_INFO
"%s: Auto-negotiation error.\n",
1709 /* If MACCtrlFrame interrupt, do nothing. */
1710 if (status
& IPG_IS_MAC_CTRL_FRAME
)
1711 IPG_DEBUG_MSG("MACCtrlFrame interrupt.\n");
1713 /* If RxComplete interrupt, do nothing. */
1714 if (status
& IPG_IS_RX_COMPLETE
)
1715 IPG_DEBUG_MSG("RxComplete interrupt.\n");
1717 /* If RxEarly interrupt, do nothing. */
1718 if (status
& IPG_IS_RX_EARLY
)
1719 IPG_DEBUG_MSG("RxEarly interrupt.\n");
1722 /* Re-enable IPG interrupts. */
1723 ipg_w16(IPG_IE_TX_DMA_COMPLETE
| IPG_IE_RX_DMA_COMPLETE
|
1724 IPG_IE_HOST_ERROR
| IPG_IE_INT_REQUESTED
| IPG_IE_TX_COMPLETE
|
1725 IPG_IE_LINK_EVENT
| IPG_IE_UPDATE_STATS
, INT_ENABLE
);
1727 spin_unlock(&sp
->lock
);
1729 return IRQ_RETVAL(handled
);
1732 static void ipg_rx_clear(struct ipg_nic_private
*sp
)
1736 for (i
= 0; i
< IPG_RFDLIST_LENGTH
; i
++) {
1737 if (sp
->RxBuff
[i
]) {
1738 struct ipg_rx
*rxfd
= sp
->rxd
+ i
;
1740 dev_kfree_skb_irq(sp
->RxBuff
[i
]);
1741 sp
->RxBuff
[i
] = NULL
;
1742 pci_unmap_single(sp
->pdev
,
1743 le64_to_cpu(rxfd
->frag_info
) & ~IPG_RFI_FRAGLEN
,
1744 sp
->rx_buf_sz
, PCI_DMA_FROMDEVICE
);
1749 static void ipg_tx_clear(struct ipg_nic_private
*sp
)
1753 for (i
= 0; i
< IPG_TFDLIST_LENGTH
; i
++) {
1754 if (sp
->TxBuff
[i
]) {
1755 struct ipg_tx
*txfd
= sp
->txd
+ i
;
1757 pci_unmap_single(sp
->pdev
,
1758 le64_to_cpu(txfd
->frag_info
) & ~IPG_TFI_FRAGLEN
,
1759 sp
->TxBuff
[i
]->len
, PCI_DMA_TODEVICE
);
1761 dev_kfree_skb_irq(sp
->TxBuff
[i
]);
1763 sp
->TxBuff
[i
] = NULL
;
1768 static int ipg_nic_open(struct net_device
*dev
)
1770 struct ipg_nic_private
*sp
= netdev_priv(dev
);
1771 void __iomem
*ioaddr
= sp
->ioaddr
;
1772 struct pci_dev
*pdev
= sp
->pdev
;
1775 IPG_DEBUG_MSG("_nic_open\n");
1777 sp
->rx_buf_sz
= IPG_RXSUPPORT_SIZE
;
1779 /* Check for interrupt line conflicts, and request interrupt
1782 * IMPORTANT: Disable IPG interrupts prior to registering
1785 ipg_w16(0x0000, INT_ENABLE
);
1787 /* Register the interrupt line to be used by the IPG within
1790 rc
= request_irq(pdev
->irq
, &ipg_interrupt_handler
, IRQF_SHARED
,
1793 printk(KERN_INFO
"%s: Error when requesting interrupt.\n",
1798 dev
->irq
= pdev
->irq
;
1802 sp
->rxd
= dma_alloc_coherent(&pdev
->dev
, IPG_RX_RING_BYTES
,
1803 &sp
->rxd_map
, GFP_KERNEL
);
1805 goto err_free_irq_0
;
1807 sp
->txd
= dma_alloc_coherent(&pdev
->dev
, IPG_TX_RING_BYTES
,
1808 &sp
->txd_map
, GFP_KERNEL
);
1812 rc
= init_rfdlist(dev
);
1814 printk(KERN_INFO
"%s: Error during configuration.\n",
1821 rc
= ipg_io_config(dev
);
1823 printk(KERN_INFO
"%s: Error during configuration.\n",
1825 goto err_release_tfdlist_3
;
1828 /* Resolve autonegotiation. */
1829 if (ipg_config_autoneg(dev
) < 0)
1830 printk(KERN_INFO
"%s: Auto-negotiation error.\n", dev
->name
);
1833 /* initialize JUMBO Frame control variable */
1834 sp
->Jumbo
.FoundStart
= 0;
1835 sp
->Jumbo
.CurrentSize
= 0;
1837 dev
->mtu
= IPG_TXFRAG_SIZE
;
1840 /* Enable transmit and receive operation of the IPG. */
1841 ipg_w32((ipg_r32(MAC_CTRL
) | IPG_MC_RX_ENABLE
| IPG_MC_TX_ENABLE
) &
1842 IPG_MC_RSVD_MASK
, MAC_CTRL
);
1844 netif_start_queue(dev
);
1848 err_release_tfdlist_3
:
1852 dma_free_coherent(&pdev
->dev
, IPG_TX_RING_BYTES
, sp
->txd
, sp
->txd_map
);
1854 dma_free_coherent(&pdev
->dev
, IPG_RX_RING_BYTES
, sp
->rxd
, sp
->rxd_map
);
1856 free_irq(pdev
->irq
, dev
);
1860 static int ipg_nic_stop(struct net_device
*dev
)
1862 struct ipg_nic_private
*sp
= netdev_priv(dev
);
1863 void __iomem
*ioaddr
= sp
->ioaddr
;
1864 struct pci_dev
*pdev
= sp
->pdev
;
1866 IPG_DEBUG_MSG("_nic_stop\n");
1868 netif_stop_queue(dev
);
1870 IPG_DDEBUG_MSG("RFDlistendCount = %i\n", sp
->RFDlistendCount
);
1871 IPG_DDEBUG_MSG("RFDListCheckedCount = %i\n", sp
->rxdCheckedCount
);
1872 IPG_DDEBUG_MSG("EmptyRFDListCount = %i\n", sp
->EmptyRFDListCount
);
1873 IPG_DUMPTFDLIST(dev
);
1876 (void) ipg_r16(INT_STATUS_ACK
);
1878 ipg_reset(dev
, IPG_AC_GLOBAL_RESET
| IPG_AC_HOST
| IPG_AC_DMA
);
1880 synchronize_irq(pdev
->irq
);
1881 } while (ipg_r16(INT_ENABLE
) & IPG_IE_RSVD_MASK
);
1887 pci_free_consistent(pdev
, IPG_RX_RING_BYTES
, sp
->rxd
, sp
->rxd_map
);
1888 pci_free_consistent(pdev
, IPG_TX_RING_BYTES
, sp
->txd
, sp
->txd_map
);
1890 free_irq(pdev
->irq
, dev
);
1895 static int ipg_nic_hard_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1897 struct ipg_nic_private
*sp
= netdev_priv(dev
);
1898 void __iomem
*ioaddr
= sp
->ioaddr
;
1899 unsigned int entry
= sp
->tx_current
% IPG_TFDLIST_LENGTH
;
1900 unsigned long flags
;
1901 struct ipg_tx
*txfd
;
1903 IPG_DDEBUG_MSG("_nic_hard_start_xmit\n");
1905 /* If in 10Mbps mode, stop the transmit queue so
1906 * no more transmit frames are accepted.
1908 if (sp
->tenmbpsmode
)
1909 netif_stop_queue(dev
);
1911 if (sp
->ResetCurrentTFD
) {
1912 sp
->ResetCurrentTFD
= 0;
1916 txfd
= sp
->txd
+ entry
;
1918 sp
->TxBuff
[entry
] = skb
;
1920 /* Clear all TFC fields, except TFDDONE. */
1921 txfd
->tfc
= cpu_to_le64(IPG_TFC_TFDDONE
);
1923 /* Specify the TFC field within the TFD. */
1924 txfd
->tfc
|= cpu_to_le64(IPG_TFC_WORDALIGNDISABLED
|
1925 (IPG_TFC_FRAMEID
& cpu_to_le64(sp
->tx_current
)) |
1926 (IPG_TFC_FRAGCOUNT
& (1 << 24)));
1928 /* Request TxComplete interrupts at an interval defined
1929 * by the constant IPG_FRAMESBETWEENTXCOMPLETES.
1930 * Request TxComplete interrupt for every frame
1931 * if in 10Mbps mode to accomodate problem with 10Mbps
1934 if (sp
->tenmbpsmode
)
1935 txfd
->tfc
|= cpu_to_le64(IPG_TFC_TXINDICATE
);
1936 txfd
->tfc
|= cpu_to_le64(IPG_TFC_TXDMAINDICATE
);
1937 /* Based on compilation option, determine if FCS is to be
1938 * appended to transmit frame by IPG.
1940 if (!(IPG_APPEND_FCS_ON_TX
))
1941 txfd
->tfc
|= cpu_to_le64(IPG_TFC_FCSAPPENDDISABLE
);
1943 /* Based on compilation option, determine if IP, TCP and/or
1944 * UDP checksums are to be added to transmit frame by IPG.
1946 if (IPG_ADD_IPCHECKSUM_ON_TX
)
1947 txfd
->tfc
|= cpu_to_le64(IPG_TFC_IPCHECKSUMENABLE
);
1949 if (IPG_ADD_TCPCHECKSUM_ON_TX
)
1950 txfd
->tfc
|= cpu_to_le64(IPG_TFC_TCPCHECKSUMENABLE
);
1952 if (IPG_ADD_UDPCHECKSUM_ON_TX
)
1953 txfd
->tfc
|= cpu_to_le64(IPG_TFC_UDPCHECKSUMENABLE
);
1955 /* Based on compilation option, determine if VLAN tag info is to be
1956 * inserted into transmit frame by IPG.
1958 if (IPG_INSERT_MANUAL_VLAN_TAG
) {
1959 txfd
->tfc
|= cpu_to_le64(IPG_TFC_VLANTAGINSERT
|
1960 ((u64
) IPG_MANUAL_VLAN_VID
<< 32) |
1961 ((u64
) IPG_MANUAL_VLAN_CFI
<< 44) |
1962 ((u64
) IPG_MANUAL_VLAN_USERPRIORITY
<< 45));
1965 /* The fragment start location within system memory is defined
1966 * by the sk_buff structure's data field. The physical address
1967 * of this location within the system's virtual memory space
1968 * is determined using the IPG_HOST2BUS_MAP function.
1970 txfd
->frag_info
= cpu_to_le64(pci_map_single(sp
->pdev
, skb
->data
,
1971 skb
->len
, PCI_DMA_TODEVICE
));
1973 /* The length of the fragment within system memory is defined by
1974 * the sk_buff structure's len field.
1976 txfd
->frag_info
|= cpu_to_le64(IPG_TFI_FRAGLEN
&
1977 ((u64
) (skb
->len
& 0xffff) << 48));
1979 /* Clear the TFDDone bit last to indicate the TFD is ready
1980 * for transfer to the IPG.
1982 txfd
->tfc
&= cpu_to_le64(~IPG_TFC_TFDDONE
);
1984 spin_lock_irqsave(&sp
->lock
, flags
);
1990 ipg_w32(IPG_DC_TX_DMA_POLL_NOW
, DMA_CTRL
);
1992 if (sp
->tx_current
== (sp
->tx_dirty
+ IPG_TFDLIST_LENGTH
))
1993 netif_stop_queue(dev
);
1995 spin_unlock_irqrestore(&sp
->lock
, flags
);
1997 return NETDEV_TX_OK
;
2000 static void ipg_set_phy_default_param(unsigned char rev
,
2001 struct net_device
*dev
, int phy_address
)
2003 unsigned short length
;
2004 unsigned char revision
;
2005 unsigned short *phy_param
;
2006 unsigned short address
, value
;
2008 phy_param
= &DefaultPhyParam
[0];
2009 length
= *phy_param
& 0x00FF;
2010 revision
= (unsigned char)((*phy_param
) >> 8);
2012 while (length
!= 0) {
2013 if (rev
== revision
) {
2014 while (length
> 1) {
2015 address
= *phy_param
;
2016 value
= *(phy_param
+ 1);
2018 mdio_write(dev
, phy_address
, address
, value
);
2023 phy_param
+= length
/ 2;
2024 length
= *phy_param
& 0x00FF;
2025 revision
= (unsigned char)((*phy_param
) >> 8);
2031 /* JES20040127EEPROM */
2032 static int read_eeprom(struct net_device
*dev
, int eep_addr
)
2034 void __iomem
*ioaddr
= ipg_ioaddr(dev
);
2039 value
= IPG_EC_EEPROM_READOPCODE
| (eep_addr
& 0xff);
2040 ipg_w16(value
, EEPROM_CTRL
);
2042 for (i
= 0; i
< 1000; i
++) {
2046 data
= ipg_r16(EEPROM_CTRL
);
2047 if (!(data
& IPG_EC_EEPROM_BUSY
)) {
2048 ret
= ipg_r16(EEPROM_DATA
);
2055 static void ipg_init_mii(struct net_device
*dev
)
2057 struct ipg_nic_private
*sp
= netdev_priv(dev
);
2058 struct mii_if_info
*mii_if
= &sp
->mii_if
;
2062 mii_if
->mdio_read
= mdio_read
;
2063 mii_if
->mdio_write
= mdio_write
;
2064 mii_if
->phy_id_mask
= 0x1f;
2065 mii_if
->reg_num_mask
= 0x1f;
2067 mii_if
->phy_id
= phyaddr
= ipg_find_phyaddr(dev
);
2069 if (phyaddr
!= 0x1f) {
2070 u16 mii_phyctrl
, mii_1000cr
;
2073 mii_1000cr
= mdio_read(dev
, phyaddr
, MII_CTRL1000
);
2074 mii_1000cr
|= ADVERTISE_1000FULL
| ADVERTISE_1000HALF
|
2075 GMII_PHY_1000BASETCONTROL_PreferMaster
;
2076 mdio_write(dev
, phyaddr
, MII_CTRL1000
, mii_1000cr
);
2078 mii_phyctrl
= mdio_read(dev
, phyaddr
, MII_BMCR
);
2080 /* Set default phyparam */
2081 pci_read_config_byte(sp
->pdev
, PCI_REVISION_ID
, &revisionid
);
2082 ipg_set_phy_default_param(revisionid
, dev
, phyaddr
);
2085 mii_phyctrl
|= BMCR_RESET
| BMCR_ANRESTART
;
2086 mdio_write(dev
, phyaddr
, MII_BMCR
, mii_phyctrl
);
2091 static int ipg_hw_init(struct net_device
*dev
)
2093 struct ipg_nic_private
*sp
= netdev_priv(dev
);
2094 void __iomem
*ioaddr
= sp
->ioaddr
;
2098 /* Read/Write and Reset EEPROM Value Jesse20040128EEPROM_VALUE */
2099 /* Read LED Mode Configuration from EEPROM */
2100 sp
->LED_Mode
= read_eeprom(dev
, 6);
2102 /* Reset all functions within the IPG. Do not assert
2103 * RST_OUT as not compatible with some PHYs.
2105 rc
= ipg_reset(dev
, IPG_RESET_MASK
);
2111 /* Read MAC Address from EEPROM */
2112 for (i
= 0; i
< 3; i
++)
2113 sp
->station_addr
[i
] = read_eeprom(dev
, 16 + i
);
2115 for (i
= 0; i
< 3; i
++)
2116 ipg_w16(sp
->station_addr
[i
], STATION_ADDRESS_0
+ 2*i
);
2118 /* Set station address in ethernet_device structure. */
2119 dev
->dev_addr
[0] = ipg_r16(STATION_ADDRESS_0
) & 0x00ff;
2120 dev
->dev_addr
[1] = (ipg_r16(STATION_ADDRESS_0
) & 0xff00) >> 8;
2121 dev
->dev_addr
[2] = ipg_r16(STATION_ADDRESS_1
) & 0x00ff;
2122 dev
->dev_addr
[3] = (ipg_r16(STATION_ADDRESS_1
) & 0xff00) >> 8;
2123 dev
->dev_addr
[4] = ipg_r16(STATION_ADDRESS_2
) & 0x00ff;
2124 dev
->dev_addr
[5] = (ipg_r16(STATION_ADDRESS_2
) & 0xff00) >> 8;
2129 static int ipg_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2131 struct ipg_nic_private
*sp
= netdev_priv(dev
);
2134 mutex_lock(&sp
->mii_mutex
);
2135 rc
= generic_mii_ioctl(&sp
->mii_if
, if_mii(ifr
), cmd
, NULL
);
2136 mutex_unlock(&sp
->mii_mutex
);
2141 static int ipg_nic_change_mtu(struct net_device
*dev
, int new_mtu
)
2143 /* Function to accomodate changes to Maximum Transfer Unit
2144 * (or MTU) of IPG NIC. Cannot use default function since
2145 * the default will not allow for MTU > 1500 bytes.
2148 IPG_DEBUG_MSG("_nic_change_mtu\n");
2150 /* Check that the new MTU value is between 68 (14 byte header, 46
2151 * byte payload, 4 byte FCS) and IPG_MAX_RXFRAME_SIZE, which
2152 * corresponds to the MAXFRAMESIZE register in the IPG.
2154 if ((new_mtu
< 68) || (new_mtu
> IPG_MAX_RXFRAME_SIZE
))
2162 static int ipg_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
2164 struct ipg_nic_private
*sp
= netdev_priv(dev
);
2167 mutex_lock(&sp
->mii_mutex
);
2168 rc
= mii_ethtool_gset(&sp
->mii_if
, cmd
);
2169 mutex_unlock(&sp
->mii_mutex
);
2174 static int ipg_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
2176 struct ipg_nic_private
*sp
= netdev_priv(dev
);
2179 mutex_lock(&sp
->mii_mutex
);
2180 rc
= mii_ethtool_sset(&sp
->mii_if
, cmd
);
2181 mutex_unlock(&sp
->mii_mutex
);
2186 static int ipg_nway_reset(struct net_device
*dev
)
2188 struct ipg_nic_private
*sp
= netdev_priv(dev
);
2191 mutex_lock(&sp
->mii_mutex
);
2192 rc
= mii_nway_restart(&sp
->mii_if
);
2193 mutex_unlock(&sp
->mii_mutex
);
2198 static struct ethtool_ops ipg_ethtool_ops
= {
2199 .get_settings
= ipg_get_settings
,
2200 .set_settings
= ipg_set_settings
,
2201 .nway_reset
= ipg_nway_reset
,
2204 static void ipg_remove(struct pci_dev
*pdev
)
2206 struct net_device
*dev
= pci_get_drvdata(pdev
);
2207 struct ipg_nic_private
*sp
= netdev_priv(dev
);
2209 IPG_DEBUG_MSG("_remove\n");
2211 /* Un-register Ethernet device. */
2212 unregister_netdev(dev
);
2214 pci_iounmap(pdev
, sp
->ioaddr
);
2216 pci_release_regions(pdev
);
2219 pci_disable_device(pdev
);
2220 pci_set_drvdata(pdev
, NULL
);
2223 static int __devinit
ipg_probe(struct pci_dev
*pdev
,
2224 const struct pci_device_id
*id
)
2226 unsigned int i
= id
->driver_data
;
2227 struct ipg_nic_private
*sp
;
2228 struct net_device
*dev
;
2229 void __iomem
*ioaddr
;
2232 rc
= pci_enable_device(pdev
);
2236 printk(KERN_INFO
"%s: %s\n", pci_name(pdev
), ipg_brand_name
[i
]);
2238 pci_set_master(pdev
);
2240 rc
= pci_set_dma_mask(pdev
, DMA_40BIT_MASK
);
2242 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
2244 printk(KERN_ERR
"%s: DMA config failed.\n",
2251 * Initialize net device.
2253 dev
= alloc_etherdev(sizeof(struct ipg_nic_private
));
2255 printk(KERN_ERR
"%s: alloc_etherdev failed\n", pci_name(pdev
));
2260 sp
= netdev_priv(dev
);
2261 spin_lock_init(&sp
->lock
);
2262 mutex_init(&sp
->mii_mutex
);
2264 /* Declare IPG NIC functions for Ethernet device methods.
2266 dev
->open
= &ipg_nic_open
;
2267 dev
->stop
= &ipg_nic_stop
;
2268 dev
->hard_start_xmit
= &ipg_nic_hard_start_xmit
;
2269 dev
->get_stats
= &ipg_nic_get_stats
;
2270 dev
->set_multicast_list
= &ipg_nic_set_multicast_list
;
2271 dev
->do_ioctl
= ipg_ioctl
;
2272 dev
->tx_timeout
= ipg_tx_timeout
;
2273 dev
->change_mtu
= &ipg_nic_change_mtu
;
2275 SET_NETDEV_DEV(dev
, &pdev
->dev
);
2276 SET_ETHTOOL_OPS(dev
, &ipg_ethtool_ops
);
2278 rc
= pci_request_regions(pdev
, DRV_NAME
);
2280 goto err_free_dev_1
;
2282 ioaddr
= pci_iomap(pdev
, 1, pci_resource_len(pdev
, 1));
2284 printk(KERN_ERR
"%s cannot map MMIO\n", pci_name(pdev
));
2286 goto err_release_regions_2
;
2289 /* Save the pointer to the PCI device information. */
2290 sp
->ioaddr
= ioaddr
;
2294 INIT_DELAYED_WORK(&sp
->task
, ipg_reset_after_host_error
);
2296 pci_set_drvdata(pdev
, dev
);
2298 rc
= ipg_hw_init(dev
);
2302 rc
= register_netdev(dev
);
2306 printk(KERN_INFO
"Ethernet device registered as: %s\n", dev
->name
);
2311 pci_iounmap(pdev
, ioaddr
);
2312 err_release_regions_2
:
2313 pci_release_regions(pdev
);
2317 pci_disable_device(pdev
);
2321 static struct pci_driver ipg_pci_driver
= {
2322 .name
= IPG_DRIVER_NAME
,
2323 .id_table
= ipg_pci_tbl
,
2325 .remove
= __devexit_p(ipg_remove
),
2328 static int __init
ipg_init_module(void)
2330 return pci_register_driver(&ipg_pci_driver
);
2333 static void __exit
ipg_exit_module(void)
2335 pci_unregister_driver(&ipg_pci_driver
);
2338 module_init(ipg_init_module
);
2339 module_exit(ipg_exit_module
);