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ipg: remove driver version
[deliverable/linux.git] / drivers / net / ipg.h
1 /*
2 * Include file for Gigabit Ethernet device driver for Network
3 * Interface Cards (NICs) utilizing the Tamarack Microelectronics
4 * Inc. IPG Gigabit or Triple Speed Ethernet Media Access
5 * Controller.
6 */
7 #ifndef __LINUX_IPG_H
8 #define __LINUX_IPG_H
9
10 #include <linux/version.h>
11 #include <linux/module.h>
12
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/ioport.h>
16 #include <linux/errno.h>
17 #include <asm/io.h>
18 #include <linux/delay.h>
19 #include <linux/types.h>
20 #include <linux/netdevice.h>
21 #include <linux/etherdevice.h>
22 #include <linux/init.h>
23 #include <linux/skbuff.h>
24 #include <linux/version.h>
25 #include <asm/bitops.h>
26 /*#include <asm/spinlock.h>*/
27
28 /*
29 * Constants
30 */
31
32 /* GMII based PHY IDs */
33 #define NS 0x2000
34 #define MARVELL 0x0141
35 #define ICPLUS_PHY 0x243
36
37 /* NIC Physical Layer Device MII register fields. */
38 #define MII_PHY_SELECTOR_IEEE8023 0x0001
39 #define MII_PHY_TECHABILITYFIELD 0x1FE0
40
41 /* GMII_PHY_1000 need to set to prefer master */
42 #define GMII_PHY_1000BASETCONTROL_PreferMaster 0x0400
43
44 /* NIC Physical Layer Device GMII constants. */
45 #define GMII_PREAMBLE 0xFFFFFFFF
46 #define GMII_ST 0x1
47 #define GMII_READ 0x2
48 #define GMII_WRITE 0x1
49 #define GMII_TA_READ_MASK 0x1
50 #define GMII_TA_WRITE 0x2
51
52 /* I/O register offsets. */
53 enum ipg_regs {
54 DMA_CTRL = 0x00,
55 RX_DMA_STATUS = 0x08, // Unused + reserved
56 TFD_LIST_PTR_0 = 0x10,
57 TFD_LIST_PTR_1 = 0x14,
58 TX_DMA_BURST_THRESH = 0x18,
59 TX_DMA_URGENT_THRESH = 0x19,
60 TX_DMA_POLL_PERIOD = 0x1a,
61 RFD_LIST_PTR_0 = 0x1c,
62 RFD_LIST_PTR_1 = 0x20,
63 RX_DMA_BURST_THRESH = 0x24,
64 RX_DMA_URGENT_THRESH = 0x25,
65 RX_DMA_POLL_PERIOD = 0x26,
66 DEBUG_CTRL = 0x2c,
67 ASIC_CTRL = 0x30,
68 FIFO_CTRL = 0x38, // Unused
69 FLOW_OFF_THRESH = 0x3c,
70 FLOW_ON_THRESH = 0x3e,
71 EEPROM_DATA = 0x48,
72 EEPROM_CTRL = 0x4a,
73 EXPROM_ADDR = 0x4c, // Unused
74 EXPROM_DATA = 0x50, // Unused
75 WAKE_EVENT = 0x51, // Unused
76 COUNTDOWN = 0x54, // Unused
77 INT_STATUS_ACK = 0x5a,
78 INT_ENABLE = 0x5c,
79 INT_STATUS = 0x5e, // Unused
80 TX_STATUS = 0x60,
81 MAC_CTRL = 0x6c,
82 VLAN_TAG = 0x70, // Unused
83 PHY_SET = 0x75, // JES20040127EEPROM
84 PHY_CTRL = 0x76,
85 STATION_ADDRESS_0 = 0x78,
86 STATION_ADDRESS_1 = 0x7a,
87 STATION_ADDRESS_2 = 0x7c,
88 MAX_FRAME_SIZE = 0x86,
89 RECEIVE_MODE = 0x88,
90 HASHTABLE_0 = 0x8c,
91 HASHTABLE_1 = 0x90,
92 RMON_STATISTICS_MASK = 0x98,
93 STATISTICS_MASK = 0x9c,
94 RX_JUMBO_FRAMES = 0xbc, // Unused
95 TCP_CHECKSUM_ERRORS = 0xc0, // Unused
96 IP_CHECKSUM_ERRORS = 0xc2, // Unused
97 UDP_CHECKSUM_ERRORS = 0xc4, // Unused
98 TX_JUMBO_FRAMES = 0xf4 // Unused
99 };
100
101 /* Ethernet MIB statistic register offsets. */
102 #define IPG_OCTETRCVOK 0xA8
103 #define IPG_MCSTOCTETRCVDOK 0xAC
104 #define IPG_BCSTOCTETRCVOK 0xB0
105 #define IPG_FRAMESRCVDOK 0xB4
106 #define IPG_MCSTFRAMESRCVDOK 0xB8
107 #define IPG_BCSTFRAMESRCVDOK 0xBE
108 #define IPG_MACCONTROLFRAMESRCVD 0xC6
109 #define IPG_FRAMETOOLONGERRRORS 0xC8
110 #define IPG_INRANGELENGTHERRORS 0xCA
111 #define IPG_FRAMECHECKSEQERRORS 0xCC
112 #define IPG_FRAMESLOSTRXERRORS 0xCE
113 #define IPG_OCTETXMTOK 0xD0
114 #define IPG_MCSTOCTETXMTOK 0xD4
115 #define IPG_BCSTOCTETXMTOK 0xD8
116 #define IPG_FRAMESXMTDOK 0xDC
117 #define IPG_MCSTFRAMESXMTDOK 0xE0
118 #define IPG_FRAMESWDEFERREDXMT 0xE4
119 #define IPG_LATECOLLISIONS 0xE8
120 #define IPG_MULTICOLFRAMES 0xEC
121 #define IPG_SINGLECOLFRAMES 0xF0
122 #define IPG_BCSTFRAMESXMTDOK 0xF6
123 #define IPG_CARRIERSENSEERRORS 0xF8
124 #define IPG_MACCONTROLFRAMESXMTDOK 0xFA
125 #define IPG_FRAMESABORTXSCOLLS 0xFC
126 #define IPG_FRAMESWEXDEFERRAL 0xFE
127
128 /* RMON statistic register offsets. */
129 #define IPG_ETHERSTATSCOLLISIONS 0x100
130 #define IPG_ETHERSTATSOCTETSTRANSMIT 0x104
131 #define IPG_ETHERSTATSPKTSTRANSMIT 0x108
132 #define IPG_ETHERSTATSPKTS64OCTESTSTRANSMIT 0x10C
133 #define IPG_ETHERSTATSPKTS65TO127OCTESTSTRANSMIT 0x110
134 #define IPG_ETHERSTATSPKTS128TO255OCTESTSTRANSMIT 0x114
135 #define IPG_ETHERSTATSPKTS256TO511OCTESTSTRANSMIT 0x118
136 #define IPG_ETHERSTATSPKTS512TO1023OCTESTSTRANSMIT 0x11C
137 #define IPG_ETHERSTATSPKTS1024TO1518OCTESTSTRANSMIT 0x120
138 #define IPG_ETHERSTATSCRCALIGNERRORS 0x124
139 #define IPG_ETHERSTATSUNDERSIZEPKTS 0x128
140 #define IPG_ETHERSTATSFRAGMENTS 0x12C
141 #define IPG_ETHERSTATSJABBERS 0x130
142 #define IPG_ETHERSTATSOCTETS 0x134
143 #define IPG_ETHERSTATSPKTS 0x138
144 #define IPG_ETHERSTATSPKTS64OCTESTS 0x13C
145 #define IPG_ETHERSTATSPKTS65TO127OCTESTS 0x140
146 #define IPG_ETHERSTATSPKTS128TO255OCTESTS 0x144
147 #define IPG_ETHERSTATSPKTS256TO511OCTESTS 0x148
148 #define IPG_ETHERSTATSPKTS512TO1023OCTESTS 0x14C
149 #define IPG_ETHERSTATSPKTS1024TO1518OCTESTS 0x150
150
151 /* RMON statistic register equivalents. */
152 #define IPG_ETHERSTATSMULTICASTPKTSTRANSMIT 0xE0
153 #define IPG_ETHERSTATSBROADCASTPKTSTRANSMIT 0xF6
154 #define IPG_ETHERSTATSMULTICASTPKTS 0xB8
155 #define IPG_ETHERSTATSBROADCASTPKTS 0xBE
156 #define IPG_ETHERSTATSOVERSIZEPKTS 0xC8
157 #define IPG_ETHERSTATSDROPEVENTS 0xCE
158
159 /* Serial EEPROM offsets */
160 #define IPG_EEPROM_CONFIGPARAM 0x00
161 #define IPG_EEPROM_ASICCTRL 0x01
162 #define IPG_EEPROM_SUBSYSTEMVENDORID 0x02
163 #define IPG_EEPROM_SUBSYSTEMID 0x03
164 #define IPG_EEPROM_STATIONADDRESS0 0x10
165 #define IPG_EEPROM_STATIONADDRESS1 0x11
166 #define IPG_EEPROM_STATIONADDRESS2 0x12
167
168 /* Register & data structure bit masks */
169
170 /* PCI register masks. */
171
172 /* IOBaseAddress */
173 #define IPG_PIB_RSVD_MASK 0xFFFFFE01
174 #define IPG_PIB_IOBASEADDRESS 0xFFFFFF00
175 #define IPG_PIB_IOBASEADDRIND 0x00000001
176
177 /* MemBaseAddress */
178 #define IPG_PMB_RSVD_MASK 0xFFFFFE07
179 #define IPG_PMB_MEMBASEADDRIND 0x00000001
180 #define IPG_PMB_MEMMAPTYPE 0x00000006
181 #define IPG_PMB_MEMMAPTYPE0 0x00000002
182 #define IPG_PMB_MEMMAPTYPE1 0x00000004
183 #define IPG_PMB_MEMBASEADDRESS 0xFFFFFE00
184
185 /* ConfigStatus */
186 #define IPG_CS_RSVD_MASK 0xFFB0
187 #define IPG_CS_CAPABILITIES 0x0010
188 #define IPG_CS_66MHZCAPABLE 0x0020
189 #define IPG_CS_FASTBACK2BACK 0x0080
190 #define IPG_CS_DATAPARITYREPORTED 0x0100
191 #define IPG_CS_DEVSELTIMING 0x0600
192 #define IPG_CS_SIGNALEDTARGETABORT 0x0800
193 #define IPG_CS_RECEIVEDTARGETABORT 0x1000
194 #define IPG_CS_RECEIVEDMASTERABORT 0x2000
195 #define IPG_CS_SIGNALEDSYSTEMERROR 0x4000
196 #define IPG_CS_DETECTEDPARITYERROR 0x8000
197
198 /* TFD data structure masks. */
199
200 /* TFDList, TFC */
201 #define IPG_TFC_RSVD_MASK 0x0000FFFF9FFFFFFF
202 #define IPG_TFC_FRAMEID 0x000000000000FFFF
203 #define IPG_TFC_WORDALIGN 0x0000000000030000
204 #define IPG_TFC_WORDALIGNTODWORD 0x0000000000000000
205 #define IPG_TFC_WORDALIGNTOWORD 0x0000000000020000
206 #define IPG_TFC_WORDALIGNDISABLED 0x0000000000030000
207 #define IPG_TFC_TCPCHECKSUMENABLE 0x0000000000040000
208 #define IPG_TFC_UDPCHECKSUMENABLE 0x0000000000080000
209 #define IPG_TFC_IPCHECKSUMENABLE 0x0000000000100000
210 #define IPG_TFC_FCSAPPENDDISABLE 0x0000000000200000
211 #define IPG_TFC_TXINDICATE 0x0000000000400000
212 #define IPG_TFC_TXDMAINDICATE 0x0000000000800000
213 #define IPG_TFC_FRAGCOUNT 0x000000000F000000
214 #define IPG_TFC_VLANTAGINSERT 0x0000000010000000
215 #define IPG_TFC_TFDDONE 0x0000000080000000
216 #define IPG_TFC_VID 0x00000FFF00000000
217 #define IPG_TFC_CFI 0x0000100000000000
218 #define IPG_TFC_USERPRIORITY 0x0000E00000000000
219
220 /* TFDList, FragInfo */
221 #define IPG_TFI_RSVD_MASK 0xFFFF00FFFFFFFFFF
222 #define IPG_TFI_FRAGADDR 0x000000FFFFFFFFFF
223 #define IPG_TFI_FRAGLEN 0xFFFF000000000000LL
224
225 /* RFD data structure masks. */
226
227 /* RFDList, RFS */
228 #define IPG_RFS_RSVD_MASK 0x0000FFFFFFFFFFFF
229 #define IPG_RFS_RXFRAMELEN 0x000000000000FFFF
230 #define IPG_RFS_RXFIFOOVERRUN 0x0000000000010000
231 #define IPG_RFS_RXRUNTFRAME 0x0000000000020000
232 #define IPG_RFS_RXALIGNMENTERROR 0x0000000000040000
233 #define IPG_RFS_RXFCSERROR 0x0000000000080000
234 #define IPG_RFS_RXOVERSIZEDFRAME 0x0000000000100000
235 #define IPG_RFS_RXLENGTHERROR 0x0000000000200000
236 #define IPG_RFS_VLANDETECTED 0x0000000000400000
237 #define IPG_RFS_TCPDETECTED 0x0000000000800000
238 #define IPG_RFS_TCPERROR 0x0000000001000000
239 #define IPG_RFS_UDPDETECTED 0x0000000002000000
240 #define IPG_RFS_UDPERROR 0x0000000004000000
241 #define IPG_RFS_IPDETECTED 0x0000000008000000
242 #define IPG_RFS_IPERROR 0x0000000010000000
243 #define IPG_RFS_FRAMESTART 0x0000000020000000
244 #define IPG_RFS_FRAMEEND 0x0000000040000000
245 #define IPG_RFS_RFDDONE 0x0000000080000000
246 #define IPG_RFS_TCI 0x0000FFFF00000000
247
248 /* RFDList, FragInfo */
249 #define IPG_RFI_RSVD_MASK 0xFFFF00FFFFFFFFFF
250 #define IPG_RFI_FRAGADDR 0x000000FFFFFFFFFF
251 #define IPG_RFI_FRAGLEN 0xFFFF000000000000LL
252
253 /* I/O Register masks. */
254
255 /* RMON Statistics Mask */
256 #define IPG_RZ_ALL 0x0FFFFFFF
257
258 /* Statistics Mask */
259 #define IPG_SM_ALL 0x0FFFFFFF
260 #define IPG_SM_OCTETRCVOK_FRAMESRCVDOK 0x00000001
261 #define IPG_SM_MCSTOCTETRCVDOK_MCSTFRAMESRCVDOK 0x00000002
262 #define IPG_SM_BCSTOCTETRCVDOK_BCSTFRAMESRCVDOK 0x00000004
263 #define IPG_SM_RXJUMBOFRAMES 0x00000008
264 #define IPG_SM_TCPCHECKSUMERRORS 0x00000010
265 #define IPG_SM_IPCHECKSUMERRORS 0x00000020
266 #define IPG_SM_UDPCHECKSUMERRORS 0x00000040
267 #define IPG_SM_MACCONTROLFRAMESRCVD 0x00000080
268 #define IPG_SM_FRAMESTOOLONGERRORS 0x00000100
269 #define IPG_SM_INRANGELENGTHERRORS 0x00000200
270 #define IPG_SM_FRAMECHECKSEQERRORS 0x00000400
271 #define IPG_SM_FRAMESLOSTRXERRORS 0x00000800
272 #define IPG_SM_OCTETXMTOK_FRAMESXMTOK 0x00001000
273 #define IPG_SM_MCSTOCTETXMTOK_MCSTFRAMESXMTDOK 0x00002000
274 #define IPG_SM_BCSTOCTETXMTOK_BCSTFRAMESXMTDOK 0x00004000
275 #define IPG_SM_FRAMESWDEFERREDXMT 0x00008000
276 #define IPG_SM_LATECOLLISIONS 0x00010000
277 #define IPG_SM_MULTICOLFRAMES 0x00020000
278 #define IPG_SM_SINGLECOLFRAMES 0x00040000
279 #define IPG_SM_TXJUMBOFRAMES 0x00080000
280 #define IPG_SM_CARRIERSENSEERRORS 0x00100000
281 #define IPG_SM_MACCONTROLFRAMESXMTD 0x00200000
282 #define IPG_SM_FRAMESABORTXSCOLLS 0x00400000
283 #define IPG_SM_FRAMESWEXDEFERAL 0x00800000
284
285 /* Countdown */
286 #define IPG_CD_RSVD_MASK 0x0700FFFF
287 #define IPG_CD_COUNT 0x0000FFFF
288 #define IPG_CD_COUNTDOWNSPEED 0x01000000
289 #define IPG_CD_COUNTDOWNMODE 0x02000000
290 #define IPG_CD_COUNTINTENABLED 0x04000000
291
292 /* TxDMABurstThresh */
293 #define IPG_TB_RSVD_MASK 0xFF
294
295 /* TxDMAUrgentThresh */
296 #define IPG_TU_RSVD_MASK 0xFF
297
298 /* TxDMAPollPeriod */
299 #define IPG_TP_RSVD_MASK 0xFF
300
301 /* RxDMAUrgentThresh */
302 #define IPG_RU_RSVD_MASK 0xFF
303
304 /* RxDMAPollPeriod */
305 #define IPG_RP_RSVD_MASK 0xFF
306
307 /* ReceiveMode */
308 #define IPG_RM_RSVD_MASK 0x3F
309 #define IPG_RM_RECEIVEUNICAST 0x01
310 #define IPG_RM_RECEIVEMULTICAST 0x02
311 #define IPG_RM_RECEIVEBROADCAST 0x04
312 #define IPG_RM_RECEIVEALLFRAMES 0x08
313 #define IPG_RM_RECEIVEMULTICASTHASH 0x10
314 #define IPG_RM_RECEIVEIPMULTICAST 0x20
315
316 /* PhySet JES20040127EEPROM*/
317 #define IPG_PS_MEM_LENB9B 0x01
318 #define IPG_PS_MEM_LEN9 0x02
319 #define IPG_PS_NON_COMPDET 0x04
320
321 /* PhyCtrl */
322 #define IPG_PC_RSVD_MASK 0xFF
323 #define IPG_PC_MGMTCLK_LO 0x00
324 #define IPG_PC_MGMTCLK_HI 0x01
325 #define IPG_PC_MGMTCLK 0x01
326 #define IPG_PC_MGMTDATA 0x02
327 #define IPG_PC_MGMTDIR 0x04
328 #define IPG_PC_DUPLEX_POLARITY 0x08
329 #define IPG_PC_DUPLEX_STATUS 0x10
330 #define IPG_PC_LINK_POLARITY 0x20
331 #define IPG_PC_LINK_SPEED 0xC0
332 #define IPG_PC_LINK_SPEED_10MBPS 0x40
333 #define IPG_PC_LINK_SPEED_100MBPS 0x80
334 #define IPG_PC_LINK_SPEED_1000MBPS 0xC0
335
336 /* DMACtrl */
337 #define IPG_DC_RSVD_MASK 0xC07D9818
338 #define IPG_DC_RX_DMA_COMPLETE 0x00000008
339 #define IPG_DC_RX_DMA_POLL_NOW 0x00000010
340 #define IPG_DC_TX_DMA_COMPLETE 0x00000800
341 #define IPG_DC_TX_DMA_POLL_NOW 0x00001000
342 #define IPG_DC_TX_DMA_IN_PROG 0x00008000
343 #define IPG_DC_RX_EARLY_DISABLE 0x00010000
344 #define IPG_DC_MWI_DISABLE 0x00040000
345 #define IPG_DC_TX_WRITE_BACK_DISABLE 0x00080000
346 #define IPG_DC_TX_BURST_LIMIT 0x00700000
347 #define IPG_DC_TARGET_ABORT 0x40000000
348 #define IPG_DC_MASTER_ABORT 0x80000000
349
350 /* ASICCtrl */
351 #define IPG_AC_RSVD_MASK 0x07FFEFF2
352 #define IPG_AC_EXP_ROM_SIZE 0x00000002
353 #define IPG_AC_PHY_SPEED10 0x00000010
354 #define IPG_AC_PHY_SPEED100 0x00000020
355 #define IPG_AC_PHY_SPEED1000 0x00000040
356 #define IPG_AC_PHY_MEDIA 0x00000080
357 #define IPG_AC_FORCED_CFG 0x00000700
358 #define IPG_AC_D3RESETDISABLE 0x00000800
359 #define IPG_AC_SPEED_UP_MODE 0x00002000
360 #define IPG_AC_LED_MODE 0x00004000
361 #define IPG_AC_RST_OUT_POLARITY 0x00008000
362 #define IPG_AC_GLOBAL_RESET 0x00010000
363 #define IPG_AC_RX_RESET 0x00020000
364 #define IPG_AC_TX_RESET 0x00040000
365 #define IPG_AC_DMA 0x00080000
366 #define IPG_AC_FIFO 0x00100000
367 #define IPG_AC_NETWORK 0x00200000
368 #define IPG_AC_HOST 0x00400000
369 #define IPG_AC_AUTO_INIT 0x00800000
370 #define IPG_AC_RST_OUT 0x01000000
371 #define IPG_AC_INT_REQUEST 0x02000000
372 #define IPG_AC_RESET_BUSY 0x04000000
373 #define IPG_AC_LED_SPEED 0x08000000 //JES20040127EEPROM
374 #define IPG_AC_LED_MODE_BIT_1 0x20000000 //JES20040127EEPROM
375
376 /* EepromCtrl */
377 #define IPG_EC_RSVD_MASK 0x83FF
378 #define IPG_EC_EEPROM_ADDR 0x00FF
379 #define IPG_EC_EEPROM_OPCODE 0x0300
380 #define IPG_EC_EEPROM_SUBCOMMAD 0x0000
381 #define IPG_EC_EEPROM_WRITEOPCODE 0x0100
382 #define IPG_EC_EEPROM_READOPCODE 0x0200
383 #define IPG_EC_EEPROM_ERASEOPCODE 0x0300
384 #define IPG_EC_EEPROM_BUSY 0x8000
385
386 /* FIFOCtrl */
387 #define IPG_FC_RSVD_MASK 0xC001
388 #define IPG_FC_RAM_TEST_MODE 0x0001
389 #define IPG_FC_TRANSMITTING 0x4000
390 #define IPG_FC_RECEIVING 0x8000
391
392 /* TxStatus */
393 #define IPG_TS_RSVD_MASK 0xFFFF00DD
394 #define IPG_TS_TX_ERROR 0x00000001
395 #define IPG_TS_LATE_COLLISION 0x00000004
396 #define IPG_TS_TX_MAX_COLL 0x00000008
397 #define IPG_TS_TX_UNDERRUN 0x00000010
398 #define IPG_TS_TX_IND_REQD 0x00000040
399 #define IPG_TS_TX_COMPLETE 0x00000080
400 #define IPG_TS_TX_FRAMEID 0xFFFF0000
401
402 /* WakeEvent */
403 #define IPG_WE_WAKE_PKT_ENABLE 0x01
404 #define IPG_WE_MAGIC_PKT_ENABLE 0x02
405 #define IPG_WE_LINK_EVT_ENABLE 0x04
406 #define IPG_WE_WAKE_POLARITY 0x08
407 #define IPG_WE_WAKE_PKT_EVT 0x10
408 #define IPG_WE_MAGIC_PKT_EVT 0x20
409 #define IPG_WE_LINK_EVT 0x40
410 #define IPG_WE_WOL_ENABLE 0x80
411
412 /* IntEnable */
413 #define IPG_IE_RSVD_MASK 0x1FFE
414 #define IPG_IE_HOST_ERROR 0x0002
415 #define IPG_IE_TX_COMPLETE 0x0004
416 #define IPG_IE_MAC_CTRL_FRAME 0x0008
417 #define IPG_IE_RX_COMPLETE 0x0010
418 #define IPG_IE_RX_EARLY 0x0020
419 #define IPG_IE_INT_REQUESTED 0x0040
420 #define IPG_IE_UPDATE_STATS 0x0080
421 #define IPG_IE_LINK_EVENT 0x0100
422 #define IPG_IE_TX_DMA_COMPLETE 0x0200
423 #define IPG_IE_RX_DMA_COMPLETE 0x0400
424 #define IPG_IE_RFD_LIST_END 0x0800
425 #define IPG_IE_RX_DMA_PRIORITY 0x1000
426
427 /* IntStatus */
428 #define IPG_IS_RSVD_MASK 0x1FFF
429 #define IPG_IS_INTERRUPT_STATUS 0x0001
430 #define IPG_IS_HOST_ERROR 0x0002
431 #define IPG_IS_TX_COMPLETE 0x0004
432 #define IPG_IS_MAC_CTRL_FRAME 0x0008
433 #define IPG_IS_RX_COMPLETE 0x0010
434 #define IPG_IS_RX_EARLY 0x0020
435 #define IPG_IS_INT_REQUESTED 0x0040
436 #define IPG_IS_UPDATE_STATS 0x0080
437 #define IPG_IS_LINK_EVENT 0x0100
438 #define IPG_IS_TX_DMA_COMPLETE 0x0200
439 #define IPG_IS_RX_DMA_COMPLETE 0x0400
440 #define IPG_IS_RFD_LIST_END 0x0800
441 #define IPG_IS_RX_DMA_PRIORITY 0x1000
442
443 /* MACCtrl */
444 #define IPG_MC_RSVD_MASK 0x7FE33FA3
445 #define IPG_MC_IFS_SELECT 0x00000003
446 #define IPG_MC_IFS_4352BIT 0x00000003
447 #define IPG_MC_IFS_1792BIT 0x00000002
448 #define IPG_MC_IFS_1024BIT 0x00000001
449 #define IPG_MC_IFS_96BIT 0x00000000
450 #define IPG_MC_DUPLEX_SELECT 0x00000020
451 #define IPG_MC_DUPLEX_SELECT_FD 0x00000020
452 #define IPG_MC_DUPLEX_SELECT_HD 0x00000000
453 #define IPG_MC_TX_FLOW_CONTROL_ENABLE 0x00000080
454 #define IPG_MC_RX_FLOW_CONTROL_ENABLE 0x00000100
455 #define IPG_MC_RCV_FCS 0x00000200
456 #define IPG_MC_FIFO_LOOPBACK 0x00000400
457 #define IPG_MC_MAC_LOOPBACK 0x00000800
458 #define IPG_MC_AUTO_VLAN_TAGGING 0x00001000
459 #define IPG_MC_AUTO_VLAN_UNTAGGING 0x00002000
460 #define IPG_MC_COLLISION_DETECT 0x00010000
461 #define IPG_MC_CARRIER_SENSE 0x00020000
462 #define IPG_MC_STATISTICS_ENABLE 0x00200000
463 #define IPG_MC_STATISTICS_DISABLE 0x00400000
464 #define IPG_MC_STATISTICS_ENABLED 0x00800000
465 #define IPG_MC_TX_ENABLE 0x01000000
466 #define IPG_MC_TX_DISABLE 0x02000000
467 #define IPG_MC_TX_ENABLED 0x04000000
468 #define IPG_MC_RX_ENABLE 0x08000000
469 #define IPG_MC_RX_DISABLE 0x10000000
470 #define IPG_MC_RX_ENABLED 0x20000000
471 #define IPG_MC_PAUSED 0x40000000
472
473 /*
474 * Tune
475 */
476
477 /* Assign IPG_APPEND_FCS_ON_TX > 0 for auto FCS append on TX. */
478 #define IPG_APPEND_FCS_ON_TX 1
479
480 /* Assign IPG_APPEND_FCS_ON_TX > 0 for auto FCS strip on RX. */
481 #define IPG_STRIP_FCS_ON_RX 1
482
483 /* Assign IPG_DROP_ON_RX_ETH_ERRORS > 0 to drop RX frames with
484 * Ethernet errors.
485 */
486 #define IPG_DROP_ON_RX_ETH_ERRORS 1
487
488 /* Assign IPG_INSERT_MANUAL_VLAN_TAG > 0 to insert VLAN tags manually
489 * (via TFC).
490 */
491 #define IPG_INSERT_MANUAL_VLAN_TAG 0
492
493 /* Assign IPG_ADD_IPCHECKSUM_ON_TX > 0 for auto IP checksum on TX. */
494 #define IPG_ADD_IPCHECKSUM_ON_TX 0
495
496 /* Assign IPG_ADD_TCPCHECKSUM_ON_TX > 0 for auto TCP checksum on TX.
497 * DO NOT USE FOR SILICON REVISIONS B3 AND EARLIER.
498 */
499 #define IPG_ADD_TCPCHECKSUM_ON_TX 0
500
501 /* Assign IPG_ADD_UDPCHECKSUM_ON_TX > 0 for auto UDP checksum on TX.
502 * DO NOT USE FOR SILICON REVISIONS B3 AND EARLIER.
503 */
504 #define IPG_ADD_UDPCHECKSUM_ON_TX 0
505
506 /* If inserting VLAN tags manually, assign the IPG_MANUAL_VLAN_xx
507 * constants as desired.
508 */
509 #define IPG_MANUAL_VLAN_VID 0xABC
510 #define IPG_MANUAL_VLAN_CFI 0x1
511 #define IPG_MANUAL_VLAN_USERPRIORITY 0x5
512
513 #define IPG_IO_REG_RANGE 0xFF
514 #define IPG_MEM_REG_RANGE 0x154
515 #define IPG_DRIVER_NAME "Sundance Technology IPG Triple-Speed Ethernet"
516 #define IPG_NIC_PHY_ADDRESS 0x01
517 #define IPG_DMALIST_ALIGN_PAD 0x07
518 #define IPG_MULTICAST_HASHTABLE_SIZE 0x40
519
520 /* Number of miliseconds to wait after issuing a software reset.
521 * 0x05 <= IPG_AC_RESETWAIT to account for proper 10Mbps operation.
522 */
523 #define IPG_AC_RESETWAIT 0x05
524
525 /* Number of IPG_AC_RESETWAIT timeperiods before declaring timeout. */
526 #define IPG_AC_RESET_TIMEOUT 0x0A
527
528 /* Minimum number of nanoseconds used to toggle MDC clock during
529 * MII/GMII register access.
530 */
531 #define IPG_PC_PHYCTRLWAIT_NS 200
532
533 #define IPG_TFDLIST_LENGTH 0x100
534
535 /* Number of frames between TxDMAComplete interrupt.
536 * 0 < IPG_FRAMESBETWEENTXDMACOMPLETES <= IPG_TFDLIST_LENGTH
537 */
538 #define IPG_FRAMESBETWEENTXDMACOMPLETES 0x1
539
540 #ifdef JUMBO_FRAME
541
542 # ifdef JUMBO_FRAME_SIZE_2K
543 # define JUMBO_FRAME_SIZE 2048
544 # define __IPG_RXFRAG_SIZE 2048
545 # else
546 # ifdef JUMBO_FRAME_SIZE_3K
547 # define JUMBO_FRAME_SIZE 3072
548 # define __IPG_RXFRAG_SIZE 3072
549 # else
550 # ifdef JUMBO_FRAME_SIZE_4K
551 # define JUMBO_FRAME_SIZE 4096
552 # define __IPG_RXFRAG_SIZE 4088
553 # else
554 # ifdef JUMBO_FRAME_SIZE_5K
555 # define JUMBO_FRAME_SIZE 5120
556 # define __IPG_RXFRAG_SIZE 4088
557 # else
558 # ifdef JUMBO_FRAME_SIZE_6K
559 # define JUMBO_FRAME_SIZE 6144
560 # define __IPG_RXFRAG_SIZE 4088
561 # else
562 # ifdef JUMBO_FRAME_SIZE_7K
563 # define JUMBO_FRAME_SIZE 7168
564 # define __IPG_RXFRAG_SIZE 4088
565 # else
566 # ifdef JUMBO_FRAME_SIZE_8K
567 # define JUMBO_FRAME_SIZE 8192
568 # define __IPG_RXFRAG_SIZE 4088
569 # else
570 # ifdef JUMBO_FRAME_SIZE_9K
571 # define JUMBO_FRAME_SIZE 9216
572 # define __IPG_RXFRAG_SIZE 4088
573 # else
574 # ifdef JUMBO_FRAME_SIZE_10K
575 # define JUMBO_FRAME_SIZE 10240
576 # define __IPG_RXFRAG_SIZE 4088
577 # else
578 # define JUMBO_FRAME_SIZE 4096
579 # endif
580 # endif
581 # endif
582 # endif
583 # endif
584 # endif
585 # endif
586 # endif
587 # endif
588 #endif
589
590 /* Size of allocated received buffers. Nominally 0x0600.
591 * Define larger if expecting jumbo frames.
592 */
593 #ifdef JUMBO_FRAME
594 //IPG_TXFRAG_SIZE must <= 0x2b00, or TX will crash
595 #define IPG_TXFRAG_SIZE JUMBO_FRAME_SIZE
596 #endif
597
598 /* Size of allocated received buffers. Nominally 0x0600.
599 * Define larger if expecting jumbo frames.
600 */
601 #ifdef JUMBO_FRAME
602 //4088=4096-8
603 #define IPG_RXFRAG_SIZE __IPG_RXFRAG_SIZE
604 #define IPG_RXSUPPORT_SIZE IPG_MAX_RXFRAME_SIZE
605 #else
606 #define IPG_RXFRAG_SIZE 0x0600
607 #define IPG_RXSUPPORT_SIZE IPG_RXFRAG_SIZE
608 #endif
609
610 /* IPG_MAX_RXFRAME_SIZE <= IPG_RXFRAG_SIZE */
611 #ifdef JUMBO_FRAME
612 #define IPG_MAX_RXFRAME_SIZE JUMBO_FRAME_SIZE
613 #else
614 #define IPG_MAX_RXFRAME_SIZE 0x0600
615 #endif
616
617 #define IPG_RFDLIST_LENGTH 0x100
618
619 /* Maximum number of RFDs to process per interrupt.
620 * 1 < IPG_MAXRFDPROCESS_COUNT < IPG_RFDLIST_LENGTH
621 */
622 #define IPG_MAXRFDPROCESS_COUNT 0x80
623
624 /* Minimum margin between last freed RFD, and current RFD.
625 * 1 < IPG_MINUSEDRFDSTOFREE < IPG_RFDLIST_LENGTH
626 */
627 #define IPG_MINUSEDRFDSTOFREE 0x80
628
629 /* specify the jumbo frame maximum size
630 * per unit is 0x600 (the RxBuffer size that one RFD can carry)
631 */
632 #define MAX_JUMBOSIZE 0x8 // max is 12K
633
634 /* Key register values loaded at driver start up. */
635
636 /* TXDMAPollPeriod is specified in 320ns increments.
637 *
638 * Value Time
639 * ---------------------
640 * 0x00-0x01 320ns
641 * 0x03 ~1us
642 * 0x1F ~10us
643 * 0xFF ~82us
644 */
645 #define IPG_TXDMAPOLLPERIOD_VALUE 0x26
646
647 /* TxDMAUrgentThresh specifies the minimum amount of
648 * data in the transmit FIFO before asserting an
649 * urgent transmit DMA request.
650 *
651 * Value Min TxFIFO occupied space before urgent TX request
652 * ---------------------------------------------------------------
653 * 0x00-0x04 128 bytes (1024 bits)
654 * 0x27 1248 bytes (~10000 bits)
655 * 0x30 1536 bytes (12288 bits)
656 * 0xFF 8192 bytes (65535 bits)
657 */
658 #define IPG_TXDMAURGENTTHRESH_VALUE 0x04
659
660 /* TxDMABurstThresh specifies the minimum amount of
661 * free space in the transmit FIFO before asserting an
662 * transmit DMA request.
663 *
664 * Value Min TxFIFO free space before TX request
665 * ----------------------------------------------------
666 * 0x00-0x08 256 bytes
667 * 0x30 1536 bytes
668 * 0xFF 8192 bytes
669 */
670 #define IPG_TXDMABURSTTHRESH_VALUE 0x30
671
672 /* RXDMAPollPeriod is specified in 320ns increments.
673 *
674 * Value Time
675 * ---------------------
676 * 0x00-0x01 320ns
677 * 0x03 ~1us
678 * 0x1F ~10us
679 * 0xFF ~82us
680 */
681 #define IPG_RXDMAPOLLPERIOD_VALUE 0x01
682
683 /* RxDMAUrgentThresh specifies the minimum amount of
684 * free space within the receive FIFO before asserting
685 * a urgent receive DMA request.
686 *
687 * Value Min RxFIFO free space before urgent RX request
688 * ---------------------------------------------------------------
689 * 0x00-0x04 128 bytes (1024 bits)
690 * 0x27 1248 bytes (~10000 bits)
691 * 0x30 1536 bytes (12288 bits)
692 * 0xFF 8192 bytes (65535 bits)
693 */
694 #define IPG_RXDMAURGENTTHRESH_VALUE 0x30
695
696 /* RxDMABurstThresh specifies the minimum amount of
697 * occupied space within the receive FIFO before asserting
698 * a receive DMA request.
699 *
700 * Value Min TxFIFO free space before TX request
701 * ----------------------------------------------------
702 * 0x00-0x08 256 bytes
703 * 0x30 1536 bytes
704 * 0xFF 8192 bytes
705 */
706 #define IPG_RXDMABURSTTHRESH_VALUE 0x30
707
708 /* FlowOnThresh specifies the maximum amount of occupied
709 * space in the receive FIFO before a PAUSE frame with
710 * maximum pause time transmitted.
711 *
712 * Value Max RxFIFO occupied space before PAUSE
713 * ---------------------------------------------------
714 * 0x0000 0 bytes
715 * 0x0740 29,696 bytes
716 * 0x07FF 32,752 bytes
717 */
718 #define IPG_FLOWONTHRESH_VALUE 0x0740
719
720 /* FlowOffThresh specifies the minimum amount of occupied
721 * space in the receive FIFO before a PAUSE frame with
722 * zero pause time is transmitted.
723 *
724 * Value Max RxFIFO occupied space before PAUSE
725 * ---------------------------------------------------
726 * 0x0000 0 bytes
727 * 0x00BF 3056 bytes
728 * 0x07FF 32,752 bytes
729 */
730 #define IPG_FLOWOFFTHRESH_VALUE 0x00BF
731
732 /*
733 * Miscellaneous macros.
734 */
735
736 /* Marco for printing debug statements.
737 # define IPG_DDEBUG_MSG(args...) printk(KERN_DEBUG "IPG: " ## args) */
738 #ifdef IPG_DEBUG
739 # define IPG_DEBUG_MSG(args...)
740 # define IPG_DDEBUG_MSG(args...) printk(KERN_DEBUG "IPG: " args)
741 # define IPG_DUMPRFDLIST(args) ipg_dump_rfdlist(args)
742 # define IPG_DUMPTFDLIST(args) ipg_dump_tfdlist(args)
743 #else
744 # define IPG_DEBUG_MSG(args...)
745 # define IPG_DDEBUG_MSG(args...)
746 # define IPG_DUMPRFDLIST(args)
747 # define IPG_DUMPTFDLIST(args)
748 #endif
749
750 /*
751 * End miscellaneous macros.
752 */
753
754 /* Transmit Frame Descriptor. The IPG supports 15 fragments,
755 * however Linux requires only a single fragment. Note, each
756 * TFD field is 64 bits wide.
757 */
758 struct ipg_tx {
759 __le64 next_desc;
760 __le64 tfc;
761 __le64 frag_info;
762 };
763
764 /* Receive Frame Descriptor. Note, each RFD field is 64 bits wide.
765 */
766 struct ipg_rx {
767 __le64 next_desc;
768 __le64 rfs;
769 __le64 frag_info;
770 };
771
772 struct SJumbo {
773 int FoundStart;
774 int CurrentSize;
775 struct sk_buff *skb;
776 };
777 /* Structure of IPG NIC specific data. */
778 struct ipg_nic_private {
779 void __iomem *ioaddr;
780 struct ipg_tx *txd;
781 struct ipg_rx *rxd;
782 dma_addr_t txd_map;
783 dma_addr_t rxd_map;
784 struct sk_buff *TxBuff[IPG_TFDLIST_LENGTH];
785 struct sk_buff *RxBuff[IPG_RFDLIST_LENGTH];
786 unsigned int tx_current;
787 unsigned int tx_dirty;
788 unsigned int rx_current;
789 unsigned int rx_dirty;
790 // Add by Grace 2005/05/19
791 #ifdef JUMBO_FRAME
792 struct SJumbo Jumbo;
793 #endif
794 unsigned int rx_buf_sz;
795 struct pci_dev *pdev;
796 struct net_device *dev;
797 struct net_device_stats stats;
798 spinlock_t lock;
799 int tenmbpsmode;
800
801 /*Jesse20040128EEPROM_VALUE */
802 u16 LED_Mode;
803 u16 station_addr[3]; /* Station Address in EEPROM Reg 0x10..0x12 */
804
805 struct mutex mii_mutex;
806 struct mii_if_info mii_if;
807 int ResetCurrentTFD;
808 #ifdef IPG_DEBUG
809 int RFDlistendCount;
810 int RFDListCheckedCount;
811 int EmptyRFDListCount;
812 #endif
813 struct delayed_work task;
814 };
815
816 #endif /* __LINUX_IPG_H */
Linux kernel - Deliverables
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