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[netdrvr] Fix 8390 build breakage
[deliverable/linux.git] / drivers / net / irda / smsc-ircc2.c
1 /*********************************************************************
2 * $Id: smsc-ircc2.c,v 1.19.2.5 2002/10/27 11:34:26 dip Exp $
3 *
4 * Description: Driver for the SMC Infrared Communications Controller
5 * Status: Experimental.
6 * Author: Daniele Peri (peri@csai.unipa.it)
7 * Created at:
8 * Modified at:
9 * Modified by:
10 *
11 * Copyright (c) 2002 Daniele Peri
12 * All Rights Reserved.
13 * Copyright (c) 2002 Jean Tourrilhes
14 * Copyright (c) 2006 Linus Walleij
15 *
16 *
17 * Based on smc-ircc.c:
18 *
19 * Copyright (c) 2001 Stefani Seibold
20 * Copyright (c) 1999-2001 Dag Brattli
21 * Copyright (c) 1998-1999 Thomas Davis,
22 *
23 * and irport.c:
24 *
25 * Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved.
26 *
27 *
28 * This program is free software; you can redistribute it and/or
29 * modify it under the terms of the GNU General Public License as
30 * published by the Free Software Foundation; either version 2 of
31 * the License, or (at your option) any later version.
32 *
33 * This program is distributed in the hope that it will be useful,
34 * but WITHOUT ANY WARRANTY; without even the implied warranty of
35 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
36 * GNU General Public License for more details.
37 *
38 * You should have received a copy of the GNU General Public License
39 * along with this program; if not, write to the Free Software
40 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
41 * MA 02111-1307 USA
42 *
43 ********************************************************************/
44
45 #include <linux/module.h>
46 #include <linux/kernel.h>
47 #include <linux/types.h>
48 #include <linux/skbuff.h>
49 #include <linux/netdevice.h>
50 #include <linux/ioport.h>
51 #include <linux/delay.h>
52 #include <linux/slab.h>
53 #include <linux/init.h>
54 #include <linux/rtnetlink.h>
55 #include <linux/serial_reg.h>
56 #include <linux/dma-mapping.h>
57 #include <linux/pnp.h>
58 #include <linux/platform_device.h>
59
60 #include <asm/io.h>
61 #include <asm/dma.h>
62 #include <asm/byteorder.h>
63
64 #include <linux/spinlock.h>
65 #include <linux/pm.h>
66 #ifdef CONFIG_PCI
67 #include <linux/pci.h>
68 #endif
69
70 #include <net/irda/wrapper.h>
71 #include <net/irda/irda.h>
72 #include <net/irda/irda_device.h>
73
74 #include "smsc-ircc2.h"
75 #include "smsc-sio.h"
76
77
78 MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>");
79 MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver");
80 MODULE_LICENSE("GPL");
81
82 static int smsc_nopnp = 1;
83 module_param_named(nopnp, smsc_nopnp, bool, 0);
84 MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings, defaults to true");
85
86 #define DMA_INVAL 255
87 static int ircc_dma = DMA_INVAL;
88 module_param(ircc_dma, int, 0);
89 MODULE_PARM_DESC(ircc_dma, "DMA channel");
90
91 #define IRQ_INVAL 255
92 static int ircc_irq = IRQ_INVAL;
93 module_param(ircc_irq, int, 0);
94 MODULE_PARM_DESC(ircc_irq, "IRQ line");
95
96 static int ircc_fir;
97 module_param(ircc_fir, int, 0);
98 MODULE_PARM_DESC(ircc_fir, "FIR Base Address");
99
100 static int ircc_sir;
101 module_param(ircc_sir, int, 0);
102 MODULE_PARM_DESC(ircc_sir, "SIR Base Address");
103
104 static int ircc_cfg;
105 module_param(ircc_cfg, int, 0);
106 MODULE_PARM_DESC(ircc_cfg, "Configuration register base address");
107
108 static int ircc_transceiver;
109 module_param(ircc_transceiver, int, 0);
110 MODULE_PARM_DESC(ircc_transceiver, "Transceiver type");
111
112 /* Types */
113
114 #ifdef CONFIG_PCI
115 struct smsc_ircc_subsystem_configuration {
116 unsigned short vendor; /* PCI vendor ID */
117 unsigned short device; /* PCI vendor ID */
118 unsigned short subvendor; /* PCI subsystem vendor ID */
119 unsigned short subdevice; /* PCI sybsystem device ID */
120 unsigned short sir_io; /* I/O port for SIR */
121 unsigned short fir_io; /* I/O port for FIR */
122 unsigned char fir_irq; /* FIR IRQ */
123 unsigned char fir_dma; /* FIR DMA */
124 unsigned short cfg_base; /* I/O port for chip configuration */
125 int (*preconfigure)(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); /* Preconfig function */
126 const char *name; /* name shown as info */
127 };
128 #endif
129
130 struct smsc_transceiver {
131 char *name;
132 void (*set_for_speed)(int fir_base, u32 speed);
133 int (*probe)(int fir_base);
134 };
135
136 struct smsc_chip {
137 char *name;
138 #if 0
139 u8 type;
140 #endif
141 u16 flags;
142 u8 devid;
143 u8 rev;
144 };
145
146 struct smsc_chip_address {
147 unsigned int cfg_base;
148 unsigned int type;
149 };
150
151 /* Private data for each instance */
152 struct smsc_ircc_cb {
153 struct net_device *netdev; /* Yes! we are some kind of netdevice */
154 struct net_device_stats stats;
155 struct irlap_cb *irlap; /* The link layer we are binded to */
156
157 chipio_t io; /* IrDA controller information */
158 iobuff_t tx_buff; /* Transmit buffer */
159 iobuff_t rx_buff; /* Receive buffer */
160 dma_addr_t tx_buff_dma;
161 dma_addr_t rx_buff_dma;
162
163 struct qos_info qos; /* QoS capabilities for this device */
164
165 spinlock_t lock; /* For serializing operations */
166
167 __u32 new_speed;
168 __u32 flags; /* Interface flags */
169
170 int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */
171 int tx_len; /* Number of frames in tx_buff */
172
173 int transceiver;
174 struct platform_device *pldev;
175 };
176
177 /* Constants */
178
179 #define SMSC_IRCC2_DRIVER_NAME "smsc-ircc2"
180
181 #define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED 9600
182 #define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER 1
183 #define SMSC_IRCC2_C_NET_TIMEOUT 0
184 #define SMSC_IRCC2_C_SIR_STOP 0
185
186 static const char *driver_name = SMSC_IRCC2_DRIVER_NAME;
187
188 /* Prototypes */
189
190 static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq);
191 static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base);
192 static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq);
193 static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self);
194 static void smsc_ircc_init_chip(struct smsc_ircc_cb *self);
195 static int __exit smsc_ircc_close(struct smsc_ircc_cb *self);
196 static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self);
197 static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self);
198 static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self);
199 static int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev);
200 static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev);
201 static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs);
202 static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self);
203 static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed);
204 static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, u32 speed);
205 static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id);
206 static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev);
207 static void smsc_ircc_sir_start(struct smsc_ircc_cb *self);
208 #if SMSC_IRCC2_C_SIR_STOP
209 static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self);
210 #endif
211 static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self);
212 static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
213 static int smsc_ircc_net_open(struct net_device *dev);
214 static int smsc_ircc_net_close(struct net_device *dev);
215 static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
216 #if SMSC_IRCC2_C_NET_TIMEOUT
217 static void smsc_ircc_timeout(struct net_device *dev);
218 #endif
219 static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev);
220 static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self);
221 static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self);
222 static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed);
223 static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self);
224
225 /* Probing */
226 static int __init smsc_ircc_look_for_chips(void);
227 static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type);
228 static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
229 static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
230 static int __init smsc_superio_fdc(unsigned short cfg_base);
231 static int __init smsc_superio_lpc(unsigned short cfg_base);
232 #ifdef CONFIG_PCI
233 static int __init preconfigure_smsc_chip(struct smsc_ircc_subsystem_configuration *conf);
234 static int __init preconfigure_through_82801(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
235 static void __init preconfigure_ali_port(struct pci_dev *dev,
236 unsigned short port);
237 static int __init preconfigure_through_ali(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
238 static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
239 unsigned short ircc_fir,
240 unsigned short ircc_sir,
241 unsigned char ircc_dma,
242 unsigned char ircc_irq);
243 #endif
244
245 /* Transceivers specific functions */
246
247 static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed);
248 static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base);
249 static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed);
250 static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base);
251 static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed);
252 static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base);
253
254 /* Power Management */
255
256 static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state);
257 static int smsc_ircc_resume(struct platform_device *dev);
258
259 static struct platform_driver smsc_ircc_driver = {
260 .suspend = smsc_ircc_suspend,
261 .resume = smsc_ircc_resume,
262 .driver = {
263 .name = SMSC_IRCC2_DRIVER_NAME,
264 },
265 };
266
267 /* Transceivers for SMSC-ircc */
268
269 static struct smsc_transceiver smsc_transceivers[] =
270 {
271 { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 },
272 { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select },
273 { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc },
274 { NULL, NULL }
275 };
276 #define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (ARRAY_SIZE(smsc_transceivers) - 1)
277
278 /* SMC SuperIO chipsets definitions */
279
280 #define KEY55_1 0 /* SuperIO Configuration mode with Key <0x55> */
281 #define KEY55_2 1 /* SuperIO Configuration mode with Key <0x55,0x55> */
282 #define NoIRDA 2 /* SuperIO Chip has no IRDA Port */
283 #define SIR 0 /* SuperIO Chip has only slow IRDA */
284 #define FIR 4 /* SuperIO Chip has fast IRDA */
285 #define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */
286
287 static struct smsc_chip __initdata fdc_chips_flat[] =
288 {
289 /* Base address 0x3f0 or 0x370 */
290 { "37C44", KEY55_1|NoIRDA, 0x00, 0x00 }, /* This chip cannot be detected */
291 { "37C665GT", KEY55_2|NoIRDA, 0x65, 0x01 },
292 { "37C665GT", KEY55_2|NoIRDA, 0x66, 0x01 },
293 { "37C669", KEY55_2|SIR|SERx4, 0x03, 0x02 },
294 { "37C669", KEY55_2|SIR|SERx4, 0x04, 0x02 }, /* ID? */
295 { "37C78", KEY55_2|NoIRDA, 0x78, 0x00 },
296 { "37N769", KEY55_1|FIR|SERx4, 0x28, 0x00 },
297 { "37N869", KEY55_1|FIR|SERx4, 0x29, 0x00 },
298 { NULL }
299 };
300
301 static struct smsc_chip __initdata fdc_chips_paged[] =
302 {
303 /* Base address 0x3f0 or 0x370 */
304 { "37B72X", KEY55_1|SIR|SERx4, 0x4c, 0x00 },
305 { "37B77X", KEY55_1|SIR|SERx4, 0x43, 0x00 },
306 { "37B78X", KEY55_1|SIR|SERx4, 0x44, 0x00 },
307 { "37B80X", KEY55_1|SIR|SERx4, 0x42, 0x00 },
308 { "37C67X", KEY55_1|FIR|SERx4, 0x40, 0x00 },
309 { "37C93X", KEY55_2|SIR|SERx4, 0x02, 0x01 },
310 { "37C93XAPM", KEY55_1|SIR|SERx4, 0x30, 0x01 },
311 { "37C93XFR", KEY55_2|FIR|SERx4, 0x03, 0x01 },
312 { "37M707", KEY55_1|SIR|SERx4, 0x42, 0x00 },
313 { "37M81X", KEY55_1|SIR|SERx4, 0x4d, 0x00 },
314 { "37N958FR", KEY55_1|FIR|SERx4, 0x09, 0x04 },
315 { "37N971", KEY55_1|FIR|SERx4, 0x0a, 0x00 },
316 { "37N972", KEY55_1|FIR|SERx4, 0x0b, 0x00 },
317 { NULL }
318 };
319
320 static struct smsc_chip __initdata lpc_chips_flat[] =
321 {
322 /* Base address 0x2E or 0x4E */
323 { "47N227", KEY55_1|FIR|SERx4, 0x5a, 0x00 },
324 { "47N227", KEY55_1|FIR|SERx4, 0x7a, 0x00 },
325 { "47N267", KEY55_1|FIR|SERx4, 0x5e, 0x00 },
326 { NULL }
327 };
328
329 static struct smsc_chip __initdata lpc_chips_paged[] =
330 {
331 /* Base address 0x2E or 0x4E */
332 { "47B27X", KEY55_1|SIR|SERx4, 0x51, 0x00 },
333 { "47B37X", KEY55_1|SIR|SERx4, 0x52, 0x00 },
334 { "47M10X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
335 { "47M120", KEY55_1|NoIRDA|SERx4, 0x5c, 0x00 },
336 { "47M13X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
337 { "47M14X", KEY55_1|SIR|SERx4, 0x5f, 0x00 },
338 { "47N252", KEY55_1|FIR|SERx4, 0x0e, 0x00 },
339 { "47S42X", KEY55_1|SIR|SERx4, 0x57, 0x00 },
340 { NULL }
341 };
342
343 #define SMSCSIO_TYPE_FDC 1
344 #define SMSCSIO_TYPE_LPC 2
345 #define SMSCSIO_TYPE_FLAT 4
346 #define SMSCSIO_TYPE_PAGED 8
347
348 static struct smsc_chip_address __initdata possible_addresses[] =
349 {
350 { 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
351 { 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
352 { 0xe0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
353 { 0x2e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
354 { 0x4e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
355 { 0, 0 }
356 };
357
358 /* Globals */
359
360 static struct smsc_ircc_cb *dev_self[] = { NULL, NULL };
361 static unsigned short dev_count;
362
363 static inline void register_bank(int iobase, int bank)
364 {
365 outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)),
366 iobase + IRCC_MASTER);
367 }
368
369 /* PNP hotplug support */
370 static const struct pnp_device_id smsc_ircc_pnp_table[] = {
371 { .id = "SMCf010", .driver_data = 0 },
372 /* and presumably others */
373 { }
374 };
375 MODULE_DEVICE_TABLE(pnp, smsc_ircc_pnp_table);
376
377 static int pnp_driver_registered;
378
379 #ifdef CONFIG_PNP
380 static int __init smsc_ircc_pnp_probe(struct pnp_dev *dev,
381 const struct pnp_device_id *dev_id)
382 {
383 unsigned int firbase, sirbase;
384 u8 dma, irq;
385
386 if (!(pnp_port_valid(dev, 0) && pnp_port_valid(dev, 1) &&
387 pnp_dma_valid(dev, 0) && pnp_irq_valid(dev, 0)))
388 return -EINVAL;
389
390 sirbase = pnp_port_start(dev, 0);
391 firbase = pnp_port_start(dev, 1);
392 dma = pnp_dma(dev, 0);
393 irq = pnp_irq(dev, 0);
394
395 if (smsc_ircc_open(firbase, sirbase, dma, irq))
396 return -ENODEV;
397
398 return 0;
399 }
400
401 static struct pnp_driver smsc_ircc_pnp_driver = {
402 .name = "smsc-ircc2",
403 .id_table = smsc_ircc_pnp_table,
404 .probe = smsc_ircc_pnp_probe,
405 };
406 #else /* CONFIG_PNP */
407 static struct pnp_driver smsc_ircc_pnp_driver;
408 #endif
409
410 /*******************************************************************************
411 *
412 *
413 * SMSC-ircc stuff
414 *
415 *
416 *******************************************************************************/
417
418 static int __init smsc_ircc_legacy_probe(void)
419 {
420 int ret = 0;
421
422 #ifdef CONFIG_PCI
423 if (smsc_ircc_preconfigure_subsystems(ircc_cfg, ircc_fir, ircc_sir, ircc_dma, ircc_irq) < 0) {
424 /* Ignore errors from preconfiguration */
425 IRDA_ERROR("%s, Preconfiguration failed !\n", driver_name);
426 }
427 #endif
428
429 if (ircc_fir > 0 && ircc_sir > 0) {
430 IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir);
431 IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir);
432
433 if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq))
434 ret = -ENODEV;
435 } else {
436 ret = -ENODEV;
437
438 /* try user provided configuration register base address */
439 if (ircc_cfg > 0) {
440 IRDA_MESSAGE(" Overriding configuration address "
441 "0x%04x\n", ircc_cfg);
442 if (!smsc_superio_fdc(ircc_cfg))
443 ret = 0;
444 if (!smsc_superio_lpc(ircc_cfg))
445 ret = 0;
446 }
447
448 if (smsc_ircc_look_for_chips() > 0)
449 ret = 0;
450 }
451 return ret;
452 }
453
454 /*
455 * Function smsc_ircc_init ()
456 *
457 * Initialize chip. Just try to find out how many chips we are dealing with
458 * and where they are
459 */
460 static int __init smsc_ircc_init(void)
461 {
462 int ret;
463
464 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
465
466 ret = platform_driver_register(&smsc_ircc_driver);
467 if (ret) {
468 IRDA_ERROR("%s, Can't register driver!\n", driver_name);
469 return ret;
470 }
471
472 dev_count = 0;
473
474 if (smsc_nopnp || !pnp_platform_devices ||
475 ircc_cfg || ircc_fir || ircc_sir ||
476 ircc_dma != DMA_INVAL || ircc_irq != IRQ_INVAL) {
477 ret = smsc_ircc_legacy_probe();
478 } else {
479 if (pnp_register_driver(&smsc_ircc_pnp_driver) == 0)
480 pnp_driver_registered = 1;
481 }
482
483 if (ret) {
484 if (pnp_driver_registered)
485 pnp_unregister_driver(&smsc_ircc_pnp_driver);
486 platform_driver_unregister(&smsc_ircc_driver);
487 }
488
489 return ret;
490 }
491
492 /*
493 * Function smsc_ircc_open (firbase, sirbase, dma, irq)
494 *
495 * Try to open driver instance
496 *
497 */
498 static int __init smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq)
499 {
500 struct smsc_ircc_cb *self;
501 struct net_device *dev;
502 int err;
503
504 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
505
506 err = smsc_ircc_present(fir_base, sir_base);
507 if (err)
508 goto err_out;
509
510 err = -ENOMEM;
511 if (dev_count >= ARRAY_SIZE(dev_self)) {
512 IRDA_WARNING("%s(), too many devices!\n", __FUNCTION__);
513 goto err_out1;
514 }
515
516 /*
517 * Allocate new instance of the driver
518 */
519 dev = alloc_irdadev(sizeof(struct smsc_ircc_cb));
520 if (!dev) {
521 IRDA_WARNING("%s() can't allocate net device\n", __FUNCTION__);
522 goto err_out1;
523 }
524
525 dev->hard_start_xmit = smsc_ircc_hard_xmit_sir;
526 #if SMSC_IRCC2_C_NET_TIMEOUT
527 dev->tx_timeout = smsc_ircc_timeout;
528 dev->watchdog_timeo = HZ * 2; /* Allow enough time for speed change */
529 #endif
530 dev->open = smsc_ircc_net_open;
531 dev->stop = smsc_ircc_net_close;
532 dev->do_ioctl = smsc_ircc_net_ioctl;
533 dev->get_stats = smsc_ircc_net_get_stats;
534
535 self = netdev_priv(dev);
536 self->netdev = dev;
537
538 /* Make ifconfig display some details */
539 dev->base_addr = self->io.fir_base = fir_base;
540 dev->irq = self->io.irq = irq;
541
542 /* Need to store self somewhere */
543 dev_self[dev_count] = self;
544 spin_lock_init(&self->lock);
545
546 self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE;
547 self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE;
548
549 self->rx_buff.head =
550 dma_alloc_coherent(NULL, self->rx_buff.truesize,
551 &self->rx_buff_dma, GFP_KERNEL);
552 if (self->rx_buff.head == NULL) {
553 IRDA_ERROR("%s, Can't allocate memory for receive buffer!\n",
554 driver_name);
555 goto err_out2;
556 }
557
558 self->tx_buff.head =
559 dma_alloc_coherent(NULL, self->tx_buff.truesize,
560 &self->tx_buff_dma, GFP_KERNEL);
561 if (self->tx_buff.head == NULL) {
562 IRDA_ERROR("%s, Can't allocate memory for transmit buffer!\n",
563 driver_name);
564 goto err_out3;
565 }
566
567 memset(self->rx_buff.head, 0, self->rx_buff.truesize);
568 memset(self->tx_buff.head, 0, self->tx_buff.truesize);
569
570 self->rx_buff.in_frame = FALSE;
571 self->rx_buff.state = OUTSIDE_FRAME;
572 self->tx_buff.data = self->tx_buff.head;
573 self->rx_buff.data = self->rx_buff.head;
574
575 smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq);
576 smsc_ircc_setup_qos(self);
577 smsc_ircc_init_chip(self);
578
579 if (ircc_transceiver > 0 &&
580 ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS)
581 self->transceiver = ircc_transceiver;
582 else
583 smsc_ircc_probe_transceiver(self);
584
585 err = register_netdev(self->netdev);
586 if (err) {
587 IRDA_ERROR("%s, Network device registration failed!\n",
588 driver_name);
589 goto err_out4;
590 }
591
592 self->pldev = platform_device_register_simple(SMSC_IRCC2_DRIVER_NAME,
593 dev_count, NULL, 0);
594 if (IS_ERR(self->pldev)) {
595 err = PTR_ERR(self->pldev);
596 goto err_out5;
597 }
598 platform_set_drvdata(self->pldev, self);
599
600 IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name);
601 dev_count++;
602
603 return 0;
604
605 err_out5:
606 unregister_netdev(self->netdev);
607
608 err_out4:
609 dma_free_coherent(NULL, self->tx_buff.truesize,
610 self->tx_buff.head, self->tx_buff_dma);
611 err_out3:
612 dma_free_coherent(NULL, self->rx_buff.truesize,
613 self->rx_buff.head, self->rx_buff_dma);
614 err_out2:
615 free_netdev(self->netdev);
616 dev_self[dev_count] = NULL;
617 err_out1:
618 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
619 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
620 err_out:
621 return err;
622 }
623
624 /*
625 * Function smsc_ircc_present(fir_base, sir_base)
626 *
627 * Check the smsc-ircc chip presence
628 *
629 */
630 static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base)
631 {
632 unsigned char low, high, chip, config, dma, irq, version;
633
634 if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT,
635 driver_name)) {
636 IRDA_WARNING("%s: can't get fir_base of 0x%03x\n",
637 __FUNCTION__, fir_base);
638 goto out1;
639 }
640
641 if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT,
642 driver_name)) {
643 IRDA_WARNING("%s: can't get sir_base of 0x%03x\n",
644 __FUNCTION__, sir_base);
645 goto out2;
646 }
647
648 register_bank(fir_base, 3);
649
650 high = inb(fir_base + IRCC_ID_HIGH);
651 low = inb(fir_base + IRCC_ID_LOW);
652 chip = inb(fir_base + IRCC_CHIP_ID);
653 version = inb(fir_base + IRCC_VERSION);
654 config = inb(fir_base + IRCC_INTERFACE);
655 dma = config & IRCC_INTERFACE_DMA_MASK;
656 irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
657
658 if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) {
659 IRDA_WARNING("%s(), addr 0x%04x - no device found!\n",
660 __FUNCTION__, fir_base);
661 goto out3;
662 }
663 IRDA_MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, "
664 "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n",
665 chip & 0x0f, version, fir_base, sir_base, dma, irq);
666
667 return 0;
668
669 out3:
670 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
671 out2:
672 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
673 out1:
674 return -ENODEV;
675 }
676
677 /*
678 * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq)
679 *
680 * Setup I/O
681 *
682 */
683 static void smsc_ircc_setup_io(struct smsc_ircc_cb *self,
684 unsigned int fir_base, unsigned int sir_base,
685 u8 dma, u8 irq)
686 {
687 unsigned char config, chip_dma, chip_irq;
688
689 register_bank(fir_base, 3);
690 config = inb(fir_base + IRCC_INTERFACE);
691 chip_dma = config & IRCC_INTERFACE_DMA_MASK;
692 chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
693
694 self->io.fir_base = fir_base;
695 self->io.sir_base = sir_base;
696 self->io.fir_ext = SMSC_IRCC2_FIR_CHIP_IO_EXTENT;
697 self->io.sir_ext = SMSC_IRCC2_SIR_CHIP_IO_EXTENT;
698 self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE;
699 self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED;
700
701 if (irq != IRQ_INVAL) {
702 if (irq != chip_irq)
703 IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n",
704 driver_name, chip_irq, irq);
705 self->io.irq = irq;
706 } else
707 self->io.irq = chip_irq;
708
709 if (dma != DMA_INVAL) {
710 if (dma != chip_dma)
711 IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n",
712 driver_name, chip_dma, dma);
713 self->io.dma = dma;
714 } else
715 self->io.dma = chip_dma;
716
717 }
718
719 /*
720 * Function smsc_ircc_setup_qos(self)
721 *
722 * Setup qos
723 *
724 */
725 static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self)
726 {
727 /* Initialize QoS for this device */
728 irda_init_max_qos_capabilies(&self->qos);
729
730 self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
731 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
732
733 self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME;
734 self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE;
735 irda_qos_bits_to_value(&self->qos);
736 }
737
738 /*
739 * Function smsc_ircc_init_chip(self)
740 *
741 * Init chip
742 *
743 */
744 static void smsc_ircc_init_chip(struct smsc_ircc_cb *self)
745 {
746 int iobase = self->io.fir_base;
747
748 register_bank(iobase, 0);
749 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
750 outb(0x00, iobase + IRCC_MASTER);
751
752 register_bank(iobase, 1);
753 outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A),
754 iobase + IRCC_SCE_CFGA);
755
756 #ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */
757 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
758 iobase + IRCC_SCE_CFGB);
759 #else
760 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
761 iobase + IRCC_SCE_CFGB);
762 #endif
763 (void) inb(iobase + IRCC_FIFO_THRESHOLD);
764 outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD);
765
766 register_bank(iobase, 4);
767 outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL);
768
769 register_bank(iobase, 0);
770 outb(0, iobase + IRCC_LCR_A);
771
772 smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
773
774 /* Power on device */
775 outb(0x00, iobase + IRCC_MASTER);
776 }
777
778 /*
779 * Function smsc_ircc_net_ioctl (dev, rq, cmd)
780 *
781 * Process IOCTL commands for this device
782 *
783 */
784 static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
785 {
786 struct if_irda_req *irq = (struct if_irda_req *) rq;
787 struct smsc_ircc_cb *self;
788 unsigned long flags;
789 int ret = 0;
790
791 IRDA_ASSERT(dev != NULL, return -1;);
792
793 self = netdev_priv(dev);
794
795 IRDA_ASSERT(self != NULL, return -1;);
796
797 IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __FUNCTION__, dev->name, cmd);
798
799 switch (cmd) {
800 case SIOCSBANDWIDTH: /* Set bandwidth */
801 if (!capable(CAP_NET_ADMIN))
802 ret = -EPERM;
803 else {
804 /* Make sure we are the only one touching
805 * self->io.speed and the hardware - Jean II */
806 spin_lock_irqsave(&self->lock, flags);
807 smsc_ircc_change_speed(self, irq->ifr_baudrate);
808 spin_unlock_irqrestore(&self->lock, flags);
809 }
810 break;
811 case SIOCSMEDIABUSY: /* Set media busy */
812 if (!capable(CAP_NET_ADMIN)) {
813 ret = -EPERM;
814 break;
815 }
816
817 irda_device_set_media_busy(self->netdev, TRUE);
818 break;
819 case SIOCGRECEIVING: /* Check if we are receiving right now */
820 irq->ifr_receiving = smsc_ircc_is_receiving(self);
821 break;
822 #if 0
823 case SIOCSDTRRTS:
824 if (!capable(CAP_NET_ADMIN)) {
825 ret = -EPERM;
826 break;
827 }
828 smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts);
829 break;
830 #endif
831 default:
832 ret = -EOPNOTSUPP;
833 }
834
835 return ret;
836 }
837
838 static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev)
839 {
840 struct smsc_ircc_cb *self = netdev_priv(dev);
841
842 return &self->stats;
843 }
844
845 #if SMSC_IRCC2_C_NET_TIMEOUT
846 /*
847 * Function smsc_ircc_timeout (struct net_device *dev)
848 *
849 * The networking timeout management.
850 *
851 */
852
853 static void smsc_ircc_timeout(struct net_device *dev)
854 {
855 struct smsc_ircc_cb *self = netdev_priv(dev);
856 unsigned long flags;
857
858 IRDA_WARNING("%s: transmit timed out, changing speed to: %d\n",
859 dev->name, self->io.speed);
860 spin_lock_irqsave(&self->lock, flags);
861 smsc_ircc_sir_start(self);
862 smsc_ircc_change_speed(self, self->io.speed);
863 dev->trans_start = jiffies;
864 netif_wake_queue(dev);
865 spin_unlock_irqrestore(&self->lock, flags);
866 }
867 #endif
868
869 /*
870 * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev)
871 *
872 * Transmits the current frame until FIFO is full, then
873 * waits until the next transmit interrupt, and continues until the
874 * frame is transmitted.
875 */
876 int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev)
877 {
878 struct smsc_ircc_cb *self;
879 unsigned long flags;
880 s32 speed;
881
882 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
883
884 IRDA_ASSERT(dev != NULL, return 0;);
885
886 self = netdev_priv(dev);
887 IRDA_ASSERT(self != NULL, return 0;);
888
889 netif_stop_queue(dev);
890
891 /* Make sure test of self->io.speed & speed change are atomic */
892 spin_lock_irqsave(&self->lock, flags);
893
894 /* Check if we need to change the speed */
895 speed = irda_get_next_speed(skb);
896 if (speed != self->io.speed && speed != -1) {
897 /* Check for empty frame */
898 if (!skb->len) {
899 /*
900 * We send frames one by one in SIR mode (no
901 * pipelining), so at this point, if we were sending
902 * a previous frame, we just received the interrupt
903 * telling us it is finished (UART_IIR_THRI).
904 * Therefore, waiting for the transmitter to really
905 * finish draining the fifo won't take too long.
906 * And the interrupt handler is not expected to run.
907 * - Jean II */
908 smsc_ircc_sir_wait_hw_transmitter_finish(self);
909 smsc_ircc_change_speed(self, speed);
910 spin_unlock_irqrestore(&self->lock, flags);
911 dev_kfree_skb(skb);
912 return 0;
913 }
914 self->new_speed = speed;
915 }
916
917 /* Init tx buffer */
918 self->tx_buff.data = self->tx_buff.head;
919
920 /* Copy skb to tx_buff while wrapping, stuffing and making CRC */
921 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
922 self->tx_buff.truesize);
923
924 self->stats.tx_bytes += self->tx_buff.len;
925
926 /* Turn on transmit finished interrupt. Will fire immediately! */
927 outb(UART_IER_THRI, self->io.sir_base + UART_IER);
928
929 spin_unlock_irqrestore(&self->lock, flags);
930
931 dev_kfree_skb(skb);
932
933 return 0;
934 }
935
936 /*
937 * Function smsc_ircc_set_fir_speed (self, baud)
938 *
939 * Change the speed of the device
940 *
941 */
942 static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed)
943 {
944 int fir_base, ir_mode, ctrl, fast;
945
946 IRDA_ASSERT(self != NULL, return;);
947 fir_base = self->io.fir_base;
948
949 self->io.speed = speed;
950
951 switch (speed) {
952 default:
953 case 576000:
954 ir_mode = IRCC_CFGA_IRDA_HDLC;
955 ctrl = IRCC_CRC;
956 fast = 0;
957 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __FUNCTION__);
958 break;
959 case 1152000:
960 ir_mode = IRCC_CFGA_IRDA_HDLC;
961 ctrl = IRCC_1152 | IRCC_CRC;
962 fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA;
963 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n",
964 __FUNCTION__);
965 break;
966 case 4000000:
967 ir_mode = IRCC_CFGA_IRDA_4PPM;
968 ctrl = IRCC_CRC;
969 fast = IRCC_LCR_A_FAST;
970 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n",
971 __FUNCTION__);
972 break;
973 }
974 #if 0
975 Now in tranceiver!
976 /* This causes an interrupt */
977 register_bank(fir_base, 0);
978 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast, fir_base + IRCC_LCR_A);
979 #endif
980
981 register_bank(fir_base, 1);
982 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA);
983
984 register_bank(fir_base, 4);
985 outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL);
986 }
987
988 /*
989 * Function smsc_ircc_fir_start(self)
990 *
991 * Change the speed of the device
992 *
993 */
994 static void smsc_ircc_fir_start(struct smsc_ircc_cb *self)
995 {
996 struct net_device *dev;
997 int fir_base;
998
999 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1000
1001 IRDA_ASSERT(self != NULL, return;);
1002 dev = self->netdev;
1003 IRDA_ASSERT(dev != NULL, return;);
1004
1005 fir_base = self->io.fir_base;
1006
1007 /* Reset everything */
1008
1009 /* Install FIR transmit handler */
1010 dev->hard_start_xmit = smsc_ircc_hard_xmit_fir;
1011
1012 /* Clear FIFO */
1013 outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A);
1014
1015 /* Enable interrupt */
1016 /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/
1017
1018 register_bank(fir_base, 1);
1019
1020 /* Select the TX/RX interface */
1021 #ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */
1022 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
1023 fir_base + IRCC_SCE_CFGB);
1024 #else
1025 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
1026 fir_base + IRCC_SCE_CFGB);
1027 #endif
1028 (void) inb(fir_base + IRCC_FIFO_THRESHOLD);
1029
1030 /* Enable SCE interrupts */
1031 outb(0, fir_base + IRCC_MASTER);
1032 register_bank(fir_base, 0);
1033 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER);
1034 outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER);
1035 }
1036
1037 /*
1038 * Function smsc_ircc_fir_stop(self, baud)
1039 *
1040 * Change the speed of the device
1041 *
1042 */
1043 static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self)
1044 {
1045 int fir_base;
1046
1047 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1048
1049 IRDA_ASSERT(self != NULL, return;);
1050
1051 fir_base = self->io.fir_base;
1052 register_bank(fir_base, 0);
1053 /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/
1054 outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B);
1055 }
1056
1057
1058 /*
1059 * Function smsc_ircc_change_speed(self, baud)
1060 *
1061 * Change the speed of the device
1062 *
1063 * This function *must* be called with spinlock held, because it may
1064 * be called from the irq handler. - Jean II
1065 */
1066 static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed)
1067 {
1068 struct net_device *dev;
1069 int last_speed_was_sir;
1070
1071 IRDA_DEBUG(0, "%s() changing speed to: %d\n", __FUNCTION__, speed);
1072
1073 IRDA_ASSERT(self != NULL, return;);
1074 dev = self->netdev;
1075
1076 last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED;
1077
1078 #if 0
1079 /* Temp Hack */
1080 speed= 1152000;
1081 self->io.speed = speed;
1082 last_speed_was_sir = 0;
1083 smsc_ircc_fir_start(self);
1084 #endif
1085
1086 if (self->io.speed == 0)
1087 smsc_ircc_sir_start(self);
1088
1089 #if 0
1090 if (!last_speed_was_sir) speed = self->io.speed;
1091 #endif
1092
1093 if (self->io.speed != speed)
1094 smsc_ircc_set_transceiver_for_speed(self, speed);
1095
1096 self->io.speed = speed;
1097
1098 if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1099 if (!last_speed_was_sir) {
1100 smsc_ircc_fir_stop(self);
1101 smsc_ircc_sir_start(self);
1102 }
1103 smsc_ircc_set_sir_speed(self, speed);
1104 } else {
1105 if (last_speed_was_sir) {
1106 #if SMSC_IRCC2_C_SIR_STOP
1107 smsc_ircc_sir_stop(self);
1108 #endif
1109 smsc_ircc_fir_start(self);
1110 }
1111 smsc_ircc_set_fir_speed(self, speed);
1112
1113 #if 0
1114 self->tx_buff.len = 10;
1115 self->tx_buff.data = self->tx_buff.head;
1116
1117 smsc_ircc_dma_xmit(self, 4000);
1118 #endif
1119 /* Be ready for incoming frames */
1120 smsc_ircc_dma_receive(self);
1121 }
1122
1123 netif_wake_queue(dev);
1124 }
1125
1126 /*
1127 * Function smsc_ircc_set_sir_speed (self, speed)
1128 *
1129 * Set speed of IrDA port to specified baudrate
1130 *
1131 */
1132 void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, __u32 speed)
1133 {
1134 int iobase;
1135 int fcr; /* FIFO control reg */
1136 int lcr; /* Line control reg */
1137 int divisor;
1138
1139 IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __FUNCTION__, speed);
1140
1141 IRDA_ASSERT(self != NULL, return;);
1142 iobase = self->io.sir_base;
1143
1144 /* Update accounting for new speed */
1145 self->io.speed = speed;
1146
1147 /* Turn off interrupts */
1148 outb(0, iobase + UART_IER);
1149
1150 divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed;
1151
1152 fcr = UART_FCR_ENABLE_FIFO;
1153
1154 /*
1155 * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and
1156 * almost 1,7 ms at 19200 bps. At speeds above that we can just forget
1157 * about this timeout since it will always be fast enough.
1158 */
1159 fcr |= self->io.speed < 38400 ?
1160 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
1161
1162 /* IrDA ports use 8N1 */
1163 lcr = UART_LCR_WLEN8;
1164
1165 outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */
1166 outb(divisor & 0xff, iobase + UART_DLL); /* Set speed */
1167 outb(divisor >> 8, iobase + UART_DLM);
1168 outb(lcr, iobase + UART_LCR); /* Set 8N1 */
1169 outb(fcr, iobase + UART_FCR); /* Enable FIFO's */
1170
1171 /* Turn on interrups */
1172 outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER);
1173
1174 IRDA_DEBUG(2, "%s() speed changed to: %d\n", __FUNCTION__, speed);
1175 }
1176
1177
1178 /*
1179 * Function smsc_ircc_hard_xmit_fir (skb, dev)
1180 *
1181 * Transmit the frame!
1182 *
1183 */
1184 static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev)
1185 {
1186 struct smsc_ircc_cb *self;
1187 unsigned long flags;
1188 s32 speed;
1189 int mtt;
1190
1191 IRDA_ASSERT(dev != NULL, return 0;);
1192 self = netdev_priv(dev);
1193 IRDA_ASSERT(self != NULL, return 0;);
1194
1195 netif_stop_queue(dev);
1196
1197 /* Make sure test of self->io.speed & speed change are atomic */
1198 spin_lock_irqsave(&self->lock, flags);
1199
1200 /* Check if we need to change the speed after this frame */
1201 speed = irda_get_next_speed(skb);
1202 if (speed != self->io.speed && speed != -1) {
1203 /* Check for empty frame */
1204 if (!skb->len) {
1205 /* Note : you should make sure that speed changes
1206 * are not going to corrupt any outgoing frame.
1207 * Look at nsc-ircc for the gory details - Jean II */
1208 smsc_ircc_change_speed(self, speed);
1209 spin_unlock_irqrestore(&self->lock, flags);
1210 dev_kfree_skb(skb);
1211 return 0;
1212 }
1213
1214 self->new_speed = speed;
1215 }
1216
1217 skb_copy_from_linear_data(skb, self->tx_buff.head, skb->len);
1218
1219 self->tx_buff.len = skb->len;
1220 self->tx_buff.data = self->tx_buff.head;
1221
1222 mtt = irda_get_mtt(skb);
1223 if (mtt) {
1224 int bofs;
1225
1226 /*
1227 * Compute how many BOFs (STA or PA's) we need to waste the
1228 * min turn time given the speed of the link.
1229 */
1230 bofs = mtt * (self->io.speed / 1000) / 8000;
1231 if (bofs > 4095)
1232 bofs = 4095;
1233
1234 smsc_ircc_dma_xmit(self, bofs);
1235 } else {
1236 /* Transmit frame */
1237 smsc_ircc_dma_xmit(self, 0);
1238 }
1239
1240 spin_unlock_irqrestore(&self->lock, flags);
1241 dev_kfree_skb(skb);
1242
1243 return 0;
1244 }
1245
1246 /*
1247 * Function smsc_ircc_dma_xmit (self, bofs)
1248 *
1249 * Transmit data using DMA
1250 *
1251 */
1252 static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs)
1253 {
1254 int iobase = self->io.fir_base;
1255 u8 ctrl;
1256
1257 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1258 #if 1
1259 /* Disable Rx */
1260 register_bank(iobase, 0);
1261 outb(0x00, iobase + IRCC_LCR_B);
1262 #endif
1263 register_bank(iobase, 1);
1264 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1265 iobase + IRCC_SCE_CFGB);
1266
1267 self->io.direction = IO_XMIT;
1268
1269 /* Set BOF additional count for generating the min turn time */
1270 register_bank(iobase, 4);
1271 outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO);
1272 ctrl = inb(iobase + IRCC_CONTROL) & 0xf0;
1273 outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI);
1274
1275 /* Set max Tx frame size */
1276 outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI);
1277 outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO);
1278
1279 /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/
1280
1281 /* Enable burst mode chip Tx DMA */
1282 register_bank(iobase, 1);
1283 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1284 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1285
1286 /* Setup DMA controller (must be done after enabling chip DMA) */
1287 irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
1288 DMA_TX_MODE);
1289
1290 /* Enable interrupt */
1291
1292 register_bank(iobase, 0);
1293 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1294 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1295
1296 /* Enable transmit */
1297 outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B);
1298 }
1299
1300 /*
1301 * Function smsc_ircc_dma_xmit_complete (self)
1302 *
1303 * The transfer of a frame in finished. This function will only be called
1304 * by the interrupt handler
1305 *
1306 */
1307 static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self)
1308 {
1309 int iobase = self->io.fir_base;
1310
1311 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1312 #if 0
1313 /* Disable Tx */
1314 register_bank(iobase, 0);
1315 outb(0x00, iobase + IRCC_LCR_B);
1316 #endif
1317 register_bank(iobase, 1);
1318 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1319 iobase + IRCC_SCE_CFGB);
1320
1321 /* Check for underrun! */
1322 register_bank(iobase, 0);
1323 if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) {
1324 self->stats.tx_errors++;
1325 self->stats.tx_fifo_errors++;
1326
1327 /* Reset error condition */
1328 register_bank(iobase, 0);
1329 outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER);
1330 outb(0x00, iobase + IRCC_MASTER);
1331 } else {
1332 self->stats.tx_packets++;
1333 self->stats.tx_bytes += self->tx_buff.len;
1334 }
1335
1336 /* Check if it's time to change the speed */
1337 if (self->new_speed) {
1338 smsc_ircc_change_speed(self, self->new_speed);
1339 self->new_speed = 0;
1340 }
1341
1342 netif_wake_queue(self->netdev);
1343 }
1344
1345 /*
1346 * Function smsc_ircc_dma_receive(self)
1347 *
1348 * Get ready for receiving a frame. The device will initiate a DMA
1349 * if it starts to receive a frame.
1350 *
1351 */
1352 static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self)
1353 {
1354 int iobase = self->io.fir_base;
1355 #if 0
1356 /* Turn off chip DMA */
1357 register_bank(iobase, 1);
1358 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1359 iobase + IRCC_SCE_CFGB);
1360 #endif
1361
1362 /* Disable Tx */
1363 register_bank(iobase, 0);
1364 outb(0x00, iobase + IRCC_LCR_B);
1365
1366 /* Turn off chip DMA */
1367 register_bank(iobase, 1);
1368 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1369 iobase + IRCC_SCE_CFGB);
1370
1371 self->io.direction = IO_RECV;
1372 self->rx_buff.data = self->rx_buff.head;
1373
1374 /* Set max Rx frame size */
1375 register_bank(iobase, 4);
1376 outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI);
1377 outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO);
1378
1379 /* Setup DMA controller */
1380 irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
1381 DMA_RX_MODE);
1382
1383 /* Enable burst mode chip Rx DMA */
1384 register_bank(iobase, 1);
1385 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1386 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1387
1388 /* Enable interrupt */
1389 register_bank(iobase, 0);
1390 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1391 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1392
1393 /* Enable receiver */
1394 register_bank(iobase, 0);
1395 outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE,
1396 iobase + IRCC_LCR_B);
1397
1398 return 0;
1399 }
1400
1401 /*
1402 * Function smsc_ircc_dma_receive_complete(self)
1403 *
1404 * Finished with receiving frames
1405 *
1406 */
1407 static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self)
1408 {
1409 struct sk_buff *skb;
1410 int len, msgcnt, lsr;
1411 int iobase = self->io.fir_base;
1412
1413 register_bank(iobase, 0);
1414
1415 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1416 #if 0
1417 /* Disable Rx */
1418 register_bank(iobase, 0);
1419 outb(0x00, iobase + IRCC_LCR_B);
1420 #endif
1421 register_bank(iobase, 0);
1422 outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR);
1423 lsr= inb(iobase + IRCC_LSR);
1424 msgcnt = inb(iobase + IRCC_LCR_B) & 0x08;
1425
1426 IRDA_DEBUG(2, "%s: dma count = %d\n", __FUNCTION__,
1427 get_dma_residue(self->io.dma));
1428
1429 len = self->rx_buff.truesize - get_dma_residue(self->io.dma);
1430
1431 /* Look for errors */
1432 if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) {
1433 self->stats.rx_errors++;
1434 if (lsr & IRCC_LSR_FRAME_ERROR)
1435 self->stats.rx_frame_errors++;
1436 if (lsr & IRCC_LSR_CRC_ERROR)
1437 self->stats.rx_crc_errors++;
1438 if (lsr & IRCC_LSR_SIZE_ERROR)
1439 self->stats.rx_length_errors++;
1440 if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN))
1441 self->stats.rx_length_errors++;
1442 return;
1443 }
1444
1445 /* Remove CRC */
1446 len -= self->io.speed < 4000000 ? 2 : 4;
1447
1448 if (len < 2 || len > 2050) {
1449 IRDA_WARNING("%s(), bogus len=%d\n", __FUNCTION__, len);
1450 return;
1451 }
1452 IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __FUNCTION__, msgcnt, len);
1453
1454 skb = dev_alloc_skb(len + 1);
1455 if (!skb) {
1456 IRDA_WARNING("%s(), memory squeeze, dropping frame.\n",
1457 __FUNCTION__);
1458 return;
1459 }
1460 /* Make sure IP header gets aligned */
1461 skb_reserve(skb, 1);
1462
1463 memcpy(skb_put(skb, len), self->rx_buff.data, len);
1464 self->stats.rx_packets++;
1465 self->stats.rx_bytes += len;
1466
1467 skb->dev = self->netdev;
1468 skb_reset_mac_header(skb);
1469 skb->protocol = htons(ETH_P_IRDA);
1470 netif_rx(skb);
1471 }
1472
1473 /*
1474 * Function smsc_ircc_sir_receive (self)
1475 *
1476 * Receive one frame from the infrared port
1477 *
1478 */
1479 static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self)
1480 {
1481 int boguscount = 0;
1482 int iobase;
1483
1484 IRDA_ASSERT(self != NULL, return;);
1485
1486 iobase = self->io.sir_base;
1487
1488 /*
1489 * Receive all characters in Rx FIFO, unwrap and unstuff them.
1490 * async_unwrap_char will deliver all found frames
1491 */
1492 do {
1493 async_unwrap_char(self->netdev, &self->stats, &self->rx_buff,
1494 inb(iobase + UART_RX));
1495
1496 /* Make sure we don't stay here to long */
1497 if (boguscount++ > 32) {
1498 IRDA_DEBUG(2, "%s(), breaking!\n", __FUNCTION__);
1499 break;
1500 }
1501 } while (inb(iobase + UART_LSR) & UART_LSR_DR);
1502 }
1503
1504
1505 /*
1506 * Function smsc_ircc_interrupt (irq, dev_id, regs)
1507 *
1508 * An interrupt from the chip has arrived. Time to do some work
1509 *
1510 */
1511 static irqreturn_t smsc_ircc_interrupt(int dummy, void *dev_id)
1512 {
1513 struct net_device *dev = dev_id;
1514 struct smsc_ircc_cb *self = netdev_priv(dev);
1515 int iobase, iir, lcra, lsr;
1516 irqreturn_t ret = IRQ_NONE;
1517
1518 /* Serialise the interrupt handler in various CPUs, stop Tx path */
1519 spin_lock(&self->lock);
1520
1521 /* Check if we should use the SIR interrupt handler */
1522 if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1523 ret = smsc_ircc_interrupt_sir(dev);
1524 goto irq_ret_unlock;
1525 }
1526
1527 iobase = self->io.fir_base;
1528
1529 register_bank(iobase, 0);
1530 iir = inb(iobase + IRCC_IIR);
1531 if (iir == 0)
1532 goto irq_ret_unlock;
1533 ret = IRQ_HANDLED;
1534
1535 /* Disable interrupts */
1536 outb(0, iobase + IRCC_IER);
1537 lcra = inb(iobase + IRCC_LCR_A);
1538 lsr = inb(iobase + IRCC_LSR);
1539
1540 IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __FUNCTION__, iir);
1541
1542 if (iir & IRCC_IIR_EOM) {
1543 if (self->io.direction == IO_RECV)
1544 smsc_ircc_dma_receive_complete(self);
1545 else
1546 smsc_ircc_dma_xmit_complete(self);
1547
1548 smsc_ircc_dma_receive(self);
1549 }
1550
1551 if (iir & IRCC_IIR_ACTIVE_FRAME) {
1552 /*printk(KERN_WARNING "%s(): Active Frame\n", __FUNCTION__);*/
1553 }
1554
1555 /* Enable interrupts again */
1556
1557 register_bank(iobase, 0);
1558 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1559
1560 irq_ret_unlock:
1561 spin_unlock(&self->lock);
1562
1563 return ret;
1564 }
1565
1566 /*
1567 * Function irport_interrupt_sir (irq, dev_id)
1568 *
1569 * Interrupt handler for SIR modes
1570 */
1571 static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev)
1572 {
1573 struct smsc_ircc_cb *self = netdev_priv(dev);
1574 int boguscount = 0;
1575 int iobase;
1576 int iir, lsr;
1577
1578 /* Already locked comming here in smsc_ircc_interrupt() */
1579 /*spin_lock(&self->lock);*/
1580
1581 iobase = self->io.sir_base;
1582
1583 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1584 if (iir == 0)
1585 return IRQ_NONE;
1586 while (iir) {
1587 /* Clear interrupt */
1588 lsr = inb(iobase + UART_LSR);
1589
1590 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
1591 __FUNCTION__, iir, lsr, iobase);
1592
1593 switch (iir) {
1594 case UART_IIR_RLSI:
1595 IRDA_DEBUG(2, "%s(), RLSI\n", __FUNCTION__);
1596 break;
1597 case UART_IIR_RDI:
1598 /* Receive interrupt */
1599 smsc_ircc_sir_receive(self);
1600 break;
1601 case UART_IIR_THRI:
1602 if (lsr & UART_LSR_THRE)
1603 /* Transmitter ready for data */
1604 smsc_ircc_sir_write_wakeup(self);
1605 break;
1606 default:
1607 IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n",
1608 __FUNCTION__, iir);
1609 break;
1610 }
1611
1612 /* Make sure we don't stay here to long */
1613 if (boguscount++ > 100)
1614 break;
1615
1616 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1617 }
1618 /*spin_unlock(&self->lock);*/
1619 return IRQ_HANDLED;
1620 }
1621
1622
1623 #if 0 /* unused */
1624 /*
1625 * Function ircc_is_receiving (self)
1626 *
1627 * Return TRUE is we are currently receiving a frame
1628 *
1629 */
1630 static int ircc_is_receiving(struct smsc_ircc_cb *self)
1631 {
1632 int status = FALSE;
1633 /* int iobase; */
1634
1635 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1636
1637 IRDA_ASSERT(self != NULL, return FALSE;);
1638
1639 IRDA_DEBUG(0, "%s: dma count = %d\n", __FUNCTION__,
1640 get_dma_residue(self->io.dma));
1641
1642 status = (self->rx_buff.state != OUTSIDE_FRAME);
1643
1644 return status;
1645 }
1646 #endif /* unused */
1647
1648 static int smsc_ircc_request_irq(struct smsc_ircc_cb *self)
1649 {
1650 int error;
1651
1652 error = request_irq(self->io.irq, smsc_ircc_interrupt, 0,
1653 self->netdev->name, self->netdev);
1654 if (error)
1655 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d, err=%d\n",
1656 __FUNCTION__, self->io.irq, error);
1657
1658 return error;
1659 }
1660
1661 static void smsc_ircc_start_interrupts(struct smsc_ircc_cb *self)
1662 {
1663 unsigned long flags;
1664
1665 spin_lock_irqsave(&self->lock, flags);
1666
1667 self->io.speed = 0;
1668 smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
1669
1670 spin_unlock_irqrestore(&self->lock, flags);
1671 }
1672
1673 static void smsc_ircc_stop_interrupts(struct smsc_ircc_cb *self)
1674 {
1675 int iobase = self->io.fir_base;
1676 unsigned long flags;
1677
1678 spin_lock_irqsave(&self->lock, flags);
1679
1680 register_bank(iobase, 0);
1681 outb(0, iobase + IRCC_IER);
1682 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
1683 outb(0x00, iobase + IRCC_MASTER);
1684
1685 spin_unlock_irqrestore(&self->lock, flags);
1686 }
1687
1688
1689 /*
1690 * Function smsc_ircc_net_open (dev)
1691 *
1692 * Start the device
1693 *
1694 */
1695 static int smsc_ircc_net_open(struct net_device *dev)
1696 {
1697 struct smsc_ircc_cb *self;
1698 char hwname[16];
1699
1700 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1701
1702 IRDA_ASSERT(dev != NULL, return -1;);
1703 self = netdev_priv(dev);
1704 IRDA_ASSERT(self != NULL, return 0;);
1705
1706 if (self->io.suspended) {
1707 IRDA_DEBUG(0, "%s(), device is suspended\n", __FUNCTION__);
1708 return -EAGAIN;
1709 }
1710
1711 if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name,
1712 (void *) dev)) {
1713 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n",
1714 __FUNCTION__, self->io.irq);
1715 return -EAGAIN;
1716 }
1717
1718 smsc_ircc_start_interrupts(self);
1719
1720 /* Give self a hardware name */
1721 /* It would be cool to offer the chip revision here - Jean II */
1722 sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base);
1723
1724 /*
1725 * Open new IrLAP layer instance, now that everything should be
1726 * initialized properly
1727 */
1728 self->irlap = irlap_open(dev, &self->qos, hwname);
1729
1730 /*
1731 * Always allocate the DMA channel after the IRQ,
1732 * and clean up on failure.
1733 */
1734 if (request_dma(self->io.dma, dev->name)) {
1735 smsc_ircc_net_close(dev);
1736
1737 IRDA_WARNING("%s(), unable to allocate DMA=%d\n",
1738 __FUNCTION__, self->io.dma);
1739 return -EAGAIN;
1740 }
1741
1742 netif_start_queue(dev);
1743
1744 return 0;
1745 }
1746
1747 /*
1748 * Function smsc_ircc_net_close (dev)
1749 *
1750 * Stop the device
1751 *
1752 */
1753 static int smsc_ircc_net_close(struct net_device *dev)
1754 {
1755 struct smsc_ircc_cb *self;
1756
1757 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1758
1759 IRDA_ASSERT(dev != NULL, return -1;);
1760 self = netdev_priv(dev);
1761 IRDA_ASSERT(self != NULL, return 0;);
1762
1763 /* Stop device */
1764 netif_stop_queue(dev);
1765
1766 /* Stop and remove instance of IrLAP */
1767 if (self->irlap)
1768 irlap_close(self->irlap);
1769 self->irlap = NULL;
1770
1771 smsc_ircc_stop_interrupts(self);
1772
1773 /* if we are called from smsc_ircc_resume we don't have IRQ reserved */
1774 if (!self->io.suspended)
1775 free_irq(self->io.irq, dev);
1776
1777 disable_dma(self->io.dma);
1778 free_dma(self->io.dma);
1779
1780 return 0;
1781 }
1782
1783 static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state)
1784 {
1785 struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1786
1787 if (!self->io.suspended) {
1788 IRDA_DEBUG(1, "%s, Suspending\n", driver_name);
1789
1790 rtnl_lock();
1791 if (netif_running(self->netdev)) {
1792 netif_device_detach(self->netdev);
1793 smsc_ircc_stop_interrupts(self);
1794 free_irq(self->io.irq, self->netdev);
1795 disable_dma(self->io.dma);
1796 }
1797 self->io.suspended = 1;
1798 rtnl_unlock();
1799 }
1800
1801 return 0;
1802 }
1803
1804 static int smsc_ircc_resume(struct platform_device *dev)
1805 {
1806 struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1807
1808 if (self->io.suspended) {
1809 IRDA_DEBUG(1, "%s, Waking up\n", driver_name);
1810
1811 rtnl_lock();
1812 smsc_ircc_init_chip(self);
1813 if (netif_running(self->netdev)) {
1814 if (smsc_ircc_request_irq(self)) {
1815 /*
1816 * Don't fail resume process, just kill this
1817 * network interface
1818 */
1819 unregister_netdevice(self->netdev);
1820 } else {
1821 enable_dma(self->io.dma);
1822 smsc_ircc_start_interrupts(self);
1823 netif_device_attach(self->netdev);
1824 }
1825 }
1826 self->io.suspended = 0;
1827 rtnl_unlock();
1828 }
1829 return 0;
1830 }
1831
1832 /*
1833 * Function smsc_ircc_close (self)
1834 *
1835 * Close driver instance
1836 *
1837 */
1838 static int __exit smsc_ircc_close(struct smsc_ircc_cb *self)
1839 {
1840 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1841
1842 IRDA_ASSERT(self != NULL, return -1;);
1843
1844 platform_device_unregister(self->pldev);
1845
1846 /* Remove netdevice */
1847 unregister_netdev(self->netdev);
1848
1849 smsc_ircc_stop_interrupts(self);
1850
1851 /* Release the PORTS that this driver is using */
1852 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__,
1853 self->io.fir_base);
1854
1855 release_region(self->io.fir_base, self->io.fir_ext);
1856
1857 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__,
1858 self->io.sir_base);
1859
1860 release_region(self->io.sir_base, self->io.sir_ext);
1861
1862 if (self->tx_buff.head)
1863 dma_free_coherent(NULL, self->tx_buff.truesize,
1864 self->tx_buff.head, self->tx_buff_dma);
1865
1866 if (self->rx_buff.head)
1867 dma_free_coherent(NULL, self->rx_buff.truesize,
1868 self->rx_buff.head, self->rx_buff_dma);
1869
1870 free_netdev(self->netdev);
1871
1872 return 0;
1873 }
1874
1875 static void __exit smsc_ircc_cleanup(void)
1876 {
1877 int i;
1878
1879 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1880
1881 for (i = 0; i < 2; i++) {
1882 if (dev_self[i])
1883 smsc_ircc_close(dev_self[i]);
1884 }
1885
1886 if (pnp_driver_registered)
1887 pnp_unregister_driver(&smsc_ircc_pnp_driver);
1888
1889 platform_driver_unregister(&smsc_ircc_driver);
1890 }
1891
1892 /*
1893 * Start SIR operations
1894 *
1895 * This function *must* be called with spinlock held, because it may
1896 * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II
1897 */
1898 void smsc_ircc_sir_start(struct smsc_ircc_cb *self)
1899 {
1900 struct net_device *dev;
1901 int fir_base, sir_base;
1902
1903 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1904
1905 IRDA_ASSERT(self != NULL, return;);
1906 dev = self->netdev;
1907 IRDA_ASSERT(dev != NULL, return;);
1908 dev->hard_start_xmit = &smsc_ircc_hard_xmit_sir;
1909
1910 fir_base = self->io.fir_base;
1911 sir_base = self->io.sir_base;
1912
1913 /* Reset everything */
1914 outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);
1915
1916 #if SMSC_IRCC2_C_SIR_STOP
1917 /*smsc_ircc_sir_stop(self);*/
1918 #endif
1919
1920 register_bank(fir_base, 1);
1921 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA);
1922
1923 /* Initialize UART */
1924 outb(UART_LCR_WLEN8, sir_base + UART_LCR); /* Reset DLAB */
1925 outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR);
1926
1927 /* Turn on interrups */
1928 outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER);
1929
1930 IRDA_DEBUG(3, "%s() - exit\n", __FUNCTION__);
1931
1932 outb(0x00, fir_base + IRCC_MASTER);
1933 }
1934
1935 #if SMSC_IRCC2_C_SIR_STOP
1936 void smsc_ircc_sir_stop(struct smsc_ircc_cb *self)
1937 {
1938 int iobase;
1939
1940 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1941 iobase = self->io.sir_base;
1942
1943 /* Reset UART */
1944 outb(0, iobase + UART_MCR);
1945
1946 /* Turn off interrupts */
1947 outb(0, iobase + UART_IER);
1948 }
1949 #endif
1950
1951 /*
1952 * Function smsc_sir_write_wakeup (self)
1953 *
1954 * Called by the SIR interrupt handler when there's room for more data.
1955 * If we have more packets to send, we send them here.
1956 *
1957 */
1958 static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self)
1959 {
1960 int actual = 0;
1961 int iobase;
1962 int fcr;
1963
1964 IRDA_ASSERT(self != NULL, return;);
1965
1966 IRDA_DEBUG(4, "%s\n", __FUNCTION__);
1967
1968 iobase = self->io.sir_base;
1969
1970 /* Finished with frame? */
1971 if (self->tx_buff.len > 0) {
1972 /* Write data left in transmit buffer */
1973 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size,
1974 self->tx_buff.data, self->tx_buff.len);
1975 self->tx_buff.data += actual;
1976 self->tx_buff.len -= actual;
1977 } else {
1978
1979 /*if (self->tx_buff.len ==0) {*/
1980
1981 /*
1982 * Now serial buffer is almost free & we can start
1983 * transmission of another packet. But first we must check
1984 * if we need to change the speed of the hardware
1985 */
1986 if (self->new_speed) {
1987 IRDA_DEBUG(5, "%s(), Changing speed to %d.\n",
1988 __FUNCTION__, self->new_speed);
1989 smsc_ircc_sir_wait_hw_transmitter_finish(self);
1990 smsc_ircc_change_speed(self, self->new_speed);
1991 self->new_speed = 0;
1992 } else {
1993 /* Tell network layer that we want more frames */
1994 netif_wake_queue(self->netdev);
1995 }
1996 self->stats.tx_packets++;
1997
1998 if (self->io.speed <= 115200) {
1999 /*
2000 * Reset Rx FIFO to make sure that all reflected transmit data
2001 * is discarded. This is needed for half duplex operation
2002 */
2003 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR;
2004 fcr |= self->io.speed < 38400 ?
2005 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
2006
2007 outb(fcr, iobase + UART_FCR);
2008
2009 /* Turn on receive interrupts */
2010 outb(UART_IER_RDI, iobase + UART_IER);
2011 }
2012 }
2013 }
2014
2015 /*
2016 * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len)
2017 *
2018 * Fill Tx FIFO with transmit data
2019 *
2020 */
2021 static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
2022 {
2023 int actual = 0;
2024
2025 /* Tx FIFO should be empty! */
2026 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) {
2027 IRDA_WARNING("%s(), failed, fifo not empty!\n", __FUNCTION__);
2028 return 0;
2029 }
2030
2031 /* Fill FIFO with current frame */
2032 while (fifo_size-- > 0 && actual < len) {
2033 /* Transmit next byte */
2034 outb(buf[actual], iobase + UART_TX);
2035 actual++;
2036 }
2037 return actual;
2038 }
2039
2040 /*
2041 * Function smsc_ircc_is_receiving (self)
2042 *
2043 * Returns true is we are currently receiving data
2044 *
2045 */
2046 static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self)
2047 {
2048 return (self->rx_buff.state != OUTSIDE_FRAME);
2049 }
2050
2051
2052 /*
2053 * Function smsc_ircc_probe_transceiver(self)
2054 *
2055 * Tries to find the used Transceiver
2056 *
2057 */
2058 static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self)
2059 {
2060 unsigned int i;
2061
2062 IRDA_ASSERT(self != NULL, return;);
2063
2064 for (i = 0; smsc_transceivers[i].name != NULL; i++)
2065 if (smsc_transceivers[i].probe(self->io.fir_base)) {
2066 IRDA_MESSAGE(" %s transceiver found\n",
2067 smsc_transceivers[i].name);
2068 self->transceiver= i + 1;
2069 return;
2070 }
2071
2072 IRDA_MESSAGE("No transceiver found. Defaulting to %s\n",
2073 smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name);
2074
2075 self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER;
2076 }
2077
2078
2079 /*
2080 * Function smsc_ircc_set_transceiver_for_speed(self, speed)
2081 *
2082 * Set the transceiver according to the speed
2083 *
2084 */
2085 static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed)
2086 {
2087 unsigned int trx;
2088
2089 trx = self->transceiver;
2090 if (trx > 0)
2091 smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed);
2092 }
2093
2094 /*
2095 * Function smsc_ircc_wait_hw_transmitter_finish ()
2096 *
2097 * Wait for the real end of HW transmission
2098 *
2099 * The UART is a strict FIFO, and we get called only when we have finished
2100 * pushing data to the FIFO, so the maximum amount of time we must wait
2101 * is only for the FIFO to drain out.
2102 *
2103 * We use a simple calibrated loop. We may need to adjust the loop
2104 * delay (udelay) to balance I/O traffic and latency. And we also need to
2105 * adjust the maximum timeout.
2106 * It would probably be better to wait for the proper interrupt,
2107 * but it doesn't seem to be available.
2108 *
2109 * We can't use jiffies or kernel timers because :
2110 * 1) We are called from the interrupt handler, which disable softirqs,
2111 * so jiffies won't be increased
2112 * 2) Jiffies granularity is usually very coarse (10ms), and we don't
2113 * want to wait that long to detect stuck hardware.
2114 * Jean II
2115 */
2116
2117 static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self)
2118 {
2119 int iobase = self->io.sir_base;
2120 int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US;
2121
2122 /* Calibrated busy loop */
2123 while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT))
2124 udelay(1);
2125
2126 if (count == 0)
2127 IRDA_DEBUG(0, "%s(): stuck transmitter\n", __FUNCTION__);
2128 }
2129
2130
2131 /* PROBING
2132 *
2133 * REVISIT we can be told about the device by PNP, and should use that info
2134 * instead of probing hardware and creating a platform_device ...
2135 */
2136
2137 static int __init smsc_ircc_look_for_chips(void)
2138 {
2139 struct smsc_chip_address *address;
2140 char *type;
2141 unsigned int cfg_base, found;
2142
2143 found = 0;
2144 address = possible_addresses;
2145
2146 while (address->cfg_base) {
2147 cfg_base = address->cfg_base;
2148
2149 /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __FUNCTION__, cfg_base, address->type);*/
2150
2151 if (address->type & SMSCSIO_TYPE_FDC) {
2152 type = "FDC";
2153 if (address->type & SMSCSIO_TYPE_FLAT)
2154 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type))
2155 found++;
2156
2157 if (address->type & SMSCSIO_TYPE_PAGED)
2158 if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type))
2159 found++;
2160 }
2161 if (address->type & SMSCSIO_TYPE_LPC) {
2162 type = "LPC";
2163 if (address->type & SMSCSIO_TYPE_FLAT)
2164 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type))
2165 found++;
2166
2167 if (address->type & SMSCSIO_TYPE_PAGED)
2168 if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type))
2169 found++;
2170 }
2171 address++;
2172 }
2173 return found;
2174 }
2175
2176 /*
2177 * Function smsc_superio_flat (chip, base, type)
2178 *
2179 * Try to get configuration of a smc SuperIO chip with flat register model
2180 *
2181 */
2182 static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfgbase, char *type)
2183 {
2184 unsigned short firbase, sirbase;
2185 u8 mode, dma, irq;
2186 int ret = -ENODEV;
2187
2188 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2189
2190 if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL)
2191 return ret;
2192
2193 outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase);
2194 mode = inb(cfgbase + 1);
2195
2196 /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __FUNCTION__, mode);*/
2197
2198 if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA))
2199 IRDA_WARNING("%s(): IrDA not enabled\n", __FUNCTION__);
2200
2201 outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase);
2202 sirbase = inb(cfgbase + 1) << 2;
2203
2204 /* FIR iobase */
2205 outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase);
2206 firbase = inb(cfgbase + 1) << 3;
2207
2208 /* DMA */
2209 outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase);
2210 dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK;
2211
2212 /* IRQ */
2213 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase);
2214 irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2215
2216 IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __FUNCTION__, firbase, sirbase, dma, irq, mode);
2217
2218 if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0)
2219 ret = 0;
2220
2221 /* Exit configuration */
2222 outb(SMSCSIO_CFGEXITKEY, cfgbase);
2223
2224 return ret;
2225 }
2226
2227 /*
2228 * Function smsc_superio_paged (chip, base, type)
2229 *
2230 * Try to get configuration of a smc SuperIO chip with paged register model
2231 *
2232 */
2233 static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type)
2234 {
2235 unsigned short fir_io, sir_io;
2236 int ret = -ENODEV;
2237
2238 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2239
2240 if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL)
2241 return ret;
2242
2243 /* Select logical device (UART2) */
2244 outb(0x07, cfg_base);
2245 outb(0x05, cfg_base + 1);
2246
2247 /* SIR iobase */
2248 outb(0x60, cfg_base);
2249 sir_io = inb(cfg_base + 1) << 8;
2250 outb(0x61, cfg_base);
2251 sir_io |= inb(cfg_base + 1);
2252
2253 /* Read FIR base */
2254 outb(0x62, cfg_base);
2255 fir_io = inb(cfg_base + 1) << 8;
2256 outb(0x63, cfg_base);
2257 fir_io |= inb(cfg_base + 1);
2258 outb(0x2b, cfg_base); /* ??? */
2259
2260 if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0)
2261 ret = 0;
2262
2263 /* Exit configuration */
2264 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2265
2266 return ret;
2267 }
2268
2269
2270 static int __init smsc_access(unsigned short cfg_base, unsigned char reg)
2271 {
2272 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2273
2274 outb(reg, cfg_base);
2275 return inb(cfg_base) != reg ? -1 : 0;
2276 }
2277
2278 static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type)
2279 {
2280 u8 devid, xdevid, rev;
2281
2282 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2283
2284 /* Leave configuration */
2285
2286 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2287
2288 if (inb(cfg_base) == SMSCSIO_CFGEXITKEY) /* not a smc superio chip */
2289 return NULL;
2290
2291 outb(reg, cfg_base);
2292
2293 xdevid = inb(cfg_base + 1);
2294
2295 /* Enter configuration */
2296
2297 outb(SMSCSIO_CFGACCESSKEY, cfg_base);
2298
2299 #if 0
2300 if (smsc_access(cfg_base,0x55)) /* send second key and check */
2301 return NULL;
2302 #endif
2303
2304 /* probe device ID */
2305
2306 if (smsc_access(cfg_base, reg))
2307 return NULL;
2308
2309 devid = inb(cfg_base + 1);
2310
2311 if (devid == 0 || devid == 0xff) /* typical values for unused port */
2312 return NULL;
2313
2314 /* probe revision ID */
2315
2316 if (smsc_access(cfg_base, reg + 1))
2317 return NULL;
2318
2319 rev = inb(cfg_base + 1);
2320
2321 if (rev >= 128) /* i think this will make no sense */
2322 return NULL;
2323
2324 if (devid == xdevid) /* protection against false positives */
2325 return NULL;
2326
2327 /* Check for expected device ID; are there others? */
2328
2329 while (chip->devid != devid) {
2330
2331 chip++;
2332
2333 if (chip->name == NULL)
2334 return NULL;
2335 }
2336
2337 IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n",
2338 devid, rev, cfg_base, type, chip->name);
2339
2340 if (chip->rev > rev) {
2341 IRDA_MESSAGE("Revision higher than expected\n");
2342 return NULL;
2343 }
2344
2345 if (chip->flags & NoIRDA)
2346 IRDA_MESSAGE("chipset does not support IRDA\n");
2347
2348 return chip;
2349 }
2350
2351 static int __init smsc_superio_fdc(unsigned short cfg_base)
2352 {
2353 int ret = -1;
2354
2355 if (!request_region(cfg_base, 2, driver_name)) {
2356 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2357 __FUNCTION__, cfg_base);
2358 } else {
2359 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") ||
2360 !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC"))
2361 ret = 0;
2362
2363 release_region(cfg_base, 2);
2364 }
2365
2366 return ret;
2367 }
2368
2369 static int __init smsc_superio_lpc(unsigned short cfg_base)
2370 {
2371 int ret = -1;
2372
2373 if (!request_region(cfg_base, 2, driver_name)) {
2374 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2375 __FUNCTION__, cfg_base);
2376 } else {
2377 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") ||
2378 !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC"))
2379 ret = 0;
2380
2381 release_region(cfg_base, 2);
2382 }
2383 return ret;
2384 }
2385
2386 /*
2387 * Look for some specific subsystem setups that need
2388 * pre-configuration not properly done by the BIOS (especially laptops)
2389 * This code is based in part on smcinit.c, tosh1800-smcinit.c
2390 * and tosh2450-smcinit.c. The table lists the device entries
2391 * for ISA bridges with an LPC (Low Pin Count) controller which
2392 * handles the communication with the SMSC device. After the LPC
2393 * controller is initialized through PCI, the SMSC device is initialized
2394 * through a dedicated port in the ISA port-mapped I/O area, this latter
2395 * area is used to configure the SMSC device with default
2396 * SIR and FIR I/O ports, DMA and IRQ. Different vendors have
2397 * used different sets of parameters and different control port
2398 * addresses making a subsystem device table necessary.
2399 */
2400 #ifdef CONFIG_PCI
2401 #define PCIID_VENDOR_INTEL 0x8086
2402 #define PCIID_VENDOR_ALI 0x10b9
2403 static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __initdata = {
2404 /*
2405 * Subsystems needing entries:
2406 * 0x10b9:0x1533 0x103c:0x0850 HP nx9010 family
2407 * 0x10b9:0x1533 0x0e11:0x005a Compaq nc4000 family
2408 * 0x8086:0x24cc 0x0e11:0x002a HP nx9000 family
2409 */
2410 {
2411 /* Guessed entry */
2412 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2413 .device = 0x24cc,
2414 .subvendor = 0x103c,
2415 .subdevice = 0x08bc,
2416 .sir_io = 0x02f8,
2417 .fir_io = 0x0130,
2418 .fir_irq = 0x05,
2419 .fir_dma = 0x03,
2420 .cfg_base = 0x004e,
2421 .preconfigure = preconfigure_through_82801,
2422 .name = "HP nx5000 family",
2423 },
2424 {
2425 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2426 .device = 0x24cc,
2427 .subvendor = 0x103c,
2428 .subdevice = 0x088c,
2429 /* Quite certain these are the same for nc8000 as for nc6000 */
2430 .sir_io = 0x02f8,
2431 .fir_io = 0x0130,
2432 .fir_irq = 0x05,
2433 .fir_dma = 0x03,
2434 .cfg_base = 0x004e,
2435 .preconfigure = preconfigure_through_82801,
2436 .name = "HP nc8000 family",
2437 },
2438 {
2439 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2440 .device = 0x24cc,
2441 .subvendor = 0x103c,
2442 .subdevice = 0x0890,
2443 .sir_io = 0x02f8,
2444 .fir_io = 0x0130,
2445 .fir_irq = 0x05,
2446 .fir_dma = 0x03,
2447 .cfg_base = 0x004e,
2448 .preconfigure = preconfigure_through_82801,
2449 .name = "HP nc6000 family",
2450 },
2451 {
2452 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2453 .device = 0x24cc,
2454 .subvendor = 0x0e11,
2455 .subdevice = 0x0860,
2456 /* I assume these are the same for x1000 as for the others */
2457 .sir_io = 0x02e8,
2458 .fir_io = 0x02f8,
2459 .fir_irq = 0x07,
2460 .fir_dma = 0x03,
2461 .cfg_base = 0x002e,
2462 .preconfigure = preconfigure_through_82801,
2463 .name = "Compaq x1000 family",
2464 },
2465 {
2466 /* Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge */
2467 .vendor = PCIID_VENDOR_INTEL,
2468 .device = 0x24c0,
2469 .subvendor = 0x1179,
2470 .subdevice = 0xffff, /* 0xffff is "any" */
2471 .sir_io = 0x03f8,
2472 .fir_io = 0x0130,
2473 .fir_irq = 0x07,
2474 .fir_dma = 0x01,
2475 .cfg_base = 0x002e,
2476 .preconfigure = preconfigure_through_82801,
2477 .name = "Toshiba laptop with Intel 82801DB/DBL LPC bridge",
2478 },
2479 {
2480 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801CAM ISA bridge */
2481 .device = 0x248c,
2482 .subvendor = 0x1179,
2483 .subdevice = 0xffff, /* 0xffff is "any" */
2484 .sir_io = 0x03f8,
2485 .fir_io = 0x0130,
2486 .fir_irq = 0x03,
2487 .fir_dma = 0x03,
2488 .cfg_base = 0x002e,
2489 .preconfigure = preconfigure_through_82801,
2490 .name = "Toshiba laptop with Intel 82801CAM ISA bridge",
2491 },
2492 {
2493 /* 82801DBM (ICH4-M) LPC Interface Bridge */
2494 .vendor = PCIID_VENDOR_INTEL,
2495 .device = 0x24cc,
2496 .subvendor = 0x1179,
2497 .subdevice = 0xffff, /* 0xffff is "any" */
2498 .sir_io = 0x03f8,
2499 .fir_io = 0x0130,
2500 .fir_irq = 0x03,
2501 .fir_dma = 0x03,
2502 .cfg_base = 0x002e,
2503 .preconfigure = preconfigure_through_82801,
2504 .name = "Toshiba laptop with Intel 8281DBM LPC bridge",
2505 },
2506 {
2507 /* ALi M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+] */
2508 .vendor = PCIID_VENDOR_ALI,
2509 .device = 0x1533,
2510 .subvendor = 0x1179,
2511 .subdevice = 0xffff, /* 0xffff is "any" */
2512 .sir_io = 0x02e8,
2513 .fir_io = 0x02f8,
2514 .fir_irq = 0x07,
2515 .fir_dma = 0x03,
2516 .cfg_base = 0x002e,
2517 .preconfigure = preconfigure_through_ali,
2518 .name = "Toshiba laptop with ALi ISA bridge",
2519 },
2520 { } // Terminator
2521 };
2522
2523
2524 /*
2525 * This sets up the basic SMSC parameters
2526 * (FIR port, SIR port, FIR DMA, FIR IRQ)
2527 * through the chip configuration port.
2528 */
2529 static int __init preconfigure_smsc_chip(struct
2530 smsc_ircc_subsystem_configuration
2531 *conf)
2532 {
2533 unsigned short iobase = conf->cfg_base;
2534 unsigned char tmpbyte;
2535
2536 outb(LPC47N227_CFGACCESSKEY, iobase); // enter configuration state
2537 outb(SMSCSIOFLAT_DEVICEID_REG, iobase); // set for device ID
2538 tmpbyte = inb(iobase +1); // Read device ID
2539 IRDA_DEBUG(0,
2540 "Detected Chip id: 0x%02x, setting up registers...\n",
2541 tmpbyte);
2542
2543 /* Disable UART1 and set up SIR I/O port */
2544 outb(0x24, iobase); // select CR24 - UART1 base addr
2545 outb(0x00, iobase + 1); // disable UART1
2546 outb(SMSCSIOFLAT_UART2BASEADDR_REG, iobase); // select CR25 - UART2 base addr
2547 outb( (conf->sir_io >> 2), iobase + 1); // bits 2-9 of 0x3f8
2548 tmpbyte = inb(iobase + 1);
2549 if (tmpbyte != (conf->sir_io >> 2) ) {
2550 IRDA_WARNING("ERROR: could not configure SIR ioport.\n");
2551 IRDA_WARNING("Try to supply ircc_cfg argument.\n");
2552 return -ENXIO;
2553 }
2554
2555 /* Set up FIR IRQ channel for UART2 */
2556 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, iobase); // select CR28 - UART1,2 IRQ select
2557 tmpbyte = inb(iobase + 1);
2558 tmpbyte &= SMSCSIOFLAT_UART1IRQSELECT_MASK; // Do not touch the UART1 portion
2559 tmpbyte |= (conf->fir_irq & SMSCSIOFLAT_UART2IRQSELECT_MASK);
2560 outb(tmpbyte, iobase + 1);
2561 tmpbyte = inb(iobase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2562 if (tmpbyte != conf->fir_irq) {
2563 IRDA_WARNING("ERROR: could not configure FIR IRQ channel.\n");
2564 return -ENXIO;
2565 }
2566
2567 /* Set up FIR I/O port */
2568 outb(SMSCSIOFLAT_FIRBASEADDR_REG, iobase); // CR2B - SCE (FIR) base addr
2569 outb((conf->fir_io >> 3), iobase + 1);
2570 tmpbyte = inb(iobase + 1);
2571 if (tmpbyte != (conf->fir_io >> 3) ) {
2572 IRDA_WARNING("ERROR: could not configure FIR I/O port.\n");
2573 return -ENXIO;
2574 }
2575
2576 /* Set up FIR DMA channel */
2577 outb(SMSCSIOFLAT_FIRDMASELECT_REG, iobase); // CR2C - SCE (FIR) DMA select
2578 outb((conf->fir_dma & LPC47N227_FIRDMASELECT_MASK), iobase + 1); // DMA
2579 tmpbyte = inb(iobase + 1) & LPC47N227_FIRDMASELECT_MASK;
2580 if (tmpbyte != (conf->fir_dma & LPC47N227_FIRDMASELECT_MASK)) {
2581 IRDA_WARNING("ERROR: could not configure FIR DMA channel.\n");
2582 return -ENXIO;
2583 }
2584
2585 outb(SMSCSIOFLAT_UARTMODE0C_REG, iobase); // CR0C - UART mode
2586 tmpbyte = inb(iobase + 1);
2587 tmpbyte &= ~SMSCSIOFLAT_UART2MODE_MASK |
2588 SMSCSIOFLAT_UART2MODE_VAL_IRDA;
2589 outb(tmpbyte, iobase + 1); // enable IrDA (HPSIR) mode, high speed
2590
2591 outb(LPC47N227_APMBOOTDRIVE_REG, iobase); // CR07 - Auto Pwr Mgt/boot drive sel
2592 tmpbyte = inb(iobase + 1);
2593 outb(tmpbyte | LPC47N227_UART2AUTOPWRDOWN_MASK, iobase + 1); // enable UART2 autopower down
2594
2595 /* This one was not part of tosh1800 */
2596 outb(0x0a, iobase); // CR0a - ecp fifo / ir mux
2597 tmpbyte = inb(iobase + 1);
2598 outb(tmpbyte | 0x40, iobase + 1); // send active device to ir port
2599
2600 outb(LPC47N227_UART12POWER_REG, iobase); // CR02 - UART 1,2 power
2601 tmpbyte = inb(iobase + 1);
2602 outb(tmpbyte | LPC47N227_UART2POWERDOWN_MASK, iobase + 1); // UART2 power up mode, UART1 power down
2603
2604 outb(LPC47N227_FDCPOWERVALIDCONF_REG, iobase); // CR00 - FDC Power/valid config cycle
2605 tmpbyte = inb(iobase + 1);
2606 outb(tmpbyte | LPC47N227_VALID_MASK, iobase + 1); // valid config cycle done
2607
2608 outb(LPC47N227_CFGEXITKEY, iobase); // Exit configuration
2609
2610 return 0;
2611 }
2612
2613 /* 82801CAM generic registers */
2614 #define VID 0x00
2615 #define DID 0x02
2616 #define PIRQ_A_D_ROUT 0x60
2617 #define SIRQ_CNTL 0x64
2618 #define PIRQ_E_H_ROUT 0x68
2619 #define PCI_DMA_C 0x90
2620 /* LPC-specific registers */
2621 #define COM_DEC 0xe0
2622 #define GEN1_DEC 0xe4
2623 #define LPC_EN 0xe6
2624 #define GEN2_DEC 0xec
2625 /*
2626 * Sets up the I/O range using the 82801CAM ISA bridge, 82801DBM LPC bridge
2627 * or Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge.
2628 * They all work the same way!
2629 */
2630 static int __init preconfigure_through_82801(struct pci_dev *dev,
2631 struct
2632 smsc_ircc_subsystem_configuration
2633 *conf)
2634 {
2635 unsigned short tmpword;
2636 unsigned char tmpbyte;
2637
2638 IRDA_MESSAGE("Setting up Intel 82801 controller and SMSC device\n");
2639 /*
2640 * Select the range for the COMA COM port (SIR)
2641 * Register COM_DEC:
2642 * Bit 7: reserved
2643 * Bit 6-4, COMB decode range
2644 * Bit 3: reserved
2645 * Bit 2-0, COMA decode range
2646 *
2647 * Decode ranges:
2648 * 000 = 0x3f8-0x3ff (COM1)
2649 * 001 = 0x2f8-0x2ff (COM2)
2650 * 010 = 0x220-0x227
2651 * 011 = 0x228-0x22f
2652 * 100 = 0x238-0x23f
2653 * 101 = 0x2e8-0x2ef (COM4)
2654 * 110 = 0x338-0x33f
2655 * 111 = 0x3e8-0x3ef (COM3)
2656 */
2657 pci_read_config_byte(dev, COM_DEC, &tmpbyte);
2658 tmpbyte &= 0xf8; /* mask COMA bits */
2659 switch(conf->sir_io) {
2660 case 0x3f8:
2661 tmpbyte |= 0x00;
2662 break;
2663 case 0x2f8:
2664 tmpbyte |= 0x01;
2665 break;
2666 case 0x220:
2667 tmpbyte |= 0x02;
2668 break;
2669 case 0x228:
2670 tmpbyte |= 0x03;
2671 break;
2672 case 0x238:
2673 tmpbyte |= 0x04;
2674 break;
2675 case 0x2e8:
2676 tmpbyte |= 0x05;
2677 break;
2678 case 0x338:
2679 tmpbyte |= 0x06;
2680 break;
2681 case 0x3e8:
2682 tmpbyte |= 0x07;
2683 break;
2684 default:
2685 tmpbyte |= 0x01; /* COM2 default */
2686 }
2687 IRDA_DEBUG(1, "COM_DEC (write): 0x%02x\n", tmpbyte);
2688 pci_write_config_byte(dev, COM_DEC, tmpbyte);
2689
2690 /* Enable Low Pin Count interface */
2691 pci_read_config_word(dev, LPC_EN, &tmpword);
2692 /* These seem to be set up at all times,
2693 * just make sure it is properly set.
2694 */
2695 switch(conf->cfg_base) {
2696 case 0x04e:
2697 tmpword |= 0x2000;
2698 break;
2699 case 0x02e:
2700 tmpword |= 0x1000;
2701 break;
2702 case 0x062:
2703 tmpword |= 0x0800;
2704 break;
2705 case 0x060:
2706 tmpword |= 0x0400;
2707 break;
2708 default:
2709 IRDA_WARNING("Uncommon I/O base address: 0x%04x\n",
2710 conf->cfg_base);
2711 break;
2712 }
2713 tmpword &= 0xfffd; /* disable LPC COMB */
2714 tmpword |= 0x0001; /* set bit 0 : enable LPC COMA addr range (GEN2) */
2715 IRDA_DEBUG(1, "LPC_EN (write): 0x%04x\n", tmpword);
2716 pci_write_config_word(dev, LPC_EN, tmpword);
2717
2718 /*
2719 * Configure LPC DMA channel
2720 * PCI_DMA_C bits:
2721 * Bit 15-14: DMA channel 7 select
2722 * Bit 13-12: DMA channel 6 select
2723 * Bit 11-10: DMA channel 5 select
2724 * Bit 9-8: Reserved
2725 * Bit 7-6: DMA channel 3 select
2726 * Bit 5-4: DMA channel 2 select
2727 * Bit 3-2: DMA channel 1 select
2728 * Bit 1-0: DMA channel 0 select
2729 * 00 = Reserved value
2730 * 01 = PC/PCI DMA
2731 * 10 = Reserved value
2732 * 11 = LPC I/F DMA
2733 */
2734 pci_read_config_word(dev, PCI_DMA_C, &tmpword);
2735 switch(conf->fir_dma) {
2736 case 0x07:
2737 tmpword |= 0xc000;
2738 break;
2739 case 0x06:
2740 tmpword |= 0x3000;
2741 break;
2742 case 0x05:
2743 tmpword |= 0x0c00;
2744 break;
2745 case 0x03:
2746 tmpword |= 0x00c0;
2747 break;
2748 case 0x02:
2749 tmpword |= 0x0030;
2750 break;
2751 case 0x01:
2752 tmpword |= 0x000c;
2753 break;
2754 case 0x00:
2755 tmpword |= 0x0003;
2756 break;
2757 default:
2758 break; /* do not change settings */
2759 }
2760 IRDA_DEBUG(1, "PCI_DMA_C (write): 0x%04x\n", tmpword);
2761 pci_write_config_word(dev, PCI_DMA_C, tmpword);
2762
2763 /*
2764 * GEN2_DEC bits:
2765 * Bit 15-4: Generic I/O range
2766 * Bit 3-1: reserved (read as 0)
2767 * Bit 0: enable GEN2 range on LPC I/F
2768 */
2769 tmpword = conf->fir_io & 0xfff8;
2770 tmpword |= 0x0001;
2771 IRDA_DEBUG(1, "GEN2_DEC (write): 0x%04x\n", tmpword);
2772 pci_write_config_word(dev, GEN2_DEC, tmpword);
2773
2774 /* Pre-configure chip */
2775 return preconfigure_smsc_chip(conf);
2776 }
2777
2778 /*
2779 * Pre-configure a certain port on the ALi 1533 bridge.
2780 * This is based on reverse-engineering since ALi does not
2781 * provide any data sheet for the 1533 chip.
2782 */
2783 static void __init preconfigure_ali_port(struct pci_dev *dev,
2784 unsigned short port)
2785 {
2786 unsigned char reg;
2787 /* These bits obviously control the different ports */
2788 unsigned char mask;
2789 unsigned char tmpbyte;
2790
2791 switch(port) {
2792 case 0x0130:
2793 case 0x0178:
2794 reg = 0xb0;
2795 mask = 0x80;
2796 break;
2797 case 0x03f8:
2798 reg = 0xb4;
2799 mask = 0x80;
2800 break;
2801 case 0x02f8:
2802 reg = 0xb4;
2803 mask = 0x30;
2804 break;
2805 case 0x02e8:
2806 reg = 0xb4;
2807 mask = 0x08;
2808 break;
2809 default:
2810 IRDA_ERROR("Failed to configure unsupported port on ALi 1533 bridge: 0x%04x\n", port);
2811 return;
2812 }
2813
2814 pci_read_config_byte(dev, reg, &tmpbyte);
2815 /* Turn on the right bits */
2816 tmpbyte |= mask;
2817 pci_write_config_byte(dev, reg, tmpbyte);
2818 IRDA_MESSAGE("Activated ALi 1533 ISA bridge port 0x%04x.\n", port);
2819 return;
2820 }
2821
2822 static int __init preconfigure_through_ali(struct pci_dev *dev,
2823 struct
2824 smsc_ircc_subsystem_configuration
2825 *conf)
2826 {
2827 /* Configure the two ports on the ALi 1533 */
2828 preconfigure_ali_port(dev, conf->sir_io);
2829 preconfigure_ali_port(dev, conf->fir_io);
2830
2831 /* Pre-configure chip */
2832 return preconfigure_smsc_chip(conf);
2833 }
2834
2835 static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
2836 unsigned short ircc_fir,
2837 unsigned short ircc_sir,
2838 unsigned char ircc_dma,
2839 unsigned char ircc_irq)
2840 {
2841 struct pci_dev *dev = NULL;
2842 unsigned short ss_vendor = 0x0000;
2843 unsigned short ss_device = 0x0000;
2844 int ret = 0;
2845
2846 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
2847
2848 while (dev != NULL) {
2849 struct smsc_ircc_subsystem_configuration *conf;
2850
2851 /*
2852 * Cache the subsystem vendor/device:
2853 * some manufacturers fail to set this for all components,
2854 * so we save it in case there is just 0x0000 0x0000 on the
2855 * device we want to check.
2856 */
2857 if (dev->subsystem_vendor != 0x0000U) {
2858 ss_vendor = dev->subsystem_vendor;
2859 ss_device = dev->subsystem_device;
2860 }
2861 conf = subsystem_configurations;
2862 for( ; conf->subvendor; conf++) {
2863 if(conf->vendor == dev->vendor &&
2864 conf->device == dev->device &&
2865 conf->subvendor == ss_vendor &&
2866 /* Sometimes these are cached values */
2867 (conf->subdevice == ss_device ||
2868 conf->subdevice == 0xffff)) {
2869 struct smsc_ircc_subsystem_configuration
2870 tmpconf;
2871
2872 memcpy(&tmpconf, conf,
2873 sizeof(struct smsc_ircc_subsystem_configuration));
2874
2875 /*
2876 * Override the default values with anything
2877 * passed in as parameter
2878 */
2879 if (ircc_cfg != 0)
2880 tmpconf.cfg_base = ircc_cfg;
2881 if (ircc_fir != 0)
2882 tmpconf.fir_io = ircc_fir;
2883 if (ircc_sir != 0)
2884 tmpconf.sir_io = ircc_sir;
2885 if (ircc_dma != DMA_INVAL)
2886 tmpconf.fir_dma = ircc_dma;
2887 if (ircc_irq != IRQ_INVAL)
2888 tmpconf.fir_irq = ircc_irq;
2889
2890 IRDA_MESSAGE("Detected unconfigured %s SMSC IrDA chip, pre-configuring device.\n", conf->name);
2891 if (conf->preconfigure)
2892 ret = conf->preconfigure(dev, &tmpconf);
2893 else
2894 ret = -ENODEV;
2895 }
2896 }
2897 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
2898 }
2899
2900 return ret;
2901 }
2902 #endif // CONFIG_PCI
2903
2904 /************************************************
2905 *
2906 * Transceivers specific functions
2907 *
2908 ************************************************/
2909
2910
2911 /*
2912 * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed)
2913 *
2914 * Program transceiver through smsc-ircc ATC circuitry
2915 *
2916 */
2917
2918 static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed)
2919 {
2920 unsigned long jiffies_now, jiffies_timeout;
2921 u8 val;
2922
2923 jiffies_now = jiffies;
2924 jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES;
2925
2926 /* ATC */
2927 register_bank(fir_base, 4);
2928 outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE,
2929 fir_base + IRCC_ATC);
2930
2931 while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) &&
2932 !time_after(jiffies, jiffies_timeout))
2933 /* empty */;
2934
2935 if (val)
2936 IRDA_WARNING("%s(): ATC: 0x%02x\n", __FUNCTION__,
2937 inb(fir_base + IRCC_ATC));
2938 }
2939
2940 /*
2941 * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base)
2942 *
2943 * Probe transceiver smsc-ircc ATC circuitry
2944 *
2945 */
2946
2947 static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base)
2948 {
2949 return 0;
2950 }
2951
2952 /*
2953 * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed)
2954 *
2955 * Set transceiver
2956 *
2957 */
2958
2959 static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed)
2960 {
2961 u8 fast_mode;
2962
2963 switch (speed) {
2964 default:
2965 case 576000 :
2966 fast_mode = 0;
2967 break;
2968 case 1152000 :
2969 case 4000000 :
2970 fast_mode = IRCC_LCR_A_FAST;
2971 break;
2972 }
2973 register_bank(fir_base, 0);
2974 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
2975 }
2976
2977 /*
2978 * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base)
2979 *
2980 * Probe transceiver
2981 *
2982 */
2983
2984 static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base)
2985 {
2986 return 0;
2987 }
2988
2989 /*
2990 * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed)
2991 *
2992 * Set transceiver
2993 *
2994 */
2995
2996 static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed)
2997 {
2998 u8 fast_mode;
2999
3000 switch (speed) {
3001 default:
3002 case 576000 :
3003 fast_mode = 0;
3004 break;
3005 case 1152000 :
3006 case 4000000 :
3007 fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA;
3008 break;
3009
3010 }
3011 /* This causes an interrupt */
3012 register_bank(fir_base, 0);
3013 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
3014 }
3015
3016 /*
3017 * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base)
3018 *
3019 * Probe transceiver
3020 *
3021 */
3022
3023 static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base)
3024 {
3025 return 0;
3026 }
3027
3028
3029 module_init(smsc_ircc_init);
3030 module_exit(smsc_ircc_cleanup);
Linux kernel - Deliverables
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