1 /*********************************************************************
3 * Description: Driver for the SMC Infrared Communications Controller
4 * Status: Experimental.
5 * Author: Daniele Peri (peri@csai.unipa.it)
10 * Copyright (c) 2002 Daniele Peri
11 * All Rights Reserved.
12 * Copyright (c) 2002 Jean Tourrilhes
13 * Copyright (c) 2006 Linus Walleij
16 * Based on smc-ircc.c:
18 * Copyright (c) 2001 Stefani Seibold
19 * Copyright (c) 1999-2001 Dag Brattli
20 * Copyright (c) 1998-1999 Thomas Davis,
24 * Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved.
27 * This program is free software; you can redistribute it and/or
28 * modify it under the terms of the GNU General Public License as
29 * published by the Free Software Foundation; either version 2 of
30 * the License, or (at your option) any later version.
32 * This program is distributed in the hope that it will be useful,
33 * but WITHOUT ANY WARRANTY; without even the implied warranty of
34 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35 * GNU General Public License for more details.
37 * You should have received a copy of the GNU General Public License
38 * along with this program; if not, write to the Free Software
39 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
42 ********************************************************************/
44 #include <linux/module.h>
45 #include <linux/kernel.h>
46 #include <linux/types.h>
47 #include <linux/skbuff.h>
48 #include <linux/netdevice.h>
49 #include <linux/ioport.h>
50 #include <linux/delay.h>
51 #include <linux/slab.h>
52 #include <linux/init.h>
53 #include <linux/rtnetlink.h>
54 #include <linux/serial_reg.h>
55 #include <linux/dma-mapping.h>
56 #include <linux/pnp.h>
57 #include <linux/platform_device.h>
61 #include <asm/byteorder.h>
63 #include <linux/spinlock.h>
66 #include <linux/pci.h>
69 #include <net/irda/wrapper.h>
70 #include <net/irda/irda.h>
71 #include <net/irda/irda_device.h>
73 #include "smsc-ircc2.h"
77 MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>");
78 MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver");
79 MODULE_LICENSE("GPL");
81 static int smsc_nopnp
= 1;
82 module_param_named(nopnp
, smsc_nopnp
, bool, 0);
83 MODULE_PARM_DESC(nopnp
, "Do not use PNP to detect controller settings, defaults to true");
86 static int ircc_dma
= DMA_INVAL
;
87 module_param(ircc_dma
, int, 0);
88 MODULE_PARM_DESC(ircc_dma
, "DMA channel");
91 static int ircc_irq
= IRQ_INVAL
;
92 module_param(ircc_irq
, int, 0);
93 MODULE_PARM_DESC(ircc_irq
, "IRQ line");
96 module_param(ircc_fir
, int, 0);
97 MODULE_PARM_DESC(ircc_fir
, "FIR Base Address");
100 module_param(ircc_sir
, int, 0);
101 MODULE_PARM_DESC(ircc_sir
, "SIR Base Address");
104 module_param(ircc_cfg
, int, 0);
105 MODULE_PARM_DESC(ircc_cfg
, "Configuration register base address");
107 static int ircc_transceiver
;
108 module_param(ircc_transceiver
, int, 0);
109 MODULE_PARM_DESC(ircc_transceiver
, "Transceiver type");
114 struct smsc_ircc_subsystem_configuration
{
115 unsigned short vendor
; /* PCI vendor ID */
116 unsigned short device
; /* PCI vendor ID */
117 unsigned short subvendor
; /* PCI subsystem vendor ID */
118 unsigned short subdevice
; /* PCI sybsystem device ID */
119 unsigned short sir_io
; /* I/O port for SIR */
120 unsigned short fir_io
; /* I/O port for FIR */
121 unsigned char fir_irq
; /* FIR IRQ */
122 unsigned char fir_dma
; /* FIR DMA */
123 unsigned short cfg_base
; /* I/O port for chip configuration */
124 int (*preconfigure
)(struct pci_dev
*dev
, struct smsc_ircc_subsystem_configuration
*conf
); /* Preconfig function */
125 const char *name
; /* name shown as info */
129 struct smsc_transceiver
{
131 void (*set_for_speed
)(int fir_base
, u32 speed
);
132 int (*probe
)(int fir_base
);
145 struct smsc_chip_address
{
146 unsigned int cfg_base
;
150 /* Private data for each instance */
151 struct smsc_ircc_cb
{
152 struct net_device
*netdev
; /* Yes! we are some kind of netdevice */
153 struct irlap_cb
*irlap
; /* The link layer we are binded to */
155 chipio_t io
; /* IrDA controller information */
156 iobuff_t tx_buff
; /* Transmit buffer */
157 iobuff_t rx_buff
; /* Receive buffer */
158 dma_addr_t tx_buff_dma
;
159 dma_addr_t rx_buff_dma
;
161 struct qos_info qos
; /* QoS capabilities for this device */
163 spinlock_t lock
; /* For serializing operations */
166 __u32 flags
; /* Interface flags */
168 int tx_buff_offsets
[10]; /* Offsets between frames in tx_buff */
169 int tx_len
; /* Number of frames in tx_buff */
172 struct platform_device
*pldev
;
177 #define SMSC_IRCC2_DRIVER_NAME "smsc-ircc2"
179 #define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED 9600
180 #define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER 1
181 #define SMSC_IRCC2_C_NET_TIMEOUT 0
182 #define SMSC_IRCC2_C_SIR_STOP 0
184 static const char *driver_name
= SMSC_IRCC2_DRIVER_NAME
;
188 static int smsc_ircc_open(unsigned int firbase
, unsigned int sirbase
, u8 dma
, u8 irq
);
189 static int smsc_ircc_present(unsigned int fir_base
, unsigned int sir_base
);
190 static void smsc_ircc_setup_io(struct smsc_ircc_cb
*self
, unsigned int fir_base
, unsigned int sir_base
, u8 dma
, u8 irq
);
191 static void smsc_ircc_setup_qos(struct smsc_ircc_cb
*self
);
192 static void smsc_ircc_init_chip(struct smsc_ircc_cb
*self
);
193 static int __exit
smsc_ircc_close(struct smsc_ircc_cb
*self
);
194 static int smsc_ircc_dma_receive(struct smsc_ircc_cb
*self
);
195 static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb
*self
);
196 static void smsc_ircc_sir_receive(struct smsc_ircc_cb
*self
);
197 static int smsc_ircc_hard_xmit_sir(struct sk_buff
*skb
, struct net_device
*dev
);
198 static int smsc_ircc_hard_xmit_fir(struct sk_buff
*skb
, struct net_device
*dev
);
199 static void smsc_ircc_dma_xmit(struct smsc_ircc_cb
*self
, int bofs
);
200 static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb
*self
);
201 static void smsc_ircc_change_speed(struct smsc_ircc_cb
*self
, u32 speed
);
202 static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb
*self
, u32 speed
);
203 static irqreturn_t
smsc_ircc_interrupt(int irq
, void *dev_id
);
204 static irqreturn_t
smsc_ircc_interrupt_sir(struct net_device
*dev
);
205 static void smsc_ircc_sir_start(struct smsc_ircc_cb
*self
);
206 #if SMSC_IRCC2_C_SIR_STOP
207 static void smsc_ircc_sir_stop(struct smsc_ircc_cb
*self
);
209 static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb
*self
);
210 static int smsc_ircc_sir_write(int iobase
, int fifo_size
, __u8
*buf
, int len
);
211 static int smsc_ircc_net_open(struct net_device
*dev
);
212 static int smsc_ircc_net_close(struct net_device
*dev
);
213 static int smsc_ircc_net_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
);
214 #if SMSC_IRCC2_C_NET_TIMEOUT
215 static void smsc_ircc_timeout(struct net_device
*dev
);
217 static int smsc_ircc_is_receiving(struct smsc_ircc_cb
*self
);
218 static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb
*self
);
219 static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb
*self
, u32 speed
);
220 static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb
*self
);
223 static int __init
smsc_ircc_look_for_chips(void);
224 static const struct smsc_chip
* __init
smsc_ircc_probe(unsigned short cfg_base
, u8 reg
, const struct smsc_chip
*chip
, char *type
);
225 static int __init
smsc_superio_flat(const struct smsc_chip
*chips
, unsigned short cfg_base
, char *type
);
226 static int __init
smsc_superio_paged(const struct smsc_chip
*chips
, unsigned short cfg_base
, char *type
);
227 static int __init
smsc_superio_fdc(unsigned short cfg_base
);
228 static int __init
smsc_superio_lpc(unsigned short cfg_base
);
230 static int __init
preconfigure_smsc_chip(struct smsc_ircc_subsystem_configuration
*conf
);
231 static int __init
preconfigure_through_82801(struct pci_dev
*dev
, struct smsc_ircc_subsystem_configuration
*conf
);
232 static void __init
preconfigure_ali_port(struct pci_dev
*dev
,
233 unsigned short port
);
234 static int __init
preconfigure_through_ali(struct pci_dev
*dev
, struct smsc_ircc_subsystem_configuration
*conf
);
235 static int __init
smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg
,
236 unsigned short ircc_fir
,
237 unsigned short ircc_sir
,
238 unsigned char ircc_dma
,
239 unsigned char ircc_irq
);
242 /* Transceivers specific functions */
244 static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base
, u32 speed
);
245 static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base
);
246 static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base
, u32 speed
);
247 static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base
);
248 static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base
, u32 speed
);
249 static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base
);
251 /* Power Management */
253 static int smsc_ircc_suspend(struct platform_device
*dev
, pm_message_t state
);
254 static int smsc_ircc_resume(struct platform_device
*dev
);
256 static struct platform_driver smsc_ircc_driver
= {
257 .suspend
= smsc_ircc_suspend
,
258 .resume
= smsc_ircc_resume
,
260 .name
= SMSC_IRCC2_DRIVER_NAME
,
264 /* Transceivers for SMSC-ircc */
266 static struct smsc_transceiver smsc_transceivers
[] =
268 { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800
, smsc_ircc_probe_transceiver_toshiba_sat1800
},
269 { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select
, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select
},
270 { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc
, smsc_ircc_probe_transceiver_smsc_ircc_atc
},
273 #define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (ARRAY_SIZE(smsc_transceivers) - 1)
275 /* SMC SuperIO chipsets definitions */
277 #define KEY55_1 0 /* SuperIO Configuration mode with Key <0x55> */
278 #define KEY55_2 1 /* SuperIO Configuration mode with Key <0x55,0x55> */
279 #define NoIRDA 2 /* SuperIO Chip has no IRDA Port */
280 #define SIR 0 /* SuperIO Chip has only slow IRDA */
281 #define FIR 4 /* SuperIO Chip has fast IRDA */
282 #define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */
284 static struct smsc_chip __initdata fdc_chips_flat
[] =
286 /* Base address 0x3f0 or 0x370 */
287 { "37C44", KEY55_1
|NoIRDA
, 0x00, 0x00 }, /* This chip cannot be detected */
288 { "37C665GT", KEY55_2
|NoIRDA
, 0x65, 0x01 },
289 { "37C665GT", KEY55_2
|NoIRDA
, 0x66, 0x01 },
290 { "37C669", KEY55_2
|SIR
|SERx4
, 0x03, 0x02 },
291 { "37C669", KEY55_2
|SIR
|SERx4
, 0x04, 0x02 }, /* ID? */
292 { "37C78", KEY55_2
|NoIRDA
, 0x78, 0x00 },
293 { "37N769", KEY55_1
|FIR
|SERx4
, 0x28, 0x00 },
294 { "37N869", KEY55_1
|FIR
|SERx4
, 0x29, 0x00 },
298 static struct smsc_chip __initdata fdc_chips_paged
[] =
300 /* Base address 0x3f0 or 0x370 */
301 { "37B72X", KEY55_1
|SIR
|SERx4
, 0x4c, 0x00 },
302 { "37B77X", KEY55_1
|SIR
|SERx4
, 0x43, 0x00 },
303 { "37B78X", KEY55_1
|SIR
|SERx4
, 0x44, 0x00 },
304 { "37B80X", KEY55_1
|SIR
|SERx4
, 0x42, 0x00 },
305 { "37C67X", KEY55_1
|FIR
|SERx4
, 0x40, 0x00 },
306 { "37C93X", KEY55_2
|SIR
|SERx4
, 0x02, 0x01 },
307 { "37C93XAPM", KEY55_1
|SIR
|SERx4
, 0x30, 0x01 },
308 { "37C93XFR", KEY55_2
|FIR
|SERx4
, 0x03, 0x01 },
309 { "37M707", KEY55_1
|SIR
|SERx4
, 0x42, 0x00 },
310 { "37M81X", KEY55_1
|SIR
|SERx4
, 0x4d, 0x00 },
311 { "37N958FR", KEY55_1
|FIR
|SERx4
, 0x09, 0x04 },
312 { "37N971", KEY55_1
|FIR
|SERx4
, 0x0a, 0x00 },
313 { "37N972", KEY55_1
|FIR
|SERx4
, 0x0b, 0x00 },
317 static struct smsc_chip __initdata lpc_chips_flat
[] =
319 /* Base address 0x2E or 0x4E */
320 { "47N227", KEY55_1
|FIR
|SERx4
, 0x5a, 0x00 },
321 { "47N227", KEY55_1
|FIR
|SERx4
, 0x7a, 0x00 },
322 { "47N267", KEY55_1
|FIR
|SERx4
, 0x5e, 0x00 },
326 static struct smsc_chip __initdata lpc_chips_paged
[] =
328 /* Base address 0x2E or 0x4E */
329 { "47B27X", KEY55_1
|SIR
|SERx4
, 0x51, 0x00 },
330 { "47B37X", KEY55_1
|SIR
|SERx4
, 0x52, 0x00 },
331 { "47M10X", KEY55_1
|SIR
|SERx4
, 0x59, 0x00 },
332 { "47M120", KEY55_1
|NoIRDA
|SERx4
, 0x5c, 0x00 },
333 { "47M13X", KEY55_1
|SIR
|SERx4
, 0x59, 0x00 },
334 { "47M14X", KEY55_1
|SIR
|SERx4
, 0x5f, 0x00 },
335 { "47N252", KEY55_1
|FIR
|SERx4
, 0x0e, 0x00 },
336 { "47S42X", KEY55_1
|SIR
|SERx4
, 0x57, 0x00 },
340 #define SMSCSIO_TYPE_FDC 1
341 #define SMSCSIO_TYPE_LPC 2
342 #define SMSCSIO_TYPE_FLAT 4
343 #define SMSCSIO_TYPE_PAGED 8
345 static struct smsc_chip_address __initdata possible_addresses
[] =
347 { 0x3f0, SMSCSIO_TYPE_FDC
|SMSCSIO_TYPE_FLAT
|SMSCSIO_TYPE_PAGED
},
348 { 0x370, SMSCSIO_TYPE_FDC
|SMSCSIO_TYPE_FLAT
|SMSCSIO_TYPE_PAGED
},
349 { 0xe0, SMSCSIO_TYPE_FDC
|SMSCSIO_TYPE_FLAT
|SMSCSIO_TYPE_PAGED
},
350 { 0x2e, SMSCSIO_TYPE_LPC
|SMSCSIO_TYPE_FLAT
|SMSCSIO_TYPE_PAGED
},
351 { 0x4e, SMSCSIO_TYPE_LPC
|SMSCSIO_TYPE_FLAT
|SMSCSIO_TYPE_PAGED
},
357 static struct smsc_ircc_cb
*dev_self
[] = { NULL
, NULL
};
358 static unsigned short dev_count
;
360 static inline void register_bank(int iobase
, int bank
)
362 outb(((inb(iobase
+ IRCC_MASTER
) & 0xf0) | (bank
& 0x07)),
363 iobase
+ IRCC_MASTER
);
366 /* PNP hotplug support */
367 static const struct pnp_device_id smsc_ircc_pnp_table
[] = {
368 { .id
= "SMCf010", .driver_data
= 0 },
369 /* and presumably others */
372 MODULE_DEVICE_TABLE(pnp
, smsc_ircc_pnp_table
);
374 static int pnp_driver_registered
;
377 static int __init
smsc_ircc_pnp_probe(struct pnp_dev
*dev
,
378 const struct pnp_device_id
*dev_id
)
380 unsigned int firbase
, sirbase
;
383 if (!(pnp_port_valid(dev
, 0) && pnp_port_valid(dev
, 1) &&
384 pnp_dma_valid(dev
, 0) && pnp_irq_valid(dev
, 0)))
387 sirbase
= pnp_port_start(dev
, 0);
388 firbase
= pnp_port_start(dev
, 1);
389 dma
= pnp_dma(dev
, 0);
390 irq
= pnp_irq(dev
, 0);
392 if (smsc_ircc_open(firbase
, sirbase
, dma
, irq
))
398 static struct pnp_driver smsc_ircc_pnp_driver
= {
399 .name
= "smsc-ircc2",
400 .id_table
= smsc_ircc_pnp_table
,
401 .probe
= smsc_ircc_pnp_probe
,
403 #else /* CONFIG_PNP */
404 static struct pnp_driver smsc_ircc_pnp_driver
;
407 /*******************************************************************************
413 *******************************************************************************/
415 static int __init
smsc_ircc_legacy_probe(void)
420 if (smsc_ircc_preconfigure_subsystems(ircc_cfg
, ircc_fir
, ircc_sir
, ircc_dma
, ircc_irq
) < 0) {
421 /* Ignore errors from preconfiguration */
422 IRDA_ERROR("%s, Preconfiguration failed !\n", driver_name
);
426 if (ircc_fir
> 0 && ircc_sir
> 0) {
427 IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir
);
428 IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir
);
430 if (smsc_ircc_open(ircc_fir
, ircc_sir
, ircc_dma
, ircc_irq
))
435 /* try user provided configuration register base address */
437 IRDA_MESSAGE(" Overriding configuration address "
438 "0x%04x\n", ircc_cfg
);
439 if (!smsc_superio_fdc(ircc_cfg
))
441 if (!smsc_superio_lpc(ircc_cfg
))
445 if (smsc_ircc_look_for_chips() > 0)
452 * Function smsc_ircc_init ()
454 * Initialize chip. Just try to find out how many chips we are dealing with
457 static int __init
smsc_ircc_init(void)
461 IRDA_DEBUG(1, "%s\n", __func__
);
463 ret
= platform_driver_register(&smsc_ircc_driver
);
465 IRDA_ERROR("%s, Can't register driver!\n", driver_name
);
471 if (smsc_nopnp
|| !pnp_platform_devices
||
472 ircc_cfg
|| ircc_fir
|| ircc_sir
||
473 ircc_dma
!= DMA_INVAL
|| ircc_irq
!= IRQ_INVAL
) {
474 ret
= smsc_ircc_legacy_probe();
476 if (pnp_register_driver(&smsc_ircc_pnp_driver
) == 0)
477 pnp_driver_registered
= 1;
481 if (pnp_driver_registered
)
482 pnp_unregister_driver(&smsc_ircc_pnp_driver
);
483 platform_driver_unregister(&smsc_ircc_driver
);
490 * Function smsc_ircc_open (firbase, sirbase, dma, irq)
492 * Try to open driver instance
495 static int __init
smsc_ircc_open(unsigned int fir_base
, unsigned int sir_base
, u8 dma
, u8 irq
)
497 struct smsc_ircc_cb
*self
;
498 struct net_device
*dev
;
501 IRDA_DEBUG(1, "%s\n", __func__
);
503 err
= smsc_ircc_present(fir_base
, sir_base
);
508 if (dev_count
>= ARRAY_SIZE(dev_self
)) {
509 IRDA_WARNING("%s(), too many devices!\n", __func__
);
514 * Allocate new instance of the driver
516 dev
= alloc_irdadev(sizeof(struct smsc_ircc_cb
));
518 IRDA_WARNING("%s() can't allocate net device\n", __func__
);
522 dev
->hard_start_xmit
= smsc_ircc_hard_xmit_sir
;
523 #if SMSC_IRCC2_C_NET_TIMEOUT
524 dev
->tx_timeout
= smsc_ircc_timeout
;
525 dev
->watchdog_timeo
= HZ
* 2; /* Allow enough time for speed change */
527 dev
->open
= smsc_ircc_net_open
;
528 dev
->stop
= smsc_ircc_net_close
;
529 dev
->do_ioctl
= smsc_ircc_net_ioctl
;
531 self
= netdev_priv(dev
);
534 /* Make ifconfig display some details */
535 dev
->base_addr
= self
->io
.fir_base
= fir_base
;
536 dev
->irq
= self
->io
.irq
= irq
;
538 /* Need to store self somewhere */
539 dev_self
[dev_count
] = self
;
540 spin_lock_init(&self
->lock
);
542 self
->rx_buff
.truesize
= SMSC_IRCC2_RX_BUFF_TRUESIZE
;
543 self
->tx_buff
.truesize
= SMSC_IRCC2_TX_BUFF_TRUESIZE
;
546 dma_alloc_coherent(NULL
, self
->rx_buff
.truesize
,
547 &self
->rx_buff_dma
, GFP_KERNEL
);
548 if (self
->rx_buff
.head
== NULL
) {
549 IRDA_ERROR("%s, Can't allocate memory for receive buffer!\n",
555 dma_alloc_coherent(NULL
, self
->tx_buff
.truesize
,
556 &self
->tx_buff_dma
, GFP_KERNEL
);
557 if (self
->tx_buff
.head
== NULL
) {
558 IRDA_ERROR("%s, Can't allocate memory for transmit buffer!\n",
563 memset(self
->rx_buff
.head
, 0, self
->rx_buff
.truesize
);
564 memset(self
->tx_buff
.head
, 0, self
->tx_buff
.truesize
);
566 self
->rx_buff
.in_frame
= FALSE
;
567 self
->rx_buff
.state
= OUTSIDE_FRAME
;
568 self
->tx_buff
.data
= self
->tx_buff
.head
;
569 self
->rx_buff
.data
= self
->rx_buff
.head
;
571 smsc_ircc_setup_io(self
, fir_base
, sir_base
, dma
, irq
);
572 smsc_ircc_setup_qos(self
);
573 smsc_ircc_init_chip(self
);
575 if (ircc_transceiver
> 0 &&
576 ircc_transceiver
< SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS
)
577 self
->transceiver
= ircc_transceiver
;
579 smsc_ircc_probe_transceiver(self
);
581 err
= register_netdev(self
->netdev
);
583 IRDA_ERROR("%s, Network device registration failed!\n",
588 self
->pldev
= platform_device_register_simple(SMSC_IRCC2_DRIVER_NAME
,
590 if (IS_ERR(self
->pldev
)) {
591 err
= PTR_ERR(self
->pldev
);
594 platform_set_drvdata(self
->pldev
, self
);
596 IRDA_MESSAGE("IrDA: Registered device %s\n", dev
->name
);
602 unregister_netdev(self
->netdev
);
605 dma_free_coherent(NULL
, self
->tx_buff
.truesize
,
606 self
->tx_buff
.head
, self
->tx_buff_dma
);
608 dma_free_coherent(NULL
, self
->rx_buff
.truesize
,
609 self
->rx_buff
.head
, self
->rx_buff_dma
);
611 free_netdev(self
->netdev
);
612 dev_self
[dev_count
] = NULL
;
614 release_region(fir_base
, SMSC_IRCC2_FIR_CHIP_IO_EXTENT
);
615 release_region(sir_base
, SMSC_IRCC2_SIR_CHIP_IO_EXTENT
);
621 * Function smsc_ircc_present(fir_base, sir_base)
623 * Check the smsc-ircc chip presence
626 static int smsc_ircc_present(unsigned int fir_base
, unsigned int sir_base
)
628 unsigned char low
, high
, chip
, config
, dma
, irq
, version
;
630 if (!request_region(fir_base
, SMSC_IRCC2_FIR_CHIP_IO_EXTENT
,
632 IRDA_WARNING("%s: can't get fir_base of 0x%03x\n",
637 if (!request_region(sir_base
, SMSC_IRCC2_SIR_CHIP_IO_EXTENT
,
639 IRDA_WARNING("%s: can't get sir_base of 0x%03x\n",
644 register_bank(fir_base
, 3);
646 high
= inb(fir_base
+ IRCC_ID_HIGH
);
647 low
= inb(fir_base
+ IRCC_ID_LOW
);
648 chip
= inb(fir_base
+ IRCC_CHIP_ID
);
649 version
= inb(fir_base
+ IRCC_VERSION
);
650 config
= inb(fir_base
+ IRCC_INTERFACE
);
651 dma
= config
& IRCC_INTERFACE_DMA_MASK
;
652 irq
= (config
& IRCC_INTERFACE_IRQ_MASK
) >> 4;
654 if (high
!= 0x10 || low
!= 0xb8 || (chip
!= 0xf1 && chip
!= 0xf2)) {
655 IRDA_WARNING("%s(), addr 0x%04x - no device found!\n",
659 IRDA_MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, "
660 "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n",
661 chip
& 0x0f, version
, fir_base
, sir_base
, dma
, irq
);
666 release_region(sir_base
, SMSC_IRCC2_SIR_CHIP_IO_EXTENT
);
668 release_region(fir_base
, SMSC_IRCC2_FIR_CHIP_IO_EXTENT
);
674 * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq)
679 static void smsc_ircc_setup_io(struct smsc_ircc_cb
*self
,
680 unsigned int fir_base
, unsigned int sir_base
,
683 unsigned char config
, chip_dma
, chip_irq
;
685 register_bank(fir_base
, 3);
686 config
= inb(fir_base
+ IRCC_INTERFACE
);
687 chip_dma
= config
& IRCC_INTERFACE_DMA_MASK
;
688 chip_irq
= (config
& IRCC_INTERFACE_IRQ_MASK
) >> 4;
690 self
->io
.fir_base
= fir_base
;
691 self
->io
.sir_base
= sir_base
;
692 self
->io
.fir_ext
= SMSC_IRCC2_FIR_CHIP_IO_EXTENT
;
693 self
->io
.sir_ext
= SMSC_IRCC2_SIR_CHIP_IO_EXTENT
;
694 self
->io
.fifo_size
= SMSC_IRCC2_FIFO_SIZE
;
695 self
->io
.speed
= SMSC_IRCC2_C_IRDA_FALLBACK_SPEED
;
697 if (irq
!= IRQ_INVAL
) {
699 IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n",
700 driver_name
, chip_irq
, irq
);
703 self
->io
.irq
= chip_irq
;
705 if (dma
!= DMA_INVAL
) {
707 IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n",
708 driver_name
, chip_dma
, dma
);
711 self
->io
.dma
= chip_dma
;
716 * Function smsc_ircc_setup_qos(self)
721 static void smsc_ircc_setup_qos(struct smsc_ircc_cb
*self
)
723 /* Initialize QoS for this device */
724 irda_init_max_qos_capabilies(&self
->qos
);
726 self
->qos
.baud_rate
.bits
= IR_9600
|IR_19200
|IR_38400
|IR_57600
|
727 IR_115200
|IR_576000
|IR_1152000
|(IR_4000000
<< 8);
729 self
->qos
.min_turn_time
.bits
= SMSC_IRCC2_MIN_TURN_TIME
;
730 self
->qos
.window_size
.bits
= SMSC_IRCC2_WINDOW_SIZE
;
731 irda_qos_bits_to_value(&self
->qos
);
735 * Function smsc_ircc_init_chip(self)
740 static void smsc_ircc_init_chip(struct smsc_ircc_cb
*self
)
742 int iobase
= self
->io
.fir_base
;
744 register_bank(iobase
, 0);
745 outb(IRCC_MASTER_RESET
, iobase
+ IRCC_MASTER
);
746 outb(0x00, iobase
+ IRCC_MASTER
);
748 register_bank(iobase
, 1);
749 outb(((inb(iobase
+ IRCC_SCE_CFGA
) & 0x87) | IRCC_CFGA_IRDA_SIR_A
),
750 iobase
+ IRCC_SCE_CFGA
);
752 #ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */
753 outb(((inb(iobase
+ IRCC_SCE_CFGB
) & 0x3f) | IRCC_CFGB_MUX_COM
),
754 iobase
+ IRCC_SCE_CFGB
);
756 outb(((inb(iobase
+ IRCC_SCE_CFGB
) & 0x3f) | IRCC_CFGB_MUX_IR
),
757 iobase
+ IRCC_SCE_CFGB
);
759 (void) inb(iobase
+ IRCC_FIFO_THRESHOLD
);
760 outb(SMSC_IRCC2_FIFO_THRESHOLD
, iobase
+ IRCC_FIFO_THRESHOLD
);
762 register_bank(iobase
, 4);
763 outb((inb(iobase
+ IRCC_CONTROL
) & 0x30), iobase
+ IRCC_CONTROL
);
765 register_bank(iobase
, 0);
766 outb(0, iobase
+ IRCC_LCR_A
);
768 smsc_ircc_set_sir_speed(self
, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED
);
770 /* Power on device */
771 outb(0x00, iobase
+ IRCC_MASTER
);
775 * Function smsc_ircc_net_ioctl (dev, rq, cmd)
777 * Process IOCTL commands for this device
780 static int smsc_ircc_net_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
782 struct if_irda_req
*irq
= (struct if_irda_req
*) rq
;
783 struct smsc_ircc_cb
*self
;
787 IRDA_ASSERT(dev
!= NULL
, return -1;);
789 self
= netdev_priv(dev
);
791 IRDA_ASSERT(self
!= NULL
, return -1;);
793 IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __func__
, dev
->name
, cmd
);
796 case SIOCSBANDWIDTH
: /* Set bandwidth */
797 if (!capable(CAP_NET_ADMIN
))
800 /* Make sure we are the only one touching
801 * self->io.speed and the hardware - Jean II */
802 spin_lock_irqsave(&self
->lock
, flags
);
803 smsc_ircc_change_speed(self
, irq
->ifr_baudrate
);
804 spin_unlock_irqrestore(&self
->lock
, flags
);
807 case SIOCSMEDIABUSY
: /* Set media busy */
808 if (!capable(CAP_NET_ADMIN
)) {
813 irda_device_set_media_busy(self
->netdev
, TRUE
);
815 case SIOCGRECEIVING
: /* Check if we are receiving right now */
816 irq
->ifr_receiving
= smsc_ircc_is_receiving(self
);
820 if (!capable(CAP_NET_ADMIN
)) {
824 smsc_ircc_sir_set_dtr_rts(dev
, irq
->ifr_dtr
, irq
->ifr_rts
);
834 #if SMSC_IRCC2_C_NET_TIMEOUT
836 * Function smsc_ircc_timeout (struct net_device *dev)
838 * The networking timeout management.
842 static void smsc_ircc_timeout(struct net_device
*dev
)
844 struct smsc_ircc_cb
*self
= netdev_priv(dev
);
847 IRDA_WARNING("%s: transmit timed out, changing speed to: %d\n",
848 dev
->name
, self
->io
.speed
);
849 spin_lock_irqsave(&self
->lock
, flags
);
850 smsc_ircc_sir_start(self
);
851 smsc_ircc_change_speed(self
, self
->io
.speed
);
852 dev
->trans_start
= jiffies
;
853 netif_wake_queue(dev
);
854 spin_unlock_irqrestore(&self
->lock
, flags
);
859 * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev)
861 * Transmits the current frame until FIFO is full, then
862 * waits until the next transmit interrupt, and continues until the
863 * frame is transmitted.
865 static int smsc_ircc_hard_xmit_sir(struct sk_buff
*skb
, struct net_device
*dev
)
867 struct smsc_ircc_cb
*self
;
871 IRDA_DEBUG(1, "%s\n", __func__
);
873 IRDA_ASSERT(dev
!= NULL
, return 0;);
875 self
= netdev_priv(dev
);
876 IRDA_ASSERT(self
!= NULL
, return 0;);
878 netif_stop_queue(dev
);
880 /* Make sure test of self->io.speed & speed change are atomic */
881 spin_lock_irqsave(&self
->lock
, flags
);
883 /* Check if we need to change the speed */
884 speed
= irda_get_next_speed(skb
);
885 if (speed
!= self
->io
.speed
&& speed
!= -1) {
886 /* Check for empty frame */
889 * We send frames one by one in SIR mode (no
890 * pipelining), so at this point, if we were sending
891 * a previous frame, we just received the interrupt
892 * telling us it is finished (UART_IIR_THRI).
893 * Therefore, waiting for the transmitter to really
894 * finish draining the fifo won't take too long.
895 * And the interrupt handler is not expected to run.
897 smsc_ircc_sir_wait_hw_transmitter_finish(self
);
898 smsc_ircc_change_speed(self
, speed
);
899 spin_unlock_irqrestore(&self
->lock
, flags
);
903 self
->new_speed
= speed
;
907 self
->tx_buff
.data
= self
->tx_buff
.head
;
909 /* Copy skb to tx_buff while wrapping, stuffing and making CRC */
910 self
->tx_buff
.len
= async_wrap_skb(skb
, self
->tx_buff
.data
,
911 self
->tx_buff
.truesize
);
913 dev
->stats
.tx_bytes
+= self
->tx_buff
.len
;
915 /* Turn on transmit finished interrupt. Will fire immediately! */
916 outb(UART_IER_THRI
, self
->io
.sir_base
+ UART_IER
);
918 spin_unlock_irqrestore(&self
->lock
, flags
);
926 * Function smsc_ircc_set_fir_speed (self, baud)
928 * Change the speed of the device
931 static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb
*self
, u32 speed
)
933 int fir_base
, ir_mode
, ctrl
, fast
;
935 IRDA_ASSERT(self
!= NULL
, return;);
936 fir_base
= self
->io
.fir_base
;
938 self
->io
.speed
= speed
;
943 ir_mode
= IRCC_CFGA_IRDA_HDLC
;
946 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __func__
);
949 ir_mode
= IRCC_CFGA_IRDA_HDLC
;
950 ctrl
= IRCC_1152
| IRCC_CRC
;
951 fast
= IRCC_LCR_A_FAST
| IRCC_LCR_A_GP_DATA
;
952 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n",
956 ir_mode
= IRCC_CFGA_IRDA_4PPM
;
958 fast
= IRCC_LCR_A_FAST
;
959 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n",
965 /* This causes an interrupt */
966 register_bank(fir_base
, 0);
967 outb((inb(fir_base
+ IRCC_LCR_A
) & 0xbf) | fast
, fir_base
+ IRCC_LCR_A
);
970 register_bank(fir_base
, 1);
971 outb(((inb(fir_base
+ IRCC_SCE_CFGA
) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK
) | ir_mode
), fir_base
+ IRCC_SCE_CFGA
);
973 register_bank(fir_base
, 4);
974 outb((inb(fir_base
+ IRCC_CONTROL
) & 0x30) | ctrl
, fir_base
+ IRCC_CONTROL
);
978 * Function smsc_ircc_fir_start(self)
980 * Change the speed of the device
983 static void smsc_ircc_fir_start(struct smsc_ircc_cb
*self
)
985 struct net_device
*dev
;
988 IRDA_DEBUG(1, "%s\n", __func__
);
990 IRDA_ASSERT(self
!= NULL
, return;);
992 IRDA_ASSERT(dev
!= NULL
, return;);
994 fir_base
= self
->io
.fir_base
;
996 /* Reset everything */
998 /* Install FIR transmit handler */
999 dev
->hard_start_xmit
= smsc_ircc_hard_xmit_fir
;
1002 outb(inb(fir_base
+ IRCC_LCR_A
) | IRCC_LCR_A_FIFO_RESET
, fir_base
+ IRCC_LCR_A
);
1004 /* Enable interrupt */
1005 /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/
1007 register_bank(fir_base
, 1);
1009 /* Select the TX/RX interface */
1010 #ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */
1011 outb(((inb(fir_base
+ IRCC_SCE_CFGB
) & 0x3f) | IRCC_CFGB_MUX_COM
),
1012 fir_base
+ IRCC_SCE_CFGB
);
1014 outb(((inb(fir_base
+ IRCC_SCE_CFGB
) & 0x3f) | IRCC_CFGB_MUX_IR
),
1015 fir_base
+ IRCC_SCE_CFGB
);
1017 (void) inb(fir_base
+ IRCC_FIFO_THRESHOLD
);
1019 /* Enable SCE interrupts */
1020 outb(0, fir_base
+ IRCC_MASTER
);
1021 register_bank(fir_base
, 0);
1022 outb(IRCC_IER_ACTIVE_FRAME
| IRCC_IER_EOM
, fir_base
+ IRCC_IER
);
1023 outb(IRCC_MASTER_INT_EN
, fir_base
+ IRCC_MASTER
);
1027 * Function smsc_ircc_fir_stop(self, baud)
1029 * Change the speed of the device
1032 static void smsc_ircc_fir_stop(struct smsc_ircc_cb
*self
)
1036 IRDA_DEBUG(1, "%s\n", __func__
);
1038 IRDA_ASSERT(self
!= NULL
, return;);
1040 fir_base
= self
->io
.fir_base
;
1041 register_bank(fir_base
, 0);
1042 /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/
1043 outb(inb(fir_base
+ IRCC_LCR_B
) & IRCC_LCR_B_SIP_ENABLE
, fir_base
+ IRCC_LCR_B
);
1048 * Function smsc_ircc_change_speed(self, baud)
1050 * Change the speed of the device
1052 * This function *must* be called with spinlock held, because it may
1053 * be called from the irq handler. - Jean II
1055 static void smsc_ircc_change_speed(struct smsc_ircc_cb
*self
, u32 speed
)
1057 struct net_device
*dev
;
1058 int last_speed_was_sir
;
1060 IRDA_DEBUG(0, "%s() changing speed to: %d\n", __func__
, speed
);
1062 IRDA_ASSERT(self
!= NULL
, return;);
1065 last_speed_was_sir
= self
->io
.speed
<= SMSC_IRCC2_MAX_SIR_SPEED
;
1070 self
->io
.speed
= speed
;
1071 last_speed_was_sir
= 0;
1072 smsc_ircc_fir_start(self
);
1075 if (self
->io
.speed
== 0)
1076 smsc_ircc_sir_start(self
);
1079 if (!last_speed_was_sir
) speed
= self
->io
.speed
;
1082 if (self
->io
.speed
!= speed
)
1083 smsc_ircc_set_transceiver_for_speed(self
, speed
);
1085 self
->io
.speed
= speed
;
1087 if (speed
<= SMSC_IRCC2_MAX_SIR_SPEED
) {
1088 if (!last_speed_was_sir
) {
1089 smsc_ircc_fir_stop(self
);
1090 smsc_ircc_sir_start(self
);
1092 smsc_ircc_set_sir_speed(self
, speed
);
1094 if (last_speed_was_sir
) {
1095 #if SMSC_IRCC2_C_SIR_STOP
1096 smsc_ircc_sir_stop(self
);
1098 smsc_ircc_fir_start(self
);
1100 smsc_ircc_set_fir_speed(self
, speed
);
1103 self
->tx_buff
.len
= 10;
1104 self
->tx_buff
.data
= self
->tx_buff
.head
;
1106 smsc_ircc_dma_xmit(self
, 4000);
1108 /* Be ready for incoming frames */
1109 smsc_ircc_dma_receive(self
);
1112 netif_wake_queue(dev
);
1116 * Function smsc_ircc_set_sir_speed (self, speed)
1118 * Set speed of IrDA port to specified baudrate
1121 static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb
*self
, __u32 speed
)
1124 int fcr
; /* FIFO control reg */
1125 int lcr
; /* Line control reg */
1128 IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __func__
, speed
);
1130 IRDA_ASSERT(self
!= NULL
, return;);
1131 iobase
= self
->io
.sir_base
;
1133 /* Update accounting for new speed */
1134 self
->io
.speed
= speed
;
1136 /* Turn off interrupts */
1137 outb(0, iobase
+ UART_IER
);
1139 divisor
= SMSC_IRCC2_MAX_SIR_SPEED
/ speed
;
1141 fcr
= UART_FCR_ENABLE_FIFO
;
1144 * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and
1145 * almost 1,7 ms at 19200 bps. At speeds above that we can just forget
1146 * about this timeout since it will always be fast enough.
1148 fcr
|= self
->io
.speed
< 38400 ?
1149 UART_FCR_TRIGGER_1
: UART_FCR_TRIGGER_14
;
1151 /* IrDA ports use 8N1 */
1152 lcr
= UART_LCR_WLEN8
;
1154 outb(UART_LCR_DLAB
| lcr
, iobase
+ UART_LCR
); /* Set DLAB */
1155 outb(divisor
& 0xff, iobase
+ UART_DLL
); /* Set speed */
1156 outb(divisor
>> 8, iobase
+ UART_DLM
);
1157 outb(lcr
, iobase
+ UART_LCR
); /* Set 8N1 */
1158 outb(fcr
, iobase
+ UART_FCR
); /* Enable FIFO's */
1160 /* Turn on interrups */
1161 outb(UART_IER_RLSI
| UART_IER_RDI
| UART_IER_THRI
, iobase
+ UART_IER
);
1163 IRDA_DEBUG(2, "%s() speed changed to: %d\n", __func__
, speed
);
1168 * Function smsc_ircc_hard_xmit_fir (skb, dev)
1170 * Transmit the frame!
1173 static int smsc_ircc_hard_xmit_fir(struct sk_buff
*skb
, struct net_device
*dev
)
1175 struct smsc_ircc_cb
*self
;
1176 unsigned long flags
;
1180 IRDA_ASSERT(dev
!= NULL
, return 0;);
1181 self
= netdev_priv(dev
);
1182 IRDA_ASSERT(self
!= NULL
, return 0;);
1184 netif_stop_queue(dev
);
1186 /* Make sure test of self->io.speed & speed change are atomic */
1187 spin_lock_irqsave(&self
->lock
, flags
);
1189 /* Check if we need to change the speed after this frame */
1190 speed
= irda_get_next_speed(skb
);
1191 if (speed
!= self
->io
.speed
&& speed
!= -1) {
1192 /* Check for empty frame */
1194 /* Note : you should make sure that speed changes
1195 * are not going to corrupt any outgoing frame.
1196 * Look at nsc-ircc for the gory details - Jean II */
1197 smsc_ircc_change_speed(self
, speed
);
1198 spin_unlock_irqrestore(&self
->lock
, flags
);
1203 self
->new_speed
= speed
;
1206 skb_copy_from_linear_data(skb
, self
->tx_buff
.head
, skb
->len
);
1208 self
->tx_buff
.len
= skb
->len
;
1209 self
->tx_buff
.data
= self
->tx_buff
.head
;
1211 mtt
= irda_get_mtt(skb
);
1216 * Compute how many BOFs (STA or PA's) we need to waste the
1217 * min turn time given the speed of the link.
1219 bofs
= mtt
* (self
->io
.speed
/ 1000) / 8000;
1223 smsc_ircc_dma_xmit(self
, bofs
);
1225 /* Transmit frame */
1226 smsc_ircc_dma_xmit(self
, 0);
1229 spin_unlock_irqrestore(&self
->lock
, flags
);
1236 * Function smsc_ircc_dma_xmit (self, bofs)
1238 * Transmit data using DMA
1241 static void smsc_ircc_dma_xmit(struct smsc_ircc_cb
*self
, int bofs
)
1243 int iobase
= self
->io
.fir_base
;
1246 IRDA_DEBUG(3, "%s\n", __func__
);
1249 register_bank(iobase
, 0);
1250 outb(0x00, iobase
+ IRCC_LCR_B
);
1252 register_bank(iobase
, 1);
1253 outb(inb(iobase
+ IRCC_SCE_CFGB
) & ~IRCC_CFGB_DMA_ENABLE
,
1254 iobase
+ IRCC_SCE_CFGB
);
1256 self
->io
.direction
= IO_XMIT
;
1258 /* Set BOF additional count for generating the min turn time */
1259 register_bank(iobase
, 4);
1260 outb(bofs
& 0xff, iobase
+ IRCC_BOF_COUNT_LO
);
1261 ctrl
= inb(iobase
+ IRCC_CONTROL
) & 0xf0;
1262 outb(ctrl
| ((bofs
>> 8) & 0x0f), iobase
+ IRCC_BOF_COUNT_HI
);
1264 /* Set max Tx frame size */
1265 outb(self
->tx_buff
.len
>> 8, iobase
+ IRCC_TX_SIZE_HI
);
1266 outb(self
->tx_buff
.len
& 0xff, iobase
+ IRCC_TX_SIZE_LO
);
1268 /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/
1270 /* Enable burst mode chip Tx DMA */
1271 register_bank(iobase
, 1);
1272 outb(inb(iobase
+ IRCC_SCE_CFGB
) | IRCC_CFGB_DMA_ENABLE
|
1273 IRCC_CFGB_DMA_BURST
, iobase
+ IRCC_SCE_CFGB
);
1275 /* Setup DMA controller (must be done after enabling chip DMA) */
1276 irda_setup_dma(self
->io
.dma
, self
->tx_buff_dma
, self
->tx_buff
.len
,
1279 /* Enable interrupt */
1281 register_bank(iobase
, 0);
1282 outb(IRCC_IER_ACTIVE_FRAME
| IRCC_IER_EOM
, iobase
+ IRCC_IER
);
1283 outb(IRCC_MASTER_INT_EN
, iobase
+ IRCC_MASTER
);
1285 /* Enable transmit */
1286 outb(IRCC_LCR_B_SCE_TRANSMIT
| IRCC_LCR_B_SIP_ENABLE
, iobase
+ IRCC_LCR_B
);
1290 * Function smsc_ircc_dma_xmit_complete (self)
1292 * The transfer of a frame in finished. This function will only be called
1293 * by the interrupt handler
1296 static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb
*self
)
1298 int iobase
= self
->io
.fir_base
;
1300 IRDA_DEBUG(3, "%s\n", __func__
);
1303 register_bank(iobase
, 0);
1304 outb(0x00, iobase
+ IRCC_LCR_B
);
1306 register_bank(iobase
, 1);
1307 outb(inb(iobase
+ IRCC_SCE_CFGB
) & ~IRCC_CFGB_DMA_ENABLE
,
1308 iobase
+ IRCC_SCE_CFGB
);
1310 /* Check for underrun! */
1311 register_bank(iobase
, 0);
1312 if (inb(iobase
+ IRCC_LSR
) & IRCC_LSR_UNDERRUN
) {
1313 self
->netdev
->stats
.tx_errors
++;
1314 self
->netdev
->stats
.tx_fifo_errors
++;
1316 /* Reset error condition */
1317 register_bank(iobase
, 0);
1318 outb(IRCC_MASTER_ERROR_RESET
, iobase
+ IRCC_MASTER
);
1319 outb(0x00, iobase
+ IRCC_MASTER
);
1321 self
->netdev
->stats
.tx_packets
++;
1322 self
->netdev
->stats
.tx_bytes
+= self
->tx_buff
.len
;
1325 /* Check if it's time to change the speed */
1326 if (self
->new_speed
) {
1327 smsc_ircc_change_speed(self
, self
->new_speed
);
1328 self
->new_speed
= 0;
1331 netif_wake_queue(self
->netdev
);
1335 * Function smsc_ircc_dma_receive(self)
1337 * Get ready for receiving a frame. The device will initiate a DMA
1338 * if it starts to receive a frame.
1341 static int smsc_ircc_dma_receive(struct smsc_ircc_cb
*self
)
1343 int iobase
= self
->io
.fir_base
;
1345 /* Turn off chip DMA */
1346 register_bank(iobase
, 1);
1347 outb(inb(iobase
+ IRCC_SCE_CFGB
) & ~IRCC_CFGB_DMA_ENABLE
,
1348 iobase
+ IRCC_SCE_CFGB
);
1352 register_bank(iobase
, 0);
1353 outb(0x00, iobase
+ IRCC_LCR_B
);
1355 /* Turn off chip DMA */
1356 register_bank(iobase
, 1);
1357 outb(inb(iobase
+ IRCC_SCE_CFGB
) & ~IRCC_CFGB_DMA_ENABLE
,
1358 iobase
+ IRCC_SCE_CFGB
);
1360 self
->io
.direction
= IO_RECV
;
1361 self
->rx_buff
.data
= self
->rx_buff
.head
;
1363 /* Set max Rx frame size */
1364 register_bank(iobase
, 4);
1365 outb((2050 >> 8) & 0x0f, iobase
+ IRCC_RX_SIZE_HI
);
1366 outb(2050 & 0xff, iobase
+ IRCC_RX_SIZE_LO
);
1368 /* Setup DMA controller */
1369 irda_setup_dma(self
->io
.dma
, self
->rx_buff_dma
, self
->rx_buff
.truesize
,
1372 /* Enable burst mode chip Rx DMA */
1373 register_bank(iobase
, 1);
1374 outb(inb(iobase
+ IRCC_SCE_CFGB
) | IRCC_CFGB_DMA_ENABLE
|
1375 IRCC_CFGB_DMA_BURST
, iobase
+ IRCC_SCE_CFGB
);
1377 /* Enable interrupt */
1378 register_bank(iobase
, 0);
1379 outb(IRCC_IER_ACTIVE_FRAME
| IRCC_IER_EOM
, iobase
+ IRCC_IER
);
1380 outb(IRCC_MASTER_INT_EN
, iobase
+ IRCC_MASTER
);
1382 /* Enable receiver */
1383 register_bank(iobase
, 0);
1384 outb(IRCC_LCR_B_SCE_RECEIVE
| IRCC_LCR_B_SIP_ENABLE
,
1385 iobase
+ IRCC_LCR_B
);
1391 * Function smsc_ircc_dma_receive_complete(self)
1393 * Finished with receiving frames
1396 static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb
*self
)
1398 struct sk_buff
*skb
;
1399 int len
, msgcnt
, lsr
;
1400 int iobase
= self
->io
.fir_base
;
1402 register_bank(iobase
, 0);
1404 IRDA_DEBUG(3, "%s\n", __func__
);
1407 register_bank(iobase
, 0);
1408 outb(0x00, iobase
+ IRCC_LCR_B
);
1410 register_bank(iobase
, 0);
1411 outb(inb(iobase
+ IRCC_LSAR
) & ~IRCC_LSAR_ADDRESS_MASK
, iobase
+ IRCC_LSAR
);
1412 lsr
= inb(iobase
+ IRCC_LSR
);
1413 msgcnt
= inb(iobase
+ IRCC_LCR_B
) & 0x08;
1415 IRDA_DEBUG(2, "%s: dma count = %d\n", __func__
,
1416 get_dma_residue(self
->io
.dma
));
1418 len
= self
->rx_buff
.truesize
- get_dma_residue(self
->io
.dma
);
1420 /* Look for errors */
1421 if (lsr
& (IRCC_LSR_FRAME_ERROR
| IRCC_LSR_CRC_ERROR
| IRCC_LSR_SIZE_ERROR
)) {
1422 self
->netdev
->stats
.rx_errors
++;
1423 if (lsr
& IRCC_LSR_FRAME_ERROR
)
1424 self
->netdev
->stats
.rx_frame_errors
++;
1425 if (lsr
& IRCC_LSR_CRC_ERROR
)
1426 self
->netdev
->stats
.rx_crc_errors
++;
1427 if (lsr
& IRCC_LSR_SIZE_ERROR
)
1428 self
->netdev
->stats
.rx_length_errors
++;
1429 if (lsr
& (IRCC_LSR_UNDERRUN
| IRCC_LSR_OVERRUN
))
1430 self
->netdev
->stats
.rx_length_errors
++;
1435 len
-= self
->io
.speed
< 4000000 ? 2 : 4;
1437 if (len
< 2 || len
> 2050) {
1438 IRDA_WARNING("%s(), bogus len=%d\n", __func__
, len
);
1441 IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __func__
, msgcnt
, len
);
1443 skb
= dev_alloc_skb(len
+ 1);
1445 IRDA_WARNING("%s(), memory squeeze, dropping frame.\n",
1449 /* Make sure IP header gets aligned */
1450 skb_reserve(skb
, 1);
1452 memcpy(skb_put(skb
, len
), self
->rx_buff
.data
, len
);
1453 self
->netdev
->stats
.rx_packets
++;
1454 self
->netdev
->stats
.rx_bytes
+= len
;
1456 skb
->dev
= self
->netdev
;
1457 skb_reset_mac_header(skb
);
1458 skb
->protocol
= htons(ETH_P_IRDA
);
1463 * Function smsc_ircc_sir_receive (self)
1465 * Receive one frame from the infrared port
1468 static void smsc_ircc_sir_receive(struct smsc_ircc_cb
*self
)
1473 IRDA_ASSERT(self
!= NULL
, return;);
1475 iobase
= self
->io
.sir_base
;
1478 * Receive all characters in Rx FIFO, unwrap and unstuff them.
1479 * async_unwrap_char will deliver all found frames
1482 async_unwrap_char(self
->netdev
, &self
->netdev
->stats
, &self
->rx_buff
,
1483 inb(iobase
+ UART_RX
));
1485 /* Make sure we don't stay here to long */
1486 if (boguscount
++ > 32) {
1487 IRDA_DEBUG(2, "%s(), breaking!\n", __func__
);
1490 } while (inb(iobase
+ UART_LSR
) & UART_LSR_DR
);
1495 * Function smsc_ircc_interrupt (irq, dev_id, regs)
1497 * An interrupt from the chip has arrived. Time to do some work
1500 static irqreturn_t
smsc_ircc_interrupt(int dummy
, void *dev_id
)
1502 struct net_device
*dev
= dev_id
;
1503 struct smsc_ircc_cb
*self
= netdev_priv(dev
);
1504 int iobase
, iir
, lcra
, lsr
;
1505 irqreturn_t ret
= IRQ_NONE
;
1507 /* Serialise the interrupt handler in various CPUs, stop Tx path */
1508 spin_lock(&self
->lock
);
1510 /* Check if we should use the SIR interrupt handler */
1511 if (self
->io
.speed
<= SMSC_IRCC2_MAX_SIR_SPEED
) {
1512 ret
= smsc_ircc_interrupt_sir(dev
);
1513 goto irq_ret_unlock
;
1516 iobase
= self
->io
.fir_base
;
1518 register_bank(iobase
, 0);
1519 iir
= inb(iobase
+ IRCC_IIR
);
1521 goto irq_ret_unlock
;
1524 /* Disable interrupts */
1525 outb(0, iobase
+ IRCC_IER
);
1526 lcra
= inb(iobase
+ IRCC_LCR_A
);
1527 lsr
= inb(iobase
+ IRCC_LSR
);
1529 IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __func__
, iir
);
1531 if (iir
& IRCC_IIR_EOM
) {
1532 if (self
->io
.direction
== IO_RECV
)
1533 smsc_ircc_dma_receive_complete(self
);
1535 smsc_ircc_dma_xmit_complete(self
);
1537 smsc_ircc_dma_receive(self
);
1540 if (iir
& IRCC_IIR_ACTIVE_FRAME
) {
1541 /*printk(KERN_WARNING "%s(): Active Frame\n", __func__);*/
1544 /* Enable interrupts again */
1546 register_bank(iobase
, 0);
1547 outb(IRCC_IER_ACTIVE_FRAME
| IRCC_IER_EOM
, iobase
+ IRCC_IER
);
1550 spin_unlock(&self
->lock
);
1556 * Function irport_interrupt_sir (irq, dev_id)
1558 * Interrupt handler for SIR modes
1560 static irqreturn_t
smsc_ircc_interrupt_sir(struct net_device
*dev
)
1562 struct smsc_ircc_cb
*self
= netdev_priv(dev
);
1567 /* Already locked comming here in smsc_ircc_interrupt() */
1568 /*spin_lock(&self->lock);*/
1570 iobase
= self
->io
.sir_base
;
1572 iir
= inb(iobase
+ UART_IIR
) & UART_IIR_ID
;
1576 /* Clear interrupt */
1577 lsr
= inb(iobase
+ UART_LSR
);
1579 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
1580 __func__
, iir
, lsr
, iobase
);
1584 IRDA_DEBUG(2, "%s(), RLSI\n", __func__
);
1587 /* Receive interrupt */
1588 smsc_ircc_sir_receive(self
);
1591 if (lsr
& UART_LSR_THRE
)
1592 /* Transmitter ready for data */
1593 smsc_ircc_sir_write_wakeup(self
);
1596 IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n",
1601 /* Make sure we don't stay here to long */
1602 if (boguscount
++ > 100)
1605 iir
= inb(iobase
+ UART_IIR
) & UART_IIR_ID
;
1607 /*spin_unlock(&self->lock);*/
1614 * Function ircc_is_receiving (self)
1616 * Return TRUE is we are currently receiving a frame
1619 static int ircc_is_receiving(struct smsc_ircc_cb
*self
)
1624 IRDA_DEBUG(1, "%s\n", __func__
);
1626 IRDA_ASSERT(self
!= NULL
, return FALSE
;);
1628 IRDA_DEBUG(0, "%s: dma count = %d\n", __func__
,
1629 get_dma_residue(self
->io
.dma
));
1631 status
= (self
->rx_buff
.state
!= OUTSIDE_FRAME
);
1637 static int smsc_ircc_request_irq(struct smsc_ircc_cb
*self
)
1641 error
= request_irq(self
->io
.irq
, smsc_ircc_interrupt
, 0,
1642 self
->netdev
->name
, self
->netdev
);
1644 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d, err=%d\n",
1645 __func__
, self
->io
.irq
, error
);
1650 static void smsc_ircc_start_interrupts(struct smsc_ircc_cb
*self
)
1652 unsigned long flags
;
1654 spin_lock_irqsave(&self
->lock
, flags
);
1657 smsc_ircc_change_speed(self
, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED
);
1659 spin_unlock_irqrestore(&self
->lock
, flags
);
1662 static void smsc_ircc_stop_interrupts(struct smsc_ircc_cb
*self
)
1664 int iobase
= self
->io
.fir_base
;
1665 unsigned long flags
;
1667 spin_lock_irqsave(&self
->lock
, flags
);
1669 register_bank(iobase
, 0);
1670 outb(0, iobase
+ IRCC_IER
);
1671 outb(IRCC_MASTER_RESET
, iobase
+ IRCC_MASTER
);
1672 outb(0x00, iobase
+ IRCC_MASTER
);
1674 spin_unlock_irqrestore(&self
->lock
, flags
);
1679 * Function smsc_ircc_net_open (dev)
1684 static int smsc_ircc_net_open(struct net_device
*dev
)
1686 struct smsc_ircc_cb
*self
;
1689 IRDA_DEBUG(1, "%s\n", __func__
);
1691 IRDA_ASSERT(dev
!= NULL
, return -1;);
1692 self
= netdev_priv(dev
);
1693 IRDA_ASSERT(self
!= NULL
, return 0;);
1695 if (self
->io
.suspended
) {
1696 IRDA_DEBUG(0, "%s(), device is suspended\n", __func__
);
1700 if (request_irq(self
->io
.irq
, smsc_ircc_interrupt
, 0, dev
->name
,
1702 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n",
1703 __func__
, self
->io
.irq
);
1707 smsc_ircc_start_interrupts(self
);
1709 /* Give self a hardware name */
1710 /* It would be cool to offer the chip revision here - Jean II */
1711 sprintf(hwname
, "SMSC @ 0x%03x", self
->io
.fir_base
);
1714 * Open new IrLAP layer instance, now that everything should be
1715 * initialized properly
1717 self
->irlap
= irlap_open(dev
, &self
->qos
, hwname
);
1720 * Always allocate the DMA channel after the IRQ,
1721 * and clean up on failure.
1723 if (request_dma(self
->io
.dma
, dev
->name
)) {
1724 smsc_ircc_net_close(dev
);
1726 IRDA_WARNING("%s(), unable to allocate DMA=%d\n",
1727 __func__
, self
->io
.dma
);
1731 netif_start_queue(dev
);
1737 * Function smsc_ircc_net_close (dev)
1742 static int smsc_ircc_net_close(struct net_device
*dev
)
1744 struct smsc_ircc_cb
*self
;
1746 IRDA_DEBUG(1, "%s\n", __func__
);
1748 IRDA_ASSERT(dev
!= NULL
, return -1;);
1749 self
= netdev_priv(dev
);
1750 IRDA_ASSERT(self
!= NULL
, return 0;);
1753 netif_stop_queue(dev
);
1755 /* Stop and remove instance of IrLAP */
1757 irlap_close(self
->irlap
);
1760 smsc_ircc_stop_interrupts(self
);
1762 /* if we are called from smsc_ircc_resume we don't have IRQ reserved */
1763 if (!self
->io
.suspended
)
1764 free_irq(self
->io
.irq
, dev
);
1766 disable_dma(self
->io
.dma
);
1767 free_dma(self
->io
.dma
);
1772 static int smsc_ircc_suspend(struct platform_device
*dev
, pm_message_t state
)
1774 struct smsc_ircc_cb
*self
= platform_get_drvdata(dev
);
1776 if (!self
->io
.suspended
) {
1777 IRDA_DEBUG(1, "%s, Suspending\n", driver_name
);
1780 if (netif_running(self
->netdev
)) {
1781 netif_device_detach(self
->netdev
);
1782 smsc_ircc_stop_interrupts(self
);
1783 free_irq(self
->io
.irq
, self
->netdev
);
1784 disable_dma(self
->io
.dma
);
1786 self
->io
.suspended
= 1;
1793 static int smsc_ircc_resume(struct platform_device
*dev
)
1795 struct smsc_ircc_cb
*self
= platform_get_drvdata(dev
);
1797 if (self
->io
.suspended
) {
1798 IRDA_DEBUG(1, "%s, Waking up\n", driver_name
);
1801 smsc_ircc_init_chip(self
);
1802 if (netif_running(self
->netdev
)) {
1803 if (smsc_ircc_request_irq(self
)) {
1805 * Don't fail resume process, just kill this
1808 unregister_netdevice(self
->netdev
);
1810 enable_dma(self
->io
.dma
);
1811 smsc_ircc_start_interrupts(self
);
1812 netif_device_attach(self
->netdev
);
1815 self
->io
.suspended
= 0;
1822 * Function smsc_ircc_close (self)
1824 * Close driver instance
1827 static int __exit
smsc_ircc_close(struct smsc_ircc_cb
*self
)
1829 IRDA_DEBUG(1, "%s\n", __func__
);
1831 IRDA_ASSERT(self
!= NULL
, return -1;);
1833 platform_device_unregister(self
->pldev
);
1835 /* Remove netdevice */
1836 unregister_netdev(self
->netdev
);
1838 smsc_ircc_stop_interrupts(self
);
1840 /* Release the PORTS that this driver is using */
1841 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __func__
,
1844 release_region(self
->io
.fir_base
, self
->io
.fir_ext
);
1846 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __func__
,
1849 release_region(self
->io
.sir_base
, self
->io
.sir_ext
);
1851 if (self
->tx_buff
.head
)
1852 dma_free_coherent(NULL
, self
->tx_buff
.truesize
,
1853 self
->tx_buff
.head
, self
->tx_buff_dma
);
1855 if (self
->rx_buff
.head
)
1856 dma_free_coherent(NULL
, self
->rx_buff
.truesize
,
1857 self
->rx_buff
.head
, self
->rx_buff_dma
);
1859 free_netdev(self
->netdev
);
1864 static void __exit
smsc_ircc_cleanup(void)
1868 IRDA_DEBUG(1, "%s\n", __func__
);
1870 for (i
= 0; i
< 2; i
++) {
1872 smsc_ircc_close(dev_self
[i
]);
1875 if (pnp_driver_registered
)
1876 pnp_unregister_driver(&smsc_ircc_pnp_driver
);
1878 platform_driver_unregister(&smsc_ircc_driver
);
1882 * Start SIR operations
1884 * This function *must* be called with spinlock held, because it may
1885 * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II
1887 static void smsc_ircc_sir_start(struct smsc_ircc_cb
*self
)
1889 struct net_device
*dev
;
1890 int fir_base
, sir_base
;
1892 IRDA_DEBUG(3, "%s\n", __func__
);
1894 IRDA_ASSERT(self
!= NULL
, return;);
1896 IRDA_ASSERT(dev
!= NULL
, return;);
1897 dev
->hard_start_xmit
= &smsc_ircc_hard_xmit_sir
;
1899 fir_base
= self
->io
.fir_base
;
1900 sir_base
= self
->io
.sir_base
;
1902 /* Reset everything */
1903 outb(IRCC_MASTER_RESET
, fir_base
+ IRCC_MASTER
);
1905 #if SMSC_IRCC2_C_SIR_STOP
1906 /*smsc_ircc_sir_stop(self);*/
1909 register_bank(fir_base
, 1);
1910 outb(((inb(fir_base
+ IRCC_SCE_CFGA
) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK
) | IRCC_CFGA_IRDA_SIR_A
), fir_base
+ IRCC_SCE_CFGA
);
1912 /* Initialize UART */
1913 outb(UART_LCR_WLEN8
, sir_base
+ UART_LCR
); /* Reset DLAB */
1914 outb((UART_MCR_DTR
| UART_MCR_RTS
| UART_MCR_OUT2
), sir_base
+ UART_MCR
);
1916 /* Turn on interrups */
1917 outb(UART_IER_RLSI
| UART_IER_RDI
|UART_IER_THRI
, sir_base
+ UART_IER
);
1919 IRDA_DEBUG(3, "%s() - exit\n", __func__
);
1921 outb(0x00, fir_base
+ IRCC_MASTER
);
1924 #if SMSC_IRCC2_C_SIR_STOP
1925 void smsc_ircc_sir_stop(struct smsc_ircc_cb
*self
)
1929 IRDA_DEBUG(3, "%s\n", __func__
);
1930 iobase
= self
->io
.sir_base
;
1933 outb(0, iobase
+ UART_MCR
);
1935 /* Turn off interrupts */
1936 outb(0, iobase
+ UART_IER
);
1941 * Function smsc_sir_write_wakeup (self)
1943 * Called by the SIR interrupt handler when there's room for more data.
1944 * If we have more packets to send, we send them here.
1947 static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb
*self
)
1953 IRDA_ASSERT(self
!= NULL
, return;);
1955 IRDA_DEBUG(4, "%s\n", __func__
);
1957 iobase
= self
->io
.sir_base
;
1959 /* Finished with frame? */
1960 if (self
->tx_buff
.len
> 0) {
1961 /* Write data left in transmit buffer */
1962 actual
= smsc_ircc_sir_write(iobase
, self
->io
.fifo_size
,
1963 self
->tx_buff
.data
, self
->tx_buff
.len
);
1964 self
->tx_buff
.data
+= actual
;
1965 self
->tx_buff
.len
-= actual
;
1968 /*if (self->tx_buff.len ==0) {*/
1971 * Now serial buffer is almost free & we can start
1972 * transmission of another packet. But first we must check
1973 * if we need to change the speed of the hardware
1975 if (self
->new_speed
) {
1976 IRDA_DEBUG(5, "%s(), Changing speed to %d.\n",
1977 __func__
, self
->new_speed
);
1978 smsc_ircc_sir_wait_hw_transmitter_finish(self
);
1979 smsc_ircc_change_speed(self
, self
->new_speed
);
1980 self
->new_speed
= 0;
1982 /* Tell network layer that we want more frames */
1983 netif_wake_queue(self
->netdev
);
1985 self
->netdev
->stats
.tx_packets
++;
1987 if (self
->io
.speed
<= 115200) {
1989 * Reset Rx FIFO to make sure that all reflected transmit data
1990 * is discarded. This is needed for half duplex operation
1992 fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_CLEAR_RCVR
;
1993 fcr
|= self
->io
.speed
< 38400 ?
1994 UART_FCR_TRIGGER_1
: UART_FCR_TRIGGER_14
;
1996 outb(fcr
, iobase
+ UART_FCR
);
1998 /* Turn on receive interrupts */
1999 outb(UART_IER_RDI
, iobase
+ UART_IER
);
2005 * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len)
2007 * Fill Tx FIFO with transmit data
2010 static int smsc_ircc_sir_write(int iobase
, int fifo_size
, __u8
*buf
, int len
)
2014 /* Tx FIFO should be empty! */
2015 if (!(inb(iobase
+ UART_LSR
) & UART_LSR_THRE
)) {
2016 IRDA_WARNING("%s(), failed, fifo not empty!\n", __func__
);
2020 /* Fill FIFO with current frame */
2021 while (fifo_size
-- > 0 && actual
< len
) {
2022 /* Transmit next byte */
2023 outb(buf
[actual
], iobase
+ UART_TX
);
2030 * Function smsc_ircc_is_receiving (self)
2032 * Returns true is we are currently receiving data
2035 static int smsc_ircc_is_receiving(struct smsc_ircc_cb
*self
)
2037 return (self
->rx_buff
.state
!= OUTSIDE_FRAME
);
2042 * Function smsc_ircc_probe_transceiver(self)
2044 * Tries to find the used Transceiver
2047 static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb
*self
)
2051 IRDA_ASSERT(self
!= NULL
, return;);
2053 for (i
= 0; smsc_transceivers
[i
].name
!= NULL
; i
++)
2054 if (smsc_transceivers
[i
].probe(self
->io
.fir_base
)) {
2055 IRDA_MESSAGE(" %s transceiver found\n",
2056 smsc_transceivers
[i
].name
);
2057 self
->transceiver
= i
+ 1;
2061 IRDA_MESSAGE("No transceiver found. Defaulting to %s\n",
2062 smsc_transceivers
[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER
].name
);
2064 self
->transceiver
= SMSC_IRCC2_C_DEFAULT_TRANSCEIVER
;
2069 * Function smsc_ircc_set_transceiver_for_speed(self, speed)
2071 * Set the transceiver according to the speed
2074 static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb
*self
, u32 speed
)
2078 trx
= self
->transceiver
;
2080 smsc_transceivers
[trx
- 1].set_for_speed(self
->io
.fir_base
, speed
);
2084 * Function smsc_ircc_wait_hw_transmitter_finish ()
2086 * Wait for the real end of HW transmission
2088 * The UART is a strict FIFO, and we get called only when we have finished
2089 * pushing data to the FIFO, so the maximum amount of time we must wait
2090 * is only for the FIFO to drain out.
2092 * We use a simple calibrated loop. We may need to adjust the loop
2093 * delay (udelay) to balance I/O traffic and latency. And we also need to
2094 * adjust the maximum timeout.
2095 * It would probably be better to wait for the proper interrupt,
2096 * but it doesn't seem to be available.
2098 * We can't use jiffies or kernel timers because :
2099 * 1) We are called from the interrupt handler, which disable softirqs,
2100 * so jiffies won't be increased
2101 * 2) Jiffies granularity is usually very coarse (10ms), and we don't
2102 * want to wait that long to detect stuck hardware.
2106 static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb
*self
)
2108 int iobase
= self
->io
.sir_base
;
2109 int count
= SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US
;
2111 /* Calibrated busy loop */
2112 while (count
-- > 0 && !(inb(iobase
+ UART_LSR
) & UART_LSR_TEMT
))
2116 IRDA_DEBUG(0, "%s(): stuck transmitter\n", __func__
);
2122 * REVISIT we can be told about the device by PNP, and should use that info
2123 * instead of probing hardware and creating a platform_device ...
2126 static int __init
smsc_ircc_look_for_chips(void)
2128 struct smsc_chip_address
*address
;
2130 unsigned int cfg_base
, found
;
2133 address
= possible_addresses
;
2135 while (address
->cfg_base
) {
2136 cfg_base
= address
->cfg_base
;
2138 /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __func__, cfg_base, address->type);*/
2140 if (address
->type
& SMSCSIO_TYPE_FDC
) {
2142 if (address
->type
& SMSCSIO_TYPE_FLAT
)
2143 if (!smsc_superio_flat(fdc_chips_flat
, cfg_base
, type
))
2146 if (address
->type
& SMSCSIO_TYPE_PAGED
)
2147 if (!smsc_superio_paged(fdc_chips_paged
, cfg_base
, type
))
2150 if (address
->type
& SMSCSIO_TYPE_LPC
) {
2152 if (address
->type
& SMSCSIO_TYPE_FLAT
)
2153 if (!smsc_superio_flat(lpc_chips_flat
, cfg_base
, type
))
2156 if (address
->type
& SMSCSIO_TYPE_PAGED
)
2157 if (!smsc_superio_paged(lpc_chips_paged
, cfg_base
, type
))
2166 * Function smsc_superio_flat (chip, base, type)
2168 * Try to get configuration of a smc SuperIO chip with flat register model
2171 static int __init
smsc_superio_flat(const struct smsc_chip
*chips
, unsigned short cfgbase
, char *type
)
2173 unsigned short firbase
, sirbase
;
2177 IRDA_DEBUG(1, "%s\n", __func__
);
2179 if (smsc_ircc_probe(cfgbase
, SMSCSIOFLAT_DEVICEID_REG
, chips
, type
) == NULL
)
2182 outb(SMSCSIOFLAT_UARTMODE0C_REG
, cfgbase
);
2183 mode
= inb(cfgbase
+ 1);
2185 /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __func__, mode);*/
2187 if (!(mode
& SMSCSIOFLAT_UART2MODE_VAL_IRDA
))
2188 IRDA_WARNING("%s(): IrDA not enabled\n", __func__
);
2190 outb(SMSCSIOFLAT_UART2BASEADDR_REG
, cfgbase
);
2191 sirbase
= inb(cfgbase
+ 1) << 2;
2194 outb(SMSCSIOFLAT_FIRBASEADDR_REG
, cfgbase
);
2195 firbase
= inb(cfgbase
+ 1) << 3;
2198 outb(SMSCSIOFLAT_FIRDMASELECT_REG
, cfgbase
);
2199 dma
= inb(cfgbase
+ 1) & SMSCSIOFLAT_FIRDMASELECT_MASK
;
2202 outb(SMSCSIOFLAT_UARTIRQSELECT_REG
, cfgbase
);
2203 irq
= inb(cfgbase
+ 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK
;
2205 IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __func__
, firbase
, sirbase
, dma
, irq
, mode
);
2207 if (firbase
&& smsc_ircc_open(firbase
, sirbase
, dma
, irq
) == 0)
2210 /* Exit configuration */
2211 outb(SMSCSIO_CFGEXITKEY
, cfgbase
);
2217 * Function smsc_superio_paged (chip, base, type)
2219 * Try to get configuration of a smc SuperIO chip with paged register model
2222 static int __init
smsc_superio_paged(const struct smsc_chip
*chips
, unsigned short cfg_base
, char *type
)
2224 unsigned short fir_io
, sir_io
;
2227 IRDA_DEBUG(1, "%s\n", __func__
);
2229 if (smsc_ircc_probe(cfg_base
, 0x20, chips
, type
) == NULL
)
2232 /* Select logical device (UART2) */
2233 outb(0x07, cfg_base
);
2234 outb(0x05, cfg_base
+ 1);
2237 outb(0x60, cfg_base
);
2238 sir_io
= inb(cfg_base
+ 1) << 8;
2239 outb(0x61, cfg_base
);
2240 sir_io
|= inb(cfg_base
+ 1);
2243 outb(0x62, cfg_base
);
2244 fir_io
= inb(cfg_base
+ 1) << 8;
2245 outb(0x63, cfg_base
);
2246 fir_io
|= inb(cfg_base
+ 1);
2247 outb(0x2b, cfg_base
); /* ??? */
2249 if (fir_io
&& smsc_ircc_open(fir_io
, sir_io
, ircc_dma
, ircc_irq
) == 0)
2252 /* Exit configuration */
2253 outb(SMSCSIO_CFGEXITKEY
, cfg_base
);
2259 static int __init
smsc_access(unsigned short cfg_base
, unsigned char reg
)
2261 IRDA_DEBUG(1, "%s\n", __func__
);
2263 outb(reg
, cfg_base
);
2264 return inb(cfg_base
) != reg
? -1 : 0;
2267 static const struct smsc_chip
* __init
smsc_ircc_probe(unsigned short cfg_base
, u8 reg
, const struct smsc_chip
*chip
, char *type
)
2269 u8 devid
, xdevid
, rev
;
2271 IRDA_DEBUG(1, "%s\n", __func__
);
2273 /* Leave configuration */
2275 outb(SMSCSIO_CFGEXITKEY
, cfg_base
);
2277 if (inb(cfg_base
) == SMSCSIO_CFGEXITKEY
) /* not a smc superio chip */
2280 outb(reg
, cfg_base
);
2282 xdevid
= inb(cfg_base
+ 1);
2284 /* Enter configuration */
2286 outb(SMSCSIO_CFGACCESSKEY
, cfg_base
);
2289 if (smsc_access(cfg_base
,0x55)) /* send second key and check */
2293 /* probe device ID */
2295 if (smsc_access(cfg_base
, reg
))
2298 devid
= inb(cfg_base
+ 1);
2300 if (devid
== 0 || devid
== 0xff) /* typical values for unused port */
2303 /* probe revision ID */
2305 if (smsc_access(cfg_base
, reg
+ 1))
2308 rev
= inb(cfg_base
+ 1);
2310 if (rev
>= 128) /* i think this will make no sense */
2313 if (devid
== xdevid
) /* protection against false positives */
2316 /* Check for expected device ID; are there others? */
2318 while (chip
->devid
!= devid
) {
2322 if (chip
->name
== NULL
)
2326 IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n",
2327 devid
, rev
, cfg_base
, type
, chip
->name
);
2329 if (chip
->rev
> rev
) {
2330 IRDA_MESSAGE("Revision higher than expected\n");
2334 if (chip
->flags
& NoIRDA
)
2335 IRDA_MESSAGE("chipset does not support IRDA\n");
2340 static int __init
smsc_superio_fdc(unsigned short cfg_base
)
2344 if (!request_region(cfg_base
, 2, driver_name
)) {
2345 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2346 __func__
, cfg_base
);
2348 if (!smsc_superio_flat(fdc_chips_flat
, cfg_base
, "FDC") ||
2349 !smsc_superio_paged(fdc_chips_paged
, cfg_base
, "FDC"))
2352 release_region(cfg_base
, 2);
2358 static int __init
smsc_superio_lpc(unsigned short cfg_base
)
2362 if (!request_region(cfg_base
, 2, driver_name
)) {
2363 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2364 __func__
, cfg_base
);
2366 if (!smsc_superio_flat(lpc_chips_flat
, cfg_base
, "LPC") ||
2367 !smsc_superio_paged(lpc_chips_paged
, cfg_base
, "LPC"))
2370 release_region(cfg_base
, 2);
2376 * Look for some specific subsystem setups that need
2377 * pre-configuration not properly done by the BIOS (especially laptops)
2378 * This code is based in part on smcinit.c, tosh1800-smcinit.c
2379 * and tosh2450-smcinit.c. The table lists the device entries
2380 * for ISA bridges with an LPC (Low Pin Count) controller which
2381 * handles the communication with the SMSC device. After the LPC
2382 * controller is initialized through PCI, the SMSC device is initialized
2383 * through a dedicated port in the ISA port-mapped I/O area, this latter
2384 * area is used to configure the SMSC device with default
2385 * SIR and FIR I/O ports, DMA and IRQ. Different vendors have
2386 * used different sets of parameters and different control port
2387 * addresses making a subsystem device table necessary.
2390 #define PCIID_VENDOR_INTEL 0x8086
2391 #define PCIID_VENDOR_ALI 0x10b9
2392 static struct smsc_ircc_subsystem_configuration subsystem_configurations
[] __initdata
= {
2394 * Subsystems needing entries:
2395 * 0x10b9:0x1533 0x103c:0x0850 HP nx9010 family
2396 * 0x10b9:0x1533 0x0e11:0x005a Compaq nc4000 family
2397 * 0x8086:0x24cc 0x0e11:0x002a HP nx9000 family
2401 .vendor
= PCIID_VENDOR_INTEL
, /* Intel 82801DBM LPC bridge */
2403 .subvendor
= 0x103c,
2404 .subdevice
= 0x08bc,
2410 .preconfigure
= preconfigure_through_82801
,
2411 .name
= "HP nx5000 family",
2414 .vendor
= PCIID_VENDOR_INTEL
, /* Intel 82801DBM LPC bridge */
2416 .subvendor
= 0x103c,
2417 .subdevice
= 0x088c,
2418 /* Quite certain these are the same for nc8000 as for nc6000 */
2424 .preconfigure
= preconfigure_through_82801
,
2425 .name
= "HP nc8000 family",
2428 .vendor
= PCIID_VENDOR_INTEL
, /* Intel 82801DBM LPC bridge */
2430 .subvendor
= 0x103c,
2431 .subdevice
= 0x0890,
2437 .preconfigure
= preconfigure_through_82801
,
2438 .name
= "HP nc6000 family",
2441 .vendor
= PCIID_VENDOR_INTEL
, /* Intel 82801DBM LPC bridge */
2443 .subvendor
= 0x0e11,
2444 .subdevice
= 0x0860,
2445 /* I assume these are the same for x1000 as for the others */
2451 .preconfigure
= preconfigure_through_82801
,
2452 .name
= "Compaq x1000 family",
2455 /* Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge */
2456 .vendor
= PCIID_VENDOR_INTEL
,
2458 .subvendor
= 0x1179,
2459 .subdevice
= 0xffff, /* 0xffff is "any" */
2465 .preconfigure
= preconfigure_through_82801
,
2466 .name
= "Toshiba laptop with Intel 82801DB/DBL LPC bridge",
2469 .vendor
= PCIID_VENDOR_INTEL
, /* Intel 82801CAM ISA bridge */
2471 .subvendor
= 0x1179,
2472 .subdevice
= 0xffff, /* 0xffff is "any" */
2478 .preconfigure
= preconfigure_through_82801
,
2479 .name
= "Toshiba laptop with Intel 82801CAM ISA bridge",
2482 /* 82801DBM (ICH4-M) LPC Interface Bridge */
2483 .vendor
= PCIID_VENDOR_INTEL
,
2485 .subvendor
= 0x1179,
2486 .subdevice
= 0xffff, /* 0xffff is "any" */
2492 .preconfigure
= preconfigure_through_82801
,
2493 .name
= "Toshiba laptop with Intel 8281DBM LPC bridge",
2496 /* ALi M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+] */
2497 .vendor
= PCIID_VENDOR_ALI
,
2499 .subvendor
= 0x1179,
2500 .subdevice
= 0xffff, /* 0xffff is "any" */
2506 .preconfigure
= preconfigure_through_ali
,
2507 .name
= "Toshiba laptop with ALi ISA bridge",
2514 * This sets up the basic SMSC parameters
2515 * (FIR port, SIR port, FIR DMA, FIR IRQ)
2516 * through the chip configuration port.
2518 static int __init
preconfigure_smsc_chip(struct
2519 smsc_ircc_subsystem_configuration
2522 unsigned short iobase
= conf
->cfg_base
;
2523 unsigned char tmpbyte
;
2525 outb(LPC47N227_CFGACCESSKEY
, iobase
); // enter configuration state
2526 outb(SMSCSIOFLAT_DEVICEID_REG
, iobase
); // set for device ID
2527 tmpbyte
= inb(iobase
+1); // Read device ID
2529 "Detected Chip id: 0x%02x, setting up registers...\n",
2532 /* Disable UART1 and set up SIR I/O port */
2533 outb(0x24, iobase
); // select CR24 - UART1 base addr
2534 outb(0x00, iobase
+ 1); // disable UART1
2535 outb(SMSCSIOFLAT_UART2BASEADDR_REG
, iobase
); // select CR25 - UART2 base addr
2536 outb( (conf
->sir_io
>> 2), iobase
+ 1); // bits 2-9 of 0x3f8
2537 tmpbyte
= inb(iobase
+ 1);
2538 if (tmpbyte
!= (conf
->sir_io
>> 2) ) {
2539 IRDA_WARNING("ERROR: could not configure SIR ioport.\n");
2540 IRDA_WARNING("Try to supply ircc_cfg argument.\n");
2544 /* Set up FIR IRQ channel for UART2 */
2545 outb(SMSCSIOFLAT_UARTIRQSELECT_REG
, iobase
); // select CR28 - UART1,2 IRQ select
2546 tmpbyte
= inb(iobase
+ 1);
2547 tmpbyte
&= SMSCSIOFLAT_UART1IRQSELECT_MASK
; // Do not touch the UART1 portion
2548 tmpbyte
|= (conf
->fir_irq
& SMSCSIOFLAT_UART2IRQSELECT_MASK
);
2549 outb(tmpbyte
, iobase
+ 1);
2550 tmpbyte
= inb(iobase
+ 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK
;
2551 if (tmpbyte
!= conf
->fir_irq
) {
2552 IRDA_WARNING("ERROR: could not configure FIR IRQ channel.\n");
2556 /* Set up FIR I/O port */
2557 outb(SMSCSIOFLAT_FIRBASEADDR_REG
, iobase
); // CR2B - SCE (FIR) base addr
2558 outb((conf
->fir_io
>> 3), iobase
+ 1);
2559 tmpbyte
= inb(iobase
+ 1);
2560 if (tmpbyte
!= (conf
->fir_io
>> 3) ) {
2561 IRDA_WARNING("ERROR: could not configure FIR I/O port.\n");
2565 /* Set up FIR DMA channel */
2566 outb(SMSCSIOFLAT_FIRDMASELECT_REG
, iobase
); // CR2C - SCE (FIR) DMA select
2567 outb((conf
->fir_dma
& LPC47N227_FIRDMASELECT_MASK
), iobase
+ 1); // DMA
2568 tmpbyte
= inb(iobase
+ 1) & LPC47N227_FIRDMASELECT_MASK
;
2569 if (tmpbyte
!= (conf
->fir_dma
& LPC47N227_FIRDMASELECT_MASK
)) {
2570 IRDA_WARNING("ERROR: could not configure FIR DMA channel.\n");
2574 outb(SMSCSIOFLAT_UARTMODE0C_REG
, iobase
); // CR0C - UART mode
2575 tmpbyte
= inb(iobase
+ 1);
2576 tmpbyte
&= ~SMSCSIOFLAT_UART2MODE_MASK
|
2577 SMSCSIOFLAT_UART2MODE_VAL_IRDA
;
2578 outb(tmpbyte
, iobase
+ 1); // enable IrDA (HPSIR) mode, high speed
2580 outb(LPC47N227_APMBOOTDRIVE_REG
, iobase
); // CR07 - Auto Pwr Mgt/boot drive sel
2581 tmpbyte
= inb(iobase
+ 1);
2582 outb(tmpbyte
| LPC47N227_UART2AUTOPWRDOWN_MASK
, iobase
+ 1); // enable UART2 autopower down
2584 /* This one was not part of tosh1800 */
2585 outb(0x0a, iobase
); // CR0a - ecp fifo / ir mux
2586 tmpbyte
= inb(iobase
+ 1);
2587 outb(tmpbyte
| 0x40, iobase
+ 1); // send active device to ir port
2589 outb(LPC47N227_UART12POWER_REG
, iobase
); // CR02 - UART 1,2 power
2590 tmpbyte
= inb(iobase
+ 1);
2591 outb(tmpbyte
| LPC47N227_UART2POWERDOWN_MASK
, iobase
+ 1); // UART2 power up mode, UART1 power down
2593 outb(LPC47N227_FDCPOWERVALIDCONF_REG
, iobase
); // CR00 - FDC Power/valid config cycle
2594 tmpbyte
= inb(iobase
+ 1);
2595 outb(tmpbyte
| LPC47N227_VALID_MASK
, iobase
+ 1); // valid config cycle done
2597 outb(LPC47N227_CFGEXITKEY
, iobase
); // Exit configuration
2602 /* 82801CAM generic registers */
2605 #define PIRQ_A_D_ROUT 0x60
2606 #define SIRQ_CNTL 0x64
2607 #define PIRQ_E_H_ROUT 0x68
2608 #define PCI_DMA_C 0x90
2609 /* LPC-specific registers */
2610 #define COM_DEC 0xe0
2611 #define GEN1_DEC 0xe4
2613 #define GEN2_DEC 0xec
2615 * Sets up the I/O range using the 82801CAM ISA bridge, 82801DBM LPC bridge
2616 * or Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge.
2617 * They all work the same way!
2619 static int __init
preconfigure_through_82801(struct pci_dev
*dev
,
2621 smsc_ircc_subsystem_configuration
2624 unsigned short tmpword
;
2625 unsigned char tmpbyte
;
2627 IRDA_MESSAGE("Setting up Intel 82801 controller and SMSC device\n");
2629 * Select the range for the COMA COM port (SIR)
2632 * Bit 6-4, COMB decode range
2634 * Bit 2-0, COMA decode range
2637 * 000 = 0x3f8-0x3ff (COM1)
2638 * 001 = 0x2f8-0x2ff (COM2)
2642 * 101 = 0x2e8-0x2ef (COM4)
2644 * 111 = 0x3e8-0x3ef (COM3)
2646 pci_read_config_byte(dev
, COM_DEC
, &tmpbyte
);
2647 tmpbyte
&= 0xf8; /* mask COMA bits */
2648 switch(conf
->sir_io
) {
2674 tmpbyte
|= 0x01; /* COM2 default */
2676 IRDA_DEBUG(1, "COM_DEC (write): 0x%02x\n", tmpbyte
);
2677 pci_write_config_byte(dev
, COM_DEC
, tmpbyte
);
2679 /* Enable Low Pin Count interface */
2680 pci_read_config_word(dev
, LPC_EN
, &tmpword
);
2681 /* These seem to be set up at all times,
2682 * just make sure it is properly set.
2684 switch(conf
->cfg_base
) {
2698 IRDA_WARNING("Uncommon I/O base address: 0x%04x\n",
2702 tmpword
&= 0xfffd; /* disable LPC COMB */
2703 tmpword
|= 0x0001; /* set bit 0 : enable LPC COMA addr range (GEN2) */
2704 IRDA_DEBUG(1, "LPC_EN (write): 0x%04x\n", tmpword
);
2705 pci_write_config_word(dev
, LPC_EN
, tmpword
);
2708 * Configure LPC DMA channel
2710 * Bit 15-14: DMA channel 7 select
2711 * Bit 13-12: DMA channel 6 select
2712 * Bit 11-10: DMA channel 5 select
2714 * Bit 7-6: DMA channel 3 select
2715 * Bit 5-4: DMA channel 2 select
2716 * Bit 3-2: DMA channel 1 select
2717 * Bit 1-0: DMA channel 0 select
2718 * 00 = Reserved value
2720 * 10 = Reserved value
2723 pci_read_config_word(dev
, PCI_DMA_C
, &tmpword
);
2724 switch(conf
->fir_dma
) {
2747 break; /* do not change settings */
2749 IRDA_DEBUG(1, "PCI_DMA_C (write): 0x%04x\n", tmpword
);
2750 pci_write_config_word(dev
, PCI_DMA_C
, tmpword
);
2754 * Bit 15-4: Generic I/O range
2755 * Bit 3-1: reserved (read as 0)
2756 * Bit 0: enable GEN2 range on LPC I/F
2758 tmpword
= conf
->fir_io
& 0xfff8;
2760 IRDA_DEBUG(1, "GEN2_DEC (write): 0x%04x\n", tmpword
);
2761 pci_write_config_word(dev
, GEN2_DEC
, tmpword
);
2763 /* Pre-configure chip */
2764 return preconfigure_smsc_chip(conf
);
2768 * Pre-configure a certain port on the ALi 1533 bridge.
2769 * This is based on reverse-engineering since ALi does not
2770 * provide any data sheet for the 1533 chip.
2772 static void __init
preconfigure_ali_port(struct pci_dev
*dev
,
2773 unsigned short port
)
2776 /* These bits obviously control the different ports */
2778 unsigned char tmpbyte
;
2799 IRDA_ERROR("Failed to configure unsupported port on ALi 1533 bridge: 0x%04x\n", port
);
2803 pci_read_config_byte(dev
, reg
, &tmpbyte
);
2804 /* Turn on the right bits */
2806 pci_write_config_byte(dev
, reg
, tmpbyte
);
2807 IRDA_MESSAGE("Activated ALi 1533 ISA bridge port 0x%04x.\n", port
);
2811 static int __init
preconfigure_through_ali(struct pci_dev
*dev
,
2813 smsc_ircc_subsystem_configuration
2816 /* Configure the two ports on the ALi 1533 */
2817 preconfigure_ali_port(dev
, conf
->sir_io
);
2818 preconfigure_ali_port(dev
, conf
->fir_io
);
2820 /* Pre-configure chip */
2821 return preconfigure_smsc_chip(conf
);
2824 static int __init
smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg
,
2825 unsigned short ircc_fir
,
2826 unsigned short ircc_sir
,
2827 unsigned char ircc_dma
,
2828 unsigned char ircc_irq
)
2830 struct pci_dev
*dev
= NULL
;
2831 unsigned short ss_vendor
= 0x0000;
2832 unsigned short ss_device
= 0x0000;
2835 dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
);
2837 while (dev
!= NULL
) {
2838 struct smsc_ircc_subsystem_configuration
*conf
;
2841 * Cache the subsystem vendor/device:
2842 * some manufacturers fail to set this for all components,
2843 * so we save it in case there is just 0x0000 0x0000 on the
2844 * device we want to check.
2846 if (dev
->subsystem_vendor
!= 0x0000U
) {
2847 ss_vendor
= dev
->subsystem_vendor
;
2848 ss_device
= dev
->subsystem_device
;
2850 conf
= subsystem_configurations
;
2851 for( ; conf
->subvendor
; conf
++) {
2852 if(conf
->vendor
== dev
->vendor
&&
2853 conf
->device
== dev
->device
&&
2854 conf
->subvendor
== ss_vendor
&&
2855 /* Sometimes these are cached values */
2856 (conf
->subdevice
== ss_device
||
2857 conf
->subdevice
== 0xffff)) {
2858 struct smsc_ircc_subsystem_configuration
2861 memcpy(&tmpconf
, conf
,
2862 sizeof(struct smsc_ircc_subsystem_configuration
));
2865 * Override the default values with anything
2866 * passed in as parameter
2869 tmpconf
.cfg_base
= ircc_cfg
;
2871 tmpconf
.fir_io
= ircc_fir
;
2873 tmpconf
.sir_io
= ircc_sir
;
2874 if (ircc_dma
!= DMA_INVAL
)
2875 tmpconf
.fir_dma
= ircc_dma
;
2876 if (ircc_irq
!= IRQ_INVAL
)
2877 tmpconf
.fir_irq
= ircc_irq
;
2879 IRDA_MESSAGE("Detected unconfigured %s SMSC IrDA chip, pre-configuring device.\n", conf
->name
);
2880 if (conf
->preconfigure
)
2881 ret
= conf
->preconfigure(dev
, &tmpconf
);
2886 dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
);
2891 #endif // CONFIG_PCI
2893 /************************************************
2895 * Transceivers specific functions
2897 ************************************************/
2901 * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed)
2903 * Program transceiver through smsc-ircc ATC circuitry
2907 static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base
, u32 speed
)
2909 unsigned long jiffies_now
, jiffies_timeout
;
2912 jiffies_now
= jiffies
;
2913 jiffies_timeout
= jiffies
+ SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES
;
2916 register_bank(fir_base
, 4);
2917 outb((inb(fir_base
+ IRCC_ATC
) & IRCC_ATC_MASK
) | IRCC_ATC_nPROGREADY
|IRCC_ATC_ENABLE
,
2918 fir_base
+ IRCC_ATC
);
2920 while ((val
= (inb(fir_base
+ IRCC_ATC
) & IRCC_ATC_nPROGREADY
)) &&
2921 !time_after(jiffies
, jiffies_timeout
))
2925 IRDA_WARNING("%s(): ATC: 0x%02x\n", __func__
,
2926 inb(fir_base
+ IRCC_ATC
));
2930 * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base)
2932 * Probe transceiver smsc-ircc ATC circuitry
2936 static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base
)
2942 * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed)
2948 static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base
, u32 speed
)
2959 fast_mode
= IRCC_LCR_A_FAST
;
2962 register_bank(fir_base
, 0);
2963 outb((inb(fir_base
+ IRCC_LCR_A
) & 0xbf) | fast_mode
, fir_base
+ IRCC_LCR_A
);
2967 * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base)
2973 static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base
)
2979 * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed)
2985 static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base
, u32 speed
)
2996 fast_mode
= /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA
;
3000 /* This causes an interrupt */
3001 register_bank(fir_base
, 0);
3002 outb((inb(fir_base
+ IRCC_LCR_A
) & 0xbf) | fast_mode
, fir_base
+ IRCC_LCR_A
);
3006 * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base)
3012 static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base
)
3018 module_init(smsc_ircc_init
);
3019 module_exit(smsc_ircc_cleanup
);