drivers/net/irda/via-ircc.h

   1 /*********************************************************************
   2  *
   3  * Filename:      via-ircc.h
   4  * Version:       1.0
   5  * Description:   Driver for the VIA VT8231/VT8233 IrDA chipsets
   6  * Author:        VIA Technologies, inc
   7  * Date  :        08/06/2003
   8
   9 Copyright (c) 1998-2003 VIA Technologies, Inc.
  10
  11 This program is free software; you can redistribute it and/or modify it under
  12 the terms of the GNU General Public License as published by the Free Software
  13 Foundation; either version 2, or (at your option) any later version.
  14
  15 This program is distributed in the hope that it will be useful, but WITHOUT
  16 ANY WARRANTIES OR REPRESENTATIONS; without even the implied warranty of
  17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  18 See the GNU General Public License for more details.
  19
  20 You should have received a copy of the GNU General Public License along with
  21 this program; if not, see <http://www.gnu.org/licenses/>.
  22
  23  * Comment:
  24  * jul/08/2002 : Rx buffer length should use Rx ring ptr.
  25  * Oct/28/2002 : Add SB id for 3147 and 3177.
  26  * jul/09/2002 : only implement two kind of dongle currently.
  27  * Oct/02/2002 : work on VT8231 and VT8233 .
  28  * Aug/06/2003 : change driver format to pci driver .
  29  ********************************************************************/
  30 #ifndef via_IRCC_H
  31 #define via_IRCC_H
  32 #include <linux/spinlock.h>
  33 #include <linux/pm.h>
  34 #include <linux/types.h>
  35 #include <asm/io.h>
  36
  37 #define MAX_TX_WINDOW 7
  38 #define MAX_RX_WINDOW 7
  39
  40 struct st_fifo_entry {
  41         int status;
  42         int len;
  43 };
  44
  45 struct st_fifo {
  46         struct st_fifo_entry entries[MAX_RX_WINDOW + 2];
  47         int pending_bytes;
  48         int head;
  49         int tail;
  50         int len;
  51 };
  52
  53 struct frame_cb {
  54         void *start;            /* Start of frame in DMA mem */
  55         int len;                /* Length of frame in DMA mem */
  56 };
  57
  58 struct tx_fifo {
  59         struct frame_cb queue[MAX_TX_WINDOW + 2];       /* Info about frames in queue */
  60         int ptr;                /* Currently being sent */
  61         int len;                /* Length of queue */
  62         int free;               /* Next free slot */
  63         void *tail;             /* Next free start in DMA mem */
  64 };
  65
  66
  67 struct eventflag                // for keeping track of Interrupt Events
  68 {
  69         //--------tx part
  70         unsigned char TxFIFOUnderRun;
  71         unsigned char EOMessage;
  72         unsigned char TxFIFOReady;
  73         unsigned char EarlyEOM;
  74         //--------rx part
  75         unsigned char PHYErr;
  76         unsigned char CRCErr;
  77         unsigned char RxFIFOOverRun;
  78         unsigned char EOPacket;
  79         unsigned char RxAvail;
  80         unsigned char TooLargePacket;
  81         unsigned char SIRBad;
  82         //--------unknown
  83         unsigned char Unknown;
  84         //----------
  85         unsigned char TimeOut;
  86         unsigned char RxDMATC;
  87         unsigned char TxDMATC;
  88 };
  89
  90 /* Private data for each instance */
  91 struct via_ircc_cb {
  92         struct st_fifo st_fifo; /* Info about received frames */
  93         struct tx_fifo tx_fifo; /* Info about frames to be transmitted */
  94
  95         struct net_device *netdev;      /* Yes! we are some kind of netdevice */
  96
  97         struct irlap_cb *irlap; /* The link layer we are binded to */
  98         struct qos_info qos;    /* QoS capabilities for this device */
  99
 100         chipio_t io;            /* IrDA controller information */
 101         iobuff_t tx_buff;       /* Transmit buffer */
 102         iobuff_t rx_buff;       /* Receive buffer */
 103         dma_addr_t tx_buff_dma;
 104         dma_addr_t rx_buff_dma;
 105
 106         __u8 ier;               /* Interrupt enable register */
 107
 108         spinlock_t lock;        /* For serializing operations */
 109
 110         __u32 flags;            /* Interface flags */
 111         __u32 new_speed;
 112         int index;              /* Instance index */
 113
 114         struct eventflag EventFlag;
 115         unsigned int chip_id;   /* to remember chip id */
 116         unsigned int RetryCount;
 117         unsigned int RxDataReady;
 118         unsigned int RxLastCount;
 119 };
 120
 121
 122 //---------I=Infrared,  H=Host, M=Misc, T=Tx, R=Rx, ST=Status,
 123 //         CF=Config, CT=Control, L=Low, H=High, C=Count
 124 #define  I_CF_L_0               0x10
 125 #define  I_CF_H_0               0x11
 126 #define  I_SIR_BOF              0x12
 127 #define  I_SIR_EOF              0x13
 128 #define  I_ST_CT_0              0x15
 129 #define  I_ST_L_1               0x16
 130 #define  I_ST_H_1               0x17
 131 #define  I_CF_L_1               0x18
 132 #define  I_CF_H_1               0x19
 133 #define  I_CF_L_2               0x1a
 134 #define  I_CF_H_2               0x1b
 135 #define  I_CF_3         0x1e
 136 #define  H_CT                   0x20
 137 #define  H_ST                   0x21
 138 #define  M_CT                   0x22
 139 #define  TX_CT_1                0x23
 140 #define  TX_CT_2                0x24
 141 #define  TX_ST                  0x25
 142 #define  RX_CT                  0x26
 143 #define  RX_ST                  0x27
 144 #define  RESET                  0x28
 145 #define  P_ADDR         0x29
 146 #define  RX_C_L         0x2a
 147 #define  RX_C_H         0x2b
 148 #define  RX_P_L         0x2c
 149 #define  RX_P_H         0x2d
 150 #define  TX_C_L         0x2e
 151 #define  TX_C_H         0x2f
 152 #define  TIMER          0x32
 153 #define  I_CF_4                 0x33
 154 #define  I_T_C_L                0x34
 155 #define  I_T_C_H                0x35
 156 #define  VERSION                0x3f
 157 //-------------------------------
 158 #define StartAddr       0x10    // the first register address
 159 #define EndAddr         0x3f    // the last register address
 160 #define GetBit(val,bit)  val = (unsigned char) ((val>>bit) & 0x1)
 161                         // Returns the bit
 162 #define SetBit(val,bit)  val= (unsigned char ) (val | (0x1 << bit))
 163                         // Sets bit to 1
 164 #define ResetBit(val,bit) val= (unsigned char ) (val & ~(0x1 << bit))
 165                         // Sets bit to 0
 166
 167 #define OFF   0
 168 #define ON   1
 169 #define DMA_TX_MODE   0x08
 170 #define DMA_RX_MODE   0x04
 171
 172 #define DMA1   0
 173 #define DMA2   0xc0
 174 #define MASK1   DMA1+0x0a
 175 #define MASK2   DMA2+0x14
 176
 177 #define Clk_bit 0x40
 178 #define Tx_bit 0x01
 179 #define Rd_Valid 0x08
 180 #define RxBit 0x08
 181
 182 static void DisableDmaChannel(unsigned int channel)
 183 {
 184         switch (channel) {      // 8 Bit DMA channels DMAC1
 185         case 0:
 186                 outb(4, MASK1); //mask channel 0
 187                 break;
 188         case 1:
 189                 outb(5, MASK1); //Mask channel 1
 190                 break;
 191         case 2:
 192                 outb(6, MASK1); //Mask channel 2
 193                 break;
 194         case 3:
 195                 outb(7, MASK1); //Mask channel 3
 196                 break;
 197         case 5:
 198                 outb(5, MASK2); //Mask channel 5
 199                 break;
 200         case 6:
 201                 outb(6, MASK2); //Mask channel 6
 202                 break;
 203         case 7:
 204                 outb(7, MASK2); //Mask channel 7
 205                 break;
 206         default:
 207                 break;
 208         }
 209 }
 210
 211 static unsigned char ReadLPCReg(int iRegNum)
 212 {
 213         unsigned char iVal;
 214
 215         outb(0x87, 0x2e);
 216         outb(0x87, 0x2e);
 217         outb(iRegNum, 0x2e);
 218         iVal = inb(0x2f);
 219         outb(0xaa, 0x2e);
 220
 221         return iVal;
 222 }
 223
 224 static void WriteLPCReg(int iRegNum, unsigned char iVal)
 225 {
 226
 227         outb(0x87, 0x2e);
 228         outb(0x87, 0x2e);
 229         outb(iRegNum, 0x2e);
 230         outb(iVal, 0x2f);
 231         outb(0xAA, 0x2e);
 232 }
 233
 234 static __u8 ReadReg(unsigned int BaseAddr, int iRegNum)
 235 {
 236         return (__u8) inb(BaseAddr + iRegNum);
 237 }
 238
 239 static void WriteReg(unsigned int BaseAddr, int iRegNum, unsigned char iVal)
 240 {
 241         outb(iVal, BaseAddr + iRegNum);
 242 }
 243
 244 static int WriteRegBit(unsigned int BaseAddr, unsigned char RegNum,
 245                 unsigned char BitPos, unsigned char value)
 246 {
 247         __u8 Rtemp, Wtemp;
 248
 249         if (BitPos > 7) {
 250                 return -1;
 251         }
 252         if ((RegNum < StartAddr) || (RegNum > EndAddr))
 253                 return -1;
 254         Rtemp = ReadReg(BaseAddr, RegNum);
 255         if (value == 0)
 256                 Wtemp = ResetBit(Rtemp, BitPos);
 257         else {
 258                 if (value == 1)
 259                         Wtemp = SetBit(Rtemp, BitPos);
 260                 else
 261                         return -1;
 262         }
 263         WriteReg(BaseAddr, RegNum, Wtemp);
 264         return 0;
 265 }
 266
 267 static __u8 CheckRegBit(unsigned int BaseAddr, unsigned char RegNum,
 268                  unsigned char BitPos)
 269 {
 270         __u8 temp;
 271
 272         if (BitPos > 7)
 273                 return 0xff;
 274         if ((RegNum < StartAddr) || (RegNum > EndAddr)) {
 275 //     printf("what is the register %x!\n",RegNum);
 276         }
 277         temp = ReadReg(BaseAddr, RegNum);
 278         return GetBit(temp, BitPos);
 279 }
 280
 281 static void SetMaxRxPacketSize(__u16 iobase, __u16 size)
 282 {
 283         __u16 low, high;
 284         if ((size & 0xe000) == 0) {
 285                 low = size & 0x00ff;
 286                 high = (size & 0x1f00) >> 8;
 287                 WriteReg(iobase, I_CF_L_2, low);
 288                 WriteReg(iobase, I_CF_H_2, high);
 289
 290         }
 291
 292 }
 293
 294 //for both Rx and Tx
 295
 296 static void SetFIFO(__u16 iobase, __u16 value)
 297 {
 298         switch (value) {
 299         case 128:
 300                 WriteRegBit(iobase, 0x11, 0, 0);
 301                 WriteRegBit(iobase, 0x11, 7, 1);
 302                 break;
 303         case 64:
 304                 WriteRegBit(iobase, 0x11, 0, 0);
 305                 WriteRegBit(iobase, 0x11, 7, 0);
 306                 break;
 307         case 32:
 308                 WriteRegBit(iobase, 0x11, 0, 1);
 309                 WriteRegBit(iobase, 0x11, 7, 0);
 310                 break;
 311         default:
 312                 WriteRegBit(iobase, 0x11, 0, 0);
 313                 WriteRegBit(iobase, 0x11, 7, 0);
 314         }
 315
 316 }
 317
 318 #define CRC16(BaseAddr,val)         WriteRegBit(BaseAddr,I_CF_L_0,7,val)        //0 for 32 CRC
 319 /*
 320 #define SetVFIR(BaseAddr,val)       WriteRegBit(BaseAddr,I_CF_H_0,5,val)
 321 #define SetFIR(BaseAddr,val)        WriteRegBit(BaseAddr,I_CF_L_0,6,val)
 322 #define SetMIR(BaseAddr,val)        WriteRegBit(BaseAddr,I_CF_L_0,5,val)
 323 #define SetSIR(BaseAddr,val)        WriteRegBit(BaseAddr,I_CF_L_0,4,val)
 324 */
 325 #define SIRFilter(BaseAddr,val)     WriteRegBit(BaseAddr,I_CF_L_0,3,val)
 326 #define Filter(BaseAddr,val)        WriteRegBit(BaseAddr,I_CF_L_0,2,val)
 327 #define InvertTX(BaseAddr,val)      WriteRegBit(BaseAddr,I_CF_L_0,1,val)
 328 #define InvertRX(BaseAddr,val)      WriteRegBit(BaseAddr,I_CF_L_0,0,val)
 329 //****************************I_CF_H_0
 330 #define EnableTX(BaseAddr,val)      WriteRegBit(BaseAddr,I_CF_H_0,4,val)
 331 #define EnableRX(BaseAddr,val)      WriteRegBit(BaseAddr,I_CF_H_0,3,val)
 332 #define EnableDMA(BaseAddr,val)     WriteRegBit(BaseAddr,I_CF_H_0,2,val)
 333 #define SIRRecvAny(BaseAddr,val)    WriteRegBit(BaseAddr,I_CF_H_0,1,val)
 334 #define DiableTrans(BaseAddr,val)   WriteRegBit(BaseAddr,I_CF_H_0,0,val)
 335 //***************************I_SIR_BOF,I_SIR_EOF
 336 #define SetSIRBOF(BaseAddr,val)     WriteReg(BaseAddr,I_SIR_BOF,val)
 337 #define SetSIREOF(BaseAddr,val)     WriteReg(BaseAddr,I_SIR_EOF,val)
 338 #define GetSIRBOF(BaseAddr)        ReadReg(BaseAddr,I_SIR_BOF)
 339 #define GetSIREOF(BaseAddr)        ReadReg(BaseAddr,I_SIR_EOF)
 340 //*******************I_ST_CT_0
 341 #define EnPhys(BaseAddr,val)   WriteRegBit(BaseAddr,I_ST_CT_0,7,val)
 342 #define IsModeError(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,6) //RO
 343 #define IsVFIROn(BaseAddr)     CheckRegBit(BaseAddr,0x14,0)     //RO for VT1211 only
 344 #define IsFIROn(BaseAddr)     CheckRegBit(BaseAddr,I_ST_CT_0,5) //RO
 345 #define IsMIROn(BaseAddr)     CheckRegBit(BaseAddr,I_ST_CT_0,4) //RO
 346 #define IsSIROn(BaseAddr)     CheckRegBit(BaseAddr,I_ST_CT_0,3) //RO
 347 #define IsEnableTX(BaseAddr)  CheckRegBit(BaseAddr,I_ST_CT_0,2) //RO
 348 #define IsEnableRX(BaseAddr)  CheckRegBit(BaseAddr,I_ST_CT_0,1) //RO
 349 #define Is16CRC(BaseAddr)     CheckRegBit(BaseAddr,I_ST_CT_0,0) //RO
 350 //***************************I_CF_3
 351 #define DisableAdjacentPulseWidth(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_3,5,val)      //1 disable
 352 #define DisablePulseWidthAdjust(BaseAddr,val)   WriteRegBit(BaseAddr,I_CF_3,4,val)      //1 disable
 353 #define UseOneRX(BaseAddr,val)                  WriteRegBit(BaseAddr,I_CF_3,1,val)      //0 use two RX
 354 #define SlowIRRXLowActive(BaseAddr,val)         WriteRegBit(BaseAddr,I_CF_3,0,val)      //0 show RX high=1 in SIR
 355 //***************************H_CT
 356 #define EnAllInt(BaseAddr,val)   WriteRegBit(BaseAddr,H_CT,7,val)
 357 #define TXStart(BaseAddr,val)    WriteRegBit(BaseAddr,H_CT,6,val)
 358 #define RXStart(BaseAddr,val)    WriteRegBit(BaseAddr,H_CT,5,val)
 359 #define ClearRXInt(BaseAddr,val)   WriteRegBit(BaseAddr,H_CT,4,val)     // 1 clear
 360 //*****************H_ST
 361 #define IsRXInt(BaseAddr)           CheckRegBit(BaseAddr,H_ST,4)
 362 #define GetIntIndentify(BaseAddr)   ((ReadReg(BaseAddr,H_ST)&0xf1) >>1)
 363 #define IsHostBusy(BaseAddr)        CheckRegBit(BaseAddr,H_ST,0)
 364 #define GetHostStatus(BaseAddr)     ReadReg(BaseAddr,H_ST)      //RO
 365 //**************************M_CT
 366 #define EnTXDMA(BaseAddr,val)         WriteRegBit(BaseAddr,M_CT,7,val)
 367 #define EnRXDMA(BaseAddr,val)         WriteRegBit(BaseAddr,M_CT,6,val)
 368 #define SwapDMA(BaseAddr,val)         WriteRegBit(BaseAddr,M_CT,5,val)
 369 #define EnInternalLoop(BaseAddr,val)  WriteRegBit(BaseAddr,M_CT,4,val)
 370 #define EnExternalLoop(BaseAddr,val)  WriteRegBit(BaseAddr,M_CT,3,val)
 371 //**************************TX_CT_1
 372 #define EnTXFIFOHalfLevelInt(BaseAddr,val)   WriteRegBit(BaseAddr,TX_CT_1,4,val)        //half empty int (1 half)
 373 #define EnTXFIFOUnderrunEOMInt(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_1,5,val)
 374 #define EnTXFIFOReadyInt(BaseAddr,val)       WriteRegBit(BaseAddr,TX_CT_1,6,val)        //int when reach it threshold (setting by bit 4)
 375 //**************************TX_CT_2
 376 #define ForceUnderrun(BaseAddr,val)   WriteRegBit(BaseAddr,TX_CT_2,7,val)       // force an underrun int
 377 #define EnTXCRC(BaseAddr,val)         WriteRegBit(BaseAddr,TX_CT_2,6,val)       //1 for FIR,MIR...0 (not SIR)
 378 #define ForceBADCRC(BaseAddr,val)     WriteRegBit(BaseAddr,TX_CT_2,5,val)       //force an bad CRC
 379 #define SendSIP(BaseAddr,val)         WriteRegBit(BaseAddr,TX_CT_2,4,val)       //send indication pulse for prevent SIR disturb
 380 #define ClearEnTX(BaseAddr,val)       WriteRegBit(BaseAddr,TX_CT_2,3,val)       // opposite to EnTX
 381 //*****************TX_ST
 382 #define GetTXStatus(BaseAddr)   ReadReg(BaseAddr,TX_ST) //RO
 383 //**************************RX_CT
 384 #define EnRXSpecInt(BaseAddr,val)           WriteRegBit(BaseAddr,RX_CT,0,val)
 385 #define EnRXFIFOReadyInt(BaseAddr,val)      WriteRegBit(BaseAddr,RX_CT,1,val)   //enable int when reach it threshold (setting by bit 7)
 386 #define EnRXFIFOHalfLevelInt(BaseAddr,val)  WriteRegBit(BaseAddr,RX_CT,7,val)   //enable int when (1) half full...or (0) just not full
 387 //*****************RX_ST
 388 #define GetRXStatus(BaseAddr)   ReadReg(BaseAddr,RX_ST) //RO
 389 //***********************P_ADDR
 390 #define SetPacketAddr(BaseAddr,addr)        WriteReg(BaseAddr,P_ADDR,addr)
 391 //***********************I_CF_4
 392 #define EnGPIOtoRX2(BaseAddr,val)       WriteRegBit(BaseAddr,I_CF_4,7,val)
 393 #define EnTimerInt(BaseAddr,val)                WriteRegBit(BaseAddr,I_CF_4,1,val)
 394 #define ClearTimerInt(BaseAddr,val)     WriteRegBit(BaseAddr,I_CF_4,0,val)
 395 //***********************I_T_C_L
 396 #define WriteGIO(BaseAddr,val)      WriteRegBit(BaseAddr,I_T_C_L,7,val)
 397 #define ReadGIO(BaseAddr)                   CheckRegBit(BaseAddr,I_T_C_L,7)
 398 #define ReadRX(BaseAddr)                    CheckRegBit(BaseAddr,I_T_C_L,3)     //RO
 399 #define WriteTX(BaseAddr,val)           WriteRegBit(BaseAddr,I_T_C_L,0,val)
 400 //***********************I_T_C_H
 401 #define EnRX2(BaseAddr,val)                 WriteRegBit(BaseAddr,I_T_C_H,7,val)
 402 #define ReadRX2(BaseAddr)           CheckRegBit(BaseAddr,I_T_C_H,7)
 403 //**********************Version
 404 #define GetFIRVersion(BaseAddr)         ReadReg(BaseAddr,VERSION)
 405
 406
 407 static void SetTimer(__u16 iobase, __u8 count)
 408 {
 409         EnTimerInt(iobase, OFF);
 410         WriteReg(iobase, TIMER, count);
 411         EnTimerInt(iobase, ON);
 412 }
 413
 414
 415 static void SetSendByte(__u16 iobase, __u32 count)
 416 {
 417         __u32 low, high;
 418
 419         if ((count & 0xf000) == 0) {
 420                 low = count & 0x00ff;
 421                 high = (count & 0x0f00) >> 8;
 422                 WriteReg(iobase, TX_C_L, low);
 423                 WriteReg(iobase, TX_C_H, high);
 424         }
 425 }
 426
 427 static void ResetChip(__u16 iobase, __u8 type)
 428 {
 429         __u8 value;
 430
 431         value = (type + 2) << 4;
 432         WriteReg(iobase, RESET, type);
 433 }
 434
 435 static int CkRxRecv(__u16 iobase, struct via_ircc_cb *self)
 436 {
 437         __u8 low, high;
 438         __u16 wTmp = 0, wTmp1 = 0, wTmp_new = 0;
 439
 440         low = ReadReg(iobase, RX_C_L);
 441         high = ReadReg(iobase, RX_C_H);
 442         wTmp1 = high;
 443         wTmp = (wTmp1 << 8) | low;
 444         udelay(10);
 445         low = ReadReg(iobase, RX_C_L);
 446         high = ReadReg(iobase, RX_C_H);
 447         wTmp1 = high;
 448         wTmp_new = (wTmp1 << 8) | low;
 449         if (wTmp_new != wTmp)
 450                 return 1;
 451         else
 452                 return 0;
 453
 454 }
 455
 456 static __u16 RxCurCount(__u16 iobase, struct via_ircc_cb * self)
 457 {
 458         __u8 low, high;
 459         __u16 wTmp = 0, wTmp1 = 0;
 460
 461         low = ReadReg(iobase, RX_P_L);
 462         high = ReadReg(iobase, RX_P_H);
 463         wTmp1 = high;
 464         wTmp = (wTmp1 << 8) | low;
 465         return wTmp;
 466 }
 467
 468 /* This Routine can only use in recevie_complete
 469  * for it will update last count.
 470  */
 471
 472 static __u16 GetRecvByte(__u16 iobase, struct via_ircc_cb * self)
 473 {
 474         __u8 low, high;
 475         __u16 wTmp, wTmp1, ret;
 476
 477         low = ReadReg(iobase, RX_P_L);
 478         high = ReadReg(iobase, RX_P_H);
 479         wTmp1 = high;
 480         wTmp = (wTmp1 << 8) | low;
 481
 482
 483         if (wTmp >= self->RxLastCount)
 484                 ret = wTmp - self->RxLastCount;
 485         else
 486                 ret = (0x8000 - self->RxLastCount) + wTmp;
 487         self->RxLastCount = wTmp;
 488
 489 /* RX_P is more actually the RX_C
 490  low=ReadReg(iobase,RX_C_L);
 491  high=ReadReg(iobase,RX_C_H);
 492
 493  if(!(high&0xe000)) {
 494          temp=(high<<8)+low;
 495          return temp;
 496  }
 497  else return 0;
 498 */
 499         return ret;
 500 }
 501
 502 static void Sdelay(__u16 scale)
 503 {
 504         __u8 bTmp;
 505         int i, j;
 506
 507         for (j = 0; j < scale; j++) {
 508                 for (i = 0; i < 0x20; i++) {
 509                         bTmp = inb(0xeb);
 510                         outb(bTmp, 0xeb);
 511                 }
 512         }
 513 }
 514
 515 static void Tdelay(__u16 scale)
 516 {
 517         __u8 bTmp;
 518         int i, j;
 519
 520         for (j = 0; j < scale; j++) {
 521                 for (i = 0; i < 0x50; i++) {
 522                         bTmp = inb(0xeb);
 523                         outb(bTmp, 0xeb);
 524                 }
 525         }
 526 }
 527
 528
 529 static void ActClk(__u16 iobase, __u8 value)
 530 {
 531         __u8 bTmp;
 532         bTmp = ReadReg(iobase, 0x34);
 533         if (value)
 534                 WriteReg(iobase, 0x34, bTmp | Clk_bit);
 535         else
 536                 WriteReg(iobase, 0x34, bTmp & ~Clk_bit);
 537 }
 538
 539 static void ClkTx(__u16 iobase, __u8 Clk, __u8 Tx)
 540 {
 541         __u8 bTmp;
 542
 543         bTmp = ReadReg(iobase, 0x34);
 544         if (Clk == 0)
 545                 bTmp &= ~Clk_bit;
 546         else {
 547                 if (Clk == 1)
 548                         bTmp |= Clk_bit;
 549         }
 550         WriteReg(iobase, 0x34, bTmp);
 551         Sdelay(1);
 552         if (Tx == 0)
 553                 bTmp &= ~Tx_bit;
 554         else {
 555                 if (Tx == 1)
 556                         bTmp |= Tx_bit;
 557         }
 558         WriteReg(iobase, 0x34, bTmp);
 559 }
 560
 561 static void Wr_Byte(__u16 iobase, __u8 data)
 562 {
 563         __u8 bData = data;
 564 //      __u8 btmp;
 565         int i;
 566
 567         ClkTx(iobase, 0, 1);
 568
 569         Tdelay(2);
 570         ActClk(iobase, 1);
 571         Tdelay(1);
 572
 573         for (i = 0; i < 8; i++) {       //LDN
 574
 575                 if ((bData >> i) & 0x01) {
 576                         ClkTx(iobase, 0, 1);    //bit data = 1;
 577                 } else {
 578                         ClkTx(iobase, 0, 0);    //bit data = 1;
 579                 }
 580                 Tdelay(2);
 581                 Sdelay(1);
 582                 ActClk(iobase, 1);      //clk hi
 583                 Tdelay(1);
 584         }
 585 }
 586
 587 static __u8 Rd_Indx(__u16 iobase, __u8 addr, __u8 index)
 588 {
 589         __u8 data = 0, bTmp, data_bit;
 590         int i;
 591
 592         bTmp = addr | (index << 1) | 0;
 593         ClkTx(iobase, 0, 0);
 594         Tdelay(2);
 595         ActClk(iobase, 1);
 596         udelay(1);
 597         Wr_Byte(iobase, bTmp);
 598         Sdelay(1);
 599         ClkTx(iobase, 0, 0);
 600         Tdelay(2);
 601         for (i = 0; i < 10; i++) {
 602                 ActClk(iobase, 1);
 603                 Tdelay(1);
 604                 ActClk(iobase, 0);
 605                 Tdelay(1);
 606                 ClkTx(iobase, 0, 1);
 607                 Tdelay(1);
 608                 bTmp = ReadReg(iobase, 0x34);
 609                 if (!(bTmp & Rd_Valid))
 610                         break;
 611         }
 612         if (!(bTmp & Rd_Valid)) {
 613                 for (i = 0; i < 8; i++) {
 614                         ActClk(iobase, 1);
 615                         Tdelay(1);
 616                         ActClk(iobase, 0);
 617                         bTmp = ReadReg(iobase, 0x34);
 618                         data_bit = 1 << i;
 619                         if (bTmp & RxBit)
 620                                 data |= data_bit;
 621                         else
 622                                 data &= ~data_bit;
 623                         Tdelay(2);
 624                 }
 625         } else {
 626                 for (i = 0; i < 2; i++) {
 627                         ActClk(iobase, 1);
 628                         Tdelay(1);
 629                         ActClk(iobase, 0);
 630                         Tdelay(2);
 631                 }
 632                 bTmp = ReadReg(iobase, 0x34);
 633         }
 634         for (i = 0; i < 1; i++) {
 635                 ActClk(iobase, 1);
 636                 Tdelay(1);
 637                 ActClk(iobase, 0);
 638                 Tdelay(2);
 639         }
 640         ClkTx(iobase, 0, 0);
 641         Tdelay(1);
 642         for (i = 0; i < 3; i++) {
 643                 ActClk(iobase, 1);
 644                 Tdelay(1);
 645                 ActClk(iobase, 0);
 646                 Tdelay(2);
 647         }
 648         return data;
 649 }
 650
 651 static void Wr_Indx(__u16 iobase, __u8 addr, __u8 index, __u8 data)
 652 {
 653         int i;
 654         __u8 bTmp;
 655
 656         ClkTx(iobase, 0, 0);
 657         udelay(2);
 658         ActClk(iobase, 1);
 659         udelay(1);
 660         bTmp = addr | (index << 1) | 1;
 661         Wr_Byte(iobase, bTmp);
 662         Wr_Byte(iobase, data);
 663         for (i = 0; i < 2; i++) {
 664                 ClkTx(iobase, 0, 0);
 665                 Tdelay(2);
 666                 ActClk(iobase, 1);
 667                 Tdelay(1);
 668         }
 669         ActClk(iobase, 0);
 670 }
 671
 672 static void ResetDongle(__u16 iobase)
 673 {
 674         int i;
 675         ClkTx(iobase, 0, 0);
 676         Tdelay(1);
 677         for (i = 0; i < 30; i++) {
 678                 ActClk(iobase, 1);
 679                 Tdelay(1);
 680                 ActClk(iobase, 0);
 681                 Tdelay(1);
 682         }
 683         ActClk(iobase, 0);
 684 }
 685
 686 static void SetSITmode(__u16 iobase)
 687 {
 688
 689         __u8 bTmp;
 690
 691         bTmp = ReadLPCReg(0x28);
 692         WriteLPCReg(0x28, bTmp | 0x10); //select ITMOFF
 693         bTmp = ReadReg(iobase, 0x35);
 694         WriteReg(iobase, 0x35, bTmp | 0x40);    // Driver ITMOFF
 695         WriteReg(iobase, 0x28, bTmp | 0x80);    // enable All interrupt
 696 }
 697
 698 static void SI_SetMode(__u16 iobase, int mode)
 699 {
 700         //__u32 dTmp;
 701         __u8 bTmp;
 702
 703         WriteLPCReg(0x28, 0x70);        // S/W Reset
 704         SetSITmode(iobase);
 705         ResetDongle(iobase);
 706         udelay(10);
 707         Wr_Indx(iobase, 0x40, 0x0, 0x17);       //RX ,APEN enable,Normal power
 708         Wr_Indx(iobase, 0x40, 0x1, mode);       //Set Mode
 709         Wr_Indx(iobase, 0x40, 0x2, 0xff);       //Set power to FIR VFIR > 1m
 710         bTmp = Rd_Indx(iobase, 0x40, 1);
 711 }
 712
 713 static void InitCard(__u16 iobase)
 714 {
 715         ResetChip(iobase, 5);
 716         WriteReg(iobase, I_ST_CT_0, 0x00);      // open CHIP on
 717         SetSIRBOF(iobase, 0xc0);        // hardware default value
 718         SetSIREOF(iobase, 0xc1);
 719 }
 720
 721 static void CommonInit(__u16 iobase)
 722 {
 723 //  EnTXCRC(iobase,0);
 724         SwapDMA(iobase, OFF);
 725         SetMaxRxPacketSize(iobase, 0x0fff);     //set to max:4095
 726         EnRXFIFOReadyInt(iobase, OFF);
 727         EnRXFIFOHalfLevelInt(iobase, OFF);
 728         EnTXFIFOHalfLevelInt(iobase, OFF);
 729         EnTXFIFOUnderrunEOMInt(iobase, ON);
 730 //  EnTXFIFOReadyInt(iobase,ON);
 731         InvertTX(iobase, OFF);
 732         InvertRX(iobase, OFF);
 733 //  WriteLPCReg(0xF0,0); //(if VT1211 then do this)
 734         if (IsSIROn(iobase)) {
 735                 SIRFilter(iobase, ON);
 736                 SIRRecvAny(iobase, ON);
 737         } else {
 738                 SIRFilter(iobase, OFF);
 739                 SIRRecvAny(iobase, OFF);
 740         }
 741         EnRXSpecInt(iobase, ON);
 742         WriteReg(iobase, I_ST_CT_0, 0x80);
 743         EnableDMA(iobase, ON);
 744 }
 745
 746 static void SetBaudRate(__u16 iobase, __u32 rate)
 747 {
 748         __u8 value = 11, temp;
 749
 750         if (IsSIROn(iobase)) {
 751                 switch (rate) {
 752                 case (__u32) (2400L):
 753                         value = 47;
 754                         break;
 755                 case (__u32) (9600L):
 756                         value = 11;
 757                         break;
 758                 case (__u32) (19200L):
 759                         value = 5;
 760                         break;
 761                 case (__u32) (38400L):
 762                         value = 2;
 763                         break;
 764                 case (__u32) (57600L):
 765                         value = 1;
 766                         break;
 767                 case (__u32) (115200L):
 768                         value = 0;
 769                         break;
 770                 default:
 771                         break;
 772                 }
 773         } else if (IsMIROn(iobase)) {
 774                 value = 0;      // will automatically be fixed in 1.152M
 775         } else if (IsFIROn(iobase)) {
 776                 value = 0;      // will automatically be fixed in 4M
 777         }
 778         temp = (ReadReg(iobase, I_CF_H_1) & 0x03);
 779         temp |= value << 2;
 780         WriteReg(iobase, I_CF_H_1, temp);
 781 }
 782
 783 static void SetPulseWidth(__u16 iobase, __u8 width)
 784 {
 785         __u8 temp, temp1, temp2;
 786
 787         temp = (ReadReg(iobase, I_CF_L_1) & 0x1f);
 788         temp1 = (ReadReg(iobase, I_CF_H_1) & 0xfc);
 789         temp2 = (width & 0x07) << 5;
 790         temp |= temp2;
 791         temp2 = (width & 0x18) >> 3;
 792         temp1 |= temp2;
 793         WriteReg(iobase, I_CF_L_1, temp);
 794         WriteReg(iobase, I_CF_H_1, temp1);
 795 }
 796
 797 static void SetSendPreambleCount(__u16 iobase, __u8 count)
 798 {
 799         __u8 temp;
 800
 801         temp = ReadReg(iobase, I_CF_L_1) & 0xe0;
 802         temp |= count;
 803         WriteReg(iobase, I_CF_L_1, temp);
 804
 805 }
 806
 807 static void SetVFIR(__u16 BaseAddr, __u8 val)
 808 {
 809         __u8 tmp;
 810
 811         tmp = ReadReg(BaseAddr, I_CF_L_0);
 812         WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);
 813         WriteRegBit(BaseAddr, I_CF_H_0, 5, val);
 814 }
 815
 816 static void SetFIR(__u16 BaseAddr, __u8 val)
 817 {
 818         __u8 tmp;
 819
 820         WriteRegBit(BaseAddr, I_CF_H_0, 5, 0);
 821         tmp = ReadReg(BaseAddr, I_CF_L_0);
 822         WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);
 823         WriteRegBit(BaseAddr, I_CF_L_0, 6, val);
 824 }
 825
 826 static void SetMIR(__u16 BaseAddr, __u8 val)
 827 {
 828         __u8 tmp;
 829
 830         WriteRegBit(BaseAddr, I_CF_H_0, 5, 0);
 831         tmp = ReadReg(BaseAddr, I_CF_L_0);
 832         WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);
 833         WriteRegBit(BaseAddr, I_CF_L_0, 5, val);
 834 }
 835
 836 static void SetSIR(__u16 BaseAddr, __u8 val)
 837 {
 838         __u8 tmp;
 839
 840         WriteRegBit(BaseAddr, I_CF_H_0, 5, 0);
 841         tmp = ReadReg(BaseAddr, I_CF_L_0);
 842         WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);
 843         WriteRegBit(BaseAddr, I_CF_L_0, 4, val);
 844 }
 845
 846 #endif                          /* via_IRCC_H */