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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/drzeus/mmc
[deliverable/linux.git] / drivers / net / ixgb / ixgb_hw.c
1 /*******************************************************************************
2
3 Intel PRO/10GbE Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /* ixgb_hw.c
30 * Shared functions for accessing and configuring the adapter
31 */
32
33 #include "ixgb_hw.h"
34 #include "ixgb_ids.h"
35
36 /* Local function prototypes */
37
38 static uint32_t ixgb_hash_mc_addr(struct ixgb_hw *hw, uint8_t * mc_addr);
39
40 static void ixgb_mta_set(struct ixgb_hw *hw, uint32_t hash_value);
41
42 static void ixgb_get_bus_info(struct ixgb_hw *hw);
43
44 static boolean_t ixgb_link_reset(struct ixgb_hw *hw);
45
46 static void ixgb_optics_reset(struct ixgb_hw *hw);
47
48 static ixgb_phy_type ixgb_identify_phy(struct ixgb_hw *hw);
49
50 static void ixgb_clear_hw_cntrs(struct ixgb_hw *hw);
51
52 static void ixgb_clear_vfta(struct ixgb_hw *hw);
53
54 static void ixgb_init_rx_addrs(struct ixgb_hw *hw);
55
56 static uint16_t ixgb_read_phy_reg(struct ixgb_hw *hw,
57 uint32_t reg_address,
58 uint32_t phy_address,
59 uint32_t device_type);
60
61 static boolean_t ixgb_setup_fc(struct ixgb_hw *hw);
62
63 static boolean_t mac_addr_valid(uint8_t *mac_addr);
64
65 static uint32_t ixgb_mac_reset(struct ixgb_hw *hw)
66 {
67 uint32_t ctrl_reg;
68
69 ctrl_reg = IXGB_CTRL0_RST |
70 IXGB_CTRL0_SDP3_DIR | /* All pins are Output=1 */
71 IXGB_CTRL0_SDP2_DIR |
72 IXGB_CTRL0_SDP1_DIR |
73 IXGB_CTRL0_SDP0_DIR |
74 IXGB_CTRL0_SDP3 | /* Initial value 1101 */
75 IXGB_CTRL0_SDP2 |
76 IXGB_CTRL0_SDP0;
77
78 #ifdef HP_ZX1
79 /* Workaround for 82597EX reset errata */
80 IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg);
81 #else
82 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
83 #endif
84
85 /* Delay a few ms just to allow the reset to complete */
86 msleep(IXGB_DELAY_AFTER_RESET);
87 ctrl_reg = IXGB_READ_REG(hw, CTRL0);
88 #ifdef DBG
89 /* Make sure the self-clearing global reset bit did self clear */
90 ASSERT(!(ctrl_reg & IXGB_CTRL0_RST));
91 #endif
92
93 if (hw->phy_type == ixgb_phy_type_txn17401) {
94 ixgb_optics_reset(hw);
95 }
96
97 return ctrl_reg;
98 }
99
100 /******************************************************************************
101 * Reset the transmit and receive units; mask and clear all interrupts.
102 *
103 * hw - Struct containing variables accessed by shared code
104 *****************************************************************************/
105 boolean_t
106 ixgb_adapter_stop(struct ixgb_hw *hw)
107 {
108 uint32_t ctrl_reg;
109 uint32_t icr_reg;
110
111 DEBUGFUNC("ixgb_adapter_stop");
112
113 /* If we are stopped or resetting exit gracefully and wait to be
114 * started again before accessing the hardware.
115 */
116 if(hw->adapter_stopped) {
117 DEBUGOUT("Exiting because the adapter is already stopped!!!\n");
118 return FALSE;
119 }
120
121 /* Set the Adapter Stopped flag so other driver functions stop
122 * touching the Hardware.
123 */
124 hw->adapter_stopped = TRUE;
125
126 /* Clear interrupt mask to stop board from generating interrupts */
127 DEBUGOUT("Masking off all interrupts\n");
128 IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF);
129
130 /* Disable the Transmit and Receive units. Then delay to allow
131 * any pending transactions to complete before we hit the MAC with
132 * the global reset.
133 */
134 IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN);
135 IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN);
136 msleep(IXGB_DELAY_BEFORE_RESET);
137
138 /* Issue a global reset to the MAC. This will reset the chip's
139 * transmit, receive, DMA, and link units. It will not effect
140 * the current PCI configuration. The global reset bit is self-
141 * clearing, and should clear within a microsecond.
142 */
143 DEBUGOUT("Issuing a global reset to MAC\n");
144
145 ctrl_reg = ixgb_mac_reset(hw);
146
147 /* Clear interrupt mask to stop board from generating interrupts */
148 DEBUGOUT("Masking off all interrupts\n");
149 IXGB_WRITE_REG(hw, IMC, 0xffffffff);
150
151 /* Clear any pending interrupt events. */
152 icr_reg = IXGB_READ_REG(hw, ICR);
153
154 return (ctrl_reg & IXGB_CTRL0_RST);
155 }
156
157
158 /******************************************************************************
159 * Identifies the vendor of the optics module on the adapter. The SR adapters
160 * support two different types of XPAK optics, so it is necessary to determine
161 * which optics are present before applying any optics-specific workarounds.
162 *
163 * hw - Struct containing variables accessed by shared code.
164 *
165 * Returns: the vendor of the XPAK optics module.
166 *****************************************************************************/
167 static ixgb_xpak_vendor
168 ixgb_identify_xpak_vendor(struct ixgb_hw *hw)
169 {
170 uint32_t i;
171 uint16_t vendor_name[5];
172 ixgb_xpak_vendor xpak_vendor;
173
174 DEBUGFUNC("ixgb_identify_xpak_vendor");
175
176 /* Read the first few bytes of the vendor string from the XPAK NVR
177 * registers. These are standard XENPAK/XPAK registers, so all XPAK
178 * devices should implement them. */
179 for (i = 0; i < 5; i++) {
180 vendor_name[i] = ixgb_read_phy_reg(hw,
181 MDIO_PMA_PMD_XPAK_VENDOR_NAME
182 + i, IXGB_PHY_ADDRESS,
183 MDIO_PMA_PMD_DID);
184 }
185
186 /* Determine the actual vendor */
187 if (vendor_name[0] == 'I' &&
188 vendor_name[1] == 'N' &&
189 vendor_name[2] == 'T' &&
190 vendor_name[3] == 'E' && vendor_name[4] == 'L') {
191 xpak_vendor = ixgb_xpak_vendor_intel;
192 } else {
193 xpak_vendor = ixgb_xpak_vendor_infineon;
194 }
195
196 return (xpak_vendor);
197 }
198
199 /******************************************************************************
200 * Determine the physical layer module on the adapter.
201 *
202 * hw - Struct containing variables accessed by shared code. The device_id
203 * field must be (correctly) populated before calling this routine.
204 *
205 * Returns: the phy type of the adapter.
206 *****************************************************************************/
207 static ixgb_phy_type
208 ixgb_identify_phy(struct ixgb_hw *hw)
209 {
210 ixgb_phy_type phy_type;
211 ixgb_xpak_vendor xpak_vendor;
212
213 DEBUGFUNC("ixgb_identify_phy");
214
215 /* Infer the transceiver/phy type from the device id */
216 switch (hw->device_id) {
217 case IXGB_DEVICE_ID_82597EX:
218 DEBUGOUT("Identified TXN17401 optics\n");
219 phy_type = ixgb_phy_type_txn17401;
220 break;
221
222 case IXGB_DEVICE_ID_82597EX_SR:
223 /* The SR adapters carry two different types of XPAK optics
224 * modules; read the vendor identifier to determine the exact
225 * type of optics. */
226 xpak_vendor = ixgb_identify_xpak_vendor(hw);
227 if (xpak_vendor == ixgb_xpak_vendor_intel) {
228 DEBUGOUT("Identified TXN17201 optics\n");
229 phy_type = ixgb_phy_type_txn17201;
230 } else {
231 DEBUGOUT("Identified G6005 optics\n");
232 phy_type = ixgb_phy_type_g6005;
233 }
234 break;
235 case IXGB_DEVICE_ID_82597EX_LR:
236 DEBUGOUT("Identified G6104 optics\n");
237 phy_type = ixgb_phy_type_g6104;
238 break;
239 case IXGB_DEVICE_ID_82597EX_CX4:
240 DEBUGOUT("Identified CX4\n");
241 xpak_vendor = ixgb_identify_xpak_vendor(hw);
242 if (xpak_vendor == ixgb_xpak_vendor_intel) {
243 DEBUGOUT("Identified TXN17201 optics\n");
244 phy_type = ixgb_phy_type_txn17201;
245 } else {
246 DEBUGOUT("Identified G6005 optics\n");
247 phy_type = ixgb_phy_type_g6005;
248 }
249 break;
250 default:
251 DEBUGOUT("Unknown physical layer module\n");
252 phy_type = ixgb_phy_type_unknown;
253 break;
254 }
255
256 return (phy_type);
257 }
258
259 /******************************************************************************
260 * Performs basic configuration of the adapter.
261 *
262 * hw - Struct containing variables accessed by shared code
263 *
264 * Resets the controller.
265 * Reads and validates the EEPROM.
266 * Initializes the receive address registers.
267 * Initializes the multicast table.
268 * Clears all on-chip counters.
269 * Calls routine to setup flow control settings.
270 * Leaves the transmit and receive units disabled and uninitialized.
271 *
272 * Returns:
273 * TRUE if successful,
274 * FALSE if unrecoverable problems were encountered.
275 *****************************************************************************/
276 boolean_t
277 ixgb_init_hw(struct ixgb_hw *hw)
278 {
279 uint32_t i;
280 uint32_t ctrl_reg;
281 boolean_t status;
282
283 DEBUGFUNC("ixgb_init_hw");
284
285 /* Issue a global reset to the MAC. This will reset the chip's
286 * transmit, receive, DMA, and link units. It will not effect
287 * the current PCI configuration. The global reset bit is self-
288 * clearing, and should clear within a microsecond.
289 */
290 DEBUGOUT("Issuing a global reset to MAC\n");
291
292 ctrl_reg = ixgb_mac_reset(hw);
293
294 DEBUGOUT("Issuing an EE reset to MAC\n");
295 #ifdef HP_ZX1
296 /* Workaround for 82597EX reset errata */
297 IXGB_WRITE_REG_IO(hw, CTRL1, IXGB_CTRL1_EE_RST);
298 #else
299 IXGB_WRITE_REG(hw, CTRL1, IXGB_CTRL1_EE_RST);
300 #endif
301
302 /* Delay a few ms just to allow the reset to complete */
303 msleep(IXGB_DELAY_AFTER_EE_RESET);
304
305 if (ixgb_get_eeprom_data(hw) == FALSE) {
306 return(FALSE);
307 }
308
309 /* Use the device id to determine the type of phy/transceiver. */
310 hw->device_id = ixgb_get_ee_device_id(hw);
311 hw->phy_type = ixgb_identify_phy(hw);
312
313 /* Setup the receive addresses.
314 * Receive Address Registers (RARs 0 - 15).
315 */
316 ixgb_init_rx_addrs(hw);
317
318 /*
319 * Check that a valid MAC address has been set.
320 * If it is not valid, we fail hardware init.
321 */
322 if (!mac_addr_valid(hw->curr_mac_addr)) {
323 DEBUGOUT("MAC address invalid after ixgb_init_rx_addrs\n");
324 return(FALSE);
325 }
326
327 /* tell the routines in this file they can access hardware again */
328 hw->adapter_stopped = FALSE;
329
330 /* Fill in the bus_info structure */
331 ixgb_get_bus_info(hw);
332
333 /* Zero out the Multicast HASH table */
334 DEBUGOUT("Zeroing the MTA\n");
335 for(i = 0; i < IXGB_MC_TBL_SIZE; i++)
336 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
337
338 /* Zero out the VLAN Filter Table Array */
339 ixgb_clear_vfta(hw);
340
341 /* Zero all of the hardware counters */
342 ixgb_clear_hw_cntrs(hw);
343
344 /* Call a subroutine to setup flow control. */
345 status = ixgb_setup_fc(hw);
346
347 /* 82597EX errata: Call check-for-link in case lane deskew is locked */
348 ixgb_check_for_link(hw);
349
350 return (status);
351 }
352
353 /******************************************************************************
354 * Initializes receive address filters.
355 *
356 * hw - Struct containing variables accessed by shared code
357 *
358 * Places the MAC address in receive address register 0 and clears the rest
359 * of the receive addresss registers. Clears the multicast table. Assumes
360 * the receiver is in reset when the routine is called.
361 *****************************************************************************/
362 static void
363 ixgb_init_rx_addrs(struct ixgb_hw *hw)
364 {
365 uint32_t i;
366
367 DEBUGFUNC("ixgb_init_rx_addrs");
368
369 /*
370 * If the current mac address is valid, assume it is a software override
371 * to the permanent address.
372 * Otherwise, use the permanent address from the eeprom.
373 */
374 if (!mac_addr_valid(hw->curr_mac_addr)) {
375
376 /* Get the MAC address from the eeprom for later reference */
377 ixgb_get_ee_mac_addr(hw, hw->curr_mac_addr);
378
379 DEBUGOUT3(" Keeping Permanent MAC Addr =%.2X %.2X %.2X ",
380 hw->curr_mac_addr[0],
381 hw->curr_mac_addr[1], hw->curr_mac_addr[2]);
382 DEBUGOUT3("%.2X %.2X %.2X\n",
383 hw->curr_mac_addr[3],
384 hw->curr_mac_addr[4], hw->curr_mac_addr[5]);
385 } else {
386
387 /* Setup the receive address. */
388 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
389 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
390 hw->curr_mac_addr[0],
391 hw->curr_mac_addr[1], hw->curr_mac_addr[2]);
392 DEBUGOUT3("%.2X %.2X %.2X\n",
393 hw->curr_mac_addr[3],
394 hw->curr_mac_addr[4], hw->curr_mac_addr[5]);
395
396 ixgb_rar_set(hw, hw->curr_mac_addr, 0);
397 }
398
399 /* Zero out the other 15 receive addresses. */
400 DEBUGOUT("Clearing RAR[1-15]\n");
401 for(i = 1; i < IXGB_RAR_ENTRIES; i++) {
402 /* Write high reg first to disable the AV bit first */
403 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
404 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
405 }
406
407 return;
408 }
409
410 /******************************************************************************
411 * Updates the MAC's list of multicast addresses.
412 *
413 * hw - Struct containing variables accessed by shared code
414 * mc_addr_list - the list of new multicast addresses
415 * mc_addr_count - number of addresses
416 * pad - number of bytes between addresses in the list
417 *
418 * The given list replaces any existing list. Clears the last 15 receive
419 * address registers and the multicast table. Uses receive address registers
420 * for the first 15 multicast addresses, and hashes the rest into the
421 * multicast table.
422 *****************************************************************************/
423 void
424 ixgb_mc_addr_list_update(struct ixgb_hw *hw,
425 uint8_t *mc_addr_list,
426 uint32_t mc_addr_count,
427 uint32_t pad)
428 {
429 uint32_t hash_value;
430 uint32_t i;
431 uint32_t rar_used_count = 1; /* RAR[0] is used for our MAC address */
432
433 DEBUGFUNC("ixgb_mc_addr_list_update");
434
435 /* Set the new number of MC addresses that we are being requested to use. */
436 hw->num_mc_addrs = mc_addr_count;
437
438 /* Clear RAR[1-15] */
439 DEBUGOUT(" Clearing RAR[1-15]\n");
440 for(i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) {
441 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
442 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
443 }
444
445 /* Clear the MTA */
446 DEBUGOUT(" Clearing MTA\n");
447 for(i = 0; i < IXGB_MC_TBL_SIZE; i++) {
448 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
449 }
450
451 /* Add the new addresses */
452 for(i = 0; i < mc_addr_count; i++) {
453 DEBUGOUT(" Adding the multicast addresses:\n");
454 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
455 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)],
456 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
457 1],
458 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
459 2],
460 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
461 3],
462 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
463 4],
464 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
465 5]);
466
467 /* Place this multicast address in the RAR if there is room, *
468 * else put it in the MTA
469 */
470 if(rar_used_count < IXGB_RAR_ENTRIES) {
471 ixgb_rar_set(hw,
472 mc_addr_list +
473 (i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)),
474 rar_used_count);
475 DEBUGOUT1("Added a multicast address to RAR[%d]\n", i);
476 rar_used_count++;
477 } else {
478 hash_value = ixgb_hash_mc_addr(hw,
479 mc_addr_list +
480 (i *
481 (IXGB_ETH_LENGTH_OF_ADDRESS
482 + pad)));
483
484 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
485
486 ixgb_mta_set(hw, hash_value);
487 }
488 }
489
490 DEBUGOUT("MC Update Complete\n");
491 return;
492 }
493
494 /******************************************************************************
495 * Hashes an address to determine its location in the multicast table
496 *
497 * hw - Struct containing variables accessed by shared code
498 * mc_addr - the multicast address to hash
499 *
500 * Returns:
501 * The hash value
502 *****************************************************************************/
503 static uint32_t
504 ixgb_hash_mc_addr(struct ixgb_hw *hw,
505 uint8_t *mc_addr)
506 {
507 uint32_t hash_value = 0;
508
509 DEBUGFUNC("ixgb_hash_mc_addr");
510
511 /* The portion of the address that is used for the hash table is
512 * determined by the mc_filter_type setting.
513 */
514 switch (hw->mc_filter_type) {
515 /* [0] [1] [2] [3] [4] [5]
516 * 01 AA 00 12 34 56
517 * LSB MSB - According to H/W docs */
518 case 0:
519 /* [47:36] i.e. 0x563 for above example address */
520 hash_value =
521 ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
522 break;
523 case 1: /* [46:35] i.e. 0xAC6 for above example address */
524 hash_value =
525 ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
526 break;
527 case 2: /* [45:34] i.e. 0x5D8 for above example address */
528 hash_value =
529 ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
530 break;
531 case 3: /* [43:32] i.e. 0x634 for above example address */
532 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
533 break;
534 default:
535 /* Invalid mc_filter_type, what should we do? */
536 DEBUGOUT("MC filter type param set incorrectly\n");
537 ASSERT(0);
538 break;
539 }
540
541 hash_value &= 0xFFF;
542 return (hash_value);
543 }
544
545 /******************************************************************************
546 * Sets the bit in the multicast table corresponding to the hash value.
547 *
548 * hw - Struct containing variables accessed by shared code
549 * hash_value - Multicast address hash value
550 *****************************************************************************/
551 static void
552 ixgb_mta_set(struct ixgb_hw *hw,
553 uint32_t hash_value)
554 {
555 uint32_t hash_bit, hash_reg;
556 uint32_t mta_reg;
557
558 /* The MTA is a register array of 128 32-bit registers.
559 * It is treated like an array of 4096 bits. We want to set
560 * bit BitArray[hash_value]. So we figure out what register
561 * the bit is in, read it, OR in the new bit, then write
562 * back the new value. The register is determined by the
563 * upper 7 bits of the hash value and the bit within that
564 * register are determined by the lower 5 bits of the value.
565 */
566 hash_reg = (hash_value >> 5) & 0x7F;
567 hash_bit = hash_value & 0x1F;
568
569 mta_reg = IXGB_READ_REG_ARRAY(hw, MTA, hash_reg);
570
571 mta_reg |= (1 << hash_bit);
572
573 IXGB_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta_reg);
574
575 return;
576 }
577
578 /******************************************************************************
579 * Puts an ethernet address into a receive address register.
580 *
581 * hw - Struct containing variables accessed by shared code
582 * addr - Address to put into receive address register
583 * index - Receive address register to write
584 *****************************************************************************/
585 void
586 ixgb_rar_set(struct ixgb_hw *hw,
587 uint8_t *addr,
588 uint32_t index)
589 {
590 uint32_t rar_low, rar_high;
591
592 DEBUGFUNC("ixgb_rar_set");
593
594 /* HW expects these in little endian so we reverse the byte order
595 * from network order (big endian) to little endian
596 */
597 rar_low = ((uint32_t) addr[0] |
598 ((uint32_t)addr[1] << 8) |
599 ((uint32_t)addr[2] << 16) |
600 ((uint32_t)addr[3] << 24));
601
602 rar_high = ((uint32_t) addr[4] |
603 ((uint32_t)addr[5] << 8) |
604 IXGB_RAH_AV);
605
606 IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
607 IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
608 return;
609 }
610
611 /******************************************************************************
612 * Writes a value to the specified offset in the VLAN filter table.
613 *
614 * hw - Struct containing variables accessed by shared code
615 * offset - Offset in VLAN filer table to write
616 * value - Value to write into VLAN filter table
617 *****************************************************************************/
618 void
619 ixgb_write_vfta(struct ixgb_hw *hw,
620 uint32_t offset,
621 uint32_t value)
622 {
623 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value);
624 return;
625 }
626
627 /******************************************************************************
628 * Clears the VLAN filer table
629 *
630 * hw - Struct containing variables accessed by shared code
631 *****************************************************************************/
632 static void
633 ixgb_clear_vfta(struct ixgb_hw *hw)
634 {
635 uint32_t offset;
636
637 for(offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++)
638 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
639 return;
640 }
641
642 /******************************************************************************
643 * Configures the flow control settings based on SW configuration.
644 *
645 * hw - Struct containing variables accessed by shared code
646 *****************************************************************************/
647
648 static boolean_t
649 ixgb_setup_fc(struct ixgb_hw *hw)
650 {
651 uint32_t ctrl_reg;
652 uint32_t pap_reg = 0; /* by default, assume no pause time */
653 boolean_t status = TRUE;
654
655 DEBUGFUNC("ixgb_setup_fc");
656
657 /* Get the current control reg 0 settings */
658 ctrl_reg = IXGB_READ_REG(hw, CTRL0);
659
660 /* Clear the Receive Pause Enable and Transmit Pause Enable bits */
661 ctrl_reg &= ~(IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
662
663 /* The possible values of the "flow_control" parameter are:
664 * 0: Flow control is completely disabled
665 * 1: Rx flow control is enabled (we can receive pause frames
666 * but not send pause frames).
667 * 2: Tx flow control is enabled (we can send pause frames
668 * but we do not support receiving pause frames).
669 * 3: Both Rx and TX flow control (symmetric) are enabled.
670 * other: Invalid.
671 */
672 switch (hw->fc.type) {
673 case ixgb_fc_none: /* 0 */
674 /* Set CMDC bit to disable Rx Flow control */
675 ctrl_reg |= (IXGB_CTRL0_CMDC);
676 break;
677 case ixgb_fc_rx_pause: /* 1 */
678 /* RX Flow control is enabled, and TX Flow control is
679 * disabled.
680 */
681 ctrl_reg |= (IXGB_CTRL0_RPE);
682 break;
683 case ixgb_fc_tx_pause: /* 2 */
684 /* TX Flow control is enabled, and RX Flow control is
685 * disabled, by a software over-ride.
686 */
687 ctrl_reg |= (IXGB_CTRL0_TPE);
688 pap_reg = hw->fc.pause_time;
689 break;
690 case ixgb_fc_full: /* 3 */
691 /* Flow control (both RX and TX) is enabled by a software
692 * over-ride.
693 */
694 ctrl_reg |= (IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
695 pap_reg = hw->fc.pause_time;
696 break;
697 default:
698 /* We should never get here. The value should be 0-3. */
699 DEBUGOUT("Flow control param set incorrectly\n");
700 ASSERT(0);
701 break;
702 }
703
704 /* Write the new settings */
705 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
706
707 if (pap_reg != 0) {
708 IXGB_WRITE_REG(hw, PAP, pap_reg);
709 }
710
711 /* Set the flow control receive threshold registers. Normally,
712 * these registers will be set to a default threshold that may be
713 * adjusted later by the driver's runtime code. However, if the
714 * ability to transmit pause frames in not enabled, then these
715 * registers will be set to 0.
716 */
717 if(!(hw->fc.type & ixgb_fc_tx_pause)) {
718 IXGB_WRITE_REG(hw, FCRTL, 0);
719 IXGB_WRITE_REG(hw, FCRTH, 0);
720 } else {
721 /* We need to set up the Receive Threshold high and low water
722 * marks as well as (optionally) enabling the transmission of XON
723 * frames. */
724 if(hw->fc.send_xon) {
725 IXGB_WRITE_REG(hw, FCRTL,
726 (hw->fc.low_water | IXGB_FCRTL_XONE));
727 } else {
728 IXGB_WRITE_REG(hw, FCRTL, hw->fc.low_water);
729 }
730 IXGB_WRITE_REG(hw, FCRTH, hw->fc.high_water);
731 }
732 return (status);
733 }
734
735 /******************************************************************************
736 * Reads a word from a device over the Management Data Interface (MDI) bus.
737 * This interface is used to manage Physical layer devices.
738 *
739 * hw - Struct containing variables accessed by hw code
740 * reg_address - Offset of device register being read.
741 * phy_address - Address of device on MDI.
742 *
743 * Returns: Data word (16 bits) from MDI device.
744 *
745 * The 82597EX has support for several MDI access methods. This routine
746 * uses the new protocol MDI Single Command and Address Operation.
747 * This requires that first an address cycle command is sent, followed by a
748 * read command.
749 *****************************************************************************/
750 static uint16_t
751 ixgb_read_phy_reg(struct ixgb_hw *hw,
752 uint32_t reg_address,
753 uint32_t phy_address,
754 uint32_t device_type)
755 {
756 uint32_t i;
757 uint32_t data;
758 uint32_t command = 0;
759
760 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
761 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
762 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
763
764 /* Setup and write the address cycle command */
765 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
766 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
767 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
768 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
769
770 IXGB_WRITE_REG(hw, MSCA, command);
771
772 /**************************************************************
773 ** Check every 10 usec to see if the address cycle completed
774 ** The COMMAND bit will clear when the operation is complete.
775 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
776 ** from the CPU Write to the Ready bit assertion.
777 **************************************************************/
778
779 for(i = 0; i < 10; i++)
780 {
781 udelay(10);
782
783 command = IXGB_READ_REG(hw, MSCA);
784
785 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
786 break;
787 }
788
789 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
790
791 /* Address cycle complete, setup and write the read command */
792 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
793 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
794 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
795 (IXGB_MSCA_READ | IXGB_MSCA_MDI_COMMAND));
796
797 IXGB_WRITE_REG(hw, MSCA, command);
798
799 /**************************************************************
800 ** Check every 10 usec to see if the read command completed
801 ** The COMMAND bit will clear when the operation is complete.
802 ** The read may take as long as 64 usecs (we'll wait 100 usecs max)
803 ** from the CPU Write to the Ready bit assertion.
804 **************************************************************/
805
806 for(i = 0; i < 10; i++)
807 {
808 udelay(10);
809
810 command = IXGB_READ_REG(hw, MSCA);
811
812 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
813 break;
814 }
815
816 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
817
818 /* Operation is complete, get the data from the MDIO Read/Write Data
819 * register and return.
820 */
821 data = IXGB_READ_REG(hw, MSRWD);
822 data >>= IXGB_MSRWD_READ_DATA_SHIFT;
823 return((uint16_t) data);
824 }
825
826 /******************************************************************************
827 * Writes a word to a device over the Management Data Interface (MDI) bus.
828 * This interface is used to manage Physical layer devices.
829 *
830 * hw - Struct containing variables accessed by hw code
831 * reg_address - Offset of device register being read.
832 * phy_address - Address of device on MDI.
833 * device_type - Also known as the Device ID or DID.
834 * data - 16-bit value to be written
835 *
836 * Returns: void.
837 *
838 * The 82597EX has support for several MDI access methods. This routine
839 * uses the new protocol MDI Single Command and Address Operation.
840 * This requires that first an address cycle command is sent, followed by a
841 * write command.
842 *****************************************************************************/
843 static void
844 ixgb_write_phy_reg(struct ixgb_hw *hw,
845 uint32_t reg_address,
846 uint32_t phy_address,
847 uint32_t device_type,
848 uint16_t data)
849 {
850 uint32_t i;
851 uint32_t command = 0;
852
853 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
854 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
855 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
856
857 /* Put the data in the MDIO Read/Write Data register */
858 IXGB_WRITE_REG(hw, MSRWD, (uint32_t)data);
859
860 /* Setup and write the address cycle command */
861 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
862 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
863 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
864 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
865
866 IXGB_WRITE_REG(hw, MSCA, command);
867
868 /**************************************************************
869 ** Check every 10 usec to see if the address cycle completed
870 ** The COMMAND bit will clear when the operation is complete.
871 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
872 ** from the CPU Write to the Ready bit assertion.
873 **************************************************************/
874
875 for(i = 0; i < 10; i++)
876 {
877 udelay(10);
878
879 command = IXGB_READ_REG(hw, MSCA);
880
881 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
882 break;
883 }
884
885 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
886
887 /* Address cycle complete, setup and write the write command */
888 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
889 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
890 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
891 (IXGB_MSCA_WRITE | IXGB_MSCA_MDI_COMMAND));
892
893 IXGB_WRITE_REG(hw, MSCA, command);
894
895 /**************************************************************
896 ** Check every 10 usec to see if the read command completed
897 ** The COMMAND bit will clear when the operation is complete.
898 ** The write may take as long as 64 usecs (we'll wait 100 usecs max)
899 ** from the CPU Write to the Ready bit assertion.
900 **************************************************************/
901
902 for(i = 0; i < 10; i++)
903 {
904 udelay(10);
905
906 command = IXGB_READ_REG(hw, MSCA);
907
908 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
909 break;
910 }
911
912 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
913
914 /* Operation is complete, return. */
915 }
916
917 /******************************************************************************
918 * Checks to see if the link status of the hardware has changed.
919 *
920 * hw - Struct containing variables accessed by hw code
921 *
922 * Called by any function that needs to check the link status of the adapter.
923 *****************************************************************************/
924 void
925 ixgb_check_for_link(struct ixgb_hw *hw)
926 {
927 uint32_t status_reg;
928 uint32_t xpcss_reg;
929
930 DEBUGFUNC("ixgb_check_for_link");
931
932 xpcss_reg = IXGB_READ_REG(hw, XPCSS);
933 status_reg = IXGB_READ_REG(hw, STATUS);
934
935 if ((xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
936 (status_reg & IXGB_STATUS_LU)) {
937 hw->link_up = TRUE;
938 } else if (!(xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
939 (status_reg & IXGB_STATUS_LU)) {
940 DEBUGOUT("XPCSS Not Aligned while Status:LU is set.\n");
941 hw->link_up = ixgb_link_reset(hw);
942 } else {
943 /*
944 * 82597EX errata. Since the lane deskew problem may prevent
945 * link, reset the link before reporting link down.
946 */
947 hw->link_up = ixgb_link_reset(hw);
948 }
949 /* Anything else for 10 Gig?? */
950 }
951
952 /******************************************************************************
953 * Check for a bad link condition that may have occured.
954 * The indication is that the RFC / LFC registers may be incrementing
955 * continually. A full adapter reset is required to recover.
956 *
957 * hw - Struct containing variables accessed by hw code
958 *
959 * Called by any function that needs to check the link status of the adapter.
960 *****************************************************************************/
961 boolean_t ixgb_check_for_bad_link(struct ixgb_hw *hw)
962 {
963 uint32_t newLFC, newRFC;
964 boolean_t bad_link_returncode = FALSE;
965
966 if (hw->phy_type == ixgb_phy_type_txn17401) {
967 newLFC = IXGB_READ_REG(hw, LFC);
968 newRFC = IXGB_READ_REG(hw, RFC);
969 if ((hw->lastLFC + 250 < newLFC)
970 || (hw->lastRFC + 250 < newRFC)) {
971 DEBUGOUT
972 ("BAD LINK! too many LFC/RFC since last check\n");
973 bad_link_returncode = TRUE;
974 }
975 hw->lastLFC = newLFC;
976 hw->lastRFC = newRFC;
977 }
978
979 return bad_link_returncode;
980 }
981
982 /******************************************************************************
983 * Clears all hardware statistics counters.
984 *
985 * hw - Struct containing variables accessed by shared code
986 *****************************************************************************/
987 static void
988 ixgb_clear_hw_cntrs(struct ixgb_hw *hw)
989 {
990 volatile uint32_t temp_reg;
991
992 DEBUGFUNC("ixgb_clear_hw_cntrs");
993
994 /* if we are stopped or resetting exit gracefully */
995 if(hw->adapter_stopped) {
996 DEBUGOUT("Exiting because the adapter is stopped!!!\n");
997 return;
998 }
999
1000 temp_reg = IXGB_READ_REG(hw, TPRL);
1001 temp_reg = IXGB_READ_REG(hw, TPRH);
1002 temp_reg = IXGB_READ_REG(hw, GPRCL);
1003 temp_reg = IXGB_READ_REG(hw, GPRCH);
1004 temp_reg = IXGB_READ_REG(hw, BPRCL);
1005 temp_reg = IXGB_READ_REG(hw, BPRCH);
1006 temp_reg = IXGB_READ_REG(hw, MPRCL);
1007 temp_reg = IXGB_READ_REG(hw, MPRCH);
1008 temp_reg = IXGB_READ_REG(hw, UPRCL);
1009 temp_reg = IXGB_READ_REG(hw, UPRCH);
1010 temp_reg = IXGB_READ_REG(hw, VPRCL);
1011 temp_reg = IXGB_READ_REG(hw, VPRCH);
1012 temp_reg = IXGB_READ_REG(hw, JPRCL);
1013 temp_reg = IXGB_READ_REG(hw, JPRCH);
1014 temp_reg = IXGB_READ_REG(hw, GORCL);
1015 temp_reg = IXGB_READ_REG(hw, GORCH);
1016 temp_reg = IXGB_READ_REG(hw, TORL);
1017 temp_reg = IXGB_READ_REG(hw, TORH);
1018 temp_reg = IXGB_READ_REG(hw, RNBC);
1019 temp_reg = IXGB_READ_REG(hw, RUC);
1020 temp_reg = IXGB_READ_REG(hw, ROC);
1021 temp_reg = IXGB_READ_REG(hw, RLEC);
1022 temp_reg = IXGB_READ_REG(hw, CRCERRS);
1023 temp_reg = IXGB_READ_REG(hw, ICBC);
1024 temp_reg = IXGB_READ_REG(hw, ECBC);
1025 temp_reg = IXGB_READ_REG(hw, MPC);
1026 temp_reg = IXGB_READ_REG(hw, TPTL);
1027 temp_reg = IXGB_READ_REG(hw, TPTH);
1028 temp_reg = IXGB_READ_REG(hw, GPTCL);
1029 temp_reg = IXGB_READ_REG(hw, GPTCH);
1030 temp_reg = IXGB_READ_REG(hw, BPTCL);
1031 temp_reg = IXGB_READ_REG(hw, BPTCH);
1032 temp_reg = IXGB_READ_REG(hw, MPTCL);
1033 temp_reg = IXGB_READ_REG(hw, MPTCH);
1034 temp_reg = IXGB_READ_REG(hw, UPTCL);
1035 temp_reg = IXGB_READ_REG(hw, UPTCH);
1036 temp_reg = IXGB_READ_REG(hw, VPTCL);
1037 temp_reg = IXGB_READ_REG(hw, VPTCH);
1038 temp_reg = IXGB_READ_REG(hw, JPTCL);
1039 temp_reg = IXGB_READ_REG(hw, JPTCH);
1040 temp_reg = IXGB_READ_REG(hw, GOTCL);
1041 temp_reg = IXGB_READ_REG(hw, GOTCH);
1042 temp_reg = IXGB_READ_REG(hw, TOTL);
1043 temp_reg = IXGB_READ_REG(hw, TOTH);
1044 temp_reg = IXGB_READ_REG(hw, DC);
1045 temp_reg = IXGB_READ_REG(hw, PLT64C);
1046 temp_reg = IXGB_READ_REG(hw, TSCTC);
1047 temp_reg = IXGB_READ_REG(hw, TSCTFC);
1048 temp_reg = IXGB_READ_REG(hw, IBIC);
1049 temp_reg = IXGB_READ_REG(hw, RFC);
1050 temp_reg = IXGB_READ_REG(hw, LFC);
1051 temp_reg = IXGB_READ_REG(hw, PFRC);
1052 temp_reg = IXGB_READ_REG(hw, PFTC);
1053 temp_reg = IXGB_READ_REG(hw, MCFRC);
1054 temp_reg = IXGB_READ_REG(hw, MCFTC);
1055 temp_reg = IXGB_READ_REG(hw, XONRXC);
1056 temp_reg = IXGB_READ_REG(hw, XONTXC);
1057 temp_reg = IXGB_READ_REG(hw, XOFFRXC);
1058 temp_reg = IXGB_READ_REG(hw, XOFFTXC);
1059 temp_reg = IXGB_READ_REG(hw, RJC);
1060 return;
1061 }
1062
1063 /******************************************************************************
1064 * Turns on the software controllable LED
1065 *
1066 * hw - Struct containing variables accessed by shared code
1067 *****************************************************************************/
1068 void
1069 ixgb_led_on(struct ixgb_hw *hw)
1070 {
1071 uint32_t ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
1072
1073 /* To turn on the LED, clear software-definable pin 0 (SDP0). */
1074 ctrl0_reg &= ~IXGB_CTRL0_SDP0;
1075 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
1076 return;
1077 }
1078
1079 /******************************************************************************
1080 * Turns off the software controllable LED
1081 *
1082 * hw - Struct containing variables accessed by shared code
1083 *****************************************************************************/
1084 void
1085 ixgb_led_off(struct ixgb_hw *hw)
1086 {
1087 uint32_t ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
1088
1089 /* To turn off the LED, set software-definable pin 0 (SDP0). */
1090 ctrl0_reg |= IXGB_CTRL0_SDP0;
1091 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
1092 return;
1093 }
1094
1095 /******************************************************************************
1096 * Gets the current PCI bus type, speed, and width of the hardware
1097 *
1098 * hw - Struct containing variables accessed by shared code
1099 *****************************************************************************/
1100 static void
1101 ixgb_get_bus_info(struct ixgb_hw *hw)
1102 {
1103 uint32_t status_reg;
1104
1105 status_reg = IXGB_READ_REG(hw, STATUS);
1106
1107 hw->bus.type = (status_reg & IXGB_STATUS_PCIX_MODE) ?
1108 ixgb_bus_type_pcix : ixgb_bus_type_pci;
1109
1110 if (hw->bus.type == ixgb_bus_type_pci) {
1111 hw->bus.speed = (status_reg & IXGB_STATUS_PCI_SPD) ?
1112 ixgb_bus_speed_66 : ixgb_bus_speed_33;
1113 } else {
1114 switch (status_reg & IXGB_STATUS_PCIX_SPD_MASK) {
1115 case IXGB_STATUS_PCIX_SPD_66:
1116 hw->bus.speed = ixgb_bus_speed_66;
1117 break;
1118 case IXGB_STATUS_PCIX_SPD_100:
1119 hw->bus.speed = ixgb_bus_speed_100;
1120 break;
1121 case IXGB_STATUS_PCIX_SPD_133:
1122 hw->bus.speed = ixgb_bus_speed_133;
1123 break;
1124 default:
1125 hw->bus.speed = ixgb_bus_speed_reserved;
1126 break;
1127 }
1128 }
1129
1130 hw->bus.width = (status_reg & IXGB_STATUS_BUS64) ?
1131 ixgb_bus_width_64 : ixgb_bus_width_32;
1132
1133 return;
1134 }
1135
1136 /******************************************************************************
1137 * Tests a MAC address to ensure it is a valid Individual Address
1138 *
1139 * mac_addr - pointer to MAC address.
1140 *
1141 *****************************************************************************/
1142 static boolean_t
1143 mac_addr_valid(uint8_t *mac_addr)
1144 {
1145 boolean_t is_valid = TRUE;
1146 DEBUGFUNC("mac_addr_valid");
1147
1148 /* Make sure it is not a multicast address */
1149 if (IS_MULTICAST(mac_addr)) {
1150 DEBUGOUT("MAC address is multicast\n");
1151 is_valid = FALSE;
1152 }
1153 /* Not a broadcast address */
1154 else if (IS_BROADCAST(mac_addr)) {
1155 DEBUGOUT("MAC address is broadcast\n");
1156 is_valid = FALSE;
1157 }
1158 /* Reject the zero address */
1159 else if (mac_addr[0] == 0 &&
1160 mac_addr[1] == 0 &&
1161 mac_addr[2] == 0 &&
1162 mac_addr[3] == 0 &&
1163 mac_addr[4] == 0 &&
1164 mac_addr[5] == 0) {
1165 DEBUGOUT("MAC address is all zeros\n");
1166 is_valid = FALSE;
1167 }
1168 return (is_valid);
1169 }
1170
1171 /******************************************************************************
1172 * Resets the 10GbE link. Waits the settle time and returns the state of
1173 * the link.
1174 *
1175 * hw - Struct containing variables accessed by shared code
1176 *****************************************************************************/
1177 boolean_t
1178 ixgb_link_reset(struct ixgb_hw *hw)
1179 {
1180 boolean_t link_status = FALSE;
1181 uint8_t wait_retries = MAX_RESET_ITERATIONS;
1182 uint8_t lrst_retries = MAX_RESET_ITERATIONS;
1183
1184 do {
1185 /* Reset the link */
1186 IXGB_WRITE_REG(hw, CTRL0,
1187 IXGB_READ_REG(hw, CTRL0) | IXGB_CTRL0_LRST);
1188
1189 /* Wait for link-up and lane re-alignment */
1190 do {
1191 udelay(IXGB_DELAY_USECS_AFTER_LINK_RESET);
1192 link_status =
1193 ((IXGB_READ_REG(hw, STATUS) & IXGB_STATUS_LU)
1194 && (IXGB_READ_REG(hw, XPCSS) &
1195 IXGB_XPCSS_ALIGN_STATUS)) ? TRUE : FALSE;
1196 } while (!link_status && --wait_retries);
1197
1198 } while (!link_status && --lrst_retries);
1199
1200 return link_status;
1201 }
1202
1203 /******************************************************************************
1204 * Resets the 10GbE optics module.
1205 *
1206 * hw - Struct containing variables accessed by shared code
1207 *****************************************************************************/
1208 void
1209 ixgb_optics_reset(struct ixgb_hw *hw)
1210 {
1211 if (hw->phy_type == ixgb_phy_type_txn17401) {
1212 uint16_t mdio_reg;
1213
1214 ixgb_write_phy_reg(hw,
1215 MDIO_PMA_PMD_CR1,
1216 IXGB_PHY_ADDRESS,
1217 MDIO_PMA_PMD_DID,
1218 MDIO_PMA_PMD_CR1_RESET);
1219
1220 mdio_reg = ixgb_read_phy_reg( hw,
1221 MDIO_PMA_PMD_CR1,
1222 IXGB_PHY_ADDRESS,
1223 MDIO_PMA_PMD_DID);
1224 }
1225
1226 return;
1227 }
Linux kernel - Deliverables
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