projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'irq-fix' of git://www.modarm9.com/gitsrc/pub/people/ukleinek/linux...
[deliverable/linux.git] / drivers / net / ixgb / ixgb_hw.c
1 /*******************************************************************************
2
3 Intel PRO/10GbE Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /* ixgb_hw.c
30 * Shared functions for accessing and configuring the adapter
31 */
32
33 #include "ixgb_hw.h"
34 #include "ixgb_ids.h"
35
36 /* Local function prototypes */
37
38 static u32 ixgb_hash_mc_addr(struct ixgb_hw *hw, u8 * mc_addr);
39
40 static void ixgb_mta_set(struct ixgb_hw *hw, u32 hash_value);
41
42 static void ixgb_get_bus_info(struct ixgb_hw *hw);
43
44 static bool ixgb_link_reset(struct ixgb_hw *hw);
45
46 static void ixgb_optics_reset(struct ixgb_hw *hw);
47
48 static void ixgb_optics_reset_bcm(struct ixgb_hw *hw);
49
50 static ixgb_phy_type ixgb_identify_phy(struct ixgb_hw *hw);
51
52 static void ixgb_clear_hw_cntrs(struct ixgb_hw *hw);
53
54 static void ixgb_clear_vfta(struct ixgb_hw *hw);
55
56 static void ixgb_init_rx_addrs(struct ixgb_hw *hw);
57
58 static u16 ixgb_read_phy_reg(struct ixgb_hw *hw,
59 u32 reg_address,
60 u32 phy_address,
61 u32 device_type);
62
63 static bool ixgb_setup_fc(struct ixgb_hw *hw);
64
65 static bool mac_addr_valid(u8 *mac_addr);
66
67 static u32 ixgb_mac_reset(struct ixgb_hw *hw)
68 {
69 u32 ctrl_reg;
70
71 ctrl_reg = IXGB_CTRL0_RST |
72 IXGB_CTRL0_SDP3_DIR | /* All pins are Output=1 */
73 IXGB_CTRL0_SDP2_DIR |
74 IXGB_CTRL0_SDP1_DIR |
75 IXGB_CTRL0_SDP0_DIR |
76 IXGB_CTRL0_SDP3 | /* Initial value 1101 */
77 IXGB_CTRL0_SDP2 |
78 IXGB_CTRL0_SDP0;
79
80 #ifdef HP_ZX1
81 /* Workaround for 82597EX reset errata */
82 IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg);
83 #else
84 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
85 #endif
86
87 /* Delay a few ms just to allow the reset to complete */
88 msleep(IXGB_DELAY_AFTER_RESET);
89 ctrl_reg = IXGB_READ_REG(hw, CTRL0);
90 #ifdef DBG
91 /* Make sure the self-clearing global reset bit did self clear */
92 ASSERT(!(ctrl_reg & IXGB_CTRL0_RST));
93 #endif
94
95 if (hw->subsystem_vendor_id == SUN_SUBVENDOR_ID) {
96 ctrl_reg = /* Enable interrupt from XFP and SerDes */
97 IXGB_CTRL1_GPI0_EN |
98 IXGB_CTRL1_SDP6_DIR |
99 IXGB_CTRL1_SDP7_DIR |
100 IXGB_CTRL1_SDP6 |
101 IXGB_CTRL1_SDP7;
102 IXGB_WRITE_REG(hw, CTRL1, ctrl_reg);
103 ixgb_optics_reset_bcm(hw);
104 }
105
106 if (hw->phy_type == ixgb_phy_type_txn17401)
107 ixgb_optics_reset(hw);
108
109 return ctrl_reg;
110 }
111
112 /******************************************************************************
113 * Reset the transmit and receive units; mask and clear all interrupts.
114 *
115 * hw - Struct containing variables accessed by shared code
116 *****************************************************************************/
117 bool
118 ixgb_adapter_stop(struct ixgb_hw *hw)
119 {
120 u32 ctrl_reg;
121 u32 icr_reg;
122
123 DEBUGFUNC("ixgb_adapter_stop");
124
125 /* If we are stopped or resetting exit gracefully and wait to be
126 * started again before accessing the hardware.
127 */
128 if(hw->adapter_stopped) {
129 DEBUGOUT("Exiting because the adapter is already stopped!!!\n");
130 return false;
131 }
132
133 /* Set the Adapter Stopped flag so other driver functions stop
134 * touching the Hardware.
135 */
136 hw->adapter_stopped = true;
137
138 /* Clear interrupt mask to stop board from generating interrupts */
139 DEBUGOUT("Masking off all interrupts\n");
140 IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF);
141
142 /* Disable the Transmit and Receive units. Then delay to allow
143 * any pending transactions to complete before we hit the MAC with
144 * the global reset.
145 */
146 IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN);
147 IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN);
148 msleep(IXGB_DELAY_BEFORE_RESET);
149
150 /* Issue a global reset to the MAC. This will reset the chip's
151 * transmit, receive, DMA, and link units. It will not effect
152 * the current PCI configuration. The global reset bit is self-
153 * clearing, and should clear within a microsecond.
154 */
155 DEBUGOUT("Issuing a global reset to MAC\n");
156
157 ctrl_reg = ixgb_mac_reset(hw);
158
159 /* Clear interrupt mask to stop board from generating interrupts */
160 DEBUGOUT("Masking off all interrupts\n");
161 IXGB_WRITE_REG(hw, IMC, 0xffffffff);
162
163 /* Clear any pending interrupt events. */
164 icr_reg = IXGB_READ_REG(hw, ICR);
165
166 return (ctrl_reg & IXGB_CTRL0_RST);
167 }
168
169
170 /******************************************************************************
171 * Identifies the vendor of the optics module on the adapter. The SR adapters
172 * support two different types of XPAK optics, so it is necessary to determine
173 * which optics are present before applying any optics-specific workarounds.
174 *
175 * hw - Struct containing variables accessed by shared code.
176 *
177 * Returns: the vendor of the XPAK optics module.
178 *****************************************************************************/
179 static ixgb_xpak_vendor
180 ixgb_identify_xpak_vendor(struct ixgb_hw *hw)
181 {
182 u32 i;
183 u16 vendor_name[5];
184 ixgb_xpak_vendor xpak_vendor;
185
186 DEBUGFUNC("ixgb_identify_xpak_vendor");
187
188 /* Read the first few bytes of the vendor string from the XPAK NVR
189 * registers. These are standard XENPAK/XPAK registers, so all XPAK
190 * devices should implement them. */
191 for (i = 0; i < 5; i++) {
192 vendor_name[i] = ixgb_read_phy_reg(hw,
193 MDIO_PMA_PMD_XPAK_VENDOR_NAME
194 + i, IXGB_PHY_ADDRESS,
195 MDIO_PMA_PMD_DID);
196 }
197
198 /* Determine the actual vendor */
199 if (vendor_name[0] == 'I' &&
200 vendor_name[1] == 'N' &&
201 vendor_name[2] == 'T' &&
202 vendor_name[3] == 'E' && vendor_name[4] == 'L') {
203 xpak_vendor = ixgb_xpak_vendor_intel;
204 } else {
205 xpak_vendor = ixgb_xpak_vendor_infineon;
206 }
207
208 return (xpak_vendor);
209 }
210
211 /******************************************************************************
212 * Determine the physical layer module on the adapter.
213 *
214 * hw - Struct containing variables accessed by shared code. The device_id
215 * field must be (correctly) populated before calling this routine.
216 *
217 * Returns: the phy type of the adapter.
218 *****************************************************************************/
219 static ixgb_phy_type
220 ixgb_identify_phy(struct ixgb_hw *hw)
221 {
222 ixgb_phy_type phy_type;
223 ixgb_xpak_vendor xpak_vendor;
224
225 DEBUGFUNC("ixgb_identify_phy");
226
227 /* Infer the transceiver/phy type from the device id */
228 switch (hw->device_id) {
229 case IXGB_DEVICE_ID_82597EX:
230 DEBUGOUT("Identified TXN17401 optics\n");
231 phy_type = ixgb_phy_type_txn17401;
232 break;
233
234 case IXGB_DEVICE_ID_82597EX_SR:
235 /* The SR adapters carry two different types of XPAK optics
236 * modules; read the vendor identifier to determine the exact
237 * type of optics. */
238 xpak_vendor = ixgb_identify_xpak_vendor(hw);
239 if (xpak_vendor == ixgb_xpak_vendor_intel) {
240 DEBUGOUT("Identified TXN17201 optics\n");
241 phy_type = ixgb_phy_type_txn17201;
242 } else {
243 DEBUGOUT("Identified G6005 optics\n");
244 phy_type = ixgb_phy_type_g6005;
245 }
246 break;
247 case IXGB_DEVICE_ID_82597EX_LR:
248 DEBUGOUT("Identified G6104 optics\n");
249 phy_type = ixgb_phy_type_g6104;
250 break;
251 case IXGB_DEVICE_ID_82597EX_CX4:
252 DEBUGOUT("Identified CX4\n");
253 xpak_vendor = ixgb_identify_xpak_vendor(hw);
254 if (xpak_vendor == ixgb_xpak_vendor_intel) {
255 DEBUGOUT("Identified TXN17201 optics\n");
256 phy_type = ixgb_phy_type_txn17201;
257 } else {
258 DEBUGOUT("Identified G6005 optics\n");
259 phy_type = ixgb_phy_type_g6005;
260 }
261 break;
262 default:
263 DEBUGOUT("Unknown physical layer module\n");
264 phy_type = ixgb_phy_type_unknown;
265 break;
266 }
267
268 /* update phy type for sun specific board */
269 if (hw->subsystem_vendor_id == SUN_SUBVENDOR_ID)
270 phy_type = ixgb_phy_type_bcm;
271
272 return (phy_type);
273 }
274
275 /******************************************************************************
276 * Performs basic configuration of the adapter.
277 *
278 * hw - Struct containing variables accessed by shared code
279 *
280 * Resets the controller.
281 * Reads and validates the EEPROM.
282 * Initializes the receive address registers.
283 * Initializes the multicast table.
284 * Clears all on-chip counters.
285 * Calls routine to setup flow control settings.
286 * Leaves the transmit and receive units disabled and uninitialized.
287 *
288 * Returns:
289 * true if successful,
290 * false if unrecoverable problems were encountered.
291 *****************************************************************************/
292 bool
293 ixgb_init_hw(struct ixgb_hw *hw)
294 {
295 u32 i;
296 u32 ctrl_reg;
297 bool status;
298
299 DEBUGFUNC("ixgb_init_hw");
300
301 /* Issue a global reset to the MAC. This will reset the chip's
302 * transmit, receive, DMA, and link units. It will not effect
303 * the current PCI configuration. The global reset bit is self-
304 * clearing, and should clear within a microsecond.
305 */
306 DEBUGOUT("Issuing a global reset to MAC\n");
307
308 ctrl_reg = ixgb_mac_reset(hw);
309
310 DEBUGOUT("Issuing an EE reset to MAC\n");
311 #ifdef HP_ZX1
312 /* Workaround for 82597EX reset errata */
313 IXGB_WRITE_REG_IO(hw, CTRL1, IXGB_CTRL1_EE_RST);
314 #else
315 IXGB_WRITE_REG(hw, CTRL1, IXGB_CTRL1_EE_RST);
316 #endif
317
318 /* Delay a few ms just to allow the reset to complete */
319 msleep(IXGB_DELAY_AFTER_EE_RESET);
320
321 if (!ixgb_get_eeprom_data(hw))
322 return false;
323
324 /* Use the device id to determine the type of phy/transceiver. */
325 hw->device_id = ixgb_get_ee_device_id(hw);
326 hw->phy_type = ixgb_identify_phy(hw);
327
328 /* Setup the receive addresses.
329 * Receive Address Registers (RARs 0 - 15).
330 */
331 ixgb_init_rx_addrs(hw);
332
333 /*
334 * Check that a valid MAC address has been set.
335 * If it is not valid, we fail hardware init.
336 */
337 if (!mac_addr_valid(hw->curr_mac_addr)) {
338 DEBUGOUT("MAC address invalid after ixgb_init_rx_addrs\n");
339 return(false);
340 }
341
342 /* tell the routines in this file they can access hardware again */
343 hw->adapter_stopped = false;
344
345 /* Fill in the bus_info structure */
346 ixgb_get_bus_info(hw);
347
348 /* Zero out the Multicast HASH table */
349 DEBUGOUT("Zeroing the MTA\n");
350 for(i = 0; i < IXGB_MC_TBL_SIZE; i++)
351 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
352
353 /* Zero out the VLAN Filter Table Array */
354 ixgb_clear_vfta(hw);
355
356 /* Zero all of the hardware counters */
357 ixgb_clear_hw_cntrs(hw);
358
359 /* Call a subroutine to setup flow control. */
360 status = ixgb_setup_fc(hw);
361
362 /* 82597EX errata: Call check-for-link in case lane deskew is locked */
363 ixgb_check_for_link(hw);
364
365 return (status);
366 }
367
368 /******************************************************************************
369 * Initializes receive address filters.
370 *
371 * hw - Struct containing variables accessed by shared code
372 *
373 * Places the MAC address in receive address register 0 and clears the rest
374 * of the receive addresss registers. Clears the multicast table. Assumes
375 * the receiver is in reset when the routine is called.
376 *****************************************************************************/
377 static void
378 ixgb_init_rx_addrs(struct ixgb_hw *hw)
379 {
380 u32 i;
381
382 DEBUGFUNC("ixgb_init_rx_addrs");
383
384 /*
385 * If the current mac address is valid, assume it is a software override
386 * to the permanent address.
387 * Otherwise, use the permanent address from the eeprom.
388 */
389 if (!mac_addr_valid(hw->curr_mac_addr)) {
390
391 /* Get the MAC address from the eeprom for later reference */
392 ixgb_get_ee_mac_addr(hw, hw->curr_mac_addr);
393
394 DEBUGOUT3(" Keeping Permanent MAC Addr =%.2X %.2X %.2X ",
395 hw->curr_mac_addr[0],
396 hw->curr_mac_addr[1], hw->curr_mac_addr[2]);
397 DEBUGOUT3("%.2X %.2X %.2X\n",
398 hw->curr_mac_addr[3],
399 hw->curr_mac_addr[4], hw->curr_mac_addr[5]);
400 } else {
401
402 /* Setup the receive address. */
403 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
404 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
405 hw->curr_mac_addr[0],
406 hw->curr_mac_addr[1], hw->curr_mac_addr[2]);
407 DEBUGOUT3("%.2X %.2X %.2X\n",
408 hw->curr_mac_addr[3],
409 hw->curr_mac_addr[4], hw->curr_mac_addr[5]);
410
411 ixgb_rar_set(hw, hw->curr_mac_addr, 0);
412 }
413
414 /* Zero out the other 15 receive addresses. */
415 DEBUGOUT("Clearing RAR[1-15]\n");
416 for(i = 1; i < IXGB_RAR_ENTRIES; i++) {
417 /* Write high reg first to disable the AV bit first */
418 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
419 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
420 }
421
422 return;
423 }
424
425 /******************************************************************************
426 * Updates the MAC's list of multicast addresses.
427 *
428 * hw - Struct containing variables accessed by shared code
429 * mc_addr_list - the list of new multicast addresses
430 * mc_addr_count - number of addresses
431 * pad - number of bytes between addresses in the list
432 *
433 * The given list replaces any existing list. Clears the last 15 receive
434 * address registers and the multicast table. Uses receive address registers
435 * for the first 15 multicast addresses, and hashes the rest into the
436 * multicast table.
437 *****************************************************************************/
438 void
439 ixgb_mc_addr_list_update(struct ixgb_hw *hw,
440 u8 *mc_addr_list,
441 u32 mc_addr_count,
442 u32 pad)
443 {
444 u32 hash_value;
445 u32 i;
446 u32 rar_used_count = 1; /* RAR[0] is used for our MAC address */
447
448 DEBUGFUNC("ixgb_mc_addr_list_update");
449
450 /* Set the new number of MC addresses that we are being requested to use. */
451 hw->num_mc_addrs = mc_addr_count;
452
453 /* Clear RAR[1-15] */
454 DEBUGOUT(" Clearing RAR[1-15]\n");
455 for(i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) {
456 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
457 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
458 }
459
460 /* Clear the MTA */
461 DEBUGOUT(" Clearing MTA\n");
462 for(i = 0; i < IXGB_MC_TBL_SIZE; i++) {
463 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
464 }
465
466 /* Add the new addresses */
467 for(i = 0; i < mc_addr_count; i++) {
468 DEBUGOUT(" Adding the multicast addresses:\n");
469 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
470 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)],
471 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
472 1],
473 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
474 2],
475 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
476 3],
477 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
478 4],
479 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
480 5]);
481
482 /* Place this multicast address in the RAR if there is room, *
483 * else put it in the MTA
484 */
485 if(rar_used_count < IXGB_RAR_ENTRIES) {
486 ixgb_rar_set(hw,
487 mc_addr_list +
488 (i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)),
489 rar_used_count);
490 DEBUGOUT1("Added a multicast address to RAR[%d]\n", i);
491 rar_used_count++;
492 } else {
493 hash_value = ixgb_hash_mc_addr(hw,
494 mc_addr_list +
495 (i *
496 (IXGB_ETH_LENGTH_OF_ADDRESS
497 + pad)));
498
499 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
500
501 ixgb_mta_set(hw, hash_value);
502 }
503 }
504
505 DEBUGOUT("MC Update Complete\n");
506 return;
507 }
508
509 /******************************************************************************
510 * Hashes an address to determine its location in the multicast table
511 *
512 * hw - Struct containing variables accessed by shared code
513 * mc_addr - the multicast address to hash
514 *
515 * Returns:
516 * The hash value
517 *****************************************************************************/
518 static u32
519 ixgb_hash_mc_addr(struct ixgb_hw *hw,
520 u8 *mc_addr)
521 {
522 u32 hash_value = 0;
523
524 DEBUGFUNC("ixgb_hash_mc_addr");
525
526 /* The portion of the address that is used for the hash table is
527 * determined by the mc_filter_type setting.
528 */
529 switch (hw->mc_filter_type) {
530 /* [0] [1] [2] [3] [4] [5]
531 * 01 AA 00 12 34 56
532 * LSB MSB - According to H/W docs */
533 case 0:
534 /* [47:36] i.e. 0x563 for above example address */
535 hash_value =
536 ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4));
537 break;
538 case 1: /* [46:35] i.e. 0xAC6 for above example address */
539 hash_value =
540 ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5));
541 break;
542 case 2: /* [45:34] i.e. 0x5D8 for above example address */
543 hash_value =
544 ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6));
545 break;
546 case 3: /* [43:32] i.e. 0x634 for above example address */
547 hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8));
548 break;
549 default:
550 /* Invalid mc_filter_type, what should we do? */
551 DEBUGOUT("MC filter type param set incorrectly\n");
552 ASSERT(0);
553 break;
554 }
555
556 hash_value &= 0xFFF;
557 return (hash_value);
558 }
559
560 /******************************************************************************
561 * Sets the bit in the multicast table corresponding to the hash value.
562 *
563 * hw - Struct containing variables accessed by shared code
564 * hash_value - Multicast address hash value
565 *****************************************************************************/
566 static void
567 ixgb_mta_set(struct ixgb_hw *hw,
568 u32 hash_value)
569 {
570 u32 hash_bit, hash_reg;
571 u32 mta_reg;
572
573 /* The MTA is a register array of 128 32-bit registers.
574 * It is treated like an array of 4096 bits. We want to set
575 * bit BitArray[hash_value]. So we figure out what register
576 * the bit is in, read it, OR in the new bit, then write
577 * back the new value. The register is determined by the
578 * upper 7 bits of the hash value and the bit within that
579 * register are determined by the lower 5 bits of the value.
580 */
581 hash_reg = (hash_value >> 5) & 0x7F;
582 hash_bit = hash_value & 0x1F;
583
584 mta_reg = IXGB_READ_REG_ARRAY(hw, MTA, hash_reg);
585
586 mta_reg |= (1 << hash_bit);
587
588 IXGB_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta_reg);
589
590 return;
591 }
592
593 /******************************************************************************
594 * Puts an ethernet address into a receive address register.
595 *
596 * hw - Struct containing variables accessed by shared code
597 * addr - Address to put into receive address register
598 * index - Receive address register to write
599 *****************************************************************************/
600 void
601 ixgb_rar_set(struct ixgb_hw *hw,
602 u8 *addr,
603 u32 index)
604 {
605 u32 rar_low, rar_high;
606
607 DEBUGFUNC("ixgb_rar_set");
608
609 /* HW expects these in little endian so we reverse the byte order
610 * from network order (big endian) to little endian
611 */
612 rar_low = ((u32) addr[0] |
613 ((u32)addr[1] << 8) |
614 ((u32)addr[2] << 16) |
615 ((u32)addr[3] << 24));
616
617 rar_high = ((u32) addr[4] |
618 ((u32)addr[5] << 8) |
619 IXGB_RAH_AV);
620
621 IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
622 IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
623 return;
624 }
625
626 /******************************************************************************
627 * Writes a value to the specified offset in the VLAN filter table.
628 *
629 * hw - Struct containing variables accessed by shared code
630 * offset - Offset in VLAN filer table to write
631 * value - Value to write into VLAN filter table
632 *****************************************************************************/
633 void
634 ixgb_write_vfta(struct ixgb_hw *hw,
635 u32 offset,
636 u32 value)
637 {
638 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value);
639 return;
640 }
641
642 /******************************************************************************
643 * Clears the VLAN filer table
644 *
645 * hw - Struct containing variables accessed by shared code
646 *****************************************************************************/
647 static void
648 ixgb_clear_vfta(struct ixgb_hw *hw)
649 {
650 u32 offset;
651
652 for(offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++)
653 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
654 return;
655 }
656
657 /******************************************************************************
658 * Configures the flow control settings based on SW configuration.
659 *
660 * hw - Struct containing variables accessed by shared code
661 *****************************************************************************/
662
663 static bool
664 ixgb_setup_fc(struct ixgb_hw *hw)
665 {
666 u32 ctrl_reg;
667 u32 pap_reg = 0; /* by default, assume no pause time */
668 bool status = true;
669
670 DEBUGFUNC("ixgb_setup_fc");
671
672 /* Get the current control reg 0 settings */
673 ctrl_reg = IXGB_READ_REG(hw, CTRL0);
674
675 /* Clear the Receive Pause Enable and Transmit Pause Enable bits */
676 ctrl_reg &= ~(IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
677
678 /* The possible values of the "flow_control" parameter are:
679 * 0: Flow control is completely disabled
680 * 1: Rx flow control is enabled (we can receive pause frames
681 * but not send pause frames).
682 * 2: Tx flow control is enabled (we can send pause frames
683 * but we do not support receiving pause frames).
684 * 3: Both Rx and TX flow control (symmetric) are enabled.
685 * other: Invalid.
686 */
687 switch (hw->fc.type) {
688 case ixgb_fc_none: /* 0 */
689 /* Set CMDC bit to disable Rx Flow control */
690 ctrl_reg |= (IXGB_CTRL0_CMDC);
691 break;
692 case ixgb_fc_rx_pause: /* 1 */
693 /* RX Flow control is enabled, and TX Flow control is
694 * disabled.
695 */
696 ctrl_reg |= (IXGB_CTRL0_RPE);
697 break;
698 case ixgb_fc_tx_pause: /* 2 */
699 /* TX Flow control is enabled, and RX Flow control is
700 * disabled, by a software over-ride.
701 */
702 ctrl_reg |= (IXGB_CTRL0_TPE);
703 pap_reg = hw->fc.pause_time;
704 break;
705 case ixgb_fc_full: /* 3 */
706 /* Flow control (both RX and TX) is enabled by a software
707 * over-ride.
708 */
709 ctrl_reg |= (IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
710 pap_reg = hw->fc.pause_time;
711 break;
712 default:
713 /* We should never get here. The value should be 0-3. */
714 DEBUGOUT("Flow control param set incorrectly\n");
715 ASSERT(0);
716 break;
717 }
718
719 /* Write the new settings */
720 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
721
722 if (pap_reg != 0) {
723 IXGB_WRITE_REG(hw, PAP, pap_reg);
724 }
725
726 /* Set the flow control receive threshold registers. Normally,
727 * these registers will be set to a default threshold that may be
728 * adjusted later by the driver's runtime code. However, if the
729 * ability to transmit pause frames in not enabled, then these
730 * registers will be set to 0.
731 */
732 if(!(hw->fc.type & ixgb_fc_tx_pause)) {
733 IXGB_WRITE_REG(hw, FCRTL, 0);
734 IXGB_WRITE_REG(hw, FCRTH, 0);
735 } else {
736 /* We need to set up the Receive Threshold high and low water
737 * marks as well as (optionally) enabling the transmission of XON
738 * frames. */
739 if(hw->fc.send_xon) {
740 IXGB_WRITE_REG(hw, FCRTL,
741 (hw->fc.low_water | IXGB_FCRTL_XONE));
742 } else {
743 IXGB_WRITE_REG(hw, FCRTL, hw->fc.low_water);
744 }
745 IXGB_WRITE_REG(hw, FCRTH, hw->fc.high_water);
746 }
747 return (status);
748 }
749
750 /******************************************************************************
751 * Reads a word from a device over the Management Data Interface (MDI) bus.
752 * This interface is used to manage Physical layer devices.
753 *
754 * hw - Struct containing variables accessed by hw code
755 * reg_address - Offset of device register being read.
756 * phy_address - Address of device on MDI.
757 *
758 * Returns: Data word (16 bits) from MDI device.
759 *
760 * The 82597EX has support for several MDI access methods. This routine
761 * uses the new protocol MDI Single Command and Address Operation.
762 * This requires that first an address cycle command is sent, followed by a
763 * read command.
764 *****************************************************************************/
765 static u16
766 ixgb_read_phy_reg(struct ixgb_hw *hw,
767 u32 reg_address,
768 u32 phy_address,
769 u32 device_type)
770 {
771 u32 i;
772 u32 data;
773 u32 command = 0;
774
775 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
776 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
777 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
778
779 /* Setup and write the address cycle command */
780 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
781 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
782 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
783 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
784
785 IXGB_WRITE_REG(hw, MSCA, command);
786
787 /**************************************************************
788 ** Check every 10 usec to see if the address cycle completed
789 ** The COMMAND bit will clear when the operation is complete.
790 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
791 ** from the CPU Write to the Ready bit assertion.
792 **************************************************************/
793
794 for(i = 0; i < 10; i++)
795 {
796 udelay(10);
797
798 command = IXGB_READ_REG(hw, MSCA);
799
800 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
801 break;
802 }
803
804 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
805
806 /* Address cycle complete, setup and write the read command */
807 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
808 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
809 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
810 (IXGB_MSCA_READ | IXGB_MSCA_MDI_COMMAND));
811
812 IXGB_WRITE_REG(hw, MSCA, command);
813
814 /**************************************************************
815 ** Check every 10 usec to see if the read command completed
816 ** The COMMAND bit will clear when the operation is complete.
817 ** The read may take as long as 64 usecs (we'll wait 100 usecs max)
818 ** from the CPU Write to the Ready bit assertion.
819 **************************************************************/
820
821 for(i = 0; i < 10; i++)
822 {
823 udelay(10);
824
825 command = IXGB_READ_REG(hw, MSCA);
826
827 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
828 break;
829 }
830
831 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
832
833 /* Operation is complete, get the data from the MDIO Read/Write Data
834 * register and return.
835 */
836 data = IXGB_READ_REG(hw, MSRWD);
837 data >>= IXGB_MSRWD_READ_DATA_SHIFT;
838 return((u16) data);
839 }
840
841 /******************************************************************************
842 * Writes a word to a device over the Management Data Interface (MDI) bus.
843 * This interface is used to manage Physical layer devices.
844 *
845 * hw - Struct containing variables accessed by hw code
846 * reg_address - Offset of device register being read.
847 * phy_address - Address of device on MDI.
848 * device_type - Also known as the Device ID or DID.
849 * data - 16-bit value to be written
850 *
851 * Returns: void.
852 *
853 * The 82597EX has support for several MDI access methods. This routine
854 * uses the new protocol MDI Single Command and Address Operation.
855 * This requires that first an address cycle command is sent, followed by a
856 * write command.
857 *****************************************************************************/
858 static void
859 ixgb_write_phy_reg(struct ixgb_hw *hw,
860 u32 reg_address,
861 u32 phy_address,
862 u32 device_type,
863 u16 data)
864 {
865 u32 i;
866 u32 command = 0;
867
868 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
869 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
870 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
871
872 /* Put the data in the MDIO Read/Write Data register */
873 IXGB_WRITE_REG(hw, MSRWD, (u32)data);
874
875 /* Setup and write the address cycle command */
876 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
877 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
878 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
879 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
880
881 IXGB_WRITE_REG(hw, MSCA, command);
882
883 /**************************************************************
884 ** Check every 10 usec to see if the address cycle completed
885 ** The COMMAND bit will clear when the operation is complete.
886 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
887 ** from the CPU Write to the Ready bit assertion.
888 **************************************************************/
889
890 for(i = 0; i < 10; i++)
891 {
892 udelay(10);
893
894 command = IXGB_READ_REG(hw, MSCA);
895
896 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
897 break;
898 }
899
900 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
901
902 /* Address cycle complete, setup and write the write command */
903 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
904 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
905 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
906 (IXGB_MSCA_WRITE | IXGB_MSCA_MDI_COMMAND));
907
908 IXGB_WRITE_REG(hw, MSCA, command);
909
910 /**************************************************************
911 ** Check every 10 usec to see if the read command completed
912 ** The COMMAND bit will clear when the operation is complete.
913 ** The write may take as long as 64 usecs (we'll wait 100 usecs max)
914 ** from the CPU Write to the Ready bit assertion.
915 **************************************************************/
916
917 for(i = 0; i < 10; i++)
918 {
919 udelay(10);
920
921 command = IXGB_READ_REG(hw, MSCA);
922
923 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
924 break;
925 }
926
927 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
928
929 /* Operation is complete, return. */
930 }
931
932 /******************************************************************************
933 * Checks to see if the link status of the hardware has changed.
934 *
935 * hw - Struct containing variables accessed by hw code
936 *
937 * Called by any function that needs to check the link status of the adapter.
938 *****************************************************************************/
939 void
940 ixgb_check_for_link(struct ixgb_hw *hw)
941 {
942 u32 status_reg;
943 u32 xpcss_reg;
944
945 DEBUGFUNC("ixgb_check_for_link");
946
947 xpcss_reg = IXGB_READ_REG(hw, XPCSS);
948 status_reg = IXGB_READ_REG(hw, STATUS);
949
950 if ((xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
951 (status_reg & IXGB_STATUS_LU)) {
952 hw->link_up = true;
953 } else if (!(xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
954 (status_reg & IXGB_STATUS_LU)) {
955 DEBUGOUT("XPCSS Not Aligned while Status:LU is set.\n");
956 hw->link_up = ixgb_link_reset(hw);
957 } else {
958 /*
959 * 82597EX errata. Since the lane deskew problem may prevent
960 * link, reset the link before reporting link down.
961 */
962 hw->link_up = ixgb_link_reset(hw);
963 }
964 /* Anything else for 10 Gig?? */
965 }
966
967 /******************************************************************************
968 * Check for a bad link condition that may have occured.
969 * The indication is that the RFC / LFC registers may be incrementing
970 * continually. A full adapter reset is required to recover.
971 *
972 * hw - Struct containing variables accessed by hw code
973 *
974 * Called by any function that needs to check the link status of the adapter.
975 *****************************************************************************/
976 bool ixgb_check_for_bad_link(struct ixgb_hw *hw)
977 {
978 u32 newLFC, newRFC;
979 bool bad_link_returncode = false;
980
981 if (hw->phy_type == ixgb_phy_type_txn17401) {
982 newLFC = IXGB_READ_REG(hw, LFC);
983 newRFC = IXGB_READ_REG(hw, RFC);
984 if ((hw->lastLFC + 250 < newLFC)
985 || (hw->lastRFC + 250 < newRFC)) {
986 DEBUGOUT
987 ("BAD LINK! too many LFC/RFC since last check\n");
988 bad_link_returncode = true;
989 }
990 hw->lastLFC = newLFC;
991 hw->lastRFC = newRFC;
992 }
993
994 return bad_link_returncode;
995 }
996
997 /******************************************************************************
998 * Clears all hardware statistics counters.
999 *
1000 * hw - Struct containing variables accessed by shared code
1001 *****************************************************************************/
1002 static void
1003 ixgb_clear_hw_cntrs(struct ixgb_hw *hw)
1004 {
1005 volatile u32 temp_reg;
1006
1007 DEBUGFUNC("ixgb_clear_hw_cntrs");
1008
1009 /* if we are stopped or resetting exit gracefully */
1010 if(hw->adapter_stopped) {
1011 DEBUGOUT("Exiting because the adapter is stopped!!!\n");
1012 return;
1013 }
1014
1015 temp_reg = IXGB_READ_REG(hw, TPRL);
1016 temp_reg = IXGB_READ_REG(hw, TPRH);
1017 temp_reg = IXGB_READ_REG(hw, GPRCL);
1018 temp_reg = IXGB_READ_REG(hw, GPRCH);
1019 temp_reg = IXGB_READ_REG(hw, BPRCL);
1020 temp_reg = IXGB_READ_REG(hw, BPRCH);
1021 temp_reg = IXGB_READ_REG(hw, MPRCL);
1022 temp_reg = IXGB_READ_REG(hw, MPRCH);
1023 temp_reg = IXGB_READ_REG(hw, UPRCL);
1024 temp_reg = IXGB_READ_REG(hw, UPRCH);
1025 temp_reg = IXGB_READ_REG(hw, VPRCL);
1026 temp_reg = IXGB_READ_REG(hw, VPRCH);
1027 temp_reg = IXGB_READ_REG(hw, JPRCL);
1028 temp_reg = IXGB_READ_REG(hw, JPRCH);
1029 temp_reg = IXGB_READ_REG(hw, GORCL);
1030 temp_reg = IXGB_READ_REG(hw, GORCH);
1031 temp_reg = IXGB_READ_REG(hw, TORL);
1032 temp_reg = IXGB_READ_REG(hw, TORH);
1033 temp_reg = IXGB_READ_REG(hw, RNBC);
1034 temp_reg = IXGB_READ_REG(hw, RUC);
1035 temp_reg = IXGB_READ_REG(hw, ROC);
1036 temp_reg = IXGB_READ_REG(hw, RLEC);
1037 temp_reg = IXGB_READ_REG(hw, CRCERRS);
1038 temp_reg = IXGB_READ_REG(hw, ICBC);
1039 temp_reg = IXGB_READ_REG(hw, ECBC);
1040 temp_reg = IXGB_READ_REG(hw, MPC);
1041 temp_reg = IXGB_READ_REG(hw, TPTL);
1042 temp_reg = IXGB_READ_REG(hw, TPTH);
1043 temp_reg = IXGB_READ_REG(hw, GPTCL);
1044 temp_reg = IXGB_READ_REG(hw, GPTCH);
1045 temp_reg = IXGB_READ_REG(hw, BPTCL);
1046 temp_reg = IXGB_READ_REG(hw, BPTCH);
1047 temp_reg = IXGB_READ_REG(hw, MPTCL);
1048 temp_reg = IXGB_READ_REG(hw, MPTCH);
1049 temp_reg = IXGB_READ_REG(hw, UPTCL);
1050 temp_reg = IXGB_READ_REG(hw, UPTCH);
1051 temp_reg = IXGB_READ_REG(hw, VPTCL);
1052 temp_reg = IXGB_READ_REG(hw, VPTCH);
1053 temp_reg = IXGB_READ_REG(hw, JPTCL);
1054 temp_reg = IXGB_READ_REG(hw, JPTCH);
1055 temp_reg = IXGB_READ_REG(hw, GOTCL);
1056 temp_reg = IXGB_READ_REG(hw, GOTCH);
1057 temp_reg = IXGB_READ_REG(hw, TOTL);
1058 temp_reg = IXGB_READ_REG(hw, TOTH);
1059 temp_reg = IXGB_READ_REG(hw, DC);
1060 temp_reg = IXGB_READ_REG(hw, PLT64C);
1061 temp_reg = IXGB_READ_REG(hw, TSCTC);
1062 temp_reg = IXGB_READ_REG(hw, TSCTFC);
1063 temp_reg = IXGB_READ_REG(hw, IBIC);
1064 temp_reg = IXGB_READ_REG(hw, RFC);
1065 temp_reg = IXGB_READ_REG(hw, LFC);
1066 temp_reg = IXGB_READ_REG(hw, PFRC);
1067 temp_reg = IXGB_READ_REG(hw, PFTC);
1068 temp_reg = IXGB_READ_REG(hw, MCFRC);
1069 temp_reg = IXGB_READ_REG(hw, MCFTC);
1070 temp_reg = IXGB_READ_REG(hw, XONRXC);
1071 temp_reg = IXGB_READ_REG(hw, XONTXC);
1072 temp_reg = IXGB_READ_REG(hw, XOFFRXC);
1073 temp_reg = IXGB_READ_REG(hw, XOFFTXC);
1074 temp_reg = IXGB_READ_REG(hw, RJC);
1075 return;
1076 }
1077
1078 /******************************************************************************
1079 * Turns on the software controllable LED
1080 *
1081 * hw - Struct containing variables accessed by shared code
1082 *****************************************************************************/
1083 void
1084 ixgb_led_on(struct ixgb_hw *hw)
1085 {
1086 u32 ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
1087
1088 /* To turn on the LED, clear software-definable pin 0 (SDP0). */
1089 ctrl0_reg &= ~IXGB_CTRL0_SDP0;
1090 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
1091 return;
1092 }
1093
1094 /******************************************************************************
1095 * Turns off the software controllable LED
1096 *
1097 * hw - Struct containing variables accessed by shared code
1098 *****************************************************************************/
1099 void
1100 ixgb_led_off(struct ixgb_hw *hw)
1101 {
1102 u32 ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
1103
1104 /* To turn off the LED, set software-definable pin 0 (SDP0). */
1105 ctrl0_reg |= IXGB_CTRL0_SDP0;
1106 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
1107 return;
1108 }
1109
1110 /******************************************************************************
1111 * Gets the current PCI bus type, speed, and width of the hardware
1112 *
1113 * hw - Struct containing variables accessed by shared code
1114 *****************************************************************************/
1115 static void
1116 ixgb_get_bus_info(struct ixgb_hw *hw)
1117 {
1118 u32 status_reg;
1119
1120 status_reg = IXGB_READ_REG(hw, STATUS);
1121
1122 hw->bus.type = (status_reg & IXGB_STATUS_PCIX_MODE) ?
1123 ixgb_bus_type_pcix : ixgb_bus_type_pci;
1124
1125 if (hw->bus.type == ixgb_bus_type_pci) {
1126 hw->bus.speed = (status_reg & IXGB_STATUS_PCI_SPD) ?
1127 ixgb_bus_speed_66 : ixgb_bus_speed_33;
1128 } else {
1129 switch (status_reg & IXGB_STATUS_PCIX_SPD_MASK) {
1130 case IXGB_STATUS_PCIX_SPD_66:
1131 hw->bus.speed = ixgb_bus_speed_66;
1132 break;
1133 case IXGB_STATUS_PCIX_SPD_100:
1134 hw->bus.speed = ixgb_bus_speed_100;
1135 break;
1136 case IXGB_STATUS_PCIX_SPD_133:
1137 hw->bus.speed = ixgb_bus_speed_133;
1138 break;
1139 default:
1140 hw->bus.speed = ixgb_bus_speed_reserved;
1141 break;
1142 }
1143 }
1144
1145 hw->bus.width = (status_reg & IXGB_STATUS_BUS64) ?
1146 ixgb_bus_width_64 : ixgb_bus_width_32;
1147
1148 return;
1149 }
1150
1151 /******************************************************************************
1152 * Tests a MAC address to ensure it is a valid Individual Address
1153 *
1154 * mac_addr - pointer to MAC address.
1155 *
1156 *****************************************************************************/
1157 static bool
1158 mac_addr_valid(u8 *mac_addr)
1159 {
1160 bool is_valid = true;
1161 DEBUGFUNC("mac_addr_valid");
1162
1163 /* Make sure it is not a multicast address */
1164 if (IS_MULTICAST(mac_addr)) {
1165 DEBUGOUT("MAC address is multicast\n");
1166 is_valid = false;
1167 }
1168 /* Not a broadcast address */
1169 else if (IS_BROADCAST(mac_addr)) {
1170 DEBUGOUT("MAC address is broadcast\n");
1171 is_valid = false;
1172 }
1173 /* Reject the zero address */
1174 else if (mac_addr[0] == 0 &&
1175 mac_addr[1] == 0 &&
1176 mac_addr[2] == 0 &&
1177 mac_addr[3] == 0 &&
1178 mac_addr[4] == 0 &&
1179 mac_addr[5] == 0) {
1180 DEBUGOUT("MAC address is all zeros\n");
1181 is_valid = false;
1182 }
1183 return (is_valid);
1184 }
1185
1186 /******************************************************************************
1187 * Resets the 10GbE link. Waits the settle time and returns the state of
1188 * the link.
1189 *
1190 * hw - Struct containing variables accessed by shared code
1191 *****************************************************************************/
1192 static bool
1193 ixgb_link_reset(struct ixgb_hw *hw)
1194 {
1195 bool link_status = false;
1196 u8 wait_retries = MAX_RESET_ITERATIONS;
1197 u8 lrst_retries = MAX_RESET_ITERATIONS;
1198
1199 do {
1200 /* Reset the link */
1201 IXGB_WRITE_REG(hw, CTRL0,
1202 IXGB_READ_REG(hw, CTRL0) | IXGB_CTRL0_LRST);
1203
1204 /* Wait for link-up and lane re-alignment */
1205 do {
1206 udelay(IXGB_DELAY_USECS_AFTER_LINK_RESET);
1207 link_status =
1208 ((IXGB_READ_REG(hw, STATUS) & IXGB_STATUS_LU)
1209 && (IXGB_READ_REG(hw, XPCSS) &
1210 IXGB_XPCSS_ALIGN_STATUS)) ? true : false;
1211 } while (!link_status && --wait_retries);
1212
1213 } while (!link_status && --lrst_retries);
1214
1215 return link_status;
1216 }
1217
1218 /******************************************************************************
1219 * Resets the 10GbE optics module.
1220 *
1221 * hw - Struct containing variables accessed by shared code
1222 *****************************************************************************/
1223 static void
1224 ixgb_optics_reset(struct ixgb_hw *hw)
1225 {
1226 if (hw->phy_type == ixgb_phy_type_txn17401) {
1227 u16 mdio_reg;
1228
1229 ixgb_write_phy_reg(hw,
1230 MDIO_PMA_PMD_CR1,
1231 IXGB_PHY_ADDRESS,
1232 MDIO_PMA_PMD_DID,
1233 MDIO_PMA_PMD_CR1_RESET);
1234
1235 mdio_reg = ixgb_read_phy_reg( hw,
1236 MDIO_PMA_PMD_CR1,
1237 IXGB_PHY_ADDRESS,
1238 MDIO_PMA_PMD_DID);
1239 }
1240
1241 return;
1242 }
1243
1244 /******************************************************************************
1245 * Resets the 10GbE optics module for Sun variant NIC.
1246 *
1247 * hw - Struct containing variables accessed by shared code
1248 *****************************************************************************/
1249
1250 #define IXGB_BCM8704_USER_PMD_TX_CTRL_REG 0xC803
1251 #define IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL 0x0164
1252 #define IXGB_BCM8704_USER_CTRL_REG 0xC800
1253 #define IXGB_BCM8704_USER_CTRL_REG_VAL 0x7FBF
1254 #define IXGB_BCM8704_USER_DEV3_ADDR 0x0003
1255 #define IXGB_SUN_PHY_ADDRESS 0x0000
1256 #define IXGB_SUN_PHY_RESET_DELAY 305
1257
1258 static void
1259 ixgb_optics_reset_bcm(struct ixgb_hw *hw)
1260 {
1261 u32 ctrl = IXGB_READ_REG(hw, CTRL0);
1262 ctrl &= ~IXGB_CTRL0_SDP2;
1263 ctrl |= IXGB_CTRL0_SDP3;
1264 IXGB_WRITE_REG(hw, CTRL0, ctrl);
1265
1266 /* SerDes needs extra delay */
1267 msleep(IXGB_SUN_PHY_RESET_DELAY);
1268
1269 /* Broadcom 7408L configuration */
1270 /* Reference clock config */
1271 ixgb_write_phy_reg(hw,
1272 IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1273 IXGB_SUN_PHY_ADDRESS,
1274 IXGB_BCM8704_USER_DEV3_ADDR,
1275 IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL);
1276 /* we must read the registers twice */
1277 ixgb_read_phy_reg(hw,
1278 IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1279 IXGB_SUN_PHY_ADDRESS,
1280 IXGB_BCM8704_USER_DEV3_ADDR);
1281 ixgb_read_phy_reg(hw,
1282 IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1283 IXGB_SUN_PHY_ADDRESS,
1284 IXGB_BCM8704_USER_DEV3_ADDR);
1285
1286 ixgb_write_phy_reg(hw,
1287 IXGB_BCM8704_USER_CTRL_REG,
1288 IXGB_SUN_PHY_ADDRESS,
1289 IXGB_BCM8704_USER_DEV3_ADDR,
1290 IXGB_BCM8704_USER_CTRL_REG_VAL);
1291 ixgb_read_phy_reg(hw,
1292 IXGB_BCM8704_USER_CTRL_REG,
1293 IXGB_SUN_PHY_ADDRESS,
1294 IXGB_BCM8704_USER_DEV3_ADDR);
1295 ixgb_read_phy_reg(hw,
1296 IXGB_BCM8704_USER_CTRL_REG,
1297 IXGB_SUN_PHY_ADDRESS,
1298 IXGB_BCM8704_USER_DEV3_ADDR);
1299
1300 /* SerDes needs extra delay */
1301 msleep(IXGB_SUN_PHY_RESET_DELAY);
1302
1303 return;
1304 }
Linux kernel - Deliverables
This page took 0.063633 seconds and 6 git commands to generate.