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Merge branches 'release', 'asus', 'sony-laptop' and 'thinkpad' into release
[deliverable/linux.git] / drivers / net / ixgb / ixgb_hw.c
1 /*******************************************************************************
2
3 Intel PRO/10GbE Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /* ixgb_hw.c
30 * Shared functions for accessing and configuring the adapter
31 */
32
33 #include "ixgb_hw.h"
34 #include "ixgb_ids.h"
35
36 /* Local function prototypes */
37
38 static uint32_t ixgb_hash_mc_addr(struct ixgb_hw *hw, uint8_t * mc_addr);
39
40 static void ixgb_mta_set(struct ixgb_hw *hw, uint32_t hash_value);
41
42 static void ixgb_get_bus_info(struct ixgb_hw *hw);
43
44 static boolean_t ixgb_link_reset(struct ixgb_hw *hw);
45
46 static void ixgb_optics_reset(struct ixgb_hw *hw);
47
48 static void ixgb_optics_reset_bcm(struct ixgb_hw *hw);
49
50 static ixgb_phy_type ixgb_identify_phy(struct ixgb_hw *hw);
51
52 static void ixgb_clear_hw_cntrs(struct ixgb_hw *hw);
53
54 static void ixgb_clear_vfta(struct ixgb_hw *hw);
55
56 static void ixgb_init_rx_addrs(struct ixgb_hw *hw);
57
58 static uint16_t ixgb_read_phy_reg(struct ixgb_hw *hw,
59 uint32_t reg_address,
60 uint32_t phy_address,
61 uint32_t device_type);
62
63 static boolean_t ixgb_setup_fc(struct ixgb_hw *hw);
64
65 static boolean_t mac_addr_valid(uint8_t *mac_addr);
66
67 static uint32_t ixgb_mac_reset(struct ixgb_hw *hw)
68 {
69 uint32_t ctrl_reg;
70
71 ctrl_reg = IXGB_CTRL0_RST |
72 IXGB_CTRL0_SDP3_DIR | /* All pins are Output=1 */
73 IXGB_CTRL0_SDP2_DIR |
74 IXGB_CTRL0_SDP1_DIR |
75 IXGB_CTRL0_SDP0_DIR |
76 IXGB_CTRL0_SDP3 | /* Initial value 1101 */
77 IXGB_CTRL0_SDP2 |
78 IXGB_CTRL0_SDP0;
79
80 #ifdef HP_ZX1
81 /* Workaround for 82597EX reset errata */
82 IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg);
83 #else
84 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
85 #endif
86
87 /* Delay a few ms just to allow the reset to complete */
88 msleep(IXGB_DELAY_AFTER_RESET);
89 ctrl_reg = IXGB_READ_REG(hw, CTRL0);
90 #ifdef DBG
91 /* Make sure the self-clearing global reset bit did self clear */
92 ASSERT(!(ctrl_reg & IXGB_CTRL0_RST));
93 #endif
94
95 if (hw->subsystem_vendor_id == SUN_SUBVENDOR_ID) {
96 ctrl_reg = /* Enable interrupt from XFP and SerDes */
97 IXGB_CTRL1_GPI0_EN |
98 IXGB_CTRL1_SDP6_DIR |
99 IXGB_CTRL1_SDP7_DIR |
100 IXGB_CTRL1_SDP6 |
101 IXGB_CTRL1_SDP7;
102 IXGB_WRITE_REG(hw, CTRL1, ctrl_reg);
103 ixgb_optics_reset_bcm(hw);
104 }
105
106 if (hw->phy_type == ixgb_phy_type_txn17401)
107 ixgb_optics_reset(hw);
108
109 return ctrl_reg;
110 }
111
112 /******************************************************************************
113 * Reset the transmit and receive units; mask and clear all interrupts.
114 *
115 * hw - Struct containing variables accessed by shared code
116 *****************************************************************************/
117 boolean_t
118 ixgb_adapter_stop(struct ixgb_hw *hw)
119 {
120 uint32_t ctrl_reg;
121 uint32_t icr_reg;
122
123 DEBUGFUNC("ixgb_adapter_stop");
124
125 /* If we are stopped or resetting exit gracefully and wait to be
126 * started again before accessing the hardware.
127 */
128 if(hw->adapter_stopped) {
129 DEBUGOUT("Exiting because the adapter is already stopped!!!\n");
130 return FALSE;
131 }
132
133 /* Set the Adapter Stopped flag so other driver functions stop
134 * touching the Hardware.
135 */
136 hw->adapter_stopped = TRUE;
137
138 /* Clear interrupt mask to stop board from generating interrupts */
139 DEBUGOUT("Masking off all interrupts\n");
140 IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF);
141
142 /* Disable the Transmit and Receive units. Then delay to allow
143 * any pending transactions to complete before we hit the MAC with
144 * the global reset.
145 */
146 IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN);
147 IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN);
148 msleep(IXGB_DELAY_BEFORE_RESET);
149
150 /* Issue a global reset to the MAC. This will reset the chip's
151 * transmit, receive, DMA, and link units. It will not effect
152 * the current PCI configuration. The global reset bit is self-
153 * clearing, and should clear within a microsecond.
154 */
155 DEBUGOUT("Issuing a global reset to MAC\n");
156
157 ctrl_reg = ixgb_mac_reset(hw);
158
159 /* Clear interrupt mask to stop board from generating interrupts */
160 DEBUGOUT("Masking off all interrupts\n");
161 IXGB_WRITE_REG(hw, IMC, 0xffffffff);
162
163 /* Clear any pending interrupt events. */
164 icr_reg = IXGB_READ_REG(hw, ICR);
165
166 return (ctrl_reg & IXGB_CTRL0_RST);
167 }
168
169
170 /******************************************************************************
171 * Identifies the vendor of the optics module on the adapter. The SR adapters
172 * support two different types of XPAK optics, so it is necessary to determine
173 * which optics are present before applying any optics-specific workarounds.
174 *
175 * hw - Struct containing variables accessed by shared code.
176 *
177 * Returns: the vendor of the XPAK optics module.
178 *****************************************************************************/
179 static ixgb_xpak_vendor
180 ixgb_identify_xpak_vendor(struct ixgb_hw *hw)
181 {
182 uint32_t i;
183 uint16_t vendor_name[5];
184 ixgb_xpak_vendor xpak_vendor;
185
186 DEBUGFUNC("ixgb_identify_xpak_vendor");
187
188 /* Read the first few bytes of the vendor string from the XPAK NVR
189 * registers. These are standard XENPAK/XPAK registers, so all XPAK
190 * devices should implement them. */
191 for (i = 0; i < 5; i++) {
192 vendor_name[i] = ixgb_read_phy_reg(hw,
193 MDIO_PMA_PMD_XPAK_VENDOR_NAME
194 + i, IXGB_PHY_ADDRESS,
195 MDIO_PMA_PMD_DID);
196 }
197
198 /* Determine the actual vendor */
199 if (vendor_name[0] == 'I' &&
200 vendor_name[1] == 'N' &&
201 vendor_name[2] == 'T' &&
202 vendor_name[3] == 'E' && vendor_name[4] == 'L') {
203 xpak_vendor = ixgb_xpak_vendor_intel;
204 } else {
205 xpak_vendor = ixgb_xpak_vendor_infineon;
206 }
207
208 return (xpak_vendor);
209 }
210
211 /******************************************************************************
212 * Determine the physical layer module on the adapter.
213 *
214 * hw - Struct containing variables accessed by shared code. The device_id
215 * field must be (correctly) populated before calling this routine.
216 *
217 * Returns: the phy type of the adapter.
218 *****************************************************************************/
219 static ixgb_phy_type
220 ixgb_identify_phy(struct ixgb_hw *hw)
221 {
222 ixgb_phy_type phy_type;
223 ixgb_xpak_vendor xpak_vendor;
224
225 DEBUGFUNC("ixgb_identify_phy");
226
227 /* Infer the transceiver/phy type from the device id */
228 switch (hw->device_id) {
229 case IXGB_DEVICE_ID_82597EX:
230 DEBUGOUT("Identified TXN17401 optics\n");
231 phy_type = ixgb_phy_type_txn17401;
232 break;
233
234 case IXGB_DEVICE_ID_82597EX_SR:
235 /* The SR adapters carry two different types of XPAK optics
236 * modules; read the vendor identifier to determine the exact
237 * type of optics. */
238 xpak_vendor = ixgb_identify_xpak_vendor(hw);
239 if (xpak_vendor == ixgb_xpak_vendor_intel) {
240 DEBUGOUT("Identified TXN17201 optics\n");
241 phy_type = ixgb_phy_type_txn17201;
242 } else {
243 DEBUGOUT("Identified G6005 optics\n");
244 phy_type = ixgb_phy_type_g6005;
245 }
246 break;
247 case IXGB_DEVICE_ID_82597EX_LR:
248 DEBUGOUT("Identified G6104 optics\n");
249 phy_type = ixgb_phy_type_g6104;
250 break;
251 case IXGB_DEVICE_ID_82597EX_CX4:
252 DEBUGOUT("Identified CX4\n");
253 xpak_vendor = ixgb_identify_xpak_vendor(hw);
254 if (xpak_vendor == ixgb_xpak_vendor_intel) {
255 DEBUGOUT("Identified TXN17201 optics\n");
256 phy_type = ixgb_phy_type_txn17201;
257 } else {
258 DEBUGOUT("Identified G6005 optics\n");
259 phy_type = ixgb_phy_type_g6005;
260 }
261 break;
262 default:
263 DEBUGOUT("Unknown physical layer module\n");
264 phy_type = ixgb_phy_type_unknown;
265 break;
266 }
267
268 /* update phy type for sun specific board */
269 if (hw->subsystem_vendor_id == SUN_SUBVENDOR_ID)
270 phy_type = ixgb_phy_type_bcm;
271
272 return (phy_type);
273 }
274
275 /******************************************************************************
276 * Performs basic configuration of the adapter.
277 *
278 * hw - Struct containing variables accessed by shared code
279 *
280 * Resets the controller.
281 * Reads and validates the EEPROM.
282 * Initializes the receive address registers.
283 * Initializes the multicast table.
284 * Clears all on-chip counters.
285 * Calls routine to setup flow control settings.
286 * Leaves the transmit and receive units disabled and uninitialized.
287 *
288 * Returns:
289 * TRUE if successful,
290 * FALSE if unrecoverable problems were encountered.
291 *****************************************************************************/
292 boolean_t
293 ixgb_init_hw(struct ixgb_hw *hw)
294 {
295 uint32_t i;
296 uint32_t ctrl_reg;
297 boolean_t status;
298
299 DEBUGFUNC("ixgb_init_hw");
300
301 /* Issue a global reset to the MAC. This will reset the chip's
302 * transmit, receive, DMA, and link units. It will not effect
303 * the current PCI configuration. The global reset bit is self-
304 * clearing, and should clear within a microsecond.
305 */
306 DEBUGOUT("Issuing a global reset to MAC\n");
307
308 ctrl_reg = ixgb_mac_reset(hw);
309
310 DEBUGOUT("Issuing an EE reset to MAC\n");
311 #ifdef HP_ZX1
312 /* Workaround for 82597EX reset errata */
313 IXGB_WRITE_REG_IO(hw, CTRL1, IXGB_CTRL1_EE_RST);
314 #else
315 IXGB_WRITE_REG(hw, CTRL1, IXGB_CTRL1_EE_RST);
316 #endif
317
318 /* Delay a few ms just to allow the reset to complete */
319 msleep(IXGB_DELAY_AFTER_EE_RESET);
320
321 if (ixgb_get_eeprom_data(hw) == FALSE) {
322 return(FALSE);
323 }
324
325 /* Use the device id to determine the type of phy/transceiver. */
326 hw->device_id = ixgb_get_ee_device_id(hw);
327 hw->phy_type = ixgb_identify_phy(hw);
328
329 /* Setup the receive addresses.
330 * Receive Address Registers (RARs 0 - 15).
331 */
332 ixgb_init_rx_addrs(hw);
333
334 /*
335 * Check that a valid MAC address has been set.
336 * If it is not valid, we fail hardware init.
337 */
338 if (!mac_addr_valid(hw->curr_mac_addr)) {
339 DEBUGOUT("MAC address invalid after ixgb_init_rx_addrs\n");
340 return(FALSE);
341 }
342
343 /* tell the routines in this file they can access hardware again */
344 hw->adapter_stopped = FALSE;
345
346 /* Fill in the bus_info structure */
347 ixgb_get_bus_info(hw);
348
349 /* Zero out the Multicast HASH table */
350 DEBUGOUT("Zeroing the MTA\n");
351 for(i = 0; i < IXGB_MC_TBL_SIZE; i++)
352 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
353
354 /* Zero out the VLAN Filter Table Array */
355 ixgb_clear_vfta(hw);
356
357 /* Zero all of the hardware counters */
358 ixgb_clear_hw_cntrs(hw);
359
360 /* Call a subroutine to setup flow control. */
361 status = ixgb_setup_fc(hw);
362
363 /* 82597EX errata: Call check-for-link in case lane deskew is locked */
364 ixgb_check_for_link(hw);
365
366 return (status);
367 }
368
369 /******************************************************************************
370 * Initializes receive address filters.
371 *
372 * hw - Struct containing variables accessed by shared code
373 *
374 * Places the MAC address in receive address register 0 and clears the rest
375 * of the receive addresss registers. Clears the multicast table. Assumes
376 * the receiver is in reset when the routine is called.
377 *****************************************************************************/
378 static void
379 ixgb_init_rx_addrs(struct ixgb_hw *hw)
380 {
381 uint32_t i;
382
383 DEBUGFUNC("ixgb_init_rx_addrs");
384
385 /*
386 * If the current mac address is valid, assume it is a software override
387 * to the permanent address.
388 * Otherwise, use the permanent address from the eeprom.
389 */
390 if (!mac_addr_valid(hw->curr_mac_addr)) {
391
392 /* Get the MAC address from the eeprom for later reference */
393 ixgb_get_ee_mac_addr(hw, hw->curr_mac_addr);
394
395 DEBUGOUT3(" Keeping Permanent MAC Addr =%.2X %.2X %.2X ",
396 hw->curr_mac_addr[0],
397 hw->curr_mac_addr[1], hw->curr_mac_addr[2]);
398 DEBUGOUT3("%.2X %.2X %.2X\n",
399 hw->curr_mac_addr[3],
400 hw->curr_mac_addr[4], hw->curr_mac_addr[5]);
401 } else {
402
403 /* Setup the receive address. */
404 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
405 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
406 hw->curr_mac_addr[0],
407 hw->curr_mac_addr[1], hw->curr_mac_addr[2]);
408 DEBUGOUT3("%.2X %.2X %.2X\n",
409 hw->curr_mac_addr[3],
410 hw->curr_mac_addr[4], hw->curr_mac_addr[5]);
411
412 ixgb_rar_set(hw, hw->curr_mac_addr, 0);
413 }
414
415 /* Zero out the other 15 receive addresses. */
416 DEBUGOUT("Clearing RAR[1-15]\n");
417 for(i = 1; i < IXGB_RAR_ENTRIES; i++) {
418 /* Write high reg first to disable the AV bit first */
419 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
420 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
421 }
422
423 return;
424 }
425
426 /******************************************************************************
427 * Updates the MAC's list of multicast addresses.
428 *
429 * hw - Struct containing variables accessed by shared code
430 * mc_addr_list - the list of new multicast addresses
431 * mc_addr_count - number of addresses
432 * pad - number of bytes between addresses in the list
433 *
434 * The given list replaces any existing list. Clears the last 15 receive
435 * address registers and the multicast table. Uses receive address registers
436 * for the first 15 multicast addresses, and hashes the rest into the
437 * multicast table.
438 *****************************************************************************/
439 void
440 ixgb_mc_addr_list_update(struct ixgb_hw *hw,
441 uint8_t *mc_addr_list,
442 uint32_t mc_addr_count,
443 uint32_t pad)
444 {
445 uint32_t hash_value;
446 uint32_t i;
447 uint32_t rar_used_count = 1; /* RAR[0] is used for our MAC address */
448
449 DEBUGFUNC("ixgb_mc_addr_list_update");
450
451 /* Set the new number of MC addresses that we are being requested to use. */
452 hw->num_mc_addrs = mc_addr_count;
453
454 /* Clear RAR[1-15] */
455 DEBUGOUT(" Clearing RAR[1-15]\n");
456 for(i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) {
457 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
458 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
459 }
460
461 /* Clear the MTA */
462 DEBUGOUT(" Clearing MTA\n");
463 for(i = 0; i < IXGB_MC_TBL_SIZE; i++) {
464 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
465 }
466
467 /* Add the new addresses */
468 for(i = 0; i < mc_addr_count; i++) {
469 DEBUGOUT(" Adding the multicast addresses:\n");
470 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
471 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)],
472 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
473 1],
474 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
475 2],
476 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
477 3],
478 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
479 4],
480 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
481 5]);
482
483 /* Place this multicast address in the RAR if there is room, *
484 * else put it in the MTA
485 */
486 if(rar_used_count < IXGB_RAR_ENTRIES) {
487 ixgb_rar_set(hw,
488 mc_addr_list +
489 (i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)),
490 rar_used_count);
491 DEBUGOUT1("Added a multicast address to RAR[%d]\n", i);
492 rar_used_count++;
493 } else {
494 hash_value = ixgb_hash_mc_addr(hw,
495 mc_addr_list +
496 (i *
497 (IXGB_ETH_LENGTH_OF_ADDRESS
498 + pad)));
499
500 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
501
502 ixgb_mta_set(hw, hash_value);
503 }
504 }
505
506 DEBUGOUT("MC Update Complete\n");
507 return;
508 }
509
510 /******************************************************************************
511 * Hashes an address to determine its location in the multicast table
512 *
513 * hw - Struct containing variables accessed by shared code
514 * mc_addr - the multicast address to hash
515 *
516 * Returns:
517 * The hash value
518 *****************************************************************************/
519 static uint32_t
520 ixgb_hash_mc_addr(struct ixgb_hw *hw,
521 uint8_t *mc_addr)
522 {
523 uint32_t hash_value = 0;
524
525 DEBUGFUNC("ixgb_hash_mc_addr");
526
527 /* The portion of the address that is used for the hash table is
528 * determined by the mc_filter_type setting.
529 */
530 switch (hw->mc_filter_type) {
531 /* [0] [1] [2] [3] [4] [5]
532 * 01 AA 00 12 34 56
533 * LSB MSB - According to H/W docs */
534 case 0:
535 /* [47:36] i.e. 0x563 for above example address */
536 hash_value =
537 ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
538 break;
539 case 1: /* [46:35] i.e. 0xAC6 for above example address */
540 hash_value =
541 ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
542 break;
543 case 2: /* [45:34] i.e. 0x5D8 for above example address */
544 hash_value =
545 ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
546 break;
547 case 3: /* [43:32] i.e. 0x634 for above example address */
548 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
549 break;
550 default:
551 /* Invalid mc_filter_type, what should we do? */
552 DEBUGOUT("MC filter type param set incorrectly\n");
553 ASSERT(0);
554 break;
555 }
556
557 hash_value &= 0xFFF;
558 return (hash_value);
559 }
560
561 /******************************************************************************
562 * Sets the bit in the multicast table corresponding to the hash value.
563 *
564 * hw - Struct containing variables accessed by shared code
565 * hash_value - Multicast address hash value
566 *****************************************************************************/
567 static void
568 ixgb_mta_set(struct ixgb_hw *hw,
569 uint32_t hash_value)
570 {
571 uint32_t hash_bit, hash_reg;
572 uint32_t mta_reg;
573
574 /* The MTA is a register array of 128 32-bit registers.
575 * It is treated like an array of 4096 bits. We want to set
576 * bit BitArray[hash_value]. So we figure out what register
577 * the bit is in, read it, OR in the new bit, then write
578 * back the new value. The register is determined by the
579 * upper 7 bits of the hash value and the bit within that
580 * register are determined by the lower 5 bits of the value.
581 */
582 hash_reg = (hash_value >> 5) & 0x7F;
583 hash_bit = hash_value & 0x1F;
584
585 mta_reg = IXGB_READ_REG_ARRAY(hw, MTA, hash_reg);
586
587 mta_reg |= (1 << hash_bit);
588
589 IXGB_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta_reg);
590
591 return;
592 }
593
594 /******************************************************************************
595 * Puts an ethernet address into a receive address register.
596 *
597 * hw - Struct containing variables accessed by shared code
598 * addr - Address to put into receive address register
599 * index - Receive address register to write
600 *****************************************************************************/
601 void
602 ixgb_rar_set(struct ixgb_hw *hw,
603 uint8_t *addr,
604 uint32_t index)
605 {
606 uint32_t rar_low, rar_high;
607
608 DEBUGFUNC("ixgb_rar_set");
609
610 /* HW expects these in little endian so we reverse the byte order
611 * from network order (big endian) to little endian
612 */
613 rar_low = ((uint32_t) addr[0] |
614 ((uint32_t)addr[1] << 8) |
615 ((uint32_t)addr[2] << 16) |
616 ((uint32_t)addr[3] << 24));
617
618 rar_high = ((uint32_t) addr[4] |
619 ((uint32_t)addr[5] << 8) |
620 IXGB_RAH_AV);
621
622 IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
623 IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
624 return;
625 }
626
627 /******************************************************************************
628 * Writes a value to the specified offset in the VLAN filter table.
629 *
630 * hw - Struct containing variables accessed by shared code
631 * offset - Offset in VLAN filer table to write
632 * value - Value to write into VLAN filter table
633 *****************************************************************************/
634 void
635 ixgb_write_vfta(struct ixgb_hw *hw,
636 uint32_t offset,
637 uint32_t value)
638 {
639 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value);
640 return;
641 }
642
643 /******************************************************************************
644 * Clears the VLAN filer table
645 *
646 * hw - Struct containing variables accessed by shared code
647 *****************************************************************************/
648 static void
649 ixgb_clear_vfta(struct ixgb_hw *hw)
650 {
651 uint32_t offset;
652
653 for(offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++)
654 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
655 return;
656 }
657
658 /******************************************************************************
659 * Configures the flow control settings based on SW configuration.
660 *
661 * hw - Struct containing variables accessed by shared code
662 *****************************************************************************/
663
664 static boolean_t
665 ixgb_setup_fc(struct ixgb_hw *hw)
666 {
667 uint32_t ctrl_reg;
668 uint32_t pap_reg = 0; /* by default, assume no pause time */
669 boolean_t status = TRUE;
670
671 DEBUGFUNC("ixgb_setup_fc");
672
673 /* Get the current control reg 0 settings */
674 ctrl_reg = IXGB_READ_REG(hw, CTRL0);
675
676 /* Clear the Receive Pause Enable and Transmit Pause Enable bits */
677 ctrl_reg &= ~(IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
678
679 /* The possible values of the "flow_control" parameter are:
680 * 0: Flow control is completely disabled
681 * 1: Rx flow control is enabled (we can receive pause frames
682 * but not send pause frames).
683 * 2: Tx flow control is enabled (we can send pause frames
684 * but we do not support receiving pause frames).
685 * 3: Both Rx and TX flow control (symmetric) are enabled.
686 * other: Invalid.
687 */
688 switch (hw->fc.type) {
689 case ixgb_fc_none: /* 0 */
690 /* Set CMDC bit to disable Rx Flow control */
691 ctrl_reg |= (IXGB_CTRL0_CMDC);
692 break;
693 case ixgb_fc_rx_pause: /* 1 */
694 /* RX Flow control is enabled, and TX Flow control is
695 * disabled.
696 */
697 ctrl_reg |= (IXGB_CTRL0_RPE);
698 break;
699 case ixgb_fc_tx_pause: /* 2 */
700 /* TX Flow control is enabled, and RX Flow control is
701 * disabled, by a software over-ride.
702 */
703 ctrl_reg |= (IXGB_CTRL0_TPE);
704 pap_reg = hw->fc.pause_time;
705 break;
706 case ixgb_fc_full: /* 3 */
707 /* Flow control (both RX and TX) is enabled by a software
708 * over-ride.
709 */
710 ctrl_reg |= (IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
711 pap_reg = hw->fc.pause_time;
712 break;
713 default:
714 /* We should never get here. The value should be 0-3. */
715 DEBUGOUT("Flow control param set incorrectly\n");
716 ASSERT(0);
717 break;
718 }
719
720 /* Write the new settings */
721 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
722
723 if (pap_reg != 0) {
724 IXGB_WRITE_REG(hw, PAP, pap_reg);
725 }
726
727 /* Set the flow control receive threshold registers. Normally,
728 * these registers will be set to a default threshold that may be
729 * adjusted later by the driver's runtime code. However, if the
730 * ability to transmit pause frames in not enabled, then these
731 * registers will be set to 0.
732 */
733 if(!(hw->fc.type & ixgb_fc_tx_pause)) {
734 IXGB_WRITE_REG(hw, FCRTL, 0);
735 IXGB_WRITE_REG(hw, FCRTH, 0);
736 } else {
737 /* We need to set up the Receive Threshold high and low water
738 * marks as well as (optionally) enabling the transmission of XON
739 * frames. */
740 if(hw->fc.send_xon) {
741 IXGB_WRITE_REG(hw, FCRTL,
742 (hw->fc.low_water | IXGB_FCRTL_XONE));
743 } else {
744 IXGB_WRITE_REG(hw, FCRTL, hw->fc.low_water);
745 }
746 IXGB_WRITE_REG(hw, FCRTH, hw->fc.high_water);
747 }
748 return (status);
749 }
750
751 /******************************************************************************
752 * Reads a word from a device over the Management Data Interface (MDI) bus.
753 * This interface is used to manage Physical layer devices.
754 *
755 * hw - Struct containing variables accessed by hw code
756 * reg_address - Offset of device register being read.
757 * phy_address - Address of device on MDI.
758 *
759 * Returns: Data word (16 bits) from MDI device.
760 *
761 * The 82597EX has support for several MDI access methods. This routine
762 * uses the new protocol MDI Single Command and Address Operation.
763 * This requires that first an address cycle command is sent, followed by a
764 * read command.
765 *****************************************************************************/
766 static uint16_t
767 ixgb_read_phy_reg(struct ixgb_hw *hw,
768 uint32_t reg_address,
769 uint32_t phy_address,
770 uint32_t device_type)
771 {
772 uint32_t i;
773 uint32_t data;
774 uint32_t command = 0;
775
776 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
777 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
778 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
779
780 /* Setup and write the address cycle command */
781 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
782 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
783 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
784 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
785
786 IXGB_WRITE_REG(hw, MSCA, command);
787
788 /**************************************************************
789 ** Check every 10 usec to see if the address cycle completed
790 ** The COMMAND bit will clear when the operation is complete.
791 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
792 ** from the CPU Write to the Ready bit assertion.
793 **************************************************************/
794
795 for(i = 0; i < 10; i++)
796 {
797 udelay(10);
798
799 command = IXGB_READ_REG(hw, MSCA);
800
801 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
802 break;
803 }
804
805 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
806
807 /* Address cycle complete, setup and write the read command */
808 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
809 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
810 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
811 (IXGB_MSCA_READ | IXGB_MSCA_MDI_COMMAND));
812
813 IXGB_WRITE_REG(hw, MSCA, command);
814
815 /**************************************************************
816 ** Check every 10 usec to see if the read command completed
817 ** The COMMAND bit will clear when the operation is complete.
818 ** The read may take as long as 64 usecs (we'll wait 100 usecs max)
819 ** from the CPU Write to the Ready bit assertion.
820 **************************************************************/
821
822 for(i = 0; i < 10; i++)
823 {
824 udelay(10);
825
826 command = IXGB_READ_REG(hw, MSCA);
827
828 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
829 break;
830 }
831
832 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
833
834 /* Operation is complete, get the data from the MDIO Read/Write Data
835 * register and return.
836 */
837 data = IXGB_READ_REG(hw, MSRWD);
838 data >>= IXGB_MSRWD_READ_DATA_SHIFT;
839 return((uint16_t) data);
840 }
841
842 /******************************************************************************
843 * Writes a word to a device over the Management Data Interface (MDI) bus.
844 * This interface is used to manage Physical layer devices.
845 *
846 * hw - Struct containing variables accessed by hw code
847 * reg_address - Offset of device register being read.
848 * phy_address - Address of device on MDI.
849 * device_type - Also known as the Device ID or DID.
850 * data - 16-bit value to be written
851 *
852 * Returns: void.
853 *
854 * The 82597EX has support for several MDI access methods. This routine
855 * uses the new protocol MDI Single Command and Address Operation.
856 * This requires that first an address cycle command is sent, followed by a
857 * write command.
858 *****************************************************************************/
859 static void
860 ixgb_write_phy_reg(struct ixgb_hw *hw,
861 uint32_t reg_address,
862 uint32_t phy_address,
863 uint32_t device_type,
864 uint16_t data)
865 {
866 uint32_t i;
867 uint32_t command = 0;
868
869 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
870 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
871 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
872
873 /* Put the data in the MDIO Read/Write Data register */
874 IXGB_WRITE_REG(hw, MSRWD, (uint32_t)data);
875
876 /* Setup and write the address cycle command */
877 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
878 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
879 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
880 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
881
882 IXGB_WRITE_REG(hw, MSCA, command);
883
884 /**************************************************************
885 ** Check every 10 usec to see if the address cycle completed
886 ** The COMMAND bit will clear when the operation is complete.
887 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
888 ** from the CPU Write to the Ready bit assertion.
889 **************************************************************/
890
891 for(i = 0; i < 10; i++)
892 {
893 udelay(10);
894
895 command = IXGB_READ_REG(hw, MSCA);
896
897 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
898 break;
899 }
900
901 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
902
903 /* Address cycle complete, setup and write the write command */
904 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
905 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
906 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
907 (IXGB_MSCA_WRITE | IXGB_MSCA_MDI_COMMAND));
908
909 IXGB_WRITE_REG(hw, MSCA, command);
910
911 /**************************************************************
912 ** Check every 10 usec to see if the read command completed
913 ** The COMMAND bit will clear when the operation is complete.
914 ** The write may take as long as 64 usecs (we'll wait 100 usecs max)
915 ** from the CPU Write to the Ready bit assertion.
916 **************************************************************/
917
918 for(i = 0; i < 10; i++)
919 {
920 udelay(10);
921
922 command = IXGB_READ_REG(hw, MSCA);
923
924 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
925 break;
926 }
927
928 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
929
930 /* Operation is complete, return. */
931 }
932
933 /******************************************************************************
934 * Checks to see if the link status of the hardware has changed.
935 *
936 * hw - Struct containing variables accessed by hw code
937 *
938 * Called by any function that needs to check the link status of the adapter.
939 *****************************************************************************/
940 void
941 ixgb_check_for_link(struct ixgb_hw *hw)
942 {
943 uint32_t status_reg;
944 uint32_t xpcss_reg;
945
946 DEBUGFUNC("ixgb_check_for_link");
947
948 xpcss_reg = IXGB_READ_REG(hw, XPCSS);
949 status_reg = IXGB_READ_REG(hw, STATUS);
950
951 if ((xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
952 (status_reg & IXGB_STATUS_LU)) {
953 hw->link_up = TRUE;
954 } else if (!(xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
955 (status_reg & IXGB_STATUS_LU)) {
956 DEBUGOUT("XPCSS Not Aligned while Status:LU is set.\n");
957 hw->link_up = ixgb_link_reset(hw);
958 } else {
959 /*
960 * 82597EX errata. Since the lane deskew problem may prevent
961 * link, reset the link before reporting link down.
962 */
963 hw->link_up = ixgb_link_reset(hw);
964 }
965 /* Anything else for 10 Gig?? */
966 }
967
968 /******************************************************************************
969 * Check for a bad link condition that may have occured.
970 * The indication is that the RFC / LFC registers may be incrementing
971 * continually. A full adapter reset is required to recover.
972 *
973 * hw - Struct containing variables accessed by hw code
974 *
975 * Called by any function that needs to check the link status of the adapter.
976 *****************************************************************************/
977 boolean_t ixgb_check_for_bad_link(struct ixgb_hw *hw)
978 {
979 uint32_t newLFC, newRFC;
980 boolean_t bad_link_returncode = FALSE;
981
982 if (hw->phy_type == ixgb_phy_type_txn17401) {
983 newLFC = IXGB_READ_REG(hw, LFC);
984 newRFC = IXGB_READ_REG(hw, RFC);
985 if ((hw->lastLFC + 250 < newLFC)
986 || (hw->lastRFC + 250 < newRFC)) {
987 DEBUGOUT
988 ("BAD LINK! too many LFC/RFC since last check\n");
989 bad_link_returncode = TRUE;
990 }
991 hw->lastLFC = newLFC;
992 hw->lastRFC = newRFC;
993 }
994
995 return bad_link_returncode;
996 }
997
998 /******************************************************************************
999 * Clears all hardware statistics counters.
1000 *
1001 * hw - Struct containing variables accessed by shared code
1002 *****************************************************************************/
1003 static void
1004 ixgb_clear_hw_cntrs(struct ixgb_hw *hw)
1005 {
1006 volatile uint32_t temp_reg;
1007
1008 DEBUGFUNC("ixgb_clear_hw_cntrs");
1009
1010 /* if we are stopped or resetting exit gracefully */
1011 if(hw->adapter_stopped) {
1012 DEBUGOUT("Exiting because the adapter is stopped!!!\n");
1013 return;
1014 }
1015
1016 temp_reg = IXGB_READ_REG(hw, TPRL);
1017 temp_reg = IXGB_READ_REG(hw, TPRH);
1018 temp_reg = IXGB_READ_REG(hw, GPRCL);
1019 temp_reg = IXGB_READ_REG(hw, GPRCH);
1020 temp_reg = IXGB_READ_REG(hw, BPRCL);
1021 temp_reg = IXGB_READ_REG(hw, BPRCH);
1022 temp_reg = IXGB_READ_REG(hw, MPRCL);
1023 temp_reg = IXGB_READ_REG(hw, MPRCH);
1024 temp_reg = IXGB_READ_REG(hw, UPRCL);
1025 temp_reg = IXGB_READ_REG(hw, UPRCH);
1026 temp_reg = IXGB_READ_REG(hw, VPRCL);
1027 temp_reg = IXGB_READ_REG(hw, VPRCH);
1028 temp_reg = IXGB_READ_REG(hw, JPRCL);
1029 temp_reg = IXGB_READ_REG(hw, JPRCH);
1030 temp_reg = IXGB_READ_REG(hw, GORCL);
1031 temp_reg = IXGB_READ_REG(hw, GORCH);
1032 temp_reg = IXGB_READ_REG(hw, TORL);
1033 temp_reg = IXGB_READ_REG(hw, TORH);
1034 temp_reg = IXGB_READ_REG(hw, RNBC);
1035 temp_reg = IXGB_READ_REG(hw, RUC);
1036 temp_reg = IXGB_READ_REG(hw, ROC);
1037 temp_reg = IXGB_READ_REG(hw, RLEC);
1038 temp_reg = IXGB_READ_REG(hw, CRCERRS);
1039 temp_reg = IXGB_READ_REG(hw, ICBC);
1040 temp_reg = IXGB_READ_REG(hw, ECBC);
1041 temp_reg = IXGB_READ_REG(hw, MPC);
1042 temp_reg = IXGB_READ_REG(hw, TPTL);
1043 temp_reg = IXGB_READ_REG(hw, TPTH);
1044 temp_reg = IXGB_READ_REG(hw, GPTCL);
1045 temp_reg = IXGB_READ_REG(hw, GPTCH);
1046 temp_reg = IXGB_READ_REG(hw, BPTCL);
1047 temp_reg = IXGB_READ_REG(hw, BPTCH);
1048 temp_reg = IXGB_READ_REG(hw, MPTCL);
1049 temp_reg = IXGB_READ_REG(hw, MPTCH);
1050 temp_reg = IXGB_READ_REG(hw, UPTCL);
1051 temp_reg = IXGB_READ_REG(hw, UPTCH);
1052 temp_reg = IXGB_READ_REG(hw, VPTCL);
1053 temp_reg = IXGB_READ_REG(hw, VPTCH);
1054 temp_reg = IXGB_READ_REG(hw, JPTCL);
1055 temp_reg = IXGB_READ_REG(hw, JPTCH);
1056 temp_reg = IXGB_READ_REG(hw, GOTCL);
1057 temp_reg = IXGB_READ_REG(hw, GOTCH);
1058 temp_reg = IXGB_READ_REG(hw, TOTL);
1059 temp_reg = IXGB_READ_REG(hw, TOTH);
1060 temp_reg = IXGB_READ_REG(hw, DC);
1061 temp_reg = IXGB_READ_REG(hw, PLT64C);
1062 temp_reg = IXGB_READ_REG(hw, TSCTC);
1063 temp_reg = IXGB_READ_REG(hw, TSCTFC);
1064 temp_reg = IXGB_READ_REG(hw, IBIC);
1065 temp_reg = IXGB_READ_REG(hw, RFC);
1066 temp_reg = IXGB_READ_REG(hw, LFC);
1067 temp_reg = IXGB_READ_REG(hw, PFRC);
1068 temp_reg = IXGB_READ_REG(hw, PFTC);
1069 temp_reg = IXGB_READ_REG(hw, MCFRC);
1070 temp_reg = IXGB_READ_REG(hw, MCFTC);
1071 temp_reg = IXGB_READ_REG(hw, XONRXC);
1072 temp_reg = IXGB_READ_REG(hw, XONTXC);
1073 temp_reg = IXGB_READ_REG(hw, XOFFRXC);
1074 temp_reg = IXGB_READ_REG(hw, XOFFTXC);
1075 temp_reg = IXGB_READ_REG(hw, RJC);
1076 return;
1077 }
1078
1079 /******************************************************************************
1080 * Turns on the software controllable LED
1081 *
1082 * hw - Struct containing variables accessed by shared code
1083 *****************************************************************************/
1084 void
1085 ixgb_led_on(struct ixgb_hw *hw)
1086 {
1087 uint32_t ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
1088
1089 /* To turn on the LED, clear software-definable pin 0 (SDP0). */
1090 ctrl0_reg &= ~IXGB_CTRL0_SDP0;
1091 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
1092 return;
1093 }
1094
1095 /******************************************************************************
1096 * Turns off the software controllable LED
1097 *
1098 * hw - Struct containing variables accessed by shared code
1099 *****************************************************************************/
1100 void
1101 ixgb_led_off(struct ixgb_hw *hw)
1102 {
1103 uint32_t ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
1104
1105 /* To turn off the LED, set software-definable pin 0 (SDP0). */
1106 ctrl0_reg |= IXGB_CTRL0_SDP0;
1107 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
1108 return;
1109 }
1110
1111 /******************************************************************************
1112 * Gets the current PCI bus type, speed, and width of the hardware
1113 *
1114 * hw - Struct containing variables accessed by shared code
1115 *****************************************************************************/
1116 static void
1117 ixgb_get_bus_info(struct ixgb_hw *hw)
1118 {
1119 uint32_t status_reg;
1120
1121 status_reg = IXGB_READ_REG(hw, STATUS);
1122
1123 hw->bus.type = (status_reg & IXGB_STATUS_PCIX_MODE) ?
1124 ixgb_bus_type_pcix : ixgb_bus_type_pci;
1125
1126 if (hw->bus.type == ixgb_bus_type_pci) {
1127 hw->bus.speed = (status_reg & IXGB_STATUS_PCI_SPD) ?
1128 ixgb_bus_speed_66 : ixgb_bus_speed_33;
1129 } else {
1130 switch (status_reg & IXGB_STATUS_PCIX_SPD_MASK) {
1131 case IXGB_STATUS_PCIX_SPD_66:
1132 hw->bus.speed = ixgb_bus_speed_66;
1133 break;
1134 case IXGB_STATUS_PCIX_SPD_100:
1135 hw->bus.speed = ixgb_bus_speed_100;
1136 break;
1137 case IXGB_STATUS_PCIX_SPD_133:
1138 hw->bus.speed = ixgb_bus_speed_133;
1139 break;
1140 default:
1141 hw->bus.speed = ixgb_bus_speed_reserved;
1142 break;
1143 }
1144 }
1145
1146 hw->bus.width = (status_reg & IXGB_STATUS_BUS64) ?
1147 ixgb_bus_width_64 : ixgb_bus_width_32;
1148
1149 return;
1150 }
1151
1152 /******************************************************************************
1153 * Tests a MAC address to ensure it is a valid Individual Address
1154 *
1155 * mac_addr - pointer to MAC address.
1156 *
1157 *****************************************************************************/
1158 static boolean_t
1159 mac_addr_valid(uint8_t *mac_addr)
1160 {
1161 boolean_t is_valid = TRUE;
1162 DEBUGFUNC("mac_addr_valid");
1163
1164 /* Make sure it is not a multicast address */
1165 if (IS_MULTICAST(mac_addr)) {
1166 DEBUGOUT("MAC address is multicast\n");
1167 is_valid = FALSE;
1168 }
1169 /* Not a broadcast address */
1170 else if (IS_BROADCAST(mac_addr)) {
1171 DEBUGOUT("MAC address is broadcast\n");
1172 is_valid = FALSE;
1173 }
1174 /* Reject the zero address */
1175 else if (mac_addr[0] == 0 &&
1176 mac_addr[1] == 0 &&
1177 mac_addr[2] == 0 &&
1178 mac_addr[3] == 0 &&
1179 mac_addr[4] == 0 &&
1180 mac_addr[5] == 0) {
1181 DEBUGOUT("MAC address is all zeros\n");
1182 is_valid = FALSE;
1183 }
1184 return (is_valid);
1185 }
1186
1187 /******************************************************************************
1188 * Resets the 10GbE link. Waits the settle time and returns the state of
1189 * the link.
1190 *
1191 * hw - Struct containing variables accessed by shared code
1192 *****************************************************************************/
1193 static boolean_t
1194 ixgb_link_reset(struct ixgb_hw *hw)
1195 {
1196 boolean_t link_status = FALSE;
1197 uint8_t wait_retries = MAX_RESET_ITERATIONS;
1198 uint8_t lrst_retries = MAX_RESET_ITERATIONS;
1199
1200 do {
1201 /* Reset the link */
1202 IXGB_WRITE_REG(hw, CTRL0,
1203 IXGB_READ_REG(hw, CTRL0) | IXGB_CTRL0_LRST);
1204
1205 /* Wait for link-up and lane re-alignment */
1206 do {
1207 udelay(IXGB_DELAY_USECS_AFTER_LINK_RESET);
1208 link_status =
1209 ((IXGB_READ_REG(hw, STATUS) & IXGB_STATUS_LU)
1210 && (IXGB_READ_REG(hw, XPCSS) &
1211 IXGB_XPCSS_ALIGN_STATUS)) ? TRUE : FALSE;
1212 } while (!link_status && --wait_retries);
1213
1214 } while (!link_status && --lrst_retries);
1215
1216 return link_status;
1217 }
1218
1219 /******************************************************************************
1220 * Resets the 10GbE optics module.
1221 *
1222 * hw - Struct containing variables accessed by shared code
1223 *****************************************************************************/
1224 static void
1225 ixgb_optics_reset(struct ixgb_hw *hw)
1226 {
1227 if (hw->phy_type == ixgb_phy_type_txn17401) {
1228 uint16_t mdio_reg;
1229
1230 ixgb_write_phy_reg(hw,
1231 MDIO_PMA_PMD_CR1,
1232 IXGB_PHY_ADDRESS,
1233 MDIO_PMA_PMD_DID,
1234 MDIO_PMA_PMD_CR1_RESET);
1235
1236 mdio_reg = ixgb_read_phy_reg( hw,
1237 MDIO_PMA_PMD_CR1,
1238 IXGB_PHY_ADDRESS,
1239 MDIO_PMA_PMD_DID);
1240 }
1241
1242 return;
1243 }
1244
1245 /******************************************************************************
1246 * Resets the 10GbE optics module for Sun variant NIC.
1247 *
1248 * hw - Struct containing variables accessed by shared code
1249 *****************************************************************************/
1250
1251 #define IXGB_BCM8704_USER_PMD_TX_CTRL_REG 0xC803
1252 #define IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL 0x0164
1253 #define IXGB_BCM8704_USER_CTRL_REG 0xC800
1254 #define IXGB_BCM8704_USER_CTRL_REG_VAL 0x7FBF
1255 #define IXGB_BCM8704_USER_DEV3_ADDR 0x0003
1256 #define IXGB_SUN_PHY_ADDRESS 0x0000
1257 #define IXGB_SUN_PHY_RESET_DELAY 305
1258
1259 static void
1260 ixgb_optics_reset_bcm(struct ixgb_hw *hw)
1261 {
1262 u32 ctrl = IXGB_READ_REG(hw, CTRL0);
1263 ctrl &= ~IXGB_CTRL0_SDP2;
1264 ctrl |= IXGB_CTRL0_SDP3;
1265 IXGB_WRITE_REG(hw, CTRL0, ctrl);
1266
1267 /* SerDes needs extra delay */
1268 msleep(IXGB_SUN_PHY_RESET_DELAY);
1269
1270 /* Broadcom 7408L configuration */
1271 /* Reference clock config */
1272 ixgb_write_phy_reg(hw,
1273 IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1274 IXGB_SUN_PHY_ADDRESS,
1275 IXGB_BCM8704_USER_DEV3_ADDR,
1276 IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL);
1277 /* we must read the registers twice */
1278 ixgb_read_phy_reg(hw,
1279 IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1280 IXGB_SUN_PHY_ADDRESS,
1281 IXGB_BCM8704_USER_DEV3_ADDR);
1282 ixgb_read_phy_reg(hw,
1283 IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1284 IXGB_SUN_PHY_ADDRESS,
1285 IXGB_BCM8704_USER_DEV3_ADDR);
1286
1287 ixgb_write_phy_reg(hw,
1288 IXGB_BCM8704_USER_CTRL_REG,
1289 IXGB_SUN_PHY_ADDRESS,
1290 IXGB_BCM8704_USER_DEV3_ADDR,
1291 IXGB_BCM8704_USER_CTRL_REG_VAL);
1292 ixgb_read_phy_reg(hw,
1293 IXGB_BCM8704_USER_CTRL_REG,
1294 IXGB_SUN_PHY_ADDRESS,
1295 IXGB_BCM8704_USER_DEV3_ADDR);
1296 ixgb_read_phy_reg(hw,
1297 IXGB_BCM8704_USER_CTRL_REG,
1298 IXGB_SUN_PHY_ADDRESS,
1299 IXGB_BCM8704_USER_DEV3_ADDR);
1300
1301 /* SerDes needs extra delay */
1302 msleep(IXGB_SUN_PHY_RESET_DELAY);
1303
1304 return;
1305 }
Linux kernel - Deliverables
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