drivers/net/ixgbe/ixgbe.h

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2007 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 #ifndef _IXGBE_H_
  30 #define _IXGBE_H_
  31
  32 #include <linux/types.h>
  33 #include <linux/pci.h>
  34 #include <linux/netdevice.h>
  35
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_common.h"
  38
  39 #ifdef CONFIG_DCA
  40 #include <linux/dca.h>
  41 #endif
  42
  43 #define IXGBE_ERR(args...) printk(KERN_ERR "ixgbe: " args)
  44
  45 #define PFX "ixgbe: "
  46 #define DPRINTK(nlevel, klevel, fmt, args...) \
  47         ((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
  48         printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
  49                 __FUNCTION__ , ## args)))
  50
  51 /* TX/RX descriptor defines */
  52 #define IXGBE_DEFAULT_TXD                  1024
  53 #define IXGBE_MAX_TXD                      4096
  54 #define IXGBE_MIN_TXD                        64
  55
  56 #define IXGBE_DEFAULT_RXD                  1024
  57 #define IXGBE_MAX_RXD                      4096
  58 #define IXGBE_MIN_RXD                        64
  59
  60 #define IXGBE_DEFAULT_RXQ                          1
  61 #define IXGBE_MAX_RXQ                              1
  62 #define IXGBE_MIN_RXQ                              1
  63
  64 #define IXGBE_DEFAULT_ITR_RX_USECS          125  /*   8k irqs/sec */
  65 #define IXGBE_DEFAULT_ITR_TX_USECS          250  /*   4k irqs/sec */
  66 #define IXGBE_MIN_ITR_USECS                 100  /* 500k irqs/sec */
  67 #define IXGBE_MAX_ITR_USECS               10000  /* 100  irqs/sec */
  68
  69 /* flow control */
  70 #define IXGBE_DEFAULT_FCRTL             0x10000
  71 #define IXGBE_MIN_FCRTL                       0
  72 #define IXGBE_MAX_FCRTL                 0x7FF80
  73 #define IXGBE_DEFAULT_FCRTH             0x20000
  74 #define IXGBE_MIN_FCRTH                       0
  75 #define IXGBE_MAX_FCRTH                 0x7FFF0
  76 #define IXGBE_DEFAULT_FCPAUSE            0x6800  /* may be too long */
  77 #define IXGBE_MIN_FCPAUSE                     0
  78 #define IXGBE_MAX_FCPAUSE                0xFFFF
  79
  80 /* Supported Rx Buffer Sizes */
  81 #define IXGBE_RXBUFFER_64    64     /* Used for packet split */
  82 #define IXGBE_RXBUFFER_128   128    /* Used for packet split */
  83 #define IXGBE_RXBUFFER_256   256    /* Used for packet split */
  84 #define IXGBE_RXBUFFER_2048  2048
  85
  86 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
  87
  88 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
  89
  90 /* How many Tx Descriptors do we need to call netif_wake_queue? */
  91 #define IXGBE_TX_QUEUE_WAKE 16
  92
  93 /* How many Rx Buffers do we bundle into one write to the hardware ? */
  94 #define IXGBE_RX_BUFFER_WRITE   16      /* Must be power of 2 */
  95
  96 #define IXGBE_TX_FLAGS_CSUM             (u32)(1)
  97 #define IXGBE_TX_FLAGS_VLAN             (u32)(1 << 1)
  98 #define IXGBE_TX_FLAGS_TSO              (u32)(1 << 2)
  99 #define IXGBE_TX_FLAGS_IPV4             (u32)(1 << 3)
 100 #define IXGBE_TX_FLAGS_VLAN_MASK        0xffff0000
 101 #define IXGBE_TX_FLAGS_VLAN_SHIFT       16
 102
 103 /* wrapper around a pointer to a socket buffer,
 104  * so a DMA handle can be stored along with the buffer */
 105 struct ixgbe_tx_buffer {
 106         struct sk_buff *skb;
 107         dma_addr_t dma;
 108         unsigned long time_stamp;
 109         u16 length;
 110         u16 next_to_watch;
 111 };
 112
 113 struct ixgbe_rx_buffer {
 114         struct sk_buff *skb;
 115         dma_addr_t dma;
 116         struct page *page;
 117         dma_addr_t page_dma;
 118 };
 119
 120 struct ixgbe_queue_stats {
 121         u64 packets;
 122         u64 bytes;
 123 };
 124
 125 struct ixgbe_ring {
 126         void *desc;                     /* descriptor ring memory */
 127         dma_addr_t dma;                 /* phys. address of descriptor ring */
 128         unsigned int size;              /* length in bytes */
 129         unsigned int count;             /* amount of descriptors */
 130         unsigned int next_to_use;
 131         unsigned int next_to_clean;
 132
 133         int queue_index; /* needed for multiqueue queue management */
 134         union {
 135                 struct ixgbe_tx_buffer *tx_buffer_info;
 136                 struct ixgbe_rx_buffer *rx_buffer_info;
 137         };
 138
 139         u16 head;
 140         u16 tail;
 141
 142         unsigned int total_bytes;
 143         unsigned int total_packets;
 144
 145         u16 reg_idx; /* holds the special value that gets the hardware register
 146                       * offset associated with this ring, which is different
 147                       * for DCE and RSS modes */
 148
 149 #ifdef CONFIG_DCA
 150         /* cpu for tx queue */
 151         int cpu;
 152 #endif
 153         struct ixgbe_queue_stats stats;
 154         u8 v_idx; /* maps directly to the index for this ring in the hardware
 155                    * vector array, can also be used for finding the bit in EICR
 156                    * and friends that represents the vector for this ring */
 157
 158         u32 eims_value;
 159         u16 itr_register;
 160
 161         char name[IFNAMSIZ + 5];
 162         u16 work_limit;                /* max work per interrupt */
 163 };
 164
 165 #define RING_F_VMDQ 1
 166 #define RING_F_RSS  2
 167 #define IXGBE_MAX_RSS_INDICES  16
 168 #define IXGBE_MAX_VMDQ_INDICES 16
 169 struct ixgbe_ring_feature {
 170         int indices;
 171         int mask;
 172 };
 173
 174 #define MAX_RX_QUEUES 64
 175 #define MAX_TX_QUEUES 32
 176
 177 /* MAX_MSIX_Q_VECTORS of these are allocated,
 178  * but we only use one per queue-specific vector.
 179  */
 180 struct ixgbe_q_vector {
 181         struct ixgbe_adapter *adapter;
 182         struct napi_struct napi;
 183         DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
 184         DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
 185         u8 rxr_count;     /* Rx ring count assigned to this vector */
 186         u8 txr_count;     /* Tx ring count assigned to this vector */
 187         u8 tx_eitr;
 188         u8 rx_eitr;
 189         u32 eitr;
 190 };
 191
 192 /* Helper macros to switch between ints/sec and what the register uses.
 193  * And yes, it's the same math going both ways.
 194  */
 195 #define EITR_INTS_PER_SEC_TO_REG(_eitr) \
 196         ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 0)
 197 #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
 198
 199 #define IXGBE_DESC_UNUSED(R) \
 200         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 201         (R)->next_to_clean - (R)->next_to_use - 1)
 202
 203 #define IXGBE_RX_DESC_ADV(R, i)     \
 204         (&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
 205 #define IXGBE_TX_DESC_ADV(R, i)     \
 206         (&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
 207 #define IXGBE_TX_CTXTDESC_ADV(R, i)         \
 208         (&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))
 209
 210 #define IXGBE_MAX_JUMBO_FRAME_SIZE        16128
 211
 212 #define OTHER_VECTOR 1
 213 #define NON_Q_VECTORS (OTHER_VECTOR)
 214
 215 #define MAX_MSIX_Q_VECTORS 16
 216 #define MIN_MSIX_Q_VECTORS 2
 217 #define MAX_MSIX_COUNT (MAX_MSIX_Q_VECTORS + NON_Q_VECTORS)
 218 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
 219
 220 /* board specific private data structure */
 221 struct ixgbe_adapter {
 222         struct timer_list watchdog_timer;
 223         struct vlan_group *vlgrp;
 224         u16 bd_number;
 225         u16 rx_buf_len;
 226         struct work_struct reset_task;
 227         struct ixgbe_q_vector q_vector[MAX_MSIX_Q_VECTORS];
 228         char name[MAX_MSIX_COUNT][IFNAMSIZ + 5];
 229
 230         /* Interrupt Throttle Rate */
 231         u32 itr_setting;
 232         u16 eitr_low;
 233         u16 eitr_high;
 234
 235         /* TX */
 236         struct ixgbe_ring *tx_ring;     /* One per active queue */
 237         u64 restart_queue;
 238         u64 lsc_int;
 239         u64 hw_tso_ctxt;
 240         u64 hw_tso6_ctxt;
 241         u32 tx_timeout_count;
 242         bool detect_tx_hung;
 243
 244         /* RX */
 245         struct ixgbe_ring *rx_ring;     /* One per active queue */
 246         u64 hw_csum_tx_good;
 247         u64 hw_csum_rx_error;
 248         u64 hw_csum_rx_good;
 249         u64 non_eop_descs;
 250         int num_tx_queues;
 251         int num_rx_queues;
 252         int num_msix_vectors;
 253         struct ixgbe_ring_feature ring_feature[3];
 254         struct msix_entry *msix_entries;
 255
 256         u64 rx_hdr_split;
 257         u32 alloc_rx_page_failed;
 258         u32 alloc_rx_buff_failed;
 259
 260         /* Some features need tri-state capability,
 261          * thus the additional *_CAPABLE flags.
 262          */
 263         u32 flags;
 264 #define IXGBE_FLAG_RX_CSUM_ENABLED              (u32)(1 << 0)
 265 #define IXGBE_FLAG_MSI_ENABLED                  (u32)(1 << 1)
 266 #define IXGBE_FLAG_MSIX_ENABLED                 (u32)(1 << 2)
 267 #define IXGBE_FLAG_RX_PS_ENABLED                (u32)(1 << 3)
 268 #define IXGBE_FLAG_IN_NETPOLL                   (u32)(1 << 4)
 269 #define IXGBE_FLAG_IMIR_ENABLED                 (u32)(1 << 5)
 270 #define IXGBE_FLAG_RSS_ENABLED                  (u32)(1 << 6)
 271 #define IXGBE_FLAG_VMDQ_ENABLED                 (u32)(1 << 7)
 272 #define IXGBE_FLAG_DCA_ENABLED                  (u32)(1 << 8)
 273
 274         /* OS defined structs */
 275         struct net_device *netdev;
 276         struct pci_dev *pdev;
 277         struct net_device_stats net_stats;
 278
 279         /* structs defined in ixgbe_hw.h */
 280         struct ixgbe_hw hw;
 281         u16 msg_enable;
 282         struct ixgbe_hw_stats stats;
 283
 284         /* Interrupt Throttle Rate */
 285         u32 rx_eitr;
 286         u32 tx_eitr;
 287
 288         unsigned long state;
 289         u64 tx_busy;
 290 };
 291
 292 enum ixbge_state_t {
 293         __IXGBE_TESTING,
 294         __IXGBE_RESETTING,
 295         __IXGBE_DOWN
 296 };
 297
 298 enum ixgbe_boards {
 299         board_82598,
 300 };
 301
 302 extern struct ixgbe_info ixgbe_82598_info;
 303
 304 extern char ixgbe_driver_name[];
 305 extern const char ixgbe_driver_version[];
 306
 307 extern int ixgbe_up(struct ixgbe_adapter *adapter);
 308 extern void ixgbe_down(struct ixgbe_adapter *adapter);
 309 extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
 310 extern void ixgbe_reset(struct ixgbe_adapter *adapter);
 311 extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
 312 extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
 313 extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
 314                                     struct ixgbe_ring *rxdr);
 315 extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
 316                                     struct ixgbe_ring *txdr);
 317
 318 #endif /* _IXGBE_H_ */