drivers/net/ixgbe/ixgbe.h

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #ifndef _IXGBE_H_
  29 #define _IXGBE_H_
  30
  31 #include <linux/types.h>
  32 #include <linux/pci.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/inet_lro.h>
  35
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_common.h"
  38
  39 #ifdef CONFIG_IXGBE_DCA
  40 #include <linux/dca.h>
  41 #endif
  42
  43 #define PFX "ixgbe: "
  44 #define DPRINTK(nlevel, klevel, fmt, args...) \
  45         ((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
  46         printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
  47                 __func__ , ## args)))
  48
  49 /* TX/RX descriptor defines */
  50 #define IXGBE_DEFAULT_TXD                  1024
  51 #define IXGBE_MAX_TXD                      4096
  52 #define IXGBE_MIN_TXD                        64
  53
  54 #define IXGBE_DEFAULT_RXD                  1024
  55 #define IXGBE_MAX_RXD                      4096
  56 #define IXGBE_MIN_RXD                        64
  57
  58 /* flow control */
  59 #define IXGBE_DEFAULT_FCRTL             0x10000
  60 #define IXGBE_MIN_FCRTL                    0x40
  61 #define IXGBE_MAX_FCRTL                 0x7FF80
  62 #define IXGBE_DEFAULT_FCRTH             0x20000
  63 #define IXGBE_MIN_FCRTH                   0x600
  64 #define IXGBE_MAX_FCRTH                 0x7FFF0
  65 #define IXGBE_DEFAULT_FCPAUSE            0xFFFF
  66 #define IXGBE_MIN_FCPAUSE                     0
  67 #define IXGBE_MAX_FCPAUSE                0xFFFF
  68
  69 /* Supported Rx Buffer Sizes */
  70 #define IXGBE_RXBUFFER_64    64     /* Used for packet split */
  71 #define IXGBE_RXBUFFER_128   128    /* Used for packet split */
  72 #define IXGBE_RXBUFFER_256   256    /* Used for packet split */
  73 #define IXGBE_RXBUFFER_2048  2048
  74
  75 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
  76
  77 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
  78
  79 /* How many Rx Buffers do we bundle into one write to the hardware ? */
  80 #define IXGBE_RX_BUFFER_WRITE   16      /* Must be power of 2 */
  81
  82 #define IXGBE_TX_FLAGS_CSUM             (u32)(1)
  83 #define IXGBE_TX_FLAGS_VLAN             (u32)(1 << 1)
  84 #define IXGBE_TX_FLAGS_TSO              (u32)(1 << 2)
  85 #define IXGBE_TX_FLAGS_IPV4             (u32)(1 << 3)
  86 #define IXGBE_TX_FLAGS_VLAN_MASK        0xffff0000
  87 #define IXGBE_TX_FLAGS_VLAN_SHIFT       16
  88
  89 #define IXGBE_MAX_LRO_DESCRIPTORS       8
  90 #define IXGBE_MAX_LRO_AGGREGATE         32
  91
  92 /* wrapper around a pointer to a socket buffer,
  93  * so a DMA handle can be stored along with the buffer */
  94 struct ixgbe_tx_buffer {
  95         struct sk_buff *skb;
  96         dma_addr_t dma;
  97         unsigned long time_stamp;
  98         u16 length;
  99         u16 next_to_watch;
 100 };
 101
 102 struct ixgbe_rx_buffer {
 103         struct sk_buff *skb;
 104         dma_addr_t dma;
 105         struct page *page;
 106         dma_addr_t page_dma;
 107         unsigned int page_offset;
 108 };
 109
 110 struct ixgbe_queue_stats {
 111         u64 packets;
 112         u64 bytes;
 113 };
 114
 115 struct ixgbe_ring {
 116         void *desc;                     /* descriptor ring memory */
 117         dma_addr_t dma;                 /* phys. address of descriptor ring */
 118         unsigned int size;              /* length in bytes */
 119         unsigned int count;             /* amount of descriptors */
 120         unsigned int next_to_use;
 121         unsigned int next_to_clean;
 122
 123         int queue_index; /* needed for multiqueue queue management */
 124         union {
 125                 struct ixgbe_tx_buffer *tx_buffer_info;
 126                 struct ixgbe_rx_buffer *rx_buffer_info;
 127         };
 128
 129         u16 head;
 130         u16 tail;
 131
 132         unsigned int total_bytes;
 133         unsigned int total_packets;
 134
 135         u16 reg_idx; /* holds the special value that gets the hardware register
 136                       * offset associated with this ring, which is different
 137                       * for DCE and RSS modes */
 138
 139 #ifdef CONFIG_IXGBE_DCA
 140         /* cpu for tx queue */
 141         int cpu;
 142 #endif
 143         struct net_lro_mgr lro_mgr;
 144         bool lro_used;
 145         struct ixgbe_queue_stats stats;
 146         u16 v_idx; /* maps directly to the index for this ring in the hardware
 147                    * vector array, can also be used for finding the bit in EICR
 148                    * and friends that represents the vector for this ring */
 149
 150
 151         u16 work_limit;                /* max work per interrupt */
 152         u16 rx_buf_len;
 153 };
 154
 155 #define RING_F_VMDQ 1
 156 #define RING_F_RSS  2
 157 #define IXGBE_MAX_RSS_INDICES  16
 158 #define IXGBE_MAX_VMDQ_INDICES 16
 159 struct ixgbe_ring_feature {
 160         int indices;
 161         int mask;
 162 };
 163
 164 #define MAX_RX_QUEUES 64
 165 #define MAX_TX_QUEUES 32
 166
 167 /* MAX_MSIX_Q_VECTORS of these are allocated,
 168  * but we only use one per queue-specific vector.
 169  */
 170 struct ixgbe_q_vector {
 171         struct ixgbe_adapter *adapter;
 172         struct napi_struct napi;
 173         DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
 174         DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
 175         u8 rxr_count;     /* Rx ring count assigned to this vector */
 176         u8 txr_count;     /* Tx ring count assigned to this vector */
 177         u8 tx_itr;
 178         u8 rx_itr;
 179         u32 eitr;
 180 };
 181
 182 /* Helper macros to switch between ints/sec and what the register uses.
 183  * And yes, it's the same math going both ways.
 184  */
 185 #define EITR_INTS_PER_SEC_TO_REG(_eitr) \
 186         ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 0)
 187 #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
 188
 189 #define IXGBE_DESC_UNUSED(R) \
 190         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 191         (R)->next_to_clean - (R)->next_to_use - 1)
 192
 193 #define IXGBE_RX_DESC_ADV(R, i)     \
 194         (&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
 195 #define IXGBE_TX_DESC_ADV(R, i)     \
 196         (&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
 197 #define IXGBE_TX_CTXTDESC_ADV(R, i)         \
 198         (&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))
 199
 200 #define IXGBE_MAX_JUMBO_FRAME_SIZE        16128
 201
 202 #define OTHER_VECTOR 1
 203 #define NON_Q_VECTORS (OTHER_VECTOR)
 204
 205 #define MAX_MSIX_Q_VECTORS 16
 206 #define MIN_MSIX_Q_VECTORS 2
 207 #define MAX_MSIX_COUNT (MAX_MSIX_Q_VECTORS + NON_Q_VECTORS)
 208 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
 209
 210 /* board specific private data structure */
 211 struct ixgbe_adapter {
 212         struct timer_list watchdog_timer;
 213         struct vlan_group *vlgrp;
 214         u16 bd_number;
 215         struct work_struct reset_task;
 216         struct ixgbe_q_vector q_vector[MAX_MSIX_Q_VECTORS];
 217         char name[MAX_MSIX_COUNT][IFNAMSIZ + 5];
 218
 219         /* Interrupt Throttle Rate */
 220         u32 itr_setting;
 221         u16 eitr_low;
 222         u16 eitr_high;
 223
 224         /* TX */
 225         struct ixgbe_ring *tx_ring;     /* One per active queue */
 226         int num_tx_queues;
 227         u64 restart_queue;
 228         u64 hw_csum_tx_good;
 229         u64 lsc_int;
 230         u64 hw_tso_ctxt;
 231         u64 hw_tso6_ctxt;
 232         u32 tx_timeout_count;
 233         bool detect_tx_hung;
 234
 235         /* RX */
 236         struct ixgbe_ring *rx_ring;     /* One per active queue */
 237         int num_rx_queues;
 238         u64 hw_csum_rx_error;
 239         u64 hw_csum_rx_good;
 240         u64 non_eop_descs;
 241         int num_msix_vectors;
 242         struct ixgbe_ring_feature ring_feature[3];
 243         struct msix_entry *msix_entries;
 244
 245         u64 rx_hdr_split;
 246         u32 alloc_rx_page_failed;
 247         u32 alloc_rx_buff_failed;
 248
 249         /* Some features need tri-state capability,
 250          * thus the additional *_CAPABLE flags.
 251          */
 252         u32 flags;
 253 #define IXGBE_FLAG_RX_CSUM_ENABLED              (u32)(1)
 254 #define IXGBE_FLAG_MSI_CAPABLE                  (u32)(1 << 1)
 255 #define IXGBE_FLAG_MSI_ENABLED                  (u32)(1 << 2)
 256 #define IXGBE_FLAG_MSIX_CAPABLE                 (u32)(1 << 3)
 257 #define IXGBE_FLAG_MSIX_ENABLED                 (u32)(1 << 4)
 258 #define IXGBE_FLAG_RX_1BUF_CAPABLE              (u32)(1 << 6)
 259 #define IXGBE_FLAG_RX_PS_CAPABLE                (u32)(1 << 7)
 260 #define IXGBE_FLAG_RX_PS_ENABLED                (u32)(1 << 8)
 261 #define IXGBE_FLAG_IN_NETPOLL                   (u32)(1 << 9)
 262 #define IXGBE_FLAG_DCA_ENABLED                  (u32)(1 << 10)
 263 #define IXGBE_FLAG_DCA_CAPABLE                  (u32)(1 << 11)
 264 #define IXGBE_FLAG_IMIR_ENABLED                 (u32)(1 << 12)
 265 #define IXGBE_FLAG_MQ_CAPABLE                   (u32)(1 << 13)
 266 #define IXGBE_FLAG_RSS_ENABLED                  (u32)(1 << 16)
 267 #define IXGBE_FLAG_RSS_CAPABLE                  (u32)(1 << 17)
 268 #define IXGBE_FLAG_VMDQ_CAPABLE                 (u32)(1 << 18)
 269 #define IXGBE_FLAG_VMDQ_ENABLED                 (u32)(1 << 19)
 270 #define IXGBE_FLAG_NEED_LINK_UPDATE             (u32)(1 << 22)
 271 #define IXGBE_FLAG_IN_WATCHDOG_TASK             (u32)(1 << 23)
 272
 273 /* default to trying for four seconds */
 274 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
 275
 276         /* OS defined structs */
 277         struct net_device *netdev;
 278         struct pci_dev *pdev;
 279         struct net_device_stats net_stats;
 280
 281         /* structs defined in ixgbe_hw.h */
 282         struct ixgbe_hw hw;
 283         u16 msg_enable;
 284         struct ixgbe_hw_stats stats;
 285
 286         /* Interrupt Throttle Rate */
 287         u32 eitr_param;
 288
 289         unsigned long state;
 290         u64 tx_busy;
 291         u64 lro_aggregated;
 292         u64 lro_flushed;
 293         u64 lro_no_desc;
 294         unsigned int tx_ring_count;
 295         unsigned int rx_ring_count;
 296
 297         u32 link_speed;
 298         bool link_up;
 299         unsigned long link_check_timeout;
 300
 301         struct work_struct watchdog_task;
 302 };
 303
 304 enum ixbge_state_t {
 305         __IXGBE_TESTING,
 306         __IXGBE_RESETTING,
 307         __IXGBE_DOWN
 308 };
 309
 310 enum ixgbe_boards {
 311         board_82598,
 312 };
 313
 314 extern struct ixgbe_info ixgbe_82598_info;
 315
 316 extern char ixgbe_driver_name[];
 317 extern const char ixgbe_driver_version[];
 318
 319 extern int ixgbe_up(struct ixgbe_adapter *adapter);
 320 extern void ixgbe_down(struct ixgbe_adapter *adapter);
 321 extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
 322 extern void ixgbe_reset(struct ixgbe_adapter *adapter);
 323 extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
 324 extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
 325 extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
 326 extern void ixgbe_free_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
 327 extern void ixgbe_free_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
 328 extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
 329
 330 #endif /* _IXGBE_H_ */