drivers/net/ixgbe/ixgbe.h

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #ifndef _IXGBE_H_
  29 #define _IXGBE_H_
  30
  31 #include <linux/types.h>
  32 #include <linux/pci.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/aer.h>
  35
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_common.h"
  38 #include "ixgbe_dcb.h"
  39 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
  40 #define IXGBE_FCOE
  41 #include "ixgbe_fcoe.h"
  42 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
  43 #ifdef CONFIG_IXGBE_DCA
  44 #include <linux/dca.h>
  45 #endif
  46
  47 #define PFX "ixgbe: "
  48 #define DPRINTK(nlevel, klevel, fmt, args...) \
  49         ((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
  50         printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
  51                 __func__ , ## args)))
  52
  53 /* TX/RX descriptor defines */
  54 #define IXGBE_DEFAULT_TXD                   512
  55 #define IXGBE_MAX_TXD                      4096
  56 #define IXGBE_MIN_TXD                        64
  57
  58 #define IXGBE_DEFAULT_RXD                   512
  59 #define IXGBE_MAX_RXD                      4096
  60 #define IXGBE_MIN_RXD                        64
  61
  62 /* flow control */
  63 #define IXGBE_DEFAULT_FCRTL             0x10000
  64 #define IXGBE_MIN_FCRTL                    0x40
  65 #define IXGBE_MAX_FCRTL                 0x7FF80
  66 #define IXGBE_DEFAULT_FCRTH             0x20000
  67 #define IXGBE_MIN_FCRTH                   0x600
  68 #define IXGBE_MAX_FCRTH                 0x7FFF0
  69 #define IXGBE_DEFAULT_FCPAUSE            0xFFFF
  70 #define IXGBE_MIN_FCPAUSE                     0
  71 #define IXGBE_MAX_FCPAUSE                0xFFFF
  72
  73 /* Supported Rx Buffer Sizes */
  74 #define IXGBE_RXBUFFER_64    64     /* Used for packet split */
  75 #define IXGBE_RXBUFFER_128   128    /* Used for packet split */
  76 #define IXGBE_RXBUFFER_256   256    /* Used for packet split */
  77 #define IXGBE_RXBUFFER_2048  2048
  78 #define IXGBE_RXBUFFER_4096  4096
  79 #define IXGBE_RXBUFFER_8192  8192
  80 #define IXGBE_MAX_RXBUFFER   16384  /* largest size for a single descriptor */
  81
  82 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
  83
  84 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
  85
  86 /* How many Rx Buffers do we bundle into one write to the hardware ? */
  87 #define IXGBE_RX_BUFFER_WRITE   16      /* Must be power of 2 */
  88
  89 #define IXGBE_TX_FLAGS_CSUM             (u32)(1)
  90 #define IXGBE_TX_FLAGS_VLAN             (u32)(1 << 1)
  91 #define IXGBE_TX_FLAGS_TSO              (u32)(1 << 2)
  92 #define IXGBE_TX_FLAGS_IPV4             (u32)(1 << 3)
  93 #define IXGBE_TX_FLAGS_FCOE             (u32)(1 << 4)
  94 #define IXGBE_TX_FLAGS_FSO              (u32)(1 << 5)
  95 #define IXGBE_TX_FLAGS_VLAN_MASK        0xffff0000
  96 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK   0x0000e000
  97 #define IXGBE_TX_FLAGS_VLAN_SHIFT       16
  98
  99 #define IXGBE_MAX_RSC_INT_RATE          162760
 100
 101 /* wrapper around a pointer to a socket buffer,
 102  * so a DMA handle can be stored along with the buffer */
 103 struct ixgbe_tx_buffer {
 104         struct sk_buff *skb;
 105         dma_addr_t dma;
 106         unsigned long time_stamp;
 107         u16 length;
 108         u16 next_to_watch;
 109         u16 mapped_as_page;
 110 };
 111
 112 struct ixgbe_rx_buffer {
 113         struct sk_buff *skb;
 114         dma_addr_t dma;
 115         struct page *page;
 116         dma_addr_t page_dma;
 117         unsigned int page_offset;
 118 };
 119
 120 struct ixgbe_queue_stats {
 121         u64 packets;
 122         u64 bytes;
 123 };
 124
 125 struct ixgbe_ring {
 126         void *desc;                     /* descriptor ring memory */
 127         union {
 128                 struct ixgbe_tx_buffer *tx_buffer_info;
 129                 struct ixgbe_rx_buffer *rx_buffer_info;
 130         };
 131         u8 atr_sample_rate;
 132         u8 atr_count;
 133         u16 count;                      /* amount of descriptors */
 134         u16 rx_buf_len;
 135         u16 next_to_use;
 136         u16 next_to_clean;
 137
 138         u8 queue_index; /* needed for multiqueue queue management */
 139
 140 #define IXGBE_RING_RX_PS_ENABLED                (u8)(1)
 141         u8 flags;                       /* per ring feature flags */
 142         u16 head;
 143         u16 tail;
 144
 145         unsigned int total_bytes;
 146         unsigned int total_packets;
 147
 148 #ifdef CONFIG_IXGBE_DCA
 149         /* cpu for tx queue */
 150         int cpu;
 151 #endif
 152
 153         u16 work_limit;                 /* max work per interrupt */
 154         u16 reg_idx;                    /* holds the special value that gets
 155                                          * the hardware register offset
 156                                          * associated with this ring, which is
 157                                          * different for DCB and RSS modes
 158                                          */
 159
 160         struct ixgbe_queue_stats stats;
 161         unsigned long reinit_state;
 162         u64 rsc_count;                  /* stat for coalesced packets */
 163         u64 rsc_flush;                  /* stats for flushed packets */
 164         u32 restart_queue;              /* track tx queue restarts */
 165         u32 non_eop_descs;              /* track hardware descriptor chaining */
 166
 167         unsigned int size;              /* length in bytes */
 168         dma_addr_t dma;                 /* phys. address of descriptor ring */
 169 } ____cacheline_internodealigned_in_smp;
 170
 171 enum ixgbe_ring_f_enum {
 172         RING_F_NONE = 0,
 173         RING_F_DCB,
 174         RING_F_VMDQ,
 175         RING_F_RSS,
 176         RING_F_FDIR,
 177 #ifdef IXGBE_FCOE
 178         RING_F_FCOE,
 179 #endif /* IXGBE_FCOE */
 180
 181         RING_F_ARRAY_SIZE      /* must be last in enum set */
 182 };
 183
 184 #define IXGBE_MAX_DCB_INDICES   8
 185 #define IXGBE_MAX_RSS_INDICES  16
 186 #define IXGBE_MAX_VMDQ_INDICES 16
 187 #define IXGBE_MAX_FDIR_INDICES 64
 188 #ifdef IXGBE_FCOE
 189 #define IXGBE_MAX_FCOE_INDICES  8
 190 #endif /* IXGBE_FCOE */
 191 struct ixgbe_ring_feature {
 192         int indices;
 193         int mask;
 194 } ____cacheline_internodealigned_in_smp;
 195
 196 #define MAX_RX_QUEUES 128
 197 #define MAX_TX_QUEUES 128
 198
 199 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
 200                               ? 8 : 1)
 201 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
 202
 203 /* MAX_MSIX_Q_VECTORS of these are allocated,
 204  * but we only use one per queue-specific vector.
 205  */
 206 struct ixgbe_q_vector {
 207         struct ixgbe_adapter *adapter;
 208         unsigned int v_idx; /* index of q_vector within array, also used for
 209                              * finding the bit in EICR and friends that
 210                              * represents the vector for this ring */
 211         struct napi_struct napi;
 212         DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
 213         DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
 214         u8 rxr_count;     /* Rx ring count assigned to this vector */
 215         u8 txr_count;     /* Tx ring count assigned to this vector */
 216         u8 tx_itr;
 217         u8 rx_itr;
 218         u32 eitr;
 219 };
 220
 221 /* Helper macros to switch between ints/sec and what the register uses.
 222  * And yes, it's the same math going both ways.  The lowest value
 223  * supported by all of the ixgbe hardware is 8.
 224  */
 225 #define EITR_INTS_PER_SEC_TO_REG(_eitr) \
 226         ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
 227 #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
 228
 229 #define IXGBE_DESC_UNUSED(R) \
 230         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 231         (R)->next_to_clean - (R)->next_to_use - 1)
 232
 233 #define IXGBE_RX_DESC_ADV(R, i)     \
 234         (&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
 235 #define IXGBE_TX_DESC_ADV(R, i)     \
 236         (&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
 237 #define IXGBE_TX_CTXTDESC_ADV(R, i)         \
 238         (&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))
 239
 240 #define IXGBE_MAX_JUMBO_FRAME_SIZE        16128
 241 #ifdef IXGBE_FCOE
 242 /* Use 3K as the baby jumbo frame size for FCoE */
 243 #define IXGBE_FCOE_JUMBO_FRAME_SIZE       3072
 244 #endif /* IXGBE_FCOE */
 245
 246 #define OTHER_VECTOR 1
 247 #define NON_Q_VECTORS (OTHER_VECTOR)
 248
 249 #define MAX_MSIX_VECTORS_82599 64
 250 #define MAX_MSIX_Q_VECTORS_82599 64
 251 #define MAX_MSIX_VECTORS_82598 18
 252 #define MAX_MSIX_Q_VECTORS_82598 16
 253
 254 #define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
 255 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
 256
 257 #define MIN_MSIX_Q_VECTORS 2
 258 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
 259
 260 /* board specific private data structure */
 261 struct ixgbe_adapter {
 262         struct timer_list watchdog_timer;
 263         struct vlan_group *vlgrp;
 264         u16 bd_number;
 265         struct work_struct reset_task;
 266         struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
 267         char name[MAX_MSIX_COUNT][IFNAMSIZ + 9];
 268         struct ixgbe_dcb_config dcb_cfg;
 269         struct ixgbe_dcb_config temp_dcb_cfg;
 270         u8 dcb_set_bitmap;
 271         enum ixgbe_fc_mode last_lfc_mode;
 272
 273         /* Interrupt Throttle Rate */
 274         u32 rx_itr_setting;
 275         u32 tx_itr_setting;
 276         u16 eitr_low;
 277         u16 eitr_high;
 278
 279         /* TX */
 280         struct ixgbe_ring *tx_ring ____cacheline_aligned_in_smp; /* One per active queue */
 281         int num_tx_queues;
 282         u32 tx_timeout_count;
 283         bool detect_tx_hung;
 284
 285         u64 restart_queue;
 286         u64 lsc_int;
 287
 288         /* RX */
 289         struct ixgbe_ring *rx_ring ____cacheline_aligned_in_smp; /* One per active queue */
 290         int num_rx_queues;
 291         u64 hw_csum_rx_error;
 292         u64 hw_rx_no_dma_resources;
 293         u64 non_eop_descs;
 294         int num_msix_vectors;
 295         int max_msix_q_vectors;         /* true count of q_vectors for device */
 296         struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
 297         struct msix_entry *msix_entries;
 298
 299         u32 alloc_rx_page_failed;
 300         u32 alloc_rx_buff_failed;
 301
 302         /* Some features need tri-state capability,
 303          * thus the additional *_CAPABLE flags.
 304          */
 305         u32 flags;
 306 #define IXGBE_FLAG_RX_CSUM_ENABLED              (u32)(1)
 307 #define IXGBE_FLAG_MSI_CAPABLE                  (u32)(1 << 1)
 308 #define IXGBE_FLAG_MSI_ENABLED                  (u32)(1 << 2)
 309 #define IXGBE_FLAG_MSIX_CAPABLE                 (u32)(1 << 3)
 310 #define IXGBE_FLAG_MSIX_ENABLED                 (u32)(1 << 4)
 311 #define IXGBE_FLAG_RX_1BUF_CAPABLE              (u32)(1 << 6)
 312 #define IXGBE_FLAG_RX_PS_CAPABLE                (u32)(1 << 7)
 313 #define IXGBE_FLAG_RX_PS_ENABLED                (u32)(1 << 8)
 314 #define IXGBE_FLAG_IN_NETPOLL                   (u32)(1 << 9)
 315 #define IXGBE_FLAG_DCA_ENABLED                  (u32)(1 << 10)
 316 #define IXGBE_FLAG_DCA_CAPABLE                  (u32)(1 << 11)
 317 #define IXGBE_FLAG_IMIR_ENABLED                 (u32)(1 << 12)
 318 #define IXGBE_FLAG_MQ_CAPABLE                   (u32)(1 << 13)
 319 #define IXGBE_FLAG_DCB_ENABLED                  (u32)(1 << 14)
 320 #define IXGBE_FLAG_RSS_ENABLED                  (u32)(1 << 16)
 321 #define IXGBE_FLAG_RSS_CAPABLE                  (u32)(1 << 17)
 322 #define IXGBE_FLAG_VMDQ_CAPABLE                 (u32)(1 << 18)
 323 #define IXGBE_FLAG_VMDQ_ENABLED                 (u32)(1 << 19)
 324 #define IXGBE_FLAG_FAN_FAIL_CAPABLE             (u32)(1 << 20)
 325 #define IXGBE_FLAG_NEED_LINK_UPDATE             (u32)(1 << 22)
 326 #define IXGBE_FLAG_IN_WATCHDOG_TASK             (u32)(1 << 23)
 327 #define IXGBE_FLAG_IN_SFP_LINK_TASK             (u32)(1 << 24)
 328 #define IXGBE_FLAG_IN_SFP_MOD_TASK              (u32)(1 << 25)
 329 #define IXGBE_FLAG_FDIR_HASH_CAPABLE            (u32)(1 << 26)
 330 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE         (u32)(1 << 27)
 331 #define IXGBE_FLAG_FCOE_CAPABLE                 (u32)(1 << 28)
 332 #define IXGBE_FLAG_FCOE_ENABLED                 (u32)(1 << 29)
 333
 334         u32 flags2;
 335 #define IXGBE_FLAG2_RSC_CAPABLE                 (u32)(1)
 336 #define IXGBE_FLAG2_RSC_ENABLED                 (u32)(1 << 1)
 337 /* default to trying for four seconds */
 338 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
 339
 340         /* OS defined structs */
 341         struct net_device *netdev;
 342         struct pci_dev *pdev;
 343
 344         u32 test_icr;
 345         struct ixgbe_ring test_tx_ring;
 346         struct ixgbe_ring test_rx_ring;
 347
 348         /* structs defined in ixgbe_hw.h */
 349         struct ixgbe_hw hw;
 350         u16 msg_enable;
 351         struct ixgbe_hw_stats stats;
 352
 353         /* Interrupt Throttle Rate */
 354         u32 rx_eitr_param;
 355         u32 tx_eitr_param;
 356
 357         unsigned long state;
 358         u64 tx_busy;
 359         unsigned int tx_ring_count;
 360         unsigned int rx_ring_count;
 361
 362         u32 link_speed;
 363         bool link_up;
 364         unsigned long link_check_timeout;
 365
 366         struct work_struct watchdog_task;
 367         struct work_struct sfp_task;
 368         struct timer_list sfp_timer;
 369         struct work_struct multispeed_fiber_task;
 370         struct work_struct sfp_config_module_task;
 371         u32 fdir_pballoc;
 372         u32 atr_sample_rate;
 373         spinlock_t fdir_perfect_lock;
 374         struct work_struct fdir_reinit_task;
 375 #ifdef IXGBE_FCOE
 376         struct ixgbe_fcoe fcoe;
 377 #endif /* IXGBE_FCOE */
 378         u64 rsc_total_count;
 379         u64 rsc_total_flush;
 380         u32 wol;
 381         u16 eeprom_version;
 382 };
 383
 384 enum ixbge_state_t {
 385         __IXGBE_TESTING,
 386         __IXGBE_RESETTING,
 387         __IXGBE_DOWN,
 388         __IXGBE_FDIR_INIT_DONE,
 389         __IXGBE_SFP_MODULE_NOT_FOUND
 390 };
 391
 392 enum ixgbe_boards {
 393         board_82598,
 394         board_82599,
 395 };
 396
 397 extern struct ixgbe_info ixgbe_82598_info;
 398 extern struct ixgbe_info ixgbe_82599_info;
 399 #ifdef CONFIG_IXGBE_DCB
 400 extern const struct dcbnl_rtnl_ops dcbnl_ops;
 401 extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
 402                               struct ixgbe_dcb_config *dst_dcb_cfg,
 403                               int tc_max);
 404 #endif
 405
 406 extern char ixgbe_driver_name[];
 407 extern const char ixgbe_driver_version[];
 408
 409 extern int ixgbe_up(struct ixgbe_adapter *adapter);
 410 extern void ixgbe_down(struct ixgbe_adapter *adapter);
 411 extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
 412 extern void ixgbe_reset(struct ixgbe_adapter *adapter);
 413 extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
 414 extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
 415 extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
 416 extern void ixgbe_free_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
 417 extern void ixgbe_free_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
 418 extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
 419 extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
 420 extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
 421 extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
 422 extern int ethtool_ioctl(struct ifreq *ifr);
 423 extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
 424 extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc);
 425 extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc);
 426 extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
 427                                                  struct ixgbe_atr_input *input,
 428                                                  u8 queue);
 429 extern s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input,
 430                                        u16 vlan_id);
 431 extern s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input,
 432                                         u32 src_addr);
 433 extern s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input,
 434                                         u32 dst_addr);
 435 extern s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input,
 436                                         u16 src_port);
 437 extern s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input,
 438                                         u16 dst_port);
 439 extern s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input,
 440                                          u16 flex_byte);
 441 extern s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input,
 442                                       u8 l4type);
 443 #ifdef IXGBE_FCOE
 444 extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
 445 extern int ixgbe_fso(struct ixgbe_adapter *adapter,
 446                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
 447                      u32 tx_flags, u8 *hdr_len);
 448 extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
 449 extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
 450                           union ixgbe_adv_rx_desc *rx_desc,
 451                           struct sk_buff *skb);
 452 extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
 453                               struct scatterlist *sgl, unsigned int sgc);
 454 extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
 455 extern int ixgbe_fcoe_enable(struct net_device *netdev);
 456 extern int ixgbe_fcoe_disable(struct net_device *netdev);
 457 #ifdef CONFIG_IXGBE_DCB
 458 extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
 459 extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
 460 #endif /* CONFIG_IXGBE_DCB */
 461 extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
 462 #endif /* IXGBE_FCOE */
 463
 464 #endif /* _IXGBE_H_ */