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ixgbe: Do not return 0 in ixgbe_fcoe_ddp() upon FCP_RSP in DDP completion
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_82598.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe.h"
33 #include "ixgbe_phy.h"
34
35 #define IXGBE_82598_MAX_TX_QUEUES 32
36 #define IXGBE_82598_MAX_RX_QUEUES 64
37 #define IXGBE_82598_RAR_ENTRIES 16
38 #define IXGBE_82598_MC_TBL_SIZE 128
39 #define IXGBE_82598_VFT_TBL_SIZE 128
40
41 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
42 ixgbe_link_speed *speed,
43 bool *autoneg);
44 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw);
45 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
46 ixgbe_link_speed speed,
47 bool autoneg,
48 bool autoneg_wait_to_complete);
49 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
50 u8 *eeprom_data);
51
52 /**
53 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
54 * @hw: pointer to the HW structure
55 *
56 * The defaults for 82598 should be in the range of 50us to 50ms,
57 * however the hardware default for these parts is 500us to 1ms which is less
58 * than the 10ms recommended by the pci-e spec. To address this we need to
59 * increase the value to either 10ms to 250ms for capability version 1 config,
60 * or 16ms to 55ms for version 2.
61 **/
62 void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)
63 {
64 struct ixgbe_adapter *adapter = hw->back;
65 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);
66 u16 pcie_devctl2;
67
68 /* only take action if timeout value is defaulted to 0 */
69 if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK)
70 goto out;
71
72 /*
73 * if capababilities version is type 1 we can write the
74 * timeout of 10ms to 250ms through the GCR register
75 */
76 if (!(gcr & IXGBE_GCR_CAP_VER2)) {
77 gcr |= IXGBE_GCR_CMPL_TMOUT_10ms;
78 goto out;
79 }
80
81 /*
82 * for version 2 capabilities we need to write the config space
83 * directly in order to set the completion timeout value for
84 * 16ms to 55ms
85 */
86 pci_read_config_word(adapter->pdev,
87 IXGBE_PCI_DEVICE_CONTROL2, &pcie_devctl2);
88 pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms;
89 pci_write_config_word(adapter->pdev,
90 IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2);
91 out:
92 /* disable completion timeout resend */
93 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND;
94 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);
95 }
96
97 /**
98 * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
99 * @hw: pointer to hardware structure
100 *
101 * Read PCIe configuration space, and get the MSI-X vector count from
102 * the capabilities table.
103 **/
104 static u16 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
105 {
106 struct ixgbe_adapter *adapter = hw->back;
107 u16 msix_count;
108 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82598_CAPS,
109 &msix_count);
110 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
111
112 /* MSI-X count is zero-based in HW, so increment to give proper value */
113 msix_count++;
114
115 return msix_count;
116 }
117
118 /**
119 */
120 static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
121 {
122 struct ixgbe_mac_info *mac = &hw->mac;
123
124 /* Call PHY identify routine to get the phy type */
125 ixgbe_identify_phy_generic(hw);
126
127 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
128 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
129 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
130 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
131 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
132 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw);
133
134 return 0;
135 }
136
137 /**
138 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
139 * @hw: pointer to hardware structure
140 *
141 * Initialize any function pointers that were not able to be
142 * set during get_invariants because the PHY/SFP type was
143 * not known. Perform the SFP init if necessary.
144 *
145 **/
146 s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
147 {
148 struct ixgbe_mac_info *mac = &hw->mac;
149 struct ixgbe_phy_info *phy = &hw->phy;
150 s32 ret_val = 0;
151 u16 list_offset, data_offset;
152
153 /* Identify the PHY */
154 phy->ops.identify(hw);
155
156 /* Overwrite the link function pointers if copper PHY */
157 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
158 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
159 mac->ops.setup_link_speed =
160 &ixgbe_setup_copper_link_speed_82598;
161 mac->ops.get_link_capabilities =
162 &ixgbe_get_copper_link_capabilities_82598;
163 }
164
165 switch (hw->phy.type) {
166 case ixgbe_phy_tn:
167 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
168 phy->ops.get_firmware_version =
169 &ixgbe_get_phy_firmware_version_tnx;
170 break;
171 case ixgbe_phy_nl:
172 phy->ops.reset = &ixgbe_reset_phy_nl;
173
174 /* Call SFP+ identify routine to get the SFP+ module type */
175 ret_val = phy->ops.identify_sfp(hw);
176 if (ret_val != 0)
177 goto out;
178 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
179 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
180 goto out;
181 }
182
183 /* Check to see if SFP+ module is supported */
184 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
185 &list_offset,
186 &data_offset);
187 if (ret_val != 0) {
188 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
189 goto out;
190 }
191 break;
192 default:
193 break;
194 }
195
196 out:
197 return ret_val;
198 }
199
200 /**
201 * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx
202 * @hw: pointer to hardware structure
203 *
204 * Starts the hardware using the generic start_hw function.
205 * Then set pcie completion timeout
206 **/
207 s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
208 {
209 s32 ret_val = 0;
210
211 ret_val = ixgbe_start_hw_generic(hw);
212
213 /* set the completion timeout for interface */
214 if (ret_val == 0)
215 ixgbe_set_pcie_completion_timeout(hw);
216
217 return ret_val;
218 }
219
220 /**
221 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
222 * @hw: pointer to hardware structure
223 * @speed: pointer to link speed
224 * @autoneg: boolean auto-negotiation value
225 *
226 * Determines the link capabilities by reading the AUTOC register.
227 **/
228 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
229 ixgbe_link_speed *speed,
230 bool *autoneg)
231 {
232 s32 status = 0;
233 u32 autoc = 0;
234
235 /*
236 * Determine link capabilities based on the stored value of AUTOC,
237 * which represents EEPROM defaults. If AUTOC value has not been
238 * stored, use the current register value.
239 */
240 if (hw->mac.orig_link_settings_stored)
241 autoc = hw->mac.orig_autoc;
242 else
243 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
244
245 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
246 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
247 *speed = IXGBE_LINK_SPEED_1GB_FULL;
248 *autoneg = false;
249 break;
250
251 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
252 *speed = IXGBE_LINK_SPEED_10GB_FULL;
253 *autoneg = false;
254 break;
255
256 case IXGBE_AUTOC_LMS_1G_AN:
257 *speed = IXGBE_LINK_SPEED_1GB_FULL;
258 *autoneg = true;
259 break;
260
261 case IXGBE_AUTOC_LMS_KX4_AN:
262 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
263 *speed = IXGBE_LINK_SPEED_UNKNOWN;
264 if (autoc & IXGBE_AUTOC_KX4_SUPP)
265 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
266 if (autoc & IXGBE_AUTOC_KX_SUPP)
267 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
268 *autoneg = true;
269 break;
270
271 default:
272 status = IXGBE_ERR_LINK_SETUP;
273 break;
274 }
275
276 return status;
277 }
278
279 /**
280 * ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities
281 * @hw: pointer to hardware structure
282 * @speed: pointer to link speed
283 * @autoneg: boolean auto-negotiation value
284 *
285 * Determines the link capabilities by reading the AUTOC register.
286 **/
287 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
288 ixgbe_link_speed *speed,
289 bool *autoneg)
290 {
291 s32 status = IXGBE_ERR_LINK_SETUP;
292 u16 speed_ability;
293
294 *speed = 0;
295 *autoneg = true;
296
297 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
298 &speed_ability);
299
300 if (status == 0) {
301 if (speed_ability & MDIO_SPEED_10G)
302 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
303 if (speed_ability & MDIO_PMA_SPEED_1000)
304 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
305 }
306
307 return status;
308 }
309
310 /**
311 * ixgbe_get_media_type_82598 - Determines media type
312 * @hw: pointer to hardware structure
313 *
314 * Returns the media type (fiber, copper, backplane)
315 **/
316 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
317 {
318 enum ixgbe_media_type media_type;
319
320 /* Media type for I82598 is based on device ID */
321 switch (hw->device_id) {
322 case IXGBE_DEV_ID_82598:
323 case IXGBE_DEV_ID_82598_BX:
324 media_type = ixgbe_media_type_backplane;
325 break;
326 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
327 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
328 case IXGBE_DEV_ID_82598EB_CX4:
329 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
330 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
331 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
332 case IXGBE_DEV_ID_82598EB_XF_LR:
333 case IXGBE_DEV_ID_82598EB_SFP_LOM:
334 media_type = ixgbe_media_type_fiber;
335 break;
336 case IXGBE_DEV_ID_82598AT:
337 media_type = ixgbe_media_type_copper;
338 break;
339 default:
340 media_type = ixgbe_media_type_unknown;
341 break;
342 }
343
344 return media_type;
345 }
346
347 /**
348 * ixgbe_fc_enable_82598 - Enable flow control
349 * @hw: pointer to hardware structure
350 * @packetbuf_num: packet buffer number (0-7)
351 *
352 * Enable flow control according to the current settings.
353 **/
354 static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
355 {
356 s32 ret_val = 0;
357 u32 fctrl_reg;
358 u32 rmcs_reg;
359 u32 reg;
360
361 #ifdef CONFIG_DCB
362 if (hw->fc.requested_mode == ixgbe_fc_pfc)
363 goto out;
364
365 #endif /* CONFIG_DCB */
366 /* Negotiate the fc mode to use */
367 ret_val = ixgbe_fc_autoneg(hw);
368 if (ret_val)
369 goto out;
370
371 /* Disable any previous flow control settings */
372 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
373 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
374
375 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
376 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
377
378 /*
379 * The possible values of fc.current_mode are:
380 * 0: Flow control is completely disabled
381 * 1: Rx flow control is enabled (we can receive pause frames,
382 * but not send pause frames).
383 * 2: Tx flow control is enabled (we can send pause frames but
384 * we do not support receiving pause frames).
385 * 3: Both Rx and Tx flow control (symmetric) are enabled.
386 * other: Invalid.
387 #ifdef CONFIG_DCB
388 * 4: Priority Flow Control is enabled.
389 #endif
390 */
391 switch (hw->fc.current_mode) {
392 case ixgbe_fc_none:
393 /*
394 * Flow control is disabled by software override or autoneg.
395 * The code below will actually disable it in the HW.
396 */
397 break;
398 case ixgbe_fc_rx_pause:
399 /*
400 * Rx Flow control is enabled and Tx Flow control is
401 * disabled by software override. Since there really
402 * isn't a way to advertise that we are capable of RX
403 * Pause ONLY, we will advertise that we support both
404 * symmetric and asymmetric Rx PAUSE. Later, we will
405 * disable the adapter's ability to send PAUSE frames.
406 */
407 fctrl_reg |= IXGBE_FCTRL_RFCE;
408 break;
409 case ixgbe_fc_tx_pause:
410 /*
411 * Tx Flow control is enabled, and Rx Flow control is
412 * disabled by software override.
413 */
414 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
415 break;
416 case ixgbe_fc_full:
417 /* Flow control (both Rx and Tx) is enabled by SW override. */
418 fctrl_reg |= IXGBE_FCTRL_RFCE;
419 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
420 break;
421 #ifdef CONFIG_DCB
422 case ixgbe_fc_pfc:
423 goto out;
424 break;
425 #endif /* CONFIG_DCB */
426 default:
427 hw_dbg(hw, "Flow control param set incorrectly\n");
428 ret_val = -IXGBE_ERR_CONFIG;
429 goto out;
430 break;
431 }
432
433 /* Set 802.3x based flow control settings. */
434 fctrl_reg |= IXGBE_FCTRL_DPF;
435 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
436 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
437
438 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
439 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
440 if (hw->fc.send_xon) {
441 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
442 (hw->fc.low_water | IXGBE_FCRTL_XONE));
443 } else {
444 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
445 hw->fc.low_water);
446 }
447
448 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num),
449 (hw->fc.high_water | IXGBE_FCRTH_FCEN));
450 }
451
452 /* Configure pause time (2 TCs per register) */
453 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
454 if ((packetbuf_num & 1) == 0)
455 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
456 else
457 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
458 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
459
460 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
461
462 out:
463 return ret_val;
464 }
465
466 /**
467 * ixgbe_setup_mac_link_82598 - Configures MAC link settings
468 * @hw: pointer to hardware structure
469 *
470 * Configures link settings based on values in the ixgbe_hw struct.
471 * Restarts the link. Performs autonegotiation if needed.
472 **/
473 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
474 {
475 u32 autoc_reg;
476 u32 links_reg;
477 u32 i;
478 s32 status = 0;
479
480 /* Restart link */
481 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
482 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
483 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
484
485 /* Only poll for autoneg to complete if specified to do so */
486 if (hw->phy.autoneg_wait_to_complete) {
487 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
488 IXGBE_AUTOC_LMS_KX4_AN ||
489 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
490 IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
491 links_reg = 0; /* Just in case Autoneg time = 0 */
492 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
493 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
494 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
495 break;
496 msleep(100);
497 }
498 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
499 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
500 hw_dbg(hw, "Autonegotiation did not complete.\n");
501 }
502 }
503 }
504
505 /* Add delay to filter out noises during initial link setup */
506 msleep(50);
507
508 return status;
509 }
510
511 /**
512 * ixgbe_check_mac_link_82598 - Get link/speed status
513 * @hw: pointer to hardware structure
514 * @speed: pointer to link speed
515 * @link_up: true is link is up, false otherwise
516 * @link_up_wait_to_complete: bool used to wait for link up or not
517 *
518 * Reads the links register to determine if link is up and the current speed
519 **/
520 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
521 ixgbe_link_speed *speed, bool *link_up,
522 bool link_up_wait_to_complete)
523 {
524 u32 links_reg;
525 u32 i;
526 u16 link_reg, adapt_comp_reg;
527
528 /*
529 * SERDES PHY requires us to read link status from register 0xC79F.
530 * Bit 0 set indicates link is up/ready; clear indicates link down.
531 * 0xC00C is read to check that the XAUI lanes are active. Bit 0
532 * clear indicates active; set indicates inactive.
533 */
534 if (hw->phy.type == ixgbe_phy_nl) {
535 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
536 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
537 hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD,
538 &adapt_comp_reg);
539 if (link_up_wait_to_complete) {
540 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
541 if ((link_reg & 1) &&
542 ((adapt_comp_reg & 1) == 0)) {
543 *link_up = true;
544 break;
545 } else {
546 *link_up = false;
547 }
548 msleep(100);
549 hw->phy.ops.read_reg(hw, 0xC79F,
550 MDIO_MMD_PMAPMD,
551 &link_reg);
552 hw->phy.ops.read_reg(hw, 0xC00C,
553 MDIO_MMD_PMAPMD,
554 &adapt_comp_reg);
555 }
556 } else {
557 if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
558 *link_up = true;
559 else
560 *link_up = false;
561 }
562
563 if (*link_up == false)
564 goto out;
565 }
566
567 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
568 if (link_up_wait_to_complete) {
569 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
570 if (links_reg & IXGBE_LINKS_UP) {
571 *link_up = true;
572 break;
573 } else {
574 *link_up = false;
575 }
576 msleep(100);
577 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
578 }
579 } else {
580 if (links_reg & IXGBE_LINKS_UP)
581 *link_up = true;
582 else
583 *link_up = false;
584 }
585
586 if (links_reg & IXGBE_LINKS_SPEED)
587 *speed = IXGBE_LINK_SPEED_10GB_FULL;
588 else
589 *speed = IXGBE_LINK_SPEED_1GB_FULL;
590
591 /* if link is down, zero out the current_mode */
592 if (*link_up == false) {
593 hw->fc.current_mode = ixgbe_fc_none;
594 hw->fc.fc_was_autonegged = false;
595 }
596 out:
597 return 0;
598 }
599
600
601 /**
602 * ixgbe_setup_mac_link_speed_82598 - Set MAC link speed
603 * @hw: pointer to hardware structure
604 * @speed: new link speed
605 * @autoneg: true if auto-negotiation enabled
606 * @autoneg_wait_to_complete: true if waiting is needed to complete
607 *
608 * Set the link speed in the AUTOC register and restarts link.
609 **/
610 static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
611 ixgbe_link_speed speed, bool autoneg,
612 bool autoneg_wait_to_complete)
613 {
614 s32 status = 0;
615 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
616 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
617 u32 autoc = curr_autoc;
618 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
619
620 /* Check to see if speed passed in is supported. */
621 ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg);
622 speed &= link_capabilities;
623
624 if (speed == IXGBE_LINK_SPEED_UNKNOWN)
625 status = IXGBE_ERR_LINK_SETUP;
626
627 /* Set KX4/KX support according to speed requested */
628 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
629 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
630 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
631 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
632 autoc |= IXGBE_AUTOC_KX4_SUPP;
633 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
634 autoc |= IXGBE_AUTOC_KX_SUPP;
635 if (autoc != curr_autoc)
636 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
637 }
638
639 if (status == 0) {
640 hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete;
641
642 /*
643 * Setup and restart the link based on the new values in
644 * ixgbe_hw This will write the AUTOC register based on the new
645 * stored values
646 */
647 status = ixgbe_setup_mac_link_82598(hw);
648 }
649
650 return status;
651 }
652
653
654 /**
655 * ixgbe_setup_copper_link_82598 - Setup copper link settings
656 * @hw: pointer to hardware structure
657 *
658 * Configures link settings based on values in the ixgbe_hw struct.
659 * Restarts the link. Performs autonegotiation if needed. Restart
660 * phy and wait for autonegotiate to finish. Then synchronize the
661 * MAC and PHY.
662 **/
663 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
664 {
665 s32 status;
666
667 /* Restart autonegotiation on PHY */
668 status = hw->phy.ops.setup_link(hw);
669
670 /* Set up MAC */
671 ixgbe_setup_mac_link_82598(hw);
672
673 return status;
674 }
675
676 /**
677 * ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field
678 * @hw: pointer to hardware structure
679 * @speed: new link speed
680 * @autoneg: true if autonegotiation enabled
681 * @autoneg_wait_to_complete: true if waiting is needed to complete
682 *
683 * Sets the link speed in the AUTOC register in the MAC and restarts link.
684 **/
685 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
686 ixgbe_link_speed speed,
687 bool autoneg,
688 bool autoneg_wait_to_complete)
689 {
690 s32 status;
691
692 /* Setup the PHY according to input speed */
693 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
694 autoneg_wait_to_complete);
695
696 /* Set up MAC */
697 ixgbe_setup_mac_link_82598(hw);
698
699 return status;
700 }
701
702 /**
703 * ixgbe_reset_hw_82598 - Performs hardware reset
704 * @hw: pointer to hardware structure
705 *
706 * Resets the hardware by resetting the transmit and receive units, masks and
707 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
708 * reset.
709 **/
710 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
711 {
712 s32 status = 0;
713 s32 phy_status = 0;
714 u32 ctrl;
715 u32 gheccr;
716 u32 i;
717 u32 autoc;
718 u8 analog_val;
719
720 /* Call adapter stop to disable tx/rx and clear interrupts */
721 hw->mac.ops.stop_adapter(hw);
722
723 /*
724 * Power up the Atlas Tx lanes if they are currently powered down.
725 * Atlas Tx lanes are powered down for MAC loopback tests, but
726 * they are not automatically restored on reset.
727 */
728 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
729 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
730 /* Enable Tx Atlas so packets can be transmitted again */
731 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
732 &analog_val);
733 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
734 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
735 analog_val);
736
737 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
738 &analog_val);
739 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
740 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
741 analog_val);
742
743 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
744 &analog_val);
745 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
746 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
747 analog_val);
748
749 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
750 &analog_val);
751 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
752 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
753 analog_val);
754 }
755
756 /* Reset PHY */
757 if (hw->phy.reset_disable == false) {
758 /* PHY ops must be identified and initialized prior to reset */
759
760 /* Init PHY and function pointers, perform SFP setup */
761 phy_status = hw->phy.ops.init(hw);
762 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED)
763 goto reset_hw_out;
764 else if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)
765 goto no_phy_reset;
766
767
768 hw->phy.ops.reset(hw);
769 }
770
771 no_phy_reset:
772 /*
773 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
774 * access and verify no pending requests before reset
775 */
776 status = ixgbe_disable_pcie_master(hw);
777 if (status != 0) {
778 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
779 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
780 }
781
782 /*
783 * Issue global reset to the MAC. This needs to be a SW reset.
784 * If link reset is used, it might reset the MAC when mng is using it
785 */
786 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
787 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
788 IXGBE_WRITE_FLUSH(hw);
789
790 /* Poll for reset bit to self-clear indicating reset is complete */
791 for (i = 0; i < 10; i++) {
792 udelay(1);
793 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
794 if (!(ctrl & IXGBE_CTRL_RST))
795 break;
796 }
797 if (ctrl & IXGBE_CTRL_RST) {
798 status = IXGBE_ERR_RESET_FAILED;
799 hw_dbg(hw, "Reset polling failed to complete.\n");
800 }
801
802 msleep(50);
803
804 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
805 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
806 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
807
808 /*
809 * Store the original AUTOC value if it has not been
810 * stored off yet. Otherwise restore the stored original
811 * AUTOC value since the reset operation sets back to deaults.
812 */
813 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
814 if (hw->mac.orig_link_settings_stored == false) {
815 hw->mac.orig_autoc = autoc;
816 hw->mac.orig_link_settings_stored = true;
817 } else if (autoc != hw->mac.orig_autoc) {
818 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
819 }
820
821 /*
822 * Store MAC address from RAR0, clear receive address registers, and
823 * clear the multicast table
824 */
825 hw->mac.ops.init_rx_addrs(hw);
826
827 /* Store the permanent mac address */
828 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
829
830 reset_hw_out:
831 if (phy_status)
832 status = phy_status;
833
834 return status;
835 }
836
837 /**
838 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
839 * @hw: pointer to hardware struct
840 * @rar: receive address register index to associate with a VMDq index
841 * @vmdq: VMDq set index
842 **/
843 static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
844 {
845 u32 rar_high;
846
847 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
848 rar_high &= ~IXGBE_RAH_VIND_MASK;
849 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
850 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
851 return 0;
852 }
853
854 /**
855 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
856 * @hw: pointer to hardware struct
857 * @rar: receive address register index to associate with a VMDq index
858 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
859 **/
860 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
861 {
862 u32 rar_high;
863 u32 rar_entries = hw->mac.num_rar_entries;
864
865 if (rar < rar_entries) {
866 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
867 if (rar_high & IXGBE_RAH_VIND_MASK) {
868 rar_high &= ~IXGBE_RAH_VIND_MASK;
869 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
870 }
871 } else {
872 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
873 }
874
875 return 0;
876 }
877
878 /**
879 * ixgbe_set_vfta_82598 - Set VLAN filter table
880 * @hw: pointer to hardware structure
881 * @vlan: VLAN id to write to VLAN filter
882 * @vind: VMDq output index that maps queue to VLAN id in VFTA
883 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
884 *
885 * Turn on/off specified VLAN in the VLAN filter table.
886 **/
887 static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
888 bool vlan_on)
889 {
890 u32 regindex;
891 u32 bitindex;
892 u32 bits;
893 u32 vftabyte;
894
895 if (vlan > 4095)
896 return IXGBE_ERR_PARAM;
897
898 /* Determine 32-bit word position in array */
899 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */
900
901 /* Determine the location of the (VMD) queue index */
902 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
903 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */
904
905 /* Set the nibble for VMD queue index */
906 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
907 bits &= (~(0x0F << bitindex));
908 bits |= (vind << bitindex);
909 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
910
911 /* Determine the location of the bit for this VLAN id */
912 bitindex = vlan & 0x1F; /* lower five bits */
913
914 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
915 if (vlan_on)
916 /* Turn on this VLAN id */
917 bits |= (1 << bitindex);
918 else
919 /* Turn off this VLAN id */
920 bits &= ~(1 << bitindex);
921 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
922
923 return 0;
924 }
925
926 /**
927 * ixgbe_clear_vfta_82598 - Clear VLAN filter table
928 * @hw: pointer to hardware structure
929 *
930 * Clears the VLAN filer table, and the VMDq index associated with the filter
931 **/
932 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
933 {
934 u32 offset;
935 u32 vlanbyte;
936
937 for (offset = 0; offset < hw->mac.vft_size; offset++)
938 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
939
940 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
941 for (offset = 0; offset < hw->mac.vft_size; offset++)
942 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
943 0);
944
945 return 0;
946 }
947
948 /**
949 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
950 * @hw: pointer to hardware structure
951 * @reg: analog register to read
952 * @val: read value
953 *
954 * Performs read operation to Atlas analog register specified.
955 **/
956 static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
957 {
958 u32 atlas_ctl;
959
960 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
961 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
962 IXGBE_WRITE_FLUSH(hw);
963 udelay(10);
964 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
965 *val = (u8)atlas_ctl;
966
967 return 0;
968 }
969
970 /**
971 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
972 * @hw: pointer to hardware structure
973 * @reg: atlas register to write
974 * @val: value to write
975 *
976 * Performs write operation to Atlas analog register specified.
977 **/
978 static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
979 {
980 u32 atlas_ctl;
981
982 atlas_ctl = (reg << 8) | val;
983 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
984 IXGBE_WRITE_FLUSH(hw);
985 udelay(10);
986
987 return 0;
988 }
989
990 /**
991 * ixgbe_read_i2c_eeprom_82598 - Read 8 bit EEPROM word of an SFP+ module
992 * over I2C interface through an intermediate phy.
993 * @hw: pointer to hardware structure
994 * @byte_offset: EEPROM byte offset to read
995 * @eeprom_data: value read
996 *
997 * Performs byte read operation to SFP module's EEPROM over I2C interface.
998 **/
999 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
1000 u8 *eeprom_data)
1001 {
1002 s32 status = 0;
1003 u16 sfp_addr = 0;
1004 u16 sfp_data = 0;
1005 u16 sfp_stat = 0;
1006 u32 i;
1007
1008 if (hw->phy.type == ixgbe_phy_nl) {
1009 /*
1010 * phy SDA/SCL registers are at addresses 0xC30A to
1011 * 0xC30D. These registers are used to talk to the SFP+
1012 * module's EEPROM through the SDA/SCL (I2C) interface.
1013 */
1014 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
1015 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
1016 hw->phy.ops.write_reg(hw,
1017 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
1018 MDIO_MMD_PMAPMD,
1019 sfp_addr);
1020
1021 /* Poll status */
1022 for (i = 0; i < 100; i++) {
1023 hw->phy.ops.read_reg(hw,
1024 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
1025 MDIO_MMD_PMAPMD,
1026 &sfp_stat);
1027 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
1028 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
1029 break;
1030 msleep(10);
1031 }
1032
1033 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
1034 hw_dbg(hw, "EEPROM read did not pass.\n");
1035 status = IXGBE_ERR_SFP_NOT_PRESENT;
1036 goto out;
1037 }
1038
1039 /* Read data */
1040 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1041 MDIO_MMD_PMAPMD, &sfp_data);
1042
1043 *eeprom_data = (u8)(sfp_data >> 8);
1044 } else {
1045 status = IXGBE_ERR_PHY;
1046 goto out;
1047 }
1048
1049 out:
1050 return status;
1051 }
1052
1053 /**
1054 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1055 * @hw: pointer to hardware structure
1056 *
1057 * Determines physical layer capabilities of the current configuration.
1058 **/
1059 static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1060 {
1061 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1062 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1063 u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1064 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1065 u16 ext_ability = 0;
1066
1067 hw->phy.ops.identify(hw);
1068
1069 /* Copper PHY must be checked before AUTOC LMS to determine correct
1070 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
1071 if (hw->phy.type == ixgbe_phy_tn ||
1072 hw->phy.type == ixgbe_phy_cu_unknown) {
1073 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1074 &ext_ability);
1075 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
1076 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1077 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
1078 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1079 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
1080 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1081 goto out;
1082 }
1083
1084 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1085 case IXGBE_AUTOC_LMS_1G_AN:
1086 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1087 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX)
1088 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1089 else
1090 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1091 break;
1092 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1093 if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4)
1094 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1095 else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4)
1096 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1097 else /* XAUI */
1098 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1099 break;
1100 case IXGBE_AUTOC_LMS_KX4_AN:
1101 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
1102 if (autoc & IXGBE_AUTOC_KX_SUPP)
1103 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1104 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1105 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1106 break;
1107 default:
1108 break;
1109 }
1110
1111 if (hw->phy.type == ixgbe_phy_nl) {
1112 hw->phy.ops.identify_sfp(hw);
1113
1114 switch (hw->phy.sfp_type) {
1115 case ixgbe_sfp_type_da_cu:
1116 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1117 break;
1118 case ixgbe_sfp_type_sr:
1119 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1120 break;
1121 case ixgbe_sfp_type_lr:
1122 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1123 break;
1124 default:
1125 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1126 break;
1127 }
1128 }
1129
1130 switch (hw->device_id) {
1131 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1132 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1133 break;
1134 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
1135 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1136 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
1137 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1138 break;
1139 case IXGBE_DEV_ID_82598EB_XF_LR:
1140 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1141 break;
1142 default:
1143 break;
1144 }
1145
1146 out:
1147 return physical_layer;
1148 }
1149
1150 static struct ixgbe_mac_operations mac_ops_82598 = {
1151 .init_hw = &ixgbe_init_hw_generic,
1152 .reset_hw = &ixgbe_reset_hw_82598,
1153 .start_hw = &ixgbe_start_hw_82598,
1154 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
1155 .get_media_type = &ixgbe_get_media_type_82598,
1156 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598,
1157 .enable_rx_dma = &ixgbe_enable_rx_dma_generic,
1158 .get_mac_addr = &ixgbe_get_mac_addr_generic,
1159 .stop_adapter = &ixgbe_stop_adapter_generic,
1160 .get_bus_info = &ixgbe_get_bus_info_generic,
1161 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
1162 .read_analog_reg8 = &ixgbe_read_analog_reg8_82598,
1163 .write_analog_reg8 = &ixgbe_write_analog_reg8_82598,
1164 .setup_link = &ixgbe_setup_mac_link_82598,
1165 .setup_link_speed = &ixgbe_setup_mac_link_speed_82598,
1166 .check_link = &ixgbe_check_mac_link_82598,
1167 .get_link_capabilities = &ixgbe_get_link_capabilities_82598,
1168 .led_on = &ixgbe_led_on_generic,
1169 .led_off = &ixgbe_led_off_generic,
1170 .blink_led_start = &ixgbe_blink_led_start_generic,
1171 .blink_led_stop = &ixgbe_blink_led_stop_generic,
1172 .set_rar = &ixgbe_set_rar_generic,
1173 .clear_rar = &ixgbe_clear_rar_generic,
1174 .set_vmdq = &ixgbe_set_vmdq_82598,
1175 .clear_vmdq = &ixgbe_clear_vmdq_82598,
1176 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
1177 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
1178 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
1179 .enable_mc = &ixgbe_enable_mc_generic,
1180 .disable_mc = &ixgbe_disable_mc_generic,
1181 .clear_vfta = &ixgbe_clear_vfta_82598,
1182 .set_vfta = &ixgbe_set_vfta_82598,
1183 .fc_enable = &ixgbe_fc_enable_82598,
1184 };
1185
1186 static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
1187 .init_params = &ixgbe_init_eeprom_params_generic,
1188 .read = &ixgbe_read_eeprom_generic,
1189 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
1190 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
1191 };
1192
1193 static struct ixgbe_phy_operations phy_ops_82598 = {
1194 .identify = &ixgbe_identify_phy_generic,
1195 .identify_sfp = &ixgbe_identify_sfp_module_generic,
1196 .init = &ixgbe_init_phy_ops_82598,
1197 .reset = &ixgbe_reset_phy_generic,
1198 .read_reg = &ixgbe_read_phy_reg_generic,
1199 .write_reg = &ixgbe_write_phy_reg_generic,
1200 .setup_link = &ixgbe_setup_phy_link_generic,
1201 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
1202 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598,
1203 };
1204
1205 struct ixgbe_info ixgbe_82598_info = {
1206 .mac = ixgbe_mac_82598EB,
1207 .get_invariants = &ixgbe_get_invariants_82598,
1208 .mac_ops = &mac_ops_82598,
1209 .eeprom_ops = &eeprom_ops_82598,
1210 .phy_ops = &phy_ops_82598,
1211 };
1212
Linux kernel - Deliverables
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