1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
33 #include "ixgbe_phy.h"
35 #define IXGBE_82598_MAX_TX_QUEUES 32
36 #define IXGBE_82598_MAX_RX_QUEUES 64
37 #define IXGBE_82598_RAR_ENTRIES 16
38 #define IXGBE_82598_MC_TBL_SIZE 128
39 #define IXGBE_82598_VFT_TBL_SIZE 128
41 static s32
ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw
*hw
,
42 ixgbe_link_speed
*speed
,
44 static s32
ixgbe_setup_copper_link_82598(struct ixgbe_hw
*hw
);
45 static s32
ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw
*hw
,
46 ixgbe_link_speed speed
,
48 bool autoneg_wait_to_complete
);
49 static s32
ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw
*hw
, u8 byte_offset
,
53 * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
54 * @hw: pointer to hardware structure
56 * Read PCIe configuration space, and get the MSI-X vector count from
57 * the capabilities table.
59 static u16
ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw
*hw
)
61 struct ixgbe_adapter
*adapter
= hw
->back
;
63 pci_read_config_word(adapter
->pdev
, IXGBE_PCIE_MSIX_82598_CAPS
,
65 msix_count
&= IXGBE_PCIE_MSIX_TBL_SZ_MASK
;
67 /* MSI-X count is zero-based in HW, so increment to give proper value */
75 static s32
ixgbe_get_invariants_82598(struct ixgbe_hw
*hw
)
77 struct ixgbe_mac_info
*mac
= &hw
->mac
;
79 /* Call PHY identify routine to get the phy type */
80 ixgbe_identify_phy_generic(hw
);
82 mac
->mcft_size
= IXGBE_82598_MC_TBL_SIZE
;
83 mac
->vft_size
= IXGBE_82598_VFT_TBL_SIZE
;
84 mac
->num_rar_entries
= IXGBE_82598_RAR_ENTRIES
;
85 mac
->max_rx_queues
= IXGBE_82598_MAX_RX_QUEUES
;
86 mac
->max_tx_queues
= IXGBE_82598_MAX_TX_QUEUES
;
87 mac
->max_msix_vectors
= ixgbe_get_pcie_msix_count_82598(hw
);
93 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
94 * @hw: pointer to hardware structure
96 * Initialize any function pointers that were not able to be
97 * set during get_invariants because the PHY/SFP type was
98 * not known. Perform the SFP init if necessary.
101 s32
ixgbe_init_phy_ops_82598(struct ixgbe_hw
*hw
)
103 struct ixgbe_mac_info
*mac
= &hw
->mac
;
104 struct ixgbe_phy_info
*phy
= &hw
->phy
;
106 u16 list_offset
, data_offset
;
108 /* Identify the PHY */
109 phy
->ops
.identify(hw
);
111 /* Overwrite the link function pointers if copper PHY */
112 if (mac
->ops
.get_media_type(hw
) == ixgbe_media_type_copper
) {
113 mac
->ops
.setup_link
= &ixgbe_setup_copper_link_82598
;
114 mac
->ops
.setup_link_speed
=
115 &ixgbe_setup_copper_link_speed_82598
;
116 mac
->ops
.get_link_capabilities
=
117 &ixgbe_get_copper_link_capabilities_82598
;
120 switch (hw
->phy
.type
) {
122 phy
->ops
.check_link
= &ixgbe_check_phy_link_tnx
;
123 phy
->ops
.get_firmware_version
=
124 &ixgbe_get_phy_firmware_version_tnx
;
127 phy
->ops
.reset
= &ixgbe_reset_phy_nl
;
129 /* Call SFP+ identify routine to get the SFP+ module type */
130 ret_val
= phy
->ops
.identify_sfp(hw
);
133 else if (hw
->phy
.sfp_type
== ixgbe_sfp_type_unknown
) {
134 ret_val
= IXGBE_ERR_SFP_NOT_SUPPORTED
;
138 /* Check to see if SFP+ module is supported */
139 ret_val
= ixgbe_get_sfp_init_sequence_offsets(hw
,
143 ret_val
= IXGBE_ERR_SFP_NOT_SUPPORTED
;
156 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
157 * @hw: pointer to hardware structure
158 * @speed: pointer to link speed
159 * @autoneg: boolean auto-negotiation value
161 * Determines the link capabilities by reading the AUTOC register.
163 static s32
ixgbe_get_link_capabilities_82598(struct ixgbe_hw
*hw
,
164 ixgbe_link_speed
*speed
,
171 * Determine link capabilities based on the stored value of AUTOC,
172 * which represents EEPROM defaults. If AUTOC value has not been
173 * stored, use the current register value.
175 if (hw
->mac
.orig_link_settings_stored
)
176 autoc
= hw
->mac
.orig_autoc
;
178 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
180 switch (autoc
& IXGBE_AUTOC_LMS_MASK
) {
181 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN
:
182 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
186 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN
:
187 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
191 case IXGBE_AUTOC_LMS_1G_AN
:
192 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
196 case IXGBE_AUTOC_LMS_KX4_AN
:
197 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN
:
198 *speed
= IXGBE_LINK_SPEED_UNKNOWN
;
199 if (autoc
& IXGBE_AUTOC_KX4_SUPP
)
200 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
201 if (autoc
& IXGBE_AUTOC_KX_SUPP
)
202 *speed
|= IXGBE_LINK_SPEED_1GB_FULL
;
207 status
= IXGBE_ERR_LINK_SETUP
;
215 * ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities
216 * @hw: pointer to hardware structure
217 * @speed: pointer to link speed
218 * @autoneg: boolean auto-negotiation value
220 * Determines the link capabilities by reading the AUTOC register.
222 static s32
ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw
*hw
,
223 ixgbe_link_speed
*speed
,
226 s32 status
= IXGBE_ERR_LINK_SETUP
;
232 status
= hw
->phy
.ops
.read_reg(hw
, MDIO_SPEED
, MDIO_MMD_PMAPMD
,
236 if (speed_ability
& MDIO_SPEED_10G
)
237 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
238 if (speed_ability
& MDIO_PMA_SPEED_1000
)
239 *speed
|= IXGBE_LINK_SPEED_1GB_FULL
;
246 * ixgbe_get_media_type_82598 - Determines media type
247 * @hw: pointer to hardware structure
249 * Returns the media type (fiber, copper, backplane)
251 static enum ixgbe_media_type
ixgbe_get_media_type_82598(struct ixgbe_hw
*hw
)
253 enum ixgbe_media_type media_type
;
255 /* Media type for I82598 is based on device ID */
256 switch (hw
->device_id
) {
257 case IXGBE_DEV_ID_82598
:
258 case IXGBE_DEV_ID_82598_BX
:
259 media_type
= ixgbe_media_type_backplane
;
261 case IXGBE_DEV_ID_82598AF_DUAL_PORT
:
262 case IXGBE_DEV_ID_82598AF_SINGLE_PORT
:
263 case IXGBE_DEV_ID_82598EB_CX4
:
264 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT
:
265 case IXGBE_DEV_ID_82598_DA_DUAL_PORT
:
266 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM
:
267 case IXGBE_DEV_ID_82598EB_XF_LR
:
268 case IXGBE_DEV_ID_82598EB_SFP_LOM
:
269 media_type
= ixgbe_media_type_fiber
;
271 case IXGBE_DEV_ID_82598AT
:
272 media_type
= ixgbe_media_type_copper
;
275 media_type
= ixgbe_media_type_unknown
;
283 * ixgbe_fc_enable_82598 - Enable flow control
284 * @hw: pointer to hardware structure
285 * @packetbuf_num: packet buffer number (0-7)
287 * Enable flow control according to the current settings.
289 static s32
ixgbe_fc_enable_82598(struct ixgbe_hw
*hw
, s32 packetbuf_num
)
296 fctrl_reg
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
297 fctrl_reg
&= ~(IXGBE_FCTRL_RFCE
| IXGBE_FCTRL_RPFCE
);
299 rmcs_reg
= IXGBE_READ_REG(hw
, IXGBE_RMCS
);
300 rmcs_reg
&= ~(IXGBE_RMCS_TFCE_PRIORITY
| IXGBE_RMCS_TFCE_802_3X
);
303 * The possible values of fc.current_mode are:
304 * 0: Flow control is completely disabled
305 * 1: Rx flow control is enabled (we can receive pause frames,
306 * but not send pause frames).
307 * 2: Tx flow control is enabled (we can send pause frames but
308 * we do not support receiving pause frames).
309 * 3: Both Rx and Tx flow control (symmetric) are enabled.
312 switch (hw
->fc
.current_mode
) {
314 /* Flow control completely disabled by software override. */
316 case ixgbe_fc_rx_pause
:
318 * Rx Flow control is enabled and Tx Flow control is
319 * disabled by software override. Since there really
320 * isn't a way to advertise that we are capable of RX
321 * Pause ONLY, we will advertise that we support both
322 * symmetric and asymmetric Rx PAUSE. Later, we will
323 * disable the adapter's ability to send PAUSE frames.
325 fctrl_reg
|= IXGBE_FCTRL_RFCE
;
327 case ixgbe_fc_tx_pause
:
329 * Tx Flow control is enabled, and Rx Flow control is
330 * disabled by software override.
332 rmcs_reg
|= IXGBE_RMCS_TFCE_802_3X
;
335 /* Flow control (both Rx and Tx) is enabled by SW override. */
336 fctrl_reg
|= IXGBE_FCTRL_RFCE
;
337 rmcs_reg
|= IXGBE_RMCS_TFCE_802_3X
;
340 hw_dbg(hw
, "Flow control param set incorrectly\n");
341 ret_val
= -IXGBE_ERR_CONFIG
;
346 /* Enable 802.3x based flow control settings. */
347 fctrl_reg
|= IXGBE_FCTRL_DPF
;
348 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl_reg
);
349 IXGBE_WRITE_REG(hw
, IXGBE_RMCS
, rmcs_reg
);
351 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
352 if (hw
->fc
.current_mode
& ixgbe_fc_tx_pause
) {
353 if (hw
->fc
.send_xon
) {
354 IXGBE_WRITE_REG(hw
, IXGBE_FCRTL(packetbuf_num
),
355 (hw
->fc
.low_water
| IXGBE_FCRTL_XONE
));
357 IXGBE_WRITE_REG(hw
, IXGBE_FCRTL(packetbuf_num
),
361 IXGBE_WRITE_REG(hw
, IXGBE_FCRTH(packetbuf_num
),
362 (hw
->fc
.high_water
| IXGBE_FCRTH_FCEN
));
365 /* Configure pause time (2 TCs per register) */
366 reg
= IXGBE_READ_REG(hw
, IXGBE_FCTTV(packetbuf_num
/ 2));
367 if ((packetbuf_num
& 1) == 0)
368 reg
= (reg
& 0xFFFF0000) | hw
->fc
.pause_time
;
370 reg
= (reg
& 0x0000FFFF) | (hw
->fc
.pause_time
<< 16);
371 IXGBE_WRITE_REG(hw
, IXGBE_FCTTV(packetbuf_num
/ 2), reg
);
373 IXGBE_WRITE_REG(hw
, IXGBE_FCRTV
, (hw
->fc
.pause_time
>> 1));
380 * ixgbe_setup_fc_82598 - Configure flow control settings
381 * @hw: pointer to hardware structure
382 * @packetbuf_num: packet buffer number (0-7)
384 * Configures the flow control settings based on SW configuration. This
385 * function is used for 802.3x flow control configuration only.
387 static s32
ixgbe_setup_fc_82598(struct ixgbe_hw
*hw
, s32 packetbuf_num
)
390 ixgbe_link_speed speed
;
393 /* Validate the packetbuf configuration */
394 if (packetbuf_num
< 0 || packetbuf_num
> 7) {
395 hw_dbg(hw
, "Invalid packet buffer number [%d], expected range is"
396 " 0-7\n", packetbuf_num
);
397 ret_val
= IXGBE_ERR_INVALID_LINK_SETTINGS
;
402 * Validate the water mark configuration. Zero water marks are invalid
403 * because it causes the controller to just blast out fc packets.
405 if (!hw
->fc
.low_water
|| !hw
->fc
.high_water
|| !hw
->fc
.pause_time
) {
406 if (hw
->fc
.requested_mode
!= ixgbe_fc_none
) {
407 hw_dbg(hw
, "Invalid water mark configuration\n");
408 ret_val
= IXGBE_ERR_INVALID_LINK_SETTINGS
;
414 * Validate the requested mode. Strict IEEE mode does not allow
415 * ixgbe_fc_rx_pause because it will cause testing anomalies.
417 if (hw
->fc
.strict_ieee
&& hw
->fc
.requested_mode
== ixgbe_fc_rx_pause
) {
418 hw_dbg(hw
, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
419 ret_val
= IXGBE_ERR_INVALID_LINK_SETTINGS
;
424 * 10gig parts do not have a word in the EEPROM to determine the
425 * default flow control setting, so we explicitly set it to full.
427 if (hw
->fc
.requested_mode
== ixgbe_fc_default
)
428 hw
->fc
.requested_mode
= ixgbe_fc_full
;
431 * Save off the requested flow control mode for use later. Depending
432 * on the link partner's capabilities, we may or may not use this mode.
435 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
437 /* Decide whether to use autoneg or not. */
438 hw
->mac
.ops
.check_link(hw
, &speed
, &link_up
, false);
439 if (!hw
->fc
.disable_fc_autoneg
&& hw
->phy
.multispeed_fiber
&&
440 (speed
== IXGBE_LINK_SPEED_1GB_FULL
))
441 ret_val
= ixgbe_fc_autoneg(hw
);
446 ret_val
= ixgbe_fc_enable_82598(hw
, packetbuf_num
);
453 * ixgbe_setup_mac_link_82598 - Configures MAC link settings
454 * @hw: pointer to hardware structure
456 * Configures link settings based on values in the ixgbe_hw struct.
457 * Restarts the link. Performs autonegotiation if needed.
459 static s32
ixgbe_setup_mac_link_82598(struct ixgbe_hw
*hw
)
467 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
468 autoc_reg
|= IXGBE_AUTOC_AN_RESTART
;
469 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc_reg
);
471 /* Only poll for autoneg to complete if specified to do so */
472 if (hw
->phy
.autoneg_wait_to_complete
) {
473 if ((autoc_reg
& IXGBE_AUTOC_LMS_MASK
) ==
474 IXGBE_AUTOC_LMS_KX4_AN
||
475 (autoc_reg
& IXGBE_AUTOC_LMS_MASK
) ==
476 IXGBE_AUTOC_LMS_KX4_AN_1G_AN
) {
477 links_reg
= 0; /* Just in case Autoneg time = 0 */
478 for (i
= 0; i
< IXGBE_AUTO_NEG_TIME
; i
++) {
479 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
480 if (links_reg
& IXGBE_LINKS_KX_AN_COMP
)
484 if (!(links_reg
& IXGBE_LINKS_KX_AN_COMP
)) {
485 status
= IXGBE_ERR_AUTONEG_NOT_COMPLETE
;
486 hw_dbg(hw
, "Autonegotiation did not complete.\n");
492 * We want to save off the original Flow Control configuration just in
493 * case we get disconnected and then reconnected into a different hub
494 * or switch with different Flow Control capabilities.
496 ixgbe_setup_fc_82598(hw
, 0);
498 /* Add delay to filter out noises during initial link setup */
505 * ixgbe_check_mac_link_82598 - Get link/speed status
506 * @hw: pointer to hardware structure
507 * @speed: pointer to link speed
508 * @link_up: true is link is up, false otherwise
509 * @link_up_wait_to_complete: bool used to wait for link up or not
511 * Reads the links register to determine if link is up and the current speed
513 static s32
ixgbe_check_mac_link_82598(struct ixgbe_hw
*hw
,
514 ixgbe_link_speed
*speed
, bool *link_up
,
515 bool link_up_wait_to_complete
)
519 u16 link_reg
, adapt_comp_reg
;
522 * SERDES PHY requires us to read link status from register 0xC79F.
523 * Bit 0 set indicates link is up/ready; clear indicates link down.
524 * 0xC00C is read to check that the XAUI lanes are active. Bit 0
525 * clear indicates active; set indicates inactive.
527 if (hw
->phy
.type
== ixgbe_phy_nl
) {
528 hw
->phy
.ops
.read_reg(hw
, 0xC79F, MDIO_MMD_PMAPMD
, &link_reg
);
529 hw
->phy
.ops
.read_reg(hw
, 0xC79F, MDIO_MMD_PMAPMD
, &link_reg
);
530 hw
->phy
.ops
.read_reg(hw
, 0xC00C, MDIO_MMD_PMAPMD
,
532 if (link_up_wait_to_complete
) {
533 for (i
= 0; i
< IXGBE_LINK_UP_TIME
; i
++) {
534 if ((link_reg
& 1) &&
535 ((adapt_comp_reg
& 1) == 0)) {
542 hw
->phy
.ops
.read_reg(hw
, 0xC79F,
545 hw
->phy
.ops
.read_reg(hw
, 0xC00C,
550 if ((link_reg
& 1) && ((adapt_comp_reg
& 1) == 0))
556 if (*link_up
== false)
560 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
561 if (link_up_wait_to_complete
) {
562 for (i
= 0; i
< IXGBE_LINK_UP_TIME
; i
++) {
563 if (links_reg
& IXGBE_LINKS_UP
) {
570 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
573 if (links_reg
& IXGBE_LINKS_UP
)
579 if (links_reg
& IXGBE_LINKS_SPEED
)
580 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
582 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
590 * ixgbe_setup_mac_link_speed_82598 - Set MAC link speed
591 * @hw: pointer to hardware structure
592 * @speed: new link speed
593 * @autoneg: true if auto-negotiation enabled
594 * @autoneg_wait_to_complete: true if waiting is needed to complete
596 * Set the link speed in the AUTOC register and restarts link.
598 static s32
ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw
*hw
,
599 ixgbe_link_speed speed
, bool autoneg
,
600 bool autoneg_wait_to_complete
)
603 ixgbe_link_speed link_capabilities
= IXGBE_LINK_SPEED_UNKNOWN
;
604 u32 curr_autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
605 u32 autoc
= curr_autoc
;
606 u32 link_mode
= autoc
& IXGBE_AUTOC_LMS_MASK
;
608 /* Check to see if speed passed in is supported. */
609 ixgbe_get_link_capabilities_82598(hw
, &link_capabilities
, &autoneg
);
610 speed
&= link_capabilities
;
612 if (speed
== IXGBE_LINK_SPEED_UNKNOWN
)
613 status
= IXGBE_ERR_LINK_SETUP
;
615 /* Set KX4/KX support according to speed requested */
616 else if (link_mode
== IXGBE_AUTOC_LMS_KX4_AN
||
617 link_mode
== IXGBE_AUTOC_LMS_KX4_AN_1G_AN
) {
618 autoc
&= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK
;
619 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
620 autoc
|= IXGBE_AUTOC_KX4_SUPP
;
621 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
622 autoc
|= IXGBE_AUTOC_KX_SUPP
;
623 if (autoc
!= curr_autoc
)
624 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc
);
628 hw
->phy
.autoneg_wait_to_complete
= autoneg_wait_to_complete
;
631 * Setup and restart the link based on the new values in
632 * ixgbe_hw This will write the AUTOC register based on the new
635 status
= ixgbe_setup_mac_link_82598(hw
);
643 * ixgbe_setup_copper_link_82598 - Setup copper link settings
644 * @hw: pointer to hardware structure
646 * Configures link settings based on values in the ixgbe_hw struct.
647 * Restarts the link. Performs autonegotiation if needed. Restart
648 * phy and wait for autonegotiate to finish. Then synchronize the
651 static s32
ixgbe_setup_copper_link_82598(struct ixgbe_hw
*hw
)
655 /* Restart autonegotiation on PHY */
656 status
= hw
->phy
.ops
.setup_link(hw
);
659 ixgbe_setup_mac_link_82598(hw
);
665 * ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field
666 * @hw: pointer to hardware structure
667 * @speed: new link speed
668 * @autoneg: true if autonegotiation enabled
669 * @autoneg_wait_to_complete: true if waiting is needed to complete
671 * Sets the link speed in the AUTOC register in the MAC and restarts link.
673 static s32
ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw
*hw
,
674 ixgbe_link_speed speed
,
676 bool autoneg_wait_to_complete
)
680 /* Setup the PHY according to input speed */
681 status
= hw
->phy
.ops
.setup_link_speed(hw
, speed
, autoneg
,
682 autoneg_wait_to_complete
);
685 ixgbe_setup_mac_link_82598(hw
);
691 * ixgbe_reset_hw_82598 - Performs hardware reset
692 * @hw: pointer to hardware structure
694 * Resets the hardware by resetting the transmit and receive units, masks and
695 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
698 static s32
ixgbe_reset_hw_82598(struct ixgbe_hw
*hw
)
707 /* Call adapter stop to disable tx/rx and clear interrupts */
708 hw
->mac
.ops
.stop_adapter(hw
);
711 * Power up the Atlas Tx lanes if they are currently powered down.
712 * Atlas Tx lanes are powered down for MAC loopback tests, but
713 * they are not automatically restored on reset.
715 hw
->mac
.ops
.read_analog_reg8(hw
, IXGBE_ATLAS_PDN_LPBK
, &analog_val
);
716 if (analog_val
& IXGBE_ATLAS_PDN_TX_REG_EN
) {
717 /* Enable Tx Atlas so packets can be transmitted again */
718 hw
->mac
.ops
.read_analog_reg8(hw
, IXGBE_ATLAS_PDN_LPBK
,
720 analog_val
&= ~IXGBE_ATLAS_PDN_TX_REG_EN
;
721 hw
->mac
.ops
.write_analog_reg8(hw
, IXGBE_ATLAS_PDN_LPBK
,
724 hw
->mac
.ops
.read_analog_reg8(hw
, IXGBE_ATLAS_PDN_10G
,
726 analog_val
&= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL
;
727 hw
->mac
.ops
.write_analog_reg8(hw
, IXGBE_ATLAS_PDN_10G
,
730 hw
->mac
.ops
.read_analog_reg8(hw
, IXGBE_ATLAS_PDN_1G
,
732 analog_val
&= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL
;
733 hw
->mac
.ops
.write_analog_reg8(hw
, IXGBE_ATLAS_PDN_1G
,
736 hw
->mac
.ops
.read_analog_reg8(hw
, IXGBE_ATLAS_PDN_AN
,
738 analog_val
&= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL
;
739 hw
->mac
.ops
.write_analog_reg8(hw
, IXGBE_ATLAS_PDN_AN
,
744 if (hw
->phy
.reset_disable
== false) {
745 /* PHY ops must be identified and initialized prior to reset */
747 /* Init PHY and function pointers, perform SFP setup */
748 status
= hw
->phy
.ops
.init(hw
);
749 if (status
== IXGBE_ERR_SFP_NOT_SUPPORTED
)
752 hw
->phy
.ops
.reset(hw
);
756 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
757 * access and verify no pending requests before reset
759 status
= ixgbe_disable_pcie_master(hw
);
761 status
= IXGBE_ERR_MASTER_REQUESTS_PENDING
;
762 hw_dbg(hw
, "PCI-E Master disable polling has failed.\n");
766 * Issue global reset to the MAC. This needs to be a SW reset.
767 * If link reset is used, it might reset the MAC when mng is using it
769 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
770 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, (ctrl
| IXGBE_CTRL_RST
));
771 IXGBE_WRITE_FLUSH(hw
);
773 /* Poll for reset bit to self-clear indicating reset is complete */
774 for (i
= 0; i
< 10; i
++) {
776 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
777 if (!(ctrl
& IXGBE_CTRL_RST
))
780 if (ctrl
& IXGBE_CTRL_RST
) {
781 status
= IXGBE_ERR_RESET_FAILED
;
782 hw_dbg(hw
, "Reset polling failed to complete.\n");
787 gheccr
= IXGBE_READ_REG(hw
, IXGBE_GHECCR
);
788 gheccr
&= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
789 IXGBE_WRITE_REG(hw
, IXGBE_GHECCR
, gheccr
);
792 * Store the original AUTOC value if it has not been
793 * stored off yet. Otherwise restore the stored original
794 * AUTOC value since the reset operation sets back to deaults.
796 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
797 if (hw
->mac
.orig_link_settings_stored
== false) {
798 hw
->mac
.orig_autoc
= autoc
;
799 hw
->mac
.orig_link_settings_stored
= true;
800 } else if (autoc
!= hw
->mac
.orig_autoc
) {
801 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, hw
->mac
.orig_autoc
);
805 * Store MAC address from RAR0, clear receive address registers, and
806 * clear the multicast table
808 hw
->mac
.ops
.init_rx_addrs(hw
);
810 /* Store the permanent mac address */
811 hw
->mac
.ops
.get_mac_addr(hw
, hw
->mac
.perm_addr
);
818 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
819 * @hw: pointer to hardware struct
820 * @rar: receive address register index to associate with a VMDq index
821 * @vmdq: VMDq set index
823 static s32
ixgbe_set_vmdq_82598(struct ixgbe_hw
*hw
, u32 rar
, u32 vmdq
)
827 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(rar
));
828 rar_high
&= ~IXGBE_RAH_VIND_MASK
;
829 rar_high
|= ((vmdq
<< IXGBE_RAH_VIND_SHIFT
) & IXGBE_RAH_VIND_MASK
);
830 IXGBE_WRITE_REG(hw
, IXGBE_RAH(rar
), rar_high
);
835 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
836 * @hw: pointer to hardware struct
837 * @rar: receive address register index to associate with a VMDq index
838 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
840 static s32
ixgbe_clear_vmdq_82598(struct ixgbe_hw
*hw
, u32 rar
, u32 vmdq
)
843 u32 rar_entries
= hw
->mac
.num_rar_entries
;
845 if (rar
< rar_entries
) {
846 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(rar
));
847 if (rar_high
& IXGBE_RAH_VIND_MASK
) {
848 rar_high
&= ~IXGBE_RAH_VIND_MASK
;
849 IXGBE_WRITE_REG(hw
, IXGBE_RAH(rar
), rar_high
);
852 hw_dbg(hw
, "RAR index %d is out of range.\n", rar
);
859 * ixgbe_set_vfta_82598 - Set VLAN filter table
860 * @hw: pointer to hardware structure
861 * @vlan: VLAN id to write to VLAN filter
862 * @vind: VMDq output index that maps queue to VLAN id in VFTA
863 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
865 * Turn on/off specified VLAN in the VLAN filter table.
867 static s32
ixgbe_set_vfta_82598(struct ixgbe_hw
*hw
, u32 vlan
, u32 vind
,
876 return IXGBE_ERR_PARAM
;
878 /* Determine 32-bit word position in array */
879 regindex
= (vlan
>> 5) & 0x7F; /* upper seven bits */
881 /* Determine the location of the (VMD) queue index */
882 vftabyte
= ((vlan
>> 3) & 0x03); /* bits (4:3) indicating byte array */
883 bitindex
= (vlan
& 0x7) << 2; /* lower 3 bits indicate nibble */
885 /* Set the nibble for VMD queue index */
886 bits
= IXGBE_READ_REG(hw
, IXGBE_VFTAVIND(vftabyte
, regindex
));
887 bits
&= (~(0x0F << bitindex
));
888 bits
|= (vind
<< bitindex
);
889 IXGBE_WRITE_REG(hw
, IXGBE_VFTAVIND(vftabyte
, regindex
), bits
);
891 /* Determine the location of the bit for this VLAN id */
892 bitindex
= vlan
& 0x1F; /* lower five bits */
894 bits
= IXGBE_READ_REG(hw
, IXGBE_VFTA(regindex
));
896 /* Turn on this VLAN id */
897 bits
|= (1 << bitindex
);
899 /* Turn off this VLAN id */
900 bits
&= ~(1 << bitindex
);
901 IXGBE_WRITE_REG(hw
, IXGBE_VFTA(regindex
), bits
);
907 * ixgbe_clear_vfta_82598 - Clear VLAN filter table
908 * @hw: pointer to hardware structure
910 * Clears the VLAN filer table, and the VMDq index associated with the filter
912 static s32
ixgbe_clear_vfta_82598(struct ixgbe_hw
*hw
)
917 for (offset
= 0; offset
< hw
->mac
.vft_size
; offset
++)
918 IXGBE_WRITE_REG(hw
, IXGBE_VFTA(offset
), 0);
920 for (vlanbyte
= 0; vlanbyte
< 4; vlanbyte
++)
921 for (offset
= 0; offset
< hw
->mac
.vft_size
; offset
++)
922 IXGBE_WRITE_REG(hw
, IXGBE_VFTAVIND(vlanbyte
, offset
),
929 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
930 * @hw: pointer to hardware structure
931 * @reg: analog register to read
934 * Performs read operation to Atlas analog register specified.
936 static s32
ixgbe_read_analog_reg8_82598(struct ixgbe_hw
*hw
, u32 reg
, u8
*val
)
940 IXGBE_WRITE_REG(hw
, IXGBE_ATLASCTL
,
941 IXGBE_ATLASCTL_WRITE_CMD
| (reg
<< 8));
942 IXGBE_WRITE_FLUSH(hw
);
944 atlas_ctl
= IXGBE_READ_REG(hw
, IXGBE_ATLASCTL
);
945 *val
= (u8
)atlas_ctl
;
951 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
952 * @hw: pointer to hardware structure
953 * @reg: atlas register to write
954 * @val: value to write
956 * Performs write operation to Atlas analog register specified.
958 static s32
ixgbe_write_analog_reg8_82598(struct ixgbe_hw
*hw
, u32 reg
, u8 val
)
962 atlas_ctl
= (reg
<< 8) | val
;
963 IXGBE_WRITE_REG(hw
, IXGBE_ATLASCTL
, atlas_ctl
);
964 IXGBE_WRITE_FLUSH(hw
);
971 * ixgbe_read_i2c_eeprom_82598 - Read 8 bit EEPROM word of an SFP+ module
972 * over I2C interface through an intermediate phy.
973 * @hw: pointer to hardware structure
974 * @byte_offset: EEPROM byte offset to read
975 * @eeprom_data: value read
977 * Performs byte read operation to SFP module's EEPROM over I2C interface.
979 static s32
ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw
*hw
, u8 byte_offset
,
988 if (hw
->phy
.type
== ixgbe_phy_nl
) {
990 * phy SDA/SCL registers are at addresses 0xC30A to
991 * 0xC30D. These registers are used to talk to the SFP+
992 * module's EEPROM through the SDA/SCL (I2C) interface.
994 sfp_addr
= (IXGBE_I2C_EEPROM_DEV_ADDR
<< 8) + byte_offset
;
995 sfp_addr
= (sfp_addr
| IXGBE_I2C_EEPROM_READ_MASK
);
996 hw
->phy
.ops
.write_reg(hw
,
997 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR
,
1002 for (i
= 0; i
< 100; i
++) {
1003 hw
->phy
.ops
.read_reg(hw
,
1004 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT
,
1007 sfp_stat
= sfp_stat
& IXGBE_I2C_EEPROM_STATUS_MASK
;
1008 if (sfp_stat
!= IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS
)
1013 if (sfp_stat
!= IXGBE_I2C_EEPROM_STATUS_PASS
) {
1014 hw_dbg(hw
, "EEPROM read did not pass.\n");
1015 status
= IXGBE_ERR_SFP_NOT_PRESENT
;
1020 hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA
,
1021 MDIO_MMD_PMAPMD
, &sfp_data
);
1023 *eeprom_data
= (u8
)(sfp_data
>> 8);
1025 status
= IXGBE_ERR_PHY
;
1034 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1035 * @hw: pointer to hardware structure
1037 * Determines physical layer capabilities of the current configuration.
1039 static u32
ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw
*hw
)
1041 u32 physical_layer
= IXGBE_PHYSICAL_LAYER_UNKNOWN
;
1042 u32 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
1043 u32 pma_pmd_10g
= autoc
& IXGBE_AUTOC_10G_PMA_PMD_MASK
;
1044 u32 pma_pmd_1g
= autoc
& IXGBE_AUTOC_1G_PMA_PMD_MASK
;
1045 u16 ext_ability
= 0;
1047 hw
->phy
.ops
.identify(hw
);
1049 /* Copper PHY must be checked before AUTOC LMS to determine correct
1050 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
1051 if (hw
->phy
.type
== ixgbe_phy_tn
||
1052 hw
->phy
.type
== ixgbe_phy_cu_unknown
) {
1053 hw
->phy
.ops
.read_reg(hw
, MDIO_PMA_EXTABLE
, MDIO_MMD_PMAPMD
,
1055 if (ext_ability
& MDIO_PMA_EXTABLE_10GBT
)
1056 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_T
;
1057 if (ext_ability
& MDIO_PMA_EXTABLE_1000BT
)
1058 physical_layer
|= IXGBE_PHYSICAL_LAYER_1000BASE_T
;
1059 if (ext_ability
& MDIO_PMA_EXTABLE_100BTX
)
1060 physical_layer
|= IXGBE_PHYSICAL_LAYER_100BASE_TX
;
1064 switch (autoc
& IXGBE_AUTOC_LMS_MASK
) {
1065 case IXGBE_AUTOC_LMS_1G_AN
:
1066 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN
:
1067 if (pma_pmd_1g
== IXGBE_AUTOC_1G_KX
)
1068 physical_layer
= IXGBE_PHYSICAL_LAYER_1000BASE_KX
;
1070 physical_layer
= IXGBE_PHYSICAL_LAYER_1000BASE_BX
;
1072 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN
:
1073 if (pma_pmd_10g
== IXGBE_AUTOC_10G_CX4
)
1074 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_CX4
;
1075 else if (pma_pmd_10g
== IXGBE_AUTOC_10G_KX4
)
1076 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_KX4
;
1078 physical_layer
= IXGBE_PHYSICAL_LAYER_UNKNOWN
;
1080 case IXGBE_AUTOC_LMS_KX4_AN
:
1081 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN
:
1082 if (autoc
& IXGBE_AUTOC_KX_SUPP
)
1083 physical_layer
|= IXGBE_PHYSICAL_LAYER_1000BASE_KX
;
1084 if (autoc
& IXGBE_AUTOC_KX4_SUPP
)
1085 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_KX4
;
1091 if (hw
->phy
.type
== ixgbe_phy_nl
) {
1092 hw
->phy
.ops
.identify_sfp(hw
);
1094 switch (hw
->phy
.sfp_type
) {
1095 case ixgbe_sfp_type_da_cu
:
1096 physical_layer
= IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU
;
1098 case ixgbe_sfp_type_sr
:
1099 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_SR
;
1101 case ixgbe_sfp_type_lr
:
1102 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_LR
;
1105 physical_layer
= IXGBE_PHYSICAL_LAYER_UNKNOWN
;
1110 switch (hw
->device_id
) {
1111 case IXGBE_DEV_ID_82598_DA_DUAL_PORT
:
1112 physical_layer
= IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU
;
1114 case IXGBE_DEV_ID_82598AF_DUAL_PORT
:
1115 case IXGBE_DEV_ID_82598AF_SINGLE_PORT
:
1116 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM
:
1117 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_SR
;
1119 case IXGBE_DEV_ID_82598EB_XF_LR
:
1120 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_LR
;
1127 return physical_layer
;
1130 static struct ixgbe_mac_operations mac_ops_82598
= {
1131 .init_hw
= &ixgbe_init_hw_generic
,
1132 .reset_hw
= &ixgbe_reset_hw_82598
,
1133 .start_hw
= &ixgbe_start_hw_generic
,
1134 .clear_hw_cntrs
= &ixgbe_clear_hw_cntrs_generic
,
1135 .get_media_type
= &ixgbe_get_media_type_82598
,
1136 .get_supported_physical_layer
= &ixgbe_get_supported_physical_layer_82598
,
1137 .enable_rx_dma
= &ixgbe_enable_rx_dma_generic
,
1138 .get_mac_addr
= &ixgbe_get_mac_addr_generic
,
1139 .stop_adapter
= &ixgbe_stop_adapter_generic
,
1140 .get_bus_info
= &ixgbe_get_bus_info_generic
,
1141 .set_lan_id
= &ixgbe_set_lan_id_multi_port_pcie
,
1142 .read_analog_reg8
= &ixgbe_read_analog_reg8_82598
,
1143 .write_analog_reg8
= &ixgbe_write_analog_reg8_82598
,
1144 .setup_link
= &ixgbe_setup_mac_link_82598
,
1145 .setup_link_speed
= &ixgbe_setup_mac_link_speed_82598
,
1146 .check_link
= &ixgbe_check_mac_link_82598
,
1147 .get_link_capabilities
= &ixgbe_get_link_capabilities_82598
,
1148 .led_on
= &ixgbe_led_on_generic
,
1149 .led_off
= &ixgbe_led_off_generic
,
1150 .blink_led_start
= &ixgbe_blink_led_start_generic
,
1151 .blink_led_stop
= &ixgbe_blink_led_stop_generic
,
1152 .set_rar
= &ixgbe_set_rar_generic
,
1153 .clear_rar
= &ixgbe_clear_rar_generic
,
1154 .set_vmdq
= &ixgbe_set_vmdq_82598
,
1155 .clear_vmdq
= &ixgbe_clear_vmdq_82598
,
1156 .init_rx_addrs
= &ixgbe_init_rx_addrs_generic
,
1157 .update_uc_addr_list
= &ixgbe_update_uc_addr_list_generic
,
1158 .update_mc_addr_list
= &ixgbe_update_mc_addr_list_generic
,
1159 .enable_mc
= &ixgbe_enable_mc_generic
,
1160 .disable_mc
= &ixgbe_disable_mc_generic
,
1161 .clear_vfta
= &ixgbe_clear_vfta_82598
,
1162 .set_vfta
= &ixgbe_set_vfta_82598
,
1163 .setup_fc
= &ixgbe_setup_fc_82598
,
1166 static struct ixgbe_eeprom_operations eeprom_ops_82598
= {
1167 .init_params
= &ixgbe_init_eeprom_params_generic
,
1168 .read
= &ixgbe_read_eeprom_generic
,
1169 .validate_checksum
= &ixgbe_validate_eeprom_checksum_generic
,
1170 .update_checksum
= &ixgbe_update_eeprom_checksum_generic
,
1173 static struct ixgbe_phy_operations phy_ops_82598
= {
1174 .identify
= &ixgbe_identify_phy_generic
,
1175 .identify_sfp
= &ixgbe_identify_sfp_module_generic
,
1176 .init
= &ixgbe_init_phy_ops_82598
,
1177 .reset
= &ixgbe_reset_phy_generic
,
1178 .read_reg
= &ixgbe_read_phy_reg_generic
,
1179 .write_reg
= &ixgbe_write_phy_reg_generic
,
1180 .setup_link
= &ixgbe_setup_phy_link_generic
,
1181 .setup_link_speed
= &ixgbe_setup_phy_link_speed_generic
,
1182 .read_i2c_eeprom
= &ixgbe_read_i2c_eeprom_82598
,
1185 struct ixgbe_info ixgbe_82598_info
= {
1186 .mac
= ixgbe_mac_82598EB
,
1187 .get_invariants
= &ixgbe_get_invariants_82598
,
1188 .mac_ops
= &mac_ops_82598
,
1189 .eeprom_ops
= &eeprom_ops_82598
,
1190 .phy_ops
= &phy_ops_82598
,