1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
33 #include "ixgbe_phy.h"
34 #include "ixgbe_mbx.h"
36 #define IXGBE_82599_MAX_TX_QUEUES 128
37 #define IXGBE_82599_MAX_RX_QUEUES 128
38 #define IXGBE_82599_RAR_ENTRIES 128
39 #define IXGBE_82599_MC_TBL_SIZE 128
40 #define IXGBE_82599_VFT_TBL_SIZE 128
41 #define IXGBE_82599_RX_PB_SIZE 512
43 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
);
44 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
);
45 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
);
46 static s32
ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw
*hw
,
47 ixgbe_link_speed speed
,
49 bool autoneg_wait_to_complete
);
50 static s32
ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw
*hw
,
51 ixgbe_link_speed speed
,
53 bool autoneg_wait_to_complete
);
54 static s32
ixgbe_start_mac_link_82599(struct ixgbe_hw
*hw
,
55 bool autoneg_wait_to_complete
);
56 static s32
ixgbe_setup_mac_link_82599(struct ixgbe_hw
*hw
,
57 ixgbe_link_speed speed
,
59 bool autoneg_wait_to_complete
);
60 static s32
ixgbe_setup_copper_link_82599(struct ixgbe_hw
*hw
,
61 ixgbe_link_speed speed
,
63 bool autoneg_wait_to_complete
);
64 static s32
ixgbe_verify_fw_version_82599(struct ixgbe_hw
*hw
);
65 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw
*hw
);
67 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw
*hw
)
69 struct ixgbe_mac_info
*mac
= &hw
->mac
;
71 /* enable the laser control functions for SFP+ fiber */
72 if (mac
->ops
.get_media_type(hw
) == ixgbe_media_type_fiber
) {
73 mac
->ops
.disable_tx_laser
=
74 &ixgbe_disable_tx_laser_multispeed_fiber
;
75 mac
->ops
.enable_tx_laser
=
76 &ixgbe_enable_tx_laser_multispeed_fiber
;
77 mac
->ops
.flap_tx_laser
= &ixgbe_flap_tx_laser_multispeed_fiber
;
79 mac
->ops
.disable_tx_laser
= NULL
;
80 mac
->ops
.enable_tx_laser
= NULL
;
81 mac
->ops
.flap_tx_laser
= NULL
;
84 if (hw
->phy
.multispeed_fiber
) {
85 /* Set up dual speed SFP+ support */
86 mac
->ops
.setup_link
= &ixgbe_setup_mac_link_multispeed_fiber
;
88 if ((mac
->ops
.get_media_type(hw
) ==
89 ixgbe_media_type_backplane
) &&
90 (hw
->phy
.smart_speed
== ixgbe_smart_speed_auto
||
91 hw
->phy
.smart_speed
== ixgbe_smart_speed_on
) &&
92 !ixgbe_verify_lesm_fw_enabled_82599(hw
))
93 mac
->ops
.setup_link
= &ixgbe_setup_mac_link_smartspeed
;
95 mac
->ops
.setup_link
= &ixgbe_setup_mac_link_82599
;
99 static s32
ixgbe_setup_sfp_modules_82599(struct ixgbe_hw
*hw
)
104 u16 list_offset
, data_offset
, data_value
;
106 if (hw
->phy
.sfp_type
!= ixgbe_sfp_type_unknown
) {
107 ixgbe_init_mac_link_ops_82599(hw
);
109 hw
->phy
.ops
.reset
= NULL
;
111 ret_val
= ixgbe_get_sfp_init_sequence_offsets(hw
, &list_offset
,
116 /* PHY config will finish before releasing the semaphore */
117 ret_val
= hw
->mac
.ops
.acquire_swfw_sync(hw
,
118 IXGBE_GSSR_MAC_CSR_SM
);
120 ret_val
= IXGBE_ERR_SWFW_SYNC
;
124 hw
->eeprom
.ops
.read(hw
, ++data_offset
, &data_value
);
125 while (data_value
!= 0xffff) {
126 IXGBE_WRITE_REG(hw
, IXGBE_CORECTL
, data_value
);
127 IXGBE_WRITE_FLUSH(hw
);
128 hw
->eeprom
.ops
.read(hw
, ++data_offset
, &data_value
);
131 /* Release the semaphore */
132 hw
->mac
.ops
.release_swfw_sync(hw
, IXGBE_GSSR_MAC_CSR_SM
);
134 * Delay obtaining semaphore again to allow FW access,
135 * semaphore_delay is in ms usleep_range needs us.
137 usleep_range(hw
->eeprom
.semaphore_delay
* 1000,
138 hw
->eeprom
.semaphore_delay
* 2000);
140 /* Now restart DSP by setting Restart_AN and clearing LMS */
141 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, ((IXGBE_READ_REG(hw
,
142 IXGBE_AUTOC
) & ~IXGBE_AUTOC_LMS_MASK
) |
143 IXGBE_AUTOC_AN_RESTART
));
145 /* Wait for AN to leave state 0 */
146 for (i
= 0; i
< 10; i
++) {
147 usleep_range(4000, 8000);
148 reg_anlp1
= IXGBE_READ_REG(hw
, IXGBE_ANLP1
);
149 if (reg_anlp1
& IXGBE_ANLP1_AN_STATE_MASK
)
152 if (!(reg_anlp1
& IXGBE_ANLP1_AN_STATE_MASK
)) {
153 hw_dbg(hw
, "sfp module setup not complete\n");
154 ret_val
= IXGBE_ERR_SFP_SETUP_NOT_COMPLETE
;
158 /* Restart DSP by setting Restart_AN and return to SFI mode */
159 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, (IXGBE_READ_REG(hw
,
160 IXGBE_AUTOC
) | IXGBE_AUTOC_LMS_10G_SERIAL
|
161 IXGBE_AUTOC_AN_RESTART
));
168 static s32
ixgbe_get_invariants_82599(struct ixgbe_hw
*hw
)
170 struct ixgbe_mac_info
*mac
= &hw
->mac
;
172 ixgbe_init_mac_link_ops_82599(hw
);
174 mac
->mcft_size
= IXGBE_82599_MC_TBL_SIZE
;
175 mac
->vft_size
= IXGBE_82599_VFT_TBL_SIZE
;
176 mac
->num_rar_entries
= IXGBE_82599_RAR_ENTRIES
;
177 mac
->max_rx_queues
= IXGBE_82599_MAX_RX_QUEUES
;
178 mac
->max_tx_queues
= IXGBE_82599_MAX_TX_QUEUES
;
179 mac
->max_msix_vectors
= ixgbe_get_pcie_msix_count_generic(hw
);
185 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
186 * @hw: pointer to hardware structure
188 * Initialize any function pointers that were not able to be
189 * set during get_invariants because the PHY/SFP type was
190 * not known. Perform the SFP init if necessary.
193 static s32
ixgbe_init_phy_ops_82599(struct ixgbe_hw
*hw
)
195 struct ixgbe_mac_info
*mac
= &hw
->mac
;
196 struct ixgbe_phy_info
*phy
= &hw
->phy
;
199 /* Identify the PHY or SFP module */
200 ret_val
= phy
->ops
.identify(hw
);
202 /* Setup function pointers based on detected SFP module and speeds */
203 ixgbe_init_mac_link_ops_82599(hw
);
205 /* If copper media, overwrite with copper function pointers */
206 if (mac
->ops
.get_media_type(hw
) == ixgbe_media_type_copper
) {
207 mac
->ops
.setup_link
= &ixgbe_setup_copper_link_82599
;
208 mac
->ops
.get_link_capabilities
=
209 &ixgbe_get_copper_link_capabilities_generic
;
212 /* Set necessary function pointers based on phy type */
213 switch (hw
->phy
.type
) {
215 phy
->ops
.check_link
= &ixgbe_check_phy_link_tnx
;
216 phy
->ops
.get_firmware_version
=
217 &ixgbe_get_phy_firmware_version_tnx
;
220 phy
->ops
.get_firmware_version
=
221 &ixgbe_get_phy_firmware_version_generic
;
231 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
232 * @hw: pointer to hardware structure
233 * @speed: pointer to link speed
234 * @negotiation: true when autoneg or autotry is enabled
236 * Determines the link capabilities by reading the AUTOC register.
238 static s32
ixgbe_get_link_capabilities_82599(struct ixgbe_hw
*hw
,
239 ixgbe_link_speed
*speed
,
245 /* Determine 1G link capabilities off of SFP+ type */
246 if (hw
->phy
.sfp_type
== ixgbe_sfp_type_1g_cu_core0
||
247 hw
->phy
.sfp_type
== ixgbe_sfp_type_1g_cu_core1
) {
248 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
254 * Determine link capabilities based on the stored value of AUTOC,
255 * which represents EEPROM defaults. If AUTOC value has not been
256 * stored, use the current register value.
258 if (hw
->mac
.orig_link_settings_stored
)
259 autoc
= hw
->mac
.orig_autoc
;
261 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
263 switch (autoc
& IXGBE_AUTOC_LMS_MASK
) {
264 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN
:
265 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
266 *negotiation
= false;
269 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN
:
270 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
271 *negotiation
= false;
274 case IXGBE_AUTOC_LMS_1G_AN
:
275 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
279 case IXGBE_AUTOC_LMS_10G_SERIAL
:
280 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
281 *negotiation
= false;
284 case IXGBE_AUTOC_LMS_KX4_KX_KR
:
285 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
:
286 *speed
= IXGBE_LINK_SPEED_UNKNOWN
;
287 if (autoc
& IXGBE_AUTOC_KR_SUPP
)
288 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
289 if (autoc
& IXGBE_AUTOC_KX4_SUPP
)
290 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
291 if (autoc
& IXGBE_AUTOC_KX_SUPP
)
292 *speed
|= IXGBE_LINK_SPEED_1GB_FULL
;
296 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
:
297 *speed
= IXGBE_LINK_SPEED_100_FULL
;
298 if (autoc
& IXGBE_AUTOC_KR_SUPP
)
299 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
300 if (autoc
& IXGBE_AUTOC_KX4_SUPP
)
301 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
302 if (autoc
& IXGBE_AUTOC_KX_SUPP
)
303 *speed
|= IXGBE_LINK_SPEED_1GB_FULL
;
307 case IXGBE_AUTOC_LMS_SGMII_1G_100M
:
308 *speed
= IXGBE_LINK_SPEED_1GB_FULL
| IXGBE_LINK_SPEED_100_FULL
;
309 *negotiation
= false;
313 status
= IXGBE_ERR_LINK_SETUP
;
318 if (hw
->phy
.multispeed_fiber
) {
319 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
|
320 IXGBE_LINK_SPEED_1GB_FULL
;
329 * ixgbe_get_media_type_82599 - Get media type
330 * @hw: pointer to hardware structure
332 * Returns the media type (fiber, copper, backplane)
334 static enum ixgbe_media_type
ixgbe_get_media_type_82599(struct ixgbe_hw
*hw
)
336 enum ixgbe_media_type media_type
;
338 /* Detect if there is a copper PHY attached. */
339 switch (hw
->phy
.type
) {
340 case ixgbe_phy_cu_unknown
:
343 media_type
= ixgbe_media_type_copper
;
349 switch (hw
->device_id
) {
350 case IXGBE_DEV_ID_82599_KX4
:
351 case IXGBE_DEV_ID_82599_KX4_MEZZ
:
352 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE
:
353 case IXGBE_DEV_ID_82599_KR
:
354 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE
:
355 case IXGBE_DEV_ID_82599_XAUI_LOM
:
356 /* Default device ID is mezzanine card KX/KX4 */
357 media_type
= ixgbe_media_type_backplane
;
359 case IXGBE_DEV_ID_82599_SFP
:
360 case IXGBE_DEV_ID_82599_SFP_FCOE
:
361 case IXGBE_DEV_ID_82599_SFP_EM
:
362 case IXGBE_DEV_ID_82599_SFP_SF2
:
363 media_type
= ixgbe_media_type_fiber
;
365 case IXGBE_DEV_ID_82599_CX4
:
366 media_type
= ixgbe_media_type_cx4
;
368 case IXGBE_DEV_ID_82599_T3_LOM
:
369 media_type
= ixgbe_media_type_copper
;
371 case IXGBE_DEV_ID_82599_LS
:
372 media_type
= ixgbe_media_type_fiber_lco
;
375 media_type
= ixgbe_media_type_unknown
;
383 * ixgbe_start_mac_link_82599 - Setup MAC link settings
384 * @hw: pointer to hardware structure
385 * @autoneg_wait_to_complete: true when waiting for completion is needed
387 * Configures link settings based on values in the ixgbe_hw struct.
388 * Restarts the link. Performs autonegotiation if needed.
390 static s32
ixgbe_start_mac_link_82599(struct ixgbe_hw
*hw
,
391 bool autoneg_wait_to_complete
)
399 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
400 autoc_reg
|= IXGBE_AUTOC_AN_RESTART
;
401 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc_reg
);
403 /* Only poll for autoneg to complete if specified to do so */
404 if (autoneg_wait_to_complete
) {
405 if ((autoc_reg
& IXGBE_AUTOC_LMS_MASK
) ==
406 IXGBE_AUTOC_LMS_KX4_KX_KR
||
407 (autoc_reg
& IXGBE_AUTOC_LMS_MASK
) ==
408 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
||
409 (autoc_reg
& IXGBE_AUTOC_LMS_MASK
) ==
410 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
) {
411 links_reg
= 0; /* Just in case Autoneg time = 0 */
412 for (i
= 0; i
< IXGBE_AUTO_NEG_TIME
; i
++) {
413 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
414 if (links_reg
& IXGBE_LINKS_KX_AN_COMP
)
418 if (!(links_reg
& IXGBE_LINKS_KX_AN_COMP
)) {
419 status
= IXGBE_ERR_AUTONEG_NOT_COMPLETE
;
420 hw_dbg(hw
, "Autoneg did not complete.\n");
425 /* Add delay to filter out noises during initial link setup */
432 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
433 * @hw: pointer to hardware structure
435 * The base drivers may require better control over SFP+ module
436 * PHY states. This includes selectively shutting down the Tx
437 * laser on the PHY, effectively halting physical link.
439 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
)
441 u32 esdp_reg
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
443 /* Disable tx laser; allow 100us to go dark per spec */
444 esdp_reg
|= IXGBE_ESDP_SDP3
;
445 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
446 IXGBE_WRITE_FLUSH(hw
);
451 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
452 * @hw: pointer to hardware structure
454 * The base drivers may require better control over SFP+ module
455 * PHY states. This includes selectively turning on the Tx
456 * laser on the PHY, effectively starting physical link.
458 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
)
460 u32 esdp_reg
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
462 /* Enable tx laser; allow 100ms to light up */
463 esdp_reg
&= ~IXGBE_ESDP_SDP3
;
464 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
465 IXGBE_WRITE_FLUSH(hw
);
470 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
471 * @hw: pointer to hardware structure
473 * When the driver changes the link speeds that it can support,
474 * it sets autotry_restart to true to indicate that we need to
475 * initiate a new autotry session with the link partner. To do
476 * so, we set the speed then disable and re-enable the tx laser, to
477 * alert the link partner that it also needs to restart autotry on its
478 * end. This is consistent with true clause 37 autoneg, which also
479 * involves a loss of signal.
481 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
)
483 if (hw
->mac
.autotry_restart
) {
484 ixgbe_disable_tx_laser_multispeed_fiber(hw
);
485 ixgbe_enable_tx_laser_multispeed_fiber(hw
);
486 hw
->mac
.autotry_restart
= false;
491 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
492 * @hw: pointer to hardware structure
493 * @speed: new link speed
494 * @autoneg: true if autonegotiation enabled
495 * @autoneg_wait_to_complete: true when waiting for completion is needed
497 * Set the link speed in the AUTOC register and restarts link.
499 static s32
ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw
*hw
,
500 ixgbe_link_speed speed
,
502 bool autoneg_wait_to_complete
)
505 ixgbe_link_speed link_speed
= IXGBE_LINK_SPEED_UNKNOWN
;
506 ixgbe_link_speed highest_link_speed
= IXGBE_LINK_SPEED_UNKNOWN
;
508 u32 esdp_reg
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
510 bool link_up
= false;
513 /* Mask off requested but non-supported speeds */
514 status
= hw
->mac
.ops
.get_link_capabilities(hw
, &link_speed
,
522 * Try each speed one by one, highest priority first. We do this in
523 * software because 10gb fiber doesn't support speed autonegotiation.
525 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
) {
527 highest_link_speed
= IXGBE_LINK_SPEED_10GB_FULL
;
529 /* If we already have link at this speed, just jump out */
530 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
,
535 if ((link_speed
== IXGBE_LINK_SPEED_10GB_FULL
) && link_up
)
538 /* Set the module link speed */
539 esdp_reg
|= (IXGBE_ESDP_SDP5_DIR
| IXGBE_ESDP_SDP5
);
540 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
541 IXGBE_WRITE_FLUSH(hw
);
543 /* Allow module to change analog characteristics (1G->10G) */
546 status
= ixgbe_setup_mac_link_82599(hw
,
547 IXGBE_LINK_SPEED_10GB_FULL
,
549 autoneg_wait_to_complete
);
553 /* Flap the tx laser if it has not already been done */
554 hw
->mac
.ops
.flap_tx_laser(hw
);
557 * Wait for the controller to acquire link. Per IEEE 802.3ap,
558 * Section 73.10.2, we may have to wait up to 500ms if KR is
559 * attempted. 82599 uses the same timing for 10g SFI.
561 for (i
= 0; i
< 5; i
++) {
562 /* Wait for the link partner to also set speed */
565 /* If we have link, just jump out */
566 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
,
576 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
) {
578 if (highest_link_speed
== IXGBE_LINK_SPEED_UNKNOWN
)
579 highest_link_speed
= IXGBE_LINK_SPEED_1GB_FULL
;
581 /* If we already have link at this speed, just jump out */
582 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
,
587 if ((link_speed
== IXGBE_LINK_SPEED_1GB_FULL
) && link_up
)
590 /* Set the module link speed */
591 esdp_reg
&= ~IXGBE_ESDP_SDP5
;
592 esdp_reg
|= IXGBE_ESDP_SDP5_DIR
;
593 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
594 IXGBE_WRITE_FLUSH(hw
);
596 /* Allow module to change analog characteristics (10G->1G) */
599 status
= ixgbe_setup_mac_link_82599(hw
,
600 IXGBE_LINK_SPEED_1GB_FULL
,
602 autoneg_wait_to_complete
);
606 /* Flap the tx laser if it has not already been done */
607 hw
->mac
.ops
.flap_tx_laser(hw
);
609 /* Wait for the link partner to also set speed */
612 /* If we have link, just jump out */
613 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
,
623 * We didn't get link. Configure back to the highest speed we tried,
624 * (if there was more than one). We call ourselves back with just the
625 * single highest speed that the user requested.
628 status
= ixgbe_setup_mac_link_multispeed_fiber(hw
,
631 autoneg_wait_to_complete
);
634 /* Set autoneg_advertised value based on input link speed */
635 hw
->phy
.autoneg_advertised
= 0;
637 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
638 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_10GB_FULL
;
640 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
641 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_1GB_FULL
;
647 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
648 * @hw: pointer to hardware structure
649 * @speed: new link speed
650 * @autoneg: true if autonegotiation enabled
651 * @autoneg_wait_to_complete: true when waiting for completion is needed
653 * Implements the Intel SmartSpeed algorithm.
655 static s32
ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw
*hw
,
656 ixgbe_link_speed speed
, bool autoneg
,
657 bool autoneg_wait_to_complete
)
660 ixgbe_link_speed link_speed
= IXGBE_LINK_SPEED_UNKNOWN
;
662 bool link_up
= false;
663 u32 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
665 /* Set autoneg_advertised value based on input link speed */
666 hw
->phy
.autoneg_advertised
= 0;
668 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
669 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_10GB_FULL
;
671 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
672 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_1GB_FULL
;
674 if (speed
& IXGBE_LINK_SPEED_100_FULL
)
675 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_100_FULL
;
678 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
679 * autoneg advertisement if link is unable to be established at the
680 * highest negotiated rate. This can sometimes happen due to integrity
681 * issues with the physical media connection.
684 /* First, try to get link with full advertisement */
685 hw
->phy
.smart_speed_active
= false;
686 for (j
= 0; j
< IXGBE_SMARTSPEED_MAX_RETRIES
; j
++) {
687 status
= ixgbe_setup_mac_link_82599(hw
, speed
, autoneg
,
688 autoneg_wait_to_complete
);
693 * Wait for the controller to acquire link. Per IEEE 802.3ap,
694 * Section 73.10.2, we may have to wait up to 500ms if KR is
695 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
696 * Table 9 in the AN MAS.
698 for (i
= 0; i
< 5; i
++) {
701 /* If we have link, just jump out */
702 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
,
713 * We didn't get link. If we advertised KR plus one of KX4/KX
714 * (or BX4/BX), then disable KR and try again.
716 if (((autoc_reg
& IXGBE_AUTOC_KR_SUPP
) == 0) ||
717 ((autoc_reg
& IXGBE_AUTOC_KX4_KX_SUPP_MASK
) == 0))
720 /* Turn SmartSpeed on to disable KR support */
721 hw
->phy
.smart_speed_active
= true;
722 status
= ixgbe_setup_mac_link_82599(hw
, speed
, autoneg
,
723 autoneg_wait_to_complete
);
728 * Wait for the controller to acquire link. 600ms will allow for
729 * the AN link_fail_inhibit_timer as well for multiple cycles of
730 * parallel detect, both 10g and 1g. This allows for the maximum
731 * connect attempts as defined in the AN MAS table 73-7.
733 for (i
= 0; i
< 6; i
++) {
736 /* If we have link, just jump out */
737 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
,
746 /* We didn't get link. Turn SmartSpeed back off. */
747 hw
->phy
.smart_speed_active
= false;
748 status
= ixgbe_setup_mac_link_82599(hw
, speed
, autoneg
,
749 autoneg_wait_to_complete
);
752 if (link_up
&& (link_speed
== IXGBE_LINK_SPEED_1GB_FULL
))
753 hw_dbg(hw
, "Smartspeed has downgraded the link speed from "
754 "the maximum advertised\n");
759 * ixgbe_setup_mac_link_82599 - Set MAC link speed
760 * @hw: pointer to hardware structure
761 * @speed: new link speed
762 * @autoneg: true if autonegotiation enabled
763 * @autoneg_wait_to_complete: true when waiting for completion is needed
765 * Set the link speed in the AUTOC register and restarts link.
767 static s32
ixgbe_setup_mac_link_82599(struct ixgbe_hw
*hw
,
768 ixgbe_link_speed speed
, bool autoneg
,
769 bool autoneg_wait_to_complete
)
772 u32 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
773 u32 autoc2
= IXGBE_READ_REG(hw
, IXGBE_AUTOC2
);
774 u32 start_autoc
= autoc
;
776 u32 link_mode
= autoc
& IXGBE_AUTOC_LMS_MASK
;
777 u32 pma_pmd_1g
= autoc
& IXGBE_AUTOC_1G_PMA_PMD_MASK
;
778 u32 pma_pmd_10g_serial
= autoc2
& IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK
;
781 ixgbe_link_speed link_capabilities
= IXGBE_LINK_SPEED_UNKNOWN
;
783 /* Check to see if speed passed in is supported. */
784 hw
->mac
.ops
.get_link_capabilities(hw
, &link_capabilities
, &autoneg
);
788 speed
&= link_capabilities
;
790 if (speed
== IXGBE_LINK_SPEED_UNKNOWN
) {
791 status
= IXGBE_ERR_LINK_SETUP
;
795 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
796 if (hw
->mac
.orig_link_settings_stored
)
797 orig_autoc
= hw
->mac
.orig_autoc
;
801 if (link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR
||
802 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
||
803 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
) {
804 /* Set KX4/KX/KR support according to speed requested */
805 autoc
&= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK
| IXGBE_AUTOC_KR_SUPP
);
806 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
807 if (orig_autoc
& IXGBE_AUTOC_KX4_SUPP
)
808 autoc
|= IXGBE_AUTOC_KX4_SUPP
;
809 if ((orig_autoc
& IXGBE_AUTOC_KR_SUPP
) &&
810 (hw
->phy
.smart_speed_active
== false))
811 autoc
|= IXGBE_AUTOC_KR_SUPP
;
812 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
813 autoc
|= IXGBE_AUTOC_KX_SUPP
;
814 } else if ((pma_pmd_1g
== IXGBE_AUTOC_1G_SFI
) &&
815 (link_mode
== IXGBE_AUTOC_LMS_1G_LINK_NO_AN
||
816 link_mode
== IXGBE_AUTOC_LMS_1G_AN
)) {
817 /* Switch from 1G SFI to 10G SFI if requested */
818 if ((speed
== IXGBE_LINK_SPEED_10GB_FULL
) &&
819 (pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_SFI
)) {
820 autoc
&= ~IXGBE_AUTOC_LMS_MASK
;
821 autoc
|= IXGBE_AUTOC_LMS_10G_SERIAL
;
823 } else if ((pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_SFI
) &&
824 (link_mode
== IXGBE_AUTOC_LMS_10G_SERIAL
)) {
825 /* Switch from 10G SFI to 1G SFI if requested */
826 if ((speed
== IXGBE_LINK_SPEED_1GB_FULL
) &&
827 (pma_pmd_1g
== IXGBE_AUTOC_1G_SFI
)) {
828 autoc
&= ~IXGBE_AUTOC_LMS_MASK
;
830 autoc
|= IXGBE_AUTOC_LMS_1G_AN
;
832 autoc
|= IXGBE_AUTOC_LMS_1G_LINK_NO_AN
;
836 if (autoc
!= start_autoc
) {
838 autoc
|= IXGBE_AUTOC_AN_RESTART
;
839 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc
);
841 /* Only poll for autoneg to complete if specified to do so */
842 if (autoneg_wait_to_complete
) {
843 if (link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR
||
844 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
||
845 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
) {
846 links_reg
= 0; /*Just in case Autoneg time=0*/
847 for (i
= 0; i
< IXGBE_AUTO_NEG_TIME
; i
++) {
849 IXGBE_READ_REG(hw
, IXGBE_LINKS
);
850 if (links_reg
& IXGBE_LINKS_KX_AN_COMP
)
854 if (!(links_reg
& IXGBE_LINKS_KX_AN_COMP
)) {
856 IXGBE_ERR_AUTONEG_NOT_COMPLETE
;
857 hw_dbg(hw
, "Autoneg did not "
863 /* Add delay to filter out noises during initial link setup */
872 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
873 * @hw: pointer to hardware structure
874 * @speed: new link speed
875 * @autoneg: true if autonegotiation enabled
876 * @autoneg_wait_to_complete: true if waiting is needed to complete
878 * Restarts link on PHY and MAC based on settings passed in.
880 static s32
ixgbe_setup_copper_link_82599(struct ixgbe_hw
*hw
,
881 ixgbe_link_speed speed
,
883 bool autoneg_wait_to_complete
)
887 /* Setup the PHY according to input speed */
888 status
= hw
->phy
.ops
.setup_link_speed(hw
, speed
, autoneg
,
889 autoneg_wait_to_complete
);
891 ixgbe_start_mac_link_82599(hw
, autoneg_wait_to_complete
);
897 * ixgbe_reset_hw_82599 - Perform hardware reset
898 * @hw: pointer to hardware structure
900 * Resets the hardware by resetting the transmit and receive units, masks
901 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
904 static s32
ixgbe_reset_hw_82599(struct ixgbe_hw
*hw
)
912 /* Call adapter stop to disable tx/rx and clear interrupts */
913 hw
->mac
.ops
.stop_adapter(hw
);
915 /* PHY ops must be identified and initialized prior to reset */
917 /* Identify PHY and related function pointers */
918 status
= hw
->phy
.ops
.init(hw
);
920 if (status
== IXGBE_ERR_SFP_NOT_SUPPORTED
)
923 /* Setup SFP module if there is one present. */
924 if (hw
->phy
.sfp_setup_needed
) {
925 status
= hw
->mac
.ops
.setup_sfp(hw
);
926 hw
->phy
.sfp_setup_needed
= false;
929 if (status
== IXGBE_ERR_SFP_NOT_SUPPORTED
)
933 if (hw
->phy
.reset_disable
== false && hw
->phy
.ops
.reset
!= NULL
)
934 hw
->phy
.ops
.reset(hw
);
937 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
938 * access and verify no pending requests before reset
940 ixgbe_disable_pcie_master(hw
);
944 * Issue global reset to the MAC. This needs to be a SW reset.
945 * If link reset is used, it might reset the MAC when mng is using it
947 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
948 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, (ctrl
| IXGBE_CTRL_RST
));
949 IXGBE_WRITE_FLUSH(hw
);
951 /* Poll for reset bit to self-clear indicating reset is complete */
952 for (i
= 0; i
< 10; i
++) {
954 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
955 if (!(ctrl
& IXGBE_CTRL_RST
))
958 if (ctrl
& IXGBE_CTRL_RST
) {
959 status
= IXGBE_ERR_RESET_FAILED
;
960 hw_dbg(hw
, "Reset polling failed to complete.\n");
964 * Double resets are required for recovery from certain error
965 * conditions. Between resets, it is necessary to stall to allow time
966 * for any pending HW events to complete. We use 1usec since that is
967 * what is needed for ixgbe_disable_pcie_master(). The second reset
968 * then clears out any effects of those events.
970 if (hw
->mac
.flags
& IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
) {
971 hw
->mac
.flags
&= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
;
979 * Store the original AUTOC/AUTOC2 values if they have not been
980 * stored off yet. Otherwise restore the stored original
981 * values since the reset operation sets back to defaults.
983 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
984 autoc2
= IXGBE_READ_REG(hw
, IXGBE_AUTOC2
);
985 if (hw
->mac
.orig_link_settings_stored
== false) {
986 hw
->mac
.orig_autoc
= autoc
;
987 hw
->mac
.orig_autoc2
= autoc2
;
988 hw
->mac
.orig_link_settings_stored
= true;
990 if (autoc
!= hw
->mac
.orig_autoc
)
991 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, (hw
->mac
.orig_autoc
|
992 IXGBE_AUTOC_AN_RESTART
));
994 if ((autoc2
& IXGBE_AUTOC2_UPPER_MASK
) !=
995 (hw
->mac
.orig_autoc2
& IXGBE_AUTOC2_UPPER_MASK
)) {
996 autoc2
&= ~IXGBE_AUTOC2_UPPER_MASK
;
997 autoc2
|= (hw
->mac
.orig_autoc2
&
998 IXGBE_AUTOC2_UPPER_MASK
);
999 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC2
, autoc2
);
1003 /* Store the permanent mac address */
1004 hw
->mac
.ops
.get_mac_addr(hw
, hw
->mac
.perm_addr
);
1007 * Store MAC address from RAR0, clear receive address registers, and
1008 * clear the multicast table. Also reset num_rar_entries to 128,
1009 * since we modify this value when programming the SAN MAC address.
1011 hw
->mac
.num_rar_entries
= 128;
1012 hw
->mac
.ops
.init_rx_addrs(hw
);
1014 /* Store the permanent SAN mac address */
1015 hw
->mac
.ops
.get_san_mac_addr(hw
, hw
->mac
.san_addr
);
1017 /* Add the SAN MAC address to the RAR only if it's a valid address */
1018 if (ixgbe_validate_mac_addr(hw
->mac
.san_addr
) == 0) {
1019 hw
->mac
.ops
.set_rar(hw
, hw
->mac
.num_rar_entries
- 1,
1020 hw
->mac
.san_addr
, 0, IXGBE_RAH_AV
);
1022 /* Reserve the last RAR for the SAN MAC address */
1023 hw
->mac
.num_rar_entries
--;
1026 /* Store the alternative WWNN/WWPN prefix */
1027 hw
->mac
.ops
.get_wwn_prefix(hw
, &hw
->mac
.wwnn_prefix
,
1028 &hw
->mac
.wwpn_prefix
);
1035 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1036 * @hw: pointer to hardware structure
1038 s32
ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw
*hw
)
1041 u32 fdirctrl
= IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
);
1042 fdirctrl
&= ~IXGBE_FDIRCTRL_INIT_DONE
;
1045 * Before starting reinitialization process,
1046 * FDIRCMD.CMD must be zero.
1048 for (i
= 0; i
< IXGBE_FDIRCMD_CMD_POLL
; i
++) {
1049 if (!(IXGBE_READ_REG(hw
, IXGBE_FDIRCMD
) &
1050 IXGBE_FDIRCMD_CMD_MASK
))
1054 if (i
>= IXGBE_FDIRCMD_CMD_POLL
) {
1055 hw_dbg(hw
, "Flow Director previous command isn't complete, "
1056 "aborting table re-initialization.\n");
1057 return IXGBE_ERR_FDIR_REINIT_FAILED
;
1060 IXGBE_WRITE_REG(hw
, IXGBE_FDIRFREE
, 0);
1061 IXGBE_WRITE_FLUSH(hw
);
1063 * 82599 adapters flow director init flow cannot be restarted,
1064 * Workaround 82599 silicon errata by performing the following steps
1065 * before re-writing the FDIRCTRL control register with the same value.
1066 * - write 1 to bit 8 of FDIRCMD register &
1067 * - write 0 to bit 8 of FDIRCMD register
1069 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCMD
,
1070 (IXGBE_READ_REG(hw
, IXGBE_FDIRCMD
) |
1071 IXGBE_FDIRCMD_CLEARHT
));
1072 IXGBE_WRITE_FLUSH(hw
);
1073 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCMD
,
1074 (IXGBE_READ_REG(hw
, IXGBE_FDIRCMD
) &
1075 ~IXGBE_FDIRCMD_CLEARHT
));
1076 IXGBE_WRITE_FLUSH(hw
);
1078 * Clear FDIR Hash register to clear any leftover hashes
1079 * waiting to be programmed.
1081 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHASH
, 0x00);
1082 IXGBE_WRITE_FLUSH(hw
);
1084 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCTRL
, fdirctrl
);
1085 IXGBE_WRITE_FLUSH(hw
);
1087 /* Poll init-done after we write FDIRCTRL register */
1088 for (i
= 0; i
< IXGBE_FDIR_INIT_DONE_POLL
; i
++) {
1089 if (IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
) &
1090 IXGBE_FDIRCTRL_INIT_DONE
)
1094 if (i
>= IXGBE_FDIR_INIT_DONE_POLL
) {
1095 hw_dbg(hw
, "Flow Director Signature poll time exceeded!\n");
1096 return IXGBE_ERR_FDIR_REINIT_FAILED
;
1099 /* Clear FDIR statistics registers (read to clear) */
1100 IXGBE_READ_REG(hw
, IXGBE_FDIRUSTAT
);
1101 IXGBE_READ_REG(hw
, IXGBE_FDIRFSTAT
);
1102 IXGBE_READ_REG(hw
, IXGBE_FDIRMATCH
);
1103 IXGBE_READ_REG(hw
, IXGBE_FDIRMISS
);
1104 IXGBE_READ_REG(hw
, IXGBE_FDIRLEN
);
1110 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1111 * @hw: pointer to hardware structure
1112 * @pballoc: which mode to allocate filters with
1114 s32
ixgbe_init_fdir_signature_82599(struct ixgbe_hw
*hw
, u32 pballoc
)
1119 /* Send interrupt when 64 filters are left */
1120 fdirctrl
|= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT
;
1122 /* Set the maximum length per hash bucket to 0xA filters */
1123 fdirctrl
|= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT
;
1126 case IXGBE_FDIR_PBALLOC_64K
:
1127 /* 8k - 1 signature filters */
1128 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_64K
;
1130 case IXGBE_FDIR_PBALLOC_128K
:
1131 /* 16k - 1 signature filters */
1132 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_128K
;
1134 case IXGBE_FDIR_PBALLOC_256K
:
1135 /* 32k - 1 signature filters */
1136 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_256K
;
1140 return IXGBE_ERR_CONFIG
;
1143 /* Move the flexible bytes to use the ethertype - shift 6 words */
1144 fdirctrl
|= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT
);
1147 /* Prime the keys for hashing */
1148 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHKEY
, IXGBE_ATR_BUCKET_HASH_KEY
);
1149 IXGBE_WRITE_REG(hw
, IXGBE_FDIRSKEY
, IXGBE_ATR_SIGNATURE_HASH_KEY
);
1152 * Poll init-done after we write the register. Estimated times:
1153 * 10G: PBALLOC = 11b, timing is 60us
1154 * 1G: PBALLOC = 11b, timing is 600us
1155 * 100M: PBALLOC = 11b, timing is 6ms
1157 * Multiple these timings by 4 if under full Rx load
1159 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1160 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1161 * this might not finish in our poll time, but we can live with that
1164 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCTRL
, fdirctrl
);
1165 IXGBE_WRITE_FLUSH(hw
);
1166 for (i
= 0; i
< IXGBE_FDIR_INIT_DONE_POLL
; i
++) {
1167 if (IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
) &
1168 IXGBE_FDIRCTRL_INIT_DONE
)
1170 usleep_range(1000, 2000);
1172 if (i
>= IXGBE_FDIR_INIT_DONE_POLL
)
1173 hw_dbg(hw
, "Flow Director Signature poll time exceeded!\n");
1179 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1180 * @hw: pointer to hardware structure
1181 * @pballoc: which mode to allocate filters with
1183 s32
ixgbe_init_fdir_perfect_82599(struct ixgbe_hw
*hw
, u32 pballoc
)
1188 /* Send interrupt when 64 filters are left */
1189 fdirctrl
|= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT
;
1191 /* Initialize the drop queue to Rx queue 127 */
1192 fdirctrl
|= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT
);
1195 case IXGBE_FDIR_PBALLOC_64K
:
1196 /* 2k - 1 perfect filters */
1197 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_64K
;
1199 case IXGBE_FDIR_PBALLOC_128K
:
1200 /* 4k - 1 perfect filters */
1201 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_128K
;
1203 case IXGBE_FDIR_PBALLOC_256K
:
1204 /* 8k - 1 perfect filters */
1205 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_256K
;
1209 return IXGBE_ERR_CONFIG
;
1212 /* Turn perfect match filtering on */
1213 fdirctrl
|= IXGBE_FDIRCTRL_PERFECT_MATCH
;
1214 fdirctrl
|= IXGBE_FDIRCTRL_REPORT_STATUS
;
1216 /* Move the flexible bytes to use the ethertype - shift 6 words */
1217 fdirctrl
|= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT
);
1219 /* Prime the keys for hashing */
1220 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHKEY
, IXGBE_ATR_BUCKET_HASH_KEY
);
1221 IXGBE_WRITE_REG(hw
, IXGBE_FDIRSKEY
, IXGBE_ATR_SIGNATURE_HASH_KEY
);
1224 * Poll init-done after we write the register. Estimated times:
1225 * 10G: PBALLOC = 11b, timing is 60us
1226 * 1G: PBALLOC = 11b, timing is 600us
1227 * 100M: PBALLOC = 11b, timing is 6ms
1229 * Multiple these timings by 4 if under full Rx load
1231 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1232 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1233 * this might not finish in our poll time, but we can live with that
1237 /* Set the maximum length per hash bucket to 0xA filters */
1238 fdirctrl
|= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT
);
1240 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCTRL
, fdirctrl
);
1241 IXGBE_WRITE_FLUSH(hw
);
1242 for (i
= 0; i
< IXGBE_FDIR_INIT_DONE_POLL
; i
++) {
1243 if (IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
) &
1244 IXGBE_FDIRCTRL_INIT_DONE
)
1246 usleep_range(1000, 2000);
1248 if (i
>= IXGBE_FDIR_INIT_DONE_POLL
)
1249 hw_dbg(hw
, "Flow Director Perfect poll time exceeded!\n");
1256 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1257 * @stream: input bitstream to compute the hash on
1258 * @key: 32-bit hash key
1260 static u32
ixgbe_atr_compute_hash_82599(union ixgbe_atr_input
*atr_input
,
1264 * The algorithm is as follows:
1265 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1266 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1267 * and A[n] x B[n] is bitwise AND between same length strings
1269 * K[n] is 16 bits, defined as:
1270 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1271 * for n modulo 32 < 15, K[n] =
1272 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1274 * S[n] is 16 bits, defined as:
1275 * for n >= 15, S[n] = S[n:n - 15]
1276 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1278 * To simplify for programming, the algorithm is implemented
1279 * in software this way:
1281 * key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
1283 * for (i = 0; i < 352; i+=32)
1284 * hi_hash_dword[31:0] ^= Stream[(i+31):i];
1286 * lo_hash_dword[15:0] ^= Stream[15:0];
1287 * lo_hash_dword[15:0] ^= hi_hash_dword[31:16];
1288 * lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
1290 * hi_hash_dword[31:0] ^= Stream[351:320];
1293 * hash[15:0] ^= Stream[15:0];
1295 * for (i = 0; i < 16; i++) {
1297 * hash[15:0] ^= lo_hash_dword[(i+15):i];
1299 * hash[15:0] ^= hi_hash_dword[(i+15):i];
1303 __be32 common_hash_dword
= 0;
1304 u32 hi_hash_dword
, lo_hash_dword
, flow_vm_vlan
;
1305 u32 hash_result
= 0;
1308 /* record the flow_vm_vlan bits as they are a key part to the hash */
1309 flow_vm_vlan
= ntohl(atr_input
->dword_stream
[0]);
1311 /* generate common hash dword */
1312 for (i
= 10; i
; i
-= 2)
1313 common_hash_dword
^= atr_input
->dword_stream
[i
] ^
1314 atr_input
->dword_stream
[i
- 1];
1316 hi_hash_dword
= ntohl(common_hash_dword
);
1318 /* low dword is word swapped version of common */
1319 lo_hash_dword
= (hi_hash_dword
>> 16) | (hi_hash_dword
<< 16);
1321 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1322 hi_hash_dword
^= flow_vm_vlan
^ (flow_vm_vlan
>> 16);
1324 /* Process bits 0 and 16 */
1325 if (key
& 0x0001) hash_result
^= lo_hash_dword
;
1326 if (key
& 0x00010000) hash_result
^= hi_hash_dword
;
1329 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1330 * delay this because bit 0 of the stream should not be processed
1331 * so we do not add the vlan until after bit 0 was processed
1333 lo_hash_dword
^= flow_vm_vlan
^ (flow_vm_vlan
<< 16);
1336 /* process the remaining 30 bits in the key 2 bits at a time */
1337 for (i
= 15; i
; i
-- ) {
1338 if (key
& (0x0001 << i
)) hash_result
^= lo_hash_dword
>> i
;
1339 if (key
& (0x00010000 << i
)) hash_result
^= hi_hash_dword
>> i
;
1342 return hash_result
& IXGBE_ATR_HASH_MASK
;
1346 * These defines allow us to quickly generate all of the necessary instructions
1347 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1348 * for values 0 through 15
1350 #define IXGBE_ATR_COMMON_HASH_KEY \
1351 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1352 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1355 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1356 common_hash ^= lo_hash_dword >> n; \
1357 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1358 bucket_hash ^= lo_hash_dword >> n; \
1359 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1360 sig_hash ^= lo_hash_dword << (16 - n); \
1361 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1362 common_hash ^= hi_hash_dword >> n; \
1363 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1364 bucket_hash ^= hi_hash_dword >> n; \
1365 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1366 sig_hash ^= hi_hash_dword << (16 - n); \
1370 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1371 * @stream: input bitstream to compute the hash on
1373 * This function is almost identical to the function above but contains
1374 * several optomizations such as unwinding all of the loops, letting the
1375 * compiler work out all of the conditional ifs since the keys are static
1376 * defines, and computing two keys at once since the hashed dword stream
1377 * will be the same for both keys.
1379 static u32
ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input
,
1380 union ixgbe_atr_hash_dword common
)
1382 u32 hi_hash_dword
, lo_hash_dword
, flow_vm_vlan
;
1383 u32 sig_hash
= 0, bucket_hash
= 0, common_hash
= 0;
1385 /* record the flow_vm_vlan bits as they are a key part to the hash */
1386 flow_vm_vlan
= ntohl(input
.dword
);
1388 /* generate common hash dword */
1389 hi_hash_dword
= ntohl(common
.dword
);
1391 /* low dword is word swapped version of common */
1392 lo_hash_dword
= (hi_hash_dword
>> 16) | (hi_hash_dword
<< 16);
1394 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1395 hi_hash_dword
^= flow_vm_vlan
^ (flow_vm_vlan
>> 16);
1397 /* Process bits 0 and 16 */
1398 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1401 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1402 * delay this because bit 0 of the stream should not be processed
1403 * so we do not add the vlan until after bit 0 was processed
1405 lo_hash_dword
^= flow_vm_vlan
^ (flow_vm_vlan
<< 16);
1407 /* Process remaining 30 bit of the key */
1408 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1409 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1410 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1411 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1412 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1413 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1414 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1415 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1416 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1417 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1418 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1419 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1420 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1421 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1422 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1424 /* combine common_hash result with signature and bucket hashes */
1425 bucket_hash
^= common_hash
;
1426 bucket_hash
&= IXGBE_ATR_HASH_MASK
;
1428 sig_hash
^= common_hash
<< 16;
1429 sig_hash
&= IXGBE_ATR_HASH_MASK
<< 16;
1431 /* return completed signature hash */
1432 return sig_hash
^ bucket_hash
;
1436 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1437 * @hw: pointer to hardware structure
1438 * @input: unique input dword
1439 * @common: compressed common input dword
1440 * @queue: queue index to direct traffic to
1442 s32
ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw
*hw
,
1443 union ixgbe_atr_hash_dword input
,
1444 union ixgbe_atr_hash_dword common
,
1451 * Get the flow_type in order to program FDIRCMD properly
1452 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1454 switch (input
.formatted
.flow_type
) {
1455 case IXGBE_ATR_FLOW_TYPE_TCPV4
:
1456 case IXGBE_ATR_FLOW_TYPE_UDPV4
:
1457 case IXGBE_ATR_FLOW_TYPE_SCTPV4
:
1458 case IXGBE_ATR_FLOW_TYPE_TCPV6
:
1459 case IXGBE_ATR_FLOW_TYPE_UDPV6
:
1460 case IXGBE_ATR_FLOW_TYPE_SCTPV6
:
1463 hw_dbg(hw
, " Error on flow type input\n");
1464 return IXGBE_ERR_CONFIG
;
1467 /* configure FDIRCMD register */
1468 fdircmd
= IXGBE_FDIRCMD_CMD_ADD_FLOW
| IXGBE_FDIRCMD_FILTER_UPDATE
|
1469 IXGBE_FDIRCMD_LAST
| IXGBE_FDIRCMD_QUEUE_EN
;
1470 fdircmd
|= input
.formatted
.flow_type
<< IXGBE_FDIRCMD_FLOW_TYPE_SHIFT
;
1471 fdircmd
|= (u32
)queue
<< IXGBE_FDIRCMD_RX_QUEUE_SHIFT
;
1474 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1475 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1477 fdirhashcmd
= (u64
)fdircmd
<< 32;
1478 fdirhashcmd
|= ixgbe_atr_compute_sig_hash_82599(input
, common
);
1480 IXGBE_WRITE_REG64(hw
, IXGBE_FDIRHASH
, fdirhashcmd
);
1482 hw_dbg(hw
, "Tx Queue=%x hash=%x\n", queue
, (u32
)fdirhashcmd
);
1488 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1489 * @input_mask: mask to be bit swapped
1491 * The source and destination port masks for flow director are bit swapped
1492 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1493 * generate a correctly swapped value we need to bit swap the mask and that
1494 * is what is accomplished by this function.
1496 static u32
ixgbe_get_fdirtcpm_82599(struct ixgbe_atr_input_masks
*input_masks
)
1498 u32 mask
= ntohs(input_masks
->dst_port_mask
);
1499 mask
<<= IXGBE_FDIRTCPM_DPORTM_SHIFT
;
1500 mask
|= ntohs(input_masks
->src_port_mask
);
1501 mask
= ((mask
& 0x55555555) << 1) | ((mask
& 0xAAAAAAAA) >> 1);
1502 mask
= ((mask
& 0x33333333) << 2) | ((mask
& 0xCCCCCCCC) >> 2);
1503 mask
= ((mask
& 0x0F0F0F0F) << 4) | ((mask
& 0xF0F0F0F0) >> 4);
1504 return ((mask
& 0x00FF00FF) << 8) | ((mask
& 0xFF00FF00) >> 8);
1508 * These two macros are meant to address the fact that we have registers
1509 * that are either all or in part big-endian. As a result on big-endian
1510 * systems we will end up byte swapping the value to little-endian before
1511 * it is byte swapped again and written to the hardware in the original
1512 * big-endian format.
1514 #define IXGBE_STORE_AS_BE32(_value) \
1515 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1516 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1518 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1519 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
1521 #define IXGBE_STORE_AS_BE16(_value) \
1522 (((u16)(_value) >> 8) | ((u16)(_value) << 8))
1525 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1526 * @hw: pointer to hardware structure
1527 * @input: input bitstream
1528 * @input_masks: bitwise masks for relevant fields
1529 * @soft_id: software index into the silicon hash tables for filter storage
1530 * @queue: queue index to direct traffic to
1532 * Note that the caller to this function must lock before calling, since the
1533 * hardware writes must be protected from one another.
1535 s32
ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw
*hw
,
1536 union ixgbe_atr_input
*input
,
1537 struct ixgbe_atr_input_masks
*input_masks
,
1538 u16 soft_id
, u8 queue
)
1542 u32 fdirport
, fdirtcpm
;
1544 /* start with VLAN, flex bytes, VM pool, and IPv6 destination masked */
1545 u32 fdirm
= IXGBE_FDIRM_VLANID
| IXGBE_FDIRM_VLANP
| IXGBE_FDIRM_FLEX
|
1546 IXGBE_FDIRM_POOL
| IXGBE_FDIRM_DIPv6
;
1549 * Check flow_type formatting, and bail out before we touch the hardware
1550 * if there's a configuration issue
1552 switch (input
->formatted
.flow_type
) {
1553 case IXGBE_ATR_FLOW_TYPE_IPV4
:
1554 /* use the L4 protocol mask for raw IPv4/IPv6 traffic */
1555 fdirm
|= IXGBE_FDIRM_L4P
;
1556 case IXGBE_ATR_FLOW_TYPE_SCTPV4
:
1557 if (input_masks
->dst_port_mask
|| input_masks
->src_port_mask
) {
1558 hw_dbg(hw
, " Error on src/dst port mask\n");
1559 return IXGBE_ERR_CONFIG
;
1561 case IXGBE_ATR_FLOW_TYPE_TCPV4
:
1562 case IXGBE_ATR_FLOW_TYPE_UDPV4
:
1565 hw_dbg(hw
, " Error on flow type input\n");
1566 return IXGBE_ERR_CONFIG
;
1570 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1571 * are zero, then assume a full mask for that field. Also assume that
1572 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1573 * cannot be masked out in this implementation.
1575 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1580 switch (ntohs(input_masks
->vlan_id_mask
) & 0xEFFF) {
1582 /* Unmask VLAN ID - bit 0 and fall through to unmask prio */
1583 fdirm
&= ~IXGBE_FDIRM_VLANID
;
1585 /* Unmask VLAN prio - bit 1 */
1586 fdirm
&= ~IXGBE_FDIRM_VLANP
;
1589 /* Unmask VLAN ID - bit 0 */
1590 fdirm
&= ~IXGBE_FDIRM_VLANID
;
1593 /* do nothing, vlans already masked */
1596 hw_dbg(hw
, " Error on VLAN mask\n");
1597 return IXGBE_ERR_CONFIG
;
1600 if (input_masks
->flex_mask
& 0xFFFF) {
1601 if ((input_masks
->flex_mask
& 0xFFFF) != 0xFFFF) {
1602 hw_dbg(hw
, " Error on flexible byte mask\n");
1603 return IXGBE_ERR_CONFIG
;
1605 /* Unmask Flex Bytes - bit 4 */
1606 fdirm
&= ~IXGBE_FDIRM_FLEX
;
1609 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1610 IXGBE_WRITE_REG(hw
, IXGBE_FDIRM
, fdirm
);
1612 /* store the TCP/UDP port masks, bit reversed from port layout */
1613 fdirtcpm
= ixgbe_get_fdirtcpm_82599(input_masks
);
1615 /* write both the same so that UDP and TCP use the same mask */
1616 IXGBE_WRITE_REG(hw
, IXGBE_FDIRTCPM
, ~fdirtcpm
);
1617 IXGBE_WRITE_REG(hw
, IXGBE_FDIRUDPM
, ~fdirtcpm
);
1619 /* store source and destination IP masks (big-enian) */
1620 IXGBE_WRITE_REG_BE32(hw
, IXGBE_FDIRSIP4M
,
1621 ~input_masks
->src_ip_mask
[0]);
1622 IXGBE_WRITE_REG_BE32(hw
, IXGBE_FDIRDIP4M
,
1623 ~input_masks
->dst_ip_mask
[0]);
1625 /* Apply masks to input data */
1626 input
->formatted
.vlan_id
&= input_masks
->vlan_id_mask
;
1627 input
->formatted
.flex_bytes
&= input_masks
->flex_mask
;
1628 input
->formatted
.src_port
&= input_masks
->src_port_mask
;
1629 input
->formatted
.dst_port
&= input_masks
->dst_port_mask
;
1630 input
->formatted
.src_ip
[0] &= input_masks
->src_ip_mask
[0];
1631 input
->formatted
.dst_ip
[0] &= input_masks
->dst_ip_mask
[0];
1633 /* record vlan (little-endian) and flex_bytes(big-endian) */
1635 IXGBE_STORE_AS_BE16(ntohs(input
->formatted
.flex_bytes
));
1636 fdirvlan
<<= IXGBE_FDIRVLAN_FLEX_SHIFT
;
1637 fdirvlan
|= ntohs(input
->formatted
.vlan_id
);
1638 IXGBE_WRITE_REG(hw
, IXGBE_FDIRVLAN
, fdirvlan
);
1640 /* record source and destination port (little-endian)*/
1641 fdirport
= ntohs(input
->formatted
.dst_port
);
1642 fdirport
<<= IXGBE_FDIRPORT_DESTINATION_SHIFT
;
1643 fdirport
|= ntohs(input
->formatted
.src_port
);
1644 IXGBE_WRITE_REG(hw
, IXGBE_FDIRPORT
, fdirport
);
1646 /* record the first 32 bits of the destination address (big-endian) */
1647 IXGBE_WRITE_REG_BE32(hw
, IXGBE_FDIRIPDA
, input
->formatted
.dst_ip
[0]);
1649 /* record the source address (big-endian) */
1650 IXGBE_WRITE_REG_BE32(hw
, IXGBE_FDIRIPSA
, input
->formatted
.src_ip
[0]);
1652 /* configure FDIRCMD register */
1653 fdircmd
= IXGBE_FDIRCMD_CMD_ADD_FLOW
| IXGBE_FDIRCMD_FILTER_UPDATE
|
1654 IXGBE_FDIRCMD_LAST
| IXGBE_FDIRCMD_QUEUE_EN
;
1655 fdircmd
|= input
->formatted
.flow_type
<< IXGBE_FDIRCMD_FLOW_TYPE_SHIFT
;
1656 fdircmd
|= (u32
)queue
<< IXGBE_FDIRCMD_RX_QUEUE_SHIFT
;
1658 /* we only want the bucket hash so drop the upper 16 bits */
1659 fdirhash
= ixgbe_atr_compute_hash_82599(input
,
1660 IXGBE_ATR_BUCKET_HASH_KEY
);
1661 fdirhash
|= soft_id
<< IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT
;
1663 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHASH
, fdirhash
);
1664 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCMD
, fdircmd
);
1670 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1671 * @hw: pointer to hardware structure
1672 * @reg: analog register to read
1675 * Performs read operation to Omer analog register specified.
1677 static s32
ixgbe_read_analog_reg8_82599(struct ixgbe_hw
*hw
, u32 reg
, u8
*val
)
1681 IXGBE_WRITE_REG(hw
, IXGBE_CORECTL
, IXGBE_CORECTL_WRITE_CMD
|
1683 IXGBE_WRITE_FLUSH(hw
);
1685 core_ctl
= IXGBE_READ_REG(hw
, IXGBE_CORECTL
);
1686 *val
= (u8
)core_ctl
;
1692 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1693 * @hw: pointer to hardware structure
1694 * @reg: atlas register to write
1695 * @val: value to write
1697 * Performs write operation to Omer analog register specified.
1699 static s32
ixgbe_write_analog_reg8_82599(struct ixgbe_hw
*hw
, u32 reg
, u8 val
)
1703 core_ctl
= (reg
<< 8) | val
;
1704 IXGBE_WRITE_REG(hw
, IXGBE_CORECTL
, core_ctl
);
1705 IXGBE_WRITE_FLUSH(hw
);
1712 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1713 * @hw: pointer to hardware structure
1715 * Starts the hardware using the generic start_hw function
1716 * and the generation start_hw function.
1717 * Then performs revision-specific operations, if any.
1719 static s32
ixgbe_start_hw_82599(struct ixgbe_hw
*hw
)
1723 ret_val
= ixgbe_start_hw_generic(hw
);
1727 ret_val
= ixgbe_start_hw_gen2(hw
);
1731 /* We need to run link autotry after the driver loads */
1732 hw
->mac
.autotry_restart
= true;
1733 hw
->mac
.rx_pb_size
= IXGBE_82599_RX_PB_SIZE
;
1736 ret_val
= ixgbe_verify_fw_version_82599(hw
);
1742 * ixgbe_identify_phy_82599 - Get physical layer module
1743 * @hw: pointer to hardware structure
1745 * Determines the physical layer module found on the current adapter.
1746 * If PHY already detected, maintains current PHY type in hw struct,
1747 * otherwise executes the PHY detection routine.
1749 static s32
ixgbe_identify_phy_82599(struct ixgbe_hw
*hw
)
1751 s32 status
= IXGBE_ERR_PHY_ADDR_INVALID
;
1753 /* Detect PHY if not unknown - returns success if already detected. */
1754 status
= ixgbe_identify_phy_generic(hw
);
1756 /* 82599 10GBASE-T requires an external PHY */
1757 if (hw
->mac
.ops
.get_media_type(hw
) == ixgbe_media_type_copper
)
1760 status
= ixgbe_identify_sfp_module_generic(hw
);
1763 /* Set PHY type none if no PHY detected */
1764 if (hw
->phy
.type
== ixgbe_phy_unknown
) {
1765 hw
->phy
.type
= ixgbe_phy_none
;
1769 /* Return error if SFP module has been detected but is not supported */
1770 if (hw
->phy
.type
== ixgbe_phy_sfp_unsupported
)
1771 status
= IXGBE_ERR_SFP_NOT_SUPPORTED
;
1778 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1779 * @hw: pointer to hardware structure
1781 * Determines physical layer capabilities of the current configuration.
1783 static u32
ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw
*hw
)
1785 u32 physical_layer
= IXGBE_PHYSICAL_LAYER_UNKNOWN
;
1786 u32 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
1787 u32 autoc2
= IXGBE_READ_REG(hw
, IXGBE_AUTOC2
);
1788 u32 pma_pmd_10g_serial
= autoc2
& IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK
;
1789 u32 pma_pmd_10g_parallel
= autoc
& IXGBE_AUTOC_10G_PMA_PMD_MASK
;
1790 u32 pma_pmd_1g
= autoc
& IXGBE_AUTOC_1G_PMA_PMD_MASK
;
1791 u16 ext_ability
= 0;
1792 u8 comp_codes_10g
= 0;
1793 u8 comp_codes_1g
= 0;
1795 hw
->phy
.ops
.identify(hw
);
1797 switch (hw
->phy
.type
) {
1800 case ixgbe_phy_cu_unknown
:
1801 hw
->phy
.ops
.read_reg(hw
, MDIO_PMA_EXTABLE
, MDIO_MMD_PMAPMD
,
1803 if (ext_ability
& MDIO_PMA_EXTABLE_10GBT
)
1804 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_T
;
1805 if (ext_ability
& MDIO_PMA_EXTABLE_1000BT
)
1806 physical_layer
|= IXGBE_PHYSICAL_LAYER_1000BASE_T
;
1807 if (ext_ability
& MDIO_PMA_EXTABLE_100BTX
)
1808 physical_layer
|= IXGBE_PHYSICAL_LAYER_100BASE_TX
;
1814 switch (autoc
& IXGBE_AUTOC_LMS_MASK
) {
1815 case IXGBE_AUTOC_LMS_1G_AN
:
1816 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN
:
1817 if (pma_pmd_1g
== IXGBE_AUTOC_1G_KX_BX
) {
1818 physical_layer
= IXGBE_PHYSICAL_LAYER_1000BASE_KX
|
1819 IXGBE_PHYSICAL_LAYER_1000BASE_BX
;
1822 /* SFI mode so read SFP module */
1825 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN
:
1826 if (pma_pmd_10g_parallel
== IXGBE_AUTOC_10G_CX4
)
1827 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_CX4
;
1828 else if (pma_pmd_10g_parallel
== IXGBE_AUTOC_10G_KX4
)
1829 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_KX4
;
1830 else if (pma_pmd_10g_parallel
== IXGBE_AUTOC_10G_XAUI
)
1831 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_XAUI
;
1834 case IXGBE_AUTOC_LMS_10G_SERIAL
:
1835 if (pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_KR
) {
1836 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_KR
;
1838 } else if (pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_SFI
)
1841 case IXGBE_AUTOC_LMS_KX4_KX_KR
:
1842 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
:
1843 if (autoc
& IXGBE_AUTOC_KX_SUPP
)
1844 physical_layer
|= IXGBE_PHYSICAL_LAYER_1000BASE_KX
;
1845 if (autoc
& IXGBE_AUTOC_KX4_SUPP
)
1846 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_KX4
;
1847 if (autoc
& IXGBE_AUTOC_KR_SUPP
)
1848 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_KR
;
1857 /* SFP check must be done last since DA modules are sometimes used to
1858 * test KR mode - we need to id KR mode correctly before SFP module.
1859 * Call identify_sfp because the pluggable module may have changed */
1860 hw
->phy
.ops
.identify_sfp(hw
);
1861 if (hw
->phy
.sfp_type
== ixgbe_sfp_type_not_present
)
1864 switch (hw
->phy
.type
) {
1865 case ixgbe_phy_sfp_passive_tyco
:
1866 case ixgbe_phy_sfp_passive_unknown
:
1867 physical_layer
= IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU
;
1869 case ixgbe_phy_sfp_ftl_active
:
1870 case ixgbe_phy_sfp_active_unknown
:
1871 physical_layer
= IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA
;
1873 case ixgbe_phy_sfp_avago
:
1874 case ixgbe_phy_sfp_ftl
:
1875 case ixgbe_phy_sfp_intel
:
1876 case ixgbe_phy_sfp_unknown
:
1877 hw
->phy
.ops
.read_i2c_eeprom(hw
,
1878 IXGBE_SFF_1GBE_COMP_CODES
, &comp_codes_1g
);
1879 hw
->phy
.ops
.read_i2c_eeprom(hw
,
1880 IXGBE_SFF_10GBE_COMP_CODES
, &comp_codes_10g
);
1881 if (comp_codes_10g
& IXGBE_SFF_10GBASESR_CAPABLE
)
1882 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_SR
;
1883 else if (comp_codes_10g
& IXGBE_SFF_10GBASELR_CAPABLE
)
1884 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_LR
;
1885 else if (comp_codes_1g
& IXGBE_SFF_1GBASET_CAPABLE
)
1886 physical_layer
= IXGBE_PHYSICAL_LAYER_1000BASE_T
;
1893 return physical_layer
;
1897 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1898 * @hw: pointer to hardware structure
1899 * @regval: register value to write to RXCTRL
1901 * Enables the Rx DMA unit for 82599
1903 static s32
ixgbe_enable_rx_dma_82599(struct ixgbe_hw
*hw
, u32 regval
)
1905 #define IXGBE_MAX_SECRX_POLL 30
1910 * Workaround for 82599 silicon errata when enabling the Rx datapath.
1911 * If traffic is incoming before we enable the Rx unit, it could hang
1912 * the Rx DMA unit. Therefore, make sure the security engine is
1913 * completely disabled prior to enabling the Rx unit.
1915 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXCTRL
);
1916 secrxreg
|= IXGBE_SECRXCTRL_RX_DIS
;
1917 IXGBE_WRITE_REG(hw
, IXGBE_SECRXCTRL
, secrxreg
);
1918 for (i
= 0; i
< IXGBE_MAX_SECRX_POLL
; i
++) {
1919 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXSTAT
);
1920 if (secrxreg
& IXGBE_SECRXSTAT_SECRX_RDY
)
1923 /* Use interrupt-safe sleep just in case */
1927 /* For informational purposes only */
1928 if (i
>= IXGBE_MAX_SECRX_POLL
)
1929 hw_dbg(hw
, "Rx unit being enabled before security "
1930 "path fully disabled. Continuing with init.\n");
1932 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, regval
);
1933 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXCTRL
);
1934 secrxreg
&= ~IXGBE_SECRXCTRL_RX_DIS
;
1935 IXGBE_WRITE_REG(hw
, IXGBE_SECRXCTRL
, secrxreg
);
1936 IXGBE_WRITE_FLUSH(hw
);
1942 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
1943 * @hw: pointer to hardware structure
1945 * Verifies that installed the firmware version is 0.6 or higher
1946 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
1948 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
1949 * if the FW version is not supported.
1951 static s32
ixgbe_verify_fw_version_82599(struct ixgbe_hw
*hw
)
1953 s32 status
= IXGBE_ERR_EEPROM_VERSION
;
1954 u16 fw_offset
, fw_ptp_cfg_offset
;
1957 /* firmware check is only necessary for SFI devices */
1958 if (hw
->phy
.media_type
!= ixgbe_media_type_fiber
) {
1960 goto fw_version_out
;
1963 /* get the offset to the Firmware Module block */
1964 hw
->eeprom
.ops
.read(hw
, IXGBE_FW_PTR
, &fw_offset
);
1966 if ((fw_offset
== 0) || (fw_offset
== 0xFFFF))
1967 goto fw_version_out
;
1969 /* get the offset to the Pass Through Patch Configuration block */
1970 hw
->eeprom
.ops
.read(hw
, (fw_offset
+
1971 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR
),
1972 &fw_ptp_cfg_offset
);
1974 if ((fw_ptp_cfg_offset
== 0) || (fw_ptp_cfg_offset
== 0xFFFF))
1975 goto fw_version_out
;
1977 /* get the firmware version */
1978 hw
->eeprom
.ops
.read(hw
, (fw_ptp_cfg_offset
+
1979 IXGBE_FW_PATCH_VERSION_4
),
1982 if (fw_version
> 0x5)
1990 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
1991 * @hw: pointer to hardware structure
1993 * Returns true if the LESM FW module is present and enabled. Otherwise
1994 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
1996 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw
*hw
)
1998 bool lesm_enabled
= false;
1999 u16 fw_offset
, fw_lesm_param_offset
, fw_lesm_state
;
2002 /* get the offset to the Firmware Module block */
2003 status
= hw
->eeprom
.ops
.read(hw
, IXGBE_FW_PTR
, &fw_offset
);
2005 if ((status
!= 0) ||
2006 (fw_offset
== 0) || (fw_offset
== 0xFFFF))
2009 /* get the offset to the LESM Parameters block */
2010 status
= hw
->eeprom
.ops
.read(hw
, (fw_offset
+
2011 IXGBE_FW_LESM_PARAMETERS_PTR
),
2012 &fw_lesm_param_offset
);
2014 if ((status
!= 0) ||
2015 (fw_lesm_param_offset
== 0) || (fw_lesm_param_offset
== 0xFFFF))
2018 /* get the lesm state word */
2019 status
= hw
->eeprom
.ops
.read(hw
, (fw_lesm_param_offset
+
2020 IXGBE_FW_LESM_STATE_1
),
2023 if ((status
== 0) &&
2024 (fw_lesm_state
& IXGBE_FW_LESM_STATE_ENABLED
))
2025 lesm_enabled
= true;
2028 return lesm_enabled
;
2032 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2033 * fastest available method
2035 * @hw: pointer to hardware structure
2036 * @offset: offset of word in EEPROM to read
2037 * @words: number of words
2038 * @data: word(s) read from the EEPROM
2040 * Retrieves 16 bit word(s) read from EEPROM
2042 static s32
ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw
*hw
, u16 offset
,
2043 u16 words
, u16
*data
)
2045 struct ixgbe_eeprom_info
*eeprom
= &hw
->eeprom
;
2046 s32 ret_val
= IXGBE_ERR_CONFIG
;
2049 * If EEPROM is detected and can be addressed using 14 bits,
2050 * use EERD otherwise use bit bang
2052 if ((eeprom
->type
== ixgbe_eeprom_spi
) &&
2053 (offset
+ (words
- 1) <= IXGBE_EERD_MAX_ADDR
))
2054 ret_val
= ixgbe_read_eerd_buffer_generic(hw
, offset
, words
,
2057 ret_val
= ixgbe_read_eeprom_buffer_bit_bang_generic(hw
, offset
,
2065 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2066 * fastest available method
2068 * @hw: pointer to hardware structure
2069 * @offset: offset of word in the EEPROM to read
2070 * @data: word read from the EEPROM
2072 * Reads a 16 bit word from the EEPROM
2074 static s32
ixgbe_read_eeprom_82599(struct ixgbe_hw
*hw
,
2075 u16 offset
, u16
*data
)
2077 struct ixgbe_eeprom_info
*eeprom
= &hw
->eeprom
;
2078 s32 ret_val
= IXGBE_ERR_CONFIG
;
2081 * If EEPROM is detected and can be addressed using 14 bits,
2082 * use EERD otherwise use bit bang
2084 if ((eeprom
->type
== ixgbe_eeprom_spi
) &&
2085 (offset
<= IXGBE_EERD_MAX_ADDR
))
2086 ret_val
= ixgbe_read_eerd_generic(hw
, offset
, data
);
2088 ret_val
= ixgbe_read_eeprom_bit_bang_generic(hw
, offset
, data
);
2093 static struct ixgbe_mac_operations mac_ops_82599
= {
2094 .init_hw
= &ixgbe_init_hw_generic
,
2095 .reset_hw
= &ixgbe_reset_hw_82599
,
2096 .start_hw
= &ixgbe_start_hw_82599
,
2097 .clear_hw_cntrs
= &ixgbe_clear_hw_cntrs_generic
,
2098 .get_media_type
= &ixgbe_get_media_type_82599
,
2099 .get_supported_physical_layer
= &ixgbe_get_supported_physical_layer_82599
,
2100 .enable_rx_dma
= &ixgbe_enable_rx_dma_82599
,
2101 .get_mac_addr
= &ixgbe_get_mac_addr_generic
,
2102 .get_san_mac_addr
= &ixgbe_get_san_mac_addr_generic
,
2103 .get_device_caps
= &ixgbe_get_device_caps_generic
,
2104 .get_wwn_prefix
= &ixgbe_get_wwn_prefix_generic
,
2105 .stop_adapter
= &ixgbe_stop_adapter_generic
,
2106 .get_bus_info
= &ixgbe_get_bus_info_generic
,
2107 .set_lan_id
= &ixgbe_set_lan_id_multi_port_pcie
,
2108 .read_analog_reg8
= &ixgbe_read_analog_reg8_82599
,
2109 .write_analog_reg8
= &ixgbe_write_analog_reg8_82599
,
2110 .setup_link
= &ixgbe_setup_mac_link_82599
,
2111 .set_rxpba
= &ixgbe_set_rxpba_generic
,
2112 .check_link
= &ixgbe_check_mac_link_generic
,
2113 .get_link_capabilities
= &ixgbe_get_link_capabilities_82599
,
2114 .led_on
= &ixgbe_led_on_generic
,
2115 .led_off
= &ixgbe_led_off_generic
,
2116 .blink_led_start
= &ixgbe_blink_led_start_generic
,
2117 .blink_led_stop
= &ixgbe_blink_led_stop_generic
,
2118 .set_rar
= &ixgbe_set_rar_generic
,
2119 .clear_rar
= &ixgbe_clear_rar_generic
,
2120 .set_vmdq
= &ixgbe_set_vmdq_generic
,
2121 .clear_vmdq
= &ixgbe_clear_vmdq_generic
,
2122 .init_rx_addrs
= &ixgbe_init_rx_addrs_generic
,
2123 .update_mc_addr_list
= &ixgbe_update_mc_addr_list_generic
,
2124 .enable_mc
= &ixgbe_enable_mc_generic
,
2125 .disable_mc
= &ixgbe_disable_mc_generic
,
2126 .clear_vfta
= &ixgbe_clear_vfta_generic
,
2127 .set_vfta
= &ixgbe_set_vfta_generic
,
2128 .fc_enable
= &ixgbe_fc_enable_generic
,
2129 .init_uta_tables
= &ixgbe_init_uta_tables_generic
,
2130 .setup_sfp
= &ixgbe_setup_sfp_modules_82599
,
2131 .set_mac_anti_spoofing
= &ixgbe_set_mac_anti_spoofing
,
2132 .set_vlan_anti_spoofing
= &ixgbe_set_vlan_anti_spoofing
,
2133 .acquire_swfw_sync
= &ixgbe_acquire_swfw_sync
,
2134 .release_swfw_sync
= &ixgbe_release_swfw_sync
,
2138 static struct ixgbe_eeprom_operations eeprom_ops_82599
= {
2139 .init_params
= &ixgbe_init_eeprom_params_generic
,
2140 .read
= &ixgbe_read_eeprom_82599
,
2141 .read_buffer
= &ixgbe_read_eeprom_buffer_82599
,
2142 .write
= &ixgbe_write_eeprom_generic
,
2143 .write_buffer
= &ixgbe_write_eeprom_buffer_bit_bang_generic
,
2144 .calc_checksum
= &ixgbe_calc_eeprom_checksum_generic
,
2145 .validate_checksum
= &ixgbe_validate_eeprom_checksum_generic
,
2146 .update_checksum
= &ixgbe_update_eeprom_checksum_generic
,
2149 static struct ixgbe_phy_operations phy_ops_82599
= {
2150 .identify
= &ixgbe_identify_phy_82599
,
2151 .identify_sfp
= &ixgbe_identify_sfp_module_generic
,
2152 .init
= &ixgbe_init_phy_ops_82599
,
2153 .reset
= &ixgbe_reset_phy_generic
,
2154 .read_reg
= &ixgbe_read_phy_reg_generic
,
2155 .write_reg
= &ixgbe_write_phy_reg_generic
,
2156 .setup_link
= &ixgbe_setup_phy_link_generic
,
2157 .setup_link_speed
= &ixgbe_setup_phy_link_speed_generic
,
2158 .read_i2c_byte
= &ixgbe_read_i2c_byte_generic
,
2159 .write_i2c_byte
= &ixgbe_write_i2c_byte_generic
,
2160 .read_i2c_eeprom
= &ixgbe_read_i2c_eeprom_generic
,
2161 .write_i2c_eeprom
= &ixgbe_write_i2c_eeprom_generic
,
2162 .check_overtemp
= &ixgbe_tn_check_overtemp
,
2165 struct ixgbe_info ixgbe_82599_info
= {
2166 .mac
= ixgbe_mac_82599EB
,
2167 .get_invariants
= &ixgbe_get_invariants_82599
,
2168 .mac_ops
= &mac_ops_82599
,
2169 .eeprom_ops
= &eeprom_ops_82599
,
2170 .phy_ops
= &phy_ops_82599
,
2171 .mbx_ops
= &mbx_ops_generic
,