projects / deliverable / linux.git / blob
? search:


976fd9e146c6b5479c63b43d835a4f0200e10353
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_82599.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe.h"
33 #include "ixgbe_phy.h"
34 #include "ixgbe_mbx.h"
35
36 #define IXGBE_82599_MAX_TX_QUEUES 128
37 #define IXGBE_82599_MAX_RX_QUEUES 128
38 #define IXGBE_82599_RAR_ENTRIES 128
39 #define IXGBE_82599_MC_TBL_SIZE 128
40 #define IXGBE_82599_VFT_TBL_SIZE 128
41
42 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
43 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
44 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
45 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
46 ixgbe_link_speed speed,
47 bool autoneg,
48 bool autoneg_wait_to_complete);
49 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
50 ixgbe_link_speed speed,
51 bool autoneg,
52 bool autoneg_wait_to_complete);
53 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
54 bool autoneg_wait_to_complete);
55 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
56 ixgbe_link_speed speed,
57 bool autoneg,
58 bool autoneg_wait_to_complete);
59 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
60 ixgbe_link_speed *speed,
61 bool *autoneg);
62 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
63 ixgbe_link_speed speed,
64 bool autoneg,
65 bool autoneg_wait_to_complete);
66 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
67
68 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
69 {
70 struct ixgbe_mac_info *mac = &hw->mac;
71 if (hw->phy.multispeed_fiber) {
72 /* Set up dual speed SFP+ support */
73 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
74 mac->ops.disable_tx_laser =
75 &ixgbe_disable_tx_laser_multispeed_fiber;
76 mac->ops.enable_tx_laser =
77 &ixgbe_enable_tx_laser_multispeed_fiber;
78 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
79 } else {
80 mac->ops.disable_tx_laser = NULL;
81 mac->ops.enable_tx_laser = NULL;
82 mac->ops.flap_tx_laser = NULL;
83 if ((mac->ops.get_media_type(hw) ==
84 ixgbe_media_type_backplane) &&
85 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
86 hw->phy.smart_speed == ixgbe_smart_speed_on))
87 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
88 else
89 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
90 }
91 }
92
93 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
94 {
95 s32 ret_val = 0;
96 u16 list_offset, data_offset, data_value;
97
98 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
99 ixgbe_init_mac_link_ops_82599(hw);
100
101 hw->phy.ops.reset = NULL;
102
103 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
104 &data_offset);
105
106 if (ret_val != 0)
107 goto setup_sfp_out;
108
109 /* PHY config will finish before releasing the semaphore */
110 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
111 if (ret_val != 0) {
112 ret_val = IXGBE_ERR_SWFW_SYNC;
113 goto setup_sfp_out;
114 }
115
116 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
117 while (data_value != 0xffff) {
118 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
119 IXGBE_WRITE_FLUSH(hw);
120 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
121 }
122 /* Now restart DSP by setting Restart_AN */
123 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
124 (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART));
125
126 /* Release the semaphore */
127 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
128 /* Delay obtaining semaphore again to allow FW access */
129 msleep(hw->eeprom.semaphore_delay);
130 }
131
132 setup_sfp_out:
133 return ret_val;
134 }
135
136 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
137 {
138 struct ixgbe_mac_info *mac = &hw->mac;
139
140 ixgbe_init_mac_link_ops_82599(hw);
141
142 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
143 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
144 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
145 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
146 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
147 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
148
149 return 0;
150 }
151
152 /**
153 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
154 * @hw: pointer to hardware structure
155 *
156 * Initialize any function pointers that were not able to be
157 * set during get_invariants because the PHY/SFP type was
158 * not known. Perform the SFP init if necessary.
159 *
160 **/
161 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
162 {
163 struct ixgbe_mac_info *mac = &hw->mac;
164 struct ixgbe_phy_info *phy = &hw->phy;
165 s32 ret_val = 0;
166
167 /* Identify the PHY or SFP module */
168 ret_val = phy->ops.identify(hw);
169
170 /* Setup function pointers based on detected SFP module and speeds */
171 ixgbe_init_mac_link_ops_82599(hw);
172
173 /* If copper media, overwrite with copper function pointers */
174 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
175 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
176 mac->ops.get_link_capabilities =
177 &ixgbe_get_copper_link_capabilities_82599;
178 }
179
180 /* Set necessary function pointers based on phy type */
181 switch (hw->phy.type) {
182 case ixgbe_phy_tn:
183 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
184 phy->ops.get_firmware_version =
185 &ixgbe_get_phy_firmware_version_tnx;
186 break;
187 default:
188 break;
189 }
190
191 return ret_val;
192 }
193
194 /**
195 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
196 * @hw: pointer to hardware structure
197 * @speed: pointer to link speed
198 * @negotiation: true when autoneg or autotry is enabled
199 *
200 * Determines the link capabilities by reading the AUTOC register.
201 **/
202 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
203 ixgbe_link_speed *speed,
204 bool *negotiation)
205 {
206 s32 status = 0;
207 u32 autoc = 0;
208
209 /*
210 * Determine link capabilities based on the stored value of AUTOC,
211 * which represents EEPROM defaults. If AUTOC value has not been
212 * stored, use the current register value.
213 */
214 if (hw->mac.orig_link_settings_stored)
215 autoc = hw->mac.orig_autoc;
216 else
217 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
218
219 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
220 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
221 *speed = IXGBE_LINK_SPEED_1GB_FULL;
222 *negotiation = false;
223 break;
224
225 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
226 *speed = IXGBE_LINK_SPEED_10GB_FULL;
227 *negotiation = false;
228 break;
229
230 case IXGBE_AUTOC_LMS_1G_AN:
231 *speed = IXGBE_LINK_SPEED_1GB_FULL;
232 *negotiation = true;
233 break;
234
235 case IXGBE_AUTOC_LMS_10G_SERIAL:
236 *speed = IXGBE_LINK_SPEED_10GB_FULL;
237 *negotiation = false;
238 break;
239
240 case IXGBE_AUTOC_LMS_KX4_KX_KR:
241 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
242 *speed = IXGBE_LINK_SPEED_UNKNOWN;
243 if (autoc & IXGBE_AUTOC_KR_SUPP)
244 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
245 if (autoc & IXGBE_AUTOC_KX4_SUPP)
246 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
247 if (autoc & IXGBE_AUTOC_KX_SUPP)
248 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
249 *negotiation = true;
250 break;
251
252 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
253 *speed = IXGBE_LINK_SPEED_100_FULL;
254 if (autoc & IXGBE_AUTOC_KR_SUPP)
255 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
256 if (autoc & IXGBE_AUTOC_KX4_SUPP)
257 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
258 if (autoc & IXGBE_AUTOC_KX_SUPP)
259 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
260 *negotiation = true;
261 break;
262
263 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
264 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
265 *negotiation = false;
266 break;
267
268 default:
269 status = IXGBE_ERR_LINK_SETUP;
270 goto out;
271 break;
272 }
273
274 if (hw->phy.multispeed_fiber) {
275 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
276 IXGBE_LINK_SPEED_1GB_FULL;
277 *negotiation = true;
278 }
279
280 out:
281 return status;
282 }
283
284 /**
285 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
286 * @hw: pointer to hardware structure
287 * @speed: pointer to link speed
288 * @autoneg: boolean auto-negotiation value
289 *
290 * Determines the link capabilities by reading the AUTOC register.
291 **/
292 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
293 ixgbe_link_speed *speed,
294 bool *autoneg)
295 {
296 s32 status = IXGBE_ERR_LINK_SETUP;
297 u16 speed_ability;
298
299 *speed = 0;
300 *autoneg = true;
301
302 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
303 &speed_ability);
304
305 if (status == 0) {
306 if (speed_ability & MDIO_SPEED_10G)
307 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
308 if (speed_ability & MDIO_PMA_SPEED_1000)
309 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
310 }
311
312 return status;
313 }
314
315 /**
316 * ixgbe_get_media_type_82599 - Get media type
317 * @hw: pointer to hardware structure
318 *
319 * Returns the media type (fiber, copper, backplane)
320 **/
321 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
322 {
323 enum ixgbe_media_type media_type;
324
325 /* Detect if there is a copper PHY attached. */
326 if (hw->phy.type == ixgbe_phy_cu_unknown ||
327 hw->phy.type == ixgbe_phy_tn) {
328 media_type = ixgbe_media_type_copper;
329 goto out;
330 }
331
332 switch (hw->device_id) {
333 case IXGBE_DEV_ID_82599_KX4:
334 case IXGBE_DEV_ID_82599_KX4_MEZZ:
335 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
336 case IXGBE_DEV_ID_82599_KR:
337 case IXGBE_DEV_ID_82599_XAUI_LOM:
338 /* Default device ID is mezzanine card KX/KX4 */
339 media_type = ixgbe_media_type_backplane;
340 break;
341 case IXGBE_DEV_ID_82599_SFP:
342 case IXGBE_DEV_ID_82599_SFP_EM:
343 media_type = ixgbe_media_type_fiber;
344 break;
345 case IXGBE_DEV_ID_82599_CX4:
346 media_type = ixgbe_media_type_cx4;
347 break;
348 default:
349 media_type = ixgbe_media_type_unknown;
350 break;
351 }
352 out:
353 return media_type;
354 }
355
356 /**
357 * ixgbe_start_mac_link_82599 - Setup MAC link settings
358 * @hw: pointer to hardware structure
359 * @autoneg_wait_to_complete: true when waiting for completion is needed
360 *
361 * Configures link settings based on values in the ixgbe_hw struct.
362 * Restarts the link. Performs autonegotiation if needed.
363 **/
364 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
365 bool autoneg_wait_to_complete)
366 {
367 u32 autoc_reg;
368 u32 links_reg;
369 u32 i;
370 s32 status = 0;
371
372 /* Restart link */
373 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
374 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
375 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
376
377 /* Only poll for autoneg to complete if specified to do so */
378 if (autoneg_wait_to_complete) {
379 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
380 IXGBE_AUTOC_LMS_KX4_KX_KR ||
381 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
382 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
383 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
384 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
385 links_reg = 0; /* Just in case Autoneg time = 0 */
386 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
387 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
388 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
389 break;
390 msleep(100);
391 }
392 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
393 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
394 hw_dbg(hw, "Autoneg did not complete.\n");
395 }
396 }
397 }
398
399 /* Add delay to filter out noises during initial link setup */
400 msleep(50);
401
402 return status;
403 }
404
405 /**
406 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
407 * @hw: pointer to hardware structure
408 *
409 * The base drivers may require better control over SFP+ module
410 * PHY states. This includes selectively shutting down the Tx
411 * laser on the PHY, effectively halting physical link.
412 **/
413 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
414 {
415 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
416
417 /* Disable tx laser; allow 100us to go dark per spec */
418 esdp_reg |= IXGBE_ESDP_SDP3;
419 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
420 IXGBE_WRITE_FLUSH(hw);
421 udelay(100);
422 }
423
424 /**
425 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
426 * @hw: pointer to hardware structure
427 *
428 * The base drivers may require better control over SFP+ module
429 * PHY states. This includes selectively turning on the Tx
430 * laser on the PHY, effectively starting physical link.
431 **/
432 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
433 {
434 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
435
436 /* Enable tx laser; allow 100ms to light up */
437 esdp_reg &= ~IXGBE_ESDP_SDP3;
438 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
439 IXGBE_WRITE_FLUSH(hw);
440 msleep(100);
441 }
442
443 /**
444 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
445 * @hw: pointer to hardware structure
446 *
447 * When the driver changes the link speeds that it can support,
448 * it sets autotry_restart to true to indicate that we need to
449 * initiate a new autotry session with the link partner. To do
450 * so, we set the speed then disable and re-enable the tx laser, to
451 * alert the link partner that it also needs to restart autotry on its
452 * end. This is consistent with true clause 37 autoneg, which also
453 * involves a loss of signal.
454 **/
455 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
456 {
457 hw_dbg(hw, "ixgbe_flap_tx_laser_multispeed_fiber\n");
458
459 if (hw->mac.autotry_restart) {
460 ixgbe_disable_tx_laser_multispeed_fiber(hw);
461 ixgbe_enable_tx_laser_multispeed_fiber(hw);
462 hw->mac.autotry_restart = false;
463 }
464 }
465
466 /**
467 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
468 * @hw: pointer to hardware structure
469 * @speed: new link speed
470 * @autoneg: true if autonegotiation enabled
471 * @autoneg_wait_to_complete: true when waiting for completion is needed
472 *
473 * Set the link speed in the AUTOC register and restarts link.
474 **/
475 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
476 ixgbe_link_speed speed,
477 bool autoneg,
478 bool autoneg_wait_to_complete)
479 {
480 s32 status = 0;
481 ixgbe_link_speed phy_link_speed;
482 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
483 u32 speedcnt = 0;
484 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
485 bool link_up = false;
486 bool negotiation;
487 int i;
488
489 /* Mask off requested but non-supported speeds */
490 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
491 speed &= phy_link_speed;
492
493 /*
494 * Try each speed one by one, highest priority first. We do this in
495 * software because 10gb fiber doesn't support speed autonegotiation.
496 */
497 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
498 speedcnt++;
499 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
500
501 /* If we already have link at this speed, just jump out */
502 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
503
504 if ((phy_link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
505 goto out;
506
507 /* Set the module link speed */
508 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
509 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
510 IXGBE_WRITE_FLUSH(hw);
511
512 /* Allow module to change analog characteristics (1G->10G) */
513 msleep(40);
514
515 status = ixgbe_setup_mac_link_82599(hw,
516 IXGBE_LINK_SPEED_10GB_FULL,
517 autoneg,
518 autoneg_wait_to_complete);
519 if (status != 0)
520 return status;
521
522 /* Flap the tx laser if it has not already been done */
523 hw->mac.ops.flap_tx_laser(hw);
524
525 /*
526 * Wait for the controller to acquire link. Per IEEE 802.3ap,
527 * Section 73.10.2, we may have to wait up to 500ms if KR is
528 * attempted. 82599 uses the same timing for 10g SFI.
529 */
530
531 for (i = 0; i < 5; i++) {
532 /* Wait for the link partner to also set speed */
533 msleep(100);
534
535 /* If we have link, just jump out */
536 hw->mac.ops.check_link(hw, &phy_link_speed,
537 &link_up, false);
538 if (link_up)
539 goto out;
540 }
541 }
542
543 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
544 speedcnt++;
545 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
546 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
547
548 /* If we already have link at this speed, just jump out */
549 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
550
551 if ((phy_link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
552 goto out;
553
554 /* Set the module link speed */
555 esdp_reg &= ~IXGBE_ESDP_SDP5;
556 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
557 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
558 IXGBE_WRITE_FLUSH(hw);
559
560 /* Allow module to change analog characteristics (10G->1G) */
561 msleep(40);
562
563 status = ixgbe_setup_mac_link_82599(hw,
564 IXGBE_LINK_SPEED_1GB_FULL,
565 autoneg,
566 autoneg_wait_to_complete);
567 if (status != 0)
568 return status;
569
570 /* Flap the tx laser if it has not already been done */
571 hw->mac.ops.flap_tx_laser(hw);
572
573 /* Wait for the link partner to also set speed */
574 msleep(100);
575
576 /* If we have link, just jump out */
577 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
578 if (link_up)
579 goto out;
580 }
581
582 /*
583 * We didn't get link. Configure back to the highest speed we tried,
584 * (if there was more than one). We call ourselves back with just the
585 * single highest speed that the user requested.
586 */
587 if (speedcnt > 1)
588 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
589 highest_link_speed,
590 autoneg,
591 autoneg_wait_to_complete);
592
593 out:
594 /* Set autoneg_advertised value based on input link speed */
595 hw->phy.autoneg_advertised = 0;
596
597 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
598 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
599
600 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
601 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
602
603 return status;
604 }
605
606 /**
607 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
608 * @hw: pointer to hardware structure
609 * @speed: new link speed
610 * @autoneg: true if autonegotiation enabled
611 * @autoneg_wait_to_complete: true when waiting for completion is needed
612 *
613 * Implements the Intel SmartSpeed algorithm.
614 **/
615 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
616 ixgbe_link_speed speed, bool autoneg,
617 bool autoneg_wait_to_complete)
618 {
619 s32 status = 0;
620 ixgbe_link_speed link_speed;
621 s32 i, j;
622 bool link_up = false;
623 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
624 struct ixgbe_adapter *adapter = hw->back;
625
626 hw_dbg(hw, "ixgbe_setup_mac_link_smartspeed.\n");
627
628 /* Set autoneg_advertised value based on input link speed */
629 hw->phy.autoneg_advertised = 0;
630
631 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
632 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
633
634 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
635 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
636
637 if (speed & IXGBE_LINK_SPEED_100_FULL)
638 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
639
640 /*
641 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
642 * autoneg advertisement if link is unable to be established at the
643 * highest negotiated rate. This can sometimes happen due to integrity
644 * issues with the physical media connection.
645 */
646
647 /* First, try to get link with full advertisement */
648 hw->phy.smart_speed_active = false;
649 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
650 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
651 autoneg_wait_to_complete);
652 if (status)
653 goto out;
654
655 /*
656 * Wait for the controller to acquire link. Per IEEE 802.3ap,
657 * Section 73.10.2, we may have to wait up to 500ms if KR is
658 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
659 * Table 9 in the AN MAS.
660 */
661 for (i = 0; i < 5; i++) {
662 mdelay(100);
663
664 /* If we have link, just jump out */
665 hw->mac.ops.check_link(hw, &link_speed,
666 &link_up, false);
667 if (link_up)
668 goto out;
669 }
670 }
671
672 /*
673 * We didn't get link. If we advertised KR plus one of KX4/KX
674 * (or BX4/BX), then disable KR and try again.
675 */
676 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
677 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
678 goto out;
679
680 /* Turn SmartSpeed on to disable KR support */
681 hw->phy.smart_speed_active = true;
682 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
683 autoneg_wait_to_complete);
684 if (status)
685 goto out;
686
687 /*
688 * Wait for the controller to acquire link. 600ms will allow for
689 * the AN link_fail_inhibit_timer as well for multiple cycles of
690 * parallel detect, both 10g and 1g. This allows for the maximum
691 * connect attempts as defined in the AN MAS table 73-7.
692 */
693 for (i = 0; i < 6; i++) {
694 mdelay(100);
695
696 /* If we have link, just jump out */
697 hw->mac.ops.check_link(hw, &link_speed,
698 &link_up, false);
699 if (link_up)
700 goto out;
701 }
702
703 /* We didn't get link. Turn SmartSpeed back off. */
704 hw->phy.smart_speed_active = false;
705 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
706 autoneg_wait_to_complete);
707
708 out:
709 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
710 e_info("Smartspeed has downgraded the link speed from "
711 "the maximum advertised\n");
712 return status;
713 }
714
715 /**
716 * ixgbe_setup_mac_link_82599 - Set MAC link speed
717 * @hw: pointer to hardware structure
718 * @speed: new link speed
719 * @autoneg: true if autonegotiation enabled
720 * @autoneg_wait_to_complete: true when waiting for completion is needed
721 *
722 * Set the link speed in the AUTOC register and restarts link.
723 **/
724 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
725 ixgbe_link_speed speed, bool autoneg,
726 bool autoneg_wait_to_complete)
727 {
728 s32 status = 0;
729 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
730 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
731 u32 start_autoc = autoc;
732 u32 orig_autoc = 0;
733 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
734 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
735 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
736 u32 links_reg;
737 u32 i;
738 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
739
740 /* Check to see if speed passed in is supported. */
741 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
742 speed &= link_capabilities;
743
744 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
745 status = IXGBE_ERR_LINK_SETUP;
746 goto out;
747 }
748
749 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
750 if (hw->mac.orig_link_settings_stored)
751 orig_autoc = hw->mac.orig_autoc;
752 else
753 orig_autoc = autoc;
754
755
756 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
757 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
758 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
759 /* Set KX4/KX/KR support according to speed requested */
760 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
761 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
762 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
763 autoc |= IXGBE_AUTOC_KX4_SUPP;
764 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
765 (hw->phy.smart_speed_active == false))
766 autoc |= IXGBE_AUTOC_KR_SUPP;
767 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
768 autoc |= IXGBE_AUTOC_KX_SUPP;
769 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
770 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
771 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
772 /* Switch from 1G SFI to 10G SFI if requested */
773 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
774 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
775 autoc &= ~IXGBE_AUTOC_LMS_MASK;
776 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
777 }
778 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
779 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
780 /* Switch from 10G SFI to 1G SFI if requested */
781 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
782 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
783 autoc &= ~IXGBE_AUTOC_LMS_MASK;
784 if (autoneg)
785 autoc |= IXGBE_AUTOC_LMS_1G_AN;
786 else
787 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
788 }
789 }
790
791 if (autoc != start_autoc) {
792 /* Restart link */
793 autoc |= IXGBE_AUTOC_AN_RESTART;
794 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
795
796 /* Only poll for autoneg to complete if specified to do so */
797 if (autoneg_wait_to_complete) {
798 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
799 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
800 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
801 links_reg = 0; /*Just in case Autoneg time=0*/
802 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
803 links_reg =
804 IXGBE_READ_REG(hw, IXGBE_LINKS);
805 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
806 break;
807 msleep(100);
808 }
809 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
810 status =
811 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
812 hw_dbg(hw, "Autoneg did not "
813 "complete.\n");
814 }
815 }
816 }
817
818 /* Add delay to filter out noises during initial link setup */
819 msleep(50);
820 }
821
822 out:
823 return status;
824 }
825
826 /**
827 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
828 * @hw: pointer to hardware structure
829 * @speed: new link speed
830 * @autoneg: true if autonegotiation enabled
831 * @autoneg_wait_to_complete: true if waiting is needed to complete
832 *
833 * Restarts link on PHY and MAC based on settings passed in.
834 **/
835 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
836 ixgbe_link_speed speed,
837 bool autoneg,
838 bool autoneg_wait_to_complete)
839 {
840 s32 status;
841
842 /* Setup the PHY according to input speed */
843 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
844 autoneg_wait_to_complete);
845 /* Set up MAC */
846 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
847
848 return status;
849 }
850
851 /**
852 * ixgbe_reset_hw_82599 - Perform hardware reset
853 * @hw: pointer to hardware structure
854 *
855 * Resets the hardware by resetting the transmit and receive units, masks
856 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
857 * reset.
858 **/
859 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
860 {
861 s32 status = 0;
862 u32 ctrl;
863 u32 i;
864 u32 autoc;
865 u32 autoc2;
866
867 /* Call adapter stop to disable tx/rx and clear interrupts */
868 hw->mac.ops.stop_adapter(hw);
869
870 /* PHY ops must be identified and initialized prior to reset */
871
872 /* Init PHY and function pointers, perform SFP setup */
873 status = hw->phy.ops.init(hw);
874
875 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
876 goto reset_hw_out;
877
878 /* Setup SFP module if there is one present. */
879 if (hw->phy.sfp_setup_needed) {
880 status = hw->mac.ops.setup_sfp(hw);
881 hw->phy.sfp_setup_needed = false;
882 }
883
884 /* Reset PHY */
885 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
886 hw->phy.ops.reset(hw);
887
888 /*
889 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
890 * access and verify no pending requests before reset
891 */
892 status = ixgbe_disable_pcie_master(hw);
893 if (status != 0) {
894 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
895 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
896 }
897
898 /*
899 * Issue global reset to the MAC. This needs to be a SW reset.
900 * If link reset is used, it might reset the MAC when mng is using it
901 */
902 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
903 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
904 IXGBE_WRITE_FLUSH(hw);
905
906 /* Poll for reset bit to self-clear indicating reset is complete */
907 for (i = 0; i < 10; i++) {
908 udelay(1);
909 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
910 if (!(ctrl & IXGBE_CTRL_RST))
911 break;
912 }
913 if (ctrl & IXGBE_CTRL_RST) {
914 status = IXGBE_ERR_RESET_FAILED;
915 hw_dbg(hw, "Reset polling failed to complete.\n");
916 }
917
918 msleep(50);
919
920 /*
921 * Store the original AUTOC/AUTOC2 values if they have not been
922 * stored off yet. Otherwise restore the stored original
923 * values since the reset operation sets back to defaults.
924 */
925 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
926 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
927 if (hw->mac.orig_link_settings_stored == false) {
928 hw->mac.orig_autoc = autoc;
929 hw->mac.orig_autoc2 = autoc2;
930 hw->mac.orig_link_settings_stored = true;
931 } else {
932 if (autoc != hw->mac.orig_autoc)
933 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
934 IXGBE_AUTOC_AN_RESTART));
935
936 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
937 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
938 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
939 autoc2 |= (hw->mac.orig_autoc2 &
940 IXGBE_AUTOC2_UPPER_MASK);
941 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
942 }
943 }
944
945 /*
946 * Store MAC address from RAR0, clear receive address registers, and
947 * clear the multicast table. Also reset num_rar_entries to 128,
948 * since we modify this value when programming the SAN MAC address.
949 */
950 hw->mac.num_rar_entries = 128;
951 hw->mac.ops.init_rx_addrs(hw);
952
953 /* Store the permanent mac address */
954 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
955
956 /* Store the permanent SAN mac address */
957 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
958
959 /* Add the SAN MAC address to the RAR only if it's a valid address */
960 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
961 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
962 hw->mac.san_addr, 0, IXGBE_RAH_AV);
963
964 /* Reserve the last RAR for the SAN MAC address */
965 hw->mac.num_rar_entries--;
966 }
967
968 /* Store the alternative WWNN/WWPN prefix */
969 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
970 &hw->mac.wwpn_prefix);
971
972 reset_hw_out:
973 return status;
974 }
975
976 /**
977 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
978 * @hw: pointer to hardware structure
979 **/
980 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
981 {
982 int i;
983 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
984 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
985
986 /*
987 * Before starting reinitialization process,
988 * FDIRCMD.CMD must be zero.
989 */
990 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
991 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
992 IXGBE_FDIRCMD_CMD_MASK))
993 break;
994 udelay(10);
995 }
996 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
997 hw_dbg(hw ,"Flow Director previous command isn't complete, "
998 "aborting table re-initialization.\n");
999 return IXGBE_ERR_FDIR_REINIT_FAILED;
1000 }
1001
1002 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1003 IXGBE_WRITE_FLUSH(hw);
1004 /*
1005 * 82599 adapters flow director init flow cannot be restarted,
1006 * Workaround 82599 silicon errata by performing the following steps
1007 * before re-writing the FDIRCTRL control register with the same value.
1008 * - write 1 to bit 8 of FDIRCMD register &
1009 * - write 0 to bit 8 of FDIRCMD register
1010 */
1011 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1012 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1013 IXGBE_FDIRCMD_CLEARHT));
1014 IXGBE_WRITE_FLUSH(hw);
1015 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1016 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1017 ~IXGBE_FDIRCMD_CLEARHT));
1018 IXGBE_WRITE_FLUSH(hw);
1019 /*
1020 * Clear FDIR Hash register to clear any leftover hashes
1021 * waiting to be programmed.
1022 */
1023 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1024 IXGBE_WRITE_FLUSH(hw);
1025
1026 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1027 IXGBE_WRITE_FLUSH(hw);
1028
1029 /* Poll init-done after we write FDIRCTRL register */
1030 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1031 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1032 IXGBE_FDIRCTRL_INIT_DONE)
1033 break;
1034 udelay(10);
1035 }
1036 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1037 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1038 return IXGBE_ERR_FDIR_REINIT_FAILED;
1039 }
1040
1041 /* Clear FDIR statistics registers (read to clear) */
1042 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1043 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1044 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1045 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1046 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1047
1048 return 0;
1049 }
1050
1051 /**
1052 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1053 * @hw: pointer to hardware structure
1054 * @pballoc: which mode to allocate filters with
1055 **/
1056 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1057 {
1058 u32 fdirctrl = 0;
1059 u32 pbsize;
1060 int i;
1061
1062 /*
1063 * Before enabling Flow Director, the Rx Packet Buffer size
1064 * must be reduced. The new value is the current size minus
1065 * flow director memory usage size.
1066 */
1067 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1068 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1069 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1070
1071 /*
1072 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1073 * intialized to zero for non DCB mode otherwise actual total RX PB
1074 * would be bigger than programmed and filter space would run into
1075 * the PB 0 region.
1076 */
1077 for (i = 1; i < 8; i++)
1078 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1079
1080 /* Send interrupt when 64 filters are left */
1081 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1082
1083 /* Set the maximum length per hash bucket to 0xA filters */
1084 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT;
1085
1086 switch (pballoc) {
1087 case IXGBE_FDIR_PBALLOC_64K:
1088 /* 8k - 1 signature filters */
1089 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1090 break;
1091 case IXGBE_FDIR_PBALLOC_128K:
1092 /* 16k - 1 signature filters */
1093 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1094 break;
1095 case IXGBE_FDIR_PBALLOC_256K:
1096 /* 32k - 1 signature filters */
1097 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1098 break;
1099 default:
1100 /* bad value */
1101 return IXGBE_ERR_CONFIG;
1102 };
1103
1104 /* Move the flexible bytes to use the ethertype - shift 6 words */
1105 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1106
1107 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1108
1109 /* Prime the keys for hashing */
1110 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1111 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1112 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1113 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1114
1115 /*
1116 * Poll init-done after we write the register. Estimated times:
1117 * 10G: PBALLOC = 11b, timing is 60us
1118 * 1G: PBALLOC = 11b, timing is 600us
1119 * 100M: PBALLOC = 11b, timing is 6ms
1120 *
1121 * Multiple these timings by 4 if under full Rx load
1122 *
1123 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1124 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1125 * this might not finish in our poll time, but we can live with that
1126 * for now.
1127 */
1128 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1129 IXGBE_WRITE_FLUSH(hw);
1130 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1131 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1132 IXGBE_FDIRCTRL_INIT_DONE)
1133 break;
1134 msleep(1);
1135 }
1136 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1137 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1138
1139 return 0;
1140 }
1141
1142 /**
1143 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1144 * @hw: pointer to hardware structure
1145 * @pballoc: which mode to allocate filters with
1146 **/
1147 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1148 {
1149 u32 fdirctrl = 0;
1150 u32 pbsize;
1151 int i;
1152
1153 /*
1154 * Before enabling Flow Director, the Rx Packet Buffer size
1155 * must be reduced. The new value is the current size minus
1156 * flow director memory usage size.
1157 */
1158 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1159 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1160 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1161
1162 /*
1163 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1164 * intialized to zero for non DCB mode otherwise actual total RX PB
1165 * would be bigger than programmed and filter space would run into
1166 * the PB 0 region.
1167 */
1168 for (i = 1; i < 8; i++)
1169 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1170
1171 /* Send interrupt when 64 filters are left */
1172 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1173
1174 /* Initialize the drop queue to Rx queue 127 */
1175 fdirctrl |= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
1176
1177 switch (pballoc) {
1178 case IXGBE_FDIR_PBALLOC_64K:
1179 /* 2k - 1 perfect filters */
1180 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1181 break;
1182 case IXGBE_FDIR_PBALLOC_128K:
1183 /* 4k - 1 perfect filters */
1184 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1185 break;
1186 case IXGBE_FDIR_PBALLOC_256K:
1187 /* 8k - 1 perfect filters */
1188 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1189 break;
1190 default:
1191 /* bad value */
1192 return IXGBE_ERR_CONFIG;
1193 };
1194
1195 /* Turn perfect match filtering on */
1196 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
1197 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1198
1199 /* Move the flexible bytes to use the ethertype - shift 6 words */
1200 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1201
1202 /* Prime the keys for hashing */
1203 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1204 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1205 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1206 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1207
1208 /*
1209 * Poll init-done after we write the register. Estimated times:
1210 * 10G: PBALLOC = 11b, timing is 60us
1211 * 1G: PBALLOC = 11b, timing is 600us
1212 * 100M: PBALLOC = 11b, timing is 6ms
1213 *
1214 * Multiple these timings by 4 if under full Rx load
1215 *
1216 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1217 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1218 * this might not finish in our poll time, but we can live with that
1219 * for now.
1220 */
1221
1222 /* Set the maximum length per hash bucket to 0xA filters */
1223 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT);
1224
1225 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1226 IXGBE_WRITE_FLUSH(hw);
1227 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1228 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1229 IXGBE_FDIRCTRL_INIT_DONE)
1230 break;
1231 msleep(1);
1232 }
1233 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1234 hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
1235
1236 return 0;
1237 }
1238
1239
1240 /**
1241 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1242 * @stream: input bitstream to compute the hash on
1243 * @key: 32-bit hash key
1244 **/
1245 static u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input,
1246 u32 key)
1247 {
1248 /*
1249 * The algorithm is as follows:
1250 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1251 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1252 * and A[n] x B[n] is bitwise AND between same length strings
1253 *
1254 * K[n] is 16 bits, defined as:
1255 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1256 * for n modulo 32 < 15, K[n] =
1257 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1258 *
1259 * S[n] is 16 bits, defined as:
1260 * for n >= 15, S[n] = S[n:n - 15]
1261 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1262 *
1263 * To simplify for programming, the algorithm is implemented
1264 * in software this way:
1265 *
1266 * Key[31:0], Stream[335:0]
1267 *
1268 * tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times
1269 * int_key[350:0] = tmp_key[351:1]
1270 * int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321]
1271 *
1272 * hash[15:0] = 0;
1273 * for (i = 0; i < 351; i++) {
1274 * if (int_key[i])
1275 * hash ^= int_stream[(i + 15):i];
1276 * }
1277 */
1278
1279 union {
1280 u64 fill[6];
1281 u32 key[11];
1282 u8 key_stream[44];
1283 } tmp_key;
1284
1285 u8 *stream = (u8 *)atr_input;
1286 u8 int_key[44]; /* upper-most bit unused */
1287 u8 hash_str[46]; /* upper-most 2 bits unused */
1288 u16 hash_result = 0;
1289 int i, j, k, h;
1290
1291 /*
1292 * Initialize the fill member to prevent warnings
1293 * on some compilers
1294 */
1295 tmp_key.fill[0] = 0;
1296
1297 /* First load the temporary key stream */
1298 for (i = 0; i < 6; i++) {
1299 u64 fillkey = ((u64)key << 32) | key;
1300 tmp_key.fill[i] = fillkey;
1301 }
1302
1303 /*
1304 * Set the interim key for the hashing. Bit 352 is unused, so we must
1305 * shift and compensate when building the key.
1306 */
1307
1308 int_key[0] = tmp_key.key_stream[0] >> 1;
1309 for (i = 1, j = 0; i < 44; i++) {
1310 unsigned int this_key = tmp_key.key_stream[j] << 7;
1311 j++;
1312 int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1));
1313 }
1314
1315 /*
1316 * Set the interim bit string for the hashing. Bits 368 and 367 are
1317 * unused, so shift and compensate when building the string.
1318 */
1319 hash_str[0] = (stream[40] & 0x7f) >> 1;
1320 for (i = 1, j = 40; i < 46; i++) {
1321 unsigned int this_str = stream[j] << 7;
1322 j++;
1323 if (j > 41)
1324 j = 0;
1325 hash_str[i] = (u8)(this_str | (stream[j] >> 1));
1326 }
1327
1328 /*
1329 * Now compute the hash. i is the index into hash_str, j is into our
1330 * key stream, k is counting the number of bits, and h interates within
1331 * each byte.
1332 */
1333 for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) {
1334 for (h = 0; h < 8 && k < 351; h++, k++) {
1335 if (int_key[j] & (1 << h)) {
1336 /*
1337 * Key bit is set, XOR in the current 16-bit
1338 * string. Example of processing:
1339 * h = 0,
1340 * tmp = (hash_str[i - 2] & 0 << 16) |
1341 * (hash_str[i - 1] & 0xff << 8) |
1342 * (hash_str[i] & 0xff >> 0)
1343 * So tmp = hash_str[15 + k:k], since the
1344 * i + 2 clause rolls off the 16-bit value
1345 * h = 7,
1346 * tmp = (hash_str[i - 2] & 0x7f << 9) |
1347 * (hash_str[i - 1] & 0xff << 1) |
1348 * (hash_str[i] & 0x80 >> 7)
1349 */
1350 int tmp = (hash_str[i] >> h);
1351 tmp |= (hash_str[i - 1] << (8 - h));
1352 tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1))
1353 << (16 - h);
1354 hash_result ^= (u16)tmp;
1355 }
1356 }
1357 }
1358
1359 return hash_result;
1360 }
1361
1362 /**
1363 * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream
1364 * @input: input stream to modify
1365 * @vlan: the VLAN id to load
1366 **/
1367 s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan)
1368 {
1369 input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8;
1370 input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff;
1371
1372 return 0;
1373 }
1374
1375 /**
1376 * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address
1377 * @input: input stream to modify
1378 * @src_addr: the IP address to load
1379 **/
1380 s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr)
1381 {
1382 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24;
1383 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] =
1384 (src_addr >> 16) & 0xff;
1385 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] =
1386 (src_addr >> 8) & 0xff;
1387 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET] = src_addr & 0xff;
1388
1389 return 0;
1390 }
1391
1392 /**
1393 * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address
1394 * @input: input stream to modify
1395 * @dst_addr: the IP address to load
1396 **/
1397 s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr)
1398 {
1399 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24;
1400 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] =
1401 (dst_addr >> 16) & 0xff;
1402 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] =
1403 (dst_addr >> 8) & 0xff;
1404 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET] = dst_addr & 0xff;
1405
1406 return 0;
1407 }
1408
1409 /**
1410 * ixgbe_atr_set_src_ipv6_82599 - Sets the source IPv6 address
1411 * @input: input stream to modify
1412 * @src_addr_1: the first 4 bytes of the IP address to load
1413 * @src_addr_2: the second 4 bytes of the IP address to load
1414 * @src_addr_3: the third 4 bytes of the IP address to load
1415 * @src_addr_4: the fourth 4 bytes of the IP address to load
1416 **/
1417 s32 ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input,
1418 u32 src_addr_1, u32 src_addr_2,
1419 u32 src_addr_3, u32 src_addr_4)
1420 {
1421 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET] = src_addr_4 & 0xff;
1422 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] =
1423 (src_addr_4 >> 8) & 0xff;
1424 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] =
1425 (src_addr_4 >> 16) & 0xff;
1426 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] = src_addr_4 >> 24;
1427
1428 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4] = src_addr_3 & 0xff;
1429 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] =
1430 (src_addr_3 >> 8) & 0xff;
1431 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] =
1432 (src_addr_3 >> 16) & 0xff;
1433 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] = src_addr_3 >> 24;
1434
1435 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8] = src_addr_2 & 0xff;
1436 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] =
1437 (src_addr_2 >> 8) & 0xff;
1438 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] =
1439 (src_addr_2 >> 16) & 0xff;
1440 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] = src_addr_2 >> 24;
1441
1442 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12] = src_addr_1 & 0xff;
1443 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] =
1444 (src_addr_1 >> 8) & 0xff;
1445 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] =
1446 (src_addr_1 >> 16) & 0xff;
1447 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] = src_addr_1 >> 24;
1448
1449 return 0;
1450 }
1451
1452 /**
1453 * ixgbe_atr_set_dst_ipv6_82599 - Sets the destination IPv6 address
1454 * @input: input stream to modify
1455 * @dst_addr_1: the first 4 bytes of the IP address to load
1456 * @dst_addr_2: the second 4 bytes of the IP address to load
1457 * @dst_addr_3: the third 4 bytes of the IP address to load
1458 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1459 **/
1460 s32 ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input,
1461 u32 dst_addr_1, u32 dst_addr_2,
1462 u32 dst_addr_3, u32 dst_addr_4)
1463 {
1464 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET] = dst_addr_4 & 0xff;
1465 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] =
1466 (dst_addr_4 >> 8) & 0xff;
1467 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] =
1468 (dst_addr_4 >> 16) & 0xff;
1469 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] = dst_addr_4 >> 24;
1470
1471 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4] = dst_addr_3 & 0xff;
1472 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] =
1473 (dst_addr_3 >> 8) & 0xff;
1474 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] =
1475 (dst_addr_3 >> 16) & 0xff;
1476 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] = dst_addr_3 >> 24;
1477
1478 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8] = dst_addr_2 & 0xff;
1479 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] =
1480 (dst_addr_2 >> 8) & 0xff;
1481 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] =
1482 (dst_addr_2 >> 16) & 0xff;
1483 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] = dst_addr_2 >> 24;
1484
1485 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12] = dst_addr_1 & 0xff;
1486 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] =
1487 (dst_addr_1 >> 8) & 0xff;
1488 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] =
1489 (dst_addr_1 >> 16) & 0xff;
1490 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] = dst_addr_1 >> 24;
1491
1492 return 0;
1493 }
1494
1495 /**
1496 * ixgbe_atr_set_src_port_82599 - Sets the source port
1497 * @input: input stream to modify
1498 * @src_port: the source port to load
1499 **/
1500 s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port)
1501 {
1502 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8;
1503 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff;
1504
1505 return 0;
1506 }
1507
1508 /**
1509 * ixgbe_atr_set_dst_port_82599 - Sets the destination port
1510 * @input: input stream to modify
1511 * @dst_port: the destination port to load
1512 **/
1513 s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port)
1514 {
1515 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8;
1516 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff;
1517
1518 return 0;
1519 }
1520
1521 /**
1522 * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes
1523 * @input: input stream to modify
1524 * @flex_bytes: the flexible bytes to load
1525 **/
1526 s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte)
1527 {
1528 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8;
1529 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff;
1530
1531 return 0;
1532 }
1533
1534 /**
1535 * ixgbe_atr_set_vm_pool_82599 - Sets the Virtual Machine pool
1536 * @input: input stream to modify
1537 * @vm_pool: the Virtual Machine pool to load
1538 **/
1539 s32 ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input *input,
1540 u8 vm_pool)
1541 {
1542 input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET] = vm_pool;
1543
1544 return 0;
1545 }
1546
1547 /**
1548 * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type
1549 * @input: input stream to modify
1550 * @l4type: the layer 4 type value to load
1551 **/
1552 s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type)
1553 {
1554 input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type;
1555
1556 return 0;
1557 }
1558
1559 /**
1560 * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream
1561 * @input: input stream to search
1562 * @vlan: the VLAN id to load
1563 **/
1564 static s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input, u16 *vlan)
1565 {
1566 *vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET];
1567 *vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8;
1568
1569 return 0;
1570 }
1571
1572 /**
1573 * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address
1574 * @input: input stream to search
1575 * @src_addr: the IP address to load
1576 **/
1577 static s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input,
1578 u32 *src_addr)
1579 {
1580 *src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET];
1581 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8;
1582 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16;
1583 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] << 24;
1584
1585 return 0;
1586 }
1587
1588 /**
1589 * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address
1590 * @input: input stream to search
1591 * @dst_addr: the IP address to load
1592 **/
1593 static s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input,
1594 u32 *dst_addr)
1595 {
1596 *dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET];
1597 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8;
1598 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16;
1599 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] << 24;
1600
1601 return 0;
1602 }
1603
1604 /**
1605 * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address
1606 * @input: input stream to search
1607 * @src_addr_1: the first 4 bytes of the IP address to load
1608 * @src_addr_2: the second 4 bytes of the IP address to load
1609 * @src_addr_3: the third 4 bytes of the IP address to load
1610 * @src_addr_4: the fourth 4 bytes of the IP address to load
1611 **/
1612 static s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input,
1613 u32 *src_addr_1, u32 *src_addr_2,
1614 u32 *src_addr_3, u32 *src_addr_4)
1615 {
1616 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12];
1617 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8;
1618 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16;
1619 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] << 24;
1620
1621 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8];
1622 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] << 8;
1623 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] << 16;
1624 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] << 24;
1625
1626 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4];
1627 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] << 8;
1628 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] << 16;
1629 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] << 24;
1630
1631 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET];
1632 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] << 8;
1633 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] << 16;
1634 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] << 24;
1635
1636 return 0;
1637 }
1638
1639 /**
1640 * ixgbe_atr_get_dst_ipv6_82599 - Gets the destination IPv6 address
1641 * @input: input stream to search
1642 * @dst_addr_1: the first 4 bytes of the IP address to load
1643 * @dst_addr_2: the second 4 bytes of the IP address to load
1644 * @dst_addr_3: the third 4 bytes of the IP address to load
1645 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1646 **/
1647 s32 ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input *input,
1648 u32 *dst_addr_1, u32 *dst_addr_2,
1649 u32 *dst_addr_3, u32 *dst_addr_4)
1650 {
1651 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12];
1652 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] << 8;
1653 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] << 16;
1654 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] << 24;
1655
1656 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8];
1657 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] << 8;
1658 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] << 16;
1659 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] << 24;
1660
1661 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4];
1662 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] << 8;
1663 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] << 16;
1664 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] << 24;
1665
1666 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET];
1667 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] << 8;
1668 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] << 16;
1669 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] << 24;
1670
1671 return 0;
1672 }
1673
1674 /**
1675 * ixgbe_atr_get_src_port_82599 - Gets the source port
1676 * @input: input stream to modify
1677 * @src_port: the source port to load
1678 *
1679 * Even though the input is given in big-endian, the FDIRPORT registers
1680 * expect the ports to be programmed in little-endian. Hence the need to swap
1681 * endianness when retrieving the data. This can be confusing since the
1682 * internal hash engine expects it to be big-endian.
1683 **/
1684 static s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input,
1685 u16 *src_port)
1686 {
1687 *src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8;
1688 *src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1];
1689
1690 return 0;
1691 }
1692
1693 /**
1694 * ixgbe_atr_get_dst_port_82599 - Gets the destination port
1695 * @input: input stream to modify
1696 * @dst_port: the destination port to load
1697 *
1698 * Even though the input is given in big-endian, the FDIRPORT registers
1699 * expect the ports to be programmed in little-endian. Hence the need to swap
1700 * endianness when retrieving the data. This can be confusing since the
1701 * internal hash engine expects it to be big-endian.
1702 **/
1703 static s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input,
1704 u16 *dst_port)
1705 {
1706 *dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8;
1707 *dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1];
1708
1709 return 0;
1710 }
1711
1712 /**
1713 * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes
1714 * @input: input stream to modify
1715 * @flex_bytes: the flexible bytes to load
1716 **/
1717 static s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input,
1718 u16 *flex_byte)
1719 {
1720 *flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET];
1721 *flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8;
1722
1723 return 0;
1724 }
1725
1726 /**
1727 * ixgbe_atr_get_vm_pool_82599 - Gets the Virtual Machine pool
1728 * @input: input stream to modify
1729 * @vm_pool: the Virtual Machine pool to load
1730 **/
1731 s32 ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input *input,
1732 u8 *vm_pool)
1733 {
1734 *vm_pool = input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET];
1735
1736 return 0;
1737 }
1738
1739 /**
1740 * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type
1741 * @input: input stream to modify
1742 * @l4type: the layer 4 type value to load
1743 **/
1744 static s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input,
1745 u8 *l4type)
1746 {
1747 *l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET];
1748
1749 return 0;
1750 }
1751
1752 /**
1753 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1754 * @hw: pointer to hardware structure
1755 * @stream: input bitstream
1756 * @queue: queue index to direct traffic to
1757 **/
1758 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1759 struct ixgbe_atr_input *input,
1760 u8 queue)
1761 {
1762 u64 fdirhashcmd;
1763 u64 fdircmd;
1764 u32 fdirhash;
1765 u16 bucket_hash, sig_hash;
1766 u8 l4type;
1767
1768 bucket_hash = ixgbe_atr_compute_hash_82599(input,
1769 IXGBE_ATR_BUCKET_HASH_KEY);
1770
1771 /* bucket_hash is only 15 bits */
1772 bucket_hash &= IXGBE_ATR_HASH_MASK;
1773
1774 sig_hash = ixgbe_atr_compute_hash_82599(input,
1775 IXGBE_ATR_SIGNATURE_HASH_KEY);
1776
1777 /* Get the l4type in order to program FDIRCMD properly */
1778 /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */
1779 ixgbe_atr_get_l4type_82599(input, &l4type);
1780
1781 /*
1782 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1783 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1784 */
1785 fdirhash = sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
1786
1787 fdircmd = (IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1788 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN);
1789
1790 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1791 case IXGBE_ATR_L4TYPE_TCP:
1792 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
1793 break;
1794 case IXGBE_ATR_L4TYPE_UDP:
1795 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
1796 break;
1797 case IXGBE_ATR_L4TYPE_SCTP:
1798 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
1799 break;
1800 default:
1801 hw_dbg(hw, "Error on l4type input\n");
1802 return IXGBE_ERR_CONFIG;
1803 }
1804
1805 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK)
1806 fdircmd |= IXGBE_FDIRCMD_IPV6;
1807
1808 fdircmd |= ((u64)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT);
1809 fdirhashcmd = ((fdircmd << 32) | fdirhash);
1810
1811 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1812
1813 return 0;
1814 }
1815
1816 /**
1817 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1818 * @hw: pointer to hardware structure
1819 * @input: input bitstream
1820 * @input_masks: bitwise masks for relevant fields
1821 * @soft_id: software index into the silicon hash tables for filter storage
1822 * @queue: queue index to direct traffic to
1823 *
1824 * Note that the caller to this function must lock before calling, since the
1825 * hardware writes must be protected from one another.
1826 **/
1827 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1828 struct ixgbe_atr_input *input,
1829 struct ixgbe_atr_input_masks *input_masks,
1830 u16 soft_id, u8 queue)
1831 {
1832 u32 fdircmd = 0;
1833 u32 fdirhash;
1834 u32 src_ipv4 = 0, dst_ipv4 = 0;
1835 u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4;
1836 u16 src_port, dst_port, vlan_id, flex_bytes;
1837 u16 bucket_hash;
1838 u8 l4type;
1839 u8 fdirm = 0;
1840
1841 /* Get our input values */
1842 ixgbe_atr_get_l4type_82599(input, &l4type);
1843
1844 /*
1845 * Check l4type formatting, and bail out before we touch the hardware
1846 * if there's a configuration issue
1847 */
1848 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1849 case IXGBE_ATR_L4TYPE_TCP:
1850 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
1851 break;
1852 case IXGBE_ATR_L4TYPE_UDP:
1853 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
1854 break;
1855 case IXGBE_ATR_L4TYPE_SCTP:
1856 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
1857 break;
1858 default:
1859 hw_dbg(hw, "Error on l4type input\n");
1860 return IXGBE_ERR_CONFIG;
1861 }
1862
1863 bucket_hash = ixgbe_atr_compute_hash_82599(input,
1864 IXGBE_ATR_BUCKET_HASH_KEY);
1865
1866 /* bucket_hash is only 15 bits */
1867 bucket_hash &= IXGBE_ATR_HASH_MASK;
1868
1869 ixgbe_atr_get_vlan_id_82599(input, &vlan_id);
1870 ixgbe_atr_get_src_port_82599(input, &src_port);
1871 ixgbe_atr_get_dst_port_82599(input, &dst_port);
1872 ixgbe_atr_get_flex_byte_82599(input, &flex_bytes);
1873
1874 fdirhash = soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
1875
1876 /* Now figure out if we're IPv4 or IPv6 */
1877 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
1878 /* IPv6 */
1879 ixgbe_atr_get_src_ipv6_82599(input, &src_ipv6_1, &src_ipv6_2,
1880 &src_ipv6_3, &src_ipv6_4);
1881
1882 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), src_ipv6_1);
1883 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), src_ipv6_2);
1884 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), src_ipv6_3);
1885 /* The last 4 bytes is the same register as IPv4 */
1886 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv6_4);
1887
1888 fdircmd |= IXGBE_FDIRCMD_IPV6;
1889 fdircmd |= IXGBE_FDIRCMD_IPv6DMATCH;
1890 } else {
1891 /* IPv4 */
1892 ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4);
1893 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4);
1894 }
1895
1896 ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4);
1897 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, dst_ipv4);
1898
1899 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id |
1900 (flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT)));
1901 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port |
1902 (dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT)));
1903
1904 /*
1905 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1906 * are zero, then assume a full mask for that field. Also assume that
1907 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1908 * cannot be masked out in this implementation.
1909 *
1910 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1911 * point in time.
1912 */
1913 if (src_ipv4 == 0)
1914 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, 0xffffffff);
1915 else
1916 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, input_masks->src_ip_mask);
1917
1918 if (dst_ipv4 == 0)
1919 IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, 0xffffffff);
1920 else
1921 IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, input_masks->dst_ip_mask);
1922
1923 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1924 case IXGBE_ATR_L4TYPE_TCP:
1925 if (src_port == 0)
1926 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xffff);
1927 else
1928 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
1929 input_masks->src_port_mask);
1930
1931 if (dst_port == 0)
1932 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
1933 (IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) |
1934 (0xffff << 16)));
1935 else
1936 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
1937 (IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) |
1938 (input_masks->dst_port_mask << 16)));
1939 break;
1940 case IXGBE_ATR_L4TYPE_UDP:
1941 if (src_port == 0)
1942 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xffff);
1943 else
1944 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
1945 input_masks->src_port_mask);
1946
1947 if (dst_port == 0)
1948 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
1949 (IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) |
1950 (0xffff << 16)));
1951 else
1952 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
1953 (IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) |
1954 (input_masks->src_port_mask << 16)));
1955 break;
1956 default:
1957 /* this already would have failed above */
1958 break;
1959 }
1960
1961 /* Program the last mask register, FDIRM */
1962 if (input_masks->vlan_id_mask || !vlan_id)
1963 /* Mask both VLAN and VLANP - bits 0 and 1 */
1964 fdirm |= 0x3;
1965
1966 if (input_masks->data_mask || !flex_bytes)
1967 /* Flex bytes need masking, so mask the whole thing - bit 4 */
1968 fdirm |= 0x10;
1969
1970 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1971 fdirm |= 0x24;
1972
1973 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1974
1975 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW;
1976 fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE;
1977 fdircmd |= IXGBE_FDIRCMD_LAST;
1978 fdircmd |= IXGBE_FDIRCMD_QUEUE_EN;
1979 fdircmd |= queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1980
1981 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1982 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1983
1984 return 0;
1985 }
1986 /**
1987 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1988 * @hw: pointer to hardware structure
1989 * @reg: analog register to read
1990 * @val: read value
1991 *
1992 * Performs read operation to Omer analog register specified.
1993 **/
1994 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1995 {
1996 u32 core_ctl;
1997
1998 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1999 (reg << 8));
2000 IXGBE_WRITE_FLUSH(hw);
2001 udelay(10);
2002 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
2003 *val = (u8)core_ctl;
2004
2005 return 0;
2006 }
2007
2008 /**
2009 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2010 * @hw: pointer to hardware structure
2011 * @reg: atlas register to write
2012 * @val: value to write
2013 *
2014 * Performs write operation to Omer analog register specified.
2015 **/
2016 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
2017 {
2018 u32 core_ctl;
2019
2020 core_ctl = (reg << 8) | val;
2021 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2022 IXGBE_WRITE_FLUSH(hw);
2023 udelay(10);
2024
2025 return 0;
2026 }
2027
2028 /**
2029 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2030 * @hw: pointer to hardware structure
2031 *
2032 * Starts the hardware using the generic start_hw function.
2033 * Then performs device-specific:
2034 * Clears the rate limiter registers.
2035 **/
2036 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
2037 {
2038 u32 q_num;
2039 s32 ret_val;
2040
2041 ret_val = ixgbe_start_hw_generic(hw);
2042
2043 /* Clear the rate limiters */
2044 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
2045 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
2046 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
2047 }
2048 IXGBE_WRITE_FLUSH(hw);
2049
2050 /* We need to run link autotry after the driver loads */
2051 hw->mac.autotry_restart = true;
2052
2053 if (ret_val == 0)
2054 ret_val = ixgbe_verify_fw_version_82599(hw);
2055
2056 return ret_val;
2057 }
2058
2059 /**
2060 * ixgbe_identify_phy_82599 - Get physical layer module
2061 * @hw: pointer to hardware structure
2062 *
2063 * Determines the physical layer module found on the current adapter.
2064 **/
2065 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
2066 {
2067 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
2068 status = ixgbe_identify_phy_generic(hw);
2069 if (status != 0)
2070 status = ixgbe_identify_sfp_module_generic(hw);
2071 return status;
2072 }
2073
2074 /**
2075 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2076 * @hw: pointer to hardware structure
2077 *
2078 * Determines physical layer capabilities of the current configuration.
2079 **/
2080 static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
2081 {
2082 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2083 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2084 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2085 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2086 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2087 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2088 u16 ext_ability = 0;
2089 u8 comp_codes_10g = 0;
2090
2091 hw->phy.ops.identify(hw);
2092
2093 if (hw->phy.type == ixgbe_phy_tn ||
2094 hw->phy.type == ixgbe_phy_cu_unknown) {
2095 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
2096 &ext_ability);
2097 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
2098 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2099 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
2100 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2101 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
2102 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2103 goto out;
2104 }
2105
2106 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2107 case IXGBE_AUTOC_LMS_1G_AN:
2108 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2109 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2110 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2111 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2112 goto out;
2113 } else
2114 /* SFI mode so read SFP module */
2115 goto sfp_check;
2116 break;
2117 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2118 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2119 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2120 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2121 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2122 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2123 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
2124 goto out;
2125 break;
2126 case IXGBE_AUTOC_LMS_10G_SERIAL:
2127 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2128 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2129 goto out;
2130 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2131 goto sfp_check;
2132 break;
2133 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2134 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2135 if (autoc & IXGBE_AUTOC_KX_SUPP)
2136 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2137 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2138 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2139 if (autoc & IXGBE_AUTOC_KR_SUPP)
2140 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2141 goto out;
2142 break;
2143 default:
2144 goto out;
2145 break;
2146 }
2147
2148 sfp_check:
2149 /* SFP check must be done last since DA modules are sometimes used to
2150 * test KR mode - we need to id KR mode correctly before SFP module.
2151 * Call identify_sfp because the pluggable module may have changed */
2152 hw->phy.ops.identify_sfp(hw);
2153 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2154 goto out;
2155
2156 switch (hw->phy.type) {
2157 case ixgbe_phy_sfp_passive_tyco:
2158 case ixgbe_phy_sfp_passive_unknown:
2159 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2160 break;
2161 case ixgbe_phy_sfp_ftl_active:
2162 case ixgbe_phy_sfp_active_unknown:
2163 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
2164 break;
2165 case ixgbe_phy_sfp_avago:
2166 case ixgbe_phy_sfp_ftl:
2167 case ixgbe_phy_sfp_intel:
2168 case ixgbe_phy_sfp_unknown:
2169 hw->phy.ops.read_i2c_eeprom(hw,
2170 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2171 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2172 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2173 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2174 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2175 break;
2176 default:
2177 break;
2178 }
2179
2180 out:
2181 return physical_layer;
2182 }
2183
2184 /**
2185 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2186 * @hw: pointer to hardware structure
2187 * @regval: register value to write to RXCTRL
2188 *
2189 * Enables the Rx DMA unit for 82599
2190 **/
2191 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2192 {
2193 #define IXGBE_MAX_SECRX_POLL 30
2194 int i;
2195 int secrxreg;
2196
2197 /*
2198 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2199 * If traffic is incoming before we enable the Rx unit, it could hang
2200 * the Rx DMA unit. Therefore, make sure the security engine is
2201 * completely disabled prior to enabling the Rx unit.
2202 */
2203 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2204 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2205 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2206 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2207 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2208 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2209 break;
2210 else
2211 udelay(10);
2212 }
2213
2214 /* For informational purposes only */
2215 if (i >= IXGBE_MAX_SECRX_POLL)
2216 hw_dbg(hw, "Rx unit being enabled before security "
2217 "path fully disabled. Continuing with init.\n");
2218
2219 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2220 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2221 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2222 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2223 IXGBE_WRITE_FLUSH(hw);
2224
2225 return 0;
2226 }
2227
2228 /**
2229 * ixgbe_get_device_caps_82599 - Get additional device capabilities
2230 * @hw: pointer to hardware structure
2231 * @device_caps: the EEPROM word with the extra device capabilities
2232 *
2233 * This function will read the EEPROM location for the device capabilities,
2234 * and return the word through device_caps.
2235 **/
2236 static s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
2237 {
2238 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
2239
2240 return 0;
2241 }
2242
2243 /**
2244 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2245 * @hw: pointer to hardware structure
2246 *
2247 * Verifies that installed the firmware version is 0.6 or higher
2248 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2249 *
2250 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2251 * if the FW version is not supported.
2252 **/
2253 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2254 {
2255 s32 status = IXGBE_ERR_EEPROM_VERSION;
2256 u16 fw_offset, fw_ptp_cfg_offset;
2257 u16 fw_version = 0;
2258
2259 /* firmware check is only necessary for SFI devices */
2260 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2261 status = 0;
2262 goto fw_version_out;
2263 }
2264
2265 /* get the offset to the Firmware Module block */
2266 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2267
2268 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2269 goto fw_version_out;
2270
2271 /* get the offset to the Pass Through Patch Configuration block */
2272 hw->eeprom.ops.read(hw, (fw_offset +
2273 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2274 &fw_ptp_cfg_offset);
2275
2276 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2277 goto fw_version_out;
2278
2279 /* get the firmware version */
2280 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2281 IXGBE_FW_PATCH_VERSION_4),
2282 &fw_version);
2283
2284 if (fw_version > 0x5)
2285 status = 0;
2286
2287 fw_version_out:
2288 return status;
2289 }
2290
2291 /**
2292 * ixgbe_get_wwn_prefix_82599 - Get alternative WWNN/WWPN prefix from
2293 * the EEPROM
2294 * @hw: pointer to hardware structure
2295 * @wwnn_prefix: the alternative WWNN prefix
2296 * @wwpn_prefix: the alternative WWPN prefix
2297 *
2298 * This function will read the EEPROM from the alternative SAN MAC address
2299 * block to check the support for the alternative WWNN/WWPN prefix support.
2300 **/
2301 static s32 ixgbe_get_wwn_prefix_82599(struct ixgbe_hw *hw, u16 *wwnn_prefix,
2302 u16 *wwpn_prefix)
2303 {
2304 u16 offset, caps;
2305 u16 alt_san_mac_blk_offset;
2306
2307 /* clear output first */
2308 *wwnn_prefix = 0xFFFF;
2309 *wwpn_prefix = 0xFFFF;
2310
2311 /* check if alternative SAN MAC is supported */
2312 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
2313 &alt_san_mac_blk_offset);
2314
2315 if ((alt_san_mac_blk_offset == 0) ||
2316 (alt_san_mac_blk_offset == 0xFFFF))
2317 goto wwn_prefix_out;
2318
2319 /* check capability in alternative san mac address block */
2320 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
2321 hw->eeprom.ops.read(hw, offset, &caps);
2322 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
2323 goto wwn_prefix_out;
2324
2325 /* get the corresponding prefix for WWNN/WWPN */
2326 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
2327 hw->eeprom.ops.read(hw, offset, wwnn_prefix);
2328
2329 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
2330 hw->eeprom.ops.read(hw, offset, wwpn_prefix);
2331
2332 wwn_prefix_out:
2333 return 0;
2334 }
2335
2336 static struct ixgbe_mac_operations mac_ops_82599 = {
2337 .init_hw = &ixgbe_init_hw_generic,
2338 .reset_hw = &ixgbe_reset_hw_82599,
2339 .start_hw = &ixgbe_start_hw_82599,
2340 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2341 .get_media_type = &ixgbe_get_media_type_82599,
2342 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2343 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2344 .get_mac_addr = &ixgbe_get_mac_addr_generic,
2345 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
2346 .get_device_caps = &ixgbe_get_device_caps_82599,
2347 .get_wwn_prefix = &ixgbe_get_wwn_prefix_82599,
2348 .stop_adapter = &ixgbe_stop_adapter_generic,
2349 .get_bus_info = &ixgbe_get_bus_info_generic,
2350 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2351 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2352 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2353 .setup_link = &ixgbe_setup_mac_link_82599,
2354 .check_link = &ixgbe_check_mac_link_generic,
2355 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2356 .led_on = &ixgbe_led_on_generic,
2357 .led_off = &ixgbe_led_off_generic,
2358 .blink_led_start = &ixgbe_blink_led_start_generic,
2359 .blink_led_stop = &ixgbe_blink_led_stop_generic,
2360 .set_rar = &ixgbe_set_rar_generic,
2361 .clear_rar = &ixgbe_clear_rar_generic,
2362 .set_vmdq = &ixgbe_set_vmdq_generic,
2363 .clear_vmdq = &ixgbe_clear_vmdq_generic,
2364 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2365 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
2366 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2367 .enable_mc = &ixgbe_enable_mc_generic,
2368 .disable_mc = &ixgbe_disable_mc_generic,
2369 .clear_vfta = &ixgbe_clear_vfta_generic,
2370 .set_vfta = &ixgbe_set_vfta_generic,
2371 .fc_enable = &ixgbe_fc_enable_generic,
2372 .init_uta_tables = &ixgbe_init_uta_tables_generic,
2373 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2374 };
2375
2376 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2377 .init_params = &ixgbe_init_eeprom_params_generic,
2378 .read = &ixgbe_read_eerd_generic,
2379 .write = &ixgbe_write_eeprom_generic,
2380 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2381 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2382 };
2383
2384 static struct ixgbe_phy_operations phy_ops_82599 = {
2385 .identify = &ixgbe_identify_phy_82599,
2386 .identify_sfp = &ixgbe_identify_sfp_module_generic,
2387 .init = &ixgbe_init_phy_ops_82599,
2388 .reset = &ixgbe_reset_phy_generic,
2389 .read_reg = &ixgbe_read_phy_reg_generic,
2390 .write_reg = &ixgbe_write_phy_reg_generic,
2391 .setup_link = &ixgbe_setup_phy_link_generic,
2392 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2393 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2394 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2395 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2396 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2397 .check_overtemp = &ixgbe_tn_check_overtemp,
2398 };
2399
2400 struct ixgbe_info ixgbe_82599_info = {
2401 .mac = ixgbe_mac_82599EB,
2402 .get_invariants = &ixgbe_get_invariants_82599,
2403 .mac_ops = &mac_ops_82599,
2404 .eeprom_ops = &eeprom_ops_82599,
2405 .phy_ops = &phy_ops_82599,
2406 .mbx_ops = &mbx_ops_82599,
2407 };
Linux kernel - Deliverables
This page took 0.114329 seconds and 4 git commands to generate.