1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
33 #include "ixgbe_phy.h"
34 #include "ixgbe_mbx.h"
36 #define IXGBE_82599_MAX_TX_QUEUES 128
37 #define IXGBE_82599_MAX_RX_QUEUES 128
38 #define IXGBE_82599_RAR_ENTRIES 128
39 #define IXGBE_82599_MC_TBL_SIZE 128
40 #define IXGBE_82599_VFT_TBL_SIZE 128
41 #define IXGBE_82599_RX_PB_SIZE 512
43 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
);
44 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
);
45 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
);
46 static s32
ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw
*hw
,
47 ixgbe_link_speed speed
,
49 bool autoneg_wait_to_complete
);
50 static s32
ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw
*hw
,
51 ixgbe_link_speed speed
,
53 bool autoneg_wait_to_complete
);
54 static s32
ixgbe_start_mac_link_82599(struct ixgbe_hw
*hw
,
55 bool autoneg_wait_to_complete
);
56 static s32
ixgbe_setup_mac_link_82599(struct ixgbe_hw
*hw
,
57 ixgbe_link_speed speed
,
59 bool autoneg_wait_to_complete
);
60 static s32
ixgbe_setup_copper_link_82599(struct ixgbe_hw
*hw
,
61 ixgbe_link_speed speed
,
63 bool autoneg_wait_to_complete
);
64 static s32
ixgbe_verify_fw_version_82599(struct ixgbe_hw
*hw
);
65 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw
*hw
);
67 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw
*hw
)
69 struct ixgbe_mac_info
*mac
= &hw
->mac
;
71 /* enable the laser control functions for SFP+ fiber */
72 if (mac
->ops
.get_media_type(hw
) == ixgbe_media_type_fiber
) {
73 mac
->ops
.disable_tx_laser
=
74 &ixgbe_disable_tx_laser_multispeed_fiber
;
75 mac
->ops
.enable_tx_laser
=
76 &ixgbe_enable_tx_laser_multispeed_fiber
;
77 mac
->ops
.flap_tx_laser
= &ixgbe_flap_tx_laser_multispeed_fiber
;
79 mac
->ops
.disable_tx_laser
= NULL
;
80 mac
->ops
.enable_tx_laser
= NULL
;
81 mac
->ops
.flap_tx_laser
= NULL
;
84 if (hw
->phy
.multispeed_fiber
) {
85 /* Set up dual speed SFP+ support */
86 mac
->ops
.setup_link
= &ixgbe_setup_mac_link_multispeed_fiber
;
88 if ((mac
->ops
.get_media_type(hw
) ==
89 ixgbe_media_type_backplane
) &&
90 (hw
->phy
.smart_speed
== ixgbe_smart_speed_auto
||
91 hw
->phy
.smart_speed
== ixgbe_smart_speed_on
) &&
92 !ixgbe_verify_lesm_fw_enabled_82599(hw
))
93 mac
->ops
.setup_link
= &ixgbe_setup_mac_link_smartspeed
;
95 mac
->ops
.setup_link
= &ixgbe_setup_mac_link_82599
;
99 static s32
ixgbe_setup_sfp_modules_82599(struct ixgbe_hw
*hw
)
104 u16 list_offset
, data_offset
, data_value
;
106 if (hw
->phy
.sfp_type
!= ixgbe_sfp_type_unknown
) {
107 ixgbe_init_mac_link_ops_82599(hw
);
109 hw
->phy
.ops
.reset
= NULL
;
111 ret_val
= ixgbe_get_sfp_init_sequence_offsets(hw
, &list_offset
,
117 /* PHY config will finish before releasing the semaphore */
118 ret_val
= hw
->mac
.ops
.acquire_swfw_sync(hw
,
119 IXGBE_GSSR_MAC_CSR_SM
);
121 ret_val
= IXGBE_ERR_SWFW_SYNC
;
125 hw
->eeprom
.ops
.read(hw
, ++data_offset
, &data_value
);
126 while (data_value
!= 0xffff) {
127 IXGBE_WRITE_REG(hw
, IXGBE_CORECTL
, data_value
);
128 IXGBE_WRITE_FLUSH(hw
);
129 hw
->eeprom
.ops
.read(hw
, ++data_offset
, &data_value
);
132 /* Release the semaphore */
133 ixgbe_release_swfw_sync(hw
, IXGBE_GSSR_MAC_CSR_SM
);
135 * Delay obtaining semaphore again to allow FW access,
136 * semaphore_delay is in ms usleep_range needs us.
138 usleep_range(hw
->eeprom
.semaphore_delay
* 1000,
139 hw
->eeprom
.semaphore_delay
* 2000);
141 /* Now restart DSP by setting Restart_AN and clearing LMS */
142 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, ((IXGBE_READ_REG(hw
,
143 IXGBE_AUTOC
) & ~IXGBE_AUTOC_LMS_MASK
) |
144 IXGBE_AUTOC_AN_RESTART
));
146 /* Wait for AN to leave state 0 */
147 for (i
= 0; i
< 10; i
++) {
148 usleep_range(4000, 8000);
149 reg_anlp1
= IXGBE_READ_REG(hw
, IXGBE_ANLP1
);
150 if (reg_anlp1
& IXGBE_ANLP1_AN_STATE_MASK
)
153 if (!(reg_anlp1
& IXGBE_ANLP1_AN_STATE_MASK
)) {
154 hw_dbg(hw
, "sfp module setup not complete\n");
155 ret_val
= IXGBE_ERR_SFP_SETUP_NOT_COMPLETE
;
159 /* Restart DSP by setting Restart_AN and return to SFI mode */
160 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, (IXGBE_READ_REG(hw
,
161 IXGBE_AUTOC
) | IXGBE_AUTOC_LMS_10G_SERIAL
|
162 IXGBE_AUTOC_AN_RESTART
));
169 static s32
ixgbe_get_invariants_82599(struct ixgbe_hw
*hw
)
171 struct ixgbe_mac_info
*mac
= &hw
->mac
;
173 ixgbe_init_mac_link_ops_82599(hw
);
175 mac
->mcft_size
= IXGBE_82599_MC_TBL_SIZE
;
176 mac
->vft_size
= IXGBE_82599_VFT_TBL_SIZE
;
177 mac
->num_rar_entries
= IXGBE_82599_RAR_ENTRIES
;
178 mac
->max_rx_queues
= IXGBE_82599_MAX_RX_QUEUES
;
179 mac
->max_tx_queues
= IXGBE_82599_MAX_TX_QUEUES
;
180 mac
->max_msix_vectors
= ixgbe_get_pcie_msix_count_generic(hw
);
186 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
187 * @hw: pointer to hardware structure
189 * Initialize any function pointers that were not able to be
190 * set during get_invariants because the PHY/SFP type was
191 * not known. Perform the SFP init if necessary.
194 static s32
ixgbe_init_phy_ops_82599(struct ixgbe_hw
*hw
)
196 struct ixgbe_mac_info
*mac
= &hw
->mac
;
197 struct ixgbe_phy_info
*phy
= &hw
->phy
;
200 /* Identify the PHY or SFP module */
201 ret_val
= phy
->ops
.identify(hw
);
203 /* Setup function pointers based on detected SFP module and speeds */
204 ixgbe_init_mac_link_ops_82599(hw
);
206 /* If copper media, overwrite with copper function pointers */
207 if (mac
->ops
.get_media_type(hw
) == ixgbe_media_type_copper
) {
208 mac
->ops
.setup_link
= &ixgbe_setup_copper_link_82599
;
209 mac
->ops
.get_link_capabilities
=
210 &ixgbe_get_copper_link_capabilities_generic
;
213 /* Set necessary function pointers based on phy type */
214 switch (hw
->phy
.type
) {
216 phy
->ops
.check_link
= &ixgbe_check_phy_link_tnx
;
217 phy
->ops
.get_firmware_version
=
218 &ixgbe_get_phy_firmware_version_tnx
;
221 phy
->ops
.get_firmware_version
=
222 &ixgbe_get_phy_firmware_version_generic
;
232 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
233 * @hw: pointer to hardware structure
234 * @speed: pointer to link speed
235 * @negotiation: true when autoneg or autotry is enabled
237 * Determines the link capabilities by reading the AUTOC register.
239 static s32
ixgbe_get_link_capabilities_82599(struct ixgbe_hw
*hw
,
240 ixgbe_link_speed
*speed
,
246 /* Determine 1G link capabilities off of SFP+ type */
247 if (hw
->phy
.sfp_type
== ixgbe_sfp_type_1g_cu_core0
||
248 hw
->phy
.sfp_type
== ixgbe_sfp_type_1g_cu_core1
) {
249 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
255 * Determine link capabilities based on the stored value of AUTOC,
256 * which represents EEPROM defaults. If AUTOC value has not been
257 * stored, use the current register value.
259 if (hw
->mac
.orig_link_settings_stored
)
260 autoc
= hw
->mac
.orig_autoc
;
262 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
264 switch (autoc
& IXGBE_AUTOC_LMS_MASK
) {
265 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN
:
266 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
267 *negotiation
= false;
270 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN
:
271 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
272 *negotiation
= false;
275 case IXGBE_AUTOC_LMS_1G_AN
:
276 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
280 case IXGBE_AUTOC_LMS_10G_SERIAL
:
281 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
282 *negotiation
= false;
285 case IXGBE_AUTOC_LMS_KX4_KX_KR
:
286 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
:
287 *speed
= IXGBE_LINK_SPEED_UNKNOWN
;
288 if (autoc
& IXGBE_AUTOC_KR_SUPP
)
289 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
290 if (autoc
& IXGBE_AUTOC_KX4_SUPP
)
291 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
292 if (autoc
& IXGBE_AUTOC_KX_SUPP
)
293 *speed
|= IXGBE_LINK_SPEED_1GB_FULL
;
297 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
:
298 *speed
= IXGBE_LINK_SPEED_100_FULL
;
299 if (autoc
& IXGBE_AUTOC_KR_SUPP
)
300 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
301 if (autoc
& IXGBE_AUTOC_KX4_SUPP
)
302 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
303 if (autoc
& IXGBE_AUTOC_KX_SUPP
)
304 *speed
|= IXGBE_LINK_SPEED_1GB_FULL
;
308 case IXGBE_AUTOC_LMS_SGMII_1G_100M
:
309 *speed
= IXGBE_LINK_SPEED_1GB_FULL
| IXGBE_LINK_SPEED_100_FULL
;
310 *negotiation
= false;
314 status
= IXGBE_ERR_LINK_SETUP
;
319 if (hw
->phy
.multispeed_fiber
) {
320 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
|
321 IXGBE_LINK_SPEED_1GB_FULL
;
330 * ixgbe_get_media_type_82599 - Get media type
331 * @hw: pointer to hardware structure
333 * Returns the media type (fiber, copper, backplane)
335 static enum ixgbe_media_type
ixgbe_get_media_type_82599(struct ixgbe_hw
*hw
)
337 enum ixgbe_media_type media_type
;
339 /* Detect if there is a copper PHY attached. */
340 switch (hw
->phy
.type
) {
341 case ixgbe_phy_cu_unknown
:
344 media_type
= ixgbe_media_type_copper
;
350 switch (hw
->device_id
) {
351 case IXGBE_DEV_ID_82599_KX4
:
352 case IXGBE_DEV_ID_82599_KX4_MEZZ
:
353 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE
:
354 case IXGBE_DEV_ID_82599_KR
:
355 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE
:
356 case IXGBE_DEV_ID_82599_XAUI_LOM
:
357 /* Default device ID is mezzanine card KX/KX4 */
358 media_type
= ixgbe_media_type_backplane
;
360 case IXGBE_DEV_ID_82599_SFP
:
361 case IXGBE_DEV_ID_82599_SFP_FCOE
:
362 case IXGBE_DEV_ID_82599_SFP_EM
:
363 case IXGBE_DEV_ID_82599_SFP_SF2
:
364 media_type
= ixgbe_media_type_fiber
;
366 case IXGBE_DEV_ID_82599_CX4
:
367 media_type
= ixgbe_media_type_cx4
;
369 case IXGBE_DEV_ID_82599_T3_LOM
:
370 media_type
= ixgbe_media_type_copper
;
373 media_type
= ixgbe_media_type_unknown
;
381 * ixgbe_start_mac_link_82599 - Setup MAC link settings
382 * @hw: pointer to hardware structure
383 * @autoneg_wait_to_complete: true when waiting for completion is needed
385 * Configures link settings based on values in the ixgbe_hw struct.
386 * Restarts the link. Performs autonegotiation if needed.
388 static s32
ixgbe_start_mac_link_82599(struct ixgbe_hw
*hw
,
389 bool autoneg_wait_to_complete
)
397 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
398 autoc_reg
|= IXGBE_AUTOC_AN_RESTART
;
399 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc_reg
);
401 /* Only poll for autoneg to complete if specified to do so */
402 if (autoneg_wait_to_complete
) {
403 if ((autoc_reg
& IXGBE_AUTOC_LMS_MASK
) ==
404 IXGBE_AUTOC_LMS_KX4_KX_KR
||
405 (autoc_reg
& IXGBE_AUTOC_LMS_MASK
) ==
406 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
||
407 (autoc_reg
& IXGBE_AUTOC_LMS_MASK
) ==
408 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
) {
409 links_reg
= 0; /* Just in case Autoneg time = 0 */
410 for (i
= 0; i
< IXGBE_AUTO_NEG_TIME
; i
++) {
411 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
412 if (links_reg
& IXGBE_LINKS_KX_AN_COMP
)
416 if (!(links_reg
& IXGBE_LINKS_KX_AN_COMP
)) {
417 status
= IXGBE_ERR_AUTONEG_NOT_COMPLETE
;
418 hw_dbg(hw
, "Autoneg did not complete.\n");
423 /* Add delay to filter out noises during initial link setup */
430 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
431 * @hw: pointer to hardware structure
433 * The base drivers may require better control over SFP+ module
434 * PHY states. This includes selectively shutting down the Tx
435 * laser on the PHY, effectively halting physical link.
437 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
)
439 u32 esdp_reg
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
441 /* Disable tx laser; allow 100us to go dark per spec */
442 esdp_reg
|= IXGBE_ESDP_SDP3
;
443 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
444 IXGBE_WRITE_FLUSH(hw
);
449 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
450 * @hw: pointer to hardware structure
452 * The base drivers may require better control over SFP+ module
453 * PHY states. This includes selectively turning on the Tx
454 * laser on the PHY, effectively starting physical link.
456 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
)
458 u32 esdp_reg
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
460 /* Enable tx laser; allow 100ms to light up */
461 esdp_reg
&= ~IXGBE_ESDP_SDP3
;
462 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
463 IXGBE_WRITE_FLUSH(hw
);
468 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
469 * @hw: pointer to hardware structure
471 * When the driver changes the link speeds that it can support,
472 * it sets autotry_restart to true to indicate that we need to
473 * initiate a new autotry session with the link partner. To do
474 * so, we set the speed then disable and re-enable the tx laser, to
475 * alert the link partner that it also needs to restart autotry on its
476 * end. This is consistent with true clause 37 autoneg, which also
477 * involves a loss of signal.
479 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
)
481 if (hw
->mac
.autotry_restart
) {
482 ixgbe_disable_tx_laser_multispeed_fiber(hw
);
483 ixgbe_enable_tx_laser_multispeed_fiber(hw
);
484 hw
->mac
.autotry_restart
= false;
489 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
490 * @hw: pointer to hardware structure
491 * @speed: new link speed
492 * @autoneg: true if autonegotiation enabled
493 * @autoneg_wait_to_complete: true when waiting for completion is needed
495 * Set the link speed in the AUTOC register and restarts link.
497 s32
ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw
*hw
,
498 ixgbe_link_speed speed
,
500 bool autoneg_wait_to_complete
)
503 ixgbe_link_speed link_speed
= IXGBE_LINK_SPEED_UNKNOWN
;
504 ixgbe_link_speed highest_link_speed
= IXGBE_LINK_SPEED_UNKNOWN
;
506 u32 esdp_reg
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
508 bool link_up
= false;
511 /* Mask off requested but non-supported speeds */
512 status
= hw
->mac
.ops
.get_link_capabilities(hw
, &link_speed
,
520 * Try each speed one by one, highest priority first. We do this in
521 * software because 10gb fiber doesn't support speed autonegotiation.
523 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
) {
525 highest_link_speed
= IXGBE_LINK_SPEED_10GB_FULL
;
527 /* If we already have link at this speed, just jump out */
528 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
,
533 if ((link_speed
== IXGBE_LINK_SPEED_10GB_FULL
) && link_up
)
536 /* Set the module link speed */
537 esdp_reg
|= (IXGBE_ESDP_SDP5_DIR
| IXGBE_ESDP_SDP5
);
538 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
539 IXGBE_WRITE_FLUSH(hw
);
541 /* Allow module to change analog characteristics (1G->10G) */
544 status
= ixgbe_setup_mac_link_82599(hw
,
545 IXGBE_LINK_SPEED_10GB_FULL
,
547 autoneg_wait_to_complete
);
551 /* Flap the tx laser if it has not already been done */
552 hw
->mac
.ops
.flap_tx_laser(hw
);
555 * Wait for the controller to acquire link. Per IEEE 802.3ap,
556 * Section 73.10.2, we may have to wait up to 500ms if KR is
557 * attempted. 82599 uses the same timing for 10g SFI.
559 for (i
= 0; i
< 5; i
++) {
560 /* Wait for the link partner to also set speed */
563 /* If we have link, just jump out */
564 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
,
574 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
) {
576 if (highest_link_speed
== IXGBE_LINK_SPEED_UNKNOWN
)
577 highest_link_speed
= IXGBE_LINK_SPEED_1GB_FULL
;
579 /* If we already have link at this speed, just jump out */
580 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
,
585 if ((link_speed
== IXGBE_LINK_SPEED_1GB_FULL
) && link_up
)
588 /* Set the module link speed */
589 esdp_reg
&= ~IXGBE_ESDP_SDP5
;
590 esdp_reg
|= IXGBE_ESDP_SDP5_DIR
;
591 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
592 IXGBE_WRITE_FLUSH(hw
);
594 /* Allow module to change analog characteristics (10G->1G) */
597 status
= ixgbe_setup_mac_link_82599(hw
,
598 IXGBE_LINK_SPEED_1GB_FULL
,
600 autoneg_wait_to_complete
);
604 /* Flap the tx laser if it has not already been done */
605 hw
->mac
.ops
.flap_tx_laser(hw
);
607 /* Wait for the link partner to also set speed */
610 /* If we have link, just jump out */
611 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
,
621 * We didn't get link. Configure back to the highest speed we tried,
622 * (if there was more than one). We call ourselves back with just the
623 * single highest speed that the user requested.
626 status
= ixgbe_setup_mac_link_multispeed_fiber(hw
,
629 autoneg_wait_to_complete
);
632 /* Set autoneg_advertised value based on input link speed */
633 hw
->phy
.autoneg_advertised
= 0;
635 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
636 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_10GB_FULL
;
638 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
639 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_1GB_FULL
;
645 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
646 * @hw: pointer to hardware structure
647 * @speed: new link speed
648 * @autoneg: true if autonegotiation enabled
649 * @autoneg_wait_to_complete: true when waiting for completion is needed
651 * Implements the Intel SmartSpeed algorithm.
653 static s32
ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw
*hw
,
654 ixgbe_link_speed speed
, bool autoneg
,
655 bool autoneg_wait_to_complete
)
658 ixgbe_link_speed link_speed
= IXGBE_LINK_SPEED_UNKNOWN
;
660 bool link_up
= false;
661 u32 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
663 /* Set autoneg_advertised value based on input link speed */
664 hw
->phy
.autoneg_advertised
= 0;
666 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
667 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_10GB_FULL
;
669 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
670 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_1GB_FULL
;
672 if (speed
& IXGBE_LINK_SPEED_100_FULL
)
673 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_100_FULL
;
676 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
677 * autoneg advertisement if link is unable to be established at the
678 * highest negotiated rate. This can sometimes happen due to integrity
679 * issues with the physical media connection.
682 /* First, try to get link with full advertisement */
683 hw
->phy
.smart_speed_active
= false;
684 for (j
= 0; j
< IXGBE_SMARTSPEED_MAX_RETRIES
; j
++) {
685 status
= ixgbe_setup_mac_link_82599(hw
, speed
, autoneg
,
686 autoneg_wait_to_complete
);
691 * Wait for the controller to acquire link. Per IEEE 802.3ap,
692 * Section 73.10.2, we may have to wait up to 500ms if KR is
693 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
694 * Table 9 in the AN MAS.
696 for (i
= 0; i
< 5; i
++) {
699 /* If we have link, just jump out */
700 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
,
711 * We didn't get link. If we advertised KR plus one of KX4/KX
712 * (or BX4/BX), then disable KR and try again.
714 if (((autoc_reg
& IXGBE_AUTOC_KR_SUPP
) == 0) ||
715 ((autoc_reg
& IXGBE_AUTOC_KX4_KX_SUPP_MASK
) == 0))
718 /* Turn SmartSpeed on to disable KR support */
719 hw
->phy
.smart_speed_active
= true;
720 status
= ixgbe_setup_mac_link_82599(hw
, speed
, autoneg
,
721 autoneg_wait_to_complete
);
726 * Wait for the controller to acquire link. 600ms will allow for
727 * the AN link_fail_inhibit_timer as well for multiple cycles of
728 * parallel detect, both 10g and 1g. This allows for the maximum
729 * connect attempts as defined in the AN MAS table 73-7.
731 for (i
= 0; i
< 6; i
++) {
734 /* If we have link, just jump out */
735 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
,
744 /* We didn't get link. Turn SmartSpeed back off. */
745 hw
->phy
.smart_speed_active
= false;
746 status
= ixgbe_setup_mac_link_82599(hw
, speed
, autoneg
,
747 autoneg_wait_to_complete
);
750 if (link_up
&& (link_speed
== IXGBE_LINK_SPEED_1GB_FULL
))
751 hw_dbg(hw
, "Smartspeed has downgraded the link speed from "
752 "the maximum advertised\n");
757 * ixgbe_setup_mac_link_82599 - Set MAC link speed
758 * @hw: pointer to hardware structure
759 * @speed: new link speed
760 * @autoneg: true if autonegotiation enabled
761 * @autoneg_wait_to_complete: true when waiting for completion is needed
763 * Set the link speed in the AUTOC register and restarts link.
765 static s32
ixgbe_setup_mac_link_82599(struct ixgbe_hw
*hw
,
766 ixgbe_link_speed speed
, bool autoneg
,
767 bool autoneg_wait_to_complete
)
770 u32 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
771 u32 autoc2
= IXGBE_READ_REG(hw
, IXGBE_AUTOC2
);
772 u32 start_autoc
= autoc
;
774 u32 link_mode
= autoc
& IXGBE_AUTOC_LMS_MASK
;
775 u32 pma_pmd_1g
= autoc
& IXGBE_AUTOC_1G_PMA_PMD_MASK
;
776 u32 pma_pmd_10g_serial
= autoc2
& IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK
;
779 ixgbe_link_speed link_capabilities
= IXGBE_LINK_SPEED_UNKNOWN
;
781 /* Check to see if speed passed in is supported. */
782 hw
->mac
.ops
.get_link_capabilities(hw
, &link_capabilities
, &autoneg
);
786 speed
&= link_capabilities
;
788 if (speed
== IXGBE_LINK_SPEED_UNKNOWN
) {
789 status
= IXGBE_ERR_LINK_SETUP
;
793 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
794 if (hw
->mac
.orig_link_settings_stored
)
795 orig_autoc
= hw
->mac
.orig_autoc
;
799 if (link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR
||
800 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
||
801 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
) {
802 /* Set KX4/KX/KR support according to speed requested */
803 autoc
&= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK
| IXGBE_AUTOC_KR_SUPP
);
804 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
805 if (orig_autoc
& IXGBE_AUTOC_KX4_SUPP
)
806 autoc
|= IXGBE_AUTOC_KX4_SUPP
;
807 if ((orig_autoc
& IXGBE_AUTOC_KR_SUPP
) &&
808 (hw
->phy
.smart_speed_active
== false))
809 autoc
|= IXGBE_AUTOC_KR_SUPP
;
810 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
811 autoc
|= IXGBE_AUTOC_KX_SUPP
;
812 } else if ((pma_pmd_1g
== IXGBE_AUTOC_1G_SFI
) &&
813 (link_mode
== IXGBE_AUTOC_LMS_1G_LINK_NO_AN
||
814 link_mode
== IXGBE_AUTOC_LMS_1G_AN
)) {
815 /* Switch from 1G SFI to 10G SFI if requested */
816 if ((speed
== IXGBE_LINK_SPEED_10GB_FULL
) &&
817 (pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_SFI
)) {
818 autoc
&= ~IXGBE_AUTOC_LMS_MASK
;
819 autoc
|= IXGBE_AUTOC_LMS_10G_SERIAL
;
821 } else if ((pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_SFI
) &&
822 (link_mode
== IXGBE_AUTOC_LMS_10G_SERIAL
)) {
823 /* Switch from 10G SFI to 1G SFI if requested */
824 if ((speed
== IXGBE_LINK_SPEED_1GB_FULL
) &&
825 (pma_pmd_1g
== IXGBE_AUTOC_1G_SFI
)) {
826 autoc
&= ~IXGBE_AUTOC_LMS_MASK
;
828 autoc
|= IXGBE_AUTOC_LMS_1G_AN
;
830 autoc
|= IXGBE_AUTOC_LMS_1G_LINK_NO_AN
;
834 if (autoc
!= start_autoc
) {
836 autoc
|= IXGBE_AUTOC_AN_RESTART
;
837 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc
);
839 /* Only poll for autoneg to complete if specified to do so */
840 if (autoneg_wait_to_complete
) {
841 if (link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR
||
842 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
||
843 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
) {
844 links_reg
= 0; /*Just in case Autoneg time=0*/
845 for (i
= 0; i
< IXGBE_AUTO_NEG_TIME
; i
++) {
847 IXGBE_READ_REG(hw
, IXGBE_LINKS
);
848 if (links_reg
& IXGBE_LINKS_KX_AN_COMP
)
852 if (!(links_reg
& IXGBE_LINKS_KX_AN_COMP
)) {
854 IXGBE_ERR_AUTONEG_NOT_COMPLETE
;
855 hw_dbg(hw
, "Autoneg did not "
861 /* Add delay to filter out noises during initial link setup */
870 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
871 * @hw: pointer to hardware structure
872 * @speed: new link speed
873 * @autoneg: true if autonegotiation enabled
874 * @autoneg_wait_to_complete: true if waiting is needed to complete
876 * Restarts link on PHY and MAC based on settings passed in.
878 static s32
ixgbe_setup_copper_link_82599(struct ixgbe_hw
*hw
,
879 ixgbe_link_speed speed
,
881 bool autoneg_wait_to_complete
)
885 /* Setup the PHY according to input speed */
886 status
= hw
->phy
.ops
.setup_link_speed(hw
, speed
, autoneg
,
887 autoneg_wait_to_complete
);
889 ixgbe_start_mac_link_82599(hw
, autoneg_wait_to_complete
);
895 * ixgbe_reset_hw_82599 - Perform hardware reset
896 * @hw: pointer to hardware structure
898 * Resets the hardware by resetting the transmit and receive units, masks
899 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
902 static s32
ixgbe_reset_hw_82599(struct ixgbe_hw
*hw
)
910 /* Call adapter stop to disable tx/rx and clear interrupts */
911 hw
->mac
.ops
.stop_adapter(hw
);
913 /* PHY ops must be identified and initialized prior to reset */
915 /* Identify PHY and related function pointers */
916 status
= hw
->phy
.ops
.init(hw
);
918 if (status
== IXGBE_ERR_SFP_NOT_SUPPORTED
)
921 /* Setup SFP module if there is one present. */
922 if (hw
->phy
.sfp_setup_needed
) {
923 status
= hw
->mac
.ops
.setup_sfp(hw
);
924 hw
->phy
.sfp_setup_needed
= false;
927 if (status
== IXGBE_ERR_SFP_NOT_SUPPORTED
)
931 if (hw
->phy
.reset_disable
== false && hw
->phy
.ops
.reset
!= NULL
)
932 hw
->phy
.ops
.reset(hw
);
935 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
936 * access and verify no pending requests before reset
938 ixgbe_disable_pcie_master(hw
);
942 * Issue global reset to the MAC. This needs to be a SW reset.
943 * If link reset is used, it might reset the MAC when mng is using it
945 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
946 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, (ctrl
| IXGBE_CTRL_RST
));
947 IXGBE_WRITE_FLUSH(hw
);
949 /* Poll for reset bit to self-clear indicating reset is complete */
950 for (i
= 0; i
< 10; i
++) {
952 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
953 if (!(ctrl
& IXGBE_CTRL_RST
))
956 if (ctrl
& IXGBE_CTRL_RST
) {
957 status
= IXGBE_ERR_RESET_FAILED
;
958 hw_dbg(hw
, "Reset polling failed to complete.\n");
962 * Double resets are required for recovery from certain error
963 * conditions. Between resets, it is necessary to stall to allow time
964 * for any pending HW events to complete. We use 1usec since that is
965 * what is needed for ixgbe_disable_pcie_master(). The second reset
966 * then clears out any effects of those events.
968 if (hw
->mac
.flags
& IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
) {
969 hw
->mac
.flags
&= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
;
977 * Store the original AUTOC/AUTOC2 values if they have not been
978 * stored off yet. Otherwise restore the stored original
979 * values since the reset operation sets back to defaults.
981 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
982 autoc2
= IXGBE_READ_REG(hw
, IXGBE_AUTOC2
);
983 if (hw
->mac
.orig_link_settings_stored
== false) {
984 hw
->mac
.orig_autoc
= autoc
;
985 hw
->mac
.orig_autoc2
= autoc2
;
986 hw
->mac
.orig_link_settings_stored
= true;
988 if (autoc
!= hw
->mac
.orig_autoc
)
989 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, (hw
->mac
.orig_autoc
|
990 IXGBE_AUTOC_AN_RESTART
));
992 if ((autoc2
& IXGBE_AUTOC2_UPPER_MASK
) !=
993 (hw
->mac
.orig_autoc2
& IXGBE_AUTOC2_UPPER_MASK
)) {
994 autoc2
&= ~IXGBE_AUTOC2_UPPER_MASK
;
995 autoc2
|= (hw
->mac
.orig_autoc2
&
996 IXGBE_AUTOC2_UPPER_MASK
);
997 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC2
, autoc2
);
1001 /* Store the permanent mac address */
1002 hw
->mac
.ops
.get_mac_addr(hw
, hw
->mac
.perm_addr
);
1005 * Store MAC address from RAR0, clear receive address registers, and
1006 * clear the multicast table. Also reset num_rar_entries to 128,
1007 * since we modify this value when programming the SAN MAC address.
1009 hw
->mac
.num_rar_entries
= 128;
1010 hw
->mac
.ops
.init_rx_addrs(hw
);
1012 /* Store the permanent SAN mac address */
1013 hw
->mac
.ops
.get_san_mac_addr(hw
, hw
->mac
.san_addr
);
1015 /* Add the SAN MAC address to the RAR only if it's a valid address */
1016 if (ixgbe_validate_mac_addr(hw
->mac
.san_addr
) == 0) {
1017 hw
->mac
.ops
.set_rar(hw
, hw
->mac
.num_rar_entries
- 1,
1018 hw
->mac
.san_addr
, 0, IXGBE_RAH_AV
);
1020 /* Reserve the last RAR for the SAN MAC address */
1021 hw
->mac
.num_rar_entries
--;
1024 /* Store the alternative WWNN/WWPN prefix */
1025 hw
->mac
.ops
.get_wwn_prefix(hw
, &hw
->mac
.wwnn_prefix
,
1026 &hw
->mac
.wwpn_prefix
);
1033 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1034 * @hw: pointer to hardware structure
1036 s32
ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw
*hw
)
1039 u32 fdirctrl
= IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
);
1040 fdirctrl
&= ~IXGBE_FDIRCTRL_INIT_DONE
;
1043 * Before starting reinitialization process,
1044 * FDIRCMD.CMD must be zero.
1046 for (i
= 0; i
< IXGBE_FDIRCMD_CMD_POLL
; i
++) {
1047 if (!(IXGBE_READ_REG(hw
, IXGBE_FDIRCMD
) &
1048 IXGBE_FDIRCMD_CMD_MASK
))
1052 if (i
>= IXGBE_FDIRCMD_CMD_POLL
) {
1053 hw_dbg(hw
, "Flow Director previous command isn't complete, "
1054 "aborting table re-initialization.\n");
1055 return IXGBE_ERR_FDIR_REINIT_FAILED
;
1058 IXGBE_WRITE_REG(hw
, IXGBE_FDIRFREE
, 0);
1059 IXGBE_WRITE_FLUSH(hw
);
1061 * 82599 adapters flow director init flow cannot be restarted,
1062 * Workaround 82599 silicon errata by performing the following steps
1063 * before re-writing the FDIRCTRL control register with the same value.
1064 * - write 1 to bit 8 of FDIRCMD register &
1065 * - write 0 to bit 8 of FDIRCMD register
1067 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCMD
,
1068 (IXGBE_READ_REG(hw
, IXGBE_FDIRCMD
) |
1069 IXGBE_FDIRCMD_CLEARHT
));
1070 IXGBE_WRITE_FLUSH(hw
);
1071 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCMD
,
1072 (IXGBE_READ_REG(hw
, IXGBE_FDIRCMD
) &
1073 ~IXGBE_FDIRCMD_CLEARHT
));
1074 IXGBE_WRITE_FLUSH(hw
);
1076 * Clear FDIR Hash register to clear any leftover hashes
1077 * waiting to be programmed.
1079 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHASH
, 0x00);
1080 IXGBE_WRITE_FLUSH(hw
);
1082 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCTRL
, fdirctrl
);
1083 IXGBE_WRITE_FLUSH(hw
);
1085 /* Poll init-done after we write FDIRCTRL register */
1086 for (i
= 0; i
< IXGBE_FDIR_INIT_DONE_POLL
; i
++) {
1087 if (IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
) &
1088 IXGBE_FDIRCTRL_INIT_DONE
)
1092 if (i
>= IXGBE_FDIR_INIT_DONE_POLL
) {
1093 hw_dbg(hw
, "Flow Director Signature poll time exceeded!\n");
1094 return IXGBE_ERR_FDIR_REINIT_FAILED
;
1097 /* Clear FDIR statistics registers (read to clear) */
1098 IXGBE_READ_REG(hw
, IXGBE_FDIRUSTAT
);
1099 IXGBE_READ_REG(hw
, IXGBE_FDIRFSTAT
);
1100 IXGBE_READ_REG(hw
, IXGBE_FDIRMATCH
);
1101 IXGBE_READ_REG(hw
, IXGBE_FDIRMISS
);
1102 IXGBE_READ_REG(hw
, IXGBE_FDIRLEN
);
1108 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1109 * @hw: pointer to hardware structure
1110 * @pballoc: which mode to allocate filters with
1112 s32
ixgbe_init_fdir_signature_82599(struct ixgbe_hw
*hw
, u32 pballoc
)
1119 * Before enabling Flow Director, the Rx Packet Buffer size
1120 * must be reduced. The new value is the current size minus
1121 * flow director memory usage size.
1123 pbsize
= (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT
+ pballoc
));
1124 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(0),
1125 (IXGBE_READ_REG(hw
, IXGBE_RXPBSIZE(0)) - pbsize
));
1128 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1129 * initialized to zero for non DCB mode otherwise actual total RX PB
1130 * would be bigger than programmed and filter space would run into
1133 for (i
= 1; i
< 8; i
++)
1134 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(i
), 0);
1136 /* Send interrupt when 64 filters are left */
1137 fdirctrl
|= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT
;
1139 /* Set the maximum length per hash bucket to 0xA filters */
1140 fdirctrl
|= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT
;
1143 case IXGBE_FDIR_PBALLOC_64K
:
1144 /* 8k - 1 signature filters */
1145 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_64K
;
1147 case IXGBE_FDIR_PBALLOC_128K
:
1148 /* 16k - 1 signature filters */
1149 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_128K
;
1151 case IXGBE_FDIR_PBALLOC_256K
:
1152 /* 32k - 1 signature filters */
1153 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_256K
;
1157 return IXGBE_ERR_CONFIG
;
1160 /* Move the flexible bytes to use the ethertype - shift 6 words */
1161 fdirctrl
|= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT
);
1164 /* Prime the keys for hashing */
1165 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHKEY
, IXGBE_ATR_BUCKET_HASH_KEY
);
1166 IXGBE_WRITE_REG(hw
, IXGBE_FDIRSKEY
, IXGBE_ATR_SIGNATURE_HASH_KEY
);
1169 * Poll init-done after we write the register. Estimated times:
1170 * 10G: PBALLOC = 11b, timing is 60us
1171 * 1G: PBALLOC = 11b, timing is 600us
1172 * 100M: PBALLOC = 11b, timing is 6ms
1174 * Multiple these timings by 4 if under full Rx load
1176 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1177 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1178 * this might not finish in our poll time, but we can live with that
1181 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCTRL
, fdirctrl
);
1182 IXGBE_WRITE_FLUSH(hw
);
1183 for (i
= 0; i
< IXGBE_FDIR_INIT_DONE_POLL
; i
++) {
1184 if (IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
) &
1185 IXGBE_FDIRCTRL_INIT_DONE
)
1187 usleep_range(1000, 2000);
1189 if (i
>= IXGBE_FDIR_INIT_DONE_POLL
)
1190 hw_dbg(hw
, "Flow Director Signature poll time exceeded!\n");
1196 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1197 * @hw: pointer to hardware structure
1198 * @pballoc: which mode to allocate filters with
1200 s32
ixgbe_init_fdir_perfect_82599(struct ixgbe_hw
*hw
, u32 pballoc
)
1207 * Before enabling Flow Director, the Rx Packet Buffer size
1208 * must be reduced. The new value is the current size minus
1209 * flow director memory usage size.
1211 pbsize
= (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT
+ pballoc
));
1212 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(0),
1213 (IXGBE_READ_REG(hw
, IXGBE_RXPBSIZE(0)) - pbsize
));
1216 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1217 * initialized to zero for non DCB mode otherwise actual total RX PB
1218 * would be bigger than programmed and filter space would run into
1221 for (i
= 1; i
< 8; i
++)
1222 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(i
), 0);
1224 /* Send interrupt when 64 filters are left */
1225 fdirctrl
|= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT
;
1227 /* Initialize the drop queue to Rx queue 127 */
1228 fdirctrl
|= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT
);
1231 case IXGBE_FDIR_PBALLOC_64K
:
1232 /* 2k - 1 perfect filters */
1233 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_64K
;
1235 case IXGBE_FDIR_PBALLOC_128K
:
1236 /* 4k - 1 perfect filters */
1237 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_128K
;
1239 case IXGBE_FDIR_PBALLOC_256K
:
1240 /* 8k - 1 perfect filters */
1241 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_256K
;
1245 return IXGBE_ERR_CONFIG
;
1248 /* Turn perfect match filtering on */
1249 fdirctrl
|= IXGBE_FDIRCTRL_PERFECT_MATCH
;
1250 fdirctrl
|= IXGBE_FDIRCTRL_REPORT_STATUS
;
1252 /* Move the flexible bytes to use the ethertype - shift 6 words */
1253 fdirctrl
|= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT
);
1255 /* Prime the keys for hashing */
1256 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHKEY
, IXGBE_ATR_BUCKET_HASH_KEY
);
1257 IXGBE_WRITE_REG(hw
, IXGBE_FDIRSKEY
, IXGBE_ATR_SIGNATURE_HASH_KEY
);
1260 * Poll init-done after we write the register. Estimated times:
1261 * 10G: PBALLOC = 11b, timing is 60us
1262 * 1G: PBALLOC = 11b, timing is 600us
1263 * 100M: PBALLOC = 11b, timing is 6ms
1265 * Multiple these timings by 4 if under full Rx load
1267 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1268 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1269 * this might not finish in our poll time, but we can live with that
1273 /* Set the maximum length per hash bucket to 0xA filters */
1274 fdirctrl
|= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT
);
1276 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCTRL
, fdirctrl
);
1277 IXGBE_WRITE_FLUSH(hw
);
1278 for (i
= 0; i
< IXGBE_FDIR_INIT_DONE_POLL
; i
++) {
1279 if (IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
) &
1280 IXGBE_FDIRCTRL_INIT_DONE
)
1282 usleep_range(1000, 2000);
1284 if (i
>= IXGBE_FDIR_INIT_DONE_POLL
)
1285 hw_dbg(hw
, "Flow Director Perfect poll time exceeded!\n");
1292 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1293 * @stream: input bitstream to compute the hash on
1294 * @key: 32-bit hash key
1296 static u32
ixgbe_atr_compute_hash_82599(union ixgbe_atr_input
*atr_input
,
1300 * The algorithm is as follows:
1301 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1302 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1303 * and A[n] x B[n] is bitwise AND between same length strings
1305 * K[n] is 16 bits, defined as:
1306 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1307 * for n modulo 32 < 15, K[n] =
1308 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1310 * S[n] is 16 bits, defined as:
1311 * for n >= 15, S[n] = S[n:n - 15]
1312 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1314 * To simplify for programming, the algorithm is implemented
1315 * in software this way:
1317 * key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
1319 * for (i = 0; i < 352; i+=32)
1320 * hi_hash_dword[31:0] ^= Stream[(i+31):i];
1322 * lo_hash_dword[15:0] ^= Stream[15:0];
1323 * lo_hash_dword[15:0] ^= hi_hash_dword[31:16];
1324 * lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
1326 * hi_hash_dword[31:0] ^= Stream[351:320];
1329 * hash[15:0] ^= Stream[15:0];
1331 * for (i = 0; i < 16; i++) {
1333 * hash[15:0] ^= lo_hash_dword[(i+15):i];
1335 * hash[15:0] ^= hi_hash_dword[(i+15):i];
1339 __be32 common_hash_dword
= 0;
1340 u32 hi_hash_dword
, lo_hash_dword
, flow_vm_vlan
;
1341 u32 hash_result
= 0;
1344 /* record the flow_vm_vlan bits as they are a key part to the hash */
1345 flow_vm_vlan
= ntohl(atr_input
->dword_stream
[0]);
1347 /* generate common hash dword */
1348 for (i
= 10; i
; i
-= 2)
1349 common_hash_dword
^= atr_input
->dword_stream
[i
] ^
1350 atr_input
->dword_stream
[i
- 1];
1352 hi_hash_dword
= ntohl(common_hash_dword
);
1354 /* low dword is word swapped version of common */
1355 lo_hash_dword
= (hi_hash_dword
>> 16) | (hi_hash_dword
<< 16);
1357 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1358 hi_hash_dword
^= flow_vm_vlan
^ (flow_vm_vlan
>> 16);
1360 /* Process bits 0 and 16 */
1361 if (key
& 0x0001) hash_result
^= lo_hash_dword
;
1362 if (key
& 0x00010000) hash_result
^= hi_hash_dword
;
1365 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1366 * delay this because bit 0 of the stream should not be processed
1367 * so we do not add the vlan until after bit 0 was processed
1369 lo_hash_dword
^= flow_vm_vlan
^ (flow_vm_vlan
<< 16);
1372 /* process the remaining 30 bits in the key 2 bits at a time */
1373 for (i
= 15; i
; i
-- ) {
1374 if (key
& (0x0001 << i
)) hash_result
^= lo_hash_dword
>> i
;
1375 if (key
& (0x00010000 << i
)) hash_result
^= hi_hash_dword
>> i
;
1378 return hash_result
& IXGBE_ATR_HASH_MASK
;
1382 * These defines allow us to quickly generate all of the necessary instructions
1383 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1384 * for values 0 through 15
1386 #define IXGBE_ATR_COMMON_HASH_KEY \
1387 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1388 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1391 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1392 common_hash ^= lo_hash_dword >> n; \
1393 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1394 bucket_hash ^= lo_hash_dword >> n; \
1395 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1396 sig_hash ^= lo_hash_dword << (16 - n); \
1397 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1398 common_hash ^= hi_hash_dword >> n; \
1399 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1400 bucket_hash ^= hi_hash_dword >> n; \
1401 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1402 sig_hash ^= hi_hash_dword << (16 - n); \
1406 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1407 * @stream: input bitstream to compute the hash on
1409 * This function is almost identical to the function above but contains
1410 * several optomizations such as unwinding all of the loops, letting the
1411 * compiler work out all of the conditional ifs since the keys are static
1412 * defines, and computing two keys at once since the hashed dword stream
1413 * will be the same for both keys.
1415 static u32
ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input
,
1416 union ixgbe_atr_hash_dword common
)
1418 u32 hi_hash_dword
, lo_hash_dword
, flow_vm_vlan
;
1419 u32 sig_hash
= 0, bucket_hash
= 0, common_hash
= 0;
1421 /* record the flow_vm_vlan bits as they are a key part to the hash */
1422 flow_vm_vlan
= ntohl(input
.dword
);
1424 /* generate common hash dword */
1425 hi_hash_dword
= ntohl(common
.dword
);
1427 /* low dword is word swapped version of common */
1428 lo_hash_dword
= (hi_hash_dword
>> 16) | (hi_hash_dword
<< 16);
1430 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1431 hi_hash_dword
^= flow_vm_vlan
^ (flow_vm_vlan
>> 16);
1433 /* Process bits 0 and 16 */
1434 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1437 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1438 * delay this because bit 0 of the stream should not be processed
1439 * so we do not add the vlan until after bit 0 was processed
1441 lo_hash_dword
^= flow_vm_vlan
^ (flow_vm_vlan
<< 16);
1443 /* Process remaining 30 bit of the key */
1444 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1445 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1446 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1447 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1448 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1449 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1450 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1451 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1452 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1453 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1454 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1455 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1456 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1457 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1458 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1460 /* combine common_hash result with signature and bucket hashes */
1461 bucket_hash
^= common_hash
;
1462 bucket_hash
&= IXGBE_ATR_HASH_MASK
;
1464 sig_hash
^= common_hash
<< 16;
1465 sig_hash
&= IXGBE_ATR_HASH_MASK
<< 16;
1467 /* return completed signature hash */
1468 return sig_hash
^ bucket_hash
;
1472 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1473 * @hw: pointer to hardware structure
1474 * @input: unique input dword
1475 * @common: compressed common input dword
1476 * @queue: queue index to direct traffic to
1478 s32
ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw
*hw
,
1479 union ixgbe_atr_hash_dword input
,
1480 union ixgbe_atr_hash_dword common
,
1487 * Get the flow_type in order to program FDIRCMD properly
1488 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1490 switch (input
.formatted
.flow_type
) {
1491 case IXGBE_ATR_FLOW_TYPE_TCPV4
:
1492 case IXGBE_ATR_FLOW_TYPE_UDPV4
:
1493 case IXGBE_ATR_FLOW_TYPE_SCTPV4
:
1494 case IXGBE_ATR_FLOW_TYPE_TCPV6
:
1495 case IXGBE_ATR_FLOW_TYPE_UDPV6
:
1496 case IXGBE_ATR_FLOW_TYPE_SCTPV6
:
1499 hw_dbg(hw
, " Error on flow type input\n");
1500 return IXGBE_ERR_CONFIG
;
1503 /* configure FDIRCMD register */
1504 fdircmd
= IXGBE_FDIRCMD_CMD_ADD_FLOW
| IXGBE_FDIRCMD_FILTER_UPDATE
|
1505 IXGBE_FDIRCMD_LAST
| IXGBE_FDIRCMD_QUEUE_EN
;
1506 fdircmd
|= input
.formatted
.flow_type
<< IXGBE_FDIRCMD_FLOW_TYPE_SHIFT
;
1507 fdircmd
|= (u32
)queue
<< IXGBE_FDIRCMD_RX_QUEUE_SHIFT
;
1510 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1511 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1513 fdirhashcmd
= (u64
)fdircmd
<< 32;
1514 fdirhashcmd
|= ixgbe_atr_compute_sig_hash_82599(input
, common
);
1516 IXGBE_WRITE_REG64(hw
, IXGBE_FDIRHASH
, fdirhashcmd
);
1518 hw_dbg(hw
, "Tx Queue=%x hash=%x\n", queue
, (u32
)fdirhashcmd
);
1524 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1525 * @input_mask: mask to be bit swapped
1527 * The source and destination port masks for flow director are bit swapped
1528 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1529 * generate a correctly swapped value we need to bit swap the mask and that
1530 * is what is accomplished by this function.
1532 static u32
ixgbe_get_fdirtcpm_82599(struct ixgbe_atr_input_masks
*input_masks
)
1534 u32 mask
= ntohs(input_masks
->dst_port_mask
);
1535 mask
<<= IXGBE_FDIRTCPM_DPORTM_SHIFT
;
1536 mask
|= ntohs(input_masks
->src_port_mask
);
1537 mask
= ((mask
& 0x55555555) << 1) | ((mask
& 0xAAAAAAAA) >> 1);
1538 mask
= ((mask
& 0x33333333) << 2) | ((mask
& 0xCCCCCCCC) >> 2);
1539 mask
= ((mask
& 0x0F0F0F0F) << 4) | ((mask
& 0xF0F0F0F0) >> 4);
1540 return ((mask
& 0x00FF00FF) << 8) | ((mask
& 0xFF00FF00) >> 8);
1544 * These two macros are meant to address the fact that we have registers
1545 * that are either all or in part big-endian. As a result on big-endian
1546 * systems we will end up byte swapping the value to little-endian before
1547 * it is byte swapped again and written to the hardware in the original
1548 * big-endian format.
1550 #define IXGBE_STORE_AS_BE32(_value) \
1551 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1552 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1554 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1555 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
1557 #define IXGBE_STORE_AS_BE16(_value) \
1558 (((u16)(_value) >> 8) | ((u16)(_value) << 8))
1561 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1562 * @hw: pointer to hardware structure
1563 * @input: input bitstream
1564 * @input_masks: bitwise masks for relevant fields
1565 * @soft_id: software index into the silicon hash tables for filter storage
1566 * @queue: queue index to direct traffic to
1568 * Note that the caller to this function must lock before calling, since the
1569 * hardware writes must be protected from one another.
1571 s32
ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw
*hw
,
1572 union ixgbe_atr_input
*input
,
1573 struct ixgbe_atr_input_masks
*input_masks
,
1574 u16 soft_id
, u8 queue
)
1578 u32 fdirport
, fdirtcpm
;
1580 /* start with VLAN, flex bytes, VM pool, and IPv6 destination masked */
1581 u32 fdirm
= IXGBE_FDIRM_VLANID
| IXGBE_FDIRM_VLANP
| IXGBE_FDIRM_FLEX
|
1582 IXGBE_FDIRM_POOL
| IXGBE_FDIRM_DIPv6
;
1585 * Check flow_type formatting, and bail out before we touch the hardware
1586 * if there's a configuration issue
1588 switch (input
->formatted
.flow_type
) {
1589 case IXGBE_ATR_FLOW_TYPE_IPV4
:
1590 /* use the L4 protocol mask for raw IPv4/IPv6 traffic */
1591 fdirm
|= IXGBE_FDIRM_L4P
;
1592 case IXGBE_ATR_FLOW_TYPE_SCTPV4
:
1593 if (input_masks
->dst_port_mask
|| input_masks
->src_port_mask
) {
1594 hw_dbg(hw
, " Error on src/dst port mask\n");
1595 return IXGBE_ERR_CONFIG
;
1597 case IXGBE_ATR_FLOW_TYPE_TCPV4
:
1598 case IXGBE_ATR_FLOW_TYPE_UDPV4
:
1601 hw_dbg(hw
, " Error on flow type input\n");
1602 return IXGBE_ERR_CONFIG
;
1606 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1607 * are zero, then assume a full mask for that field. Also assume that
1608 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1609 * cannot be masked out in this implementation.
1611 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1616 switch (ntohs(input_masks
->vlan_id_mask
) & 0xEFFF) {
1618 /* Unmask VLAN ID - bit 0 and fall through to unmask prio */
1619 fdirm
&= ~IXGBE_FDIRM_VLANID
;
1621 /* Unmask VLAN prio - bit 1 */
1622 fdirm
&= ~IXGBE_FDIRM_VLANP
;
1625 /* Unmask VLAN ID - bit 0 */
1626 fdirm
&= ~IXGBE_FDIRM_VLANID
;
1629 /* do nothing, vlans already masked */
1632 hw_dbg(hw
, " Error on VLAN mask\n");
1633 return IXGBE_ERR_CONFIG
;
1636 if (input_masks
->flex_mask
& 0xFFFF) {
1637 if ((input_masks
->flex_mask
& 0xFFFF) != 0xFFFF) {
1638 hw_dbg(hw
, " Error on flexible byte mask\n");
1639 return IXGBE_ERR_CONFIG
;
1641 /* Unmask Flex Bytes - bit 4 */
1642 fdirm
&= ~IXGBE_FDIRM_FLEX
;
1645 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1646 IXGBE_WRITE_REG(hw
, IXGBE_FDIRM
, fdirm
);
1648 /* store the TCP/UDP port masks, bit reversed from port layout */
1649 fdirtcpm
= ixgbe_get_fdirtcpm_82599(input_masks
);
1651 /* write both the same so that UDP and TCP use the same mask */
1652 IXGBE_WRITE_REG(hw
, IXGBE_FDIRTCPM
, ~fdirtcpm
);
1653 IXGBE_WRITE_REG(hw
, IXGBE_FDIRUDPM
, ~fdirtcpm
);
1655 /* store source and destination IP masks (big-enian) */
1656 IXGBE_WRITE_REG_BE32(hw
, IXGBE_FDIRSIP4M
,
1657 ~input_masks
->src_ip_mask
[0]);
1658 IXGBE_WRITE_REG_BE32(hw
, IXGBE_FDIRDIP4M
,
1659 ~input_masks
->dst_ip_mask
[0]);
1661 /* Apply masks to input data */
1662 input
->formatted
.vlan_id
&= input_masks
->vlan_id_mask
;
1663 input
->formatted
.flex_bytes
&= input_masks
->flex_mask
;
1664 input
->formatted
.src_port
&= input_masks
->src_port_mask
;
1665 input
->formatted
.dst_port
&= input_masks
->dst_port_mask
;
1666 input
->formatted
.src_ip
[0] &= input_masks
->src_ip_mask
[0];
1667 input
->formatted
.dst_ip
[0] &= input_masks
->dst_ip_mask
[0];
1669 /* record vlan (little-endian) and flex_bytes(big-endian) */
1671 IXGBE_STORE_AS_BE16(ntohs(input
->formatted
.flex_bytes
));
1672 fdirvlan
<<= IXGBE_FDIRVLAN_FLEX_SHIFT
;
1673 fdirvlan
|= ntohs(input
->formatted
.vlan_id
);
1674 IXGBE_WRITE_REG(hw
, IXGBE_FDIRVLAN
, fdirvlan
);
1676 /* record source and destination port (little-endian)*/
1677 fdirport
= ntohs(input
->formatted
.dst_port
);
1678 fdirport
<<= IXGBE_FDIRPORT_DESTINATION_SHIFT
;
1679 fdirport
|= ntohs(input
->formatted
.src_port
);
1680 IXGBE_WRITE_REG(hw
, IXGBE_FDIRPORT
, fdirport
);
1682 /* record the first 32 bits of the destination address (big-endian) */
1683 IXGBE_WRITE_REG_BE32(hw
, IXGBE_FDIRIPDA
, input
->formatted
.dst_ip
[0]);
1685 /* record the source address (big-endian) */
1686 IXGBE_WRITE_REG_BE32(hw
, IXGBE_FDIRIPSA
, input
->formatted
.src_ip
[0]);
1688 /* configure FDIRCMD register */
1689 fdircmd
= IXGBE_FDIRCMD_CMD_ADD_FLOW
| IXGBE_FDIRCMD_FILTER_UPDATE
|
1690 IXGBE_FDIRCMD_LAST
| IXGBE_FDIRCMD_QUEUE_EN
;
1691 fdircmd
|= input
->formatted
.flow_type
<< IXGBE_FDIRCMD_FLOW_TYPE_SHIFT
;
1692 fdircmd
|= (u32
)queue
<< IXGBE_FDIRCMD_RX_QUEUE_SHIFT
;
1694 /* we only want the bucket hash so drop the upper 16 bits */
1695 fdirhash
= ixgbe_atr_compute_hash_82599(input
,
1696 IXGBE_ATR_BUCKET_HASH_KEY
);
1697 fdirhash
|= soft_id
<< IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT
;
1699 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHASH
, fdirhash
);
1700 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCMD
, fdircmd
);
1706 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1707 * @hw: pointer to hardware structure
1708 * @reg: analog register to read
1711 * Performs read operation to Omer analog register specified.
1713 static s32
ixgbe_read_analog_reg8_82599(struct ixgbe_hw
*hw
, u32 reg
, u8
*val
)
1717 IXGBE_WRITE_REG(hw
, IXGBE_CORECTL
, IXGBE_CORECTL_WRITE_CMD
|
1719 IXGBE_WRITE_FLUSH(hw
);
1721 core_ctl
= IXGBE_READ_REG(hw
, IXGBE_CORECTL
);
1722 *val
= (u8
)core_ctl
;
1728 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1729 * @hw: pointer to hardware structure
1730 * @reg: atlas register to write
1731 * @val: value to write
1733 * Performs write operation to Omer analog register specified.
1735 static s32
ixgbe_write_analog_reg8_82599(struct ixgbe_hw
*hw
, u32 reg
, u8 val
)
1739 core_ctl
= (reg
<< 8) | val
;
1740 IXGBE_WRITE_REG(hw
, IXGBE_CORECTL
, core_ctl
);
1741 IXGBE_WRITE_FLUSH(hw
);
1748 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1749 * @hw: pointer to hardware structure
1751 * Starts the hardware using the generic start_hw function
1752 * and the generation start_hw function.
1753 * Then performs revision-specific operations, if any.
1755 static s32
ixgbe_start_hw_82599(struct ixgbe_hw
*hw
)
1759 ret_val
= ixgbe_start_hw_generic(hw
);
1763 ret_val
= ixgbe_start_hw_gen2(hw
);
1767 /* We need to run link autotry after the driver loads */
1768 hw
->mac
.autotry_restart
= true;
1769 hw
->mac
.rx_pb_size
= IXGBE_82599_RX_PB_SIZE
;
1772 ret_val
= ixgbe_verify_fw_version_82599(hw
);
1778 * ixgbe_identify_phy_82599 - Get physical layer module
1779 * @hw: pointer to hardware structure
1781 * Determines the physical layer module found on the current adapter.
1782 * If PHY already detected, maintains current PHY type in hw struct,
1783 * otherwise executes the PHY detection routine.
1785 static s32
ixgbe_identify_phy_82599(struct ixgbe_hw
*hw
)
1787 s32 status
= IXGBE_ERR_PHY_ADDR_INVALID
;
1789 /* Detect PHY if not unknown - returns success if already detected. */
1790 status
= ixgbe_identify_phy_generic(hw
);
1792 /* 82599 10GBASE-T requires an external PHY */
1793 if (hw
->mac
.ops
.get_media_type(hw
) == ixgbe_media_type_copper
)
1796 status
= ixgbe_identify_sfp_module_generic(hw
);
1799 /* Set PHY type none if no PHY detected */
1800 if (hw
->phy
.type
== ixgbe_phy_unknown
) {
1801 hw
->phy
.type
= ixgbe_phy_none
;
1805 /* Return error if SFP module has been detected but is not supported */
1806 if (hw
->phy
.type
== ixgbe_phy_sfp_unsupported
)
1807 status
= IXGBE_ERR_SFP_NOT_SUPPORTED
;
1814 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1815 * @hw: pointer to hardware structure
1817 * Determines physical layer capabilities of the current configuration.
1819 static u32
ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw
*hw
)
1821 u32 physical_layer
= IXGBE_PHYSICAL_LAYER_UNKNOWN
;
1822 u32 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
1823 u32 autoc2
= IXGBE_READ_REG(hw
, IXGBE_AUTOC2
);
1824 u32 pma_pmd_10g_serial
= autoc2
& IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK
;
1825 u32 pma_pmd_10g_parallel
= autoc
& IXGBE_AUTOC_10G_PMA_PMD_MASK
;
1826 u32 pma_pmd_1g
= autoc
& IXGBE_AUTOC_1G_PMA_PMD_MASK
;
1827 u16 ext_ability
= 0;
1828 u8 comp_codes_10g
= 0;
1829 u8 comp_codes_1g
= 0;
1831 hw
->phy
.ops
.identify(hw
);
1833 switch (hw
->phy
.type
) {
1836 case ixgbe_phy_cu_unknown
:
1837 hw
->phy
.ops
.read_reg(hw
, MDIO_PMA_EXTABLE
, MDIO_MMD_PMAPMD
,
1839 if (ext_ability
& MDIO_PMA_EXTABLE_10GBT
)
1840 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_T
;
1841 if (ext_ability
& MDIO_PMA_EXTABLE_1000BT
)
1842 physical_layer
|= IXGBE_PHYSICAL_LAYER_1000BASE_T
;
1843 if (ext_ability
& MDIO_PMA_EXTABLE_100BTX
)
1844 physical_layer
|= IXGBE_PHYSICAL_LAYER_100BASE_TX
;
1850 switch (autoc
& IXGBE_AUTOC_LMS_MASK
) {
1851 case IXGBE_AUTOC_LMS_1G_AN
:
1852 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN
:
1853 if (pma_pmd_1g
== IXGBE_AUTOC_1G_KX_BX
) {
1854 physical_layer
= IXGBE_PHYSICAL_LAYER_1000BASE_KX
|
1855 IXGBE_PHYSICAL_LAYER_1000BASE_BX
;
1858 /* SFI mode so read SFP module */
1861 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN
:
1862 if (pma_pmd_10g_parallel
== IXGBE_AUTOC_10G_CX4
)
1863 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_CX4
;
1864 else if (pma_pmd_10g_parallel
== IXGBE_AUTOC_10G_KX4
)
1865 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_KX4
;
1866 else if (pma_pmd_10g_parallel
== IXGBE_AUTOC_10G_XAUI
)
1867 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_XAUI
;
1870 case IXGBE_AUTOC_LMS_10G_SERIAL
:
1871 if (pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_KR
) {
1872 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_KR
;
1874 } else if (pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_SFI
)
1877 case IXGBE_AUTOC_LMS_KX4_KX_KR
:
1878 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
:
1879 if (autoc
& IXGBE_AUTOC_KX_SUPP
)
1880 physical_layer
|= IXGBE_PHYSICAL_LAYER_1000BASE_KX
;
1881 if (autoc
& IXGBE_AUTOC_KX4_SUPP
)
1882 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_KX4
;
1883 if (autoc
& IXGBE_AUTOC_KR_SUPP
)
1884 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_KR
;
1893 /* SFP check must be done last since DA modules are sometimes used to
1894 * test KR mode - we need to id KR mode correctly before SFP module.
1895 * Call identify_sfp because the pluggable module may have changed */
1896 hw
->phy
.ops
.identify_sfp(hw
);
1897 if (hw
->phy
.sfp_type
== ixgbe_sfp_type_not_present
)
1900 switch (hw
->phy
.type
) {
1901 case ixgbe_phy_sfp_passive_tyco
:
1902 case ixgbe_phy_sfp_passive_unknown
:
1903 physical_layer
= IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU
;
1905 case ixgbe_phy_sfp_ftl_active
:
1906 case ixgbe_phy_sfp_active_unknown
:
1907 physical_layer
= IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA
;
1909 case ixgbe_phy_sfp_avago
:
1910 case ixgbe_phy_sfp_ftl
:
1911 case ixgbe_phy_sfp_intel
:
1912 case ixgbe_phy_sfp_unknown
:
1913 hw
->phy
.ops
.read_i2c_eeprom(hw
,
1914 IXGBE_SFF_1GBE_COMP_CODES
, &comp_codes_1g
);
1915 hw
->phy
.ops
.read_i2c_eeprom(hw
,
1916 IXGBE_SFF_10GBE_COMP_CODES
, &comp_codes_10g
);
1917 if (comp_codes_10g
& IXGBE_SFF_10GBASESR_CAPABLE
)
1918 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_SR
;
1919 else if (comp_codes_10g
& IXGBE_SFF_10GBASELR_CAPABLE
)
1920 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_LR
;
1921 else if (comp_codes_1g
& IXGBE_SFF_1GBASET_CAPABLE
)
1922 physical_layer
= IXGBE_PHYSICAL_LAYER_1000BASE_T
;
1929 return physical_layer
;
1933 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1934 * @hw: pointer to hardware structure
1935 * @regval: register value to write to RXCTRL
1937 * Enables the Rx DMA unit for 82599
1939 static s32
ixgbe_enable_rx_dma_82599(struct ixgbe_hw
*hw
, u32 regval
)
1941 #define IXGBE_MAX_SECRX_POLL 30
1946 * Workaround for 82599 silicon errata when enabling the Rx datapath.
1947 * If traffic is incoming before we enable the Rx unit, it could hang
1948 * the Rx DMA unit. Therefore, make sure the security engine is
1949 * completely disabled prior to enabling the Rx unit.
1951 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXCTRL
);
1952 secrxreg
|= IXGBE_SECRXCTRL_RX_DIS
;
1953 IXGBE_WRITE_REG(hw
, IXGBE_SECRXCTRL
, secrxreg
);
1954 for (i
= 0; i
< IXGBE_MAX_SECRX_POLL
; i
++) {
1955 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXSTAT
);
1956 if (secrxreg
& IXGBE_SECRXSTAT_SECRX_RDY
)
1959 /* Use interrupt-safe sleep just in case */
1963 /* For informational purposes only */
1964 if (i
>= IXGBE_MAX_SECRX_POLL
)
1965 hw_dbg(hw
, "Rx unit being enabled before security "
1966 "path fully disabled. Continuing with init.\n");
1968 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, regval
);
1969 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXCTRL
);
1970 secrxreg
&= ~IXGBE_SECRXCTRL_RX_DIS
;
1971 IXGBE_WRITE_REG(hw
, IXGBE_SECRXCTRL
, secrxreg
);
1972 IXGBE_WRITE_FLUSH(hw
);
1978 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
1979 * @hw: pointer to hardware structure
1981 * Verifies that installed the firmware version is 0.6 or higher
1982 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
1984 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
1985 * if the FW version is not supported.
1987 static s32
ixgbe_verify_fw_version_82599(struct ixgbe_hw
*hw
)
1989 s32 status
= IXGBE_ERR_EEPROM_VERSION
;
1990 u16 fw_offset
, fw_ptp_cfg_offset
;
1993 /* firmware check is only necessary for SFI devices */
1994 if (hw
->phy
.media_type
!= ixgbe_media_type_fiber
) {
1996 goto fw_version_out
;
1999 /* get the offset to the Firmware Module block */
2000 hw
->eeprom
.ops
.read(hw
, IXGBE_FW_PTR
, &fw_offset
);
2002 if ((fw_offset
== 0) || (fw_offset
== 0xFFFF))
2003 goto fw_version_out
;
2005 /* get the offset to the Pass Through Patch Configuration block */
2006 hw
->eeprom
.ops
.read(hw
, (fw_offset
+
2007 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR
),
2008 &fw_ptp_cfg_offset
);
2010 if ((fw_ptp_cfg_offset
== 0) || (fw_ptp_cfg_offset
== 0xFFFF))
2011 goto fw_version_out
;
2013 /* get the firmware version */
2014 hw
->eeprom
.ops
.read(hw
, (fw_ptp_cfg_offset
+
2015 IXGBE_FW_PATCH_VERSION_4
),
2018 if (fw_version
> 0x5)
2026 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2027 * @hw: pointer to hardware structure
2029 * Returns true if the LESM FW module is present and enabled. Otherwise
2030 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2032 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw
*hw
)
2034 bool lesm_enabled
= false;
2035 u16 fw_offset
, fw_lesm_param_offset
, fw_lesm_state
;
2038 /* get the offset to the Firmware Module block */
2039 status
= hw
->eeprom
.ops
.read(hw
, IXGBE_FW_PTR
, &fw_offset
);
2041 if ((status
!= 0) ||
2042 (fw_offset
== 0) || (fw_offset
== 0xFFFF))
2045 /* get the offset to the LESM Parameters block */
2046 status
= hw
->eeprom
.ops
.read(hw
, (fw_offset
+
2047 IXGBE_FW_LESM_PARAMETERS_PTR
),
2048 &fw_lesm_param_offset
);
2050 if ((status
!= 0) ||
2051 (fw_lesm_param_offset
== 0) || (fw_lesm_param_offset
== 0xFFFF))
2054 /* get the lesm state word */
2055 status
= hw
->eeprom
.ops
.read(hw
, (fw_lesm_param_offset
+
2056 IXGBE_FW_LESM_STATE_1
),
2059 if ((status
== 0) &&
2060 (fw_lesm_state
& IXGBE_FW_LESM_STATE_ENABLED
))
2061 lesm_enabled
= true;
2064 return lesm_enabled
;
2067 static struct ixgbe_mac_operations mac_ops_82599
= {
2068 .init_hw
= &ixgbe_init_hw_generic
,
2069 .reset_hw
= &ixgbe_reset_hw_82599
,
2070 .start_hw
= &ixgbe_start_hw_82599
,
2071 .clear_hw_cntrs
= &ixgbe_clear_hw_cntrs_generic
,
2072 .get_media_type
= &ixgbe_get_media_type_82599
,
2073 .get_supported_physical_layer
= &ixgbe_get_supported_physical_layer_82599
,
2074 .enable_rx_dma
= &ixgbe_enable_rx_dma_82599
,
2075 .get_mac_addr
= &ixgbe_get_mac_addr_generic
,
2076 .get_san_mac_addr
= &ixgbe_get_san_mac_addr_generic
,
2077 .get_device_caps
= &ixgbe_get_device_caps_generic
,
2078 .get_wwn_prefix
= &ixgbe_get_wwn_prefix_generic
,
2079 .stop_adapter
= &ixgbe_stop_adapter_generic
,
2080 .get_bus_info
= &ixgbe_get_bus_info_generic
,
2081 .set_lan_id
= &ixgbe_set_lan_id_multi_port_pcie
,
2082 .read_analog_reg8
= &ixgbe_read_analog_reg8_82599
,
2083 .write_analog_reg8
= &ixgbe_write_analog_reg8_82599
,
2084 .setup_link
= &ixgbe_setup_mac_link_82599
,
2085 .check_link
= &ixgbe_check_mac_link_generic
,
2086 .get_link_capabilities
= &ixgbe_get_link_capabilities_82599
,
2087 .led_on
= &ixgbe_led_on_generic
,
2088 .led_off
= &ixgbe_led_off_generic
,
2089 .blink_led_start
= &ixgbe_blink_led_start_generic
,
2090 .blink_led_stop
= &ixgbe_blink_led_stop_generic
,
2091 .set_rar
= &ixgbe_set_rar_generic
,
2092 .clear_rar
= &ixgbe_clear_rar_generic
,
2093 .set_vmdq
= &ixgbe_set_vmdq_generic
,
2094 .clear_vmdq
= &ixgbe_clear_vmdq_generic
,
2095 .init_rx_addrs
= &ixgbe_init_rx_addrs_generic
,
2096 .update_mc_addr_list
= &ixgbe_update_mc_addr_list_generic
,
2097 .enable_mc
= &ixgbe_enable_mc_generic
,
2098 .disable_mc
= &ixgbe_disable_mc_generic
,
2099 .clear_vfta
= &ixgbe_clear_vfta_generic
,
2100 .set_vfta
= &ixgbe_set_vfta_generic
,
2101 .fc_enable
= &ixgbe_fc_enable_generic
,
2102 .init_uta_tables
= &ixgbe_init_uta_tables_generic
,
2103 .setup_sfp
= &ixgbe_setup_sfp_modules_82599
,
2104 .set_mac_anti_spoofing
= &ixgbe_set_mac_anti_spoofing
,
2105 .set_vlan_anti_spoofing
= &ixgbe_set_vlan_anti_spoofing
,
2106 .acquire_swfw_sync
= &ixgbe_acquire_swfw_sync
,
2107 .release_swfw_sync
= &ixgbe_release_swfw_sync
,
2111 static struct ixgbe_eeprom_operations eeprom_ops_82599
= {
2112 .init_params
= &ixgbe_init_eeprom_params_generic
,
2113 .read
= &ixgbe_read_eerd_generic
,
2114 .write
= &ixgbe_write_eeprom_generic
,
2115 .calc_checksum
= &ixgbe_calc_eeprom_checksum_generic
,
2116 .validate_checksum
= &ixgbe_validate_eeprom_checksum_generic
,
2117 .update_checksum
= &ixgbe_update_eeprom_checksum_generic
,
2120 static struct ixgbe_phy_operations phy_ops_82599
= {
2121 .identify
= &ixgbe_identify_phy_82599
,
2122 .identify_sfp
= &ixgbe_identify_sfp_module_generic
,
2123 .init
= &ixgbe_init_phy_ops_82599
,
2124 .reset
= &ixgbe_reset_phy_generic
,
2125 .read_reg
= &ixgbe_read_phy_reg_generic
,
2126 .write_reg
= &ixgbe_write_phy_reg_generic
,
2127 .setup_link
= &ixgbe_setup_phy_link_generic
,
2128 .setup_link_speed
= &ixgbe_setup_phy_link_speed_generic
,
2129 .read_i2c_byte
= &ixgbe_read_i2c_byte_generic
,
2130 .write_i2c_byte
= &ixgbe_write_i2c_byte_generic
,
2131 .read_i2c_eeprom
= &ixgbe_read_i2c_eeprom_generic
,
2132 .write_i2c_eeprom
= &ixgbe_write_i2c_eeprom_generic
,
2133 .check_overtemp
= &ixgbe_tn_check_overtemp
,
2136 struct ixgbe_info ixgbe_82599_info
= {
2137 .mac
= ixgbe_mac_82599EB
,
2138 .get_invariants
= &ixgbe_get_invariants_82599
,
2139 .mac_ops
= &mac_ops_82599
,
2140 .eeprom_ops
= &eeprom_ops_82599
,
2141 .phy_ops
= &phy_ops_82599
,
2142 .mbx_ops
= &mbx_ops_generic
,