1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
33 #include "ixgbe_phy.h"
35 #define IXGBE_82599_MAX_TX_QUEUES 128
36 #define IXGBE_82599_MAX_RX_QUEUES 128
37 #define IXGBE_82599_RAR_ENTRIES 128
38 #define IXGBE_82599_MC_TBL_SIZE 128
39 #define IXGBE_82599_VFT_TBL_SIZE 128
41 s32
ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw
*hw
,
42 ixgbe_link_speed speed
,
44 bool autoneg_wait_to_complete
);
45 static s32
ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw
*hw
,
46 ixgbe_link_speed speed
,
48 bool autoneg_wait_to_complete
);
49 s32
ixgbe_start_mac_link_82599(struct ixgbe_hw
*hw
,
50 bool autoneg_wait_to_complete
);
51 s32
ixgbe_setup_mac_link_82599(struct ixgbe_hw
*hw
,
52 ixgbe_link_speed speed
,
54 bool autoneg_wait_to_complete
);
55 static s32
ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw
*hw
,
56 ixgbe_link_speed
*speed
,
58 static s32
ixgbe_setup_copper_link_82599(struct ixgbe_hw
*hw
,
59 ixgbe_link_speed speed
,
61 bool autoneg_wait_to_complete
);
62 static s32
ixgbe_verify_fw_version_82599(struct ixgbe_hw
*hw
);
64 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw
*hw
)
66 struct ixgbe_mac_info
*mac
= &hw
->mac
;
67 if (hw
->phy
.multispeed_fiber
) {
68 /* Set up dual speed SFP+ support */
69 mac
->ops
.setup_link
= &ixgbe_setup_mac_link_multispeed_fiber
;
71 if ((mac
->ops
.get_media_type(hw
) ==
72 ixgbe_media_type_backplane
) &&
73 (hw
->phy
.smart_speed
== ixgbe_smart_speed_auto
||
74 hw
->phy
.smart_speed
== ixgbe_smart_speed_on
))
75 mac
->ops
.setup_link
= &ixgbe_setup_mac_link_smartspeed
;
77 mac
->ops
.setup_link
= &ixgbe_setup_mac_link_82599
;
81 static s32
ixgbe_setup_sfp_modules_82599(struct ixgbe_hw
*hw
)
84 u16 list_offset
, data_offset
, data_value
;
86 if (hw
->phy
.sfp_type
!= ixgbe_sfp_type_unknown
) {
87 ixgbe_init_mac_link_ops_82599(hw
);
89 hw
->phy
.ops
.reset
= NULL
;
91 ret_val
= ixgbe_get_sfp_init_sequence_offsets(hw
, &list_offset
,
97 /* PHY config will finish before releasing the semaphore */
98 ret_val
= ixgbe_acquire_swfw_sync(hw
, IXGBE_GSSR_MAC_CSR_SM
);
100 ret_val
= IXGBE_ERR_SWFW_SYNC
;
104 hw
->eeprom
.ops
.read(hw
, ++data_offset
, &data_value
);
105 while (data_value
!= 0xffff) {
106 IXGBE_WRITE_REG(hw
, IXGBE_CORECTL
, data_value
);
107 IXGBE_WRITE_FLUSH(hw
);
108 hw
->eeprom
.ops
.read(hw
, ++data_offset
, &data_value
);
110 /* Now restart DSP by setting Restart_AN */
111 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
,
112 (IXGBE_READ_REG(hw
, IXGBE_AUTOC
) | IXGBE_AUTOC_AN_RESTART
));
114 /* Release the semaphore */
115 ixgbe_release_swfw_sync(hw
, IXGBE_GSSR_MAC_CSR_SM
);
116 /* Delay obtaining semaphore again to allow FW access */
117 msleep(hw
->eeprom
.semaphore_delay
);
125 * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
126 * @hw: pointer to hardware structure
128 * Read PCIe configuration space, and get the MSI-X vector count from
129 * the capabilities table.
131 static u32
ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw
*hw
)
133 struct ixgbe_adapter
*adapter
= hw
->back
;
135 pci_read_config_word(adapter
->pdev
, IXGBE_PCIE_MSIX_82599_CAPS
,
137 msix_count
&= IXGBE_PCIE_MSIX_TBL_SZ_MASK
;
139 /* MSI-X count is zero-based in HW, so increment to give proper value */
145 static s32
ixgbe_get_invariants_82599(struct ixgbe_hw
*hw
)
147 struct ixgbe_mac_info
*mac
= &hw
->mac
;
149 ixgbe_init_mac_link_ops_82599(hw
);
151 mac
->mcft_size
= IXGBE_82599_MC_TBL_SIZE
;
152 mac
->vft_size
= IXGBE_82599_VFT_TBL_SIZE
;
153 mac
->num_rar_entries
= IXGBE_82599_RAR_ENTRIES
;
154 mac
->max_rx_queues
= IXGBE_82599_MAX_RX_QUEUES
;
155 mac
->max_tx_queues
= IXGBE_82599_MAX_TX_QUEUES
;
156 mac
->max_msix_vectors
= ixgbe_get_pcie_msix_count_82599(hw
);
162 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
163 * @hw: pointer to hardware structure
165 * Initialize any function pointers that were not able to be
166 * set during get_invariants because the PHY/SFP type was
167 * not known. Perform the SFP init if necessary.
170 static s32
ixgbe_init_phy_ops_82599(struct ixgbe_hw
*hw
)
172 struct ixgbe_mac_info
*mac
= &hw
->mac
;
173 struct ixgbe_phy_info
*phy
= &hw
->phy
;
176 /* Identify the PHY or SFP module */
177 ret_val
= phy
->ops
.identify(hw
);
179 /* Setup function pointers based on detected SFP module and speeds */
180 ixgbe_init_mac_link_ops_82599(hw
);
182 /* If copper media, overwrite with copper function pointers */
183 if (mac
->ops
.get_media_type(hw
) == ixgbe_media_type_copper
) {
184 mac
->ops
.setup_link
= &ixgbe_setup_copper_link_82599
;
185 mac
->ops
.get_link_capabilities
=
186 &ixgbe_get_copper_link_capabilities_82599
;
189 /* Set necessary function pointers based on phy type */
190 switch (hw
->phy
.type
) {
192 phy
->ops
.check_link
= &ixgbe_check_phy_link_tnx
;
193 phy
->ops
.get_firmware_version
=
194 &ixgbe_get_phy_firmware_version_tnx
;
204 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
205 * @hw: pointer to hardware structure
206 * @speed: pointer to link speed
207 * @negotiation: true when autoneg or autotry is enabled
209 * Determines the link capabilities by reading the AUTOC register.
211 static s32
ixgbe_get_link_capabilities_82599(struct ixgbe_hw
*hw
,
212 ixgbe_link_speed
*speed
,
219 * Determine link capabilities based on the stored value of AUTOC,
220 * which represents EEPROM defaults. If AUTOC value has not been
221 * stored, use the current register value.
223 if (hw
->mac
.orig_link_settings_stored
)
224 autoc
= hw
->mac
.orig_autoc
;
226 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
228 switch (autoc
& IXGBE_AUTOC_LMS_MASK
) {
229 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN
:
230 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
231 *negotiation
= false;
234 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN
:
235 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
236 *negotiation
= false;
239 case IXGBE_AUTOC_LMS_1G_AN
:
240 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
244 case IXGBE_AUTOC_LMS_10G_SERIAL
:
245 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
246 *negotiation
= false;
249 case IXGBE_AUTOC_LMS_KX4_KX_KR
:
250 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
:
251 *speed
= IXGBE_LINK_SPEED_UNKNOWN
;
252 if (autoc
& IXGBE_AUTOC_KR_SUPP
)
253 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
254 if (autoc
& IXGBE_AUTOC_KX4_SUPP
)
255 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
256 if (autoc
& IXGBE_AUTOC_KX_SUPP
)
257 *speed
|= IXGBE_LINK_SPEED_1GB_FULL
;
261 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
:
262 *speed
= IXGBE_LINK_SPEED_100_FULL
;
263 if (autoc
& IXGBE_AUTOC_KR_SUPP
)
264 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
265 if (autoc
& IXGBE_AUTOC_KX4_SUPP
)
266 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
267 if (autoc
& IXGBE_AUTOC_KX_SUPP
)
268 *speed
|= IXGBE_LINK_SPEED_1GB_FULL
;
272 case IXGBE_AUTOC_LMS_SGMII_1G_100M
:
273 *speed
= IXGBE_LINK_SPEED_1GB_FULL
| IXGBE_LINK_SPEED_100_FULL
;
274 *negotiation
= false;
278 status
= IXGBE_ERR_LINK_SETUP
;
283 if (hw
->phy
.multispeed_fiber
) {
284 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
|
285 IXGBE_LINK_SPEED_1GB_FULL
;
294 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
295 * @hw: pointer to hardware structure
296 * @speed: pointer to link speed
297 * @autoneg: boolean auto-negotiation value
299 * Determines the link capabilities by reading the AUTOC register.
301 static s32
ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw
*hw
,
302 ixgbe_link_speed
*speed
,
305 s32 status
= IXGBE_ERR_LINK_SETUP
;
311 status
= hw
->phy
.ops
.read_reg(hw
, MDIO_SPEED
, MDIO_MMD_PMAPMD
,
315 if (speed_ability
& MDIO_SPEED_10G
)
316 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
317 if (speed_ability
& MDIO_PMA_SPEED_1000
)
318 *speed
|= IXGBE_LINK_SPEED_1GB_FULL
;
325 * ixgbe_get_media_type_82599 - Get media type
326 * @hw: pointer to hardware structure
328 * Returns the media type (fiber, copper, backplane)
330 static enum ixgbe_media_type
ixgbe_get_media_type_82599(struct ixgbe_hw
*hw
)
332 enum ixgbe_media_type media_type
;
334 /* Detect if there is a copper PHY attached. */
335 if (hw
->phy
.type
== ixgbe_phy_cu_unknown
||
336 hw
->phy
.type
== ixgbe_phy_tn
) {
337 media_type
= ixgbe_media_type_copper
;
341 switch (hw
->device_id
) {
342 case IXGBE_DEV_ID_82599_KX4
:
343 case IXGBE_DEV_ID_82599_KX4_MEZZ
:
344 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE
:
345 case IXGBE_DEV_ID_82599_KR
:
346 case IXGBE_DEV_ID_82599_XAUI_LOM
:
347 /* Default device ID is mezzanine card KX/KX4 */
348 media_type
= ixgbe_media_type_backplane
;
350 case IXGBE_DEV_ID_82599_SFP
:
351 case IXGBE_DEV_ID_82599_SFP_EM
:
352 media_type
= ixgbe_media_type_fiber
;
354 case IXGBE_DEV_ID_82599_CX4
:
355 media_type
= ixgbe_media_type_cx4
;
358 media_type
= ixgbe_media_type_unknown
;
366 * ixgbe_start_mac_link_82599 - Setup MAC link settings
367 * @hw: pointer to hardware structure
368 * @autoneg_wait_to_complete: true when waiting for completion is needed
370 * Configures link settings based on values in the ixgbe_hw struct.
371 * Restarts the link. Performs autonegotiation if needed.
373 s32
ixgbe_start_mac_link_82599(struct ixgbe_hw
*hw
,
374 bool autoneg_wait_to_complete
)
382 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
383 autoc_reg
|= IXGBE_AUTOC_AN_RESTART
;
384 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc_reg
);
386 /* Only poll for autoneg to complete if specified to do so */
387 if (autoneg_wait_to_complete
) {
388 if ((autoc_reg
& IXGBE_AUTOC_LMS_MASK
) ==
389 IXGBE_AUTOC_LMS_KX4_KX_KR
||
390 (autoc_reg
& IXGBE_AUTOC_LMS_MASK
) ==
391 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
||
392 (autoc_reg
& IXGBE_AUTOC_LMS_MASK
) ==
393 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
) {
394 links_reg
= 0; /* Just in case Autoneg time = 0 */
395 for (i
= 0; i
< IXGBE_AUTO_NEG_TIME
; i
++) {
396 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
397 if (links_reg
& IXGBE_LINKS_KX_AN_COMP
)
401 if (!(links_reg
& IXGBE_LINKS_KX_AN_COMP
)) {
402 status
= IXGBE_ERR_AUTONEG_NOT_COMPLETE
;
403 hw_dbg(hw
, "Autoneg did not complete.\n");
408 /* Add delay to filter out noises during initial link setup */
415 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
416 * @hw: pointer to hardware structure
417 * @speed: new link speed
418 * @autoneg: true if autonegotiation enabled
419 * @autoneg_wait_to_complete: true when waiting for completion is needed
421 * Set the link speed in the AUTOC register and restarts link.
423 s32
ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw
*hw
,
424 ixgbe_link_speed speed
,
426 bool autoneg_wait_to_complete
)
429 ixgbe_link_speed phy_link_speed
;
430 ixgbe_link_speed highest_link_speed
= IXGBE_LINK_SPEED_UNKNOWN
;
432 u32 esdp_reg
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
433 bool link_up
= false;
437 /* Mask off requested but non-supported speeds */
438 hw
->mac
.ops
.get_link_capabilities(hw
, &phy_link_speed
, &negotiation
);
439 speed
&= phy_link_speed
;
442 * When the driver changes the link speeds that it can support,
443 * it sets autotry_restart to true to indicate that we need to
444 * initiate a new autotry session with the link partner. To do
445 * so, we set the speed then disable and re-enable the tx laser, to
446 * alert the link partner that it also needs to restart autotry on its
447 * end. This is consistent with true clause 37 autoneg, which also
448 * involves a loss of signal.
452 * Try each speed one by one, highest priority first. We do this in
453 * software because 10gb fiber doesn't support speed autonegotiation.
455 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
) {
457 highest_link_speed
= IXGBE_LINK_SPEED_10GB_FULL
;
459 /* If we already have link at this speed, just jump out */
460 hw
->mac
.ops
.check_link(hw
, &phy_link_speed
, &link_up
, false);
462 if ((phy_link_speed
== IXGBE_LINK_SPEED_10GB_FULL
) && link_up
)
465 /* Set the module link speed */
466 esdp_reg
|= (IXGBE_ESDP_SDP5_DIR
| IXGBE_ESDP_SDP5
);
467 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
469 /* Allow module to change analog characteristics (1G->10G) */
472 status
= ixgbe_setup_mac_link_82599(hw
,
473 IXGBE_LINK_SPEED_10GB_FULL
,
475 autoneg_wait_to_complete
);
479 /* Flap the tx laser if it has not already been done */
480 if (hw
->mac
.autotry_restart
) {
481 /* Disable tx laser; allow 100us to go dark per spec */
482 esdp_reg
|= IXGBE_ESDP_SDP3
;
483 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
486 /* Enable tx laser; allow 2ms to light up per spec */
487 esdp_reg
&= ~IXGBE_ESDP_SDP3
;
488 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
491 hw
->mac
.autotry_restart
= false;
495 * Wait for the controller to acquire link. Per IEEE 802.3ap,
496 * Section 73.10.2, we may have to wait up to 500ms if KR is
497 * attempted. 82599 uses the same timing for 10g SFI.
500 for (i
= 0; i
< 5; i
++) {
501 /* Wait for the link partner to also set speed */
504 /* If we have link, just jump out */
505 hw
->mac
.ops
.check_link(hw
, &phy_link_speed
,
512 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
) {
514 if (highest_link_speed
== IXGBE_LINK_SPEED_UNKNOWN
)
515 highest_link_speed
= IXGBE_LINK_SPEED_1GB_FULL
;
517 /* If we already have link at this speed, just jump out */
518 hw
->mac
.ops
.check_link(hw
, &phy_link_speed
, &link_up
, false);
520 if ((phy_link_speed
== IXGBE_LINK_SPEED_1GB_FULL
) && link_up
)
523 /* Set the module link speed */
524 esdp_reg
&= ~IXGBE_ESDP_SDP5
;
525 esdp_reg
|= IXGBE_ESDP_SDP5_DIR
;
526 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
528 /* Allow module to change analog characteristics (10G->1G) */
531 status
= ixgbe_setup_mac_link_82599(hw
,
532 IXGBE_LINK_SPEED_1GB_FULL
,
534 autoneg_wait_to_complete
);
538 /* Flap the tx laser if it has not already been done */
539 if (hw
->mac
.autotry_restart
) {
540 /* Disable tx laser; allow 100us to go dark per spec */
541 esdp_reg
|= IXGBE_ESDP_SDP3
;
542 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
545 /* Enable tx laser; allow 2ms to light up per spec */
546 esdp_reg
&= ~IXGBE_ESDP_SDP3
;
547 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
550 hw
->mac
.autotry_restart
= false;
553 /* Wait for the link partner to also set speed */
556 /* If we have link, just jump out */
557 hw
->mac
.ops
.check_link(hw
, &phy_link_speed
, &link_up
, false);
563 * We didn't get link. Configure back to the highest speed we tried,
564 * (if there was more than one). We call ourselves back with just the
565 * single highest speed that the user requested.
568 status
= ixgbe_setup_mac_link_multispeed_fiber(hw
,
571 autoneg_wait_to_complete
);
574 /* Set autoneg_advertised value based on input link speed */
575 hw
->phy
.autoneg_advertised
= 0;
577 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
578 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_10GB_FULL
;
580 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
581 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_1GB_FULL
;
587 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
588 * @hw: pointer to hardware structure
589 * @speed: new link speed
590 * @autoneg: true if autonegotiation enabled
591 * @autoneg_wait_to_complete: true when waiting for completion is needed
593 * Implements the Intel SmartSpeed algorithm.
595 static s32
ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw
*hw
,
596 ixgbe_link_speed speed
, bool autoneg
,
597 bool autoneg_wait_to_complete
)
600 ixgbe_link_speed link_speed
;
602 bool link_up
= false;
603 u32 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
605 hw_dbg(hw
, "ixgbe_setup_mac_link_smartspeed.\n");
607 /* Set autoneg_advertised value based on input link speed */
608 hw
->phy
.autoneg_advertised
= 0;
610 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
611 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_10GB_FULL
;
613 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
614 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_1GB_FULL
;
616 if (speed
& IXGBE_LINK_SPEED_100_FULL
)
617 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_100_FULL
;
620 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
621 * autoneg advertisement if link is unable to be established at the
622 * highest negotiated rate. This can sometimes happen due to integrity
623 * issues with the physical media connection.
626 /* First, try to get link with full advertisement */
627 hw
->phy
.smart_speed_active
= false;
628 for (j
= 0; j
< IXGBE_SMARTSPEED_MAX_RETRIES
; j
++) {
629 status
= ixgbe_setup_mac_link_82599(hw
, speed
, autoneg
,
630 autoneg_wait_to_complete
);
635 * Wait for the controller to acquire link. Per IEEE 802.3ap,
636 * Section 73.10.2, we may have to wait up to 500ms if KR is
637 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
638 * Table 9 in the AN MAS.
640 for (i
= 0; i
< 5; i
++) {
643 /* If we have link, just jump out */
644 hw
->mac
.ops
.check_link(hw
, &link_speed
,
652 * We didn't get link. If we advertised KR plus one of KX4/KX
653 * (or BX4/BX), then disable KR and try again.
655 if (((autoc_reg
& IXGBE_AUTOC_KR_SUPP
) == 0) ||
656 ((autoc_reg
& IXGBE_AUTOC_KX4_KX_SUPP_MASK
) == 0))
659 /* Turn SmartSpeed on to disable KR support */
660 hw
->phy
.smart_speed_active
= true;
661 status
= ixgbe_setup_mac_link_82599(hw
, speed
, autoneg
,
662 autoneg_wait_to_complete
);
667 * Wait for the controller to acquire link. 600ms will allow for
668 * the AN link_fail_inhibit_timer as well for multiple cycles of
669 * parallel detect, both 10g and 1g. This allows for the maximum
670 * connect attempts as defined in the AN MAS table 73-7.
672 for (i
= 0; i
< 6; i
++) {
675 /* If we have link, just jump out */
676 hw
->mac
.ops
.check_link(hw
, &link_speed
,
682 /* We didn't get link. Turn SmartSpeed back off. */
683 hw
->phy
.smart_speed_active
= false;
684 status
= ixgbe_setup_mac_link_82599(hw
, speed
, autoneg
,
685 autoneg_wait_to_complete
);
692 * ixgbe_check_mac_link_82599 - Determine link and speed status
693 * @hw: pointer to hardware structure
694 * @speed: pointer to link speed
695 * @link_up: true when link is up
696 * @link_up_wait_to_complete: bool used to wait for link up or not
698 * Reads the links register to determine if link is up and the current speed
700 static s32
ixgbe_check_mac_link_82599(struct ixgbe_hw
*hw
,
701 ixgbe_link_speed
*speed
,
703 bool link_up_wait_to_complete
)
708 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
709 if (link_up_wait_to_complete
) {
710 for (i
= 0; i
< IXGBE_LINK_UP_TIME
; i
++) {
711 if (links_reg
& IXGBE_LINKS_UP
) {
718 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
721 if (links_reg
& IXGBE_LINKS_UP
)
727 if ((links_reg
& IXGBE_LINKS_SPEED_82599
) ==
728 IXGBE_LINKS_SPEED_10G_82599
)
729 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
730 else if ((links_reg
& IXGBE_LINKS_SPEED_82599
) ==
731 IXGBE_LINKS_SPEED_1G_82599
)
732 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
734 *speed
= IXGBE_LINK_SPEED_100_FULL
;
736 /* if link is down, zero out the current_mode */
737 if (*link_up
== false) {
738 hw
->fc
.current_mode
= ixgbe_fc_none
;
739 hw
->fc
.fc_was_autonegged
= false;
746 * ixgbe_setup_mac_link_82599 - Set MAC link speed
747 * @hw: pointer to hardware structure
748 * @speed: new link speed
749 * @autoneg: true if autonegotiation enabled
750 * @autoneg_wait_to_complete: true when waiting for completion is needed
752 * Set the link speed in the AUTOC register and restarts link.
754 s32
ixgbe_setup_mac_link_82599(struct ixgbe_hw
*hw
,
755 ixgbe_link_speed speed
, bool autoneg
,
756 bool autoneg_wait_to_complete
)
759 u32 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
760 u32 autoc2
= IXGBE_READ_REG(hw
, IXGBE_AUTOC2
);
761 u32 start_autoc
= autoc
;
763 u32 link_mode
= autoc
& IXGBE_AUTOC_LMS_MASK
;
764 u32 pma_pmd_1g
= autoc
& IXGBE_AUTOC_1G_PMA_PMD_MASK
;
765 u32 pma_pmd_10g_serial
= autoc2
& IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK
;
768 ixgbe_link_speed link_capabilities
= IXGBE_LINK_SPEED_UNKNOWN
;
770 /* Check to see if speed passed in is supported. */
771 hw
->mac
.ops
.get_link_capabilities(hw
, &link_capabilities
, &autoneg
);
772 speed
&= link_capabilities
;
774 if (speed
== IXGBE_LINK_SPEED_UNKNOWN
) {
775 status
= IXGBE_ERR_LINK_SETUP
;
779 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
780 if (hw
->mac
.orig_link_settings_stored
)
781 orig_autoc
= hw
->mac
.orig_autoc
;
786 if (link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR
||
787 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
||
788 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
) {
789 /* Set KX4/KX/KR support according to speed requested */
790 autoc
&= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK
| IXGBE_AUTOC_KR_SUPP
);
791 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
792 if (orig_autoc
& IXGBE_AUTOC_KX4_SUPP
)
793 autoc
|= IXGBE_AUTOC_KX4_SUPP
;
794 if ((orig_autoc
& IXGBE_AUTOC_KR_SUPP
) &&
795 (hw
->phy
.smart_speed_active
== false))
796 autoc
|= IXGBE_AUTOC_KR_SUPP
;
797 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
798 autoc
|= IXGBE_AUTOC_KX_SUPP
;
799 } else if ((pma_pmd_1g
== IXGBE_AUTOC_1G_SFI
) &&
800 (link_mode
== IXGBE_AUTOC_LMS_1G_LINK_NO_AN
||
801 link_mode
== IXGBE_AUTOC_LMS_1G_AN
)) {
802 /* Switch from 1G SFI to 10G SFI if requested */
803 if ((speed
== IXGBE_LINK_SPEED_10GB_FULL
) &&
804 (pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_SFI
)) {
805 autoc
&= ~IXGBE_AUTOC_LMS_MASK
;
806 autoc
|= IXGBE_AUTOC_LMS_10G_SERIAL
;
808 } else if ((pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_SFI
) &&
809 (link_mode
== IXGBE_AUTOC_LMS_10G_SERIAL
)) {
810 /* Switch from 10G SFI to 1G SFI if requested */
811 if ((speed
== IXGBE_LINK_SPEED_1GB_FULL
) &&
812 (pma_pmd_1g
== IXGBE_AUTOC_1G_SFI
)) {
813 autoc
&= ~IXGBE_AUTOC_LMS_MASK
;
815 autoc
|= IXGBE_AUTOC_LMS_1G_AN
;
817 autoc
|= IXGBE_AUTOC_LMS_1G_LINK_NO_AN
;
821 if (autoc
!= start_autoc
) {
823 autoc
|= IXGBE_AUTOC_AN_RESTART
;
824 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc
);
826 /* Only poll for autoneg to complete if specified to do so */
827 if (autoneg_wait_to_complete
) {
828 if (link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR
||
829 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
||
830 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
) {
831 links_reg
= 0; /*Just in case Autoneg time=0*/
832 for (i
= 0; i
< IXGBE_AUTO_NEG_TIME
; i
++) {
834 IXGBE_READ_REG(hw
, IXGBE_LINKS
);
835 if (links_reg
& IXGBE_LINKS_KX_AN_COMP
)
839 if (!(links_reg
& IXGBE_LINKS_KX_AN_COMP
)) {
841 IXGBE_ERR_AUTONEG_NOT_COMPLETE
;
842 hw_dbg(hw
, "Autoneg did not "
848 /* Add delay to filter out noises during initial link setup */
857 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
858 * @hw: pointer to hardware structure
859 * @speed: new link speed
860 * @autoneg: true if autonegotiation enabled
861 * @autoneg_wait_to_complete: true if waiting is needed to complete
863 * Restarts link on PHY and MAC based on settings passed in.
865 static s32
ixgbe_setup_copper_link_82599(struct ixgbe_hw
*hw
,
866 ixgbe_link_speed speed
,
868 bool autoneg_wait_to_complete
)
872 /* Setup the PHY according to input speed */
873 status
= hw
->phy
.ops
.setup_link_speed(hw
, speed
, autoneg
,
874 autoneg_wait_to_complete
);
876 ixgbe_start_mac_link_82599(hw
, autoneg_wait_to_complete
);
882 * ixgbe_reset_hw_82599 - Perform hardware reset
883 * @hw: pointer to hardware structure
885 * Resets the hardware by resetting the transmit and receive units, masks
886 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
889 static s32
ixgbe_reset_hw_82599(struct ixgbe_hw
*hw
)
897 /* Call adapter stop to disable tx/rx and clear interrupts */
898 hw
->mac
.ops
.stop_adapter(hw
);
900 /* PHY ops must be identified and initialized prior to reset */
902 /* Init PHY and function pointers, perform SFP setup */
903 status
= hw
->phy
.ops
.init(hw
);
905 if (status
== IXGBE_ERR_SFP_NOT_SUPPORTED
)
908 /* Setup SFP module if there is one present. */
909 if (hw
->phy
.sfp_setup_needed
) {
910 status
= hw
->mac
.ops
.setup_sfp(hw
);
911 hw
->phy
.sfp_setup_needed
= false;
915 if (hw
->phy
.reset_disable
== false && hw
->phy
.ops
.reset
!= NULL
)
916 hw
->phy
.ops
.reset(hw
);
919 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
920 * access and verify no pending requests before reset
922 status
= ixgbe_disable_pcie_master(hw
);
924 status
= IXGBE_ERR_MASTER_REQUESTS_PENDING
;
925 hw_dbg(hw
, "PCI-E Master disable polling has failed.\n");
929 * Issue global reset to the MAC. This needs to be a SW reset.
930 * If link reset is used, it might reset the MAC when mng is using it
932 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
933 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, (ctrl
| IXGBE_CTRL_RST
));
934 IXGBE_WRITE_FLUSH(hw
);
936 /* Poll for reset bit to self-clear indicating reset is complete */
937 for (i
= 0; i
< 10; i
++) {
939 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
940 if (!(ctrl
& IXGBE_CTRL_RST
))
943 if (ctrl
& IXGBE_CTRL_RST
) {
944 status
= IXGBE_ERR_RESET_FAILED
;
945 hw_dbg(hw
, "Reset polling failed to complete.\n");
947 /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
948 ctrl_ext
= IXGBE_READ_REG(hw
, IXGBE_CTRL_EXT
);
949 ctrl_ext
|= IXGBE_CTRL_EXT_PFRSTD
;
950 IXGBE_WRITE_REG(hw
, IXGBE_CTRL_EXT
, ctrl_ext
);
957 * Store the original AUTOC/AUTOC2 values if they have not been
958 * stored off yet. Otherwise restore the stored original
959 * values since the reset operation sets back to defaults.
961 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
962 autoc2
= IXGBE_READ_REG(hw
, IXGBE_AUTOC2
);
963 if (hw
->mac
.orig_link_settings_stored
== false) {
964 hw
->mac
.orig_autoc
= autoc
;
965 hw
->mac
.orig_autoc2
= autoc2
;
966 hw
->mac
.orig_link_settings_stored
= true;
968 if (autoc
!= hw
->mac
.orig_autoc
)
969 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, (hw
->mac
.orig_autoc
|
970 IXGBE_AUTOC_AN_RESTART
));
972 if ((autoc2
& IXGBE_AUTOC2_UPPER_MASK
) !=
973 (hw
->mac
.orig_autoc2
& IXGBE_AUTOC2_UPPER_MASK
)) {
974 autoc2
&= ~IXGBE_AUTOC2_UPPER_MASK
;
975 autoc2
|= (hw
->mac
.orig_autoc2
&
976 IXGBE_AUTOC2_UPPER_MASK
);
977 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC2
, autoc2
);
982 * Store MAC address from RAR0, clear receive address registers, and
983 * clear the multicast table. Also reset num_rar_entries to 128,
984 * since we modify this value when programming the SAN MAC address.
986 hw
->mac
.num_rar_entries
= 128;
987 hw
->mac
.ops
.init_rx_addrs(hw
);
989 /* Store the permanent mac address */
990 hw
->mac
.ops
.get_mac_addr(hw
, hw
->mac
.perm_addr
);
992 /* Store the permanent SAN mac address */
993 hw
->mac
.ops
.get_san_mac_addr(hw
, hw
->mac
.san_addr
);
995 /* Add the SAN MAC address to the RAR only if it's a valid address */
996 if (ixgbe_validate_mac_addr(hw
->mac
.san_addr
) == 0) {
997 hw
->mac
.ops
.set_rar(hw
, hw
->mac
.num_rar_entries
- 1,
998 hw
->mac
.san_addr
, 0, IXGBE_RAH_AV
);
1000 /* Reserve the last RAR for the SAN MAC address */
1001 hw
->mac
.num_rar_entries
--;
1004 /* Store the alternative WWNN/WWPN prefix */
1005 hw
->mac
.ops
.get_wwn_prefix(hw
, &hw
->mac
.wwnn_prefix
,
1006 &hw
->mac
.wwpn_prefix
);
1013 * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
1014 * @hw: pointer to hardware struct
1015 * @rar: receive address register index to disassociate
1016 * @vmdq: VMDq pool index to remove from the rar
1018 static s32
ixgbe_clear_vmdq_82599(struct ixgbe_hw
*hw
, u32 rar
, u32 vmdq
)
1020 u32 mpsar_lo
, mpsar_hi
;
1021 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1023 if (rar
< rar_entries
) {
1024 mpsar_lo
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_LO(rar
));
1025 mpsar_hi
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_HI(rar
));
1027 if (!mpsar_lo
&& !mpsar_hi
)
1030 if (vmdq
== IXGBE_CLEAR_VMDQ_ALL
) {
1032 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(rar
), 0);
1036 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(rar
), 0);
1039 } else if (vmdq
< 32) {
1040 mpsar_lo
&= ~(1 << vmdq
);
1041 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(rar
), mpsar_lo
);
1043 mpsar_hi
&= ~(1 << (vmdq
- 32));
1044 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(rar
), mpsar_hi
);
1047 /* was that the last pool using this rar? */
1048 if (mpsar_lo
== 0 && mpsar_hi
== 0 && rar
!= 0)
1049 hw
->mac
.ops
.clear_rar(hw
, rar
);
1051 hw_dbg(hw
, "RAR index %d is out of range.\n", rar
);
1059 * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
1060 * @hw: pointer to hardware struct
1061 * @rar: receive address register index to associate with a VMDq index
1062 * @vmdq: VMDq pool index
1064 static s32
ixgbe_set_vmdq_82599(struct ixgbe_hw
*hw
, u32 rar
, u32 vmdq
)
1067 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1069 if (rar
< rar_entries
) {
1071 mpsar
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_LO(rar
));
1073 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(rar
), mpsar
);
1075 mpsar
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_HI(rar
));
1076 mpsar
|= 1 << (vmdq
- 32);
1077 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(rar
), mpsar
);
1080 hw_dbg(hw
, "RAR index %d is out of range.\n", rar
);
1086 * ixgbe_set_vfta_82599 - Set VLAN filter table
1087 * @hw: pointer to hardware structure
1088 * @vlan: VLAN id to write to VLAN filter
1089 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
1090 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
1092 * Turn on/off specified VLAN in the VLAN filter table.
1094 static s32
ixgbe_set_vfta_82599(struct ixgbe_hw
*hw
, u32 vlan
, u32 vind
,
1100 u32 first_empty_slot
;
1103 return IXGBE_ERR_PARAM
;
1106 * this is a 2 part operation - first the VFTA, then the
1107 * VLVF and VLVFB if vind is set
1111 * The VFTA is a bitstring made up of 128 32-bit registers
1112 * that enable the particular VLAN id, much like the MTA:
1113 * bits[11-5]: which register
1114 * bits[4-0]: which bit in the register
1116 regindex
= (vlan
>> 5) & 0x7F;
1117 bitindex
= vlan
& 0x1F;
1118 bits
= IXGBE_READ_REG(hw
, IXGBE_VFTA(regindex
));
1120 bits
|= (1 << bitindex
);
1122 bits
&= ~(1 << bitindex
);
1123 IXGBE_WRITE_REG(hw
, IXGBE_VFTA(regindex
), bits
);
1127 * If the vind is set
1129 * make sure the vlan is in VLVF
1130 * set the vind bit in the matching VLVFB
1132 * clear the pool bit and possibly the vind
1135 /* find the vlanid or the first empty slot */
1136 first_empty_slot
= 0;
1138 for (regindex
= 1; regindex
< IXGBE_VLVF_ENTRIES
; regindex
++) {
1139 bits
= IXGBE_READ_REG(hw
, IXGBE_VLVF(regindex
));
1140 if (!bits
&& !first_empty_slot
)
1141 first_empty_slot
= regindex
;
1142 else if ((bits
& 0x0FFF) == vlan
)
1146 if (regindex
>= IXGBE_VLVF_ENTRIES
) {
1147 if (first_empty_slot
)
1148 regindex
= first_empty_slot
;
1150 hw_dbg(hw
, "No space in VLVF.\n");
1156 /* set the pool bit */
1158 bits
= IXGBE_READ_REG(hw
,
1159 IXGBE_VLVFB(regindex
* 2));
1160 bits
|= (1 << vind
);
1162 IXGBE_VLVFB(regindex
* 2), bits
);
1164 bits
= IXGBE_READ_REG(hw
,
1165 IXGBE_VLVFB((regindex
* 2) + 1));
1166 bits
|= (1 << vind
);
1168 IXGBE_VLVFB((regindex
* 2) + 1), bits
);
1171 /* clear the pool bit */
1173 bits
= IXGBE_READ_REG(hw
,
1174 IXGBE_VLVFB(regindex
* 2));
1175 bits
&= ~(1 << vind
);
1177 IXGBE_VLVFB(regindex
* 2), bits
);
1178 bits
|= IXGBE_READ_REG(hw
,
1179 IXGBE_VLVFB((regindex
* 2) + 1));
1181 bits
= IXGBE_READ_REG(hw
,
1182 IXGBE_VLVFB((regindex
* 2) + 1));
1183 bits
&= ~(1 << vind
);
1185 IXGBE_VLVFB((regindex
* 2) + 1), bits
);
1186 bits
|= IXGBE_READ_REG(hw
,
1187 IXGBE_VLVFB(regindex
* 2));
1192 IXGBE_WRITE_REG(hw
, IXGBE_VLVF(regindex
),
1193 (IXGBE_VLVF_VIEN
| vlan
));
1195 IXGBE_WRITE_REG(hw
, IXGBE_VLVF(regindex
), 0);
1203 * ixgbe_clear_vfta_82599 - Clear VLAN filter table
1204 * @hw: pointer to hardware structure
1206 * Clears the VLAN filer table, and the VMDq index associated with the filter
1208 static s32
ixgbe_clear_vfta_82599(struct ixgbe_hw
*hw
)
1212 for (offset
= 0; offset
< hw
->mac
.vft_size
; offset
++)
1213 IXGBE_WRITE_REG(hw
, IXGBE_VFTA(offset
), 0);
1215 for (offset
= 0; offset
< IXGBE_VLVF_ENTRIES
; offset
++) {
1216 IXGBE_WRITE_REG(hw
, IXGBE_VLVF(offset
), 0);
1217 IXGBE_WRITE_REG(hw
, IXGBE_VLVFB(offset
* 2), 0);
1218 IXGBE_WRITE_REG(hw
, IXGBE_VLVFB((offset
* 2) + 1), 0);
1225 * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
1226 * @hw: pointer to hardware structure
1228 static s32
ixgbe_init_uta_tables_82599(struct ixgbe_hw
*hw
)
1231 hw_dbg(hw
, " Clearing UTA\n");
1233 for (i
= 0; i
< 128; i
++)
1234 IXGBE_WRITE_REG(hw
, IXGBE_UTA(i
), 0);
1240 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1241 * @hw: pointer to hardware structure
1243 s32
ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw
*hw
)
1246 u32 fdirctrl
= IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
);
1247 fdirctrl
&= ~IXGBE_FDIRCTRL_INIT_DONE
;
1250 * Before starting reinitialization process,
1251 * FDIRCMD.CMD must be zero.
1253 for (i
= 0; i
< IXGBE_FDIRCMD_CMD_POLL
; i
++) {
1254 if (!(IXGBE_READ_REG(hw
, IXGBE_FDIRCMD
) &
1255 IXGBE_FDIRCMD_CMD_MASK
))
1259 if (i
>= IXGBE_FDIRCMD_CMD_POLL
) {
1260 hw_dbg(hw
,"Flow Director previous command isn't complete, "
1261 "aborting table re-initialization. \n");
1262 return IXGBE_ERR_FDIR_REINIT_FAILED
;
1265 IXGBE_WRITE_REG(hw
, IXGBE_FDIRFREE
, 0);
1266 IXGBE_WRITE_FLUSH(hw
);
1268 * 82599 adapters flow director init flow cannot be restarted,
1269 * Workaround 82599 silicon errata by performing the following steps
1270 * before re-writing the FDIRCTRL control register with the same value.
1271 * - write 1 to bit 8 of FDIRCMD register &
1272 * - write 0 to bit 8 of FDIRCMD register
1274 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCMD
,
1275 (IXGBE_READ_REG(hw
, IXGBE_FDIRCMD
) |
1276 IXGBE_FDIRCMD_CLEARHT
));
1277 IXGBE_WRITE_FLUSH(hw
);
1278 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCMD
,
1279 (IXGBE_READ_REG(hw
, IXGBE_FDIRCMD
) &
1280 ~IXGBE_FDIRCMD_CLEARHT
));
1281 IXGBE_WRITE_FLUSH(hw
);
1283 * Clear FDIR Hash register to clear any leftover hashes
1284 * waiting to be programmed.
1286 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHASH
, 0x00);
1287 IXGBE_WRITE_FLUSH(hw
);
1289 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCTRL
, fdirctrl
);
1290 IXGBE_WRITE_FLUSH(hw
);
1292 /* Poll init-done after we write FDIRCTRL register */
1293 for (i
= 0; i
< IXGBE_FDIR_INIT_DONE_POLL
; i
++) {
1294 if (IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
) &
1295 IXGBE_FDIRCTRL_INIT_DONE
)
1299 if (i
>= IXGBE_FDIR_INIT_DONE_POLL
) {
1300 hw_dbg(hw
, "Flow Director Signature poll time exceeded!\n");
1301 return IXGBE_ERR_FDIR_REINIT_FAILED
;
1304 /* Clear FDIR statistics registers (read to clear) */
1305 IXGBE_READ_REG(hw
, IXGBE_FDIRUSTAT
);
1306 IXGBE_READ_REG(hw
, IXGBE_FDIRFSTAT
);
1307 IXGBE_READ_REG(hw
, IXGBE_FDIRMATCH
);
1308 IXGBE_READ_REG(hw
, IXGBE_FDIRMISS
);
1309 IXGBE_READ_REG(hw
, IXGBE_FDIRLEN
);
1315 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1316 * @hw: pointer to hardware structure
1317 * @pballoc: which mode to allocate filters with
1319 s32
ixgbe_init_fdir_signature_82599(struct ixgbe_hw
*hw
, u32 pballoc
)
1326 * Before enabling Flow Director, the Rx Packet Buffer size
1327 * must be reduced. The new value is the current size minus
1328 * flow director memory usage size.
1330 pbsize
= (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT
+ pballoc
));
1331 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(0),
1332 (IXGBE_READ_REG(hw
, IXGBE_RXPBSIZE(0)) - pbsize
));
1335 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1336 * intialized to zero for non DCB mode otherwise actual total RX PB
1337 * would be bigger than programmed and filter space would run into
1340 for (i
= 1; i
< 8; i
++)
1341 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(i
), 0);
1343 /* Send interrupt when 64 filters are left */
1344 fdirctrl
|= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT
;
1346 /* Set the maximum length per hash bucket to 0xA filters */
1347 fdirctrl
|= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT
;
1350 case IXGBE_FDIR_PBALLOC_64K
:
1351 /* 8k - 1 signature filters */
1352 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_64K
;
1354 case IXGBE_FDIR_PBALLOC_128K
:
1355 /* 16k - 1 signature filters */
1356 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_128K
;
1358 case IXGBE_FDIR_PBALLOC_256K
:
1359 /* 32k - 1 signature filters */
1360 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_256K
;
1364 return IXGBE_ERR_CONFIG
;
1367 /* Move the flexible bytes to use the ethertype - shift 6 words */
1368 fdirctrl
|= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT
);
1370 fdirctrl
|= IXGBE_FDIRCTRL_REPORT_STATUS
;
1372 /* Prime the keys for hashing */
1373 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHKEY
,
1374 htonl(IXGBE_ATR_BUCKET_HASH_KEY
));
1375 IXGBE_WRITE_REG(hw
, IXGBE_FDIRSKEY
,
1376 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY
));
1379 * Poll init-done after we write the register. Estimated times:
1380 * 10G: PBALLOC = 11b, timing is 60us
1381 * 1G: PBALLOC = 11b, timing is 600us
1382 * 100M: PBALLOC = 11b, timing is 6ms
1384 * Multiple these timings by 4 if under full Rx load
1386 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1387 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1388 * this might not finish in our poll time, but we can live with that
1391 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCTRL
, fdirctrl
);
1392 IXGBE_WRITE_FLUSH(hw
);
1393 for (i
= 0; i
< IXGBE_FDIR_INIT_DONE_POLL
; i
++) {
1394 if (IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
) &
1395 IXGBE_FDIRCTRL_INIT_DONE
)
1399 if (i
>= IXGBE_FDIR_INIT_DONE_POLL
)
1400 hw_dbg(hw
, "Flow Director Signature poll time exceeded!\n");
1406 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1407 * @hw: pointer to hardware structure
1408 * @pballoc: which mode to allocate filters with
1410 s32
ixgbe_init_fdir_perfect_82599(struct ixgbe_hw
*hw
, u32 pballoc
)
1417 * Before enabling Flow Director, the Rx Packet Buffer size
1418 * must be reduced. The new value is the current size minus
1419 * flow director memory usage size.
1421 pbsize
= (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT
+ pballoc
));
1422 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(0),
1423 (IXGBE_READ_REG(hw
, IXGBE_RXPBSIZE(0)) - pbsize
));
1426 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1427 * intialized to zero for non DCB mode otherwise actual total RX PB
1428 * would be bigger than programmed and filter space would run into
1431 for (i
= 1; i
< 8; i
++)
1432 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(i
), 0);
1434 /* Send interrupt when 64 filters are left */
1435 fdirctrl
|= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT
;
1438 case IXGBE_FDIR_PBALLOC_64K
:
1439 /* 2k - 1 perfect filters */
1440 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_64K
;
1442 case IXGBE_FDIR_PBALLOC_128K
:
1443 /* 4k - 1 perfect filters */
1444 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_128K
;
1446 case IXGBE_FDIR_PBALLOC_256K
:
1447 /* 8k - 1 perfect filters */
1448 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_256K
;
1452 return IXGBE_ERR_CONFIG
;
1455 /* Turn perfect match filtering on */
1456 fdirctrl
|= IXGBE_FDIRCTRL_PERFECT_MATCH
;
1457 fdirctrl
|= IXGBE_FDIRCTRL_REPORT_STATUS
;
1459 /* Move the flexible bytes to use the ethertype - shift 6 words */
1460 fdirctrl
|= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT
);
1462 /* Prime the keys for hashing */
1463 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHKEY
,
1464 htonl(IXGBE_ATR_BUCKET_HASH_KEY
));
1465 IXGBE_WRITE_REG(hw
, IXGBE_FDIRSKEY
,
1466 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY
));
1469 * Poll init-done after we write the register. Estimated times:
1470 * 10G: PBALLOC = 11b, timing is 60us
1471 * 1G: PBALLOC = 11b, timing is 600us
1472 * 100M: PBALLOC = 11b, timing is 6ms
1474 * Multiple these timings by 4 if under full Rx load
1476 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1477 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1478 * this might not finish in our poll time, but we can live with that
1482 /* Set the maximum length per hash bucket to 0xA filters */
1483 fdirctrl
|= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT
);
1485 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCTRL
, fdirctrl
);
1486 IXGBE_WRITE_FLUSH(hw
);
1487 for (i
= 0; i
< IXGBE_FDIR_INIT_DONE_POLL
; i
++) {
1488 if (IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
) &
1489 IXGBE_FDIRCTRL_INIT_DONE
)
1493 if (i
>= IXGBE_FDIR_INIT_DONE_POLL
)
1494 hw_dbg(hw
, "Flow Director Perfect poll time exceeded!\n");
1501 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1502 * @stream: input bitstream to compute the hash on
1503 * @key: 32-bit hash key
1505 static u16
ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input
*atr_input
,
1509 * The algorithm is as follows:
1510 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1511 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1512 * and A[n] x B[n] is bitwise AND between same length strings
1514 * K[n] is 16 bits, defined as:
1515 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1516 * for n modulo 32 < 15, K[n] =
1517 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1519 * S[n] is 16 bits, defined as:
1520 * for n >= 15, S[n] = S[n:n - 15]
1521 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1523 * To simplify for programming, the algorithm is implemented
1524 * in software this way:
1526 * Key[31:0], Stream[335:0]
1528 * tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times
1529 * int_key[350:0] = tmp_key[351:1]
1530 * int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321]
1533 * for (i = 0; i < 351; i++) {
1535 * hash ^= int_stream[(i + 15):i];
1545 u8
*stream
= (u8
*)atr_input
;
1546 u8 int_key
[44]; /* upper-most bit unused */
1547 u8 hash_str
[46]; /* upper-most 2 bits unused */
1548 u16 hash_result
= 0;
1552 * Initialize the fill member to prevent warnings
1555 tmp_key
.fill
[0] = 0;
1557 /* First load the temporary key stream */
1558 for (i
= 0; i
< 6; i
++) {
1559 u64 fillkey
= ((u64
)key
<< 32) | key
;
1560 tmp_key
.fill
[i
] = fillkey
;
1564 * Set the interim key for the hashing. Bit 352 is unused, so we must
1565 * shift and compensate when building the key.
1568 int_key
[0] = tmp_key
.key_stream
[0] >> 1;
1569 for (i
= 1, j
= 0; i
< 44; i
++) {
1570 unsigned int this_key
= tmp_key
.key_stream
[j
] << 7;
1572 int_key
[i
] = (u8
)(this_key
| (tmp_key
.key_stream
[j
] >> 1));
1576 * Set the interim bit string for the hashing. Bits 368 and 367 are
1577 * unused, so shift and compensate when building the string.
1579 hash_str
[0] = (stream
[40] & 0x7f) >> 1;
1580 for (i
= 1, j
= 40; i
< 46; i
++) {
1581 unsigned int this_str
= stream
[j
] << 7;
1585 hash_str
[i
] = (u8
)(this_str
| (stream
[j
] >> 1));
1589 * Now compute the hash. i is the index into hash_str, j is into our
1590 * key stream, k is counting the number of bits, and h interates within
1593 for (i
= 45, j
= 43, k
= 0; k
< 351 && i
>= 2 && j
>= 0; i
--, j
--) {
1594 for (h
= 0; h
< 8 && k
< 351; h
++, k
++) {
1595 if (int_key
[j
] & (1 << h
)) {
1597 * Key bit is set, XOR in the current 16-bit
1598 * string. Example of processing:
1600 * tmp = (hash_str[i - 2] & 0 << 16) |
1601 * (hash_str[i - 1] & 0xff << 8) |
1602 * (hash_str[i] & 0xff >> 0)
1603 * So tmp = hash_str[15 + k:k], since the
1604 * i + 2 clause rolls off the 16-bit value
1606 * tmp = (hash_str[i - 2] & 0x7f << 9) |
1607 * (hash_str[i - 1] & 0xff << 1) |
1608 * (hash_str[i] & 0x80 >> 7)
1610 int tmp
= (hash_str
[i
] >> h
);
1611 tmp
|= (hash_str
[i
- 1] << (8 - h
));
1612 tmp
|= (int)(hash_str
[i
- 2] & ((1 << h
) - 1))
1614 hash_result
^= (u16
)tmp
;
1623 * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream
1624 * @input: input stream to modify
1625 * @vlan: the VLAN id to load
1627 s32
ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input
*input
, u16 vlan
)
1629 input
->byte_stream
[IXGBE_ATR_VLAN_OFFSET
+ 1] = vlan
>> 8;
1630 input
->byte_stream
[IXGBE_ATR_VLAN_OFFSET
] = vlan
& 0xff;
1636 * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address
1637 * @input: input stream to modify
1638 * @src_addr: the IP address to load
1640 s32
ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input
*input
, u32 src_addr
)
1642 input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
+ 3] = src_addr
>> 24;
1643 input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
+ 2] =
1644 (src_addr
>> 16) & 0xff;
1645 input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
+ 1] =
1646 (src_addr
>> 8) & 0xff;
1647 input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
] = src_addr
& 0xff;
1653 * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address
1654 * @input: input stream to modify
1655 * @dst_addr: the IP address to load
1657 s32
ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input
*input
, u32 dst_addr
)
1659 input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
+ 3] = dst_addr
>> 24;
1660 input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
+ 2] =
1661 (dst_addr
>> 16) & 0xff;
1662 input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
+ 1] =
1663 (dst_addr
>> 8) & 0xff;
1664 input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
] = dst_addr
& 0xff;
1670 * ixgbe_atr_set_src_ipv6_82599 - Sets the source IPv6 address
1671 * @input: input stream to modify
1672 * @src_addr_1: the first 4 bytes of the IP address to load
1673 * @src_addr_2: the second 4 bytes of the IP address to load
1674 * @src_addr_3: the third 4 bytes of the IP address to load
1675 * @src_addr_4: the fourth 4 bytes of the IP address to load
1677 s32
ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input
*input
,
1678 u32 src_addr_1
, u32 src_addr_2
,
1679 u32 src_addr_3
, u32 src_addr_4
)
1681 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
] = src_addr_4
& 0xff;
1682 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 1] =
1683 (src_addr_4
>> 8) & 0xff;
1684 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 2] =
1685 (src_addr_4
>> 16) & 0xff;
1686 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 3] = src_addr_4
>> 24;
1688 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 4] = src_addr_3
& 0xff;
1689 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 5] =
1690 (src_addr_3
>> 8) & 0xff;
1691 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 6] =
1692 (src_addr_3
>> 16) & 0xff;
1693 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 7] = src_addr_3
>> 24;
1695 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 8] = src_addr_2
& 0xff;
1696 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 9] =
1697 (src_addr_2
>> 8) & 0xff;
1698 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 10] =
1699 (src_addr_2
>> 16) & 0xff;
1700 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 11] = src_addr_2
>> 24;
1702 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 12] = src_addr_1
& 0xff;
1703 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 13] =
1704 (src_addr_1
>> 8) & 0xff;
1705 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 14] =
1706 (src_addr_1
>> 16) & 0xff;
1707 input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 15] = src_addr_1
>> 24;
1713 * ixgbe_atr_set_dst_ipv6_82599 - Sets the destination IPv6 address
1714 * @input: input stream to modify
1715 * @dst_addr_1: the first 4 bytes of the IP address to load
1716 * @dst_addr_2: the second 4 bytes of the IP address to load
1717 * @dst_addr_3: the third 4 bytes of the IP address to load
1718 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1720 s32
ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input
*input
,
1721 u32 dst_addr_1
, u32 dst_addr_2
,
1722 u32 dst_addr_3
, u32 dst_addr_4
)
1724 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
] = dst_addr_4
& 0xff;
1725 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 1] =
1726 (dst_addr_4
>> 8) & 0xff;
1727 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 2] =
1728 (dst_addr_4
>> 16) & 0xff;
1729 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 3] = dst_addr_4
>> 24;
1731 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 4] = dst_addr_3
& 0xff;
1732 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 5] =
1733 (dst_addr_3
>> 8) & 0xff;
1734 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 6] =
1735 (dst_addr_3
>> 16) & 0xff;
1736 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 7] = dst_addr_3
>> 24;
1738 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 8] = dst_addr_2
& 0xff;
1739 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 9] =
1740 (dst_addr_2
>> 8) & 0xff;
1741 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 10] =
1742 (dst_addr_2
>> 16) & 0xff;
1743 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 11] = dst_addr_2
>> 24;
1745 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 12] = dst_addr_1
& 0xff;
1746 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 13] =
1747 (dst_addr_1
>> 8) & 0xff;
1748 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 14] =
1749 (dst_addr_1
>> 16) & 0xff;
1750 input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 15] = dst_addr_1
>> 24;
1756 * ixgbe_atr_set_src_port_82599 - Sets the source port
1757 * @input: input stream to modify
1758 * @src_port: the source port to load
1760 s32
ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input
*input
, u16 src_port
)
1762 input
->byte_stream
[IXGBE_ATR_SRC_PORT_OFFSET
+ 1] = src_port
>> 8;
1763 input
->byte_stream
[IXGBE_ATR_SRC_PORT_OFFSET
] = src_port
& 0xff;
1769 * ixgbe_atr_set_dst_port_82599 - Sets the destination port
1770 * @input: input stream to modify
1771 * @dst_port: the destination port to load
1773 s32
ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input
*input
, u16 dst_port
)
1775 input
->byte_stream
[IXGBE_ATR_DST_PORT_OFFSET
+ 1] = dst_port
>> 8;
1776 input
->byte_stream
[IXGBE_ATR_DST_PORT_OFFSET
] = dst_port
& 0xff;
1782 * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes
1783 * @input: input stream to modify
1784 * @flex_bytes: the flexible bytes to load
1786 s32
ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input
*input
, u16 flex_byte
)
1788 input
->byte_stream
[IXGBE_ATR_FLEX_BYTE_OFFSET
+ 1] = flex_byte
>> 8;
1789 input
->byte_stream
[IXGBE_ATR_FLEX_BYTE_OFFSET
] = flex_byte
& 0xff;
1795 * ixgbe_atr_set_vm_pool_82599 - Sets the Virtual Machine pool
1796 * @input: input stream to modify
1797 * @vm_pool: the Virtual Machine pool to load
1799 s32
ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input
*input
,
1802 input
->byte_stream
[IXGBE_ATR_VM_POOL_OFFSET
] = vm_pool
;
1808 * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type
1809 * @input: input stream to modify
1810 * @l4type: the layer 4 type value to load
1812 s32
ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input
*input
, u8 l4type
)
1814 input
->byte_stream
[IXGBE_ATR_L4TYPE_OFFSET
] = l4type
;
1820 * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream
1821 * @input: input stream to search
1822 * @vlan: the VLAN id to load
1824 static s32
ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input
*input
,
1827 *vlan
= input
->byte_stream
[IXGBE_ATR_VLAN_OFFSET
];
1828 *vlan
|= input
->byte_stream
[IXGBE_ATR_VLAN_OFFSET
+ 1] << 8;
1834 * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address
1835 * @input: input stream to search
1836 * @src_addr: the IP address to load
1838 static s32
ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input
*input
,
1841 *src_addr
= input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
];
1842 *src_addr
|= input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
+ 1] << 8;
1843 *src_addr
|= input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
+ 2] << 16;
1844 *src_addr
|= input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
+ 3] << 24;
1850 * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address
1851 * @input: input stream to search
1852 * @dst_addr: the IP address to load
1854 static s32
ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input
*input
,
1857 *dst_addr
= input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
];
1858 *dst_addr
|= input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
+ 1] << 8;
1859 *dst_addr
|= input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
+ 2] << 16;
1860 *dst_addr
|= input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
+ 3] << 24;
1866 * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address
1867 * @input: input stream to search
1868 * @src_addr_1: the first 4 bytes of the IP address to load
1869 * @src_addr_2: the second 4 bytes of the IP address to load
1870 * @src_addr_3: the third 4 bytes of the IP address to load
1871 * @src_addr_4: the fourth 4 bytes of the IP address to load
1873 static s32
ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input
*input
,
1874 u32
*src_addr_1
, u32
*src_addr_2
,
1875 u32
*src_addr_3
, u32
*src_addr_4
)
1877 *src_addr_1
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 12];
1878 *src_addr_1
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 13] << 8;
1879 *src_addr_1
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 14] << 16;
1880 *src_addr_1
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 15] << 24;
1882 *src_addr_2
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 8];
1883 *src_addr_2
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 9] << 8;
1884 *src_addr_2
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 10] << 16;
1885 *src_addr_2
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 11] << 24;
1887 *src_addr_3
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 4];
1888 *src_addr_3
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 5] << 8;
1889 *src_addr_3
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 6] << 16;
1890 *src_addr_3
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 7] << 24;
1892 *src_addr_4
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
];
1893 *src_addr_4
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 1] << 8;
1894 *src_addr_4
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 2] << 16;
1895 *src_addr_4
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 3] << 24;
1901 * ixgbe_atr_get_dst_ipv6_82599 - Gets the destination IPv6 address
1902 * @input: input stream to search
1903 * @dst_addr_1: the first 4 bytes of the IP address to load
1904 * @dst_addr_2: the second 4 bytes of the IP address to load
1905 * @dst_addr_3: the third 4 bytes of the IP address to load
1906 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1908 s32
ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input
*input
,
1909 u32
*dst_addr_1
, u32
*dst_addr_2
,
1910 u32
*dst_addr_3
, u32
*dst_addr_4
)
1912 *dst_addr_1
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 12];
1913 *dst_addr_1
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 13] << 8;
1914 *dst_addr_1
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 14] << 16;
1915 *dst_addr_1
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 15] << 24;
1917 *dst_addr_2
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 8];
1918 *dst_addr_2
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 9] << 8;
1919 *dst_addr_2
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 10] << 16;
1920 *dst_addr_2
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 11] << 24;
1922 *dst_addr_3
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 4];
1923 *dst_addr_3
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 5] << 8;
1924 *dst_addr_3
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 6] << 16;
1925 *dst_addr_3
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 7] << 24;
1927 *dst_addr_4
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
];
1928 *dst_addr_4
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 1] << 8;
1929 *dst_addr_4
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 2] << 16;
1930 *dst_addr_4
= input
->byte_stream
[IXGBE_ATR_DST_IPV6_OFFSET
+ 3] << 24;
1936 * ixgbe_atr_get_src_port_82599 - Gets the source port
1937 * @input: input stream to modify
1938 * @src_port: the source port to load
1940 * Even though the input is given in big-endian, the FDIRPORT registers
1941 * expect the ports to be programmed in little-endian. Hence the need to swap
1942 * endianness when retrieving the data. This can be confusing since the
1943 * internal hash engine expects it to be big-endian.
1945 static s32
ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input
*input
,
1948 *src_port
= input
->byte_stream
[IXGBE_ATR_SRC_PORT_OFFSET
] << 8;
1949 *src_port
|= input
->byte_stream
[IXGBE_ATR_SRC_PORT_OFFSET
+ 1];
1955 * ixgbe_atr_get_dst_port_82599 - Gets the destination port
1956 * @input: input stream to modify
1957 * @dst_port: the destination port to load
1959 * Even though the input is given in big-endian, the FDIRPORT registers
1960 * expect the ports to be programmed in little-endian. Hence the need to swap
1961 * endianness when retrieving the data. This can be confusing since the
1962 * internal hash engine expects it to be big-endian.
1964 static s32
ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input
*input
,
1967 *dst_port
= input
->byte_stream
[IXGBE_ATR_DST_PORT_OFFSET
] << 8;
1968 *dst_port
|= input
->byte_stream
[IXGBE_ATR_DST_PORT_OFFSET
+ 1];
1974 * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes
1975 * @input: input stream to modify
1976 * @flex_bytes: the flexible bytes to load
1978 static s32
ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input
*input
,
1981 *flex_byte
= input
->byte_stream
[IXGBE_ATR_FLEX_BYTE_OFFSET
];
1982 *flex_byte
|= input
->byte_stream
[IXGBE_ATR_FLEX_BYTE_OFFSET
+ 1] << 8;
1988 * ixgbe_atr_get_vm_pool_82599 - Gets the Virtual Machine pool
1989 * @input: input stream to modify
1990 * @vm_pool: the Virtual Machine pool to load
1992 s32
ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input
*input
,
1995 *vm_pool
= input
->byte_stream
[IXGBE_ATR_VM_POOL_OFFSET
];
2001 * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type
2002 * @input: input stream to modify
2003 * @l4type: the layer 4 type value to load
2005 static s32
ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input
*input
,
2008 *l4type
= input
->byte_stream
[IXGBE_ATR_L4TYPE_OFFSET
];
2014 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
2015 * @hw: pointer to hardware structure
2016 * @stream: input bitstream
2017 * @queue: queue index to direct traffic to
2019 s32
ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw
*hw
,
2020 struct ixgbe_atr_input
*input
,
2026 u16 bucket_hash
, sig_hash
;
2029 bucket_hash
= ixgbe_atr_compute_hash_82599(input
,
2030 IXGBE_ATR_BUCKET_HASH_KEY
);
2032 /* bucket_hash is only 15 bits */
2033 bucket_hash
&= IXGBE_ATR_HASH_MASK
;
2035 sig_hash
= ixgbe_atr_compute_hash_82599(input
,
2036 IXGBE_ATR_SIGNATURE_HASH_KEY
);
2038 /* Get the l4type in order to program FDIRCMD properly */
2039 /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */
2040 ixgbe_atr_get_l4type_82599(input
, &l4type
);
2043 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
2044 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
2046 fdirhash
= sig_hash
<< IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT
| bucket_hash
;
2048 fdircmd
= (IXGBE_FDIRCMD_CMD_ADD_FLOW
| IXGBE_FDIRCMD_FILTER_UPDATE
|
2049 IXGBE_FDIRCMD_LAST
| IXGBE_FDIRCMD_QUEUE_EN
);
2051 switch (l4type
& IXGBE_ATR_L4TYPE_MASK
) {
2052 case IXGBE_ATR_L4TYPE_TCP
:
2053 fdircmd
|= IXGBE_FDIRCMD_L4TYPE_TCP
;
2055 case IXGBE_ATR_L4TYPE_UDP
:
2056 fdircmd
|= IXGBE_FDIRCMD_L4TYPE_UDP
;
2058 case IXGBE_ATR_L4TYPE_SCTP
:
2059 fdircmd
|= IXGBE_FDIRCMD_L4TYPE_SCTP
;
2062 hw_dbg(hw
, "Error on l4type input\n");
2063 return IXGBE_ERR_CONFIG
;
2066 if (l4type
& IXGBE_ATR_L4TYPE_IPV6_MASK
)
2067 fdircmd
|= IXGBE_FDIRCMD_IPV6
;
2069 fdircmd
|= ((u64
)queue
<< IXGBE_FDIRCMD_RX_QUEUE_SHIFT
);
2070 fdirhashcmd
= ((fdircmd
<< 32) | fdirhash
);
2072 IXGBE_WRITE_REG64(hw
, IXGBE_FDIRHASH
, fdirhashcmd
);
2078 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
2079 * @hw: pointer to hardware structure
2080 * @input: input bitstream
2081 * @queue: queue index to direct traffic to
2083 * Note that the caller to this function must lock before calling, since the
2084 * hardware writes must be protected from one another.
2086 s32
ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw
*hw
,
2087 struct ixgbe_atr_input
*input
,
2093 u32 src_ipv4
, dst_ipv4
;
2094 u32 src_ipv6_1
, src_ipv6_2
, src_ipv6_3
, src_ipv6_4
;
2095 u16 src_port
, dst_port
, vlan_id
, flex_bytes
;
2099 /* Get our input values */
2100 ixgbe_atr_get_l4type_82599(input
, &l4type
);
2103 * Check l4type formatting, and bail out before we touch the hardware
2104 * if there's a configuration issue
2106 switch (l4type
& IXGBE_ATR_L4TYPE_MASK
) {
2107 case IXGBE_ATR_L4TYPE_TCP
:
2108 fdircmd
|= IXGBE_FDIRCMD_L4TYPE_TCP
;
2110 case IXGBE_ATR_L4TYPE_UDP
:
2111 fdircmd
|= IXGBE_FDIRCMD_L4TYPE_UDP
;
2113 case IXGBE_ATR_L4TYPE_SCTP
:
2114 fdircmd
|= IXGBE_FDIRCMD_L4TYPE_SCTP
;
2117 hw_dbg(hw
, "Error on l4type input\n");
2118 return IXGBE_ERR_CONFIG
;
2121 bucket_hash
= ixgbe_atr_compute_hash_82599(input
,
2122 IXGBE_ATR_BUCKET_HASH_KEY
);
2124 /* bucket_hash is only 15 bits */
2125 bucket_hash
&= IXGBE_ATR_HASH_MASK
;
2127 ixgbe_atr_get_vlan_id_82599(input
, &vlan_id
);
2128 ixgbe_atr_get_src_port_82599(input
, &src_port
);
2129 ixgbe_atr_get_dst_port_82599(input
, &dst_port
);
2130 ixgbe_atr_get_flex_byte_82599(input
, &flex_bytes
);
2132 fdirhash
= soft_id
<< IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT
| bucket_hash
;
2134 /* Now figure out if we're IPv4 or IPv6 */
2135 if (l4type
& IXGBE_ATR_L4TYPE_IPV6_MASK
) {
2137 ixgbe_atr_get_src_ipv6_82599(input
, &src_ipv6_1
, &src_ipv6_2
,
2138 &src_ipv6_3
, &src_ipv6_4
);
2140 IXGBE_WRITE_REG(hw
, IXGBE_FDIRSIPv6(0), src_ipv6_1
);
2141 IXGBE_WRITE_REG(hw
, IXGBE_FDIRSIPv6(1), src_ipv6_2
);
2142 IXGBE_WRITE_REG(hw
, IXGBE_FDIRSIPv6(2), src_ipv6_3
);
2143 /* The last 4 bytes is the same register as IPv4 */
2144 IXGBE_WRITE_REG(hw
, IXGBE_FDIRIPSA
, src_ipv6_4
);
2146 fdircmd
|= IXGBE_FDIRCMD_IPV6
;
2147 fdircmd
|= IXGBE_FDIRCMD_IPv6DMATCH
;
2150 ixgbe_atr_get_src_ipv4_82599(input
, &src_ipv4
);
2151 IXGBE_WRITE_REG(hw
, IXGBE_FDIRIPSA
, src_ipv4
);
2155 ixgbe_atr_get_dst_ipv4_82599(input
, &dst_ipv4
);
2156 IXGBE_WRITE_REG(hw
, IXGBE_FDIRIPDA
, dst_ipv4
);
2158 IXGBE_WRITE_REG(hw
, IXGBE_FDIRVLAN
, (vlan_id
|
2159 (flex_bytes
<< IXGBE_FDIRVLAN_FLEX_SHIFT
)));
2160 IXGBE_WRITE_REG(hw
, IXGBE_FDIRPORT
, (src_port
|
2161 (dst_port
<< IXGBE_FDIRPORT_DESTINATION_SHIFT
)));
2163 fdircmd
|= IXGBE_FDIRCMD_CMD_ADD_FLOW
;
2164 fdircmd
|= IXGBE_FDIRCMD_FILTER_UPDATE
;
2165 fdircmd
|= IXGBE_FDIRCMD_LAST
;
2166 fdircmd
|= IXGBE_FDIRCMD_QUEUE_EN
;
2167 fdircmd
|= queue
<< IXGBE_FDIRCMD_RX_QUEUE_SHIFT
;
2169 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHASH
, fdirhash
);
2170 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCMD
, fdircmd
);
2175 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
2176 * @hw: pointer to hardware structure
2177 * @reg: analog register to read
2180 * Performs read operation to Omer analog register specified.
2182 static s32
ixgbe_read_analog_reg8_82599(struct ixgbe_hw
*hw
, u32 reg
, u8
*val
)
2186 IXGBE_WRITE_REG(hw
, IXGBE_CORECTL
, IXGBE_CORECTL_WRITE_CMD
|
2188 IXGBE_WRITE_FLUSH(hw
);
2190 core_ctl
= IXGBE_READ_REG(hw
, IXGBE_CORECTL
);
2191 *val
= (u8
)core_ctl
;
2197 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2198 * @hw: pointer to hardware structure
2199 * @reg: atlas register to write
2200 * @val: value to write
2202 * Performs write operation to Omer analog register specified.
2204 static s32
ixgbe_write_analog_reg8_82599(struct ixgbe_hw
*hw
, u32 reg
, u8 val
)
2208 core_ctl
= (reg
<< 8) | val
;
2209 IXGBE_WRITE_REG(hw
, IXGBE_CORECTL
, core_ctl
);
2210 IXGBE_WRITE_FLUSH(hw
);
2217 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2218 * @hw: pointer to hardware structure
2220 * Starts the hardware using the generic start_hw function.
2221 * Then performs device-specific:
2222 * Clears the rate limiter registers.
2224 static s32
ixgbe_start_hw_82599(struct ixgbe_hw
*hw
)
2229 ret_val
= ixgbe_start_hw_generic(hw
);
2231 /* Clear the rate limiters */
2232 for (q_num
= 0; q_num
< hw
->mac
.max_tx_queues
; q_num
++) {
2233 IXGBE_WRITE_REG(hw
, IXGBE_RTTDQSEL
, q_num
);
2234 IXGBE_WRITE_REG(hw
, IXGBE_RTTBCNRC
, 0);
2236 IXGBE_WRITE_FLUSH(hw
);
2238 /* We need to run link autotry after the driver loads */
2239 hw
->mac
.autotry_restart
= true;
2242 ret_val
= ixgbe_verify_fw_version_82599(hw
);
2248 * ixgbe_identify_phy_82599 - Get physical layer module
2249 * @hw: pointer to hardware structure
2251 * Determines the physical layer module found on the current adapter.
2253 static s32
ixgbe_identify_phy_82599(struct ixgbe_hw
*hw
)
2255 s32 status
= IXGBE_ERR_PHY_ADDR_INVALID
;
2256 status
= ixgbe_identify_phy_generic(hw
);
2258 status
= ixgbe_identify_sfp_module_generic(hw
);
2263 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2264 * @hw: pointer to hardware structure
2266 * Determines physical layer capabilities of the current configuration.
2268 static u32
ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw
*hw
)
2270 u32 physical_layer
= IXGBE_PHYSICAL_LAYER_UNKNOWN
;
2271 u32 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
2272 u32 autoc2
= IXGBE_READ_REG(hw
, IXGBE_AUTOC2
);
2273 u32 pma_pmd_10g_serial
= autoc2
& IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK
;
2274 u32 pma_pmd_10g_parallel
= autoc
& IXGBE_AUTOC_10G_PMA_PMD_MASK
;
2275 u32 pma_pmd_1g
= autoc
& IXGBE_AUTOC_1G_PMA_PMD_MASK
;
2276 u16 ext_ability
= 0;
2277 u8 comp_codes_10g
= 0;
2279 hw
->phy
.ops
.identify(hw
);
2281 if (hw
->phy
.type
== ixgbe_phy_tn
||
2282 hw
->phy
.type
== ixgbe_phy_cu_unknown
) {
2283 hw
->phy
.ops
.read_reg(hw
, MDIO_PMA_EXTABLE
, MDIO_MMD_PMAPMD
,
2285 if (ext_ability
& MDIO_PMA_EXTABLE_10GBT
)
2286 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_T
;
2287 if (ext_ability
& MDIO_PMA_EXTABLE_1000BT
)
2288 physical_layer
|= IXGBE_PHYSICAL_LAYER_1000BASE_T
;
2289 if (ext_ability
& MDIO_PMA_EXTABLE_100BTX
)
2290 physical_layer
|= IXGBE_PHYSICAL_LAYER_100BASE_TX
;
2294 switch (autoc
& IXGBE_AUTOC_LMS_MASK
) {
2295 case IXGBE_AUTOC_LMS_1G_AN
:
2296 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN
:
2297 if (pma_pmd_1g
== IXGBE_AUTOC_1G_KX_BX
) {
2298 physical_layer
= IXGBE_PHYSICAL_LAYER_1000BASE_KX
|
2299 IXGBE_PHYSICAL_LAYER_1000BASE_BX
;
2302 /* SFI mode so read SFP module */
2305 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN
:
2306 if (pma_pmd_10g_parallel
== IXGBE_AUTOC_10G_CX4
)
2307 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_CX4
;
2308 else if (pma_pmd_10g_parallel
== IXGBE_AUTOC_10G_KX4
)
2309 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_KX4
;
2310 else if (pma_pmd_10g_parallel
== IXGBE_AUTOC_10G_XAUI
)
2311 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_XAUI
;
2314 case IXGBE_AUTOC_LMS_10G_SERIAL
:
2315 if (pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_KR
) {
2316 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_KR
;
2318 } else if (pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_SFI
)
2321 case IXGBE_AUTOC_LMS_KX4_KX_KR
:
2322 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
:
2323 if (autoc
& IXGBE_AUTOC_KX_SUPP
)
2324 physical_layer
|= IXGBE_PHYSICAL_LAYER_1000BASE_KX
;
2325 if (autoc
& IXGBE_AUTOC_KX4_SUPP
)
2326 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_KX4
;
2327 if (autoc
& IXGBE_AUTOC_KR_SUPP
)
2328 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_KR
;
2337 /* SFP check must be done last since DA modules are sometimes used to
2338 * test KR mode - we need to id KR mode correctly before SFP module.
2339 * Call identify_sfp because the pluggable module may have changed */
2340 hw
->phy
.ops
.identify_sfp(hw
);
2341 if (hw
->phy
.sfp_type
== ixgbe_sfp_type_not_present
)
2344 switch (hw
->phy
.type
) {
2345 case ixgbe_phy_tw_tyco
:
2346 case ixgbe_phy_tw_unknown
:
2347 physical_layer
= IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU
;
2349 case ixgbe_phy_sfp_avago
:
2350 case ixgbe_phy_sfp_ftl
:
2351 case ixgbe_phy_sfp_intel
:
2352 case ixgbe_phy_sfp_unknown
:
2353 hw
->phy
.ops
.read_i2c_eeprom(hw
,
2354 IXGBE_SFF_10GBE_COMP_CODES
, &comp_codes_10g
);
2355 if (comp_codes_10g
& IXGBE_SFF_10GBASESR_CAPABLE
)
2356 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_SR
;
2357 else if (comp_codes_10g
& IXGBE_SFF_10GBASELR_CAPABLE
)
2358 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_LR
;
2365 return physical_layer
;
2369 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2370 * @hw: pointer to hardware structure
2371 * @regval: register value to write to RXCTRL
2373 * Enables the Rx DMA unit for 82599
2375 static s32
ixgbe_enable_rx_dma_82599(struct ixgbe_hw
*hw
, u32 regval
)
2377 #define IXGBE_MAX_SECRX_POLL 30
2382 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2383 * If traffic is incoming before we enable the Rx unit, it could hang
2384 * the Rx DMA unit. Therefore, make sure the security engine is
2385 * completely disabled prior to enabling the Rx unit.
2387 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXCTRL
);
2388 secrxreg
|= IXGBE_SECRXCTRL_RX_DIS
;
2389 IXGBE_WRITE_REG(hw
, IXGBE_SECRXCTRL
, secrxreg
);
2390 for (i
= 0; i
< IXGBE_MAX_SECRX_POLL
; i
++) {
2391 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXSTAT
);
2392 if (secrxreg
& IXGBE_SECRXSTAT_SECRX_RDY
)
2398 /* For informational purposes only */
2399 if (i
>= IXGBE_MAX_SECRX_POLL
)
2400 hw_dbg(hw
, "Rx unit being enabled before security "
2401 "path fully disabled. Continuing with init.\n");
2403 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, regval
);
2404 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXCTRL
);
2405 secrxreg
&= ~IXGBE_SECRXCTRL_RX_DIS
;
2406 IXGBE_WRITE_REG(hw
, IXGBE_SECRXCTRL
, secrxreg
);
2407 IXGBE_WRITE_FLUSH(hw
);
2413 * ixgbe_get_device_caps_82599 - Get additional device capabilities
2414 * @hw: pointer to hardware structure
2415 * @device_caps: the EEPROM word with the extra device capabilities
2417 * This function will read the EEPROM location for the device capabilities,
2418 * and return the word through device_caps.
2420 static s32
ixgbe_get_device_caps_82599(struct ixgbe_hw
*hw
, u16
*device_caps
)
2422 hw
->eeprom
.ops
.read(hw
, IXGBE_DEVICE_CAPS
, device_caps
);
2428 * ixgbe_get_san_mac_addr_offset_82599 - SAN MAC address offset for 82599
2429 * @hw: pointer to hardware structure
2430 * @san_mac_offset: SAN MAC address offset
2432 * This function will read the EEPROM location for the SAN MAC address
2433 * pointer, and returns the value at that location. This is used in both
2434 * get and set mac_addr routines.
2436 static s32
ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw
*hw
,
2437 u16
*san_mac_offset
)
2440 * First read the EEPROM pointer to see if the MAC addresses are
2443 hw
->eeprom
.ops
.read(hw
, IXGBE_SAN_MAC_ADDR_PTR
, san_mac_offset
);
2449 * ixgbe_get_san_mac_addr_82599 - SAN MAC address retrieval for 82599
2450 * @hw: pointer to hardware structure
2451 * @san_mac_addr: SAN MAC address
2453 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2454 * per-port, so set_lan_id() must be called before reading the addresses.
2455 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2456 * upon for non-SFP connections, so we must call it here.
2458 static s32
ixgbe_get_san_mac_addr_82599(struct ixgbe_hw
*hw
, u8
*san_mac_addr
)
2460 u16 san_mac_data
, san_mac_offset
;
2464 * First read the EEPROM pointer to see if the MAC addresses are
2465 * available. If they're not, no point in calling set_lan_id() here.
2467 ixgbe_get_san_mac_addr_offset_82599(hw
, &san_mac_offset
);
2469 if ((san_mac_offset
== 0) || (san_mac_offset
== 0xFFFF)) {
2471 * No addresses available in this EEPROM. It's not an
2472 * error though, so just wipe the local address and return.
2474 for (i
= 0; i
< 6; i
++)
2475 san_mac_addr
[i
] = 0xFF;
2477 goto san_mac_addr_out
;
2480 /* make sure we know which port we need to program */
2481 hw
->mac
.ops
.set_lan_id(hw
);
2482 /* apply the port offset to the address offset */
2483 (hw
->bus
.func
) ? (san_mac_offset
+= IXGBE_SAN_MAC_ADDR_PORT1_OFFSET
) :
2484 (san_mac_offset
+= IXGBE_SAN_MAC_ADDR_PORT0_OFFSET
);
2485 for (i
= 0; i
< 3; i
++) {
2486 hw
->eeprom
.ops
.read(hw
, san_mac_offset
, &san_mac_data
);
2487 san_mac_addr
[i
* 2] = (u8
)(san_mac_data
);
2488 san_mac_addr
[i
* 2 + 1] = (u8
)(san_mac_data
>> 8);
2497 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2498 * @hw: pointer to hardware structure
2500 * Verifies that installed the firmware version is 0.6 or higher
2501 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2503 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2504 * if the FW version is not supported.
2506 static s32
ixgbe_verify_fw_version_82599(struct ixgbe_hw
*hw
)
2508 s32 status
= IXGBE_ERR_EEPROM_VERSION
;
2509 u16 fw_offset
, fw_ptp_cfg_offset
;
2512 /* firmware check is only necessary for SFI devices */
2513 if (hw
->phy
.media_type
!= ixgbe_media_type_fiber
) {
2515 goto fw_version_out
;
2518 /* get the offset to the Firmware Module block */
2519 hw
->eeprom
.ops
.read(hw
, IXGBE_FW_PTR
, &fw_offset
);
2521 if ((fw_offset
== 0) || (fw_offset
== 0xFFFF))
2522 goto fw_version_out
;
2524 /* get the offset to the Pass Through Patch Configuration block */
2525 hw
->eeprom
.ops
.read(hw
, (fw_offset
+
2526 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR
),
2527 &fw_ptp_cfg_offset
);
2529 if ((fw_ptp_cfg_offset
== 0) || (fw_ptp_cfg_offset
== 0xFFFF))
2530 goto fw_version_out
;
2532 /* get the firmware version */
2533 hw
->eeprom
.ops
.read(hw
, (fw_ptp_cfg_offset
+
2534 IXGBE_FW_PATCH_VERSION_4
),
2537 if (fw_version
> 0x5)
2545 * ixgbe_get_wwn_prefix_82599 - Get alternative WWNN/WWPN prefix from
2547 * @hw: pointer to hardware structure
2548 * @wwnn_prefix: the alternative WWNN prefix
2549 * @wwpn_prefix: the alternative WWPN prefix
2551 * This function will read the EEPROM from the alternative SAN MAC address
2552 * block to check the support for the alternative WWNN/WWPN prefix support.
2554 static s32
ixgbe_get_wwn_prefix_82599(struct ixgbe_hw
*hw
, u16
*wwnn_prefix
,
2558 u16 alt_san_mac_blk_offset
;
2560 /* clear output first */
2561 *wwnn_prefix
= 0xFFFF;
2562 *wwpn_prefix
= 0xFFFF;
2564 /* check if alternative SAN MAC is supported */
2565 hw
->eeprom
.ops
.read(hw
, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR
,
2566 &alt_san_mac_blk_offset
);
2568 if ((alt_san_mac_blk_offset
== 0) ||
2569 (alt_san_mac_blk_offset
== 0xFFFF))
2570 goto wwn_prefix_out
;
2572 /* check capability in alternative san mac address block */
2573 offset
= alt_san_mac_blk_offset
+ IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET
;
2574 hw
->eeprom
.ops
.read(hw
, offset
, &caps
);
2575 if (!(caps
& IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN
))
2576 goto wwn_prefix_out
;
2578 /* get the corresponding prefix for WWNN/WWPN */
2579 offset
= alt_san_mac_blk_offset
+ IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET
;
2580 hw
->eeprom
.ops
.read(hw
, offset
, wwnn_prefix
);
2582 offset
= alt_san_mac_blk_offset
+ IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET
;
2583 hw
->eeprom
.ops
.read(hw
, offset
, wwpn_prefix
);
2589 static struct ixgbe_mac_operations mac_ops_82599
= {
2590 .init_hw
= &ixgbe_init_hw_generic
,
2591 .reset_hw
= &ixgbe_reset_hw_82599
,
2592 .start_hw
= &ixgbe_start_hw_82599
,
2593 .clear_hw_cntrs
= &ixgbe_clear_hw_cntrs_generic
,
2594 .get_media_type
= &ixgbe_get_media_type_82599
,
2595 .get_supported_physical_layer
= &ixgbe_get_supported_physical_layer_82599
,
2596 .enable_rx_dma
= &ixgbe_enable_rx_dma_82599
,
2597 .get_mac_addr
= &ixgbe_get_mac_addr_generic
,
2598 .get_san_mac_addr
= &ixgbe_get_san_mac_addr_82599
,
2599 .get_device_caps
= &ixgbe_get_device_caps_82599
,
2600 .get_wwn_prefix
= &ixgbe_get_wwn_prefix_82599
,
2601 .stop_adapter
= &ixgbe_stop_adapter_generic
,
2602 .get_bus_info
= &ixgbe_get_bus_info_generic
,
2603 .set_lan_id
= &ixgbe_set_lan_id_multi_port_pcie
,
2604 .read_analog_reg8
= &ixgbe_read_analog_reg8_82599
,
2605 .write_analog_reg8
= &ixgbe_write_analog_reg8_82599
,
2606 .setup_link
= &ixgbe_setup_mac_link_82599
,
2607 .check_link
= &ixgbe_check_mac_link_82599
,
2608 .get_link_capabilities
= &ixgbe_get_link_capabilities_82599
,
2609 .led_on
= &ixgbe_led_on_generic
,
2610 .led_off
= &ixgbe_led_off_generic
,
2611 .blink_led_start
= &ixgbe_blink_led_start_generic
,
2612 .blink_led_stop
= &ixgbe_blink_led_stop_generic
,
2613 .set_rar
= &ixgbe_set_rar_generic
,
2614 .clear_rar
= &ixgbe_clear_rar_generic
,
2615 .set_vmdq
= &ixgbe_set_vmdq_82599
,
2616 .clear_vmdq
= &ixgbe_clear_vmdq_82599
,
2617 .init_rx_addrs
= &ixgbe_init_rx_addrs_generic
,
2618 .update_uc_addr_list
= &ixgbe_update_uc_addr_list_generic
,
2619 .update_mc_addr_list
= &ixgbe_update_mc_addr_list_generic
,
2620 .enable_mc
= &ixgbe_enable_mc_generic
,
2621 .disable_mc
= &ixgbe_disable_mc_generic
,
2622 .clear_vfta
= &ixgbe_clear_vfta_82599
,
2623 .set_vfta
= &ixgbe_set_vfta_82599
,
2624 .fc_enable
= &ixgbe_fc_enable_generic
,
2625 .init_uta_tables
= &ixgbe_init_uta_tables_82599
,
2626 .setup_sfp
= &ixgbe_setup_sfp_modules_82599
,
2629 static struct ixgbe_eeprom_operations eeprom_ops_82599
= {
2630 .init_params
= &ixgbe_init_eeprom_params_generic
,
2631 .read
= &ixgbe_read_eeprom_generic
,
2632 .write
= &ixgbe_write_eeprom_generic
,
2633 .validate_checksum
= &ixgbe_validate_eeprom_checksum_generic
,
2634 .update_checksum
= &ixgbe_update_eeprom_checksum_generic
,
2637 static struct ixgbe_phy_operations phy_ops_82599
= {
2638 .identify
= &ixgbe_identify_phy_82599
,
2639 .identify_sfp
= &ixgbe_identify_sfp_module_generic
,
2640 .init
= &ixgbe_init_phy_ops_82599
,
2641 .reset
= &ixgbe_reset_phy_generic
,
2642 .read_reg
= &ixgbe_read_phy_reg_generic
,
2643 .write_reg
= &ixgbe_write_phy_reg_generic
,
2644 .setup_link
= &ixgbe_setup_phy_link_generic
,
2645 .setup_link_speed
= &ixgbe_setup_phy_link_speed_generic
,
2646 .read_i2c_byte
= &ixgbe_read_i2c_byte_generic
,
2647 .write_i2c_byte
= &ixgbe_write_i2c_byte_generic
,
2648 .read_i2c_eeprom
= &ixgbe_read_i2c_eeprom_generic
,
2649 .write_i2c_eeprom
= &ixgbe_write_i2c_eeprom_generic
,
2652 struct ixgbe_info ixgbe_82599_info
= {
2653 .mac
= ixgbe_mac_82599EB
,
2654 .get_invariants
= &ixgbe_get_invariants_82599
,
2655 .mac_ops
= &mac_ops_82599
,
2656 .eeprom_ops
= &eeprom_ops_82599
,
2657 .phy_ops
= &phy_ops_82599
,