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[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
45 #include <linux/if_vlan.h>
46 #include <linux/prefetch.h>
47 #include <scsi/fc/fc_fcoe.h>
48
49 #include "ixgbe.h"
50 #include "ixgbe_common.h"
51 #include "ixgbe_dcb_82599.h"
52 #include "ixgbe_sriov.h"
53
54 char ixgbe_driver_name[] = "ixgbe";
55 static const char ixgbe_driver_string[] =
56 "Intel(R) 10 Gigabit PCI Express Network Driver";
57 #define MAJ 3
58 #define MIN 4
59 #define BUILD 8
60 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
61 __stringify(BUILD) "-k"
62 const char ixgbe_driver_version[] = DRV_VERSION;
63 static const char ixgbe_copyright[] =
64 "Copyright (c) 1999-2011 Intel Corporation.";
65
66 static const struct ixgbe_info *ixgbe_info_tbl[] = {
67 [board_82598] = &ixgbe_82598_info,
68 [board_82599] = &ixgbe_82599_info,
69 [board_X540] = &ixgbe_X540_info,
70 };
71
72 /* ixgbe_pci_tbl - PCI Device ID Table
73 *
74 * Wildcard entries (PCI_ANY_ID) should come last
75 * Last entry must be all 0s
76 *
77 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
78 * Class, Class Mask, private data (not used) }
79 */
80 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
82 board_82598 },
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
84 board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
86 board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
88 board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
90 board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
92 board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
94 board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
96 board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
98 board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
100 board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
102 board_82598 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
104 board_82598 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
106 board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
108 board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
110 board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
112 board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
114 board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
116 board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
118 board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
120 board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
122 board_82599 },
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
124 board_82599 },
125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
126 board_82599 },
127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
128 board_X540 },
129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2),
130 board_82599 },
131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS),
132 board_82599 },
133
134 /* required last entry */
135 {0, }
136 };
137 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
138
139 #ifdef CONFIG_IXGBE_DCA
140 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
141 void *p);
142 static struct notifier_block dca_notifier = {
143 .notifier_call = ixgbe_notify_dca,
144 .next = NULL,
145 .priority = 0
146 };
147 #endif
148
149 #ifdef CONFIG_PCI_IOV
150 static unsigned int max_vfs;
151 module_param(max_vfs, uint, 0);
152 MODULE_PARM_DESC(max_vfs,
153 "Maximum number of virtual functions to allocate per physical function");
154 #endif /* CONFIG_PCI_IOV */
155
156 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
157 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
158 MODULE_LICENSE("GPL");
159 MODULE_VERSION(DRV_VERSION);
160
161 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
162
163 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
164 {
165 struct ixgbe_hw *hw = &adapter->hw;
166 u32 gcr;
167 u32 gpie;
168 u32 vmdctl;
169
170 #ifdef CONFIG_PCI_IOV
171 /* disable iov and allow time for transactions to clear */
172 pci_disable_sriov(adapter->pdev);
173 #endif
174
175 /* turn off device IOV mode */
176 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
177 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
178 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
179 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
180 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
181 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
182
183 /* set default pool back to 0 */
184 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
185 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
186 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
187
188 /* take a breather then clean up driver data */
189 msleep(100);
190
191 kfree(adapter->vfinfo);
192 adapter->vfinfo = NULL;
193
194 adapter->num_vfs = 0;
195 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
196 }
197
198 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
199 {
200 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
201 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
202 schedule_work(&adapter->service_task);
203 }
204
205 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
206 {
207 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
208
209 /* flush memory to make sure state is correct before next watchog */
210 smp_mb__before_clear_bit();
211 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
212 }
213
214 struct ixgbe_reg_info {
215 u32 ofs;
216 char *name;
217 };
218
219 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
220
221 /* General Registers */
222 {IXGBE_CTRL, "CTRL"},
223 {IXGBE_STATUS, "STATUS"},
224 {IXGBE_CTRL_EXT, "CTRL_EXT"},
225
226 /* Interrupt Registers */
227 {IXGBE_EICR, "EICR"},
228
229 /* RX Registers */
230 {IXGBE_SRRCTL(0), "SRRCTL"},
231 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
232 {IXGBE_RDLEN(0), "RDLEN"},
233 {IXGBE_RDH(0), "RDH"},
234 {IXGBE_RDT(0), "RDT"},
235 {IXGBE_RXDCTL(0), "RXDCTL"},
236 {IXGBE_RDBAL(0), "RDBAL"},
237 {IXGBE_RDBAH(0), "RDBAH"},
238
239 /* TX Registers */
240 {IXGBE_TDBAL(0), "TDBAL"},
241 {IXGBE_TDBAH(0), "TDBAH"},
242 {IXGBE_TDLEN(0), "TDLEN"},
243 {IXGBE_TDH(0), "TDH"},
244 {IXGBE_TDT(0), "TDT"},
245 {IXGBE_TXDCTL(0), "TXDCTL"},
246
247 /* List Terminator */
248 {}
249 };
250
251
252 /*
253 * ixgbe_regdump - register printout routine
254 */
255 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
256 {
257 int i = 0, j = 0;
258 char rname[16];
259 u32 regs[64];
260
261 switch (reginfo->ofs) {
262 case IXGBE_SRRCTL(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
265 break;
266 case IXGBE_DCA_RXCTRL(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
269 break;
270 case IXGBE_RDLEN(0):
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
273 break;
274 case IXGBE_RDH(0):
275 for (i = 0; i < 64; i++)
276 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
277 break;
278 case IXGBE_RDT(0):
279 for (i = 0; i < 64; i++)
280 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
281 break;
282 case IXGBE_RXDCTL(0):
283 for (i = 0; i < 64; i++)
284 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
285 break;
286 case IXGBE_RDBAL(0):
287 for (i = 0; i < 64; i++)
288 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
289 break;
290 case IXGBE_RDBAH(0):
291 for (i = 0; i < 64; i++)
292 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
293 break;
294 case IXGBE_TDBAL(0):
295 for (i = 0; i < 64; i++)
296 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
297 break;
298 case IXGBE_TDBAH(0):
299 for (i = 0; i < 64; i++)
300 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
301 break;
302 case IXGBE_TDLEN(0):
303 for (i = 0; i < 64; i++)
304 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
305 break;
306 case IXGBE_TDH(0):
307 for (i = 0; i < 64; i++)
308 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
309 break;
310 case IXGBE_TDT(0):
311 for (i = 0; i < 64; i++)
312 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
313 break;
314 case IXGBE_TXDCTL(0):
315 for (i = 0; i < 64; i++)
316 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
317 break;
318 default:
319 pr_info("%-15s %08x\n", reginfo->name,
320 IXGBE_READ_REG(hw, reginfo->ofs));
321 return;
322 }
323
324 for (i = 0; i < 8; i++) {
325 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
326 pr_err("%-15s", rname);
327 for (j = 0; j < 8; j++)
328 pr_cont(" %08x", regs[i*8+j]);
329 pr_cont("\n");
330 }
331
332 }
333
334 /*
335 * ixgbe_dump - Print registers, tx-rings and rx-rings
336 */
337 static void ixgbe_dump(struct ixgbe_adapter *adapter)
338 {
339 struct net_device *netdev = adapter->netdev;
340 struct ixgbe_hw *hw = &adapter->hw;
341 struct ixgbe_reg_info *reginfo;
342 int n = 0;
343 struct ixgbe_ring *tx_ring;
344 struct ixgbe_tx_buffer *tx_buffer_info;
345 union ixgbe_adv_tx_desc *tx_desc;
346 struct my_u0 { u64 a; u64 b; } *u0;
347 struct ixgbe_ring *rx_ring;
348 union ixgbe_adv_rx_desc *rx_desc;
349 struct ixgbe_rx_buffer *rx_buffer_info;
350 u32 staterr;
351 int i = 0;
352
353 if (!netif_msg_hw(adapter))
354 return;
355
356 /* Print netdevice Info */
357 if (netdev) {
358 dev_info(&adapter->pdev->dev, "Net device Info\n");
359 pr_info("Device Name state "
360 "trans_start last_rx\n");
361 pr_info("%-15s %016lX %016lX %016lX\n",
362 netdev->name,
363 netdev->state,
364 netdev->trans_start,
365 netdev->last_rx);
366 }
367
368 /* Print Registers */
369 dev_info(&adapter->pdev->dev, "Register Dump\n");
370 pr_info(" Register Name Value\n");
371 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
372 reginfo->name; reginfo++) {
373 ixgbe_regdump(hw, reginfo);
374 }
375
376 /* Print TX Ring Summary */
377 if (!netdev || !netif_running(netdev))
378 goto exit;
379
380 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
381 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
382 for (n = 0; n < adapter->num_tx_queues; n++) {
383 tx_ring = adapter->tx_ring[n];
384 tx_buffer_info =
385 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
386 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
387 n, tx_ring->next_to_use, tx_ring->next_to_clean,
388 (u64)tx_buffer_info->dma,
389 tx_buffer_info->length,
390 tx_buffer_info->next_to_watch,
391 (u64)tx_buffer_info->time_stamp);
392 }
393
394 /* Print TX Rings */
395 if (!netif_msg_tx_done(adapter))
396 goto rx_ring_summary;
397
398 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
399
400 /* Transmit Descriptor Formats
401 *
402 * Advanced Transmit Descriptor
403 * +--------------------------------------------------------------+
404 * 0 | Buffer Address [63:0] |
405 * +--------------------------------------------------------------+
406 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
407 * +--------------------------------------------------------------+
408 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
409 */
410
411 for (n = 0; n < adapter->num_tx_queues; n++) {
412 tx_ring = adapter->tx_ring[n];
413 pr_info("------------------------------------\n");
414 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
415 pr_info("------------------------------------\n");
416 pr_info("T [desc] [address 63:0 ] "
417 "[PlPOIdStDDt Ln] [bi->dma ] "
418 "leng ntw timestamp bi->skb\n");
419
420 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
421 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
422 tx_buffer_info = &tx_ring->tx_buffer_info[i];
423 u0 = (struct my_u0 *)tx_desc;
424 pr_info("T [0x%03X] %016llX %016llX %016llX"
425 " %04X %3X %016llX %p", i,
426 le64_to_cpu(u0->a),
427 le64_to_cpu(u0->b),
428 (u64)tx_buffer_info->dma,
429 tx_buffer_info->length,
430 tx_buffer_info->next_to_watch,
431 (u64)tx_buffer_info->time_stamp,
432 tx_buffer_info->skb);
433 if (i == tx_ring->next_to_use &&
434 i == tx_ring->next_to_clean)
435 pr_cont(" NTC/U\n");
436 else if (i == tx_ring->next_to_use)
437 pr_cont(" NTU\n");
438 else if (i == tx_ring->next_to_clean)
439 pr_cont(" NTC\n");
440 else
441 pr_cont("\n");
442
443 if (netif_msg_pktdata(adapter) &&
444 tx_buffer_info->dma != 0)
445 print_hex_dump(KERN_INFO, "",
446 DUMP_PREFIX_ADDRESS, 16, 1,
447 phys_to_virt(tx_buffer_info->dma),
448 tx_buffer_info->length, true);
449 }
450 }
451
452 /* Print RX Rings Summary */
453 rx_ring_summary:
454 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
455 pr_info("Queue [NTU] [NTC]\n");
456 for (n = 0; n < adapter->num_rx_queues; n++) {
457 rx_ring = adapter->rx_ring[n];
458 pr_info("%5d %5X %5X\n",
459 n, rx_ring->next_to_use, rx_ring->next_to_clean);
460 }
461
462 /* Print RX Rings */
463 if (!netif_msg_rx_status(adapter))
464 goto exit;
465
466 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
467
468 /* Advanced Receive Descriptor (Read) Format
469 * 63 1 0
470 * +-----------------------------------------------------+
471 * 0 | Packet Buffer Address [63:1] |A0/NSE|
472 * +----------------------------------------------+------+
473 * 8 | Header Buffer Address [63:1] | DD |
474 * +-----------------------------------------------------+
475 *
476 *
477 * Advanced Receive Descriptor (Write-Back) Format
478 *
479 * 63 48 47 32 31 30 21 20 16 15 4 3 0
480 * +------------------------------------------------------+
481 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
482 * | Checksum Ident | | | | Type | Type |
483 * +------------------------------------------------------+
484 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
485 * +------------------------------------------------------+
486 * 63 48 47 32 31 20 19 0
487 */
488 for (n = 0; n < adapter->num_rx_queues; n++) {
489 rx_ring = adapter->rx_ring[n];
490 pr_info("------------------------------------\n");
491 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
492 pr_info("------------------------------------\n");
493 pr_info("R [desc] [ PktBuf A0] "
494 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
495 "<-- Adv Rx Read format\n");
496 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
497 "[vl er S cks ln] ---------------- [bi->skb] "
498 "<-- Adv Rx Write-Back format\n");
499
500 for (i = 0; i < rx_ring->count; i++) {
501 rx_buffer_info = &rx_ring->rx_buffer_info[i];
502 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
503 u0 = (struct my_u0 *)rx_desc;
504 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
505 if (staterr & IXGBE_RXD_STAT_DD) {
506 /* Descriptor Done */
507 pr_info("RWB[0x%03X] %016llX "
508 "%016llX ---------------- %p", i,
509 le64_to_cpu(u0->a),
510 le64_to_cpu(u0->b),
511 rx_buffer_info->skb);
512 } else {
513 pr_info("R [0x%03X] %016llX "
514 "%016llX %016llX %p", i,
515 le64_to_cpu(u0->a),
516 le64_to_cpu(u0->b),
517 (u64)rx_buffer_info->dma,
518 rx_buffer_info->skb);
519
520 if (netif_msg_pktdata(adapter)) {
521 print_hex_dump(KERN_INFO, "",
522 DUMP_PREFIX_ADDRESS, 16, 1,
523 phys_to_virt(rx_buffer_info->dma),
524 rx_ring->rx_buf_len, true);
525
526 if (rx_ring->rx_buf_len
527 < IXGBE_RXBUFFER_2048)
528 print_hex_dump(KERN_INFO, "",
529 DUMP_PREFIX_ADDRESS, 16, 1,
530 phys_to_virt(
531 rx_buffer_info->page_dma +
532 rx_buffer_info->page_offset
533 ),
534 PAGE_SIZE/2, true);
535 }
536 }
537
538 if (i == rx_ring->next_to_use)
539 pr_cont(" NTU\n");
540 else if (i == rx_ring->next_to_clean)
541 pr_cont(" NTC\n");
542 else
543 pr_cont("\n");
544
545 }
546 }
547
548 exit:
549 return;
550 }
551
552 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
553 {
554 u32 ctrl_ext;
555
556 /* Let firmware take over control of h/w */
557 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
558 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
559 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
560 }
561
562 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
563 {
564 u32 ctrl_ext;
565
566 /* Let firmware know the driver has taken over */
567 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
568 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
569 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
570 }
571
572 /*
573 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
574 * @adapter: pointer to adapter struct
575 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
576 * @queue: queue to map the corresponding interrupt to
577 * @msix_vector: the vector to map to the corresponding queue
578 *
579 */
580 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
581 u8 queue, u8 msix_vector)
582 {
583 u32 ivar, index;
584 struct ixgbe_hw *hw = &adapter->hw;
585 switch (hw->mac.type) {
586 case ixgbe_mac_82598EB:
587 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
588 if (direction == -1)
589 direction = 0;
590 index = (((direction * 64) + queue) >> 2) & 0x1F;
591 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
592 ivar &= ~(0xFF << (8 * (queue & 0x3)));
593 ivar |= (msix_vector << (8 * (queue & 0x3)));
594 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
595 break;
596 case ixgbe_mac_82599EB:
597 case ixgbe_mac_X540:
598 if (direction == -1) {
599 /* other causes */
600 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
601 index = ((queue & 1) * 8);
602 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
603 ivar &= ~(0xFF << index);
604 ivar |= (msix_vector << index);
605 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
606 break;
607 } else {
608 /* tx or rx causes */
609 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
610 index = ((16 * (queue & 1)) + (8 * direction));
611 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
612 ivar &= ~(0xFF << index);
613 ivar |= (msix_vector << index);
614 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
615 break;
616 }
617 default:
618 break;
619 }
620 }
621
622 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
623 u64 qmask)
624 {
625 u32 mask;
626
627 switch (adapter->hw.mac.type) {
628 case ixgbe_mac_82598EB:
629 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
630 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
631 break;
632 case ixgbe_mac_82599EB:
633 case ixgbe_mac_X540:
634 mask = (qmask & 0xFFFFFFFF);
635 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
636 mask = (qmask >> 32);
637 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
638 break;
639 default:
640 break;
641 }
642 }
643
644 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
645 struct ixgbe_tx_buffer *tx_buffer_info)
646 {
647 if (tx_buffer_info->dma) {
648 if (tx_buffer_info->mapped_as_page)
649 dma_unmap_page(tx_ring->dev,
650 tx_buffer_info->dma,
651 tx_buffer_info->length,
652 DMA_TO_DEVICE);
653 else
654 dma_unmap_single(tx_ring->dev,
655 tx_buffer_info->dma,
656 tx_buffer_info->length,
657 DMA_TO_DEVICE);
658 tx_buffer_info->dma = 0;
659 }
660 if (tx_buffer_info->skb) {
661 dev_kfree_skb_any(tx_buffer_info->skb);
662 tx_buffer_info->skb = NULL;
663 }
664 tx_buffer_info->time_stamp = 0;
665 /* tx_buffer_info must be completely set up in the transmit path */
666 }
667
668 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
669 {
670 struct ixgbe_hw *hw = &adapter->hw;
671 struct ixgbe_hw_stats *hwstats = &adapter->stats;
672 u32 data = 0;
673 u32 xoff[8] = {0};
674 int i;
675
676 if ((hw->fc.current_mode == ixgbe_fc_full) ||
677 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
678 switch (hw->mac.type) {
679 case ixgbe_mac_82598EB:
680 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
681 break;
682 default:
683 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
684 }
685 hwstats->lxoffrxc += data;
686
687 /* refill credits (no tx hang) if we received xoff */
688 if (!data)
689 return;
690
691 for (i = 0; i < adapter->num_tx_queues; i++)
692 clear_bit(__IXGBE_HANG_CHECK_ARMED,
693 &adapter->tx_ring[i]->state);
694 return;
695 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
696 return;
697
698 /* update stats for each tc, only valid with PFC enabled */
699 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
700 switch (hw->mac.type) {
701 case ixgbe_mac_82598EB:
702 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
703 break;
704 default:
705 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
706 }
707 hwstats->pxoffrxc[i] += xoff[i];
708 }
709
710 /* disarm tx queues that have received xoff frames */
711 for (i = 0; i < adapter->num_tx_queues; i++) {
712 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
713 u8 tc = tx_ring->dcb_tc;
714
715 if (xoff[tc])
716 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
717 }
718 }
719
720 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
721 {
722 return ring->tx_stats.completed;
723 }
724
725 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
726 {
727 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
728 struct ixgbe_hw *hw = &adapter->hw;
729
730 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
731 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
732
733 if (head != tail)
734 return (head < tail) ?
735 tail - head : (tail + ring->count - head);
736
737 return 0;
738 }
739
740 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
741 {
742 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
743 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
744 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
745 bool ret = false;
746
747 clear_check_for_tx_hang(tx_ring);
748
749 /*
750 * Check for a hung queue, but be thorough. This verifies
751 * that a transmit has been completed since the previous
752 * check AND there is at least one packet pending. The
753 * ARMED bit is set to indicate a potential hang. The
754 * bit is cleared if a pause frame is received to remove
755 * false hang detection due to PFC or 802.3x frames. By
756 * requiring this to fail twice we avoid races with
757 * pfc clearing the ARMED bit and conditions where we
758 * run the check_tx_hang logic with a transmit completion
759 * pending but without time to complete it yet.
760 */
761 if ((tx_done_old == tx_done) && tx_pending) {
762 /* make sure it is true for two checks in a row */
763 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
764 &tx_ring->state);
765 } else {
766 /* update completed stats and continue */
767 tx_ring->tx_stats.tx_done_old = tx_done;
768 /* reset the countdown */
769 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
770 }
771
772 return ret;
773 }
774
775 /**
776 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
777 * @adapter: driver private struct
778 **/
779 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
780 {
781
782 /* Do the reset outside of interrupt context */
783 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
784 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
785 ixgbe_service_event_schedule(adapter);
786 }
787 }
788
789 /**
790 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
791 * @q_vector: structure containing interrupt and ring information
792 * @tx_ring: tx ring to clean
793 **/
794 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
795 struct ixgbe_ring *tx_ring)
796 {
797 struct ixgbe_adapter *adapter = q_vector->adapter;
798 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
799 struct ixgbe_tx_buffer *tx_buffer_info;
800 unsigned int total_bytes = 0, total_packets = 0;
801 u16 i, eop, count = 0;
802
803 i = tx_ring->next_to_clean;
804 eop = tx_ring->tx_buffer_info[i].next_to_watch;
805 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
806
807 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
808 (count < q_vector->tx.work_limit)) {
809 bool cleaned = false;
810 rmb(); /* read buffer_info after eop_desc */
811 for ( ; !cleaned; count++) {
812 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
813 tx_buffer_info = &tx_ring->tx_buffer_info[i];
814
815 tx_desc->wb.status = 0;
816 cleaned = (i == eop);
817
818 i++;
819 if (i == tx_ring->count)
820 i = 0;
821
822 if (cleaned && tx_buffer_info->skb) {
823 total_bytes += tx_buffer_info->bytecount;
824 total_packets += tx_buffer_info->gso_segs;
825 }
826
827 ixgbe_unmap_and_free_tx_resource(tx_ring,
828 tx_buffer_info);
829 }
830
831 tx_ring->tx_stats.completed++;
832 eop = tx_ring->tx_buffer_info[i].next_to_watch;
833 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
834 }
835
836 tx_ring->next_to_clean = i;
837 tx_ring->stats.bytes += total_bytes;
838 tx_ring->stats.packets += total_packets;
839 u64_stats_update_begin(&tx_ring->syncp);
840 q_vector->tx.total_bytes += total_bytes;
841 q_vector->tx.total_packets += total_packets;
842 u64_stats_update_end(&tx_ring->syncp);
843
844 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
845 /* schedule immediate reset if we believe we hung */
846 struct ixgbe_hw *hw = &adapter->hw;
847 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
848 e_err(drv, "Detected Tx Unit Hang\n"
849 " Tx Queue <%d>\n"
850 " TDH, TDT <%x>, <%x>\n"
851 " next_to_use <%x>\n"
852 " next_to_clean <%x>\n"
853 "tx_buffer_info[next_to_clean]\n"
854 " time_stamp <%lx>\n"
855 " jiffies <%lx>\n",
856 tx_ring->queue_index,
857 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
858 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
859 tx_ring->next_to_use, eop,
860 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
861
862 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
863
864 e_info(probe,
865 "tx hang %d detected on queue %d, resetting adapter\n",
866 adapter->tx_timeout_count + 1, tx_ring->queue_index);
867
868 /* schedule immediate reset if we believe we hung */
869 ixgbe_tx_timeout_reset(adapter);
870
871 /* the adapter is about to reset, no point in enabling stuff */
872 return true;
873 }
874
875 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
876 if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
877 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
878 /* Make sure that anybody stopping the queue after this
879 * sees the new next_to_clean.
880 */
881 smp_mb();
882 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
883 !test_bit(__IXGBE_DOWN, &adapter->state)) {
884 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
885 ++tx_ring->tx_stats.restart_queue;
886 }
887 }
888
889 return count < q_vector->tx.work_limit;
890 }
891
892 #ifdef CONFIG_IXGBE_DCA
893 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
894 struct ixgbe_ring *rx_ring,
895 int cpu)
896 {
897 struct ixgbe_hw *hw = &adapter->hw;
898 u32 rxctrl;
899 u8 reg_idx = rx_ring->reg_idx;
900
901 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
902 switch (hw->mac.type) {
903 case ixgbe_mac_82598EB:
904 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
905 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
906 break;
907 case ixgbe_mac_82599EB:
908 case ixgbe_mac_X540:
909 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
910 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
911 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
912 break;
913 default:
914 break;
915 }
916 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
917 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
918 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
919 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
920 }
921
922 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
923 struct ixgbe_ring *tx_ring,
924 int cpu)
925 {
926 struct ixgbe_hw *hw = &adapter->hw;
927 u32 txctrl;
928 u8 reg_idx = tx_ring->reg_idx;
929
930 switch (hw->mac.type) {
931 case ixgbe_mac_82598EB:
932 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
933 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
934 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
935 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
936 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
937 break;
938 case ixgbe_mac_82599EB:
939 case ixgbe_mac_X540:
940 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
941 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
942 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
943 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
944 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
945 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
946 break;
947 default:
948 break;
949 }
950 }
951
952 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
953 {
954 struct ixgbe_adapter *adapter = q_vector->adapter;
955 int cpu = get_cpu();
956 long r_idx;
957 int i;
958
959 if (q_vector->cpu == cpu)
960 goto out_no_update;
961
962 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
963 for (i = 0; i < q_vector->tx.count; i++) {
964 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
965 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
966 r_idx + 1);
967 }
968
969 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
970 for (i = 0; i < q_vector->rx.count; i++) {
971 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
972 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
973 r_idx + 1);
974 }
975
976 q_vector->cpu = cpu;
977 out_no_update:
978 put_cpu();
979 }
980
981 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
982 {
983 int num_q_vectors;
984 int i;
985
986 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
987 return;
988
989 /* always use CB2 mode, difference is masked in the CB driver */
990 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
991
992 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
993 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
994 else
995 num_q_vectors = 1;
996
997 for (i = 0; i < num_q_vectors; i++) {
998 adapter->q_vector[i]->cpu = -1;
999 ixgbe_update_dca(adapter->q_vector[i]);
1000 }
1001 }
1002
1003 static int __ixgbe_notify_dca(struct device *dev, void *data)
1004 {
1005 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1006 unsigned long event = *(unsigned long *)data;
1007
1008 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1009 return 0;
1010
1011 switch (event) {
1012 case DCA_PROVIDER_ADD:
1013 /* if we're already enabled, don't do it again */
1014 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1015 break;
1016 if (dca_add_requester(dev) == 0) {
1017 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1018 ixgbe_setup_dca(adapter);
1019 break;
1020 }
1021 /* Fall Through since DCA is disabled. */
1022 case DCA_PROVIDER_REMOVE:
1023 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1024 dca_remove_requester(dev);
1025 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1026 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1027 }
1028 break;
1029 }
1030
1031 return 0;
1032 }
1033 #endif /* CONFIG_IXGBE_DCA */
1034
1035 static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
1036 struct sk_buff *skb)
1037 {
1038 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1039 }
1040
1041 /**
1042 * ixgbe_receive_skb - Send a completed packet up the stack
1043 * @adapter: board private structure
1044 * @skb: packet to send up
1045 * @status: hardware indication of status of receive
1046 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1047 * @rx_desc: rx descriptor
1048 **/
1049 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1050 struct sk_buff *skb, u8 status,
1051 struct ixgbe_ring *ring,
1052 union ixgbe_adv_rx_desc *rx_desc)
1053 {
1054 struct ixgbe_adapter *adapter = q_vector->adapter;
1055 struct napi_struct *napi = &q_vector->napi;
1056 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1057 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1058
1059 if (is_vlan && (tag & VLAN_VID_MASK))
1060 __vlan_hwaccel_put_tag(skb, tag);
1061
1062 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1063 napi_gro_receive(napi, skb);
1064 else
1065 netif_rx(skb);
1066 }
1067
1068 /**
1069 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1070 * @adapter: address of board private structure
1071 * @status_err: hardware indication of status of receive
1072 * @skb: skb currently being received and modified
1073 **/
1074 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1075 union ixgbe_adv_rx_desc *rx_desc,
1076 struct sk_buff *skb)
1077 {
1078 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
1079
1080 skb_checksum_none_assert(skb);
1081
1082 /* Rx csum disabled */
1083 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1084 return;
1085
1086 /* if IP and error */
1087 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1088 (status_err & IXGBE_RXDADV_ERR_IPE)) {
1089 adapter->hw_csum_rx_error++;
1090 return;
1091 }
1092
1093 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1094 return;
1095
1096 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1097 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1098
1099 /*
1100 * 82599 errata, UDP frames with a 0 checksum can be marked as
1101 * checksum errors.
1102 */
1103 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1104 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1105 return;
1106
1107 adapter->hw_csum_rx_error++;
1108 return;
1109 }
1110
1111 /* It must be a TCP or UDP packet with a valid checksum */
1112 skb->ip_summed = CHECKSUM_UNNECESSARY;
1113 }
1114
1115 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1116 {
1117 /*
1118 * Force memory writes to complete before letting h/w
1119 * know there are new descriptors to fetch. (Only
1120 * applicable for weak-ordered memory model archs,
1121 * such as IA-64).
1122 */
1123 wmb();
1124 writel(val, rx_ring->tail);
1125 }
1126
1127 /**
1128 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1129 * @rx_ring: ring to place buffers on
1130 * @cleaned_count: number of buffers to replace
1131 **/
1132 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1133 {
1134 union ixgbe_adv_rx_desc *rx_desc;
1135 struct ixgbe_rx_buffer *bi;
1136 struct sk_buff *skb;
1137 u16 i = rx_ring->next_to_use;
1138
1139 /* do nothing if no valid netdev defined */
1140 if (!rx_ring->netdev)
1141 return;
1142
1143 while (cleaned_count--) {
1144 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1145 bi = &rx_ring->rx_buffer_info[i];
1146 skb = bi->skb;
1147
1148 if (!skb) {
1149 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1150 rx_ring->rx_buf_len);
1151 if (!skb) {
1152 rx_ring->rx_stats.alloc_rx_buff_failed++;
1153 goto no_buffers;
1154 }
1155 /* initialize queue mapping */
1156 skb_record_rx_queue(skb, rx_ring->queue_index);
1157 bi->skb = skb;
1158 }
1159
1160 if (!bi->dma) {
1161 bi->dma = dma_map_single(rx_ring->dev,
1162 skb->data,
1163 rx_ring->rx_buf_len,
1164 DMA_FROM_DEVICE);
1165 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1166 rx_ring->rx_stats.alloc_rx_buff_failed++;
1167 bi->dma = 0;
1168 goto no_buffers;
1169 }
1170 }
1171
1172 if (ring_is_ps_enabled(rx_ring)) {
1173 if (!bi->page) {
1174 bi->page = netdev_alloc_page(rx_ring->netdev);
1175 if (!bi->page) {
1176 rx_ring->rx_stats.alloc_rx_page_failed++;
1177 goto no_buffers;
1178 }
1179 }
1180
1181 if (!bi->page_dma) {
1182 /* use a half page if we're re-using */
1183 bi->page_offset ^= PAGE_SIZE / 2;
1184 bi->page_dma = dma_map_page(rx_ring->dev,
1185 bi->page,
1186 bi->page_offset,
1187 PAGE_SIZE / 2,
1188 DMA_FROM_DEVICE);
1189 if (dma_mapping_error(rx_ring->dev,
1190 bi->page_dma)) {
1191 rx_ring->rx_stats.alloc_rx_page_failed++;
1192 bi->page_dma = 0;
1193 goto no_buffers;
1194 }
1195 }
1196
1197 /* Refresh the desc even if buffer_addrs didn't change
1198 * because each write-back erases this info. */
1199 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1200 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1201 } else {
1202 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1203 rx_desc->read.hdr_addr = 0;
1204 }
1205
1206 i++;
1207 if (i == rx_ring->count)
1208 i = 0;
1209 }
1210
1211 no_buffers:
1212 if (rx_ring->next_to_use != i) {
1213 rx_ring->next_to_use = i;
1214 ixgbe_release_rx_desc(rx_ring, i);
1215 }
1216 }
1217
1218 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1219 {
1220 /* HW will not DMA in data larger than the given buffer, even if it
1221 * parses the (NFS, of course) header to be larger. In that case, it
1222 * fills the header buffer and spills the rest into the page.
1223 */
1224 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1225 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1226 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1227 if (hlen > IXGBE_RX_HDR_SIZE)
1228 hlen = IXGBE_RX_HDR_SIZE;
1229 return hlen;
1230 }
1231
1232 /**
1233 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1234 * @skb: pointer to the last skb in the rsc queue
1235 *
1236 * This function changes a queue full of hw rsc buffers into a completed
1237 * packet. It uses the ->prev pointers to find the first packet and then
1238 * turns it into the frag list owner.
1239 **/
1240 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1241 {
1242 unsigned int frag_list_size = 0;
1243 unsigned int skb_cnt = 1;
1244
1245 while (skb->prev) {
1246 struct sk_buff *prev = skb->prev;
1247 frag_list_size += skb->len;
1248 skb->prev = NULL;
1249 skb = prev;
1250 skb_cnt++;
1251 }
1252
1253 skb_shinfo(skb)->frag_list = skb->next;
1254 skb->next = NULL;
1255 skb->len += frag_list_size;
1256 skb->data_len += frag_list_size;
1257 skb->truesize += frag_list_size;
1258 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1259
1260 return skb;
1261 }
1262
1263 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1264 {
1265 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1266 IXGBE_RXDADV_RSCCNT_MASK);
1267 }
1268
1269 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1270 struct ixgbe_ring *rx_ring,
1271 int *work_done, int work_to_do)
1272 {
1273 struct ixgbe_adapter *adapter = q_vector->adapter;
1274 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1275 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1276 struct sk_buff *skb;
1277 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1278 const int current_node = numa_node_id();
1279 #ifdef IXGBE_FCOE
1280 int ddp_bytes = 0;
1281 #endif /* IXGBE_FCOE */
1282 u32 staterr;
1283 u16 i;
1284 u16 cleaned_count = 0;
1285 bool pkt_is_rsc = false;
1286
1287 i = rx_ring->next_to_clean;
1288 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1289 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1290
1291 while (staterr & IXGBE_RXD_STAT_DD) {
1292 u32 upper_len = 0;
1293
1294 rmb(); /* read descriptor and rx_buffer_info after status DD */
1295
1296 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1297
1298 skb = rx_buffer_info->skb;
1299 rx_buffer_info->skb = NULL;
1300 prefetch(skb->data);
1301
1302 if (ring_is_rsc_enabled(rx_ring))
1303 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1304
1305 /* if this is a skb from previous receive DMA will be 0 */
1306 if (rx_buffer_info->dma) {
1307 u16 hlen;
1308 if (pkt_is_rsc &&
1309 !(staterr & IXGBE_RXD_STAT_EOP) &&
1310 !skb->prev) {
1311 /*
1312 * When HWRSC is enabled, delay unmapping
1313 * of the first packet. It carries the
1314 * header information, HW may still
1315 * access the header after the writeback.
1316 * Only unmap it when EOP is reached
1317 */
1318 IXGBE_RSC_CB(skb)->delay_unmap = true;
1319 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1320 } else {
1321 dma_unmap_single(rx_ring->dev,
1322 rx_buffer_info->dma,
1323 rx_ring->rx_buf_len,
1324 DMA_FROM_DEVICE);
1325 }
1326 rx_buffer_info->dma = 0;
1327
1328 if (ring_is_ps_enabled(rx_ring)) {
1329 hlen = ixgbe_get_hlen(rx_desc);
1330 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1331 } else {
1332 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1333 }
1334
1335 skb_put(skb, hlen);
1336 } else {
1337 /* assume packet split since header is unmapped */
1338 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1339 }
1340
1341 if (upper_len) {
1342 dma_unmap_page(rx_ring->dev,
1343 rx_buffer_info->page_dma,
1344 PAGE_SIZE / 2,
1345 DMA_FROM_DEVICE);
1346 rx_buffer_info->page_dma = 0;
1347 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1348 rx_buffer_info->page,
1349 rx_buffer_info->page_offset,
1350 upper_len);
1351
1352 if ((page_count(rx_buffer_info->page) == 1) &&
1353 (page_to_nid(rx_buffer_info->page) == current_node))
1354 get_page(rx_buffer_info->page);
1355 else
1356 rx_buffer_info->page = NULL;
1357
1358 skb->len += upper_len;
1359 skb->data_len += upper_len;
1360 skb->truesize += upper_len;
1361 }
1362
1363 i++;
1364 if (i == rx_ring->count)
1365 i = 0;
1366
1367 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1368 prefetch(next_rxd);
1369 cleaned_count++;
1370
1371 if (pkt_is_rsc) {
1372 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1373 IXGBE_RXDADV_NEXTP_SHIFT;
1374 next_buffer = &rx_ring->rx_buffer_info[nextp];
1375 } else {
1376 next_buffer = &rx_ring->rx_buffer_info[i];
1377 }
1378
1379 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1380 if (ring_is_ps_enabled(rx_ring)) {
1381 rx_buffer_info->skb = next_buffer->skb;
1382 rx_buffer_info->dma = next_buffer->dma;
1383 next_buffer->skb = skb;
1384 next_buffer->dma = 0;
1385 } else {
1386 skb->next = next_buffer->skb;
1387 skb->next->prev = skb;
1388 }
1389 rx_ring->rx_stats.non_eop_descs++;
1390 goto next_desc;
1391 }
1392
1393 if (skb->prev) {
1394 skb = ixgbe_transform_rsc_queue(skb);
1395 /* if we got here without RSC the packet is invalid */
1396 if (!pkt_is_rsc) {
1397 __pskb_trim(skb, 0);
1398 rx_buffer_info->skb = skb;
1399 goto next_desc;
1400 }
1401 }
1402
1403 if (ring_is_rsc_enabled(rx_ring)) {
1404 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1405 dma_unmap_single(rx_ring->dev,
1406 IXGBE_RSC_CB(skb)->dma,
1407 rx_ring->rx_buf_len,
1408 DMA_FROM_DEVICE);
1409 IXGBE_RSC_CB(skb)->dma = 0;
1410 IXGBE_RSC_CB(skb)->delay_unmap = false;
1411 }
1412 }
1413 if (pkt_is_rsc) {
1414 if (ring_is_ps_enabled(rx_ring))
1415 rx_ring->rx_stats.rsc_count +=
1416 skb_shinfo(skb)->nr_frags;
1417 else
1418 rx_ring->rx_stats.rsc_count +=
1419 IXGBE_RSC_CB(skb)->skb_cnt;
1420 rx_ring->rx_stats.rsc_flush++;
1421 }
1422
1423 /* ERR_MASK will only have valid bits if EOP set */
1424 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1425 /* trim packet back to size 0 and recycle it */
1426 __pskb_trim(skb, 0);
1427 rx_buffer_info->skb = skb;
1428 goto next_desc;
1429 }
1430
1431 ixgbe_rx_checksum(adapter, rx_desc, skb);
1432 if (adapter->netdev->features & NETIF_F_RXHASH)
1433 ixgbe_rx_hash(rx_desc, skb);
1434
1435 /* probably a little skewed due to removing CRC */
1436 total_rx_bytes += skb->len;
1437 total_rx_packets++;
1438
1439 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1440 #ifdef IXGBE_FCOE
1441 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1442 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1443 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1444 if (!ddp_bytes)
1445 goto next_desc;
1446 }
1447 #endif /* IXGBE_FCOE */
1448 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1449
1450 next_desc:
1451 rx_desc->wb.upper.status_error = 0;
1452
1453 (*work_done)++;
1454 if (*work_done >= work_to_do)
1455 break;
1456
1457 /* return some buffers to hardware, one at a time is too slow */
1458 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1459 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1460 cleaned_count = 0;
1461 }
1462
1463 /* use prefetched values */
1464 rx_desc = next_rxd;
1465 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1466 }
1467
1468 rx_ring->next_to_clean = i;
1469 cleaned_count = ixgbe_desc_unused(rx_ring);
1470
1471 if (cleaned_count)
1472 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1473
1474 #ifdef IXGBE_FCOE
1475 /* include DDPed FCoE data */
1476 if (ddp_bytes > 0) {
1477 unsigned int mss;
1478
1479 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1480 sizeof(struct fc_frame_header) -
1481 sizeof(struct fcoe_crc_eof);
1482 if (mss > 512)
1483 mss &= ~511;
1484 total_rx_bytes += ddp_bytes;
1485 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1486 }
1487 #endif /* IXGBE_FCOE */
1488
1489 u64_stats_update_begin(&rx_ring->syncp);
1490 rx_ring->stats.packets += total_rx_packets;
1491 rx_ring->stats.bytes += total_rx_bytes;
1492 u64_stats_update_end(&rx_ring->syncp);
1493 q_vector->rx.total_packets += total_rx_packets;
1494 q_vector->rx.total_bytes += total_rx_bytes;
1495 }
1496
1497 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1498 /**
1499 * ixgbe_configure_msix - Configure MSI-X hardware
1500 * @adapter: board private structure
1501 *
1502 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1503 * interrupts.
1504 **/
1505 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1506 {
1507 struct ixgbe_q_vector *q_vector;
1508 int i, q_vectors, v_idx, r_idx;
1509 u32 mask;
1510
1511 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1512
1513 /*
1514 * Populate the IVAR table and set the ITR values to the
1515 * corresponding register.
1516 */
1517 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1518 q_vector = adapter->q_vector[v_idx];
1519 /* XXX for_each_set_bit(...) */
1520 r_idx = find_first_bit(q_vector->rx.idx,
1521 adapter->num_rx_queues);
1522
1523 for (i = 0; i < q_vector->rx.count; i++) {
1524 u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1525 ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
1526 r_idx = find_next_bit(q_vector->rx.idx,
1527 adapter->num_rx_queues,
1528 r_idx + 1);
1529 }
1530 r_idx = find_first_bit(q_vector->tx.idx,
1531 adapter->num_tx_queues);
1532
1533 for (i = 0; i < q_vector->tx.count; i++) {
1534 u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1535 ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
1536 r_idx = find_next_bit(q_vector->tx.idx,
1537 adapter->num_tx_queues,
1538 r_idx + 1);
1539 }
1540
1541 if (q_vector->tx.count && !q_vector->rx.count)
1542 /* tx only */
1543 q_vector->eitr = adapter->tx_eitr_param;
1544 else if (q_vector->rx.count)
1545 /* rx or mixed */
1546 q_vector->eitr = adapter->rx_eitr_param;
1547
1548 ixgbe_write_eitr(q_vector);
1549 /* If ATR is enabled, set interrupt affinity */
1550 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
1551 /*
1552 * Allocate the affinity_hint cpumask, assign the mask
1553 * for this vector, and set our affinity_hint for
1554 * this irq.
1555 */
1556 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1557 GFP_KERNEL))
1558 return;
1559 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1560 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1561 q_vector->affinity_mask);
1562 }
1563 }
1564
1565 switch (adapter->hw.mac.type) {
1566 case ixgbe_mac_82598EB:
1567 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1568 v_idx);
1569 break;
1570 case ixgbe_mac_82599EB:
1571 case ixgbe_mac_X540:
1572 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1573 break;
1574
1575 default:
1576 break;
1577 }
1578 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1579
1580 /* set up to autoclear timer, and the vectors */
1581 mask = IXGBE_EIMS_ENABLE_MASK;
1582 if (adapter->num_vfs)
1583 mask &= ~(IXGBE_EIMS_OTHER |
1584 IXGBE_EIMS_MAILBOX |
1585 IXGBE_EIMS_LSC);
1586 else
1587 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1588 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1589 }
1590
1591 enum latency_range {
1592 lowest_latency = 0,
1593 low_latency = 1,
1594 bulk_latency = 2,
1595 latency_invalid = 255
1596 };
1597
1598 /**
1599 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1600 * @q_vector: structure containing interrupt and ring information
1601 * @ring_container: structure containing ring performance data
1602 *
1603 * Stores a new ITR value based on packets and byte
1604 * counts during the last interrupt. The advantage of per interrupt
1605 * computation is faster updates and more accurate ITR for the current
1606 * traffic pattern. Constants in this function were computed
1607 * based on theoretical maximum wire speed and thresholds were set based
1608 * on testing data as well as attempting to minimize response time
1609 * while increasing bulk throughput.
1610 * this functionality is controlled by the InterruptThrottleRate module
1611 * parameter (see ixgbe_param.c)
1612 **/
1613 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1614 struct ixgbe_ring_container *ring_container)
1615 {
1616 u64 bytes_perint;
1617 struct ixgbe_adapter *adapter = q_vector->adapter;
1618 int bytes = ring_container->total_bytes;
1619 int packets = ring_container->total_packets;
1620 u32 timepassed_us;
1621 u8 itr_setting = ring_container->itr;
1622
1623 if (packets == 0)
1624 return;
1625
1626 /* simple throttlerate management
1627 * 0-20MB/s lowest (100000 ints/s)
1628 * 20-100MB/s low (20000 ints/s)
1629 * 100-1249MB/s bulk (8000 ints/s)
1630 */
1631 /* what was last interrupt timeslice? */
1632 timepassed_us = 1000000/q_vector->eitr;
1633 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1634
1635 switch (itr_setting) {
1636 case lowest_latency:
1637 if (bytes_perint > adapter->eitr_low)
1638 itr_setting = low_latency;
1639 break;
1640 case low_latency:
1641 if (bytes_perint > adapter->eitr_high)
1642 itr_setting = bulk_latency;
1643 else if (bytes_perint <= adapter->eitr_low)
1644 itr_setting = lowest_latency;
1645 break;
1646 case bulk_latency:
1647 if (bytes_perint <= adapter->eitr_high)
1648 itr_setting = low_latency;
1649 break;
1650 }
1651
1652 /* clear work counters since we have the values we need */
1653 ring_container->total_bytes = 0;
1654 ring_container->total_packets = 0;
1655
1656 /* write updated itr to ring container */
1657 ring_container->itr = itr_setting;
1658 }
1659
1660 /**
1661 * ixgbe_write_eitr - write EITR register in hardware specific way
1662 * @q_vector: structure containing interrupt and ring information
1663 *
1664 * This function is made to be called by ethtool and by the driver
1665 * when it needs to update EITR registers at runtime. Hardware
1666 * specific quirks/differences are taken care of here.
1667 */
1668 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1669 {
1670 struct ixgbe_adapter *adapter = q_vector->adapter;
1671 struct ixgbe_hw *hw = &adapter->hw;
1672 int v_idx = q_vector->v_idx;
1673 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1674
1675 switch (adapter->hw.mac.type) {
1676 case ixgbe_mac_82598EB:
1677 /* must write high and low 16 bits to reset counter */
1678 itr_reg |= (itr_reg << 16);
1679 break;
1680 case ixgbe_mac_82599EB:
1681 case ixgbe_mac_X540:
1682 /*
1683 * 82599 and X540 can support a value of zero, so allow it for
1684 * max interrupt rate, but there is an errata where it can
1685 * not be zero with RSC
1686 */
1687 if (itr_reg == 8 &&
1688 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1689 itr_reg = 0;
1690
1691 /*
1692 * set the WDIS bit to not clear the timer bits and cause an
1693 * immediate assertion of the interrupt
1694 */
1695 itr_reg |= IXGBE_EITR_CNT_WDIS;
1696 break;
1697 default:
1698 break;
1699 }
1700 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1701 }
1702
1703 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
1704 {
1705 u32 new_itr = q_vector->eitr;
1706 u8 current_itr;
1707
1708 ixgbe_update_itr(q_vector, &q_vector->tx);
1709 ixgbe_update_itr(q_vector, &q_vector->rx);
1710
1711 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
1712
1713 switch (current_itr) {
1714 /* counts and packets in update_itr are dependent on these numbers */
1715 case lowest_latency:
1716 new_itr = 100000;
1717 break;
1718 case low_latency:
1719 new_itr = 20000; /* aka hwitr = ~200 */
1720 break;
1721 case bulk_latency:
1722 new_itr = 8000;
1723 break;
1724 default:
1725 break;
1726 }
1727
1728 if (new_itr != q_vector->eitr) {
1729 /* do an exponential smoothing */
1730 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1731
1732 /* save the algorithm value here */
1733 q_vector->eitr = new_itr;
1734
1735 ixgbe_write_eitr(q_vector);
1736 }
1737 }
1738
1739 /**
1740 * ixgbe_check_overtemp_subtask - check for over tempurature
1741 * @adapter: pointer to adapter
1742 **/
1743 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
1744 {
1745 struct ixgbe_hw *hw = &adapter->hw;
1746 u32 eicr = adapter->interrupt_event;
1747
1748 if (test_bit(__IXGBE_DOWN, &adapter->state))
1749 return;
1750
1751 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1752 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1753 return;
1754
1755 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1756
1757 switch (hw->device_id) {
1758 case IXGBE_DEV_ID_82599_T3_LOM:
1759 /*
1760 * Since the warning interrupt is for both ports
1761 * we don't have to check if:
1762 * - This interrupt wasn't for our port.
1763 * - We may have missed the interrupt so always have to
1764 * check if we got a LSC
1765 */
1766 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1767 !(eicr & IXGBE_EICR_LSC))
1768 return;
1769
1770 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1771 u32 autoneg;
1772 bool link_up = false;
1773
1774 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1775
1776 if (link_up)
1777 return;
1778 }
1779
1780 /* Check if this is not due to overtemp */
1781 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1782 return;
1783
1784 break;
1785 default:
1786 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1787 return;
1788 break;
1789 }
1790 e_crit(drv,
1791 "Network adapter has been stopped because it has over heated. "
1792 "Restart the computer. If the problem persists, "
1793 "power off the system and replace the adapter\n");
1794
1795 adapter->interrupt_event = 0;
1796 }
1797
1798 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1799 {
1800 struct ixgbe_hw *hw = &adapter->hw;
1801
1802 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1803 (eicr & IXGBE_EICR_GPI_SDP1)) {
1804 e_crit(probe, "Fan has stopped, replace the adapter\n");
1805 /* write to clear the interrupt */
1806 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1807 }
1808 }
1809
1810 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1811 {
1812 struct ixgbe_hw *hw = &adapter->hw;
1813
1814 if (eicr & IXGBE_EICR_GPI_SDP2) {
1815 /* Clear the interrupt */
1816 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1817 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1818 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1819 ixgbe_service_event_schedule(adapter);
1820 }
1821 }
1822
1823 if (eicr & IXGBE_EICR_GPI_SDP1) {
1824 /* Clear the interrupt */
1825 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1826 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1827 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1828 ixgbe_service_event_schedule(adapter);
1829 }
1830 }
1831 }
1832
1833 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1834 {
1835 struct ixgbe_hw *hw = &adapter->hw;
1836
1837 adapter->lsc_int++;
1838 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1839 adapter->link_check_timeout = jiffies;
1840 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1841 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1842 IXGBE_WRITE_FLUSH(hw);
1843 ixgbe_service_event_schedule(adapter);
1844 }
1845 }
1846
1847 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1848 {
1849 struct ixgbe_adapter *adapter = data;
1850 struct ixgbe_hw *hw = &adapter->hw;
1851 u32 eicr;
1852
1853 /*
1854 * Workaround for Silicon errata. Use clear-by-write instead
1855 * of clear-by-read. Reading with EICS will return the
1856 * interrupt causes without clearing, which later be done
1857 * with the write to EICR.
1858 */
1859 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1860 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1861
1862 if (eicr & IXGBE_EICR_LSC)
1863 ixgbe_check_lsc(adapter);
1864
1865 if (eicr & IXGBE_EICR_MAILBOX)
1866 ixgbe_msg_task(adapter);
1867
1868 switch (hw->mac.type) {
1869 case ixgbe_mac_82599EB:
1870 case ixgbe_mac_X540:
1871 /* Handle Flow Director Full threshold interrupt */
1872 if (eicr & IXGBE_EICR_FLOW_DIR) {
1873 int reinit_count = 0;
1874 int i;
1875 for (i = 0; i < adapter->num_tx_queues; i++) {
1876 struct ixgbe_ring *ring = adapter->tx_ring[i];
1877 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1878 &ring->state))
1879 reinit_count++;
1880 }
1881 if (reinit_count) {
1882 /* no more flow director interrupts until after init */
1883 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1884 eicr &= ~IXGBE_EICR_FLOW_DIR;
1885 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1886 ixgbe_service_event_schedule(adapter);
1887 }
1888 }
1889 ixgbe_check_sfp_event(adapter, eicr);
1890 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1891 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1892 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1893 adapter->interrupt_event = eicr;
1894 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1895 ixgbe_service_event_schedule(adapter);
1896 }
1897 }
1898 break;
1899 default:
1900 break;
1901 }
1902
1903 ixgbe_check_fan_failure(adapter, eicr);
1904
1905 /* re-enable the original interrupt state, no lsc, no queues */
1906 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1907 IXGBE_WRITE_REG(hw, IXGBE_EIMS, eicr &
1908 ~(IXGBE_EIMS_LSC | IXGBE_EIMS_RTX_QUEUE));
1909
1910 return IRQ_HANDLED;
1911 }
1912
1913 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1914 u64 qmask)
1915 {
1916 u32 mask;
1917 struct ixgbe_hw *hw = &adapter->hw;
1918
1919 switch (hw->mac.type) {
1920 case ixgbe_mac_82598EB:
1921 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1922 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1923 break;
1924 case ixgbe_mac_82599EB:
1925 case ixgbe_mac_X540:
1926 mask = (qmask & 0xFFFFFFFF);
1927 if (mask)
1928 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1929 mask = (qmask >> 32);
1930 if (mask)
1931 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1932 break;
1933 default:
1934 break;
1935 }
1936 /* skip the flush */
1937 }
1938
1939 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1940 u64 qmask)
1941 {
1942 u32 mask;
1943 struct ixgbe_hw *hw = &adapter->hw;
1944
1945 switch (hw->mac.type) {
1946 case ixgbe_mac_82598EB:
1947 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1948 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1949 break;
1950 case ixgbe_mac_82599EB:
1951 case ixgbe_mac_X540:
1952 mask = (qmask & 0xFFFFFFFF);
1953 if (mask)
1954 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1955 mask = (qmask >> 32);
1956 if (mask)
1957 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1958 break;
1959 default:
1960 break;
1961 }
1962 /* skip the flush */
1963 }
1964
1965 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1966 {
1967 struct ixgbe_q_vector *q_vector = data;
1968 struct ixgbe_adapter *adapter = q_vector->adapter;
1969 struct ixgbe_ring *tx_ring;
1970 int i, r_idx;
1971
1972 if (!q_vector->tx.count)
1973 return IRQ_HANDLED;
1974
1975 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
1976 for (i = 0; i < q_vector->tx.count; i++) {
1977 tx_ring = adapter->tx_ring[r_idx];
1978 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
1979 r_idx + 1);
1980 }
1981
1982 /* EIAM disabled interrupts (on this vector) for us */
1983 napi_schedule(&q_vector->napi);
1984
1985 return IRQ_HANDLED;
1986 }
1987
1988 /**
1989 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1990 * @irq: unused
1991 * @data: pointer to our q_vector struct for this interrupt vector
1992 **/
1993 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1994 {
1995 struct ixgbe_q_vector *q_vector = data;
1996 struct ixgbe_adapter *adapter = q_vector->adapter;
1997 struct ixgbe_ring *rx_ring;
1998 int r_idx;
1999 int i;
2000
2001 #ifdef CONFIG_IXGBE_DCA
2002 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2003 ixgbe_update_dca(q_vector);
2004 #endif
2005
2006 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2007 for (i = 0; i < q_vector->rx.count; i++) {
2008 rx_ring = adapter->rx_ring[r_idx];
2009 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
2010 r_idx + 1);
2011 }
2012
2013 if (!q_vector->rx.count)
2014 return IRQ_HANDLED;
2015
2016 /* EIAM disabled interrupts (on this vector) for us */
2017 napi_schedule(&q_vector->napi);
2018
2019 return IRQ_HANDLED;
2020 }
2021
2022 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2023 {
2024 struct ixgbe_q_vector *q_vector = data;
2025 struct ixgbe_adapter *adapter = q_vector->adapter;
2026 struct ixgbe_ring *ring;
2027 int r_idx;
2028 int i;
2029
2030 if (!q_vector->tx.count && !q_vector->rx.count)
2031 return IRQ_HANDLED;
2032
2033 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2034 for (i = 0; i < q_vector->tx.count; i++) {
2035 ring = adapter->tx_ring[r_idx];
2036 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
2037 r_idx + 1);
2038 }
2039
2040 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2041 for (i = 0; i < q_vector->rx.count; i++) {
2042 ring = adapter->rx_ring[r_idx];
2043 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
2044 r_idx + 1);
2045 }
2046
2047 /* EIAM disabled interrupts (on this vector) for us */
2048 napi_schedule(&q_vector->napi);
2049
2050 return IRQ_HANDLED;
2051 }
2052
2053 /**
2054 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2055 * @napi: napi struct with our devices info in it
2056 * @budget: amount of work driver is allowed to do this pass, in packets
2057 *
2058 * This function is optimized for cleaning one queue only on a single
2059 * q_vector!!!
2060 **/
2061 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2062 {
2063 struct ixgbe_q_vector *q_vector =
2064 container_of(napi, struct ixgbe_q_vector, napi);
2065 struct ixgbe_adapter *adapter = q_vector->adapter;
2066 struct ixgbe_ring *rx_ring = NULL;
2067 int work_done = 0;
2068 long r_idx;
2069
2070 #ifdef CONFIG_IXGBE_DCA
2071 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2072 ixgbe_update_dca(q_vector);
2073 #endif
2074
2075 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2076 rx_ring = adapter->rx_ring[r_idx];
2077
2078 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
2079
2080 /* If all Rx work done, exit the polling mode */
2081 if (work_done < budget) {
2082 napi_complete(napi);
2083 if (adapter->rx_itr_setting & 1)
2084 ixgbe_set_itr(q_vector);
2085 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2086 ixgbe_irq_enable_queues(adapter,
2087 ((u64)1 << q_vector->v_idx));
2088 }
2089
2090 return work_done;
2091 }
2092
2093 /**
2094 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2095 * @napi: napi struct with our devices info in it
2096 * @budget: amount of work driver is allowed to do this pass, in packets
2097 *
2098 * This function will clean more than one rx queue associated with a
2099 * q_vector.
2100 **/
2101 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
2102 {
2103 struct ixgbe_q_vector *q_vector =
2104 container_of(napi, struct ixgbe_q_vector, napi);
2105 struct ixgbe_adapter *adapter = q_vector->adapter;
2106 struct ixgbe_ring *ring = NULL;
2107 int work_done = 0, i;
2108 long r_idx;
2109 bool tx_clean_complete = true;
2110
2111 #ifdef CONFIG_IXGBE_DCA
2112 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2113 ixgbe_update_dca(q_vector);
2114 #endif
2115
2116 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2117 for (i = 0; i < q_vector->tx.count; i++) {
2118 ring = adapter->tx_ring[r_idx];
2119 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2120 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
2121 r_idx + 1);
2122 }
2123
2124 /* attempt to distribute budget to each queue fairly, but don't allow
2125 * the budget to go below 1 because we'll exit polling */
2126 budget /= (q_vector->rx.count ?: 1);
2127 budget = max(budget, 1);
2128 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2129 for (i = 0; i < q_vector->rx.count; i++) {
2130 ring = adapter->rx_ring[r_idx];
2131 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2132 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
2133 r_idx + 1);
2134 }
2135
2136 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2137 ring = adapter->rx_ring[r_idx];
2138 /* If all Rx work done, exit the polling mode */
2139 if (work_done < budget) {
2140 napi_complete(napi);
2141 if (adapter->rx_itr_setting & 1)
2142 ixgbe_set_itr(q_vector);
2143 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2144 ixgbe_irq_enable_queues(adapter,
2145 ((u64)1 << q_vector->v_idx));
2146 return 0;
2147 }
2148
2149 return work_done;
2150 }
2151
2152 /**
2153 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2154 * @napi: napi struct with our devices info in it
2155 * @budget: amount of work driver is allowed to do this pass, in packets
2156 *
2157 * This function is optimized for cleaning one queue only on a single
2158 * q_vector!!!
2159 **/
2160 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2161 {
2162 struct ixgbe_q_vector *q_vector =
2163 container_of(napi, struct ixgbe_q_vector, napi);
2164 struct ixgbe_adapter *adapter = q_vector->adapter;
2165 struct ixgbe_ring *tx_ring = NULL;
2166 int work_done = 0;
2167 long r_idx;
2168
2169 #ifdef CONFIG_IXGBE_DCA
2170 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2171 ixgbe_update_dca(q_vector);
2172 #endif
2173
2174 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2175 tx_ring = adapter->tx_ring[r_idx];
2176
2177 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2178 work_done = budget;
2179
2180 /* If all Tx work done, exit the polling mode */
2181 if (work_done < budget) {
2182 napi_complete(napi);
2183 if (adapter->tx_itr_setting & 1)
2184 ixgbe_set_itr(q_vector);
2185 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2186 ixgbe_irq_enable_queues(adapter,
2187 ((u64)1 << q_vector->v_idx));
2188 }
2189
2190 return work_done;
2191 }
2192
2193 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2194 int r_idx)
2195 {
2196 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2197 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2198
2199 set_bit(r_idx, q_vector->rx.idx);
2200 q_vector->rx.count++;
2201 rx_ring->q_vector = q_vector;
2202 }
2203
2204 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2205 int t_idx)
2206 {
2207 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2208 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2209
2210 set_bit(t_idx, q_vector->tx.idx);
2211 q_vector->tx.count++;
2212 tx_ring->q_vector = q_vector;
2213 q_vector->tx.work_limit = a->tx_work_limit;
2214 }
2215
2216 /**
2217 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2218 * @adapter: board private structure to initialize
2219 *
2220 * This function maps descriptor rings to the queue-specific vectors
2221 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2222 * one vector per ring/queue, but on a constrained vector budget, we
2223 * group the rings as "efficiently" as possible. You would add new
2224 * mapping configurations in here.
2225 **/
2226 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2227 {
2228 int q_vectors;
2229 int v_start = 0;
2230 int rxr_idx = 0, txr_idx = 0;
2231 int rxr_remaining = adapter->num_rx_queues;
2232 int txr_remaining = adapter->num_tx_queues;
2233 int i, j;
2234 int rqpv, tqpv;
2235 int err = 0;
2236
2237 /* No mapping required if MSI-X is disabled. */
2238 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2239 goto out;
2240
2241 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2242
2243 /*
2244 * The ideal configuration...
2245 * We have enough vectors to map one per queue.
2246 */
2247 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2248 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2249 map_vector_to_rxq(adapter, v_start, rxr_idx);
2250
2251 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2252 map_vector_to_txq(adapter, v_start, txr_idx);
2253
2254 goto out;
2255 }
2256
2257 /*
2258 * If we don't have enough vectors for a 1-to-1
2259 * mapping, we'll have to group them so there are
2260 * multiple queues per vector.
2261 */
2262 /* Re-adjusting *qpv takes care of the remainder. */
2263 for (i = v_start; i < q_vectors; i++) {
2264 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
2265 for (j = 0; j < rqpv; j++) {
2266 map_vector_to_rxq(adapter, i, rxr_idx);
2267 rxr_idx++;
2268 rxr_remaining--;
2269 }
2270 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
2271 for (j = 0; j < tqpv; j++) {
2272 map_vector_to_txq(adapter, i, txr_idx);
2273 txr_idx++;
2274 txr_remaining--;
2275 }
2276 }
2277 out:
2278 return err;
2279 }
2280
2281 /**
2282 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2283 * @adapter: board private structure
2284 *
2285 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2286 * interrupts from the kernel.
2287 **/
2288 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2289 {
2290 struct net_device *netdev = adapter->netdev;
2291 irqreturn_t (*handler)(int, void *);
2292 int i, vector, q_vectors, err;
2293 int ri = 0, ti = 0;
2294
2295 /* Decrement for Other and TCP Timer vectors */
2296 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2297
2298 err = ixgbe_map_rings_to_vectors(adapter);
2299 if (err)
2300 return err;
2301
2302 #define SET_HANDLER(_v) (((_v)->rx.count && (_v)->tx.count) \
2303 ? &ixgbe_msix_clean_many : \
2304 (_v)->rx.count ? &ixgbe_msix_clean_rx : \
2305 (_v)->tx.count ? &ixgbe_msix_clean_tx : \
2306 NULL)
2307 for (vector = 0; vector < q_vectors; vector++) {
2308 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2309 handler = SET_HANDLER(q_vector);
2310
2311 if (handler == &ixgbe_msix_clean_rx) {
2312 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2313 "%s-%s-%d", netdev->name, "rx", ri++);
2314 } else if (handler == &ixgbe_msix_clean_tx) {
2315 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2316 "%s-%s-%d", netdev->name, "tx", ti++);
2317 } else if (handler == &ixgbe_msix_clean_many) {
2318 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2319 "%s-%s-%d", netdev->name, "TxRx", ri++);
2320 ti++;
2321 } else {
2322 /* skip this unused q_vector */
2323 continue;
2324 }
2325 err = request_irq(adapter->msix_entries[vector].vector,
2326 handler, 0, q_vector->name,
2327 q_vector);
2328 if (err) {
2329 e_err(probe, "request_irq failed for MSIX interrupt "
2330 "Error: %d\n", err);
2331 goto free_queue_irqs;
2332 }
2333 }
2334
2335 sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
2336 err = request_irq(adapter->msix_entries[vector].vector,
2337 ixgbe_msix_lsc, 0, adapter->lsc_int_name, adapter);
2338 if (err) {
2339 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2340 goto free_queue_irqs;
2341 }
2342
2343 return 0;
2344
2345 free_queue_irqs:
2346 for (i = vector - 1; i >= 0; i--)
2347 free_irq(adapter->msix_entries[--vector].vector,
2348 adapter->q_vector[i]);
2349 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2350 pci_disable_msix(adapter->pdev);
2351 kfree(adapter->msix_entries);
2352 adapter->msix_entries = NULL;
2353 return err;
2354 }
2355
2356 /**
2357 * ixgbe_irq_enable - Enable default interrupt generation settings
2358 * @adapter: board private structure
2359 **/
2360 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2361 bool flush)
2362 {
2363 u32 mask;
2364
2365 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2366 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2367 mask |= IXGBE_EIMS_GPI_SDP0;
2368 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2369 mask |= IXGBE_EIMS_GPI_SDP1;
2370 switch (adapter->hw.mac.type) {
2371 case ixgbe_mac_82599EB:
2372 case ixgbe_mac_X540:
2373 mask |= IXGBE_EIMS_ECC;
2374 mask |= IXGBE_EIMS_GPI_SDP1;
2375 mask |= IXGBE_EIMS_GPI_SDP2;
2376 if (adapter->num_vfs)
2377 mask |= IXGBE_EIMS_MAILBOX;
2378 break;
2379 default:
2380 break;
2381 }
2382 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
2383 mask |= IXGBE_EIMS_FLOW_DIR;
2384
2385 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2386 if (queues)
2387 ixgbe_irq_enable_queues(adapter, ~0);
2388 if (flush)
2389 IXGBE_WRITE_FLUSH(&adapter->hw);
2390
2391 if (adapter->num_vfs > 32) {
2392 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2393 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2394 }
2395 }
2396
2397 /**
2398 * ixgbe_intr - legacy mode Interrupt Handler
2399 * @irq: interrupt number
2400 * @data: pointer to a network interface device structure
2401 **/
2402 static irqreturn_t ixgbe_intr(int irq, void *data)
2403 {
2404 struct ixgbe_adapter *adapter = data;
2405 struct ixgbe_hw *hw = &adapter->hw;
2406 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2407 u32 eicr;
2408
2409 /*
2410 * Workaround for silicon errata on 82598. Mask the interrupts
2411 * before the read of EICR.
2412 */
2413 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2414
2415 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2416 * therefore no explict interrupt disable is necessary */
2417 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2418 if (!eicr) {
2419 /*
2420 * shared interrupt alert!
2421 * make sure interrupts are enabled because the read will
2422 * have disabled interrupts due to EIAM
2423 * finish the workaround of silicon errata on 82598. Unmask
2424 * the interrupt that we masked before the EICR read.
2425 */
2426 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2427 ixgbe_irq_enable(adapter, true, true);
2428 return IRQ_NONE; /* Not our interrupt */
2429 }
2430
2431 if (eicr & IXGBE_EICR_LSC)
2432 ixgbe_check_lsc(adapter);
2433
2434 switch (hw->mac.type) {
2435 case ixgbe_mac_82599EB:
2436 ixgbe_check_sfp_event(adapter, eicr);
2437 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2438 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2439 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2440 adapter->interrupt_event = eicr;
2441 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2442 ixgbe_service_event_schedule(adapter);
2443 }
2444 }
2445 break;
2446 default:
2447 break;
2448 }
2449
2450 ixgbe_check_fan_failure(adapter, eicr);
2451
2452 if (napi_schedule_prep(&(q_vector->napi))) {
2453 /* would disable interrupts here but EIAM disabled it */
2454 __napi_schedule(&(q_vector->napi));
2455 }
2456
2457 /*
2458 * re-enable link(maybe) and non-queue interrupts, no flush.
2459 * ixgbe_poll will re-enable the queue interrupts
2460 */
2461
2462 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2463 ixgbe_irq_enable(adapter, false, false);
2464
2465 return IRQ_HANDLED;
2466 }
2467
2468 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2469 {
2470 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2471
2472 for (i = 0; i < q_vectors; i++) {
2473 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2474 bitmap_zero(q_vector->rx.idx, MAX_RX_QUEUES);
2475 bitmap_zero(q_vector->tx.idx, MAX_TX_QUEUES);
2476 q_vector->rx.count = 0;
2477 q_vector->tx.count = 0;
2478 }
2479 }
2480
2481 /**
2482 * ixgbe_request_irq - initialize interrupts
2483 * @adapter: board private structure
2484 *
2485 * Attempts to configure interrupts using the best available
2486 * capabilities of the hardware and kernel.
2487 **/
2488 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2489 {
2490 struct net_device *netdev = adapter->netdev;
2491 int err;
2492
2493 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2494 err = ixgbe_request_msix_irqs(adapter);
2495 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2496 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2497 netdev->name, adapter);
2498 } else {
2499 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2500 netdev->name, adapter);
2501 }
2502
2503 if (err)
2504 e_err(probe, "request_irq failed, Error %d\n", err);
2505
2506 return err;
2507 }
2508
2509 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2510 {
2511 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2512 int i, q_vectors;
2513
2514 q_vectors = adapter->num_msix_vectors;
2515
2516 i = q_vectors - 1;
2517 free_irq(adapter->msix_entries[i].vector, adapter);
2518
2519 i--;
2520 for (; i >= 0; i--) {
2521 /* free only the irqs that were actually requested */
2522 if (!adapter->q_vector[i]->rx.count &&
2523 !adapter->q_vector[i]->tx.count)
2524 continue;
2525
2526 free_irq(adapter->msix_entries[i].vector,
2527 adapter->q_vector[i]);
2528 }
2529
2530 ixgbe_reset_q_vectors(adapter);
2531 } else {
2532 free_irq(adapter->pdev->irq, adapter);
2533 }
2534 }
2535
2536 /**
2537 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2538 * @adapter: board private structure
2539 **/
2540 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2541 {
2542 switch (adapter->hw.mac.type) {
2543 case ixgbe_mac_82598EB:
2544 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2545 break;
2546 case ixgbe_mac_82599EB:
2547 case ixgbe_mac_X540:
2548 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2549 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2550 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2551 if (adapter->num_vfs > 32)
2552 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2553 break;
2554 default:
2555 break;
2556 }
2557 IXGBE_WRITE_FLUSH(&adapter->hw);
2558 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2559 int i;
2560 for (i = 0; i < adapter->num_msix_vectors; i++)
2561 synchronize_irq(adapter->msix_entries[i].vector);
2562 } else {
2563 synchronize_irq(adapter->pdev->irq);
2564 }
2565 }
2566
2567 /**
2568 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2569 *
2570 **/
2571 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2572 {
2573 struct ixgbe_hw *hw = &adapter->hw;
2574
2575 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2576 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2577
2578 ixgbe_set_ivar(adapter, 0, 0, 0);
2579 ixgbe_set_ivar(adapter, 1, 0, 0);
2580
2581 map_vector_to_rxq(adapter, 0, 0);
2582 map_vector_to_txq(adapter, 0, 0);
2583
2584 e_info(hw, "Legacy interrupt IVAR setup done\n");
2585 }
2586
2587 /**
2588 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2589 * @adapter: board private structure
2590 * @ring: structure containing ring specific data
2591 *
2592 * Configure the Tx descriptor ring after a reset.
2593 **/
2594 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2595 struct ixgbe_ring *ring)
2596 {
2597 struct ixgbe_hw *hw = &adapter->hw;
2598 u64 tdba = ring->dma;
2599 int wait_loop = 10;
2600 u32 txdctl;
2601 u8 reg_idx = ring->reg_idx;
2602
2603 /* disable queue to avoid issues while updating state */
2604 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2605 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2606 txdctl & ~IXGBE_TXDCTL_ENABLE);
2607 IXGBE_WRITE_FLUSH(hw);
2608
2609 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2610 (tdba & DMA_BIT_MASK(32)));
2611 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2612 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2613 ring->count * sizeof(union ixgbe_adv_tx_desc));
2614 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2615 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2616 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2617
2618 /* configure fetching thresholds */
2619 if (adapter->rx_itr_setting == 0) {
2620 /* cannot set wthresh when itr==0 */
2621 txdctl &= ~0x007F0000;
2622 } else {
2623 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2624 txdctl |= (8 << 16);
2625 }
2626 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2627 /* PThresh workaround for Tx hang with DFP enabled. */
2628 txdctl |= 32;
2629 }
2630
2631 /* reinitialize flowdirector state */
2632 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2633 adapter->atr_sample_rate) {
2634 ring->atr_sample_rate = adapter->atr_sample_rate;
2635 ring->atr_count = 0;
2636 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2637 } else {
2638 ring->atr_sample_rate = 0;
2639 }
2640
2641 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2642
2643 /* enable queue */
2644 txdctl |= IXGBE_TXDCTL_ENABLE;
2645 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2646
2647 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2648 if (hw->mac.type == ixgbe_mac_82598EB &&
2649 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2650 return;
2651
2652 /* poll to verify queue is enabled */
2653 do {
2654 usleep_range(1000, 2000);
2655 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2656 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2657 if (!wait_loop)
2658 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2659 }
2660
2661 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2662 {
2663 struct ixgbe_hw *hw = &adapter->hw;
2664 u32 rttdcs;
2665 u32 reg;
2666 u8 tcs = netdev_get_num_tc(adapter->netdev);
2667
2668 if (hw->mac.type == ixgbe_mac_82598EB)
2669 return;
2670
2671 /* disable the arbiter while setting MTQC */
2672 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2673 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2674 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2675
2676 /* set transmit pool layout */
2677 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2678 case (IXGBE_FLAG_SRIOV_ENABLED):
2679 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2680 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2681 break;
2682 default:
2683 if (!tcs)
2684 reg = IXGBE_MTQC_64Q_1PB;
2685 else if (tcs <= 4)
2686 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2687 else
2688 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2689
2690 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2691
2692 /* Enable Security TX Buffer IFG for multiple pb */
2693 if (tcs) {
2694 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2695 reg |= IXGBE_SECTX_DCB;
2696 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2697 }
2698 break;
2699 }
2700
2701 /* re-enable the arbiter */
2702 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2703 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2704 }
2705
2706 /**
2707 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2708 * @adapter: board private structure
2709 *
2710 * Configure the Tx unit of the MAC after a reset.
2711 **/
2712 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2713 {
2714 struct ixgbe_hw *hw = &adapter->hw;
2715 u32 dmatxctl;
2716 u32 i;
2717
2718 ixgbe_setup_mtqc(adapter);
2719
2720 if (hw->mac.type != ixgbe_mac_82598EB) {
2721 /* DMATXCTL.EN must be before Tx queues are enabled */
2722 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2723 dmatxctl |= IXGBE_DMATXCTL_TE;
2724 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2725 }
2726
2727 /* Setup the HW Tx Head and Tail descriptor pointers */
2728 for (i = 0; i < adapter->num_tx_queues; i++)
2729 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2730 }
2731
2732 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2733
2734 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2735 struct ixgbe_ring *rx_ring)
2736 {
2737 u32 srrctl;
2738 u8 reg_idx = rx_ring->reg_idx;
2739
2740 switch (adapter->hw.mac.type) {
2741 case ixgbe_mac_82598EB: {
2742 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2743 const int mask = feature[RING_F_RSS].mask;
2744 reg_idx = reg_idx & mask;
2745 }
2746 break;
2747 case ixgbe_mac_82599EB:
2748 case ixgbe_mac_X540:
2749 default:
2750 break;
2751 }
2752
2753 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2754
2755 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2756 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2757 if (adapter->num_vfs)
2758 srrctl |= IXGBE_SRRCTL_DROP_EN;
2759
2760 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2761 IXGBE_SRRCTL_BSIZEHDR_MASK;
2762
2763 if (ring_is_ps_enabled(rx_ring)) {
2764 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2765 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2766 #else
2767 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2768 #endif
2769 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2770 } else {
2771 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2772 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2773 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2774 }
2775
2776 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2777 }
2778
2779 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2780 {
2781 struct ixgbe_hw *hw = &adapter->hw;
2782 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2783 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2784 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2785 u32 mrqc = 0, reta = 0;
2786 u32 rxcsum;
2787 int i, j;
2788 u8 tcs = netdev_get_num_tc(adapter->netdev);
2789 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2790
2791 if (tcs)
2792 maxq = min(maxq, adapter->num_tx_queues / tcs);
2793
2794 /* Fill out hash function seeds */
2795 for (i = 0; i < 10; i++)
2796 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2797
2798 /* Fill out redirection table */
2799 for (i = 0, j = 0; i < 128; i++, j++) {
2800 if (j == maxq)
2801 j = 0;
2802 /* reta = 4-byte sliding window of
2803 * 0x00..(indices-1)(indices-1)00..etc. */
2804 reta = (reta << 8) | (j * 0x11);
2805 if ((i & 3) == 3)
2806 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2807 }
2808
2809 /* Disable indicating checksum in descriptor, enables RSS hash */
2810 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2811 rxcsum |= IXGBE_RXCSUM_PCSD;
2812 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2813
2814 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2815 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
2816 mrqc = IXGBE_MRQC_RSSEN;
2817 } else {
2818 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2819 | IXGBE_FLAG_SRIOV_ENABLED);
2820
2821 switch (mask) {
2822 case (IXGBE_FLAG_RSS_ENABLED):
2823 if (!tcs)
2824 mrqc = IXGBE_MRQC_RSSEN;
2825 else if (tcs <= 4)
2826 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2827 else
2828 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2829 break;
2830 case (IXGBE_FLAG_SRIOV_ENABLED):
2831 mrqc = IXGBE_MRQC_VMDQEN;
2832 break;
2833 default:
2834 break;
2835 }
2836 }
2837
2838 /* Perform hash on these packet types */
2839 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2840 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2841 | IXGBE_MRQC_RSS_FIELD_IPV6
2842 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2843
2844 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2845 }
2846
2847 /**
2848 * ixgbe_clear_rscctl - disable RSC for the indicated ring
2849 * @adapter: address of board private structure
2850 * @ring: structure containing ring specific data
2851 **/
2852 void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
2853 struct ixgbe_ring *ring)
2854 {
2855 struct ixgbe_hw *hw = &adapter->hw;
2856 u32 rscctrl;
2857 u8 reg_idx = ring->reg_idx;
2858
2859 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2860 rscctrl &= ~IXGBE_RSCCTL_RSCEN;
2861 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2862 }
2863
2864 /**
2865 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2866 * @adapter: address of board private structure
2867 * @index: index of ring to set
2868 **/
2869 void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2870 struct ixgbe_ring *ring)
2871 {
2872 struct ixgbe_hw *hw = &adapter->hw;
2873 u32 rscctrl;
2874 int rx_buf_len;
2875 u8 reg_idx = ring->reg_idx;
2876
2877 if (!ring_is_rsc_enabled(ring))
2878 return;
2879
2880 rx_buf_len = ring->rx_buf_len;
2881 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2882 rscctrl |= IXGBE_RSCCTL_RSCEN;
2883 /*
2884 * we must limit the number of descriptors so that the
2885 * total size of max desc * buf_len is not greater
2886 * than 65535
2887 */
2888 if (ring_is_ps_enabled(ring)) {
2889 #if (MAX_SKB_FRAGS > 16)
2890 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2891 #elif (MAX_SKB_FRAGS > 8)
2892 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2893 #elif (MAX_SKB_FRAGS > 4)
2894 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2895 #else
2896 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2897 #endif
2898 } else {
2899 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2900 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2901 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2902 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2903 else
2904 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2905 }
2906 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2907 }
2908
2909 /**
2910 * ixgbe_set_uta - Set unicast filter table address
2911 * @adapter: board private structure
2912 *
2913 * The unicast table address is a register array of 32-bit registers.
2914 * The table is meant to be used in a way similar to how the MTA is used
2915 * however due to certain limitations in the hardware it is necessary to
2916 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2917 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2918 **/
2919 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2920 {
2921 struct ixgbe_hw *hw = &adapter->hw;
2922 int i;
2923
2924 /* The UTA table only exists on 82599 hardware and newer */
2925 if (hw->mac.type < ixgbe_mac_82599EB)
2926 return;
2927
2928 /* we only need to do this if VMDq is enabled */
2929 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2930 return;
2931
2932 for (i = 0; i < 128; i++)
2933 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2934 }
2935
2936 #define IXGBE_MAX_RX_DESC_POLL 10
2937 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2938 struct ixgbe_ring *ring)
2939 {
2940 struct ixgbe_hw *hw = &adapter->hw;
2941 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2942 u32 rxdctl;
2943 u8 reg_idx = ring->reg_idx;
2944
2945 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2946 if (hw->mac.type == ixgbe_mac_82598EB &&
2947 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2948 return;
2949
2950 do {
2951 usleep_range(1000, 2000);
2952 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2953 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2954
2955 if (!wait_loop) {
2956 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2957 "the polling period\n", reg_idx);
2958 }
2959 }
2960
2961 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2962 struct ixgbe_ring *ring)
2963 {
2964 struct ixgbe_hw *hw = &adapter->hw;
2965 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2966 u32 rxdctl;
2967 u8 reg_idx = ring->reg_idx;
2968
2969 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2970 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2971
2972 /* write value back with RXDCTL.ENABLE bit cleared */
2973 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2974
2975 if (hw->mac.type == ixgbe_mac_82598EB &&
2976 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2977 return;
2978
2979 /* the hardware may take up to 100us to really disable the rx queue */
2980 do {
2981 udelay(10);
2982 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2983 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2984
2985 if (!wait_loop) {
2986 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2987 "the polling period\n", reg_idx);
2988 }
2989 }
2990
2991 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2992 struct ixgbe_ring *ring)
2993 {
2994 struct ixgbe_hw *hw = &adapter->hw;
2995 u64 rdba = ring->dma;
2996 u32 rxdctl;
2997 u8 reg_idx = ring->reg_idx;
2998
2999 /* disable queue to avoid issues while updating state */
3000 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3001 ixgbe_disable_rx_queue(adapter, ring);
3002
3003 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3004 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3005 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3006 ring->count * sizeof(union ixgbe_adv_rx_desc));
3007 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3008 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3009 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3010
3011 ixgbe_configure_srrctl(adapter, ring);
3012 ixgbe_configure_rscctl(adapter, ring);
3013
3014 /* If operating in IOV mode set RLPML for X540 */
3015 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3016 hw->mac.type == ixgbe_mac_X540) {
3017 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3018 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3019 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3020 }
3021
3022 if (hw->mac.type == ixgbe_mac_82598EB) {
3023 /*
3024 * enable cache line friendly hardware writes:
3025 * PTHRESH=32 descriptors (half the internal cache),
3026 * this also removes ugly rx_no_buffer_count increment
3027 * HTHRESH=4 descriptors (to minimize latency on fetch)
3028 * WTHRESH=8 burst writeback up to two cache lines
3029 */
3030 rxdctl &= ~0x3FFFFF;
3031 rxdctl |= 0x080420;
3032 }
3033
3034 /* enable receive descriptor ring */
3035 rxdctl |= IXGBE_RXDCTL_ENABLE;
3036 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3037
3038 ixgbe_rx_desc_queue_enable(adapter, ring);
3039 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3040 }
3041
3042 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3043 {
3044 struct ixgbe_hw *hw = &adapter->hw;
3045 int p;
3046
3047 /* PSRTYPE must be initialized in non 82598 adapters */
3048 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3049 IXGBE_PSRTYPE_UDPHDR |
3050 IXGBE_PSRTYPE_IPV4HDR |
3051 IXGBE_PSRTYPE_L2HDR |
3052 IXGBE_PSRTYPE_IPV6HDR;
3053
3054 if (hw->mac.type == ixgbe_mac_82598EB)
3055 return;
3056
3057 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3058 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3059
3060 for (p = 0; p < adapter->num_rx_pools; p++)
3061 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3062 psrtype);
3063 }
3064
3065 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3066 {
3067 struct ixgbe_hw *hw = &adapter->hw;
3068 u32 gcr_ext;
3069 u32 vt_reg_bits;
3070 u32 reg_offset, vf_shift;
3071 u32 vmdctl;
3072
3073 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3074 return;
3075
3076 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3077 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3078 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3079 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3080
3081 vf_shift = adapter->num_vfs % 32;
3082 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3083
3084 /* Enable only the PF's pool for Tx/Rx */
3085 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3086 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3087 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3088 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3089 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3090
3091 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3092 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3093
3094 /*
3095 * Set up VF register offsets for selected VT Mode,
3096 * i.e. 32 or 64 VFs for SR-IOV
3097 */
3098 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3099 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3100 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3101 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3102
3103 /* enable Tx loopback for VF/PF communication */
3104 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3105 /* Enable MAC Anti-Spoofing */
3106 hw->mac.ops.set_mac_anti_spoofing(hw,
3107 (adapter->antispoofing_enabled =
3108 (adapter->num_vfs != 0)),
3109 adapter->num_vfs);
3110 }
3111
3112 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3113 {
3114 struct ixgbe_hw *hw = &adapter->hw;
3115 struct net_device *netdev = adapter->netdev;
3116 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3117 int rx_buf_len;
3118 struct ixgbe_ring *rx_ring;
3119 int i;
3120 u32 mhadd, hlreg0;
3121
3122 /* Decide whether to use packet split mode or not */
3123 /* On by default */
3124 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3125
3126 /* Do not use packet split if we're in SR-IOV Mode */
3127 if (adapter->num_vfs)
3128 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3129
3130 /* Disable packet split due to 82599 erratum #45 */
3131 if (hw->mac.type == ixgbe_mac_82599EB)
3132 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3133
3134 /* Set the RX buffer length according to the mode */
3135 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3136 rx_buf_len = IXGBE_RX_HDR_SIZE;
3137 } else {
3138 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3139 (netdev->mtu <= ETH_DATA_LEN))
3140 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3141 else
3142 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
3143 }
3144
3145 #ifdef IXGBE_FCOE
3146 /* adjust max frame to be able to do baby jumbo for FCoE */
3147 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3148 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3149 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3150
3151 #endif /* IXGBE_FCOE */
3152 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3153 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3154 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3155 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3156
3157 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3158 }
3159
3160 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3161 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3162 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3163 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3164
3165 /*
3166 * Setup the HW Rx Head and Tail Descriptor Pointers and
3167 * the Base and Length of the Rx Descriptor Ring
3168 */
3169 for (i = 0; i < adapter->num_rx_queues; i++) {
3170 rx_ring = adapter->rx_ring[i];
3171 rx_ring->rx_buf_len = rx_buf_len;
3172
3173 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
3174 set_ring_ps_enabled(rx_ring);
3175 else
3176 clear_ring_ps_enabled(rx_ring);
3177
3178 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3179 set_ring_rsc_enabled(rx_ring);
3180 else
3181 clear_ring_rsc_enabled(rx_ring);
3182
3183 #ifdef IXGBE_FCOE
3184 if (netdev->features & NETIF_F_FCOE_MTU) {
3185 struct ixgbe_ring_feature *f;
3186 f = &adapter->ring_feature[RING_F_FCOE];
3187 if ((i >= f->mask) && (i < f->mask + f->indices)) {
3188 clear_ring_ps_enabled(rx_ring);
3189 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3190 rx_ring->rx_buf_len =
3191 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3192 } else if (!ring_is_rsc_enabled(rx_ring) &&
3193 !ring_is_ps_enabled(rx_ring)) {
3194 rx_ring->rx_buf_len =
3195 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3196 }
3197 }
3198 #endif /* IXGBE_FCOE */
3199 }
3200 }
3201
3202 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3203 {
3204 struct ixgbe_hw *hw = &adapter->hw;
3205 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3206
3207 switch (hw->mac.type) {
3208 case ixgbe_mac_82598EB:
3209 /*
3210 * For VMDq support of different descriptor types or
3211 * buffer sizes through the use of multiple SRRCTL
3212 * registers, RDRXCTL.MVMEN must be set to 1
3213 *
3214 * also, the manual doesn't mention it clearly but DCA hints
3215 * will only use queue 0's tags unless this bit is set. Side
3216 * effects of setting this bit are only that SRRCTL must be
3217 * fully programmed [0..15]
3218 */
3219 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3220 break;
3221 case ixgbe_mac_82599EB:
3222 case ixgbe_mac_X540:
3223 /* Disable RSC for ACK packets */
3224 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3225 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3226 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3227 /* hardware requires some bits to be set by default */
3228 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3229 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3230 break;
3231 default:
3232 /* We should do nothing since we don't know this hardware */
3233 return;
3234 }
3235
3236 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3237 }
3238
3239 /**
3240 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3241 * @adapter: board private structure
3242 *
3243 * Configure the Rx unit of the MAC after a reset.
3244 **/
3245 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3246 {
3247 struct ixgbe_hw *hw = &adapter->hw;
3248 int i;
3249 u32 rxctrl;
3250
3251 /* disable receives while setting up the descriptors */
3252 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3253 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3254
3255 ixgbe_setup_psrtype(adapter);
3256 ixgbe_setup_rdrxctl(adapter);
3257
3258 /* Program registers for the distribution of queues */
3259 ixgbe_setup_mrqc(adapter);
3260
3261 ixgbe_set_uta(adapter);
3262
3263 /* set_rx_buffer_len must be called before ring initialization */
3264 ixgbe_set_rx_buffer_len(adapter);
3265
3266 /*
3267 * Setup the HW Rx Head and Tail Descriptor Pointers and
3268 * the Base and Length of the Rx Descriptor Ring
3269 */
3270 for (i = 0; i < adapter->num_rx_queues; i++)
3271 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3272
3273 /* disable drop enable for 82598 parts */
3274 if (hw->mac.type == ixgbe_mac_82598EB)
3275 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3276
3277 /* enable all receives */
3278 rxctrl |= IXGBE_RXCTRL_RXEN;
3279 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3280 }
3281
3282 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3283 {
3284 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3285 struct ixgbe_hw *hw = &adapter->hw;
3286 int pool_ndx = adapter->num_vfs;
3287
3288 /* add VID to filter table */
3289 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3290 set_bit(vid, adapter->active_vlans);
3291 }
3292
3293 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3294 {
3295 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3296 struct ixgbe_hw *hw = &adapter->hw;
3297 int pool_ndx = adapter->num_vfs;
3298
3299 /* remove VID from filter table */
3300 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3301 clear_bit(vid, adapter->active_vlans);
3302 }
3303
3304 /**
3305 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3306 * @adapter: driver data
3307 */
3308 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3309 {
3310 struct ixgbe_hw *hw = &adapter->hw;
3311 u32 vlnctrl;
3312
3313 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3314 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3315 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3316 }
3317
3318 /**
3319 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3320 * @adapter: driver data
3321 */
3322 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3323 {
3324 struct ixgbe_hw *hw = &adapter->hw;
3325 u32 vlnctrl;
3326
3327 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3328 vlnctrl |= IXGBE_VLNCTRL_VFE;
3329 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3330 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3331 }
3332
3333 /**
3334 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3335 * @adapter: driver data
3336 */
3337 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3338 {
3339 struct ixgbe_hw *hw = &adapter->hw;
3340 u32 vlnctrl;
3341 int i, j;
3342
3343 switch (hw->mac.type) {
3344 case ixgbe_mac_82598EB:
3345 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3346 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3347 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3348 break;
3349 case ixgbe_mac_82599EB:
3350 case ixgbe_mac_X540:
3351 for (i = 0; i < adapter->num_rx_queues; i++) {
3352 j = adapter->rx_ring[i]->reg_idx;
3353 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3354 vlnctrl &= ~IXGBE_RXDCTL_VME;
3355 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3356 }
3357 break;
3358 default:
3359 break;
3360 }
3361 }
3362
3363 /**
3364 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3365 * @adapter: driver data
3366 */
3367 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3368 {
3369 struct ixgbe_hw *hw = &adapter->hw;
3370 u32 vlnctrl;
3371 int i, j;
3372
3373 switch (hw->mac.type) {
3374 case ixgbe_mac_82598EB:
3375 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3376 vlnctrl |= IXGBE_VLNCTRL_VME;
3377 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3378 break;
3379 case ixgbe_mac_82599EB:
3380 case ixgbe_mac_X540:
3381 for (i = 0; i < adapter->num_rx_queues; i++) {
3382 j = adapter->rx_ring[i]->reg_idx;
3383 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3384 vlnctrl |= IXGBE_RXDCTL_VME;
3385 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3386 }
3387 break;
3388 default:
3389 break;
3390 }
3391 }
3392
3393 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3394 {
3395 u16 vid;
3396
3397 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3398
3399 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3400 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3401 }
3402
3403 /**
3404 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3405 * @netdev: network interface device structure
3406 *
3407 * Writes unicast address list to the RAR table.
3408 * Returns: -ENOMEM on failure/insufficient address space
3409 * 0 on no addresses written
3410 * X on writing X addresses to the RAR table
3411 **/
3412 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3413 {
3414 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3415 struct ixgbe_hw *hw = &adapter->hw;
3416 unsigned int vfn = adapter->num_vfs;
3417 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3418 int count = 0;
3419
3420 /* return ENOMEM indicating insufficient memory for addresses */
3421 if (netdev_uc_count(netdev) > rar_entries)
3422 return -ENOMEM;
3423
3424 if (!netdev_uc_empty(netdev) && rar_entries) {
3425 struct netdev_hw_addr *ha;
3426 /* return error if we do not support writing to RAR table */
3427 if (!hw->mac.ops.set_rar)
3428 return -ENOMEM;
3429
3430 netdev_for_each_uc_addr(ha, netdev) {
3431 if (!rar_entries)
3432 break;
3433 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3434 vfn, IXGBE_RAH_AV);
3435 count++;
3436 }
3437 }
3438 /* write the addresses in reverse order to avoid write combining */
3439 for (; rar_entries > 0 ; rar_entries--)
3440 hw->mac.ops.clear_rar(hw, rar_entries);
3441
3442 return count;
3443 }
3444
3445 /**
3446 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3447 * @netdev: network interface device structure
3448 *
3449 * The set_rx_method entry point is called whenever the unicast/multicast
3450 * address list or the network interface flags are updated. This routine is
3451 * responsible for configuring the hardware for proper unicast, multicast and
3452 * promiscuous mode.
3453 **/
3454 void ixgbe_set_rx_mode(struct net_device *netdev)
3455 {
3456 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3457 struct ixgbe_hw *hw = &adapter->hw;
3458 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3459 int count;
3460
3461 /* Check for Promiscuous and All Multicast modes */
3462
3463 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3464
3465 /* set all bits that we expect to always be set */
3466 fctrl |= IXGBE_FCTRL_BAM;
3467 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3468 fctrl |= IXGBE_FCTRL_PMCF;
3469
3470 /* clear the bits we are changing the status of */
3471 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3472
3473 if (netdev->flags & IFF_PROMISC) {
3474 hw->addr_ctrl.user_set_promisc = true;
3475 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3476 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3477 /* don't hardware filter vlans in promisc mode */
3478 ixgbe_vlan_filter_disable(adapter);
3479 } else {
3480 if (netdev->flags & IFF_ALLMULTI) {
3481 fctrl |= IXGBE_FCTRL_MPE;
3482 vmolr |= IXGBE_VMOLR_MPE;
3483 } else {
3484 /*
3485 * Write addresses to the MTA, if the attempt fails
3486 * then we should just turn on promiscuous mode so
3487 * that we can at least receive multicast traffic
3488 */
3489 hw->mac.ops.update_mc_addr_list(hw, netdev);
3490 vmolr |= IXGBE_VMOLR_ROMPE;
3491 }
3492 ixgbe_vlan_filter_enable(adapter);
3493 hw->addr_ctrl.user_set_promisc = false;
3494 /*
3495 * Write addresses to available RAR registers, if there is not
3496 * sufficient space to store all the addresses then enable
3497 * unicast promiscuous mode
3498 */
3499 count = ixgbe_write_uc_addr_list(netdev);
3500 if (count < 0) {
3501 fctrl |= IXGBE_FCTRL_UPE;
3502 vmolr |= IXGBE_VMOLR_ROPE;
3503 }
3504 }
3505
3506 if (adapter->num_vfs) {
3507 ixgbe_restore_vf_multicasts(adapter);
3508 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3509 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3510 IXGBE_VMOLR_ROPE);
3511 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3512 }
3513
3514 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3515
3516 if (netdev->features & NETIF_F_HW_VLAN_RX)
3517 ixgbe_vlan_strip_enable(adapter);
3518 else
3519 ixgbe_vlan_strip_disable(adapter);
3520 }
3521
3522 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3523 {
3524 int q_idx;
3525 struct ixgbe_q_vector *q_vector;
3526 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3527
3528 /* legacy and MSI only use one vector */
3529 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3530 q_vectors = 1;
3531
3532 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3533 struct napi_struct *napi;
3534 q_vector = adapter->q_vector[q_idx];
3535 napi = &q_vector->napi;
3536 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3537 if (!q_vector->rx.count || !q_vector->tx.count) {
3538 if (q_vector->tx.count == 1)
3539 napi->poll = &ixgbe_clean_txonly;
3540 else if (q_vector->rx.count == 1)
3541 napi->poll = &ixgbe_clean_rxonly;
3542 }
3543 }
3544
3545 napi_enable(napi);
3546 }
3547 }
3548
3549 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3550 {
3551 int q_idx;
3552 struct ixgbe_q_vector *q_vector;
3553 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3554
3555 /* legacy and MSI only use one vector */
3556 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3557 q_vectors = 1;
3558
3559 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3560 q_vector = adapter->q_vector[q_idx];
3561 napi_disable(&q_vector->napi);
3562 }
3563 }
3564
3565 #ifdef CONFIG_IXGBE_DCB
3566 /*
3567 * ixgbe_configure_dcb - Configure DCB hardware
3568 * @adapter: ixgbe adapter struct
3569 *
3570 * This is called by the driver on open to configure the DCB hardware.
3571 * This is also called by the gennetlink interface when reconfiguring
3572 * the DCB state.
3573 */
3574 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3575 {
3576 struct ixgbe_hw *hw = &adapter->hw;
3577 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3578
3579 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3580 if (hw->mac.type == ixgbe_mac_82598EB)
3581 netif_set_gso_max_size(adapter->netdev, 65536);
3582 return;
3583 }
3584
3585 if (hw->mac.type == ixgbe_mac_82598EB)
3586 netif_set_gso_max_size(adapter->netdev, 32768);
3587
3588
3589 /* Enable VLAN tag insert/strip */
3590 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3591
3592 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3593
3594 /* reconfigure the hardware */
3595 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3596 #ifdef CONFIG_FCOE
3597 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3598 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3599 #endif
3600 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3601 DCB_TX_CONFIG);
3602 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3603 DCB_RX_CONFIG);
3604 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3605 } else {
3606 struct net_device *dev = adapter->netdev;
3607
3608 if (adapter->ixgbe_ieee_ets)
3609 dev->dcbnl_ops->ieee_setets(dev,
3610 adapter->ixgbe_ieee_ets);
3611 if (adapter->ixgbe_ieee_pfc)
3612 dev->dcbnl_ops->ieee_setpfc(dev,
3613 adapter->ixgbe_ieee_pfc);
3614 }
3615
3616 /* Enable RSS Hash per TC */
3617 if (hw->mac.type != ixgbe_mac_82598EB) {
3618 int i;
3619 u32 reg = 0;
3620
3621 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3622 u8 msb = 0;
3623 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3624
3625 while (cnt >>= 1)
3626 msb++;
3627
3628 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3629 }
3630 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3631 }
3632 }
3633
3634 #endif
3635
3636 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3637 {
3638 int hdrm = 0;
3639 int num_tc = netdev_get_num_tc(adapter->netdev);
3640 struct ixgbe_hw *hw = &adapter->hw;
3641
3642 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3643 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3644 hdrm = 64 << adapter->fdir_pballoc;
3645
3646 hw->mac.ops.set_rxpba(&adapter->hw, num_tc, hdrm, PBA_STRATEGY_EQUAL);
3647 }
3648
3649 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3650 {
3651 struct ixgbe_hw *hw = &adapter->hw;
3652 struct hlist_node *node, *node2;
3653 struct ixgbe_fdir_filter *filter;
3654
3655 spin_lock(&adapter->fdir_perfect_lock);
3656
3657 if (!hlist_empty(&adapter->fdir_filter_list))
3658 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3659
3660 hlist_for_each_entry_safe(filter, node, node2,
3661 &adapter->fdir_filter_list, fdir_node) {
3662 ixgbe_fdir_write_perfect_filter_82599(hw,
3663 &filter->filter,
3664 filter->sw_idx,
3665 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3666 IXGBE_FDIR_DROP_QUEUE :
3667 adapter->rx_ring[filter->action]->reg_idx);
3668 }
3669
3670 spin_unlock(&adapter->fdir_perfect_lock);
3671 }
3672
3673 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3674 {
3675 struct net_device *netdev = adapter->netdev;
3676 struct ixgbe_hw *hw = &adapter->hw;
3677 int i;
3678
3679 ixgbe_configure_pb(adapter);
3680 #ifdef CONFIG_IXGBE_DCB
3681 ixgbe_configure_dcb(adapter);
3682 #endif
3683
3684 ixgbe_set_rx_mode(netdev);
3685 ixgbe_restore_vlan(adapter);
3686
3687 #ifdef IXGBE_FCOE
3688 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3689 ixgbe_configure_fcoe(adapter);
3690
3691 #endif /* IXGBE_FCOE */
3692 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3693 for (i = 0; i < adapter->num_tx_queues; i++)
3694 adapter->tx_ring[i]->atr_sample_rate =
3695 adapter->atr_sample_rate;
3696 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3697 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3698 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3699 adapter->fdir_pballoc);
3700 ixgbe_fdir_filter_restore(adapter);
3701 }
3702 ixgbe_configure_virtualization(adapter);
3703
3704 ixgbe_configure_tx(adapter);
3705 ixgbe_configure_rx(adapter);
3706 }
3707
3708 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3709 {
3710 switch (hw->phy.type) {
3711 case ixgbe_phy_sfp_avago:
3712 case ixgbe_phy_sfp_ftl:
3713 case ixgbe_phy_sfp_intel:
3714 case ixgbe_phy_sfp_unknown:
3715 case ixgbe_phy_sfp_passive_tyco:
3716 case ixgbe_phy_sfp_passive_unknown:
3717 case ixgbe_phy_sfp_active_unknown:
3718 case ixgbe_phy_sfp_ftl_active:
3719 return true;
3720 default:
3721 return false;
3722 }
3723 }
3724
3725 /**
3726 * ixgbe_sfp_link_config - set up SFP+ link
3727 * @adapter: pointer to private adapter struct
3728 **/
3729 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3730 {
3731 /*
3732 * We are assuming the worst case scenerio here, and that
3733 * is that an SFP was inserted/removed after the reset
3734 * but before SFP detection was enabled. As such the best
3735 * solution is to just start searching as soon as we start
3736 */
3737 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3738 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3739
3740 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3741 }
3742
3743 /**
3744 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3745 * @hw: pointer to private hardware struct
3746 *
3747 * Returns 0 on success, negative on failure
3748 **/
3749 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3750 {
3751 u32 autoneg;
3752 bool negotiation, link_up = false;
3753 u32 ret = IXGBE_ERR_LINK_SETUP;
3754
3755 if (hw->mac.ops.check_link)
3756 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3757
3758 if (ret)
3759 goto link_cfg_out;
3760
3761 autoneg = hw->phy.autoneg_advertised;
3762 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3763 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3764 &negotiation);
3765 if (ret)
3766 goto link_cfg_out;
3767
3768 if (hw->mac.ops.setup_link)
3769 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3770 link_cfg_out:
3771 return ret;
3772 }
3773
3774 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3775 {
3776 struct ixgbe_hw *hw = &adapter->hw;
3777 u32 gpie = 0;
3778
3779 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3780 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3781 IXGBE_GPIE_OCD;
3782 gpie |= IXGBE_GPIE_EIAME;
3783 /*
3784 * use EIAM to auto-mask when MSI-X interrupt is asserted
3785 * this saves a register write for every interrupt
3786 */
3787 switch (hw->mac.type) {
3788 case ixgbe_mac_82598EB:
3789 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3790 break;
3791 case ixgbe_mac_82599EB:
3792 case ixgbe_mac_X540:
3793 default:
3794 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3795 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3796 break;
3797 }
3798 } else {
3799 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3800 * specifically only auto mask tx and rx interrupts */
3801 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3802 }
3803
3804 /* XXX: to interrupt immediately for EICS writes, enable this */
3805 /* gpie |= IXGBE_GPIE_EIMEN; */
3806
3807 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3808 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3809 gpie |= IXGBE_GPIE_VTMODE_64;
3810 }
3811
3812 /* Enable fan failure interrupt */
3813 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3814 gpie |= IXGBE_SDP1_GPIEN;
3815
3816 if (hw->mac.type == ixgbe_mac_82599EB) {
3817 gpie |= IXGBE_SDP1_GPIEN;
3818 gpie |= IXGBE_SDP2_GPIEN;
3819 }
3820
3821 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3822 }
3823
3824 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3825 {
3826 struct ixgbe_hw *hw = &adapter->hw;
3827 int err;
3828 u32 ctrl_ext;
3829
3830 ixgbe_get_hw_control(adapter);
3831 ixgbe_setup_gpie(adapter);
3832
3833 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3834 ixgbe_configure_msix(adapter);
3835 else
3836 ixgbe_configure_msi_and_legacy(adapter);
3837
3838 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3839 if (hw->mac.ops.enable_tx_laser &&
3840 ((hw->phy.multispeed_fiber) ||
3841 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3842 (hw->mac.type == ixgbe_mac_82599EB))))
3843 hw->mac.ops.enable_tx_laser(hw);
3844
3845 clear_bit(__IXGBE_DOWN, &adapter->state);
3846 ixgbe_napi_enable_all(adapter);
3847
3848 if (ixgbe_is_sfp(hw)) {
3849 ixgbe_sfp_link_config(adapter);
3850 } else {
3851 err = ixgbe_non_sfp_link_config(hw);
3852 if (err)
3853 e_err(probe, "link_config FAILED %d\n", err);
3854 }
3855
3856 /* clear any pending interrupts, may auto mask */
3857 IXGBE_READ_REG(hw, IXGBE_EICR);
3858 ixgbe_irq_enable(adapter, true, true);
3859
3860 /*
3861 * If this adapter has a fan, check to see if we had a failure
3862 * before we enabled the interrupt.
3863 */
3864 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3865 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3866 if (esdp & IXGBE_ESDP_SDP1)
3867 e_crit(drv, "Fan has stopped, replace the adapter\n");
3868 }
3869
3870 /* enable transmits */
3871 netif_tx_start_all_queues(adapter->netdev);
3872
3873 /* bring the link up in the watchdog, this could race with our first
3874 * link up interrupt but shouldn't be a problem */
3875 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3876 adapter->link_check_timeout = jiffies;
3877 mod_timer(&adapter->service_timer, jiffies);
3878
3879 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3880 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3881 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3882 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3883
3884 return 0;
3885 }
3886
3887 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3888 {
3889 WARN_ON(in_interrupt());
3890 /* put off any impending NetWatchDogTimeout */
3891 adapter->netdev->trans_start = jiffies;
3892
3893 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3894 usleep_range(1000, 2000);
3895 ixgbe_down(adapter);
3896 /*
3897 * If SR-IOV enabled then wait a bit before bringing the adapter
3898 * back up to give the VFs time to respond to the reset. The
3899 * two second wait is based upon the watchdog timer cycle in
3900 * the VF driver.
3901 */
3902 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3903 msleep(2000);
3904 ixgbe_up(adapter);
3905 clear_bit(__IXGBE_RESETTING, &adapter->state);
3906 }
3907
3908 int ixgbe_up(struct ixgbe_adapter *adapter)
3909 {
3910 /* hardware has been reset, we need to reload some things */
3911 ixgbe_configure(adapter);
3912
3913 return ixgbe_up_complete(adapter);
3914 }
3915
3916 void ixgbe_reset(struct ixgbe_adapter *adapter)
3917 {
3918 struct ixgbe_hw *hw = &adapter->hw;
3919 int err;
3920
3921 /* lock SFP init bit to prevent race conditions with the watchdog */
3922 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3923 usleep_range(1000, 2000);
3924
3925 /* clear all SFP and link config related flags while holding SFP_INIT */
3926 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3927 IXGBE_FLAG2_SFP_NEEDS_RESET);
3928 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3929
3930 err = hw->mac.ops.init_hw(hw);
3931 switch (err) {
3932 case 0:
3933 case IXGBE_ERR_SFP_NOT_PRESENT:
3934 case IXGBE_ERR_SFP_NOT_SUPPORTED:
3935 break;
3936 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3937 e_dev_err("master disable timed out\n");
3938 break;
3939 case IXGBE_ERR_EEPROM_VERSION:
3940 /* We are running on a pre-production device, log a warning */
3941 e_dev_warn("This device is a pre-production adapter/LOM. "
3942 "Please be aware there may be issuesassociated with "
3943 "your hardware. If you are experiencing problems "
3944 "please contact your Intel or hardware "
3945 "representative who provided you with this "
3946 "hardware.\n");
3947 break;
3948 default:
3949 e_dev_err("Hardware Error: %d\n", err);
3950 }
3951
3952 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3953
3954 /* reprogram the RAR[0] in case user changed it. */
3955 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3956 IXGBE_RAH_AV);
3957 }
3958
3959 /**
3960 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3961 * @rx_ring: ring to free buffers from
3962 **/
3963 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3964 {
3965 struct device *dev = rx_ring->dev;
3966 unsigned long size;
3967 u16 i;
3968
3969 /* ring already cleared, nothing to do */
3970 if (!rx_ring->rx_buffer_info)
3971 return;
3972
3973 /* Free all the Rx ring sk_buffs */
3974 for (i = 0; i < rx_ring->count; i++) {
3975 struct ixgbe_rx_buffer *rx_buffer_info;
3976
3977 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3978 if (rx_buffer_info->dma) {
3979 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3980 rx_ring->rx_buf_len,
3981 DMA_FROM_DEVICE);
3982 rx_buffer_info->dma = 0;
3983 }
3984 if (rx_buffer_info->skb) {
3985 struct sk_buff *skb = rx_buffer_info->skb;
3986 rx_buffer_info->skb = NULL;
3987 do {
3988 struct sk_buff *this = skb;
3989 if (IXGBE_RSC_CB(this)->delay_unmap) {
3990 dma_unmap_single(dev,
3991 IXGBE_RSC_CB(this)->dma,
3992 rx_ring->rx_buf_len,
3993 DMA_FROM_DEVICE);
3994 IXGBE_RSC_CB(this)->dma = 0;
3995 IXGBE_RSC_CB(skb)->delay_unmap = false;
3996 }
3997 skb = skb->prev;
3998 dev_kfree_skb(this);
3999 } while (skb);
4000 }
4001 if (!rx_buffer_info->page)
4002 continue;
4003 if (rx_buffer_info->page_dma) {
4004 dma_unmap_page(dev, rx_buffer_info->page_dma,
4005 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4006 rx_buffer_info->page_dma = 0;
4007 }
4008 put_page(rx_buffer_info->page);
4009 rx_buffer_info->page = NULL;
4010 rx_buffer_info->page_offset = 0;
4011 }
4012
4013 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4014 memset(rx_ring->rx_buffer_info, 0, size);
4015
4016 /* Zero out the descriptor ring */
4017 memset(rx_ring->desc, 0, rx_ring->size);
4018
4019 rx_ring->next_to_clean = 0;
4020 rx_ring->next_to_use = 0;
4021 }
4022
4023 /**
4024 * ixgbe_clean_tx_ring - Free Tx Buffers
4025 * @tx_ring: ring to be cleaned
4026 **/
4027 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4028 {
4029 struct ixgbe_tx_buffer *tx_buffer_info;
4030 unsigned long size;
4031 u16 i;
4032
4033 /* ring already cleared, nothing to do */
4034 if (!tx_ring->tx_buffer_info)
4035 return;
4036
4037 /* Free all the Tx ring sk_buffs */
4038 for (i = 0; i < tx_ring->count; i++) {
4039 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4040 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4041 }
4042
4043 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4044 memset(tx_ring->tx_buffer_info, 0, size);
4045
4046 /* Zero out the descriptor ring */
4047 memset(tx_ring->desc, 0, tx_ring->size);
4048
4049 tx_ring->next_to_use = 0;
4050 tx_ring->next_to_clean = 0;
4051 }
4052
4053 /**
4054 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4055 * @adapter: board private structure
4056 **/
4057 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4058 {
4059 int i;
4060
4061 for (i = 0; i < adapter->num_rx_queues; i++)
4062 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4063 }
4064
4065 /**
4066 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4067 * @adapter: board private structure
4068 **/
4069 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4070 {
4071 int i;
4072
4073 for (i = 0; i < adapter->num_tx_queues; i++)
4074 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4075 }
4076
4077 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4078 {
4079 struct hlist_node *node, *node2;
4080 struct ixgbe_fdir_filter *filter;
4081
4082 spin_lock(&adapter->fdir_perfect_lock);
4083
4084 hlist_for_each_entry_safe(filter, node, node2,
4085 &adapter->fdir_filter_list, fdir_node) {
4086 hlist_del(&filter->fdir_node);
4087 kfree(filter);
4088 }
4089 adapter->fdir_filter_count = 0;
4090
4091 spin_unlock(&adapter->fdir_perfect_lock);
4092 }
4093
4094 void ixgbe_down(struct ixgbe_adapter *adapter)
4095 {
4096 struct net_device *netdev = adapter->netdev;
4097 struct ixgbe_hw *hw = &adapter->hw;
4098 u32 rxctrl;
4099 int i;
4100 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4101
4102 /* signal that we are down to the interrupt handler */
4103 set_bit(__IXGBE_DOWN, &adapter->state);
4104
4105 /* disable receives */
4106 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4107 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4108
4109 /* disable all enabled rx queues */
4110 for (i = 0; i < adapter->num_rx_queues; i++)
4111 /* this call also flushes the previous write */
4112 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4113
4114 usleep_range(10000, 20000);
4115
4116 netif_tx_stop_all_queues(netdev);
4117
4118 /* call carrier off first to avoid false dev_watchdog timeouts */
4119 netif_carrier_off(netdev);
4120 netif_tx_disable(netdev);
4121
4122 ixgbe_irq_disable(adapter);
4123
4124 ixgbe_napi_disable_all(adapter);
4125
4126 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4127 IXGBE_FLAG2_RESET_REQUESTED);
4128 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4129
4130 del_timer_sync(&adapter->service_timer);
4131
4132 /* disable receive for all VFs and wait one second */
4133 if (adapter->num_vfs) {
4134 /* ping all the active vfs to let them know we are going down */
4135 ixgbe_ping_all_vfs(adapter);
4136
4137 /* Disable all VFTE/VFRE TX/RX */
4138 ixgbe_disable_tx_rx(adapter);
4139
4140 /* Mark all the VFs as inactive */
4141 for (i = 0 ; i < adapter->num_vfs; i++)
4142 adapter->vfinfo[i].clear_to_send = 0;
4143 }
4144
4145 /* Cleanup the affinity_hint CPU mask memory and callback */
4146 for (i = 0; i < num_q_vectors; i++) {
4147 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4148 /* clear the affinity_mask in the IRQ descriptor */
4149 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4150 /* release the CPU mask memory */
4151 free_cpumask_var(q_vector->affinity_mask);
4152 }
4153
4154 /* disable transmits in the hardware now that interrupts are off */
4155 for (i = 0; i < adapter->num_tx_queues; i++) {
4156 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4157 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4158 }
4159
4160 /* Disable the Tx DMA engine on 82599 and X540 */
4161 switch (hw->mac.type) {
4162 case ixgbe_mac_82599EB:
4163 case ixgbe_mac_X540:
4164 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4165 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4166 ~IXGBE_DMATXCTL_TE));
4167 break;
4168 default:
4169 break;
4170 }
4171
4172 if (!pci_channel_offline(adapter->pdev))
4173 ixgbe_reset(adapter);
4174
4175 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4176 if (hw->mac.ops.disable_tx_laser &&
4177 ((hw->phy.multispeed_fiber) ||
4178 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4179 (hw->mac.type == ixgbe_mac_82599EB))))
4180 hw->mac.ops.disable_tx_laser(hw);
4181
4182 ixgbe_clean_all_tx_rings(adapter);
4183 ixgbe_clean_all_rx_rings(adapter);
4184
4185 #ifdef CONFIG_IXGBE_DCA
4186 /* since we reset the hardware DCA settings were cleared */
4187 ixgbe_setup_dca(adapter);
4188 #endif
4189 }
4190
4191 /**
4192 * ixgbe_poll - NAPI Rx polling callback
4193 * @napi: structure for representing this polling device
4194 * @budget: how many packets driver is allowed to clean
4195 *
4196 * This function is used for legacy and MSI, NAPI mode
4197 **/
4198 static int ixgbe_poll(struct napi_struct *napi, int budget)
4199 {
4200 struct ixgbe_q_vector *q_vector =
4201 container_of(napi, struct ixgbe_q_vector, napi);
4202 struct ixgbe_adapter *adapter = q_vector->adapter;
4203 int tx_clean_complete, work_done = 0;
4204
4205 #ifdef CONFIG_IXGBE_DCA
4206 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4207 ixgbe_update_dca(q_vector);
4208 #endif
4209
4210 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4211 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
4212
4213 if (!tx_clean_complete)
4214 work_done = budget;
4215
4216 /* If budget not fully consumed, exit the polling mode */
4217 if (work_done < budget) {
4218 napi_complete(napi);
4219 if (adapter->rx_itr_setting & 1)
4220 ixgbe_set_itr(q_vector);
4221 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4222 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
4223 }
4224 return work_done;
4225 }
4226
4227 /**
4228 * ixgbe_tx_timeout - Respond to a Tx Hang
4229 * @netdev: network interface device structure
4230 **/
4231 static void ixgbe_tx_timeout(struct net_device *netdev)
4232 {
4233 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4234
4235 /* Do the reset outside of interrupt context */
4236 ixgbe_tx_timeout_reset(adapter);
4237 }
4238
4239 /**
4240 * ixgbe_set_rss_queues: Allocate queues for RSS
4241 * @adapter: board private structure to initialize
4242 *
4243 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4244 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4245 *
4246 **/
4247 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4248 {
4249 bool ret = false;
4250 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4251
4252 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4253 f->mask = 0xF;
4254 adapter->num_rx_queues = f->indices;
4255 adapter->num_tx_queues = f->indices;
4256 ret = true;
4257 } else {
4258 ret = false;
4259 }
4260
4261 return ret;
4262 }
4263
4264 /**
4265 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4266 * @adapter: board private structure to initialize
4267 *
4268 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4269 * to the original CPU that initiated the Tx session. This runs in addition
4270 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4271 * Rx load across CPUs using RSS.
4272 *
4273 **/
4274 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4275 {
4276 bool ret = false;
4277 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4278
4279 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4280 f_fdir->mask = 0;
4281
4282 /* Flow Director must have RSS enabled */
4283 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4284 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4285 adapter->num_tx_queues = f_fdir->indices;
4286 adapter->num_rx_queues = f_fdir->indices;
4287 ret = true;
4288 } else {
4289 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4290 }
4291 return ret;
4292 }
4293
4294 #ifdef IXGBE_FCOE
4295 /**
4296 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4297 * @adapter: board private structure to initialize
4298 *
4299 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4300 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4301 * rx queues out of the max number of rx queues, instead, it is used as the
4302 * index of the first rx queue used by FCoE.
4303 *
4304 **/
4305 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4306 {
4307 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4308
4309 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4310 return false;
4311
4312 f->indices = min((int)num_online_cpus(), f->indices);
4313
4314 adapter->num_rx_queues = 1;
4315 adapter->num_tx_queues = 1;
4316
4317 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4318 e_info(probe, "FCoE enabled with RSS\n");
4319 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4320 ixgbe_set_fdir_queues(adapter);
4321 else
4322 ixgbe_set_rss_queues(adapter);
4323 }
4324
4325 /* adding FCoE rx rings to the end */
4326 f->mask = adapter->num_rx_queues;
4327 adapter->num_rx_queues += f->indices;
4328 adapter->num_tx_queues += f->indices;
4329
4330 return true;
4331 }
4332 #endif /* IXGBE_FCOE */
4333
4334 /* Artificial max queue cap per traffic class in DCB mode */
4335 #define DCB_QUEUE_CAP 8
4336
4337 #ifdef CONFIG_IXGBE_DCB
4338 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4339 {
4340 int per_tc_q, q, i, offset = 0;
4341 struct net_device *dev = adapter->netdev;
4342 int tcs = netdev_get_num_tc(dev);
4343
4344 if (!tcs)
4345 return false;
4346
4347 /* Map queue offset and counts onto allocated tx queues */
4348 per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4349 q = min((int)num_online_cpus(), per_tc_q);
4350
4351 for (i = 0; i < tcs; i++) {
4352 netdev_set_prio_tc_map(dev, i, i);
4353 netdev_set_tc_queue(dev, i, q, offset);
4354 offset += q;
4355 }
4356
4357 adapter->num_tx_queues = q * tcs;
4358 adapter->num_rx_queues = q * tcs;
4359
4360 #ifdef IXGBE_FCOE
4361 /* FCoE enabled queues require special configuration indexed
4362 * by feature specific indices and mask. Here we map FCoE
4363 * indices onto the DCB queue pairs allowing FCoE to own
4364 * configuration later.
4365 */
4366 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4367 int tc;
4368 struct ixgbe_ring_feature *f =
4369 &adapter->ring_feature[RING_F_FCOE];
4370
4371 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4372 f->indices = dev->tc_to_txq[tc].count;
4373 f->mask = dev->tc_to_txq[tc].offset;
4374 }
4375 #endif
4376
4377 return true;
4378 }
4379 #endif
4380
4381 /**
4382 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4383 * @adapter: board private structure to initialize
4384 *
4385 * IOV doesn't actually use anything, so just NAK the
4386 * request for now and let the other queue routines
4387 * figure out what to do.
4388 */
4389 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4390 {
4391 return false;
4392 }
4393
4394 /*
4395 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4396 * @adapter: board private structure to initialize
4397 *
4398 * This is the top level queue allocation routine. The order here is very
4399 * important, starting with the "most" number of features turned on at once,
4400 * and ending with the smallest set of features. This way large combinations
4401 * can be allocated if they're turned on, and smaller combinations are the
4402 * fallthrough conditions.
4403 *
4404 **/
4405 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4406 {
4407 /* Start with base case */
4408 adapter->num_rx_queues = 1;
4409 adapter->num_tx_queues = 1;
4410 adapter->num_rx_pools = adapter->num_rx_queues;
4411 adapter->num_rx_queues_per_pool = 1;
4412
4413 if (ixgbe_set_sriov_queues(adapter))
4414 goto done;
4415
4416 #ifdef CONFIG_IXGBE_DCB
4417 if (ixgbe_set_dcb_queues(adapter))
4418 goto done;
4419
4420 #endif
4421 #ifdef IXGBE_FCOE
4422 if (ixgbe_set_fcoe_queues(adapter))
4423 goto done;
4424
4425 #endif /* IXGBE_FCOE */
4426 if (ixgbe_set_fdir_queues(adapter))
4427 goto done;
4428
4429 if (ixgbe_set_rss_queues(adapter))
4430 goto done;
4431
4432 /* fallback to base case */
4433 adapter->num_rx_queues = 1;
4434 adapter->num_tx_queues = 1;
4435
4436 done:
4437 /* Notify the stack of the (possibly) reduced queue counts. */
4438 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4439 return netif_set_real_num_rx_queues(adapter->netdev,
4440 adapter->num_rx_queues);
4441 }
4442
4443 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4444 int vectors)
4445 {
4446 int err, vector_threshold;
4447
4448 /* We'll want at least 3 (vector_threshold):
4449 * 1) TxQ[0] Cleanup
4450 * 2) RxQ[0] Cleanup
4451 * 3) Other (Link Status Change, etc.)
4452 * 4) TCP Timer (optional)
4453 */
4454 vector_threshold = MIN_MSIX_COUNT;
4455
4456 /* The more we get, the more we will assign to Tx/Rx Cleanup
4457 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4458 * Right now, we simply care about how many we'll get; we'll
4459 * set them up later while requesting irq's.
4460 */
4461 while (vectors >= vector_threshold) {
4462 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4463 vectors);
4464 if (!err) /* Success in acquiring all requested vectors. */
4465 break;
4466 else if (err < 0)
4467 vectors = 0; /* Nasty failure, quit now */
4468 else /* err == number of vectors we should try again with */
4469 vectors = err;
4470 }
4471
4472 if (vectors < vector_threshold) {
4473 /* Can't allocate enough MSI-X interrupts? Oh well.
4474 * This just means we'll go with either a single MSI
4475 * vector or fall back to legacy interrupts.
4476 */
4477 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4478 "Unable to allocate MSI-X interrupts\n");
4479 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4480 kfree(adapter->msix_entries);
4481 adapter->msix_entries = NULL;
4482 } else {
4483 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4484 /*
4485 * Adjust for only the vectors we'll use, which is minimum
4486 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4487 * vectors we were allocated.
4488 */
4489 adapter->num_msix_vectors = min(vectors,
4490 adapter->max_msix_q_vectors + NON_Q_VECTORS);
4491 }
4492 }
4493
4494 /**
4495 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4496 * @adapter: board private structure to initialize
4497 *
4498 * Cache the descriptor ring offsets for RSS to the assigned rings.
4499 *
4500 **/
4501 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4502 {
4503 int i;
4504
4505 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4506 return false;
4507
4508 for (i = 0; i < adapter->num_rx_queues; i++)
4509 adapter->rx_ring[i]->reg_idx = i;
4510 for (i = 0; i < adapter->num_tx_queues; i++)
4511 adapter->tx_ring[i]->reg_idx = i;
4512
4513 return true;
4514 }
4515
4516 #ifdef CONFIG_IXGBE_DCB
4517
4518 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4519 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4520 unsigned int *tx, unsigned int *rx)
4521 {
4522 struct net_device *dev = adapter->netdev;
4523 struct ixgbe_hw *hw = &adapter->hw;
4524 u8 num_tcs = netdev_get_num_tc(dev);
4525
4526 *tx = 0;
4527 *rx = 0;
4528
4529 switch (hw->mac.type) {
4530 case ixgbe_mac_82598EB:
4531 *tx = tc << 2;
4532 *rx = tc << 3;
4533 break;
4534 case ixgbe_mac_82599EB:
4535 case ixgbe_mac_X540:
4536 if (num_tcs == 8) {
4537 if (tc < 3) {
4538 *tx = tc << 5;
4539 *rx = tc << 4;
4540 } else if (tc < 5) {
4541 *tx = ((tc + 2) << 4);
4542 *rx = tc << 4;
4543 } else if (tc < num_tcs) {
4544 *tx = ((tc + 8) << 3);
4545 *rx = tc << 4;
4546 }
4547 } else if (num_tcs == 4) {
4548 *rx = tc << 5;
4549 switch (tc) {
4550 case 0:
4551 *tx = 0;
4552 break;
4553 case 1:
4554 *tx = 64;
4555 break;
4556 case 2:
4557 *tx = 96;
4558 break;
4559 case 3:
4560 *tx = 112;
4561 break;
4562 default:
4563 break;
4564 }
4565 }
4566 break;
4567 default:
4568 break;
4569 }
4570 }
4571
4572 /**
4573 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4574 * @adapter: board private structure to initialize
4575 *
4576 * Cache the descriptor ring offsets for DCB to the assigned rings.
4577 *
4578 **/
4579 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4580 {
4581 struct net_device *dev = adapter->netdev;
4582 int i, j, k;
4583 u8 num_tcs = netdev_get_num_tc(dev);
4584
4585 if (!num_tcs)
4586 return false;
4587
4588 for (i = 0, k = 0; i < num_tcs; i++) {
4589 unsigned int tx_s, rx_s;
4590 u16 count = dev->tc_to_txq[i].count;
4591
4592 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4593 for (j = 0; j < count; j++, k++) {
4594 adapter->tx_ring[k]->reg_idx = tx_s + j;
4595 adapter->rx_ring[k]->reg_idx = rx_s + j;
4596 adapter->tx_ring[k]->dcb_tc = i;
4597 adapter->rx_ring[k]->dcb_tc = i;
4598 }
4599 }
4600
4601 return true;
4602 }
4603 #endif
4604
4605 /**
4606 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4607 * @adapter: board private structure to initialize
4608 *
4609 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4610 *
4611 **/
4612 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4613 {
4614 int i;
4615 bool ret = false;
4616
4617 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4618 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4619 for (i = 0; i < adapter->num_rx_queues; i++)
4620 adapter->rx_ring[i]->reg_idx = i;
4621 for (i = 0; i < adapter->num_tx_queues; i++)
4622 adapter->tx_ring[i]->reg_idx = i;
4623 ret = true;
4624 }
4625
4626 return ret;
4627 }
4628
4629 #ifdef IXGBE_FCOE
4630 /**
4631 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4632 * @adapter: board private structure to initialize
4633 *
4634 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4635 *
4636 */
4637 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4638 {
4639 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4640 int i;
4641 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4642
4643 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4644 return false;
4645
4646 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4647 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4648 ixgbe_cache_ring_fdir(adapter);
4649 else
4650 ixgbe_cache_ring_rss(adapter);
4651
4652 fcoe_rx_i = f->mask;
4653 fcoe_tx_i = f->mask;
4654 }
4655 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4656 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4657 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4658 }
4659 return true;
4660 }
4661
4662 #endif /* IXGBE_FCOE */
4663 /**
4664 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4665 * @adapter: board private structure to initialize
4666 *
4667 * SR-IOV doesn't use any descriptor rings but changes the default if
4668 * no other mapping is used.
4669 *
4670 */
4671 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4672 {
4673 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4674 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4675 if (adapter->num_vfs)
4676 return true;
4677 else
4678 return false;
4679 }
4680
4681 /**
4682 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4683 * @adapter: board private structure to initialize
4684 *
4685 * Once we know the feature-set enabled for the device, we'll cache
4686 * the register offset the descriptor ring is assigned to.
4687 *
4688 * Note, the order the various feature calls is important. It must start with
4689 * the "most" features enabled at the same time, then trickle down to the
4690 * least amount of features turned on at once.
4691 **/
4692 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4693 {
4694 /* start with default case */
4695 adapter->rx_ring[0]->reg_idx = 0;
4696 adapter->tx_ring[0]->reg_idx = 0;
4697
4698 if (ixgbe_cache_ring_sriov(adapter))
4699 return;
4700
4701 #ifdef CONFIG_IXGBE_DCB
4702 if (ixgbe_cache_ring_dcb(adapter))
4703 return;
4704 #endif
4705
4706 #ifdef IXGBE_FCOE
4707 if (ixgbe_cache_ring_fcoe(adapter))
4708 return;
4709 #endif /* IXGBE_FCOE */
4710
4711 if (ixgbe_cache_ring_fdir(adapter))
4712 return;
4713
4714 if (ixgbe_cache_ring_rss(adapter))
4715 return;
4716 }
4717
4718 /**
4719 * ixgbe_alloc_queues - Allocate memory for all rings
4720 * @adapter: board private structure to initialize
4721 *
4722 * We allocate one ring per queue at run-time since we don't know the
4723 * number of queues at compile-time. The polling_netdev array is
4724 * intended for Multiqueue, but should work fine with a single queue.
4725 **/
4726 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4727 {
4728 int rx = 0, tx = 0, nid = adapter->node;
4729
4730 if (nid < 0 || !node_online(nid))
4731 nid = first_online_node;
4732
4733 for (; tx < adapter->num_tx_queues; tx++) {
4734 struct ixgbe_ring *ring;
4735
4736 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4737 if (!ring)
4738 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4739 if (!ring)
4740 goto err_allocation;
4741 ring->count = adapter->tx_ring_count;
4742 ring->queue_index = tx;
4743 ring->numa_node = nid;
4744 ring->dev = &adapter->pdev->dev;
4745 ring->netdev = adapter->netdev;
4746
4747 adapter->tx_ring[tx] = ring;
4748 }
4749
4750 for (; rx < adapter->num_rx_queues; rx++) {
4751 struct ixgbe_ring *ring;
4752
4753 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4754 if (!ring)
4755 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4756 if (!ring)
4757 goto err_allocation;
4758 ring->count = adapter->rx_ring_count;
4759 ring->queue_index = rx;
4760 ring->numa_node = nid;
4761 ring->dev = &adapter->pdev->dev;
4762 ring->netdev = adapter->netdev;
4763
4764 adapter->rx_ring[rx] = ring;
4765 }
4766
4767 ixgbe_cache_ring_register(adapter);
4768
4769 return 0;
4770
4771 err_allocation:
4772 while (tx)
4773 kfree(adapter->tx_ring[--tx]);
4774
4775 while (rx)
4776 kfree(adapter->rx_ring[--rx]);
4777 return -ENOMEM;
4778 }
4779
4780 /**
4781 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4782 * @adapter: board private structure to initialize
4783 *
4784 * Attempt to configure the interrupts using the best available
4785 * capabilities of the hardware and the kernel.
4786 **/
4787 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4788 {
4789 struct ixgbe_hw *hw = &adapter->hw;
4790 int err = 0;
4791 int vector, v_budget;
4792
4793 /*
4794 * It's easy to be greedy for MSI-X vectors, but it really
4795 * doesn't do us much good if we have a lot more vectors
4796 * than CPU's. So let's be conservative and only ask for
4797 * (roughly) the same number of vectors as there are CPU's.
4798 */
4799 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4800 (int)num_online_cpus()) + NON_Q_VECTORS;
4801
4802 /*
4803 * At the same time, hardware can only support a maximum of
4804 * hw.mac->max_msix_vectors vectors. With features
4805 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4806 * descriptor queues supported by our device. Thus, we cap it off in
4807 * those rare cases where the cpu count also exceeds our vector limit.
4808 */
4809 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4810
4811 /* A failure in MSI-X entry allocation isn't fatal, but it does
4812 * mean we disable MSI-X capabilities of the adapter. */
4813 adapter->msix_entries = kcalloc(v_budget,
4814 sizeof(struct msix_entry), GFP_KERNEL);
4815 if (adapter->msix_entries) {
4816 for (vector = 0; vector < v_budget; vector++)
4817 adapter->msix_entries[vector].entry = vector;
4818
4819 ixgbe_acquire_msix_vectors(adapter, v_budget);
4820
4821 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4822 goto out;
4823 }
4824
4825 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4826 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4827 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4828 e_err(probe,
4829 "ATR is not supported while multiple "
4830 "queues are disabled. Disabling Flow Director\n");
4831 }
4832 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4833 adapter->atr_sample_rate = 0;
4834 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4835 ixgbe_disable_sriov(adapter);
4836
4837 err = ixgbe_set_num_queues(adapter);
4838 if (err)
4839 return err;
4840
4841 err = pci_enable_msi(adapter->pdev);
4842 if (!err) {
4843 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4844 } else {
4845 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4846 "Unable to allocate MSI interrupt, "
4847 "falling back to legacy. Error: %d\n", err);
4848 /* reset err */
4849 err = 0;
4850 }
4851
4852 out:
4853 return err;
4854 }
4855
4856 /**
4857 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4858 * @adapter: board private structure to initialize
4859 *
4860 * We allocate one q_vector per queue interrupt. If allocation fails we
4861 * return -ENOMEM.
4862 **/
4863 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4864 {
4865 int q_idx, num_q_vectors;
4866 struct ixgbe_q_vector *q_vector;
4867 int (*poll)(struct napi_struct *, int);
4868
4869 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4870 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4871 poll = &ixgbe_clean_rxtx_many;
4872 } else {
4873 num_q_vectors = 1;
4874 poll = &ixgbe_poll;
4875 }
4876
4877 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4878 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4879 GFP_KERNEL, adapter->node);
4880 if (!q_vector)
4881 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4882 GFP_KERNEL);
4883 if (!q_vector)
4884 goto err_out;
4885 q_vector->adapter = adapter;
4886 if (q_vector->tx.count && !q_vector->rx.count)
4887 q_vector->eitr = adapter->tx_eitr_param;
4888 else
4889 q_vector->eitr = adapter->rx_eitr_param;
4890 q_vector->v_idx = q_idx;
4891 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4892 adapter->q_vector[q_idx] = q_vector;
4893 }
4894
4895 return 0;
4896
4897 err_out:
4898 while (q_idx) {
4899 q_idx--;
4900 q_vector = adapter->q_vector[q_idx];
4901 netif_napi_del(&q_vector->napi);
4902 kfree(q_vector);
4903 adapter->q_vector[q_idx] = NULL;
4904 }
4905 return -ENOMEM;
4906 }
4907
4908 /**
4909 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4910 * @adapter: board private structure to initialize
4911 *
4912 * This function frees the memory allocated to the q_vectors. In addition if
4913 * NAPI is enabled it will delete any references to the NAPI struct prior
4914 * to freeing the q_vector.
4915 **/
4916 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4917 {
4918 int q_idx, num_q_vectors;
4919
4920 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4921 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4922 else
4923 num_q_vectors = 1;
4924
4925 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4926 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4927 adapter->q_vector[q_idx] = NULL;
4928 netif_napi_del(&q_vector->napi);
4929 kfree(q_vector);
4930 }
4931 }
4932
4933 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4934 {
4935 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4936 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4937 pci_disable_msix(adapter->pdev);
4938 kfree(adapter->msix_entries);
4939 adapter->msix_entries = NULL;
4940 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4941 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4942 pci_disable_msi(adapter->pdev);
4943 }
4944 }
4945
4946 /**
4947 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4948 * @adapter: board private structure to initialize
4949 *
4950 * We determine which interrupt scheme to use based on...
4951 * - Kernel support (MSI, MSI-X)
4952 * - which can be user-defined (via MODULE_PARAM)
4953 * - Hardware queue count (num_*_queues)
4954 * - defined by miscellaneous hardware support/features (RSS, etc.)
4955 **/
4956 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4957 {
4958 int err;
4959
4960 /* Number of supported queues */
4961 err = ixgbe_set_num_queues(adapter);
4962 if (err)
4963 return err;
4964
4965 err = ixgbe_set_interrupt_capability(adapter);
4966 if (err) {
4967 e_dev_err("Unable to setup interrupt capabilities\n");
4968 goto err_set_interrupt;
4969 }
4970
4971 err = ixgbe_alloc_q_vectors(adapter);
4972 if (err) {
4973 e_dev_err("Unable to allocate memory for queue vectors\n");
4974 goto err_alloc_q_vectors;
4975 }
4976
4977 err = ixgbe_alloc_queues(adapter);
4978 if (err) {
4979 e_dev_err("Unable to allocate memory for queues\n");
4980 goto err_alloc_queues;
4981 }
4982
4983 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4984 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4985 adapter->num_rx_queues, adapter->num_tx_queues);
4986
4987 set_bit(__IXGBE_DOWN, &adapter->state);
4988
4989 return 0;
4990
4991 err_alloc_queues:
4992 ixgbe_free_q_vectors(adapter);
4993 err_alloc_q_vectors:
4994 ixgbe_reset_interrupt_capability(adapter);
4995 err_set_interrupt:
4996 return err;
4997 }
4998
4999 /**
5000 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5001 * @adapter: board private structure to clear interrupt scheme on
5002 *
5003 * We go through and clear interrupt specific resources and reset the structure
5004 * to pre-load conditions
5005 **/
5006 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5007 {
5008 int i;
5009
5010 for (i = 0; i < adapter->num_tx_queues; i++) {
5011 kfree(adapter->tx_ring[i]);
5012 adapter->tx_ring[i] = NULL;
5013 }
5014 for (i = 0; i < adapter->num_rx_queues; i++) {
5015 struct ixgbe_ring *ring = adapter->rx_ring[i];
5016
5017 /* ixgbe_get_stats64() might access this ring, we must wait
5018 * a grace period before freeing it.
5019 */
5020 kfree_rcu(ring, rcu);
5021 adapter->rx_ring[i] = NULL;
5022 }
5023
5024 adapter->num_tx_queues = 0;
5025 adapter->num_rx_queues = 0;
5026
5027 ixgbe_free_q_vectors(adapter);
5028 ixgbe_reset_interrupt_capability(adapter);
5029 }
5030
5031 /**
5032 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5033 * @adapter: board private structure to initialize
5034 *
5035 * ixgbe_sw_init initializes the Adapter private data structure.
5036 * Fields are initialized based on PCI device information and
5037 * OS network device settings (MTU size).
5038 **/
5039 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5040 {
5041 struct ixgbe_hw *hw = &adapter->hw;
5042 struct pci_dev *pdev = adapter->pdev;
5043 struct net_device *dev = adapter->netdev;
5044 unsigned int rss;
5045 #ifdef CONFIG_IXGBE_DCB
5046 int j;
5047 struct tc_configuration *tc;
5048 #endif
5049 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5050
5051 /* PCI config space info */
5052
5053 hw->vendor_id = pdev->vendor;
5054 hw->device_id = pdev->device;
5055 hw->revision_id = pdev->revision;
5056 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5057 hw->subsystem_device_id = pdev->subsystem_device;
5058
5059 /* Set capability flags */
5060 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5061 adapter->ring_feature[RING_F_RSS].indices = rss;
5062 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
5063 switch (hw->mac.type) {
5064 case ixgbe_mac_82598EB:
5065 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5066 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5067 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
5068 break;
5069 case ixgbe_mac_82599EB:
5070 case ixgbe_mac_X540:
5071 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
5072 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5073 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5074 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5075 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5076 /* Flow Director hash filters enabled */
5077 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5078 adapter->atr_sample_rate = 20;
5079 adapter->ring_feature[RING_F_FDIR].indices =
5080 IXGBE_MAX_FDIR_INDICES;
5081 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5082 #ifdef IXGBE_FCOE
5083 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5084 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5085 adapter->ring_feature[RING_F_FCOE].indices = 0;
5086 #ifdef CONFIG_IXGBE_DCB
5087 /* Default traffic class to use for FCoE */
5088 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5089 #endif
5090 #endif /* IXGBE_FCOE */
5091 break;
5092 default:
5093 break;
5094 }
5095
5096 /* n-tuple support exists, always init our spinlock */
5097 spin_lock_init(&adapter->fdir_perfect_lock);
5098
5099 #ifdef CONFIG_IXGBE_DCB
5100 /* Configure DCB traffic classes */
5101 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5102 tc = &adapter->dcb_cfg.tc_config[j];
5103 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5104 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5105 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5106 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5107 tc->dcb_pfc = pfc_disabled;
5108 }
5109 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5110 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5111 adapter->dcb_cfg.pfc_mode_enable = false;
5112 adapter->dcb_set_bitmap = 0x00;
5113 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5114 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5115 MAX_TRAFFIC_CLASS);
5116
5117 #endif
5118
5119 /* default flow control settings */
5120 hw->fc.requested_mode = ixgbe_fc_full;
5121 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
5122 #ifdef CONFIG_DCB
5123 adapter->last_lfc_mode = hw->fc.current_mode;
5124 #endif
5125 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5126 hw->fc.low_water = FC_LOW_WATER(max_frame);
5127 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5128 hw->fc.send_xon = true;
5129 hw->fc.disable_fc_autoneg = false;
5130
5131 /* enable itr by default in dynamic mode */
5132 adapter->rx_itr_setting = 1;
5133 adapter->rx_eitr_param = 20000;
5134 adapter->tx_itr_setting = 1;
5135 adapter->tx_eitr_param = 10000;
5136
5137 /* set defaults for eitr in MegaBytes */
5138 adapter->eitr_low = 10;
5139 adapter->eitr_high = 20;
5140
5141 /* set default ring sizes */
5142 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5143 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5144
5145 /* set default work limits */
5146 adapter->tx_work_limit = adapter->tx_ring_count;
5147
5148 /* initialize eeprom parameters */
5149 if (ixgbe_init_eeprom_params_generic(hw)) {
5150 e_dev_err("EEPROM initialization failed\n");
5151 return -EIO;
5152 }
5153
5154 /* enable rx csum by default */
5155 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5156
5157 /* get assigned NUMA node */
5158 adapter->node = dev_to_node(&pdev->dev);
5159
5160 set_bit(__IXGBE_DOWN, &adapter->state);
5161
5162 return 0;
5163 }
5164
5165 /**
5166 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5167 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5168 *
5169 * Return 0 on success, negative on failure
5170 **/
5171 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5172 {
5173 struct device *dev = tx_ring->dev;
5174 int size;
5175
5176 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5177 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
5178 if (!tx_ring->tx_buffer_info)
5179 tx_ring->tx_buffer_info = vzalloc(size);
5180 if (!tx_ring->tx_buffer_info)
5181 goto err;
5182
5183 /* round up to nearest 4K */
5184 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5185 tx_ring->size = ALIGN(tx_ring->size, 4096);
5186
5187 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5188 &tx_ring->dma, GFP_KERNEL);
5189 if (!tx_ring->desc)
5190 goto err;
5191
5192 tx_ring->next_to_use = 0;
5193 tx_ring->next_to_clean = 0;
5194 return 0;
5195
5196 err:
5197 vfree(tx_ring->tx_buffer_info);
5198 tx_ring->tx_buffer_info = NULL;
5199 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5200 return -ENOMEM;
5201 }
5202
5203 /**
5204 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5205 * @adapter: board private structure
5206 *
5207 * If this function returns with an error, then it's possible one or
5208 * more of the rings is populated (while the rest are not). It is the
5209 * callers duty to clean those orphaned rings.
5210 *
5211 * Return 0 on success, negative on failure
5212 **/
5213 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5214 {
5215 int i, err = 0;
5216
5217 for (i = 0; i < adapter->num_tx_queues; i++) {
5218 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5219 if (!err)
5220 continue;
5221 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5222 break;
5223 }
5224
5225 return err;
5226 }
5227
5228 /**
5229 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5230 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5231 *
5232 * Returns 0 on success, negative on failure
5233 **/
5234 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5235 {
5236 struct device *dev = rx_ring->dev;
5237 int size;
5238
5239 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5240 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5241 if (!rx_ring->rx_buffer_info)
5242 rx_ring->rx_buffer_info = vzalloc(size);
5243 if (!rx_ring->rx_buffer_info)
5244 goto err;
5245
5246 /* Round up to nearest 4K */
5247 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5248 rx_ring->size = ALIGN(rx_ring->size, 4096);
5249
5250 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5251 &rx_ring->dma, GFP_KERNEL);
5252
5253 if (!rx_ring->desc)
5254 goto err;
5255
5256 rx_ring->next_to_clean = 0;
5257 rx_ring->next_to_use = 0;
5258
5259 return 0;
5260 err:
5261 vfree(rx_ring->rx_buffer_info);
5262 rx_ring->rx_buffer_info = NULL;
5263 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5264 return -ENOMEM;
5265 }
5266
5267 /**
5268 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5269 * @adapter: board private structure
5270 *
5271 * If this function returns with an error, then it's possible one or
5272 * more of the rings is populated (while the rest are not). It is the
5273 * callers duty to clean those orphaned rings.
5274 *
5275 * Return 0 on success, negative on failure
5276 **/
5277 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5278 {
5279 int i, err = 0;
5280
5281 for (i = 0; i < adapter->num_rx_queues; i++) {
5282 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5283 if (!err)
5284 continue;
5285 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5286 break;
5287 }
5288
5289 return err;
5290 }
5291
5292 /**
5293 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5294 * @tx_ring: Tx descriptor ring for a specific queue
5295 *
5296 * Free all transmit software resources
5297 **/
5298 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5299 {
5300 ixgbe_clean_tx_ring(tx_ring);
5301
5302 vfree(tx_ring->tx_buffer_info);
5303 tx_ring->tx_buffer_info = NULL;
5304
5305 /* if not set, then don't free */
5306 if (!tx_ring->desc)
5307 return;
5308
5309 dma_free_coherent(tx_ring->dev, tx_ring->size,
5310 tx_ring->desc, tx_ring->dma);
5311
5312 tx_ring->desc = NULL;
5313 }
5314
5315 /**
5316 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5317 * @adapter: board private structure
5318 *
5319 * Free all transmit software resources
5320 **/
5321 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5322 {
5323 int i;
5324
5325 for (i = 0; i < adapter->num_tx_queues; i++)
5326 if (adapter->tx_ring[i]->desc)
5327 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5328 }
5329
5330 /**
5331 * ixgbe_free_rx_resources - Free Rx Resources
5332 * @rx_ring: ring to clean the resources from
5333 *
5334 * Free all receive software resources
5335 **/
5336 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5337 {
5338 ixgbe_clean_rx_ring(rx_ring);
5339
5340 vfree(rx_ring->rx_buffer_info);
5341 rx_ring->rx_buffer_info = NULL;
5342
5343 /* if not set, then don't free */
5344 if (!rx_ring->desc)
5345 return;
5346
5347 dma_free_coherent(rx_ring->dev, rx_ring->size,
5348 rx_ring->desc, rx_ring->dma);
5349
5350 rx_ring->desc = NULL;
5351 }
5352
5353 /**
5354 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5355 * @adapter: board private structure
5356 *
5357 * Free all receive software resources
5358 **/
5359 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5360 {
5361 int i;
5362
5363 for (i = 0; i < adapter->num_rx_queues; i++)
5364 if (adapter->rx_ring[i]->desc)
5365 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5366 }
5367
5368 /**
5369 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5370 * @netdev: network interface device structure
5371 * @new_mtu: new value for maximum frame size
5372 *
5373 * Returns 0 on success, negative on failure
5374 **/
5375 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5376 {
5377 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5378 struct ixgbe_hw *hw = &adapter->hw;
5379 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5380
5381 /* MTU < 68 is an error and causes problems on some kernels */
5382 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5383 hw->mac.type != ixgbe_mac_X540) {
5384 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5385 return -EINVAL;
5386 } else {
5387 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5388 return -EINVAL;
5389 }
5390
5391 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5392 /* must set new MTU before calling down or up */
5393 netdev->mtu = new_mtu;
5394
5395 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5396 hw->fc.low_water = FC_LOW_WATER(max_frame);
5397
5398 if (netif_running(netdev))
5399 ixgbe_reinit_locked(adapter);
5400
5401 return 0;
5402 }
5403
5404 /**
5405 * ixgbe_open - Called when a network interface is made active
5406 * @netdev: network interface device structure
5407 *
5408 * Returns 0 on success, negative value on failure
5409 *
5410 * The open entry point is called when a network interface is made
5411 * active by the system (IFF_UP). At this point all resources needed
5412 * for transmit and receive operations are allocated, the interrupt
5413 * handler is registered with the OS, the watchdog timer is started,
5414 * and the stack is notified that the interface is ready.
5415 **/
5416 static int ixgbe_open(struct net_device *netdev)
5417 {
5418 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5419 int err;
5420
5421 /* disallow open during test */
5422 if (test_bit(__IXGBE_TESTING, &adapter->state))
5423 return -EBUSY;
5424
5425 netif_carrier_off(netdev);
5426
5427 /* allocate transmit descriptors */
5428 err = ixgbe_setup_all_tx_resources(adapter);
5429 if (err)
5430 goto err_setup_tx;
5431
5432 /* allocate receive descriptors */
5433 err = ixgbe_setup_all_rx_resources(adapter);
5434 if (err)
5435 goto err_setup_rx;
5436
5437 ixgbe_configure(adapter);
5438
5439 err = ixgbe_request_irq(adapter);
5440 if (err)
5441 goto err_req_irq;
5442
5443 err = ixgbe_up_complete(adapter);
5444 if (err)
5445 goto err_up;
5446
5447 netif_tx_start_all_queues(netdev);
5448
5449 return 0;
5450
5451 err_up:
5452 ixgbe_release_hw_control(adapter);
5453 ixgbe_free_irq(adapter);
5454 err_req_irq:
5455 err_setup_rx:
5456 ixgbe_free_all_rx_resources(adapter);
5457 err_setup_tx:
5458 ixgbe_free_all_tx_resources(adapter);
5459 ixgbe_reset(adapter);
5460
5461 return err;
5462 }
5463
5464 /**
5465 * ixgbe_close - Disables a network interface
5466 * @netdev: network interface device structure
5467 *
5468 * Returns 0, this is not allowed to fail
5469 *
5470 * The close entry point is called when an interface is de-activated
5471 * by the OS. The hardware is still under the drivers control, but
5472 * needs to be disabled. A global MAC reset is issued to stop the
5473 * hardware, and all transmit and receive resources are freed.
5474 **/
5475 static int ixgbe_close(struct net_device *netdev)
5476 {
5477 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5478
5479 ixgbe_down(adapter);
5480 ixgbe_free_irq(adapter);
5481
5482 ixgbe_fdir_filter_exit(adapter);
5483
5484 ixgbe_free_all_tx_resources(adapter);
5485 ixgbe_free_all_rx_resources(adapter);
5486
5487 ixgbe_release_hw_control(adapter);
5488
5489 return 0;
5490 }
5491
5492 #ifdef CONFIG_PM
5493 static int ixgbe_resume(struct pci_dev *pdev)
5494 {
5495 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5496 struct net_device *netdev = adapter->netdev;
5497 u32 err;
5498
5499 pci_set_power_state(pdev, PCI_D0);
5500 pci_restore_state(pdev);
5501 /*
5502 * pci_restore_state clears dev->state_saved so call
5503 * pci_save_state to restore it.
5504 */
5505 pci_save_state(pdev);
5506
5507 err = pci_enable_device_mem(pdev);
5508 if (err) {
5509 e_dev_err("Cannot enable PCI device from suspend\n");
5510 return err;
5511 }
5512 pci_set_master(pdev);
5513
5514 pci_wake_from_d3(pdev, false);
5515
5516 err = ixgbe_init_interrupt_scheme(adapter);
5517 if (err) {
5518 e_dev_err("Cannot initialize interrupts for device\n");
5519 return err;
5520 }
5521
5522 ixgbe_reset(adapter);
5523
5524 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5525
5526 if (netif_running(netdev)) {
5527 err = ixgbe_open(netdev);
5528 if (err)
5529 return err;
5530 }
5531
5532 netif_device_attach(netdev);
5533
5534 return 0;
5535 }
5536 #endif /* CONFIG_PM */
5537
5538 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5539 {
5540 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5541 struct net_device *netdev = adapter->netdev;
5542 struct ixgbe_hw *hw = &adapter->hw;
5543 u32 ctrl, fctrl;
5544 u32 wufc = adapter->wol;
5545 #ifdef CONFIG_PM
5546 int retval = 0;
5547 #endif
5548
5549 netif_device_detach(netdev);
5550
5551 if (netif_running(netdev)) {
5552 ixgbe_down(adapter);
5553 ixgbe_free_irq(adapter);
5554 ixgbe_free_all_tx_resources(adapter);
5555 ixgbe_free_all_rx_resources(adapter);
5556 }
5557
5558 ixgbe_clear_interrupt_scheme(adapter);
5559 #ifdef CONFIG_DCB
5560 kfree(adapter->ixgbe_ieee_pfc);
5561 kfree(adapter->ixgbe_ieee_ets);
5562 #endif
5563
5564 #ifdef CONFIG_PM
5565 retval = pci_save_state(pdev);
5566 if (retval)
5567 return retval;
5568
5569 #endif
5570 if (wufc) {
5571 ixgbe_set_rx_mode(netdev);
5572
5573 /* turn on all-multi mode if wake on multicast is enabled */
5574 if (wufc & IXGBE_WUFC_MC) {
5575 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5576 fctrl |= IXGBE_FCTRL_MPE;
5577 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5578 }
5579
5580 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5581 ctrl |= IXGBE_CTRL_GIO_DIS;
5582 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5583
5584 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5585 } else {
5586 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5587 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5588 }
5589
5590 switch (hw->mac.type) {
5591 case ixgbe_mac_82598EB:
5592 pci_wake_from_d3(pdev, false);
5593 break;
5594 case ixgbe_mac_82599EB:
5595 case ixgbe_mac_X540:
5596 pci_wake_from_d3(pdev, !!wufc);
5597 break;
5598 default:
5599 break;
5600 }
5601
5602 *enable_wake = !!wufc;
5603
5604 ixgbe_release_hw_control(adapter);
5605
5606 pci_disable_device(pdev);
5607
5608 return 0;
5609 }
5610
5611 #ifdef CONFIG_PM
5612 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5613 {
5614 int retval;
5615 bool wake;
5616
5617 retval = __ixgbe_shutdown(pdev, &wake);
5618 if (retval)
5619 return retval;
5620
5621 if (wake) {
5622 pci_prepare_to_sleep(pdev);
5623 } else {
5624 pci_wake_from_d3(pdev, false);
5625 pci_set_power_state(pdev, PCI_D3hot);
5626 }
5627
5628 return 0;
5629 }
5630 #endif /* CONFIG_PM */
5631
5632 static void ixgbe_shutdown(struct pci_dev *pdev)
5633 {
5634 bool wake;
5635
5636 __ixgbe_shutdown(pdev, &wake);
5637
5638 if (system_state == SYSTEM_POWER_OFF) {
5639 pci_wake_from_d3(pdev, wake);
5640 pci_set_power_state(pdev, PCI_D3hot);
5641 }
5642 }
5643
5644 /**
5645 * ixgbe_update_stats - Update the board statistics counters.
5646 * @adapter: board private structure
5647 **/
5648 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5649 {
5650 struct net_device *netdev = adapter->netdev;
5651 struct ixgbe_hw *hw = &adapter->hw;
5652 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5653 u64 total_mpc = 0;
5654 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5655 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5656 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5657 u64 bytes = 0, packets = 0;
5658
5659 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5660 test_bit(__IXGBE_RESETTING, &adapter->state))
5661 return;
5662
5663 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5664 u64 rsc_count = 0;
5665 u64 rsc_flush = 0;
5666 for (i = 0; i < 16; i++)
5667 adapter->hw_rx_no_dma_resources +=
5668 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5669 for (i = 0; i < adapter->num_rx_queues; i++) {
5670 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5671 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5672 }
5673 adapter->rsc_total_count = rsc_count;
5674 adapter->rsc_total_flush = rsc_flush;
5675 }
5676
5677 for (i = 0; i < adapter->num_rx_queues; i++) {
5678 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5679 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5680 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5681 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5682 bytes += rx_ring->stats.bytes;
5683 packets += rx_ring->stats.packets;
5684 }
5685 adapter->non_eop_descs = non_eop_descs;
5686 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5687 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5688 netdev->stats.rx_bytes = bytes;
5689 netdev->stats.rx_packets = packets;
5690
5691 bytes = 0;
5692 packets = 0;
5693 /* gather some stats to the adapter struct that are per queue */
5694 for (i = 0; i < adapter->num_tx_queues; i++) {
5695 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5696 restart_queue += tx_ring->tx_stats.restart_queue;
5697 tx_busy += tx_ring->tx_stats.tx_busy;
5698 bytes += tx_ring->stats.bytes;
5699 packets += tx_ring->stats.packets;
5700 }
5701 adapter->restart_queue = restart_queue;
5702 adapter->tx_busy = tx_busy;
5703 netdev->stats.tx_bytes = bytes;
5704 netdev->stats.tx_packets = packets;
5705
5706 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5707 for (i = 0; i < 8; i++) {
5708 /* for packet buffers not used, the register should read 0 */
5709 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5710 missed_rx += mpc;
5711 hwstats->mpc[i] += mpc;
5712 total_mpc += hwstats->mpc[i];
5713 if (hw->mac.type == ixgbe_mac_82598EB)
5714 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5715 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5716 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5717 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5718 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5719 switch (hw->mac.type) {
5720 case ixgbe_mac_82598EB:
5721 hwstats->pxonrxc[i] +=
5722 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5723 break;
5724 case ixgbe_mac_82599EB:
5725 case ixgbe_mac_X540:
5726 hwstats->pxonrxc[i] +=
5727 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5728 break;
5729 default:
5730 break;
5731 }
5732 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5733 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5734 }
5735 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5736 /* work around hardware counting issue */
5737 hwstats->gprc -= missed_rx;
5738
5739 ixgbe_update_xoff_received(adapter);
5740
5741 /* 82598 hardware only has a 32 bit counter in the high register */
5742 switch (hw->mac.type) {
5743 case ixgbe_mac_82598EB:
5744 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5745 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5746 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5747 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5748 break;
5749 case ixgbe_mac_X540:
5750 /* OS2BMC stats are X540 only*/
5751 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5752 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5753 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5754 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5755 case ixgbe_mac_82599EB:
5756 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5757 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5758 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5759 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5760 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5761 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5762 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5763 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5764 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5765 #ifdef IXGBE_FCOE
5766 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5767 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5768 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5769 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5770 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5771 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5772 #endif /* IXGBE_FCOE */
5773 break;
5774 default:
5775 break;
5776 }
5777 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5778 hwstats->bprc += bprc;
5779 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5780 if (hw->mac.type == ixgbe_mac_82598EB)
5781 hwstats->mprc -= bprc;
5782 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5783 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5784 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5785 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5786 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5787 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5788 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5789 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5790 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5791 hwstats->lxontxc += lxon;
5792 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5793 hwstats->lxofftxc += lxoff;
5794 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5795 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5796 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5797 /*
5798 * 82598 errata - tx of flow control packets is included in tx counters
5799 */
5800 xon_off_tot = lxon + lxoff;
5801 hwstats->gptc -= xon_off_tot;
5802 hwstats->mptc -= xon_off_tot;
5803 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5804 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5805 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5806 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5807 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5808 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5809 hwstats->ptc64 -= xon_off_tot;
5810 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5811 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5812 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5813 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5814 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5815 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5816
5817 /* Fill out the OS statistics structure */
5818 netdev->stats.multicast = hwstats->mprc;
5819
5820 /* Rx Errors */
5821 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5822 netdev->stats.rx_dropped = 0;
5823 netdev->stats.rx_length_errors = hwstats->rlec;
5824 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5825 netdev->stats.rx_missed_errors = total_mpc;
5826 }
5827
5828 /**
5829 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5830 * @adapter - pointer to the device adapter structure
5831 **/
5832 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5833 {
5834 struct ixgbe_hw *hw = &adapter->hw;
5835 int i;
5836
5837 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5838 return;
5839
5840 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5841
5842 /* if interface is down do nothing */
5843 if (test_bit(__IXGBE_DOWN, &adapter->state))
5844 return;
5845
5846 /* do nothing if we are not using signature filters */
5847 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5848 return;
5849
5850 adapter->fdir_overflow++;
5851
5852 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5853 for (i = 0; i < adapter->num_tx_queues; i++)
5854 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5855 &(adapter->tx_ring[i]->state));
5856 /* re-enable flow director interrupts */
5857 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5858 } else {
5859 e_err(probe, "failed to finish FDIR re-initialization, "
5860 "ignored adding FDIR ATR filters\n");
5861 }
5862 }
5863
5864 /**
5865 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5866 * @adapter - pointer to the device adapter structure
5867 *
5868 * This function serves two purposes. First it strobes the interrupt lines
5869 * in order to make certain interrupts are occuring. Secondly it sets the
5870 * bits needed to check for TX hangs. As a result we should immediately
5871 * determine if a hang has occured.
5872 */
5873 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5874 {
5875 struct ixgbe_hw *hw = &adapter->hw;
5876 u64 eics = 0;
5877 int i;
5878
5879 /* If we're down or resetting, just bail */
5880 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5881 test_bit(__IXGBE_RESETTING, &adapter->state))
5882 return;
5883
5884 /* Force detection of hung controller */
5885 if (netif_carrier_ok(adapter->netdev)) {
5886 for (i = 0; i < adapter->num_tx_queues; i++)
5887 set_check_for_tx_hang(adapter->tx_ring[i]);
5888 }
5889
5890 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5891 /*
5892 * for legacy and MSI interrupts don't set any bits
5893 * that are enabled for EIAM, because this operation
5894 * would set *both* EIMS and EICS for any bit in EIAM
5895 */
5896 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5897 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5898 } else {
5899 /* get one bit for every active tx/rx interrupt vector */
5900 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5901 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5902 if (qv->rx.count || qv->tx.count)
5903 eics |= ((u64)1 << i);
5904 }
5905 }
5906
5907 /* Cause software interrupt to ensure rings are cleaned */
5908 ixgbe_irq_rearm_queues(adapter, eics);
5909
5910 }
5911
5912 /**
5913 * ixgbe_watchdog_update_link - update the link status
5914 * @adapter - pointer to the device adapter structure
5915 * @link_speed - pointer to a u32 to store the link_speed
5916 **/
5917 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5918 {
5919 struct ixgbe_hw *hw = &adapter->hw;
5920 u32 link_speed = adapter->link_speed;
5921 bool link_up = adapter->link_up;
5922 int i;
5923
5924 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5925 return;
5926
5927 if (hw->mac.ops.check_link) {
5928 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5929 } else {
5930 /* always assume link is up, if no check link function */
5931 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5932 link_up = true;
5933 }
5934 if (link_up) {
5935 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5936 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5937 hw->mac.ops.fc_enable(hw, i);
5938 } else {
5939 hw->mac.ops.fc_enable(hw, 0);
5940 }
5941 }
5942
5943 if (link_up ||
5944 time_after(jiffies, (adapter->link_check_timeout +
5945 IXGBE_TRY_LINK_TIMEOUT))) {
5946 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5947 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5948 IXGBE_WRITE_FLUSH(hw);
5949 }
5950
5951 adapter->link_up = link_up;
5952 adapter->link_speed = link_speed;
5953 }
5954
5955 /**
5956 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5957 * print link up message
5958 * @adapter - pointer to the device adapter structure
5959 **/
5960 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5961 {
5962 struct net_device *netdev = adapter->netdev;
5963 struct ixgbe_hw *hw = &adapter->hw;
5964 u32 link_speed = adapter->link_speed;
5965 bool flow_rx, flow_tx;
5966
5967 /* only continue if link was previously down */
5968 if (netif_carrier_ok(netdev))
5969 return;
5970
5971 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5972
5973 switch (hw->mac.type) {
5974 case ixgbe_mac_82598EB: {
5975 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5976 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5977 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5978 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5979 }
5980 break;
5981 case ixgbe_mac_X540:
5982 case ixgbe_mac_82599EB: {
5983 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5984 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5985 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5986 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5987 }
5988 break;
5989 default:
5990 flow_tx = false;
5991 flow_rx = false;
5992 break;
5993 }
5994 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5995 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5996 "10 Gbps" :
5997 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5998 "1 Gbps" :
5999 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6000 "100 Mbps" :
6001 "unknown speed"))),
6002 ((flow_rx && flow_tx) ? "RX/TX" :
6003 (flow_rx ? "RX" :
6004 (flow_tx ? "TX" : "None"))));
6005
6006 netif_carrier_on(netdev);
6007 #ifdef HAVE_IPLINK_VF_CONFIG
6008 ixgbe_check_vf_rate_limit(adapter);
6009 #endif /* HAVE_IPLINK_VF_CONFIG */
6010 }
6011
6012 /**
6013 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6014 * print link down message
6015 * @adapter - pointer to the adapter structure
6016 **/
6017 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
6018 {
6019 struct net_device *netdev = adapter->netdev;
6020 struct ixgbe_hw *hw = &adapter->hw;
6021
6022 adapter->link_up = false;
6023 adapter->link_speed = 0;
6024
6025 /* only continue if link was up previously */
6026 if (!netif_carrier_ok(netdev))
6027 return;
6028
6029 /* poll for SFP+ cable when link is down */
6030 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6031 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
6032
6033 e_info(drv, "NIC Link is Down\n");
6034 netif_carrier_off(netdev);
6035 }
6036
6037 /**
6038 * ixgbe_watchdog_flush_tx - flush queues on link down
6039 * @adapter - pointer to the device adapter structure
6040 **/
6041 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6042 {
6043 int i;
6044 int some_tx_pending = 0;
6045
6046 if (!netif_carrier_ok(adapter->netdev)) {
6047 for (i = 0; i < adapter->num_tx_queues; i++) {
6048 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6049 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6050 some_tx_pending = 1;
6051 break;
6052 }
6053 }
6054
6055 if (some_tx_pending) {
6056 /* We've lost link, so the controller stops DMA,
6057 * but we've got queued Tx work that's never going
6058 * to get done, so reset controller to flush Tx.
6059 * (Do the reset outside of interrupt context).
6060 */
6061 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
6062 }
6063 }
6064 }
6065
6066 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6067 {
6068 u32 ssvpc;
6069
6070 /* Do not perform spoof check for 82598 */
6071 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6072 return;
6073
6074 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6075
6076 /*
6077 * ssvpc register is cleared on read, if zero then no
6078 * spoofed packets in the last interval.
6079 */
6080 if (!ssvpc)
6081 return;
6082
6083 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6084 }
6085
6086 /**
6087 * ixgbe_watchdog_subtask - check and bring link up
6088 * @adapter - pointer to the device adapter structure
6089 **/
6090 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6091 {
6092 /* if interface is down do nothing */
6093 if (test_bit(__IXGBE_DOWN, &adapter->state))
6094 return;
6095
6096 ixgbe_watchdog_update_link(adapter);
6097
6098 if (adapter->link_up)
6099 ixgbe_watchdog_link_is_up(adapter);
6100 else
6101 ixgbe_watchdog_link_is_down(adapter);
6102
6103 ixgbe_spoof_check(adapter);
6104 ixgbe_update_stats(adapter);
6105
6106 ixgbe_watchdog_flush_tx(adapter);
6107 }
6108
6109 /**
6110 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6111 * @adapter - the ixgbe adapter structure
6112 **/
6113 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6114 {
6115 struct ixgbe_hw *hw = &adapter->hw;
6116 s32 err;
6117
6118 /* not searching for SFP so there is nothing to do here */
6119 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6120 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6121 return;
6122
6123 /* someone else is in init, wait until next service event */
6124 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6125 return;
6126
6127 err = hw->phy.ops.identify_sfp(hw);
6128 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6129 goto sfp_out;
6130
6131 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6132 /* If no cable is present, then we need to reset
6133 * the next time we find a good cable. */
6134 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6135 }
6136
6137 /* exit on error */
6138 if (err)
6139 goto sfp_out;
6140
6141 /* exit if reset not needed */
6142 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6143 goto sfp_out;
6144
6145 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6146
6147 /*
6148 * A module may be identified correctly, but the EEPROM may not have
6149 * support for that module. setup_sfp() will fail in that case, so
6150 * we should not allow that module to load.
6151 */
6152 if (hw->mac.type == ixgbe_mac_82598EB)
6153 err = hw->phy.ops.reset(hw);
6154 else
6155 err = hw->mac.ops.setup_sfp(hw);
6156
6157 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6158 goto sfp_out;
6159
6160 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6161 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6162
6163 sfp_out:
6164 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6165
6166 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6167 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6168 e_dev_err("failed to initialize because an unsupported "
6169 "SFP+ module type was detected.\n");
6170 e_dev_err("Reload the driver after installing a "
6171 "supported module.\n");
6172 unregister_netdev(adapter->netdev);
6173 }
6174 }
6175
6176 /**
6177 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6178 * @adapter - the ixgbe adapter structure
6179 **/
6180 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6181 {
6182 struct ixgbe_hw *hw = &adapter->hw;
6183 u32 autoneg;
6184 bool negotiation;
6185
6186 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6187 return;
6188
6189 /* someone else is in init, wait until next service event */
6190 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6191 return;
6192
6193 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6194
6195 autoneg = hw->phy.autoneg_advertised;
6196 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6197 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6198 hw->mac.autotry_restart = false;
6199 if (hw->mac.ops.setup_link)
6200 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6201
6202 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6203 adapter->link_check_timeout = jiffies;
6204 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6205 }
6206
6207 /**
6208 * ixgbe_service_timer - Timer Call-back
6209 * @data: pointer to adapter cast into an unsigned long
6210 **/
6211 static void ixgbe_service_timer(unsigned long data)
6212 {
6213 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6214 unsigned long next_event_offset;
6215
6216 /* poll faster when waiting for link */
6217 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6218 next_event_offset = HZ / 10;
6219 else
6220 next_event_offset = HZ * 2;
6221
6222 /* Reset the timer */
6223 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6224
6225 ixgbe_service_event_schedule(adapter);
6226 }
6227
6228 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6229 {
6230 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6231 return;
6232
6233 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6234
6235 /* If we're already down or resetting, just bail */
6236 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6237 test_bit(__IXGBE_RESETTING, &adapter->state))
6238 return;
6239
6240 ixgbe_dump(adapter);
6241 netdev_err(adapter->netdev, "Reset adapter\n");
6242 adapter->tx_timeout_count++;
6243
6244 ixgbe_reinit_locked(adapter);
6245 }
6246
6247 /**
6248 * ixgbe_service_task - manages and runs subtasks
6249 * @work: pointer to work_struct containing our data
6250 **/
6251 static void ixgbe_service_task(struct work_struct *work)
6252 {
6253 struct ixgbe_adapter *adapter = container_of(work,
6254 struct ixgbe_adapter,
6255 service_task);
6256
6257 ixgbe_reset_subtask(adapter);
6258 ixgbe_sfp_detection_subtask(adapter);
6259 ixgbe_sfp_link_config_subtask(adapter);
6260 ixgbe_check_overtemp_subtask(adapter);
6261 ixgbe_watchdog_subtask(adapter);
6262 ixgbe_fdir_reinit_subtask(adapter);
6263 ixgbe_check_hang_subtask(adapter);
6264
6265 ixgbe_service_event_complete(adapter);
6266 }
6267
6268 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6269 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
6270 {
6271 struct ixgbe_adv_tx_context_desc *context_desc;
6272 u16 i = tx_ring->next_to_use;
6273
6274 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6275
6276 i++;
6277 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
6278
6279 /* set bits to identify this as an advanced context descriptor */
6280 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
6281
6282 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6283 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
6284 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
6285 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6286 }
6287
6288 static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6289 u32 tx_flags, __be16 protocol, u8 *hdr_len)
6290 {
6291 int err;
6292 u32 vlan_macip_lens, type_tucmd;
6293 u32 mss_l4len_idx, l4len;
6294
6295 if (!skb_is_gso(skb))
6296 return 0;
6297
6298 if (skb_header_cloned(skb)) {
6299 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6300 if (err)
6301 return err;
6302 }
6303
6304 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6305 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6306
6307 if (protocol == __constant_htons(ETH_P_IP)) {
6308 struct iphdr *iph = ip_hdr(skb);
6309 iph->tot_len = 0;
6310 iph->check = 0;
6311 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6312 iph->daddr, 0,
6313 IPPROTO_TCP,
6314 0);
6315 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6316 } else if (skb_is_gso_v6(skb)) {
6317 ipv6_hdr(skb)->payload_len = 0;
6318 tcp_hdr(skb)->check =
6319 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6320 &ipv6_hdr(skb)->daddr,
6321 0, IPPROTO_TCP, 0);
6322 }
6323
6324 l4len = tcp_hdrlen(skb);
6325 *hdr_len = skb_transport_offset(skb) + l4len;
6326
6327 /* mss_l4len_id: use 1 as index for TSO */
6328 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6329 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6330 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6331
6332 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6333 vlan_macip_lens = skb_network_header_len(skb);
6334 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6335 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6336
6337 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6338 mss_l4len_idx);
6339
6340 return 1;
6341 }
6342
6343 static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6344 struct sk_buff *skb, u32 tx_flags,
6345 __be16 protocol)
6346 {
6347 u32 vlan_macip_lens = 0;
6348 u32 mss_l4len_idx = 0;
6349 u32 type_tucmd = 0;
6350
6351 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6352 if (!(tx_flags & IXGBE_TX_FLAGS_VLAN))
6353 return false;
6354 } else {
6355 u8 l4_hdr = 0;
6356 switch (protocol) {
6357 case __constant_htons(ETH_P_IP):
6358 vlan_macip_lens |= skb_network_header_len(skb);
6359 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6360 l4_hdr = ip_hdr(skb)->protocol;
6361 break;
6362 case __constant_htons(ETH_P_IPV6):
6363 vlan_macip_lens |= skb_network_header_len(skb);
6364 l4_hdr = ipv6_hdr(skb)->nexthdr;
6365 break;
6366 default:
6367 if (unlikely(net_ratelimit())) {
6368 dev_warn(tx_ring->dev,
6369 "partial checksum but proto=%x!\n",
6370 skb->protocol);
6371 }
6372 break;
6373 }
6374
6375 switch (l4_hdr) {
6376 case IPPROTO_TCP:
6377 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6378 mss_l4len_idx = tcp_hdrlen(skb) <<
6379 IXGBE_ADVTXD_L4LEN_SHIFT;
6380 break;
6381 case IPPROTO_SCTP:
6382 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6383 mss_l4len_idx = sizeof(struct sctphdr) <<
6384 IXGBE_ADVTXD_L4LEN_SHIFT;
6385 break;
6386 case IPPROTO_UDP:
6387 mss_l4len_idx = sizeof(struct udphdr) <<
6388 IXGBE_ADVTXD_L4LEN_SHIFT;
6389 break;
6390 default:
6391 if (unlikely(net_ratelimit())) {
6392 dev_warn(tx_ring->dev,
6393 "partial checksum but l4 proto=%x!\n",
6394 skb->protocol);
6395 }
6396 break;
6397 }
6398 }
6399
6400 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6401 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6402
6403 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6404 type_tucmd, mss_l4len_idx);
6405
6406 return (skb->ip_summed == CHECKSUM_PARTIAL);
6407 }
6408
6409 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6410 struct ixgbe_ring *tx_ring,
6411 struct sk_buff *skb, u32 tx_flags,
6412 unsigned int first, const u8 hdr_len)
6413 {
6414 struct device *dev = tx_ring->dev;
6415 struct ixgbe_tx_buffer *tx_buffer_info;
6416 unsigned int len;
6417 unsigned int total = skb->len;
6418 unsigned int offset = 0, size, count = 0;
6419 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6420 unsigned int f;
6421 unsigned int bytecount = skb->len;
6422 u16 gso_segs = 1;
6423 u16 i;
6424
6425 i = tx_ring->next_to_use;
6426
6427 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6428 /* excluding fcoe_crc_eof for FCoE */
6429 total -= sizeof(struct fcoe_crc_eof);
6430
6431 len = min(skb_headlen(skb), total);
6432 while (len) {
6433 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6434 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6435
6436 tx_buffer_info->length = size;
6437 tx_buffer_info->mapped_as_page = false;
6438 tx_buffer_info->dma = dma_map_single(dev,
6439 skb->data + offset,
6440 size, DMA_TO_DEVICE);
6441 if (dma_mapping_error(dev, tx_buffer_info->dma))
6442 goto dma_error;
6443 tx_buffer_info->time_stamp = jiffies;
6444 tx_buffer_info->next_to_watch = i;
6445
6446 len -= size;
6447 total -= size;
6448 offset += size;
6449 count++;
6450
6451 if (len) {
6452 i++;
6453 if (i == tx_ring->count)
6454 i = 0;
6455 }
6456 }
6457
6458 for (f = 0; f < nr_frags; f++) {
6459 struct skb_frag_struct *frag;
6460
6461 frag = &skb_shinfo(skb)->frags[f];
6462 len = min((unsigned int)frag->size, total);
6463 offset = frag->page_offset;
6464
6465 while (len) {
6466 i++;
6467 if (i == tx_ring->count)
6468 i = 0;
6469
6470 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6471 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6472
6473 tx_buffer_info->length = size;
6474 tx_buffer_info->dma = dma_map_page(dev,
6475 frag->page,
6476 offset, size,
6477 DMA_TO_DEVICE);
6478 tx_buffer_info->mapped_as_page = true;
6479 if (dma_mapping_error(dev, tx_buffer_info->dma))
6480 goto dma_error;
6481 tx_buffer_info->time_stamp = jiffies;
6482 tx_buffer_info->next_to_watch = i;
6483
6484 len -= size;
6485 total -= size;
6486 offset += size;
6487 count++;
6488 }
6489 if (total == 0)
6490 break;
6491 }
6492
6493 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6494 gso_segs = skb_shinfo(skb)->gso_segs;
6495 #ifdef IXGBE_FCOE
6496 /* adjust for FCoE Sequence Offload */
6497 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6498 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6499 skb_shinfo(skb)->gso_size);
6500 #endif /* IXGBE_FCOE */
6501 bytecount += (gso_segs - 1) * hdr_len;
6502
6503 /* multiply data chunks by size of headers */
6504 tx_ring->tx_buffer_info[i].bytecount = bytecount;
6505 tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6506 tx_ring->tx_buffer_info[i].skb = skb;
6507 tx_ring->tx_buffer_info[first].next_to_watch = i;
6508
6509 return count;
6510
6511 dma_error:
6512 e_dev_err("TX DMA map failed\n");
6513
6514 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6515 tx_buffer_info->dma = 0;
6516 tx_buffer_info->time_stamp = 0;
6517 tx_buffer_info->next_to_watch = 0;
6518 if (count)
6519 count--;
6520
6521 /* clear timestamp and dma mappings for remaining portion of packet */
6522 while (count--) {
6523 if (i == 0)
6524 i += tx_ring->count;
6525 i--;
6526 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6527 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6528 }
6529
6530 return 0;
6531 }
6532
6533 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6534 int tx_flags, int count, u32 paylen, u8 hdr_len)
6535 {
6536 union ixgbe_adv_tx_desc *tx_desc = NULL;
6537 struct ixgbe_tx_buffer *tx_buffer_info;
6538 u32 olinfo_status = 0, cmd_type_len = 0;
6539 unsigned int i;
6540 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6541
6542 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6543
6544 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6545
6546 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6547 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6548
6549 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6550 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6551
6552 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6553 IXGBE_ADVTXD_POPTS_SHIFT;
6554
6555 /* use index 1 context for tso */
6556 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6557 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6558 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6559 IXGBE_ADVTXD_POPTS_SHIFT;
6560
6561 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6562 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6563 IXGBE_ADVTXD_POPTS_SHIFT;
6564
6565 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6566 olinfo_status |= IXGBE_ADVTXD_CC;
6567 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6568 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6569 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6570 }
6571
6572 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6573
6574 i = tx_ring->next_to_use;
6575 while (count--) {
6576 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6577 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6578 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6579 tx_desc->read.cmd_type_len =
6580 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6581 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6582 i++;
6583 if (i == tx_ring->count)
6584 i = 0;
6585 }
6586
6587 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6588
6589 /*
6590 * Force memory writes to complete before letting h/w
6591 * know there are new descriptors to fetch. (Only
6592 * applicable for weak-ordered memory model archs,
6593 * such as IA-64).
6594 */
6595 wmb();
6596
6597 tx_ring->next_to_use = i;
6598 writel(i, tx_ring->tail);
6599 }
6600
6601 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6602 u32 tx_flags, __be16 protocol)
6603 {
6604 struct ixgbe_q_vector *q_vector = ring->q_vector;
6605 union ixgbe_atr_hash_dword input = { .dword = 0 };
6606 union ixgbe_atr_hash_dword common = { .dword = 0 };
6607 union {
6608 unsigned char *network;
6609 struct iphdr *ipv4;
6610 struct ipv6hdr *ipv6;
6611 } hdr;
6612 struct tcphdr *th;
6613 __be16 vlan_id;
6614
6615 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6616 if (!q_vector)
6617 return;
6618
6619 /* do nothing if sampling is disabled */
6620 if (!ring->atr_sample_rate)
6621 return;
6622
6623 ring->atr_count++;
6624
6625 /* snag network header to get L4 type and address */
6626 hdr.network = skb_network_header(skb);
6627
6628 /* Currently only IPv4/IPv6 with TCP is supported */
6629 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6630 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6631 (protocol != __constant_htons(ETH_P_IP) ||
6632 hdr.ipv4->protocol != IPPROTO_TCP))
6633 return;
6634
6635 th = tcp_hdr(skb);
6636
6637 /* skip this packet since the socket is closing */
6638 if (th->fin)
6639 return;
6640
6641 /* sample on all syn packets or once every atr sample count */
6642 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6643 return;
6644
6645 /* reset sample count */
6646 ring->atr_count = 0;
6647
6648 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6649
6650 /*
6651 * src and dst are inverted, think how the receiver sees them
6652 *
6653 * The input is broken into two sections, a non-compressed section
6654 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6655 * is XORed together and stored in the compressed dword.
6656 */
6657 input.formatted.vlan_id = vlan_id;
6658
6659 /*
6660 * since src port and flex bytes occupy the same word XOR them together
6661 * and write the value to source port portion of compressed dword
6662 */
6663 if (vlan_id)
6664 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6665 else
6666 common.port.src ^= th->dest ^ protocol;
6667 common.port.dst ^= th->source;
6668
6669 if (protocol == __constant_htons(ETH_P_IP)) {
6670 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6671 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6672 } else {
6673 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6674 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6675 hdr.ipv6->saddr.s6_addr32[1] ^
6676 hdr.ipv6->saddr.s6_addr32[2] ^
6677 hdr.ipv6->saddr.s6_addr32[3] ^
6678 hdr.ipv6->daddr.s6_addr32[0] ^
6679 hdr.ipv6->daddr.s6_addr32[1] ^
6680 hdr.ipv6->daddr.s6_addr32[2] ^
6681 hdr.ipv6->daddr.s6_addr32[3];
6682 }
6683
6684 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6685 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6686 input, common, ring->queue_index);
6687 }
6688
6689 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6690 {
6691 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6692 /* Herbert's original patch had:
6693 * smp_mb__after_netif_stop_queue();
6694 * but since that doesn't exist yet, just open code it. */
6695 smp_mb();
6696
6697 /* We need to check again in a case another CPU has just
6698 * made room available. */
6699 if (likely(ixgbe_desc_unused(tx_ring) < size))
6700 return -EBUSY;
6701
6702 /* A reprieve! - use start_queue because it doesn't call schedule */
6703 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6704 ++tx_ring->tx_stats.restart_queue;
6705 return 0;
6706 }
6707
6708 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6709 {
6710 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6711 return 0;
6712 return __ixgbe_maybe_stop_tx(tx_ring, size);
6713 }
6714
6715 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6716 {
6717 struct ixgbe_adapter *adapter = netdev_priv(dev);
6718 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6719 smp_processor_id();
6720 #ifdef IXGBE_FCOE
6721 __be16 protocol = vlan_get_protocol(skb);
6722
6723 if (((protocol == htons(ETH_P_FCOE)) ||
6724 (protocol == htons(ETH_P_FIP))) &&
6725 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6726 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6727 txq += adapter->ring_feature[RING_F_FCOE].mask;
6728 return txq;
6729 }
6730 #endif
6731
6732 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6733 while (unlikely(txq >= dev->real_num_tx_queues))
6734 txq -= dev->real_num_tx_queues;
6735 return txq;
6736 }
6737
6738 return skb_tx_hash(dev, skb);
6739 }
6740
6741 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6742 struct ixgbe_adapter *adapter,
6743 struct ixgbe_ring *tx_ring)
6744 {
6745 int tso;
6746 u32 tx_flags = 0;
6747 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6748 unsigned short f;
6749 #endif
6750 u16 first;
6751 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6752 __be16 protocol;
6753 u8 hdr_len = 0;
6754
6755 /*
6756 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6757 * + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6758 * + 2 desc gap to keep tail from touching head,
6759 * + 1 desc for context descriptor,
6760 * otherwise try next time
6761 */
6762 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6763 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6764 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6765 #else
6766 count += skb_shinfo(skb)->nr_frags;
6767 #endif
6768 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6769 tx_ring->tx_stats.tx_busy++;
6770 return NETDEV_TX_BUSY;
6771 }
6772
6773 protocol = vlan_get_protocol(skb);
6774
6775 if (vlan_tx_tag_present(skb)) {
6776 tx_flags |= vlan_tx_tag_get(skb);
6777 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6778 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6779 tx_flags |= tx_ring->dcb_tc << 13;
6780 }
6781 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6782 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6783 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6784 skb->priority != TC_PRIO_CONTROL) {
6785 tx_flags |= tx_ring->dcb_tc << 13;
6786 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6787 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6788 }
6789
6790 #ifdef IXGBE_FCOE
6791 /* for FCoE with DCB, we force the priority to what
6792 * was specified by the switch */
6793 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6794 (protocol == htons(ETH_P_FCOE)))
6795 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6796
6797 #endif
6798 /* record the location of the first descriptor for this packet */
6799 first = tx_ring->next_to_use;
6800
6801 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6802 #ifdef IXGBE_FCOE
6803 /* setup tx offload for FCoE */
6804 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6805 if (tso < 0)
6806 goto out_drop;
6807 else if (tso)
6808 tx_flags |= IXGBE_TX_FLAGS_FSO;
6809 #endif /* IXGBE_FCOE */
6810 } else {
6811 if (protocol == htons(ETH_P_IP))
6812 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6813 tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6814 if (tso < 0)
6815 goto out_drop;
6816 else if (tso)
6817 tx_flags |= IXGBE_TX_FLAGS_TSO;
6818 else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
6819 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6820 }
6821
6822 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6823 if (count) {
6824 /* add the ATR filter if ATR is on */
6825 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6826 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6827 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
6828 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6829
6830 } else {
6831 tx_ring->tx_buffer_info[first].time_stamp = 0;
6832 tx_ring->next_to_use = first;
6833 goto out_drop;
6834 }
6835
6836 return NETDEV_TX_OK;
6837
6838 out_drop:
6839 dev_kfree_skb_any(skb);
6840 return NETDEV_TX_OK;
6841 }
6842
6843 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6844 {
6845 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6846 struct ixgbe_ring *tx_ring;
6847
6848 tx_ring = adapter->tx_ring[skb->queue_mapping];
6849 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6850 }
6851
6852 /**
6853 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6854 * @netdev: network interface device structure
6855 * @p: pointer to an address structure
6856 *
6857 * Returns 0 on success, negative on failure
6858 **/
6859 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6860 {
6861 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6862 struct ixgbe_hw *hw = &adapter->hw;
6863 struct sockaddr *addr = p;
6864
6865 if (!is_valid_ether_addr(addr->sa_data))
6866 return -EADDRNOTAVAIL;
6867
6868 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6869 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6870
6871 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6872 IXGBE_RAH_AV);
6873
6874 return 0;
6875 }
6876
6877 static int
6878 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6879 {
6880 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6881 struct ixgbe_hw *hw = &adapter->hw;
6882 u16 value;
6883 int rc;
6884
6885 if (prtad != hw->phy.mdio.prtad)
6886 return -EINVAL;
6887 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6888 if (!rc)
6889 rc = value;
6890 return rc;
6891 }
6892
6893 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6894 u16 addr, u16 value)
6895 {
6896 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6897 struct ixgbe_hw *hw = &adapter->hw;
6898
6899 if (prtad != hw->phy.mdio.prtad)
6900 return -EINVAL;
6901 return hw->phy.ops.write_reg(hw, addr, devad, value);
6902 }
6903
6904 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6905 {
6906 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6907
6908 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6909 }
6910
6911 /**
6912 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6913 * netdev->dev_addrs
6914 * @netdev: network interface device structure
6915 *
6916 * Returns non-zero on failure
6917 **/
6918 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6919 {
6920 int err = 0;
6921 struct ixgbe_adapter *adapter = netdev_priv(dev);
6922 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6923
6924 if (is_valid_ether_addr(mac->san_addr)) {
6925 rtnl_lock();
6926 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6927 rtnl_unlock();
6928 }
6929 return err;
6930 }
6931
6932 /**
6933 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6934 * netdev->dev_addrs
6935 * @netdev: network interface device structure
6936 *
6937 * Returns non-zero on failure
6938 **/
6939 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6940 {
6941 int err = 0;
6942 struct ixgbe_adapter *adapter = netdev_priv(dev);
6943 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6944
6945 if (is_valid_ether_addr(mac->san_addr)) {
6946 rtnl_lock();
6947 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6948 rtnl_unlock();
6949 }
6950 return err;
6951 }
6952
6953 #ifdef CONFIG_NET_POLL_CONTROLLER
6954 /*
6955 * Polling 'interrupt' - used by things like netconsole to send skbs
6956 * without having to re-enable interrupts. It's not called while
6957 * the interrupt routine is executing.
6958 */
6959 static void ixgbe_netpoll(struct net_device *netdev)
6960 {
6961 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6962 int i;
6963
6964 /* if interface is down do nothing */
6965 if (test_bit(__IXGBE_DOWN, &adapter->state))
6966 return;
6967
6968 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6969 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6970 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6971 for (i = 0; i < num_q_vectors; i++) {
6972 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6973 ixgbe_msix_clean_many(0, q_vector);
6974 }
6975 } else {
6976 ixgbe_intr(adapter->pdev->irq, netdev);
6977 }
6978 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6979 }
6980 #endif
6981
6982 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6983 struct rtnl_link_stats64 *stats)
6984 {
6985 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6986 int i;
6987
6988 rcu_read_lock();
6989 for (i = 0; i < adapter->num_rx_queues; i++) {
6990 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6991 u64 bytes, packets;
6992 unsigned int start;
6993
6994 if (ring) {
6995 do {
6996 start = u64_stats_fetch_begin_bh(&ring->syncp);
6997 packets = ring->stats.packets;
6998 bytes = ring->stats.bytes;
6999 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7000 stats->rx_packets += packets;
7001 stats->rx_bytes += bytes;
7002 }
7003 }
7004
7005 for (i = 0; i < adapter->num_tx_queues; i++) {
7006 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7007 u64 bytes, packets;
7008 unsigned int start;
7009
7010 if (ring) {
7011 do {
7012 start = u64_stats_fetch_begin_bh(&ring->syncp);
7013 packets = ring->stats.packets;
7014 bytes = ring->stats.bytes;
7015 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7016 stats->tx_packets += packets;
7017 stats->tx_bytes += bytes;
7018 }
7019 }
7020 rcu_read_unlock();
7021 /* following stats updated by ixgbe_watchdog_task() */
7022 stats->multicast = netdev->stats.multicast;
7023 stats->rx_errors = netdev->stats.rx_errors;
7024 stats->rx_length_errors = netdev->stats.rx_length_errors;
7025 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7026 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7027 return stats;
7028 }
7029
7030 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7031 * #adapter: pointer to ixgbe_adapter
7032 * @tc: number of traffic classes currently enabled
7033 *
7034 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7035 * 802.1Q priority maps to a packet buffer that exists.
7036 */
7037 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7038 {
7039 struct ixgbe_hw *hw = &adapter->hw;
7040 u32 reg, rsave;
7041 int i;
7042
7043 /* 82598 have a static priority to TC mapping that can not
7044 * be changed so no validation is needed.
7045 */
7046 if (hw->mac.type == ixgbe_mac_82598EB)
7047 return;
7048
7049 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7050 rsave = reg;
7051
7052 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7053 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7054
7055 /* If up2tc is out of bounds default to zero */
7056 if (up2tc > tc)
7057 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7058 }
7059
7060 if (reg != rsave)
7061 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7062
7063 return;
7064 }
7065
7066
7067 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7068 * classes.
7069 *
7070 * @netdev: net device to configure
7071 * @tc: number of traffic classes to enable
7072 */
7073 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7074 {
7075 struct ixgbe_adapter *adapter = netdev_priv(dev);
7076 struct ixgbe_hw *hw = &adapter->hw;
7077
7078 /* If DCB is anabled do not remove traffic classes, multiple
7079 * traffic classes are required to implement DCB
7080 */
7081 if (!tc && (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7082 return 0;
7083
7084 /* Hardware supports up to 8 traffic classes */
7085 if (tc > MAX_TRAFFIC_CLASS ||
7086 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7087 return -EINVAL;
7088
7089 /* Hardware has to reinitialize queues and interrupts to
7090 * match packet buffer alignment. Unfortunantly, the
7091 * hardware is not flexible enough to do this dynamically.
7092 */
7093 if (netif_running(dev))
7094 ixgbe_close(dev);
7095 ixgbe_clear_interrupt_scheme(adapter);
7096
7097 if (tc)
7098 netdev_set_num_tc(dev, tc);
7099 else
7100 netdev_reset_tc(dev);
7101
7102 ixgbe_init_interrupt_scheme(adapter);
7103 ixgbe_validate_rtr(adapter, tc);
7104 if (netif_running(dev))
7105 ixgbe_open(dev);
7106
7107 return 0;
7108 }
7109
7110 static const struct net_device_ops ixgbe_netdev_ops = {
7111 .ndo_open = ixgbe_open,
7112 .ndo_stop = ixgbe_close,
7113 .ndo_start_xmit = ixgbe_xmit_frame,
7114 .ndo_select_queue = ixgbe_select_queue,
7115 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7116 .ndo_set_multicast_list = ixgbe_set_rx_mode,
7117 .ndo_validate_addr = eth_validate_addr,
7118 .ndo_set_mac_address = ixgbe_set_mac,
7119 .ndo_change_mtu = ixgbe_change_mtu,
7120 .ndo_tx_timeout = ixgbe_tx_timeout,
7121 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7122 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7123 .ndo_do_ioctl = ixgbe_ioctl,
7124 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7125 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7126 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7127 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7128 .ndo_get_stats64 = ixgbe_get_stats64,
7129 .ndo_setup_tc = ixgbe_setup_tc,
7130 #ifdef CONFIG_NET_POLL_CONTROLLER
7131 .ndo_poll_controller = ixgbe_netpoll,
7132 #endif
7133 #ifdef IXGBE_FCOE
7134 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7135 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7136 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7137 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7138 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7139 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7140 #endif /* IXGBE_FCOE */
7141 };
7142
7143 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7144 const struct ixgbe_info *ii)
7145 {
7146 #ifdef CONFIG_PCI_IOV
7147 struct ixgbe_hw *hw = &adapter->hw;
7148 int err;
7149 int num_vf_macvlans, i;
7150 struct vf_macvlans *mv_list;
7151
7152 if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
7153 return;
7154
7155 /* The 82599 supports up to 64 VFs per physical function
7156 * but this implementation limits allocation to 63 so that
7157 * basic networking resources are still available to the
7158 * physical function
7159 */
7160 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7161 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7162 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7163 if (err) {
7164 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
7165 goto err_novfs;
7166 }
7167
7168 num_vf_macvlans = hw->mac.num_rar_entries -
7169 (IXGBE_MAX_PF_MACVLANS + 1 + adapter->num_vfs);
7170
7171 adapter->mv_list = mv_list = kcalloc(num_vf_macvlans,
7172 sizeof(struct vf_macvlans),
7173 GFP_KERNEL);
7174 if (mv_list) {
7175 /* Initialize list of VF macvlans */
7176 INIT_LIST_HEAD(&adapter->vf_mvs.l);
7177 for (i = 0; i < num_vf_macvlans; i++) {
7178 mv_list->vf = -1;
7179 mv_list->free = true;
7180 mv_list->rar_entry = hw->mac.num_rar_entries -
7181 (i + adapter->num_vfs + 1);
7182 list_add(&mv_list->l, &adapter->vf_mvs.l);
7183 mv_list++;
7184 }
7185 }
7186
7187 /* If call to enable VFs succeeded then allocate memory
7188 * for per VF control structures.
7189 */
7190 adapter->vfinfo =
7191 kcalloc(adapter->num_vfs,
7192 sizeof(struct vf_data_storage), GFP_KERNEL);
7193 if (adapter->vfinfo) {
7194 /* Now that we're sure SR-IOV is enabled
7195 * and memory allocated set up the mailbox parameters
7196 */
7197 ixgbe_init_mbx_params_pf(hw);
7198 memcpy(&hw->mbx.ops, ii->mbx_ops,
7199 sizeof(hw->mbx.ops));
7200
7201 /* Disable RSC when in SR-IOV mode */
7202 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7203 IXGBE_FLAG2_RSC_ENABLED);
7204 return;
7205 }
7206
7207 /* Oh oh */
7208 e_err(probe, "Unable to allocate memory for VF Data Storage - "
7209 "SRIOV disabled\n");
7210 pci_disable_sriov(adapter->pdev);
7211
7212 err_novfs:
7213 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7214 adapter->num_vfs = 0;
7215 #endif /* CONFIG_PCI_IOV */
7216 }
7217
7218 /**
7219 * ixgbe_probe - Device Initialization Routine
7220 * @pdev: PCI device information struct
7221 * @ent: entry in ixgbe_pci_tbl
7222 *
7223 * Returns 0 on success, negative on failure
7224 *
7225 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7226 * The OS initialization, configuring of the adapter private structure,
7227 * and a hardware reset occur.
7228 **/
7229 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7230 const struct pci_device_id *ent)
7231 {
7232 struct net_device *netdev;
7233 struct ixgbe_adapter *adapter = NULL;
7234 struct ixgbe_hw *hw;
7235 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7236 static int cards_found;
7237 int i, err, pci_using_dac;
7238 u8 part_str[IXGBE_PBANUM_LENGTH];
7239 unsigned int indices = num_possible_cpus();
7240 #ifdef IXGBE_FCOE
7241 u16 device_caps;
7242 #endif
7243 u32 eec;
7244
7245 /* Catch broken hardware that put the wrong VF device ID in
7246 * the PCIe SR-IOV capability.
7247 */
7248 if (pdev->is_virtfn) {
7249 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7250 pci_name(pdev), pdev->vendor, pdev->device);
7251 return -EINVAL;
7252 }
7253
7254 err = pci_enable_device_mem(pdev);
7255 if (err)
7256 return err;
7257
7258 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7259 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7260 pci_using_dac = 1;
7261 } else {
7262 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7263 if (err) {
7264 err = dma_set_coherent_mask(&pdev->dev,
7265 DMA_BIT_MASK(32));
7266 if (err) {
7267 dev_err(&pdev->dev,
7268 "No usable DMA configuration, aborting\n");
7269 goto err_dma;
7270 }
7271 }
7272 pci_using_dac = 0;
7273 }
7274
7275 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7276 IORESOURCE_MEM), ixgbe_driver_name);
7277 if (err) {
7278 dev_err(&pdev->dev,
7279 "pci_request_selected_regions failed 0x%x\n", err);
7280 goto err_pci_reg;
7281 }
7282
7283 pci_enable_pcie_error_reporting(pdev);
7284
7285 pci_set_master(pdev);
7286 pci_save_state(pdev);
7287
7288 #ifdef CONFIG_IXGBE_DCB
7289 indices *= MAX_TRAFFIC_CLASS;
7290 #endif
7291
7292 if (ii->mac == ixgbe_mac_82598EB)
7293 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7294 else
7295 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7296
7297 #ifdef IXGBE_FCOE
7298 indices += min_t(unsigned int, num_possible_cpus(),
7299 IXGBE_MAX_FCOE_INDICES);
7300 #endif
7301 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7302 if (!netdev) {
7303 err = -ENOMEM;
7304 goto err_alloc_etherdev;
7305 }
7306
7307 SET_NETDEV_DEV(netdev, &pdev->dev);
7308
7309 adapter = netdev_priv(netdev);
7310 pci_set_drvdata(pdev, adapter);
7311
7312 adapter->netdev = netdev;
7313 adapter->pdev = pdev;
7314 hw = &adapter->hw;
7315 hw->back = adapter;
7316 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7317
7318 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7319 pci_resource_len(pdev, 0));
7320 if (!hw->hw_addr) {
7321 err = -EIO;
7322 goto err_ioremap;
7323 }
7324
7325 for (i = 1; i <= 5; i++) {
7326 if (pci_resource_len(pdev, i) == 0)
7327 continue;
7328 }
7329
7330 netdev->netdev_ops = &ixgbe_netdev_ops;
7331 ixgbe_set_ethtool_ops(netdev);
7332 netdev->watchdog_timeo = 5 * HZ;
7333 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7334
7335 adapter->bd_number = cards_found;
7336
7337 /* Setup hw api */
7338 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7339 hw->mac.type = ii->mac;
7340
7341 /* EEPROM */
7342 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7343 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7344 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7345 if (!(eec & (1 << 8)))
7346 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7347
7348 /* PHY */
7349 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7350 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7351 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7352 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7353 hw->phy.mdio.mmds = 0;
7354 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7355 hw->phy.mdio.dev = netdev;
7356 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7357 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7358
7359 ii->get_invariants(hw);
7360
7361 /* setup the private structure */
7362 err = ixgbe_sw_init(adapter);
7363 if (err)
7364 goto err_sw_init;
7365
7366 /* Make it possible the adapter to be woken up via WOL */
7367 switch (adapter->hw.mac.type) {
7368 case ixgbe_mac_82599EB:
7369 case ixgbe_mac_X540:
7370 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7371 break;
7372 default:
7373 break;
7374 }
7375
7376 /*
7377 * If there is a fan on this device and it has failed log the
7378 * failure.
7379 */
7380 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7381 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7382 if (esdp & IXGBE_ESDP_SDP1)
7383 e_crit(probe, "Fan has stopped, replace the adapter\n");
7384 }
7385
7386 /* reset_hw fills in the perm_addr as well */
7387 hw->phy.reset_if_overtemp = true;
7388 err = hw->mac.ops.reset_hw(hw);
7389 hw->phy.reset_if_overtemp = false;
7390 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7391 hw->mac.type == ixgbe_mac_82598EB) {
7392 err = 0;
7393 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7394 e_dev_err("failed to load because an unsupported SFP+ "
7395 "module type was detected.\n");
7396 e_dev_err("Reload the driver after installing a supported "
7397 "module.\n");
7398 goto err_sw_init;
7399 } else if (err) {
7400 e_dev_err("HW Init failed: %d\n", err);
7401 goto err_sw_init;
7402 }
7403
7404 ixgbe_probe_vf(adapter, ii);
7405
7406 netdev->features = NETIF_F_SG |
7407 NETIF_F_IP_CSUM |
7408 NETIF_F_HW_VLAN_TX |
7409 NETIF_F_HW_VLAN_RX |
7410 NETIF_F_HW_VLAN_FILTER;
7411
7412 netdev->features |= NETIF_F_IPV6_CSUM;
7413 netdev->features |= NETIF_F_TSO;
7414 netdev->features |= NETIF_F_TSO6;
7415 netdev->features |= NETIF_F_GRO;
7416 netdev->features |= NETIF_F_RXHASH;
7417
7418 switch (adapter->hw.mac.type) {
7419 case ixgbe_mac_82599EB:
7420 case ixgbe_mac_X540:
7421 netdev->features |= NETIF_F_SCTP_CSUM;
7422 break;
7423 default:
7424 break;
7425 }
7426
7427 netdev->vlan_features |= NETIF_F_TSO;
7428 netdev->vlan_features |= NETIF_F_TSO6;
7429 netdev->vlan_features |= NETIF_F_IP_CSUM;
7430 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7431 netdev->vlan_features |= NETIF_F_SG;
7432
7433 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7434 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7435 IXGBE_FLAG_DCB_ENABLED);
7436
7437 #ifdef CONFIG_IXGBE_DCB
7438 netdev->dcbnl_ops = &dcbnl_ops;
7439 #endif
7440
7441 #ifdef IXGBE_FCOE
7442 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7443 if (hw->mac.ops.get_device_caps) {
7444 hw->mac.ops.get_device_caps(hw, &device_caps);
7445 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7446 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7447 }
7448 }
7449 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7450 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7451 netdev->vlan_features |= NETIF_F_FSO;
7452 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7453 }
7454 #endif /* IXGBE_FCOE */
7455 if (pci_using_dac) {
7456 netdev->features |= NETIF_F_HIGHDMA;
7457 netdev->vlan_features |= NETIF_F_HIGHDMA;
7458 }
7459
7460 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7461 netdev->features |= NETIF_F_LRO;
7462
7463 /* make sure the EEPROM is good */
7464 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7465 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7466 err = -EIO;
7467 goto err_eeprom;
7468 }
7469
7470 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7471 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7472
7473 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7474 e_dev_err("invalid MAC address\n");
7475 err = -EIO;
7476 goto err_eeprom;
7477 }
7478
7479 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7480 if (hw->mac.ops.disable_tx_laser &&
7481 ((hw->phy.multispeed_fiber) ||
7482 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7483 (hw->mac.type == ixgbe_mac_82599EB))))
7484 hw->mac.ops.disable_tx_laser(hw);
7485
7486 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7487 (unsigned long) adapter);
7488
7489 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7490 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7491
7492 err = ixgbe_init_interrupt_scheme(adapter);
7493 if (err)
7494 goto err_sw_init;
7495
7496 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7497 netdev->features &= ~NETIF_F_RXHASH;
7498
7499 switch (pdev->device) {
7500 case IXGBE_DEV_ID_82599_SFP:
7501 /* Only this subdevice supports WOL */
7502 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7503 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7504 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7505 break;
7506 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7507 /* All except this subdevice support WOL */
7508 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7509 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7510 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7511 break;
7512 case IXGBE_DEV_ID_82599_KX4:
7513 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7514 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7515 break;
7516 default:
7517 adapter->wol = 0;
7518 break;
7519 }
7520 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7521
7522 /* pick up the PCI bus settings for reporting later */
7523 hw->mac.ops.get_bus_info(hw);
7524
7525 /* print bus type/speed/width info */
7526 e_dev_info("(PCI Express:%s:%s) %pM\n",
7527 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7528 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7529 "Unknown"),
7530 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7531 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7532 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7533 "Unknown"),
7534 netdev->dev_addr);
7535
7536 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7537 if (err)
7538 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7539 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7540 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7541 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7542 part_str);
7543 else
7544 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7545 hw->mac.type, hw->phy.type, part_str);
7546
7547 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7548 e_dev_warn("PCI-Express bandwidth available for this card is "
7549 "not sufficient for optimal performance.\n");
7550 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7551 "is required.\n");
7552 }
7553
7554 /* save off EEPROM version number */
7555 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7556
7557 /* reset the hardware with the new settings */
7558 err = hw->mac.ops.start_hw(hw);
7559
7560 if (err == IXGBE_ERR_EEPROM_VERSION) {
7561 /* We are running on a pre-production device, log a warning */
7562 e_dev_warn("This device is a pre-production adapter/LOM. "
7563 "Please be aware there may be issues associated "
7564 "with your hardware. If you are experiencing "
7565 "problems please contact your Intel or hardware "
7566 "representative who provided you with this "
7567 "hardware.\n");
7568 }
7569 strcpy(netdev->name, "eth%d");
7570 err = register_netdev(netdev);
7571 if (err)
7572 goto err_register;
7573
7574 /* carrier off reporting is important to ethtool even BEFORE open */
7575 netif_carrier_off(netdev);
7576
7577 #ifdef CONFIG_IXGBE_DCA
7578 if (dca_add_requester(&pdev->dev) == 0) {
7579 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7580 ixgbe_setup_dca(adapter);
7581 }
7582 #endif
7583 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7584 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7585 for (i = 0; i < adapter->num_vfs; i++)
7586 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7587 }
7588
7589 /* Inform firmware of driver version */
7590 if (hw->mac.ops.set_fw_drv_ver)
7591 hw->mac.ops.set_fw_drv_ver(hw, MAJ, MIN, BUILD,
7592 FW_CEM_UNUSED_VER);
7593
7594 /* add san mac addr to netdev */
7595 ixgbe_add_sanmac_netdev(netdev);
7596
7597 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7598 cards_found++;
7599 return 0;
7600
7601 err_register:
7602 ixgbe_release_hw_control(adapter);
7603 ixgbe_clear_interrupt_scheme(adapter);
7604 err_sw_init:
7605 err_eeprom:
7606 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7607 ixgbe_disable_sriov(adapter);
7608 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7609 iounmap(hw->hw_addr);
7610 err_ioremap:
7611 free_netdev(netdev);
7612 err_alloc_etherdev:
7613 pci_release_selected_regions(pdev,
7614 pci_select_bars(pdev, IORESOURCE_MEM));
7615 err_pci_reg:
7616 err_dma:
7617 pci_disable_device(pdev);
7618 return err;
7619 }
7620
7621 /**
7622 * ixgbe_remove - Device Removal Routine
7623 * @pdev: PCI device information struct
7624 *
7625 * ixgbe_remove is called by the PCI subsystem to alert the driver
7626 * that it should release a PCI device. The could be caused by a
7627 * Hot-Plug event, or because the driver is going to be removed from
7628 * memory.
7629 **/
7630 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7631 {
7632 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7633 struct net_device *netdev = adapter->netdev;
7634
7635 set_bit(__IXGBE_DOWN, &adapter->state);
7636 cancel_work_sync(&adapter->service_task);
7637
7638 #ifdef CONFIG_IXGBE_DCA
7639 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7640 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7641 dca_remove_requester(&pdev->dev);
7642 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7643 }
7644
7645 #endif
7646 #ifdef IXGBE_FCOE
7647 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7648 ixgbe_cleanup_fcoe(adapter);
7649
7650 #endif /* IXGBE_FCOE */
7651
7652 /* remove the added san mac */
7653 ixgbe_del_sanmac_netdev(netdev);
7654
7655 if (netdev->reg_state == NETREG_REGISTERED)
7656 unregister_netdev(netdev);
7657
7658 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7659 ixgbe_disable_sriov(adapter);
7660
7661 ixgbe_clear_interrupt_scheme(adapter);
7662
7663 ixgbe_release_hw_control(adapter);
7664
7665 iounmap(adapter->hw.hw_addr);
7666 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7667 IORESOURCE_MEM));
7668
7669 e_dev_info("complete\n");
7670
7671 free_netdev(netdev);
7672
7673 pci_disable_pcie_error_reporting(pdev);
7674
7675 pci_disable_device(pdev);
7676 }
7677
7678 /**
7679 * ixgbe_io_error_detected - called when PCI error is detected
7680 * @pdev: Pointer to PCI device
7681 * @state: The current pci connection state
7682 *
7683 * This function is called after a PCI bus error affecting
7684 * this device has been detected.
7685 */
7686 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7687 pci_channel_state_t state)
7688 {
7689 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7690 struct net_device *netdev = adapter->netdev;
7691
7692 netif_device_detach(netdev);
7693
7694 if (state == pci_channel_io_perm_failure)
7695 return PCI_ERS_RESULT_DISCONNECT;
7696
7697 if (netif_running(netdev))
7698 ixgbe_down(adapter);
7699 pci_disable_device(pdev);
7700
7701 /* Request a slot reset. */
7702 return PCI_ERS_RESULT_NEED_RESET;
7703 }
7704
7705 /**
7706 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7707 * @pdev: Pointer to PCI device
7708 *
7709 * Restart the card from scratch, as if from a cold-boot.
7710 */
7711 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7712 {
7713 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7714 pci_ers_result_t result;
7715 int err;
7716
7717 if (pci_enable_device_mem(pdev)) {
7718 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7719 result = PCI_ERS_RESULT_DISCONNECT;
7720 } else {
7721 pci_set_master(pdev);
7722 pci_restore_state(pdev);
7723 pci_save_state(pdev);
7724
7725 pci_wake_from_d3(pdev, false);
7726
7727 ixgbe_reset(adapter);
7728 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7729 result = PCI_ERS_RESULT_RECOVERED;
7730 }
7731
7732 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7733 if (err) {
7734 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7735 "failed 0x%0x\n", err);
7736 /* non-fatal, continue */
7737 }
7738
7739 return result;
7740 }
7741
7742 /**
7743 * ixgbe_io_resume - called when traffic can start flowing again.
7744 * @pdev: Pointer to PCI device
7745 *
7746 * This callback is called when the error recovery driver tells us that
7747 * its OK to resume normal operation.
7748 */
7749 static void ixgbe_io_resume(struct pci_dev *pdev)
7750 {
7751 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7752 struct net_device *netdev = adapter->netdev;
7753
7754 if (netif_running(netdev)) {
7755 if (ixgbe_up(adapter)) {
7756 e_info(probe, "ixgbe_up failed after reset\n");
7757 return;
7758 }
7759 }
7760
7761 netif_device_attach(netdev);
7762 }
7763
7764 static struct pci_error_handlers ixgbe_err_handler = {
7765 .error_detected = ixgbe_io_error_detected,
7766 .slot_reset = ixgbe_io_slot_reset,
7767 .resume = ixgbe_io_resume,
7768 };
7769
7770 static struct pci_driver ixgbe_driver = {
7771 .name = ixgbe_driver_name,
7772 .id_table = ixgbe_pci_tbl,
7773 .probe = ixgbe_probe,
7774 .remove = __devexit_p(ixgbe_remove),
7775 #ifdef CONFIG_PM
7776 .suspend = ixgbe_suspend,
7777 .resume = ixgbe_resume,
7778 #endif
7779 .shutdown = ixgbe_shutdown,
7780 .err_handler = &ixgbe_err_handler
7781 };
7782
7783 /**
7784 * ixgbe_init_module - Driver Registration Routine
7785 *
7786 * ixgbe_init_module is the first routine called when the driver is
7787 * loaded. All it does is register with the PCI subsystem.
7788 **/
7789 static int __init ixgbe_init_module(void)
7790 {
7791 int ret;
7792 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7793 pr_info("%s\n", ixgbe_copyright);
7794
7795 #ifdef CONFIG_IXGBE_DCA
7796 dca_register_notify(&dca_notifier);
7797 #endif
7798
7799 ret = pci_register_driver(&ixgbe_driver);
7800 return ret;
7801 }
7802
7803 module_init(ixgbe_init_module);
7804
7805 /**
7806 * ixgbe_exit_module - Driver Exit Cleanup Routine
7807 *
7808 * ixgbe_exit_module is called just before the driver is removed
7809 * from memory.
7810 **/
7811 static void __exit ixgbe_exit_module(void)
7812 {
7813 #ifdef CONFIG_IXGBE_DCA
7814 dca_unregister_notify(&dca_notifier);
7815 #endif
7816 pci_unregister_driver(&ixgbe_driver);
7817 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7818 }
7819
7820 #ifdef CONFIG_IXGBE_DCA
7821 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7822 void *p)
7823 {
7824 int ret_val;
7825
7826 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7827 __ixgbe_notify_dca);
7828
7829 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7830 }
7831
7832 #endif /* CONFIG_IXGBE_DCA */
7833
7834 module_exit(ixgbe_exit_module);
7835
7836 /* ixgbe_main.c */
Linux kernel - Deliverables
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