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Staging: Merge branch 'tidspbridge-for-2.6.39' of git://dev.omapzoom.org/pub/scm...
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <linux/slab.h>
40 #include <net/checksum.h>
41 #include <net/ip6_checksum.h>
42 #include <linux/ethtool.h>
43 #include <linux/if_vlan.h>
44 #include <scsi/fc/fc_fcoe.h>
45
46 #include "ixgbe.h"
47 #include "ixgbe_common.h"
48 #include "ixgbe_dcb_82599.h"
49 #include "ixgbe_sriov.h"
50
51 char ixgbe_driver_name[] = "ixgbe";
52 static const char ixgbe_driver_string[] =
53 "Intel(R) 10 Gigabit PCI Express Network Driver";
54
55 #define DRV_VERSION "3.0.12-k2"
56 const char ixgbe_driver_version[] = DRV_VERSION;
57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
58
59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
60 [board_82598] = &ixgbe_82598_info,
61 [board_82599] = &ixgbe_82599_info,
62 [board_X540] = &ixgbe_X540_info,
63 };
64
65 /* ixgbe_pci_tbl - PCI Device ID Table
66 *
67 * Wildcard entries (PCI_ANY_ID) should come last
68 * Last entry must be all 0s
69 *
70 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
71 * Class, Class Mask, private data (not used) }
72 */
73 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
75 board_82598 },
76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
77 board_82598 },
78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
79 board_82598 },
80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
81 board_82598 },
82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
83 board_82598 },
84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
85 board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
87 board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
89 board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
91 board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
93 board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
95 board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
97 board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
99 board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
101 board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
103 board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
105 board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
107 board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
109 board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
111 board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
113 board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
115 board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
117 board_82599 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
119 board_82599 },
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
121 board_X540 },
122
123 /* required last entry */
124 {0, }
125 };
126 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
127
128 #ifdef CONFIG_IXGBE_DCA
129 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
130 void *p);
131 static struct notifier_block dca_notifier = {
132 .notifier_call = ixgbe_notify_dca,
133 .next = NULL,
134 .priority = 0
135 };
136 #endif
137
138 #ifdef CONFIG_PCI_IOV
139 static unsigned int max_vfs;
140 module_param(max_vfs, uint, 0);
141 MODULE_PARM_DESC(max_vfs,
142 "Maximum number of virtual functions to allocate per physical function");
143 #endif /* CONFIG_PCI_IOV */
144
145 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
146 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
147 MODULE_LICENSE("GPL");
148 MODULE_VERSION(DRV_VERSION);
149
150 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
151
152 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
153 {
154 struct ixgbe_hw *hw = &adapter->hw;
155 u32 gcr;
156 u32 gpie;
157 u32 vmdctl;
158
159 #ifdef CONFIG_PCI_IOV
160 /* disable iov and allow time for transactions to clear */
161 pci_disable_sriov(adapter->pdev);
162 #endif
163
164 /* turn off device IOV mode */
165 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
166 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
167 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
168 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
169 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
170 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
171
172 /* set default pool back to 0 */
173 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
174 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
175 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
176
177 /* take a breather then clean up driver data */
178 msleep(100);
179
180 kfree(adapter->vfinfo);
181 adapter->vfinfo = NULL;
182
183 adapter->num_vfs = 0;
184 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
185 }
186
187 struct ixgbe_reg_info {
188 u32 ofs;
189 char *name;
190 };
191
192 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
193
194 /* General Registers */
195 {IXGBE_CTRL, "CTRL"},
196 {IXGBE_STATUS, "STATUS"},
197 {IXGBE_CTRL_EXT, "CTRL_EXT"},
198
199 /* Interrupt Registers */
200 {IXGBE_EICR, "EICR"},
201
202 /* RX Registers */
203 {IXGBE_SRRCTL(0), "SRRCTL"},
204 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
205 {IXGBE_RDLEN(0), "RDLEN"},
206 {IXGBE_RDH(0), "RDH"},
207 {IXGBE_RDT(0), "RDT"},
208 {IXGBE_RXDCTL(0), "RXDCTL"},
209 {IXGBE_RDBAL(0), "RDBAL"},
210 {IXGBE_RDBAH(0), "RDBAH"},
211
212 /* TX Registers */
213 {IXGBE_TDBAL(0), "TDBAL"},
214 {IXGBE_TDBAH(0), "TDBAH"},
215 {IXGBE_TDLEN(0), "TDLEN"},
216 {IXGBE_TDH(0), "TDH"},
217 {IXGBE_TDT(0), "TDT"},
218 {IXGBE_TXDCTL(0), "TXDCTL"},
219
220 /* List Terminator */
221 {}
222 };
223
224
225 /*
226 * ixgbe_regdump - register printout routine
227 */
228 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
229 {
230 int i = 0, j = 0;
231 char rname[16];
232 u32 regs[64];
233
234 switch (reginfo->ofs) {
235 case IXGBE_SRRCTL(0):
236 for (i = 0; i < 64; i++)
237 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
238 break;
239 case IXGBE_DCA_RXCTRL(0):
240 for (i = 0; i < 64; i++)
241 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
242 break;
243 case IXGBE_RDLEN(0):
244 for (i = 0; i < 64; i++)
245 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
246 break;
247 case IXGBE_RDH(0):
248 for (i = 0; i < 64; i++)
249 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
250 break;
251 case IXGBE_RDT(0):
252 for (i = 0; i < 64; i++)
253 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
254 break;
255 case IXGBE_RXDCTL(0):
256 for (i = 0; i < 64; i++)
257 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
258 break;
259 case IXGBE_RDBAL(0):
260 for (i = 0; i < 64; i++)
261 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
262 break;
263 case IXGBE_RDBAH(0):
264 for (i = 0; i < 64; i++)
265 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
266 break;
267 case IXGBE_TDBAL(0):
268 for (i = 0; i < 64; i++)
269 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
270 break;
271 case IXGBE_TDBAH(0):
272 for (i = 0; i < 64; i++)
273 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
274 break;
275 case IXGBE_TDLEN(0):
276 for (i = 0; i < 64; i++)
277 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
278 break;
279 case IXGBE_TDH(0):
280 for (i = 0; i < 64; i++)
281 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
282 break;
283 case IXGBE_TDT(0):
284 for (i = 0; i < 64; i++)
285 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
286 break;
287 case IXGBE_TXDCTL(0):
288 for (i = 0; i < 64; i++)
289 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
290 break;
291 default:
292 pr_info("%-15s %08x\n", reginfo->name,
293 IXGBE_READ_REG(hw, reginfo->ofs));
294 return;
295 }
296
297 for (i = 0; i < 8; i++) {
298 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
299 pr_err("%-15s", rname);
300 for (j = 0; j < 8; j++)
301 pr_cont(" %08x", regs[i*8+j]);
302 pr_cont("\n");
303 }
304
305 }
306
307 /*
308 * ixgbe_dump - Print registers, tx-rings and rx-rings
309 */
310 static void ixgbe_dump(struct ixgbe_adapter *adapter)
311 {
312 struct net_device *netdev = adapter->netdev;
313 struct ixgbe_hw *hw = &adapter->hw;
314 struct ixgbe_reg_info *reginfo;
315 int n = 0;
316 struct ixgbe_ring *tx_ring;
317 struct ixgbe_tx_buffer *tx_buffer_info;
318 union ixgbe_adv_tx_desc *tx_desc;
319 struct my_u0 { u64 a; u64 b; } *u0;
320 struct ixgbe_ring *rx_ring;
321 union ixgbe_adv_rx_desc *rx_desc;
322 struct ixgbe_rx_buffer *rx_buffer_info;
323 u32 staterr;
324 int i = 0;
325
326 if (!netif_msg_hw(adapter))
327 return;
328
329 /* Print netdevice Info */
330 if (netdev) {
331 dev_info(&adapter->pdev->dev, "Net device Info\n");
332 pr_info("Device Name state "
333 "trans_start last_rx\n");
334 pr_info("%-15s %016lX %016lX %016lX\n",
335 netdev->name,
336 netdev->state,
337 netdev->trans_start,
338 netdev->last_rx);
339 }
340
341 /* Print Registers */
342 dev_info(&adapter->pdev->dev, "Register Dump\n");
343 pr_info(" Register Name Value\n");
344 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
345 reginfo->name; reginfo++) {
346 ixgbe_regdump(hw, reginfo);
347 }
348
349 /* Print TX Ring Summary */
350 if (!netdev || !netif_running(netdev))
351 goto exit;
352
353 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
354 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
355 for (n = 0; n < adapter->num_tx_queues; n++) {
356 tx_ring = adapter->tx_ring[n];
357 tx_buffer_info =
358 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
359 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
360 n, tx_ring->next_to_use, tx_ring->next_to_clean,
361 (u64)tx_buffer_info->dma,
362 tx_buffer_info->length,
363 tx_buffer_info->next_to_watch,
364 (u64)tx_buffer_info->time_stamp);
365 }
366
367 /* Print TX Rings */
368 if (!netif_msg_tx_done(adapter))
369 goto rx_ring_summary;
370
371 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
372
373 /* Transmit Descriptor Formats
374 *
375 * Advanced Transmit Descriptor
376 * +--------------------------------------------------------------+
377 * 0 | Buffer Address [63:0] |
378 * +--------------------------------------------------------------+
379 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
380 * +--------------------------------------------------------------+
381 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
382 */
383
384 for (n = 0; n < adapter->num_tx_queues; n++) {
385 tx_ring = adapter->tx_ring[n];
386 pr_info("------------------------------------\n");
387 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
388 pr_info("------------------------------------\n");
389 pr_info("T [desc] [address 63:0 ] "
390 "[PlPOIdStDDt Ln] [bi->dma ] "
391 "leng ntw timestamp bi->skb\n");
392
393 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
394 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
395 tx_buffer_info = &tx_ring->tx_buffer_info[i];
396 u0 = (struct my_u0 *)tx_desc;
397 pr_info("T [0x%03X] %016llX %016llX %016llX"
398 " %04X %3X %016llX %p", i,
399 le64_to_cpu(u0->a),
400 le64_to_cpu(u0->b),
401 (u64)tx_buffer_info->dma,
402 tx_buffer_info->length,
403 tx_buffer_info->next_to_watch,
404 (u64)tx_buffer_info->time_stamp,
405 tx_buffer_info->skb);
406 if (i == tx_ring->next_to_use &&
407 i == tx_ring->next_to_clean)
408 pr_cont(" NTC/U\n");
409 else if (i == tx_ring->next_to_use)
410 pr_cont(" NTU\n");
411 else if (i == tx_ring->next_to_clean)
412 pr_cont(" NTC\n");
413 else
414 pr_cont("\n");
415
416 if (netif_msg_pktdata(adapter) &&
417 tx_buffer_info->dma != 0)
418 print_hex_dump(KERN_INFO, "",
419 DUMP_PREFIX_ADDRESS, 16, 1,
420 phys_to_virt(tx_buffer_info->dma),
421 tx_buffer_info->length, true);
422 }
423 }
424
425 /* Print RX Rings Summary */
426 rx_ring_summary:
427 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
428 pr_info("Queue [NTU] [NTC]\n");
429 for (n = 0; n < adapter->num_rx_queues; n++) {
430 rx_ring = adapter->rx_ring[n];
431 pr_info("%5d %5X %5X\n",
432 n, rx_ring->next_to_use, rx_ring->next_to_clean);
433 }
434
435 /* Print RX Rings */
436 if (!netif_msg_rx_status(adapter))
437 goto exit;
438
439 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
440
441 /* Advanced Receive Descriptor (Read) Format
442 * 63 1 0
443 * +-----------------------------------------------------+
444 * 0 | Packet Buffer Address [63:1] |A0/NSE|
445 * +----------------------------------------------+------+
446 * 8 | Header Buffer Address [63:1] | DD |
447 * +-----------------------------------------------------+
448 *
449 *
450 * Advanced Receive Descriptor (Write-Back) Format
451 *
452 * 63 48 47 32 31 30 21 20 16 15 4 3 0
453 * +------------------------------------------------------+
454 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
455 * | Checksum Ident | | | | Type | Type |
456 * +------------------------------------------------------+
457 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
458 * +------------------------------------------------------+
459 * 63 48 47 32 31 20 19 0
460 */
461 for (n = 0; n < adapter->num_rx_queues; n++) {
462 rx_ring = adapter->rx_ring[n];
463 pr_info("------------------------------------\n");
464 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
465 pr_info("------------------------------------\n");
466 pr_info("R [desc] [ PktBuf A0] "
467 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
468 "<-- Adv Rx Read format\n");
469 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
470 "[vl er S cks ln] ---------------- [bi->skb] "
471 "<-- Adv Rx Write-Back format\n");
472
473 for (i = 0; i < rx_ring->count; i++) {
474 rx_buffer_info = &rx_ring->rx_buffer_info[i];
475 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
476 u0 = (struct my_u0 *)rx_desc;
477 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
478 if (staterr & IXGBE_RXD_STAT_DD) {
479 /* Descriptor Done */
480 pr_info("RWB[0x%03X] %016llX "
481 "%016llX ---------------- %p", i,
482 le64_to_cpu(u0->a),
483 le64_to_cpu(u0->b),
484 rx_buffer_info->skb);
485 } else {
486 pr_info("R [0x%03X] %016llX "
487 "%016llX %016llX %p", i,
488 le64_to_cpu(u0->a),
489 le64_to_cpu(u0->b),
490 (u64)rx_buffer_info->dma,
491 rx_buffer_info->skb);
492
493 if (netif_msg_pktdata(adapter)) {
494 print_hex_dump(KERN_INFO, "",
495 DUMP_PREFIX_ADDRESS, 16, 1,
496 phys_to_virt(rx_buffer_info->dma),
497 rx_ring->rx_buf_len, true);
498
499 if (rx_ring->rx_buf_len
500 < IXGBE_RXBUFFER_2048)
501 print_hex_dump(KERN_INFO, "",
502 DUMP_PREFIX_ADDRESS, 16, 1,
503 phys_to_virt(
504 rx_buffer_info->page_dma +
505 rx_buffer_info->page_offset
506 ),
507 PAGE_SIZE/2, true);
508 }
509 }
510
511 if (i == rx_ring->next_to_use)
512 pr_cont(" NTU\n");
513 else if (i == rx_ring->next_to_clean)
514 pr_cont(" NTC\n");
515 else
516 pr_cont("\n");
517
518 }
519 }
520
521 exit:
522 return;
523 }
524
525 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
526 {
527 u32 ctrl_ext;
528
529 /* Let firmware take over control of h/w */
530 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
531 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
532 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
533 }
534
535 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
536 {
537 u32 ctrl_ext;
538
539 /* Let firmware know the driver has taken over */
540 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
541 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
542 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
543 }
544
545 /*
546 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
547 * @adapter: pointer to adapter struct
548 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
549 * @queue: queue to map the corresponding interrupt to
550 * @msix_vector: the vector to map to the corresponding queue
551 *
552 */
553 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
554 u8 queue, u8 msix_vector)
555 {
556 u32 ivar, index;
557 struct ixgbe_hw *hw = &adapter->hw;
558 switch (hw->mac.type) {
559 case ixgbe_mac_82598EB:
560 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
561 if (direction == -1)
562 direction = 0;
563 index = (((direction * 64) + queue) >> 2) & 0x1F;
564 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
565 ivar &= ~(0xFF << (8 * (queue & 0x3)));
566 ivar |= (msix_vector << (8 * (queue & 0x3)));
567 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
568 break;
569 case ixgbe_mac_82599EB:
570 case ixgbe_mac_X540:
571 if (direction == -1) {
572 /* other causes */
573 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
574 index = ((queue & 1) * 8);
575 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
576 ivar &= ~(0xFF << index);
577 ivar |= (msix_vector << index);
578 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
579 break;
580 } else {
581 /* tx or rx causes */
582 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
583 index = ((16 * (queue & 1)) + (8 * direction));
584 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
585 ivar &= ~(0xFF << index);
586 ivar |= (msix_vector << index);
587 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
588 break;
589 }
590 default:
591 break;
592 }
593 }
594
595 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
596 u64 qmask)
597 {
598 u32 mask;
599
600 switch (adapter->hw.mac.type) {
601 case ixgbe_mac_82598EB:
602 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
603 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
604 break;
605 case ixgbe_mac_82599EB:
606 case ixgbe_mac_X540:
607 mask = (qmask & 0xFFFFFFFF);
608 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
609 mask = (qmask >> 32);
610 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
611 break;
612 default:
613 break;
614 }
615 }
616
617 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
618 struct ixgbe_tx_buffer *tx_buffer_info)
619 {
620 if (tx_buffer_info->dma) {
621 if (tx_buffer_info->mapped_as_page)
622 dma_unmap_page(tx_ring->dev,
623 tx_buffer_info->dma,
624 tx_buffer_info->length,
625 DMA_TO_DEVICE);
626 else
627 dma_unmap_single(tx_ring->dev,
628 tx_buffer_info->dma,
629 tx_buffer_info->length,
630 DMA_TO_DEVICE);
631 tx_buffer_info->dma = 0;
632 }
633 if (tx_buffer_info->skb) {
634 dev_kfree_skb_any(tx_buffer_info->skb);
635 tx_buffer_info->skb = NULL;
636 }
637 tx_buffer_info->time_stamp = 0;
638 /* tx_buffer_info must be completely set up in the transmit path */
639 }
640
641 /**
642 * ixgbe_dcb_txq_to_tc - convert a reg index to a traffic class
643 * @adapter: driver private struct
644 * @index: reg idx of queue to query (0-127)
645 *
646 * Helper function to determine the traffic index for a paticular
647 * register index.
648 *
649 * Returns : a tc index for use in range 0-7, or 0-3
650 */
651 u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx)
652 {
653 int tc = -1;
654 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
655
656 /* if DCB is not enabled the queues have no TC */
657 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
658 return tc;
659
660 /* check valid range */
661 if (reg_idx >= adapter->hw.mac.max_tx_queues)
662 return tc;
663
664 switch (adapter->hw.mac.type) {
665 case ixgbe_mac_82598EB:
666 tc = reg_idx >> 2;
667 break;
668 default:
669 if (dcb_i != 4 && dcb_i != 8)
670 break;
671
672 /* if VMDq is enabled the lowest order bits determine TC */
673 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
674 IXGBE_FLAG_VMDQ_ENABLED)) {
675 tc = reg_idx & (dcb_i - 1);
676 break;
677 }
678
679 /*
680 * Convert the reg_idx into the correct TC. This bitmask
681 * targets the last full 32 ring traffic class and assigns
682 * it a value of 1. From there the rest of the rings are
683 * based on shifting the mask further up to include the
684 * reg_idx / 16 and then reg_idx / 8. It assumes dcB_i
685 * will only ever be 8 or 4 and that reg_idx will never
686 * be greater then 128. The code without the power of 2
687 * optimizations would be:
688 * (((reg_idx % 32) + 32) * dcb_i) >> (9 - reg_idx / 32)
689 */
690 tc = ((reg_idx & 0X1F) + 0x20) * dcb_i;
691 tc >>= 9 - (reg_idx >> 5);
692 }
693
694 return tc;
695 }
696
697 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
698 {
699 struct ixgbe_hw *hw = &adapter->hw;
700 struct ixgbe_hw_stats *hwstats = &adapter->stats;
701 u32 data = 0;
702 u32 xoff[8] = {0};
703 int i;
704
705 if ((hw->fc.current_mode == ixgbe_fc_full) ||
706 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
707 switch (hw->mac.type) {
708 case ixgbe_mac_82598EB:
709 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
710 break;
711 default:
712 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
713 }
714 hwstats->lxoffrxc += data;
715
716 /* refill credits (no tx hang) if we received xoff */
717 if (!data)
718 return;
719
720 for (i = 0; i < adapter->num_tx_queues; i++)
721 clear_bit(__IXGBE_HANG_CHECK_ARMED,
722 &adapter->tx_ring[i]->state);
723 return;
724 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
725 return;
726
727 /* update stats for each tc, only valid with PFC enabled */
728 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
729 switch (hw->mac.type) {
730 case ixgbe_mac_82598EB:
731 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
732 break;
733 default:
734 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
735 }
736 hwstats->pxoffrxc[i] += xoff[i];
737 }
738
739 /* disarm tx queues that have received xoff frames */
740 for (i = 0; i < adapter->num_tx_queues; i++) {
741 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
742 u32 tc = ixgbe_dcb_txq_to_tc(adapter, tx_ring->reg_idx);
743
744 if (xoff[tc])
745 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
746 }
747 }
748
749 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
750 {
751 return ring->tx_stats.completed;
752 }
753
754 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
755 {
756 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
757 struct ixgbe_hw *hw = &adapter->hw;
758
759 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
760 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
761
762 if (head != tail)
763 return (head < tail) ?
764 tail - head : (tail + ring->count - head);
765
766 return 0;
767 }
768
769 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
770 {
771 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
772 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
773 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
774 bool ret = false;
775
776 clear_check_for_tx_hang(tx_ring);
777
778 /*
779 * Check for a hung queue, but be thorough. This verifies
780 * that a transmit has been completed since the previous
781 * check AND there is at least one packet pending. The
782 * ARMED bit is set to indicate a potential hang. The
783 * bit is cleared if a pause frame is received to remove
784 * false hang detection due to PFC or 802.3x frames. By
785 * requiring this to fail twice we avoid races with
786 * pfc clearing the ARMED bit and conditions where we
787 * run the check_tx_hang logic with a transmit completion
788 * pending but without time to complete it yet.
789 */
790 if ((tx_done_old == tx_done) && tx_pending) {
791 /* make sure it is true for two checks in a row */
792 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
793 &tx_ring->state);
794 } else {
795 /* update completed stats and continue */
796 tx_ring->tx_stats.tx_done_old = tx_done;
797 /* reset the countdown */
798 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
799 }
800
801 return ret;
802 }
803
804 #define IXGBE_MAX_TXD_PWR 14
805 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
806
807 /* Tx Descriptors needed, worst case */
808 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
809 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
810 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
811 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
812
813 static void ixgbe_tx_timeout(struct net_device *netdev);
814
815 /**
816 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
817 * @q_vector: structure containing interrupt and ring information
818 * @tx_ring: tx ring to clean
819 **/
820 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
821 struct ixgbe_ring *tx_ring)
822 {
823 struct ixgbe_adapter *adapter = q_vector->adapter;
824 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
825 struct ixgbe_tx_buffer *tx_buffer_info;
826 unsigned int total_bytes = 0, total_packets = 0;
827 u16 i, eop, count = 0;
828
829 i = tx_ring->next_to_clean;
830 eop = tx_ring->tx_buffer_info[i].next_to_watch;
831 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
832
833 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
834 (count < tx_ring->work_limit)) {
835 bool cleaned = false;
836 rmb(); /* read buffer_info after eop_desc */
837 for ( ; !cleaned; count++) {
838 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
839 tx_buffer_info = &tx_ring->tx_buffer_info[i];
840
841 tx_desc->wb.status = 0;
842 cleaned = (i == eop);
843
844 i++;
845 if (i == tx_ring->count)
846 i = 0;
847
848 if (cleaned && tx_buffer_info->skb) {
849 total_bytes += tx_buffer_info->bytecount;
850 total_packets += tx_buffer_info->gso_segs;
851 }
852
853 ixgbe_unmap_and_free_tx_resource(tx_ring,
854 tx_buffer_info);
855 }
856
857 tx_ring->tx_stats.completed++;
858 eop = tx_ring->tx_buffer_info[i].next_to_watch;
859 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
860 }
861
862 tx_ring->next_to_clean = i;
863 tx_ring->total_bytes += total_bytes;
864 tx_ring->total_packets += total_packets;
865 u64_stats_update_begin(&tx_ring->syncp);
866 tx_ring->stats.packets += total_packets;
867 tx_ring->stats.bytes += total_bytes;
868 u64_stats_update_end(&tx_ring->syncp);
869
870 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
871 /* schedule immediate reset if we believe we hung */
872 struct ixgbe_hw *hw = &adapter->hw;
873 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
874 e_err(drv, "Detected Tx Unit Hang\n"
875 " Tx Queue <%d>\n"
876 " TDH, TDT <%x>, <%x>\n"
877 " next_to_use <%x>\n"
878 " next_to_clean <%x>\n"
879 "tx_buffer_info[next_to_clean]\n"
880 " time_stamp <%lx>\n"
881 " jiffies <%lx>\n",
882 tx_ring->queue_index,
883 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
884 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
885 tx_ring->next_to_use, eop,
886 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
887
888 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
889
890 e_info(probe,
891 "tx hang %d detected on queue %d, resetting adapter\n",
892 adapter->tx_timeout_count + 1, tx_ring->queue_index);
893
894 /* schedule immediate reset if we believe we hung */
895 ixgbe_tx_timeout(adapter->netdev);
896
897 /* the adapter is about to reset, no point in enabling stuff */
898 return true;
899 }
900
901 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
902 if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
903 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
904 /* Make sure that anybody stopping the queue after this
905 * sees the new next_to_clean.
906 */
907 smp_mb();
908 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
909 !test_bit(__IXGBE_DOWN, &adapter->state)) {
910 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
911 ++tx_ring->tx_stats.restart_queue;
912 }
913 }
914
915 return count < tx_ring->work_limit;
916 }
917
918 #ifdef CONFIG_IXGBE_DCA
919 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
920 struct ixgbe_ring *rx_ring,
921 int cpu)
922 {
923 struct ixgbe_hw *hw = &adapter->hw;
924 u32 rxctrl;
925 u8 reg_idx = rx_ring->reg_idx;
926
927 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
928 switch (hw->mac.type) {
929 case ixgbe_mac_82598EB:
930 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
931 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
932 break;
933 case ixgbe_mac_82599EB:
934 case ixgbe_mac_X540:
935 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
936 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
937 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
938 break;
939 default:
940 break;
941 }
942 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
943 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
944 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
945 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
946 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
947 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
948 }
949
950 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
951 struct ixgbe_ring *tx_ring,
952 int cpu)
953 {
954 struct ixgbe_hw *hw = &adapter->hw;
955 u32 txctrl;
956 u8 reg_idx = tx_ring->reg_idx;
957
958 switch (hw->mac.type) {
959 case ixgbe_mac_82598EB:
960 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
961 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
962 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
963 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
964 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
965 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
966 break;
967 case ixgbe_mac_82599EB:
968 case ixgbe_mac_X540:
969 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
970 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
971 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
972 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
973 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
974 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
975 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
976 break;
977 default:
978 break;
979 }
980 }
981
982 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
983 {
984 struct ixgbe_adapter *adapter = q_vector->adapter;
985 int cpu = get_cpu();
986 long r_idx;
987 int i;
988
989 if (q_vector->cpu == cpu)
990 goto out_no_update;
991
992 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
993 for (i = 0; i < q_vector->txr_count; i++) {
994 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
995 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
996 r_idx + 1);
997 }
998
999 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1000 for (i = 0; i < q_vector->rxr_count; i++) {
1001 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
1002 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1003 r_idx + 1);
1004 }
1005
1006 q_vector->cpu = cpu;
1007 out_no_update:
1008 put_cpu();
1009 }
1010
1011 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1012 {
1013 int num_q_vectors;
1014 int i;
1015
1016 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1017 return;
1018
1019 /* always use CB2 mode, difference is masked in the CB driver */
1020 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1021
1022 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1023 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1024 else
1025 num_q_vectors = 1;
1026
1027 for (i = 0; i < num_q_vectors; i++) {
1028 adapter->q_vector[i]->cpu = -1;
1029 ixgbe_update_dca(adapter->q_vector[i]);
1030 }
1031 }
1032
1033 static int __ixgbe_notify_dca(struct device *dev, void *data)
1034 {
1035 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1036 unsigned long event = *(unsigned long *)data;
1037
1038 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1039 return 0;
1040
1041 switch (event) {
1042 case DCA_PROVIDER_ADD:
1043 /* if we're already enabled, don't do it again */
1044 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1045 break;
1046 if (dca_add_requester(dev) == 0) {
1047 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1048 ixgbe_setup_dca(adapter);
1049 break;
1050 }
1051 /* Fall Through since DCA is disabled. */
1052 case DCA_PROVIDER_REMOVE:
1053 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1054 dca_remove_requester(dev);
1055 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1056 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1057 }
1058 break;
1059 }
1060
1061 return 0;
1062 }
1063
1064 #endif /* CONFIG_IXGBE_DCA */
1065 /**
1066 * ixgbe_receive_skb - Send a completed packet up the stack
1067 * @adapter: board private structure
1068 * @skb: packet to send up
1069 * @status: hardware indication of status of receive
1070 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1071 * @rx_desc: rx descriptor
1072 **/
1073 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1074 struct sk_buff *skb, u8 status,
1075 struct ixgbe_ring *ring,
1076 union ixgbe_adv_rx_desc *rx_desc)
1077 {
1078 struct ixgbe_adapter *adapter = q_vector->adapter;
1079 struct napi_struct *napi = &q_vector->napi;
1080 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1081 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1082
1083 if (is_vlan && (tag & VLAN_VID_MASK))
1084 __vlan_hwaccel_put_tag(skb, tag);
1085
1086 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1087 napi_gro_receive(napi, skb);
1088 else
1089 netif_rx(skb);
1090 }
1091
1092 /**
1093 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1094 * @adapter: address of board private structure
1095 * @status_err: hardware indication of status of receive
1096 * @skb: skb currently being received and modified
1097 **/
1098 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1099 union ixgbe_adv_rx_desc *rx_desc,
1100 struct sk_buff *skb)
1101 {
1102 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
1103
1104 skb_checksum_none_assert(skb);
1105
1106 /* Rx csum disabled */
1107 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1108 return;
1109
1110 /* if IP and error */
1111 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1112 (status_err & IXGBE_RXDADV_ERR_IPE)) {
1113 adapter->hw_csum_rx_error++;
1114 return;
1115 }
1116
1117 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1118 return;
1119
1120 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1121 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1122
1123 /*
1124 * 82599 errata, UDP frames with a 0 checksum can be marked as
1125 * checksum errors.
1126 */
1127 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1128 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1129 return;
1130
1131 adapter->hw_csum_rx_error++;
1132 return;
1133 }
1134
1135 /* It must be a TCP or UDP packet with a valid checksum */
1136 skb->ip_summed = CHECKSUM_UNNECESSARY;
1137 }
1138
1139 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1140 {
1141 /*
1142 * Force memory writes to complete before letting h/w
1143 * know there are new descriptors to fetch. (Only
1144 * applicable for weak-ordered memory model archs,
1145 * such as IA-64).
1146 */
1147 wmb();
1148 writel(val, rx_ring->tail);
1149 }
1150
1151 /**
1152 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1153 * @rx_ring: ring to place buffers on
1154 * @cleaned_count: number of buffers to replace
1155 **/
1156 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1157 {
1158 union ixgbe_adv_rx_desc *rx_desc;
1159 struct ixgbe_rx_buffer *bi;
1160 struct sk_buff *skb;
1161 u16 i = rx_ring->next_to_use;
1162
1163 /* do nothing if no valid netdev defined */
1164 if (!rx_ring->netdev)
1165 return;
1166
1167 while (cleaned_count--) {
1168 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1169 bi = &rx_ring->rx_buffer_info[i];
1170 skb = bi->skb;
1171
1172 if (!skb) {
1173 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1174 rx_ring->rx_buf_len);
1175 if (!skb) {
1176 rx_ring->rx_stats.alloc_rx_buff_failed++;
1177 goto no_buffers;
1178 }
1179 /* initialize queue mapping */
1180 skb_record_rx_queue(skb, rx_ring->queue_index);
1181 bi->skb = skb;
1182 }
1183
1184 if (!bi->dma) {
1185 bi->dma = dma_map_single(rx_ring->dev,
1186 skb->data,
1187 rx_ring->rx_buf_len,
1188 DMA_FROM_DEVICE);
1189 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1190 rx_ring->rx_stats.alloc_rx_buff_failed++;
1191 bi->dma = 0;
1192 goto no_buffers;
1193 }
1194 }
1195
1196 if (ring_is_ps_enabled(rx_ring)) {
1197 if (!bi->page) {
1198 bi->page = netdev_alloc_page(rx_ring->netdev);
1199 if (!bi->page) {
1200 rx_ring->rx_stats.alloc_rx_page_failed++;
1201 goto no_buffers;
1202 }
1203 }
1204
1205 if (!bi->page_dma) {
1206 /* use a half page if we're re-using */
1207 bi->page_offset ^= PAGE_SIZE / 2;
1208 bi->page_dma = dma_map_page(rx_ring->dev,
1209 bi->page,
1210 bi->page_offset,
1211 PAGE_SIZE / 2,
1212 DMA_FROM_DEVICE);
1213 if (dma_mapping_error(rx_ring->dev,
1214 bi->page_dma)) {
1215 rx_ring->rx_stats.alloc_rx_page_failed++;
1216 bi->page_dma = 0;
1217 goto no_buffers;
1218 }
1219 }
1220
1221 /* Refresh the desc even if buffer_addrs didn't change
1222 * because each write-back erases this info. */
1223 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1224 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1225 } else {
1226 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1227 rx_desc->read.hdr_addr = 0;
1228 }
1229
1230 i++;
1231 if (i == rx_ring->count)
1232 i = 0;
1233 }
1234
1235 no_buffers:
1236 if (rx_ring->next_to_use != i) {
1237 rx_ring->next_to_use = i;
1238 ixgbe_release_rx_desc(rx_ring, i);
1239 }
1240 }
1241
1242 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1243 {
1244 /* HW will not DMA in data larger than the given buffer, even if it
1245 * parses the (NFS, of course) header to be larger. In that case, it
1246 * fills the header buffer and spills the rest into the page.
1247 */
1248 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1249 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1250 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1251 if (hlen > IXGBE_RX_HDR_SIZE)
1252 hlen = IXGBE_RX_HDR_SIZE;
1253 return hlen;
1254 }
1255
1256 /**
1257 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1258 * @skb: pointer to the last skb in the rsc queue
1259 *
1260 * This function changes a queue full of hw rsc buffers into a completed
1261 * packet. It uses the ->prev pointers to find the first packet and then
1262 * turns it into the frag list owner.
1263 **/
1264 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1265 {
1266 unsigned int frag_list_size = 0;
1267 unsigned int skb_cnt = 1;
1268
1269 while (skb->prev) {
1270 struct sk_buff *prev = skb->prev;
1271 frag_list_size += skb->len;
1272 skb->prev = NULL;
1273 skb = prev;
1274 skb_cnt++;
1275 }
1276
1277 skb_shinfo(skb)->frag_list = skb->next;
1278 skb->next = NULL;
1279 skb->len += frag_list_size;
1280 skb->data_len += frag_list_size;
1281 skb->truesize += frag_list_size;
1282 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1283
1284 return skb;
1285 }
1286
1287 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1288 {
1289 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1290 IXGBE_RXDADV_RSCCNT_MASK);
1291 }
1292
1293 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1294 struct ixgbe_ring *rx_ring,
1295 int *work_done, int work_to_do)
1296 {
1297 struct ixgbe_adapter *adapter = q_vector->adapter;
1298 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1299 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1300 struct sk_buff *skb;
1301 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1302 const int current_node = numa_node_id();
1303 #ifdef IXGBE_FCOE
1304 int ddp_bytes = 0;
1305 #endif /* IXGBE_FCOE */
1306 u32 staterr;
1307 u16 i;
1308 u16 cleaned_count = 0;
1309 bool pkt_is_rsc = false;
1310
1311 i = rx_ring->next_to_clean;
1312 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1313 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1314
1315 while (staterr & IXGBE_RXD_STAT_DD) {
1316 u32 upper_len = 0;
1317
1318 rmb(); /* read descriptor and rx_buffer_info after status DD */
1319
1320 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1321
1322 skb = rx_buffer_info->skb;
1323 rx_buffer_info->skb = NULL;
1324 prefetch(skb->data);
1325
1326 if (ring_is_rsc_enabled(rx_ring))
1327 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1328
1329 /* if this is a skb from previous receive DMA will be 0 */
1330 if (rx_buffer_info->dma) {
1331 u16 hlen;
1332 if (pkt_is_rsc &&
1333 !(staterr & IXGBE_RXD_STAT_EOP) &&
1334 !skb->prev) {
1335 /*
1336 * When HWRSC is enabled, delay unmapping
1337 * of the first packet. It carries the
1338 * header information, HW may still
1339 * access the header after the writeback.
1340 * Only unmap it when EOP is reached
1341 */
1342 IXGBE_RSC_CB(skb)->delay_unmap = true;
1343 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1344 } else {
1345 dma_unmap_single(rx_ring->dev,
1346 rx_buffer_info->dma,
1347 rx_ring->rx_buf_len,
1348 DMA_FROM_DEVICE);
1349 }
1350 rx_buffer_info->dma = 0;
1351
1352 if (ring_is_ps_enabled(rx_ring)) {
1353 hlen = ixgbe_get_hlen(rx_desc);
1354 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1355 } else {
1356 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1357 }
1358
1359 skb_put(skb, hlen);
1360 } else {
1361 /* assume packet split since header is unmapped */
1362 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1363 }
1364
1365 if (upper_len) {
1366 dma_unmap_page(rx_ring->dev,
1367 rx_buffer_info->page_dma,
1368 PAGE_SIZE / 2,
1369 DMA_FROM_DEVICE);
1370 rx_buffer_info->page_dma = 0;
1371 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1372 rx_buffer_info->page,
1373 rx_buffer_info->page_offset,
1374 upper_len);
1375
1376 if ((page_count(rx_buffer_info->page) == 1) &&
1377 (page_to_nid(rx_buffer_info->page) == current_node))
1378 get_page(rx_buffer_info->page);
1379 else
1380 rx_buffer_info->page = NULL;
1381
1382 skb->len += upper_len;
1383 skb->data_len += upper_len;
1384 skb->truesize += upper_len;
1385 }
1386
1387 i++;
1388 if (i == rx_ring->count)
1389 i = 0;
1390
1391 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1392 prefetch(next_rxd);
1393 cleaned_count++;
1394
1395 if (pkt_is_rsc) {
1396 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1397 IXGBE_RXDADV_NEXTP_SHIFT;
1398 next_buffer = &rx_ring->rx_buffer_info[nextp];
1399 } else {
1400 next_buffer = &rx_ring->rx_buffer_info[i];
1401 }
1402
1403 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1404 if (ring_is_ps_enabled(rx_ring)) {
1405 rx_buffer_info->skb = next_buffer->skb;
1406 rx_buffer_info->dma = next_buffer->dma;
1407 next_buffer->skb = skb;
1408 next_buffer->dma = 0;
1409 } else {
1410 skb->next = next_buffer->skb;
1411 skb->next->prev = skb;
1412 }
1413 rx_ring->rx_stats.non_eop_descs++;
1414 goto next_desc;
1415 }
1416
1417 if (skb->prev) {
1418 skb = ixgbe_transform_rsc_queue(skb);
1419 /* if we got here without RSC the packet is invalid */
1420 if (!pkt_is_rsc) {
1421 __pskb_trim(skb, 0);
1422 rx_buffer_info->skb = skb;
1423 goto next_desc;
1424 }
1425 }
1426
1427 if (ring_is_rsc_enabled(rx_ring)) {
1428 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1429 dma_unmap_single(rx_ring->dev,
1430 IXGBE_RSC_CB(skb)->dma,
1431 rx_ring->rx_buf_len,
1432 DMA_FROM_DEVICE);
1433 IXGBE_RSC_CB(skb)->dma = 0;
1434 IXGBE_RSC_CB(skb)->delay_unmap = false;
1435 }
1436 }
1437 if (pkt_is_rsc) {
1438 if (ring_is_ps_enabled(rx_ring))
1439 rx_ring->rx_stats.rsc_count +=
1440 skb_shinfo(skb)->nr_frags;
1441 else
1442 rx_ring->rx_stats.rsc_count +=
1443 IXGBE_RSC_CB(skb)->skb_cnt;
1444 rx_ring->rx_stats.rsc_flush++;
1445 }
1446
1447 /* ERR_MASK will only have valid bits if EOP set */
1448 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1449 /* trim packet back to size 0 and recycle it */
1450 __pskb_trim(skb, 0);
1451 rx_buffer_info->skb = skb;
1452 goto next_desc;
1453 }
1454
1455 ixgbe_rx_checksum(adapter, rx_desc, skb);
1456
1457 /* probably a little skewed due to removing CRC */
1458 total_rx_bytes += skb->len;
1459 total_rx_packets++;
1460
1461 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1462 #ifdef IXGBE_FCOE
1463 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1464 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1465 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1466 if (!ddp_bytes)
1467 goto next_desc;
1468 }
1469 #endif /* IXGBE_FCOE */
1470 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1471
1472 next_desc:
1473 rx_desc->wb.upper.status_error = 0;
1474
1475 (*work_done)++;
1476 if (*work_done >= work_to_do)
1477 break;
1478
1479 /* return some buffers to hardware, one at a time is too slow */
1480 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1481 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1482 cleaned_count = 0;
1483 }
1484
1485 /* use prefetched values */
1486 rx_desc = next_rxd;
1487 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1488 }
1489
1490 rx_ring->next_to_clean = i;
1491 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1492
1493 if (cleaned_count)
1494 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1495
1496 #ifdef IXGBE_FCOE
1497 /* include DDPed FCoE data */
1498 if (ddp_bytes > 0) {
1499 unsigned int mss;
1500
1501 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1502 sizeof(struct fc_frame_header) -
1503 sizeof(struct fcoe_crc_eof);
1504 if (mss > 512)
1505 mss &= ~511;
1506 total_rx_bytes += ddp_bytes;
1507 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1508 }
1509 #endif /* IXGBE_FCOE */
1510
1511 rx_ring->total_packets += total_rx_packets;
1512 rx_ring->total_bytes += total_rx_bytes;
1513 u64_stats_update_begin(&rx_ring->syncp);
1514 rx_ring->stats.packets += total_rx_packets;
1515 rx_ring->stats.bytes += total_rx_bytes;
1516 u64_stats_update_end(&rx_ring->syncp);
1517 }
1518
1519 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1520 /**
1521 * ixgbe_configure_msix - Configure MSI-X hardware
1522 * @adapter: board private structure
1523 *
1524 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1525 * interrupts.
1526 **/
1527 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1528 {
1529 struct ixgbe_q_vector *q_vector;
1530 int i, q_vectors, v_idx, r_idx;
1531 u32 mask;
1532
1533 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1534
1535 /*
1536 * Populate the IVAR table and set the ITR values to the
1537 * corresponding register.
1538 */
1539 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1540 q_vector = adapter->q_vector[v_idx];
1541 /* XXX for_each_set_bit(...) */
1542 r_idx = find_first_bit(q_vector->rxr_idx,
1543 adapter->num_rx_queues);
1544
1545 for (i = 0; i < q_vector->rxr_count; i++) {
1546 u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1547 ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
1548 r_idx = find_next_bit(q_vector->rxr_idx,
1549 adapter->num_rx_queues,
1550 r_idx + 1);
1551 }
1552 r_idx = find_first_bit(q_vector->txr_idx,
1553 adapter->num_tx_queues);
1554
1555 for (i = 0; i < q_vector->txr_count; i++) {
1556 u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1557 ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
1558 r_idx = find_next_bit(q_vector->txr_idx,
1559 adapter->num_tx_queues,
1560 r_idx + 1);
1561 }
1562
1563 if (q_vector->txr_count && !q_vector->rxr_count)
1564 /* tx only */
1565 q_vector->eitr = adapter->tx_eitr_param;
1566 else if (q_vector->rxr_count)
1567 /* rx or mixed */
1568 q_vector->eitr = adapter->rx_eitr_param;
1569
1570 ixgbe_write_eitr(q_vector);
1571 /* If Flow Director is enabled, set interrupt affinity */
1572 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1573 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1574 /*
1575 * Allocate the affinity_hint cpumask, assign the mask
1576 * for this vector, and set our affinity_hint for
1577 * this irq.
1578 */
1579 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1580 GFP_KERNEL))
1581 return;
1582 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1583 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1584 q_vector->affinity_mask);
1585 }
1586 }
1587
1588 switch (adapter->hw.mac.type) {
1589 case ixgbe_mac_82598EB:
1590 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1591 v_idx);
1592 break;
1593 case ixgbe_mac_82599EB:
1594 case ixgbe_mac_X540:
1595 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1596 break;
1597
1598 default:
1599 break;
1600 }
1601 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1602
1603 /* set up to autoclear timer, and the vectors */
1604 mask = IXGBE_EIMS_ENABLE_MASK;
1605 if (adapter->num_vfs)
1606 mask &= ~(IXGBE_EIMS_OTHER |
1607 IXGBE_EIMS_MAILBOX |
1608 IXGBE_EIMS_LSC);
1609 else
1610 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1611 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1612 }
1613
1614 enum latency_range {
1615 lowest_latency = 0,
1616 low_latency = 1,
1617 bulk_latency = 2,
1618 latency_invalid = 255
1619 };
1620
1621 /**
1622 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1623 * @adapter: pointer to adapter
1624 * @eitr: eitr setting (ints per sec) to give last timeslice
1625 * @itr_setting: current throttle rate in ints/second
1626 * @packets: the number of packets during this measurement interval
1627 * @bytes: the number of bytes during this measurement interval
1628 *
1629 * Stores a new ITR value based on packets and byte
1630 * counts during the last interrupt. The advantage of per interrupt
1631 * computation is faster updates and more accurate ITR for the current
1632 * traffic pattern. Constants in this function were computed
1633 * based on theoretical maximum wire speed and thresholds were set based
1634 * on testing data as well as attempting to minimize response time
1635 * while increasing bulk throughput.
1636 * this functionality is controlled by the InterruptThrottleRate module
1637 * parameter (see ixgbe_param.c)
1638 **/
1639 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1640 u32 eitr, u8 itr_setting,
1641 int packets, int bytes)
1642 {
1643 unsigned int retval = itr_setting;
1644 u32 timepassed_us;
1645 u64 bytes_perint;
1646
1647 if (packets == 0)
1648 goto update_itr_done;
1649
1650
1651 /* simple throttlerate management
1652 * 0-20MB/s lowest (100000 ints/s)
1653 * 20-100MB/s low (20000 ints/s)
1654 * 100-1249MB/s bulk (8000 ints/s)
1655 */
1656 /* what was last interrupt timeslice? */
1657 timepassed_us = 1000000/eitr;
1658 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1659
1660 switch (itr_setting) {
1661 case lowest_latency:
1662 if (bytes_perint > adapter->eitr_low)
1663 retval = low_latency;
1664 break;
1665 case low_latency:
1666 if (bytes_perint > adapter->eitr_high)
1667 retval = bulk_latency;
1668 else if (bytes_perint <= adapter->eitr_low)
1669 retval = lowest_latency;
1670 break;
1671 case bulk_latency:
1672 if (bytes_perint <= adapter->eitr_high)
1673 retval = low_latency;
1674 break;
1675 }
1676
1677 update_itr_done:
1678 return retval;
1679 }
1680
1681 /**
1682 * ixgbe_write_eitr - write EITR register in hardware specific way
1683 * @q_vector: structure containing interrupt and ring information
1684 *
1685 * This function is made to be called by ethtool and by the driver
1686 * when it needs to update EITR registers at runtime. Hardware
1687 * specific quirks/differences are taken care of here.
1688 */
1689 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1690 {
1691 struct ixgbe_adapter *adapter = q_vector->adapter;
1692 struct ixgbe_hw *hw = &adapter->hw;
1693 int v_idx = q_vector->v_idx;
1694 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1695
1696 switch (adapter->hw.mac.type) {
1697 case ixgbe_mac_82598EB:
1698 /* must write high and low 16 bits to reset counter */
1699 itr_reg |= (itr_reg << 16);
1700 break;
1701 case ixgbe_mac_82599EB:
1702 case ixgbe_mac_X540:
1703 /*
1704 * 82599 and X540 can support a value of zero, so allow it for
1705 * max interrupt rate, but there is an errata where it can
1706 * not be zero with RSC
1707 */
1708 if (itr_reg == 8 &&
1709 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1710 itr_reg = 0;
1711
1712 /*
1713 * set the WDIS bit to not clear the timer bits and cause an
1714 * immediate assertion of the interrupt
1715 */
1716 itr_reg |= IXGBE_EITR_CNT_WDIS;
1717 break;
1718 default:
1719 break;
1720 }
1721 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1722 }
1723
1724 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1725 {
1726 struct ixgbe_adapter *adapter = q_vector->adapter;
1727 int i, r_idx;
1728 u32 new_itr;
1729 u8 current_itr, ret_itr;
1730
1731 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1732 for (i = 0; i < q_vector->txr_count; i++) {
1733 struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
1734 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1735 q_vector->tx_itr,
1736 tx_ring->total_packets,
1737 tx_ring->total_bytes);
1738 /* if the result for this queue would decrease interrupt
1739 * rate for this vector then use that result */
1740 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1741 q_vector->tx_itr - 1 : ret_itr);
1742 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1743 r_idx + 1);
1744 }
1745
1746 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1747 for (i = 0; i < q_vector->rxr_count; i++) {
1748 struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
1749 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1750 q_vector->rx_itr,
1751 rx_ring->total_packets,
1752 rx_ring->total_bytes);
1753 /* if the result for this queue would decrease interrupt
1754 * rate for this vector then use that result */
1755 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1756 q_vector->rx_itr - 1 : ret_itr);
1757 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1758 r_idx + 1);
1759 }
1760
1761 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1762
1763 switch (current_itr) {
1764 /* counts and packets in update_itr are dependent on these numbers */
1765 case lowest_latency:
1766 new_itr = 100000;
1767 break;
1768 case low_latency:
1769 new_itr = 20000; /* aka hwitr = ~200 */
1770 break;
1771 case bulk_latency:
1772 default:
1773 new_itr = 8000;
1774 break;
1775 }
1776
1777 if (new_itr != q_vector->eitr) {
1778 /* do an exponential smoothing */
1779 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1780
1781 /* save the algorithm value here, not the smoothed one */
1782 q_vector->eitr = new_itr;
1783
1784 ixgbe_write_eitr(q_vector);
1785 }
1786 }
1787
1788 /**
1789 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1790 * @work: pointer to work_struct containing our data
1791 **/
1792 static void ixgbe_check_overtemp_task(struct work_struct *work)
1793 {
1794 struct ixgbe_adapter *adapter = container_of(work,
1795 struct ixgbe_adapter,
1796 check_overtemp_task);
1797 struct ixgbe_hw *hw = &adapter->hw;
1798 u32 eicr = adapter->interrupt_event;
1799
1800 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1801 return;
1802
1803 switch (hw->device_id) {
1804 case IXGBE_DEV_ID_82599_T3_LOM: {
1805 u32 autoneg;
1806 bool link_up = false;
1807
1808 if (hw->mac.ops.check_link)
1809 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1810
1811 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1812 (eicr & IXGBE_EICR_LSC))
1813 /* Check if this is due to overtemp */
1814 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1815 break;
1816 return;
1817 }
1818 default:
1819 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1820 return;
1821 break;
1822 }
1823 e_crit(drv,
1824 "Network adapter has been stopped because it has over heated. "
1825 "Restart the computer. If the problem persists, "
1826 "power off the system and replace the adapter\n");
1827 /* write to clear the interrupt */
1828 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1829 }
1830
1831 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1832 {
1833 struct ixgbe_hw *hw = &adapter->hw;
1834
1835 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1836 (eicr & IXGBE_EICR_GPI_SDP1)) {
1837 e_crit(probe, "Fan has stopped, replace the adapter\n");
1838 /* write to clear the interrupt */
1839 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1840 }
1841 }
1842
1843 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1844 {
1845 struct ixgbe_hw *hw = &adapter->hw;
1846
1847 if (eicr & IXGBE_EICR_GPI_SDP2) {
1848 /* Clear the interrupt */
1849 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1850 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1851 schedule_work(&adapter->sfp_config_module_task);
1852 }
1853
1854 if (eicr & IXGBE_EICR_GPI_SDP1) {
1855 /* Clear the interrupt */
1856 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1857 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1858 schedule_work(&adapter->multispeed_fiber_task);
1859 }
1860 }
1861
1862 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1863 {
1864 struct ixgbe_hw *hw = &adapter->hw;
1865
1866 adapter->lsc_int++;
1867 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1868 adapter->link_check_timeout = jiffies;
1869 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1870 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1871 IXGBE_WRITE_FLUSH(hw);
1872 schedule_work(&adapter->watchdog_task);
1873 }
1874 }
1875
1876 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1877 {
1878 struct net_device *netdev = data;
1879 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1880 struct ixgbe_hw *hw = &adapter->hw;
1881 u32 eicr;
1882
1883 /*
1884 * Workaround for Silicon errata. Use clear-by-write instead
1885 * of clear-by-read. Reading with EICS will return the
1886 * interrupt causes without clearing, which later be done
1887 * with the write to EICR.
1888 */
1889 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1890 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1891
1892 if (eicr & IXGBE_EICR_LSC)
1893 ixgbe_check_lsc(adapter);
1894
1895 if (eicr & IXGBE_EICR_MAILBOX)
1896 ixgbe_msg_task(adapter);
1897
1898 switch (hw->mac.type) {
1899 case ixgbe_mac_82599EB:
1900 ixgbe_check_sfp_event(adapter, eicr);
1901 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1902 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1903 adapter->interrupt_event = eicr;
1904 schedule_work(&adapter->check_overtemp_task);
1905 }
1906 /* now fallthrough to handle Flow Director */
1907 case ixgbe_mac_X540:
1908 /* Handle Flow Director Full threshold interrupt */
1909 if (eicr & IXGBE_EICR_FLOW_DIR) {
1910 int i;
1911 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1912 /* Disable transmits before FDIR Re-initialization */
1913 netif_tx_stop_all_queues(netdev);
1914 for (i = 0; i < adapter->num_tx_queues; i++) {
1915 struct ixgbe_ring *tx_ring =
1916 adapter->tx_ring[i];
1917 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1918 &tx_ring->state))
1919 schedule_work(&adapter->fdir_reinit_task);
1920 }
1921 }
1922 break;
1923 default:
1924 break;
1925 }
1926
1927 ixgbe_check_fan_failure(adapter, eicr);
1928
1929 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1930 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1931
1932 return IRQ_HANDLED;
1933 }
1934
1935 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1936 u64 qmask)
1937 {
1938 u32 mask;
1939 struct ixgbe_hw *hw = &adapter->hw;
1940
1941 switch (hw->mac.type) {
1942 case ixgbe_mac_82598EB:
1943 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1944 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1945 break;
1946 case ixgbe_mac_82599EB:
1947 case ixgbe_mac_X540:
1948 mask = (qmask & 0xFFFFFFFF);
1949 if (mask)
1950 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1951 mask = (qmask >> 32);
1952 if (mask)
1953 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1954 break;
1955 default:
1956 break;
1957 }
1958 /* skip the flush */
1959 }
1960
1961 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1962 u64 qmask)
1963 {
1964 u32 mask;
1965 struct ixgbe_hw *hw = &adapter->hw;
1966
1967 switch (hw->mac.type) {
1968 case ixgbe_mac_82598EB:
1969 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1970 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1971 break;
1972 case ixgbe_mac_82599EB:
1973 case ixgbe_mac_X540:
1974 mask = (qmask & 0xFFFFFFFF);
1975 if (mask)
1976 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1977 mask = (qmask >> 32);
1978 if (mask)
1979 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1980 break;
1981 default:
1982 break;
1983 }
1984 /* skip the flush */
1985 }
1986
1987 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1988 {
1989 struct ixgbe_q_vector *q_vector = data;
1990 struct ixgbe_adapter *adapter = q_vector->adapter;
1991 struct ixgbe_ring *tx_ring;
1992 int i, r_idx;
1993
1994 if (!q_vector->txr_count)
1995 return IRQ_HANDLED;
1996
1997 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1998 for (i = 0; i < q_vector->txr_count; i++) {
1999 tx_ring = adapter->tx_ring[r_idx];
2000 tx_ring->total_bytes = 0;
2001 tx_ring->total_packets = 0;
2002 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2003 r_idx + 1);
2004 }
2005
2006 /* EIAM disabled interrupts (on this vector) for us */
2007 napi_schedule(&q_vector->napi);
2008
2009 return IRQ_HANDLED;
2010 }
2011
2012 /**
2013 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2014 * @irq: unused
2015 * @data: pointer to our q_vector struct for this interrupt vector
2016 **/
2017 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2018 {
2019 struct ixgbe_q_vector *q_vector = data;
2020 struct ixgbe_adapter *adapter = q_vector->adapter;
2021 struct ixgbe_ring *rx_ring;
2022 int r_idx;
2023 int i;
2024
2025 #ifdef CONFIG_IXGBE_DCA
2026 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2027 ixgbe_update_dca(q_vector);
2028 #endif
2029
2030 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2031 for (i = 0; i < q_vector->rxr_count; i++) {
2032 rx_ring = adapter->rx_ring[r_idx];
2033 rx_ring->total_bytes = 0;
2034 rx_ring->total_packets = 0;
2035 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2036 r_idx + 1);
2037 }
2038
2039 if (!q_vector->rxr_count)
2040 return IRQ_HANDLED;
2041
2042 /* EIAM disabled interrupts (on this vector) for us */
2043 napi_schedule(&q_vector->napi);
2044
2045 return IRQ_HANDLED;
2046 }
2047
2048 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2049 {
2050 struct ixgbe_q_vector *q_vector = data;
2051 struct ixgbe_adapter *adapter = q_vector->adapter;
2052 struct ixgbe_ring *ring;
2053 int r_idx;
2054 int i;
2055
2056 if (!q_vector->txr_count && !q_vector->rxr_count)
2057 return IRQ_HANDLED;
2058
2059 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2060 for (i = 0; i < q_vector->txr_count; i++) {
2061 ring = adapter->tx_ring[r_idx];
2062 ring->total_bytes = 0;
2063 ring->total_packets = 0;
2064 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2065 r_idx + 1);
2066 }
2067
2068 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2069 for (i = 0; i < q_vector->rxr_count; i++) {
2070 ring = adapter->rx_ring[r_idx];
2071 ring->total_bytes = 0;
2072 ring->total_packets = 0;
2073 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2074 r_idx + 1);
2075 }
2076
2077 /* EIAM disabled interrupts (on this vector) for us */
2078 napi_schedule(&q_vector->napi);
2079
2080 return IRQ_HANDLED;
2081 }
2082
2083 /**
2084 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2085 * @napi: napi struct with our devices info in it
2086 * @budget: amount of work driver is allowed to do this pass, in packets
2087 *
2088 * This function is optimized for cleaning one queue only on a single
2089 * q_vector!!!
2090 **/
2091 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2092 {
2093 struct ixgbe_q_vector *q_vector =
2094 container_of(napi, struct ixgbe_q_vector, napi);
2095 struct ixgbe_adapter *adapter = q_vector->adapter;
2096 struct ixgbe_ring *rx_ring = NULL;
2097 int work_done = 0;
2098 long r_idx;
2099
2100 #ifdef CONFIG_IXGBE_DCA
2101 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2102 ixgbe_update_dca(q_vector);
2103 #endif
2104
2105 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2106 rx_ring = adapter->rx_ring[r_idx];
2107
2108 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
2109
2110 /* If all Rx work done, exit the polling mode */
2111 if (work_done < budget) {
2112 napi_complete(napi);
2113 if (adapter->rx_itr_setting & 1)
2114 ixgbe_set_itr_msix(q_vector);
2115 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2116 ixgbe_irq_enable_queues(adapter,
2117 ((u64)1 << q_vector->v_idx));
2118 }
2119
2120 return work_done;
2121 }
2122
2123 /**
2124 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2125 * @napi: napi struct with our devices info in it
2126 * @budget: amount of work driver is allowed to do this pass, in packets
2127 *
2128 * This function will clean more than one rx queue associated with a
2129 * q_vector.
2130 **/
2131 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
2132 {
2133 struct ixgbe_q_vector *q_vector =
2134 container_of(napi, struct ixgbe_q_vector, napi);
2135 struct ixgbe_adapter *adapter = q_vector->adapter;
2136 struct ixgbe_ring *ring = NULL;
2137 int work_done = 0, i;
2138 long r_idx;
2139 bool tx_clean_complete = true;
2140
2141 #ifdef CONFIG_IXGBE_DCA
2142 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2143 ixgbe_update_dca(q_vector);
2144 #endif
2145
2146 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2147 for (i = 0; i < q_vector->txr_count; i++) {
2148 ring = adapter->tx_ring[r_idx];
2149 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2150 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2151 r_idx + 1);
2152 }
2153
2154 /* attempt to distribute budget to each queue fairly, but don't allow
2155 * the budget to go below 1 because we'll exit polling */
2156 budget /= (q_vector->rxr_count ?: 1);
2157 budget = max(budget, 1);
2158 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2159 for (i = 0; i < q_vector->rxr_count; i++) {
2160 ring = adapter->rx_ring[r_idx];
2161 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2162 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2163 r_idx + 1);
2164 }
2165
2166 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2167 ring = adapter->rx_ring[r_idx];
2168 /* If all Rx work done, exit the polling mode */
2169 if (work_done < budget) {
2170 napi_complete(napi);
2171 if (adapter->rx_itr_setting & 1)
2172 ixgbe_set_itr_msix(q_vector);
2173 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2174 ixgbe_irq_enable_queues(adapter,
2175 ((u64)1 << q_vector->v_idx));
2176 return 0;
2177 }
2178
2179 return work_done;
2180 }
2181
2182 /**
2183 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2184 * @napi: napi struct with our devices info in it
2185 * @budget: amount of work driver is allowed to do this pass, in packets
2186 *
2187 * This function is optimized for cleaning one queue only on a single
2188 * q_vector!!!
2189 **/
2190 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2191 {
2192 struct ixgbe_q_vector *q_vector =
2193 container_of(napi, struct ixgbe_q_vector, napi);
2194 struct ixgbe_adapter *adapter = q_vector->adapter;
2195 struct ixgbe_ring *tx_ring = NULL;
2196 int work_done = 0;
2197 long r_idx;
2198
2199 #ifdef CONFIG_IXGBE_DCA
2200 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2201 ixgbe_update_dca(q_vector);
2202 #endif
2203
2204 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2205 tx_ring = adapter->tx_ring[r_idx];
2206
2207 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2208 work_done = budget;
2209
2210 /* If all Tx work done, exit the polling mode */
2211 if (work_done < budget) {
2212 napi_complete(napi);
2213 if (adapter->tx_itr_setting & 1)
2214 ixgbe_set_itr_msix(q_vector);
2215 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2216 ixgbe_irq_enable_queues(adapter,
2217 ((u64)1 << q_vector->v_idx));
2218 }
2219
2220 return work_done;
2221 }
2222
2223 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2224 int r_idx)
2225 {
2226 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2227 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2228
2229 set_bit(r_idx, q_vector->rxr_idx);
2230 q_vector->rxr_count++;
2231 rx_ring->q_vector = q_vector;
2232 }
2233
2234 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2235 int t_idx)
2236 {
2237 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2238 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2239
2240 set_bit(t_idx, q_vector->txr_idx);
2241 q_vector->txr_count++;
2242 tx_ring->q_vector = q_vector;
2243 }
2244
2245 /**
2246 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2247 * @adapter: board private structure to initialize
2248 *
2249 * This function maps descriptor rings to the queue-specific vectors
2250 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2251 * one vector per ring/queue, but on a constrained vector budget, we
2252 * group the rings as "efficiently" as possible. You would add new
2253 * mapping configurations in here.
2254 **/
2255 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2256 {
2257 int q_vectors;
2258 int v_start = 0;
2259 int rxr_idx = 0, txr_idx = 0;
2260 int rxr_remaining = adapter->num_rx_queues;
2261 int txr_remaining = adapter->num_tx_queues;
2262 int i, j;
2263 int rqpv, tqpv;
2264 int err = 0;
2265
2266 /* No mapping required if MSI-X is disabled. */
2267 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2268 goto out;
2269
2270 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2271
2272 /*
2273 * The ideal configuration...
2274 * We have enough vectors to map one per queue.
2275 */
2276 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2277 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2278 map_vector_to_rxq(adapter, v_start, rxr_idx);
2279
2280 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2281 map_vector_to_txq(adapter, v_start, txr_idx);
2282
2283 goto out;
2284 }
2285
2286 /*
2287 * If we don't have enough vectors for a 1-to-1
2288 * mapping, we'll have to group them so there are
2289 * multiple queues per vector.
2290 */
2291 /* Re-adjusting *qpv takes care of the remainder. */
2292 for (i = v_start; i < q_vectors; i++) {
2293 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
2294 for (j = 0; j < rqpv; j++) {
2295 map_vector_to_rxq(adapter, i, rxr_idx);
2296 rxr_idx++;
2297 rxr_remaining--;
2298 }
2299 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
2300 for (j = 0; j < tqpv; j++) {
2301 map_vector_to_txq(adapter, i, txr_idx);
2302 txr_idx++;
2303 txr_remaining--;
2304 }
2305 }
2306 out:
2307 return err;
2308 }
2309
2310 /**
2311 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2312 * @adapter: board private structure
2313 *
2314 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2315 * interrupts from the kernel.
2316 **/
2317 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2318 {
2319 struct net_device *netdev = adapter->netdev;
2320 irqreturn_t (*handler)(int, void *);
2321 int i, vector, q_vectors, err;
2322 int ri = 0, ti = 0;
2323
2324 /* Decrement for Other and TCP Timer vectors */
2325 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2326
2327 err = ixgbe_map_rings_to_vectors(adapter);
2328 if (err)
2329 return err;
2330
2331 #define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \
2332 ? &ixgbe_msix_clean_many : \
2333 (_v)->rxr_count ? &ixgbe_msix_clean_rx : \
2334 (_v)->txr_count ? &ixgbe_msix_clean_tx : \
2335 NULL)
2336 for (vector = 0; vector < q_vectors; vector++) {
2337 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2338 handler = SET_HANDLER(q_vector);
2339
2340 if (handler == &ixgbe_msix_clean_rx) {
2341 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2342 "%s-%s-%d", netdev->name, "rx", ri++);
2343 } else if (handler == &ixgbe_msix_clean_tx) {
2344 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2345 "%s-%s-%d", netdev->name, "tx", ti++);
2346 } else if (handler == &ixgbe_msix_clean_many) {
2347 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2348 "%s-%s-%d", netdev->name, "TxRx", ri++);
2349 ti++;
2350 } else {
2351 /* skip this unused q_vector */
2352 continue;
2353 }
2354 err = request_irq(adapter->msix_entries[vector].vector,
2355 handler, 0, q_vector->name,
2356 q_vector);
2357 if (err) {
2358 e_err(probe, "request_irq failed for MSIX interrupt "
2359 "Error: %d\n", err);
2360 goto free_queue_irqs;
2361 }
2362 }
2363
2364 sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
2365 err = request_irq(adapter->msix_entries[vector].vector,
2366 ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev);
2367 if (err) {
2368 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2369 goto free_queue_irqs;
2370 }
2371
2372 return 0;
2373
2374 free_queue_irqs:
2375 for (i = vector - 1; i >= 0; i--)
2376 free_irq(adapter->msix_entries[--vector].vector,
2377 adapter->q_vector[i]);
2378 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2379 pci_disable_msix(adapter->pdev);
2380 kfree(adapter->msix_entries);
2381 adapter->msix_entries = NULL;
2382 return err;
2383 }
2384
2385 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2386 {
2387 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2388 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2389 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2390 u32 new_itr = q_vector->eitr;
2391 u8 current_itr;
2392
2393 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2394 q_vector->tx_itr,
2395 tx_ring->total_packets,
2396 tx_ring->total_bytes);
2397 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2398 q_vector->rx_itr,
2399 rx_ring->total_packets,
2400 rx_ring->total_bytes);
2401
2402 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2403
2404 switch (current_itr) {
2405 /* counts and packets in update_itr are dependent on these numbers */
2406 case lowest_latency:
2407 new_itr = 100000;
2408 break;
2409 case low_latency:
2410 new_itr = 20000; /* aka hwitr = ~200 */
2411 break;
2412 case bulk_latency:
2413 new_itr = 8000;
2414 break;
2415 default:
2416 break;
2417 }
2418
2419 if (new_itr != q_vector->eitr) {
2420 /* do an exponential smoothing */
2421 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
2422
2423 /* save the algorithm value here */
2424 q_vector->eitr = new_itr;
2425
2426 ixgbe_write_eitr(q_vector);
2427 }
2428 }
2429
2430 /**
2431 * ixgbe_irq_enable - Enable default interrupt generation settings
2432 * @adapter: board private structure
2433 **/
2434 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2435 bool flush)
2436 {
2437 u32 mask;
2438
2439 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2440 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2441 mask |= IXGBE_EIMS_GPI_SDP0;
2442 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2443 mask |= IXGBE_EIMS_GPI_SDP1;
2444 switch (adapter->hw.mac.type) {
2445 case ixgbe_mac_82599EB:
2446 case ixgbe_mac_X540:
2447 mask |= IXGBE_EIMS_ECC;
2448 mask |= IXGBE_EIMS_GPI_SDP1;
2449 mask |= IXGBE_EIMS_GPI_SDP2;
2450 if (adapter->num_vfs)
2451 mask |= IXGBE_EIMS_MAILBOX;
2452 break;
2453 default:
2454 break;
2455 }
2456 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2457 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2458 mask |= IXGBE_EIMS_FLOW_DIR;
2459
2460 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2461 if (queues)
2462 ixgbe_irq_enable_queues(adapter, ~0);
2463 if (flush)
2464 IXGBE_WRITE_FLUSH(&adapter->hw);
2465
2466 if (adapter->num_vfs > 32) {
2467 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2468 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2469 }
2470 }
2471
2472 /**
2473 * ixgbe_intr - legacy mode Interrupt Handler
2474 * @irq: interrupt number
2475 * @data: pointer to a network interface device structure
2476 **/
2477 static irqreturn_t ixgbe_intr(int irq, void *data)
2478 {
2479 struct net_device *netdev = data;
2480 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2481 struct ixgbe_hw *hw = &adapter->hw;
2482 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2483 u32 eicr;
2484
2485 /*
2486 * Workaround for silicon errata on 82598. Mask the interrupts
2487 * before the read of EICR.
2488 */
2489 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2490
2491 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2492 * therefore no explict interrupt disable is necessary */
2493 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2494 if (!eicr) {
2495 /*
2496 * shared interrupt alert!
2497 * make sure interrupts are enabled because the read will
2498 * have disabled interrupts due to EIAM
2499 * finish the workaround of silicon errata on 82598. Unmask
2500 * the interrupt that we masked before the EICR read.
2501 */
2502 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2503 ixgbe_irq_enable(adapter, true, true);
2504 return IRQ_NONE; /* Not our interrupt */
2505 }
2506
2507 if (eicr & IXGBE_EICR_LSC)
2508 ixgbe_check_lsc(adapter);
2509
2510 switch (hw->mac.type) {
2511 case ixgbe_mac_82599EB:
2512 ixgbe_check_sfp_event(adapter, eicr);
2513 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2514 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2515 adapter->interrupt_event = eicr;
2516 schedule_work(&adapter->check_overtemp_task);
2517 }
2518 break;
2519 default:
2520 break;
2521 }
2522
2523 ixgbe_check_fan_failure(adapter, eicr);
2524
2525 if (napi_schedule_prep(&(q_vector->napi))) {
2526 adapter->tx_ring[0]->total_packets = 0;
2527 adapter->tx_ring[0]->total_bytes = 0;
2528 adapter->rx_ring[0]->total_packets = 0;
2529 adapter->rx_ring[0]->total_bytes = 0;
2530 /* would disable interrupts here but EIAM disabled it */
2531 __napi_schedule(&(q_vector->napi));
2532 }
2533
2534 /*
2535 * re-enable link(maybe) and non-queue interrupts, no flush.
2536 * ixgbe_poll will re-enable the queue interrupts
2537 */
2538
2539 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2540 ixgbe_irq_enable(adapter, false, false);
2541
2542 return IRQ_HANDLED;
2543 }
2544
2545 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2546 {
2547 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2548
2549 for (i = 0; i < q_vectors; i++) {
2550 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2551 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2552 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2553 q_vector->rxr_count = 0;
2554 q_vector->txr_count = 0;
2555 }
2556 }
2557
2558 /**
2559 * ixgbe_request_irq - initialize interrupts
2560 * @adapter: board private structure
2561 *
2562 * Attempts to configure interrupts using the best available
2563 * capabilities of the hardware and kernel.
2564 **/
2565 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2566 {
2567 struct net_device *netdev = adapter->netdev;
2568 int err;
2569
2570 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2571 err = ixgbe_request_msix_irqs(adapter);
2572 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2573 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2574 netdev->name, netdev);
2575 } else {
2576 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2577 netdev->name, netdev);
2578 }
2579
2580 if (err)
2581 e_err(probe, "request_irq failed, Error %d\n", err);
2582
2583 return err;
2584 }
2585
2586 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2587 {
2588 struct net_device *netdev = adapter->netdev;
2589
2590 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2591 int i, q_vectors;
2592
2593 q_vectors = adapter->num_msix_vectors;
2594
2595 i = q_vectors - 1;
2596 free_irq(adapter->msix_entries[i].vector, netdev);
2597
2598 i--;
2599 for (; i >= 0; i--) {
2600 free_irq(adapter->msix_entries[i].vector,
2601 adapter->q_vector[i]);
2602 }
2603
2604 ixgbe_reset_q_vectors(adapter);
2605 } else {
2606 free_irq(adapter->pdev->irq, netdev);
2607 }
2608 }
2609
2610 /**
2611 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2612 * @adapter: board private structure
2613 **/
2614 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2615 {
2616 switch (adapter->hw.mac.type) {
2617 case ixgbe_mac_82598EB:
2618 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2619 break;
2620 case ixgbe_mac_82599EB:
2621 case ixgbe_mac_X540:
2622 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2623 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2624 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2625 if (adapter->num_vfs > 32)
2626 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2627 break;
2628 default:
2629 break;
2630 }
2631 IXGBE_WRITE_FLUSH(&adapter->hw);
2632 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2633 int i;
2634 for (i = 0; i < adapter->num_msix_vectors; i++)
2635 synchronize_irq(adapter->msix_entries[i].vector);
2636 } else {
2637 synchronize_irq(adapter->pdev->irq);
2638 }
2639 }
2640
2641 /**
2642 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2643 *
2644 **/
2645 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2646 {
2647 struct ixgbe_hw *hw = &adapter->hw;
2648
2649 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2650 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2651
2652 ixgbe_set_ivar(adapter, 0, 0, 0);
2653 ixgbe_set_ivar(adapter, 1, 0, 0);
2654
2655 map_vector_to_rxq(adapter, 0, 0);
2656 map_vector_to_txq(adapter, 0, 0);
2657
2658 e_info(hw, "Legacy interrupt IVAR setup done\n");
2659 }
2660
2661 /**
2662 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2663 * @adapter: board private structure
2664 * @ring: structure containing ring specific data
2665 *
2666 * Configure the Tx descriptor ring after a reset.
2667 **/
2668 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2669 struct ixgbe_ring *ring)
2670 {
2671 struct ixgbe_hw *hw = &adapter->hw;
2672 u64 tdba = ring->dma;
2673 int wait_loop = 10;
2674 u32 txdctl;
2675 u8 reg_idx = ring->reg_idx;
2676
2677 /* disable queue to avoid issues while updating state */
2678 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2679 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2680 txdctl & ~IXGBE_TXDCTL_ENABLE);
2681 IXGBE_WRITE_FLUSH(hw);
2682
2683 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2684 (tdba & DMA_BIT_MASK(32)));
2685 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2686 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2687 ring->count * sizeof(union ixgbe_adv_tx_desc));
2688 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2689 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2690 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2691
2692 /* configure fetching thresholds */
2693 if (adapter->rx_itr_setting == 0) {
2694 /* cannot set wthresh when itr==0 */
2695 txdctl &= ~0x007F0000;
2696 } else {
2697 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2698 txdctl |= (8 << 16);
2699 }
2700 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2701 /* PThresh workaround for Tx hang with DFP enabled. */
2702 txdctl |= 32;
2703 }
2704
2705 /* reinitialize flowdirector state */
2706 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2707 adapter->atr_sample_rate) {
2708 ring->atr_sample_rate = adapter->atr_sample_rate;
2709 ring->atr_count = 0;
2710 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2711 } else {
2712 ring->atr_sample_rate = 0;
2713 }
2714
2715 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2716
2717 /* enable queue */
2718 txdctl |= IXGBE_TXDCTL_ENABLE;
2719 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2720
2721 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2722 if (hw->mac.type == ixgbe_mac_82598EB &&
2723 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2724 return;
2725
2726 /* poll to verify queue is enabled */
2727 do {
2728 msleep(1);
2729 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2730 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2731 if (!wait_loop)
2732 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2733 }
2734
2735 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2736 {
2737 struct ixgbe_hw *hw = &adapter->hw;
2738 u32 rttdcs;
2739 u32 mask;
2740
2741 if (hw->mac.type == ixgbe_mac_82598EB)
2742 return;
2743
2744 /* disable the arbiter while setting MTQC */
2745 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2746 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2747 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2748
2749 /* set transmit pool layout */
2750 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2751 switch (adapter->flags & mask) {
2752
2753 case (IXGBE_FLAG_SRIOV_ENABLED):
2754 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2755 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2756 break;
2757
2758 case (IXGBE_FLAG_DCB_ENABLED):
2759 /* We enable 8 traffic classes, DCB only */
2760 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2761 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2762 break;
2763
2764 default:
2765 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2766 break;
2767 }
2768
2769 /* re-enable the arbiter */
2770 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2771 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2772 }
2773
2774 /**
2775 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2776 * @adapter: board private structure
2777 *
2778 * Configure the Tx unit of the MAC after a reset.
2779 **/
2780 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2781 {
2782 struct ixgbe_hw *hw = &adapter->hw;
2783 u32 dmatxctl;
2784 u32 i;
2785
2786 ixgbe_setup_mtqc(adapter);
2787
2788 if (hw->mac.type != ixgbe_mac_82598EB) {
2789 /* DMATXCTL.EN must be before Tx queues are enabled */
2790 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2791 dmatxctl |= IXGBE_DMATXCTL_TE;
2792 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2793 }
2794
2795 /* Setup the HW Tx Head and Tail descriptor pointers */
2796 for (i = 0; i < adapter->num_tx_queues; i++)
2797 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2798 }
2799
2800 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2801
2802 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2803 struct ixgbe_ring *rx_ring)
2804 {
2805 u32 srrctl;
2806 u8 reg_idx = rx_ring->reg_idx;
2807
2808 switch (adapter->hw.mac.type) {
2809 case ixgbe_mac_82598EB: {
2810 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2811 const int mask = feature[RING_F_RSS].mask;
2812 reg_idx = reg_idx & mask;
2813 }
2814 break;
2815 case ixgbe_mac_82599EB:
2816 case ixgbe_mac_X540:
2817 default:
2818 break;
2819 }
2820
2821 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2822
2823 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2824 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2825 if (adapter->num_vfs)
2826 srrctl |= IXGBE_SRRCTL_DROP_EN;
2827
2828 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2829 IXGBE_SRRCTL_BSIZEHDR_MASK;
2830
2831 if (ring_is_ps_enabled(rx_ring)) {
2832 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2833 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2834 #else
2835 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2836 #endif
2837 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2838 } else {
2839 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2840 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2841 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2842 }
2843
2844 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2845 }
2846
2847 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2848 {
2849 struct ixgbe_hw *hw = &adapter->hw;
2850 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2851 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2852 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2853 u32 mrqc = 0, reta = 0;
2854 u32 rxcsum;
2855 int i, j;
2856 int mask;
2857
2858 /* Fill out hash function seeds */
2859 for (i = 0; i < 10; i++)
2860 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2861
2862 /* Fill out redirection table */
2863 for (i = 0, j = 0; i < 128; i++, j++) {
2864 if (j == adapter->ring_feature[RING_F_RSS].indices)
2865 j = 0;
2866 /* reta = 4-byte sliding window of
2867 * 0x00..(indices-1)(indices-1)00..etc. */
2868 reta = (reta << 8) | (j * 0x11);
2869 if ((i & 3) == 3)
2870 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2871 }
2872
2873 /* Disable indicating checksum in descriptor, enables RSS hash */
2874 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2875 rxcsum |= IXGBE_RXCSUM_PCSD;
2876 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2877
2878 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2879 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2880 else
2881 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2882 #ifdef CONFIG_IXGBE_DCB
2883 | IXGBE_FLAG_DCB_ENABLED
2884 #endif
2885 | IXGBE_FLAG_SRIOV_ENABLED
2886 );
2887
2888 switch (mask) {
2889 case (IXGBE_FLAG_RSS_ENABLED):
2890 mrqc = IXGBE_MRQC_RSSEN;
2891 break;
2892 case (IXGBE_FLAG_SRIOV_ENABLED):
2893 mrqc = IXGBE_MRQC_VMDQEN;
2894 break;
2895 #ifdef CONFIG_IXGBE_DCB
2896 case (IXGBE_FLAG_DCB_ENABLED):
2897 mrqc = IXGBE_MRQC_RT8TCEN;
2898 break;
2899 #endif /* CONFIG_IXGBE_DCB */
2900 default:
2901 break;
2902 }
2903
2904 /* Perform hash on these packet types */
2905 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2906 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2907 | IXGBE_MRQC_RSS_FIELD_IPV6
2908 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2909
2910 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2911 }
2912
2913 /**
2914 * ixgbe_clear_rscctl - disable RSC for the indicated ring
2915 * @adapter: address of board private structure
2916 * @ring: structure containing ring specific data
2917 **/
2918 void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
2919 struct ixgbe_ring *ring)
2920 {
2921 struct ixgbe_hw *hw = &adapter->hw;
2922 u32 rscctrl;
2923 u8 reg_idx = ring->reg_idx;
2924
2925 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2926 rscctrl &= ~IXGBE_RSCCTL_RSCEN;
2927 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2928 }
2929
2930 /**
2931 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2932 * @adapter: address of board private structure
2933 * @index: index of ring to set
2934 **/
2935 void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2936 struct ixgbe_ring *ring)
2937 {
2938 struct ixgbe_hw *hw = &adapter->hw;
2939 u32 rscctrl;
2940 int rx_buf_len;
2941 u8 reg_idx = ring->reg_idx;
2942
2943 if (!ring_is_rsc_enabled(ring))
2944 return;
2945
2946 rx_buf_len = ring->rx_buf_len;
2947 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2948 rscctrl |= IXGBE_RSCCTL_RSCEN;
2949 /*
2950 * we must limit the number of descriptors so that the
2951 * total size of max desc * buf_len is not greater
2952 * than 65535
2953 */
2954 if (ring_is_ps_enabled(ring)) {
2955 #if (MAX_SKB_FRAGS > 16)
2956 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2957 #elif (MAX_SKB_FRAGS > 8)
2958 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2959 #elif (MAX_SKB_FRAGS > 4)
2960 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2961 #else
2962 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2963 #endif
2964 } else {
2965 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2966 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2967 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2968 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2969 else
2970 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2971 }
2972 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2973 }
2974
2975 /**
2976 * ixgbe_set_uta - Set unicast filter table address
2977 * @adapter: board private structure
2978 *
2979 * The unicast table address is a register array of 32-bit registers.
2980 * The table is meant to be used in a way similar to how the MTA is used
2981 * however due to certain limitations in the hardware it is necessary to
2982 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2983 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2984 **/
2985 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2986 {
2987 struct ixgbe_hw *hw = &adapter->hw;
2988 int i;
2989
2990 /* The UTA table only exists on 82599 hardware and newer */
2991 if (hw->mac.type < ixgbe_mac_82599EB)
2992 return;
2993
2994 /* we only need to do this if VMDq is enabled */
2995 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2996 return;
2997
2998 for (i = 0; i < 128; i++)
2999 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3000 }
3001
3002 #define IXGBE_MAX_RX_DESC_POLL 10
3003 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3004 struct ixgbe_ring *ring)
3005 {
3006 struct ixgbe_hw *hw = &adapter->hw;
3007 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3008 u32 rxdctl;
3009 u8 reg_idx = ring->reg_idx;
3010
3011 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3012 if (hw->mac.type == ixgbe_mac_82598EB &&
3013 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3014 return;
3015
3016 do {
3017 msleep(1);
3018 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3019 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3020
3021 if (!wait_loop) {
3022 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3023 "the polling period\n", reg_idx);
3024 }
3025 }
3026
3027 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3028 struct ixgbe_ring *ring)
3029 {
3030 struct ixgbe_hw *hw = &adapter->hw;
3031 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3032 u32 rxdctl;
3033 u8 reg_idx = ring->reg_idx;
3034
3035 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3036 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3037
3038 /* write value back with RXDCTL.ENABLE bit cleared */
3039 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3040
3041 if (hw->mac.type == ixgbe_mac_82598EB &&
3042 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3043 return;
3044
3045 /* the hardware may take up to 100us to really disable the rx queue */
3046 do {
3047 udelay(10);
3048 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3049 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3050
3051 if (!wait_loop) {
3052 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3053 "the polling period\n", reg_idx);
3054 }
3055 }
3056
3057 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3058 struct ixgbe_ring *ring)
3059 {
3060 struct ixgbe_hw *hw = &adapter->hw;
3061 u64 rdba = ring->dma;
3062 u32 rxdctl;
3063 u8 reg_idx = ring->reg_idx;
3064
3065 /* disable queue to avoid issues while updating state */
3066 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3067 ixgbe_disable_rx_queue(adapter, ring);
3068
3069 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3070 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3071 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3072 ring->count * sizeof(union ixgbe_adv_rx_desc));
3073 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3074 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3075 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3076
3077 ixgbe_configure_srrctl(adapter, ring);
3078 ixgbe_configure_rscctl(adapter, ring);
3079
3080 if (hw->mac.type == ixgbe_mac_82598EB) {
3081 /*
3082 * enable cache line friendly hardware writes:
3083 * PTHRESH=32 descriptors (half the internal cache),
3084 * this also removes ugly rx_no_buffer_count increment
3085 * HTHRESH=4 descriptors (to minimize latency on fetch)
3086 * WTHRESH=8 burst writeback up to two cache lines
3087 */
3088 rxdctl &= ~0x3FFFFF;
3089 rxdctl |= 0x080420;
3090 }
3091
3092 /* enable receive descriptor ring */
3093 rxdctl |= IXGBE_RXDCTL_ENABLE;
3094 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3095
3096 ixgbe_rx_desc_queue_enable(adapter, ring);
3097 ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
3098 }
3099
3100 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3101 {
3102 struct ixgbe_hw *hw = &adapter->hw;
3103 int p;
3104
3105 /* PSRTYPE must be initialized in non 82598 adapters */
3106 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3107 IXGBE_PSRTYPE_UDPHDR |
3108 IXGBE_PSRTYPE_IPV4HDR |
3109 IXGBE_PSRTYPE_L2HDR |
3110 IXGBE_PSRTYPE_IPV6HDR;
3111
3112 if (hw->mac.type == ixgbe_mac_82598EB)
3113 return;
3114
3115 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3116 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3117
3118 for (p = 0; p < adapter->num_rx_pools; p++)
3119 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3120 psrtype);
3121 }
3122
3123 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3124 {
3125 struct ixgbe_hw *hw = &adapter->hw;
3126 u32 gcr_ext;
3127 u32 vt_reg_bits;
3128 u32 reg_offset, vf_shift;
3129 u32 vmdctl;
3130
3131 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3132 return;
3133
3134 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3135 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3136 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3137 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3138
3139 vf_shift = adapter->num_vfs % 32;
3140 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3141
3142 /* Enable only the PF's pool for Tx/Rx */
3143 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3144 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3145 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3146 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3147 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3148
3149 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3150 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3151
3152 /*
3153 * Set up VF register offsets for selected VT Mode,
3154 * i.e. 32 or 64 VFs for SR-IOV
3155 */
3156 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3157 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3158 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3159 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3160
3161 /* enable Tx loopback for VF/PF communication */
3162 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3163 /* Enable MAC Anti-Spoofing */
3164 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3165 adapter->num_vfs);
3166 }
3167
3168 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3169 {
3170 struct ixgbe_hw *hw = &adapter->hw;
3171 struct net_device *netdev = adapter->netdev;
3172 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3173 int rx_buf_len;
3174 struct ixgbe_ring *rx_ring;
3175 int i;
3176 u32 mhadd, hlreg0;
3177
3178 /* Decide whether to use packet split mode or not */
3179 /* Do not use packet split if we're in SR-IOV Mode */
3180 if (!adapter->num_vfs)
3181 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3182
3183 /* Set the RX buffer length according to the mode */
3184 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3185 rx_buf_len = IXGBE_RX_HDR_SIZE;
3186 } else {
3187 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3188 (netdev->mtu <= ETH_DATA_LEN))
3189 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3190 else
3191 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
3192 }
3193
3194 #ifdef IXGBE_FCOE
3195 /* adjust max frame to be able to do baby jumbo for FCoE */
3196 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3197 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3198 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3199
3200 #endif /* IXGBE_FCOE */
3201 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3202 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3203 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3204 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3205
3206 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3207 }
3208
3209 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3210 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3211 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3212 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3213
3214 /*
3215 * Setup the HW Rx Head and Tail Descriptor Pointers and
3216 * the Base and Length of the Rx Descriptor Ring
3217 */
3218 for (i = 0; i < adapter->num_rx_queues; i++) {
3219 rx_ring = adapter->rx_ring[i];
3220 rx_ring->rx_buf_len = rx_buf_len;
3221
3222 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
3223 set_ring_ps_enabled(rx_ring);
3224 else
3225 clear_ring_ps_enabled(rx_ring);
3226
3227 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3228 set_ring_rsc_enabled(rx_ring);
3229 else
3230 clear_ring_rsc_enabled(rx_ring);
3231
3232 #ifdef IXGBE_FCOE
3233 if (netdev->features & NETIF_F_FCOE_MTU) {
3234 struct ixgbe_ring_feature *f;
3235 f = &adapter->ring_feature[RING_F_FCOE];
3236 if ((i >= f->mask) && (i < f->mask + f->indices)) {
3237 clear_ring_ps_enabled(rx_ring);
3238 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3239 rx_ring->rx_buf_len =
3240 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3241 } else if (!ring_is_rsc_enabled(rx_ring) &&
3242 !ring_is_ps_enabled(rx_ring)) {
3243 rx_ring->rx_buf_len =
3244 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3245 }
3246 }
3247 #endif /* IXGBE_FCOE */
3248 }
3249 }
3250
3251 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3252 {
3253 struct ixgbe_hw *hw = &adapter->hw;
3254 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3255
3256 switch (hw->mac.type) {
3257 case ixgbe_mac_82598EB:
3258 /*
3259 * For VMDq support of different descriptor types or
3260 * buffer sizes through the use of multiple SRRCTL
3261 * registers, RDRXCTL.MVMEN must be set to 1
3262 *
3263 * also, the manual doesn't mention it clearly but DCA hints
3264 * will only use queue 0's tags unless this bit is set. Side
3265 * effects of setting this bit are only that SRRCTL must be
3266 * fully programmed [0..15]
3267 */
3268 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3269 break;
3270 case ixgbe_mac_82599EB:
3271 case ixgbe_mac_X540:
3272 /* Disable RSC for ACK packets */
3273 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3274 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3275 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3276 /* hardware requires some bits to be set by default */
3277 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3278 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3279 break;
3280 default:
3281 /* We should do nothing since we don't know this hardware */
3282 return;
3283 }
3284
3285 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3286 }
3287
3288 /**
3289 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3290 * @adapter: board private structure
3291 *
3292 * Configure the Rx unit of the MAC after a reset.
3293 **/
3294 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3295 {
3296 struct ixgbe_hw *hw = &adapter->hw;
3297 int i;
3298 u32 rxctrl;
3299
3300 /* disable receives while setting up the descriptors */
3301 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3302 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3303
3304 ixgbe_setup_psrtype(adapter);
3305 ixgbe_setup_rdrxctl(adapter);
3306
3307 /* Program registers for the distribution of queues */
3308 ixgbe_setup_mrqc(adapter);
3309
3310 ixgbe_set_uta(adapter);
3311
3312 /* set_rx_buffer_len must be called before ring initialization */
3313 ixgbe_set_rx_buffer_len(adapter);
3314
3315 /*
3316 * Setup the HW Rx Head and Tail Descriptor Pointers and
3317 * the Base and Length of the Rx Descriptor Ring
3318 */
3319 for (i = 0; i < adapter->num_rx_queues; i++)
3320 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3321
3322 /* disable drop enable for 82598 parts */
3323 if (hw->mac.type == ixgbe_mac_82598EB)
3324 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3325
3326 /* enable all receives */
3327 rxctrl |= IXGBE_RXCTRL_RXEN;
3328 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3329 }
3330
3331 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3332 {
3333 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3334 struct ixgbe_hw *hw = &adapter->hw;
3335 int pool_ndx = adapter->num_vfs;
3336
3337 /* add VID to filter table */
3338 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3339 set_bit(vid, adapter->active_vlans);
3340 }
3341
3342 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3343 {
3344 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3345 struct ixgbe_hw *hw = &adapter->hw;
3346 int pool_ndx = adapter->num_vfs;
3347
3348 /* remove VID from filter table */
3349 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3350 clear_bit(vid, adapter->active_vlans);
3351 }
3352
3353 /**
3354 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3355 * @adapter: driver data
3356 */
3357 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3358 {
3359 struct ixgbe_hw *hw = &adapter->hw;
3360 u32 vlnctrl;
3361
3362 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3363 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3364 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3365 }
3366
3367 /**
3368 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3369 * @adapter: driver data
3370 */
3371 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3372 {
3373 struct ixgbe_hw *hw = &adapter->hw;
3374 u32 vlnctrl;
3375
3376 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3377 vlnctrl |= IXGBE_VLNCTRL_VFE;
3378 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3379 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3380 }
3381
3382 /**
3383 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3384 * @adapter: driver data
3385 */
3386 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3387 {
3388 struct ixgbe_hw *hw = &adapter->hw;
3389 u32 vlnctrl;
3390 int i, j;
3391
3392 switch (hw->mac.type) {
3393 case ixgbe_mac_82598EB:
3394 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3395 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3396 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3397 break;
3398 case ixgbe_mac_82599EB:
3399 case ixgbe_mac_X540:
3400 for (i = 0; i < adapter->num_rx_queues; i++) {
3401 j = adapter->rx_ring[i]->reg_idx;
3402 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3403 vlnctrl &= ~IXGBE_RXDCTL_VME;
3404 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3405 }
3406 break;
3407 default:
3408 break;
3409 }
3410 }
3411
3412 /**
3413 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3414 * @adapter: driver data
3415 */
3416 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3417 {
3418 struct ixgbe_hw *hw = &adapter->hw;
3419 u32 vlnctrl;
3420 int i, j;
3421
3422 switch (hw->mac.type) {
3423 case ixgbe_mac_82598EB:
3424 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3425 vlnctrl |= IXGBE_VLNCTRL_VME;
3426 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3427 break;
3428 case ixgbe_mac_82599EB:
3429 case ixgbe_mac_X540:
3430 for (i = 0; i < adapter->num_rx_queues; i++) {
3431 j = adapter->rx_ring[i]->reg_idx;
3432 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3433 vlnctrl |= IXGBE_RXDCTL_VME;
3434 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3435 }
3436 break;
3437 default:
3438 break;
3439 }
3440 }
3441
3442 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3443 {
3444 u16 vid;
3445
3446 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3447
3448 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3449 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3450 }
3451
3452 /**
3453 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3454 * @netdev: network interface device structure
3455 *
3456 * Writes unicast address list to the RAR table.
3457 * Returns: -ENOMEM on failure/insufficient address space
3458 * 0 on no addresses written
3459 * X on writing X addresses to the RAR table
3460 **/
3461 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3462 {
3463 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3464 struct ixgbe_hw *hw = &adapter->hw;
3465 unsigned int vfn = adapter->num_vfs;
3466 unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3467 int count = 0;
3468
3469 /* return ENOMEM indicating insufficient memory for addresses */
3470 if (netdev_uc_count(netdev) > rar_entries)
3471 return -ENOMEM;
3472
3473 if (!netdev_uc_empty(netdev) && rar_entries) {
3474 struct netdev_hw_addr *ha;
3475 /* return error if we do not support writing to RAR table */
3476 if (!hw->mac.ops.set_rar)
3477 return -ENOMEM;
3478
3479 netdev_for_each_uc_addr(ha, netdev) {
3480 if (!rar_entries)
3481 break;
3482 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3483 vfn, IXGBE_RAH_AV);
3484 count++;
3485 }
3486 }
3487 /* write the addresses in reverse order to avoid write combining */
3488 for (; rar_entries > 0 ; rar_entries--)
3489 hw->mac.ops.clear_rar(hw, rar_entries);
3490
3491 return count;
3492 }
3493
3494 /**
3495 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3496 * @netdev: network interface device structure
3497 *
3498 * The set_rx_method entry point is called whenever the unicast/multicast
3499 * address list or the network interface flags are updated. This routine is
3500 * responsible for configuring the hardware for proper unicast, multicast and
3501 * promiscuous mode.
3502 **/
3503 void ixgbe_set_rx_mode(struct net_device *netdev)
3504 {
3505 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3506 struct ixgbe_hw *hw = &adapter->hw;
3507 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3508 int count;
3509
3510 /* Check for Promiscuous and All Multicast modes */
3511
3512 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3513
3514 /* set all bits that we expect to always be set */
3515 fctrl |= IXGBE_FCTRL_BAM;
3516 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3517 fctrl |= IXGBE_FCTRL_PMCF;
3518
3519 /* clear the bits we are changing the status of */
3520 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3521
3522 if (netdev->flags & IFF_PROMISC) {
3523 hw->addr_ctrl.user_set_promisc = true;
3524 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3525 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3526 /* don't hardware filter vlans in promisc mode */
3527 ixgbe_vlan_filter_disable(adapter);
3528 } else {
3529 if (netdev->flags & IFF_ALLMULTI) {
3530 fctrl |= IXGBE_FCTRL_MPE;
3531 vmolr |= IXGBE_VMOLR_MPE;
3532 } else {
3533 /*
3534 * Write addresses to the MTA, if the attempt fails
3535 * then we should just turn on promiscous mode so
3536 * that we can at least receive multicast traffic
3537 */
3538 hw->mac.ops.update_mc_addr_list(hw, netdev);
3539 vmolr |= IXGBE_VMOLR_ROMPE;
3540 }
3541 ixgbe_vlan_filter_enable(adapter);
3542 hw->addr_ctrl.user_set_promisc = false;
3543 /*
3544 * Write addresses to available RAR registers, if there is not
3545 * sufficient space to store all the addresses then enable
3546 * unicast promiscous mode
3547 */
3548 count = ixgbe_write_uc_addr_list(netdev);
3549 if (count < 0) {
3550 fctrl |= IXGBE_FCTRL_UPE;
3551 vmolr |= IXGBE_VMOLR_ROPE;
3552 }
3553 }
3554
3555 if (adapter->num_vfs) {
3556 ixgbe_restore_vf_multicasts(adapter);
3557 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3558 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3559 IXGBE_VMOLR_ROPE);
3560 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3561 }
3562
3563 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3564
3565 if (netdev->features & NETIF_F_HW_VLAN_RX)
3566 ixgbe_vlan_strip_enable(adapter);
3567 else
3568 ixgbe_vlan_strip_disable(adapter);
3569 }
3570
3571 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3572 {
3573 int q_idx;
3574 struct ixgbe_q_vector *q_vector;
3575 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3576
3577 /* legacy and MSI only use one vector */
3578 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3579 q_vectors = 1;
3580
3581 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3582 struct napi_struct *napi;
3583 q_vector = adapter->q_vector[q_idx];
3584 napi = &q_vector->napi;
3585 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3586 if (!q_vector->rxr_count || !q_vector->txr_count) {
3587 if (q_vector->txr_count == 1)
3588 napi->poll = &ixgbe_clean_txonly;
3589 else if (q_vector->rxr_count == 1)
3590 napi->poll = &ixgbe_clean_rxonly;
3591 }
3592 }
3593
3594 napi_enable(napi);
3595 }
3596 }
3597
3598 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3599 {
3600 int q_idx;
3601 struct ixgbe_q_vector *q_vector;
3602 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3603
3604 /* legacy and MSI only use one vector */
3605 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3606 q_vectors = 1;
3607
3608 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3609 q_vector = adapter->q_vector[q_idx];
3610 napi_disable(&q_vector->napi);
3611 }
3612 }
3613
3614 #ifdef CONFIG_IXGBE_DCB
3615 /*
3616 * ixgbe_configure_dcb - Configure DCB hardware
3617 * @adapter: ixgbe adapter struct
3618 *
3619 * This is called by the driver on open to configure the DCB hardware.
3620 * This is also called by the gennetlink interface when reconfiguring
3621 * the DCB state.
3622 */
3623 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3624 {
3625 struct ixgbe_hw *hw = &adapter->hw;
3626 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3627
3628 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3629 if (hw->mac.type == ixgbe_mac_82598EB)
3630 netif_set_gso_max_size(adapter->netdev, 65536);
3631 return;
3632 }
3633
3634 if (hw->mac.type == ixgbe_mac_82598EB)
3635 netif_set_gso_max_size(adapter->netdev, 32768);
3636
3637 #ifdef CONFIG_FCOE
3638 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3639 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3640 #endif
3641
3642 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3643 DCB_TX_CONFIG);
3644 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3645 DCB_RX_CONFIG);
3646
3647 /* Enable VLAN tag insert/strip */
3648 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3649
3650 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3651
3652 /* reconfigure the hardware */
3653 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3654 }
3655
3656 #endif
3657 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3658 {
3659 struct net_device *netdev = adapter->netdev;
3660 struct ixgbe_hw *hw = &adapter->hw;
3661 int i;
3662
3663 #ifdef CONFIG_IXGBE_DCB
3664 ixgbe_configure_dcb(adapter);
3665 #endif
3666
3667 ixgbe_set_rx_mode(netdev);
3668 ixgbe_restore_vlan(adapter);
3669
3670 #ifdef IXGBE_FCOE
3671 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3672 ixgbe_configure_fcoe(adapter);
3673
3674 #endif /* IXGBE_FCOE */
3675 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3676 for (i = 0; i < adapter->num_tx_queues; i++)
3677 adapter->tx_ring[i]->atr_sample_rate =
3678 adapter->atr_sample_rate;
3679 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3680 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3681 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3682 }
3683 ixgbe_configure_virtualization(adapter);
3684
3685 ixgbe_configure_tx(adapter);
3686 ixgbe_configure_rx(adapter);
3687 }
3688
3689 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3690 {
3691 switch (hw->phy.type) {
3692 case ixgbe_phy_sfp_avago:
3693 case ixgbe_phy_sfp_ftl:
3694 case ixgbe_phy_sfp_intel:
3695 case ixgbe_phy_sfp_unknown:
3696 case ixgbe_phy_sfp_passive_tyco:
3697 case ixgbe_phy_sfp_passive_unknown:
3698 case ixgbe_phy_sfp_active_unknown:
3699 case ixgbe_phy_sfp_ftl_active:
3700 return true;
3701 default:
3702 return false;
3703 }
3704 }
3705
3706 /**
3707 * ixgbe_sfp_link_config - set up SFP+ link
3708 * @adapter: pointer to private adapter struct
3709 **/
3710 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3711 {
3712 struct ixgbe_hw *hw = &adapter->hw;
3713
3714 if (hw->phy.multispeed_fiber) {
3715 /*
3716 * In multispeed fiber setups, the device may not have
3717 * had a physical connection when the driver loaded.
3718 * If that's the case, the initial link configuration
3719 * couldn't get the MAC into 10G or 1G mode, so we'll
3720 * never have a link status change interrupt fire.
3721 * We need to try and force an autonegotiation
3722 * session, then bring up link.
3723 */
3724 hw->mac.ops.setup_sfp(hw);
3725 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3726 schedule_work(&adapter->multispeed_fiber_task);
3727 } else {
3728 /*
3729 * Direct Attach Cu and non-multispeed fiber modules
3730 * still need to be configured properly prior to
3731 * attempting link.
3732 */
3733 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3734 schedule_work(&adapter->sfp_config_module_task);
3735 }
3736 }
3737
3738 /**
3739 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3740 * @hw: pointer to private hardware struct
3741 *
3742 * Returns 0 on success, negative on failure
3743 **/
3744 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3745 {
3746 u32 autoneg;
3747 bool negotiation, link_up = false;
3748 u32 ret = IXGBE_ERR_LINK_SETUP;
3749
3750 if (hw->mac.ops.check_link)
3751 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3752
3753 if (ret)
3754 goto link_cfg_out;
3755
3756 if (hw->mac.ops.get_link_capabilities)
3757 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3758 &negotiation);
3759 if (ret)
3760 goto link_cfg_out;
3761
3762 if (hw->mac.ops.setup_link)
3763 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3764 link_cfg_out:
3765 return ret;
3766 }
3767
3768 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3769 {
3770 struct ixgbe_hw *hw = &adapter->hw;
3771 u32 gpie = 0;
3772
3773 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3774 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3775 IXGBE_GPIE_OCD;
3776 gpie |= IXGBE_GPIE_EIAME;
3777 /*
3778 * use EIAM to auto-mask when MSI-X interrupt is asserted
3779 * this saves a register write for every interrupt
3780 */
3781 switch (hw->mac.type) {
3782 case ixgbe_mac_82598EB:
3783 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3784 break;
3785 case ixgbe_mac_82599EB:
3786 case ixgbe_mac_X540:
3787 default:
3788 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3789 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3790 break;
3791 }
3792 } else {
3793 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3794 * specifically only auto mask tx and rx interrupts */
3795 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3796 }
3797
3798 /* XXX: to interrupt immediately for EICS writes, enable this */
3799 /* gpie |= IXGBE_GPIE_EIMEN; */
3800
3801 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3802 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3803 gpie |= IXGBE_GPIE_VTMODE_64;
3804 }
3805
3806 /* Enable fan failure interrupt */
3807 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3808 gpie |= IXGBE_SDP1_GPIEN;
3809
3810 if (hw->mac.type == ixgbe_mac_82599EB)
3811 gpie |= IXGBE_SDP1_GPIEN;
3812 gpie |= IXGBE_SDP2_GPIEN;
3813
3814 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3815 }
3816
3817 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3818 {
3819 struct ixgbe_hw *hw = &adapter->hw;
3820 int err;
3821 u32 ctrl_ext;
3822
3823 ixgbe_get_hw_control(adapter);
3824 ixgbe_setup_gpie(adapter);
3825
3826 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3827 ixgbe_configure_msix(adapter);
3828 else
3829 ixgbe_configure_msi_and_legacy(adapter);
3830
3831 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3832 if (hw->mac.ops.enable_tx_laser &&
3833 ((hw->phy.multispeed_fiber) ||
3834 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3835 (hw->mac.type == ixgbe_mac_82599EB))))
3836 hw->mac.ops.enable_tx_laser(hw);
3837
3838 clear_bit(__IXGBE_DOWN, &adapter->state);
3839 ixgbe_napi_enable_all(adapter);
3840
3841 if (ixgbe_is_sfp(hw)) {
3842 ixgbe_sfp_link_config(adapter);
3843 } else {
3844 err = ixgbe_non_sfp_link_config(hw);
3845 if (err)
3846 e_err(probe, "link_config FAILED %d\n", err);
3847 }
3848
3849 /* clear any pending interrupts, may auto mask */
3850 IXGBE_READ_REG(hw, IXGBE_EICR);
3851 ixgbe_irq_enable(adapter, true, true);
3852
3853 /*
3854 * If this adapter has a fan, check to see if we had a failure
3855 * before we enabled the interrupt.
3856 */
3857 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3858 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3859 if (esdp & IXGBE_ESDP_SDP1)
3860 e_crit(drv, "Fan has stopped, replace the adapter\n");
3861 }
3862
3863 /*
3864 * For hot-pluggable SFP+ devices, a new SFP+ module may have
3865 * arrived before interrupts were enabled but after probe. Such
3866 * devices wouldn't have their type identified yet. We need to
3867 * kick off the SFP+ module setup first, then try to bring up link.
3868 * If we're not hot-pluggable SFP+, we just need to configure link
3869 * and bring it up.
3870 */
3871 if (hw->phy.type == ixgbe_phy_unknown)
3872 schedule_work(&adapter->sfp_config_module_task);
3873
3874 /* enable transmits */
3875 netif_tx_start_all_queues(adapter->netdev);
3876
3877 /* bring the link up in the watchdog, this could race with our first
3878 * link up interrupt but shouldn't be a problem */
3879 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3880 adapter->link_check_timeout = jiffies;
3881 mod_timer(&adapter->watchdog_timer, jiffies);
3882
3883 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3884 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3885 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3886 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3887
3888 return 0;
3889 }
3890
3891 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3892 {
3893 WARN_ON(in_interrupt());
3894 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3895 msleep(1);
3896 ixgbe_down(adapter);
3897 /*
3898 * If SR-IOV enabled then wait a bit before bringing the adapter
3899 * back up to give the VFs time to respond to the reset. The
3900 * two second wait is based upon the watchdog timer cycle in
3901 * the VF driver.
3902 */
3903 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3904 msleep(2000);
3905 ixgbe_up(adapter);
3906 clear_bit(__IXGBE_RESETTING, &adapter->state);
3907 }
3908
3909 int ixgbe_up(struct ixgbe_adapter *adapter)
3910 {
3911 /* hardware has been reset, we need to reload some things */
3912 ixgbe_configure(adapter);
3913
3914 return ixgbe_up_complete(adapter);
3915 }
3916
3917 void ixgbe_reset(struct ixgbe_adapter *adapter)
3918 {
3919 struct ixgbe_hw *hw = &adapter->hw;
3920 int err;
3921
3922 err = hw->mac.ops.init_hw(hw);
3923 switch (err) {
3924 case 0:
3925 case IXGBE_ERR_SFP_NOT_PRESENT:
3926 break;
3927 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3928 e_dev_err("master disable timed out\n");
3929 break;
3930 case IXGBE_ERR_EEPROM_VERSION:
3931 /* We are running on a pre-production device, log a warning */
3932 e_dev_warn("This device is a pre-production adapter/LOM. "
3933 "Please be aware there may be issuesassociated with "
3934 "your hardware. If you are experiencing problems "
3935 "please contact your Intel or hardware "
3936 "representative who provided you with this "
3937 "hardware.\n");
3938 break;
3939 default:
3940 e_dev_err("Hardware Error: %d\n", err);
3941 }
3942
3943 /* reprogram the RAR[0] in case user changed it. */
3944 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3945 IXGBE_RAH_AV);
3946 }
3947
3948 /**
3949 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3950 * @rx_ring: ring to free buffers from
3951 **/
3952 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3953 {
3954 struct device *dev = rx_ring->dev;
3955 unsigned long size;
3956 u16 i;
3957
3958 /* ring already cleared, nothing to do */
3959 if (!rx_ring->rx_buffer_info)
3960 return;
3961
3962 /* Free all the Rx ring sk_buffs */
3963 for (i = 0; i < rx_ring->count; i++) {
3964 struct ixgbe_rx_buffer *rx_buffer_info;
3965
3966 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3967 if (rx_buffer_info->dma) {
3968 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3969 rx_ring->rx_buf_len,
3970 DMA_FROM_DEVICE);
3971 rx_buffer_info->dma = 0;
3972 }
3973 if (rx_buffer_info->skb) {
3974 struct sk_buff *skb = rx_buffer_info->skb;
3975 rx_buffer_info->skb = NULL;
3976 do {
3977 struct sk_buff *this = skb;
3978 if (IXGBE_RSC_CB(this)->delay_unmap) {
3979 dma_unmap_single(dev,
3980 IXGBE_RSC_CB(this)->dma,
3981 rx_ring->rx_buf_len,
3982 DMA_FROM_DEVICE);
3983 IXGBE_RSC_CB(this)->dma = 0;
3984 IXGBE_RSC_CB(skb)->delay_unmap = false;
3985 }
3986 skb = skb->prev;
3987 dev_kfree_skb(this);
3988 } while (skb);
3989 }
3990 if (!rx_buffer_info->page)
3991 continue;
3992 if (rx_buffer_info->page_dma) {
3993 dma_unmap_page(dev, rx_buffer_info->page_dma,
3994 PAGE_SIZE / 2, DMA_FROM_DEVICE);
3995 rx_buffer_info->page_dma = 0;
3996 }
3997 put_page(rx_buffer_info->page);
3998 rx_buffer_info->page = NULL;
3999 rx_buffer_info->page_offset = 0;
4000 }
4001
4002 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4003 memset(rx_ring->rx_buffer_info, 0, size);
4004
4005 /* Zero out the descriptor ring */
4006 memset(rx_ring->desc, 0, rx_ring->size);
4007
4008 rx_ring->next_to_clean = 0;
4009 rx_ring->next_to_use = 0;
4010 }
4011
4012 /**
4013 * ixgbe_clean_tx_ring - Free Tx Buffers
4014 * @tx_ring: ring to be cleaned
4015 **/
4016 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4017 {
4018 struct ixgbe_tx_buffer *tx_buffer_info;
4019 unsigned long size;
4020 u16 i;
4021
4022 /* ring already cleared, nothing to do */
4023 if (!tx_ring->tx_buffer_info)
4024 return;
4025
4026 /* Free all the Tx ring sk_buffs */
4027 for (i = 0; i < tx_ring->count; i++) {
4028 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4029 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4030 }
4031
4032 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4033 memset(tx_ring->tx_buffer_info, 0, size);
4034
4035 /* Zero out the descriptor ring */
4036 memset(tx_ring->desc, 0, tx_ring->size);
4037
4038 tx_ring->next_to_use = 0;
4039 tx_ring->next_to_clean = 0;
4040 }
4041
4042 /**
4043 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4044 * @adapter: board private structure
4045 **/
4046 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4047 {
4048 int i;
4049
4050 for (i = 0; i < adapter->num_rx_queues; i++)
4051 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4052 }
4053
4054 /**
4055 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4056 * @adapter: board private structure
4057 **/
4058 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4059 {
4060 int i;
4061
4062 for (i = 0; i < adapter->num_tx_queues; i++)
4063 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4064 }
4065
4066 void ixgbe_down(struct ixgbe_adapter *adapter)
4067 {
4068 struct net_device *netdev = adapter->netdev;
4069 struct ixgbe_hw *hw = &adapter->hw;
4070 u32 rxctrl;
4071 u32 txdctl;
4072 int i;
4073 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4074
4075 /* signal that we are down to the interrupt handler */
4076 set_bit(__IXGBE_DOWN, &adapter->state);
4077
4078 /* disable receive for all VFs and wait one second */
4079 if (adapter->num_vfs) {
4080 /* ping all the active vfs to let them know we are going down */
4081 ixgbe_ping_all_vfs(adapter);
4082
4083 /* Disable all VFTE/VFRE TX/RX */
4084 ixgbe_disable_tx_rx(adapter);
4085
4086 /* Mark all the VFs as inactive */
4087 for (i = 0 ; i < adapter->num_vfs; i++)
4088 adapter->vfinfo[i].clear_to_send = 0;
4089 }
4090
4091 /* disable receives */
4092 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4093 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4094
4095 /* disable all enabled rx queues */
4096 for (i = 0; i < adapter->num_rx_queues; i++)
4097 /* this call also flushes the previous write */
4098 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4099
4100 msleep(10);
4101
4102 netif_tx_stop_all_queues(netdev);
4103
4104 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4105 del_timer_sync(&adapter->sfp_timer);
4106 del_timer_sync(&adapter->watchdog_timer);
4107 cancel_work_sync(&adapter->watchdog_task);
4108
4109 netif_carrier_off(netdev);
4110 netif_tx_disable(netdev);
4111
4112 ixgbe_irq_disable(adapter);
4113
4114 ixgbe_napi_disable_all(adapter);
4115
4116 /* Cleanup the affinity_hint CPU mask memory and callback */
4117 for (i = 0; i < num_q_vectors; i++) {
4118 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4119 /* clear the affinity_mask in the IRQ descriptor */
4120 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4121 /* release the CPU mask memory */
4122 free_cpumask_var(q_vector->affinity_mask);
4123 }
4124
4125 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4126 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4127 cancel_work_sync(&adapter->fdir_reinit_task);
4128
4129 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4130 cancel_work_sync(&adapter->check_overtemp_task);
4131
4132 /* disable transmits in the hardware now that interrupts are off */
4133 for (i = 0; i < adapter->num_tx_queues; i++) {
4134 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4135 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
4136 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
4137 (txdctl & ~IXGBE_TXDCTL_ENABLE));
4138 }
4139 /* Disable the Tx DMA engine on 82599 */
4140 switch (hw->mac.type) {
4141 case ixgbe_mac_82599EB:
4142 case ixgbe_mac_X540:
4143 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4144 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4145 ~IXGBE_DMATXCTL_TE));
4146 break;
4147 default:
4148 break;
4149 }
4150
4151 /* clear n-tuple filters that are cached */
4152 ethtool_ntuple_flush(netdev);
4153
4154 if (!pci_channel_offline(adapter->pdev))
4155 ixgbe_reset(adapter);
4156
4157 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4158 if (hw->mac.ops.disable_tx_laser &&
4159 ((hw->phy.multispeed_fiber) ||
4160 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4161 (hw->mac.type == ixgbe_mac_82599EB))))
4162 hw->mac.ops.disable_tx_laser(hw);
4163
4164 ixgbe_clean_all_tx_rings(adapter);
4165 ixgbe_clean_all_rx_rings(adapter);
4166
4167 #ifdef CONFIG_IXGBE_DCA
4168 /* since we reset the hardware DCA settings were cleared */
4169 ixgbe_setup_dca(adapter);
4170 #endif
4171 }
4172
4173 /**
4174 * ixgbe_poll - NAPI Rx polling callback
4175 * @napi: structure for representing this polling device
4176 * @budget: how many packets driver is allowed to clean
4177 *
4178 * This function is used for legacy and MSI, NAPI mode
4179 **/
4180 static int ixgbe_poll(struct napi_struct *napi, int budget)
4181 {
4182 struct ixgbe_q_vector *q_vector =
4183 container_of(napi, struct ixgbe_q_vector, napi);
4184 struct ixgbe_adapter *adapter = q_vector->adapter;
4185 int tx_clean_complete, work_done = 0;
4186
4187 #ifdef CONFIG_IXGBE_DCA
4188 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4189 ixgbe_update_dca(q_vector);
4190 #endif
4191
4192 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4193 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
4194
4195 if (!tx_clean_complete)
4196 work_done = budget;
4197
4198 /* If budget not fully consumed, exit the polling mode */
4199 if (work_done < budget) {
4200 napi_complete(napi);
4201 if (adapter->rx_itr_setting & 1)
4202 ixgbe_set_itr(adapter);
4203 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4204 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
4205 }
4206 return work_done;
4207 }
4208
4209 /**
4210 * ixgbe_tx_timeout - Respond to a Tx Hang
4211 * @netdev: network interface device structure
4212 **/
4213 static void ixgbe_tx_timeout(struct net_device *netdev)
4214 {
4215 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4216
4217 adapter->tx_timeout_count++;
4218
4219 /* Do the reset outside of interrupt context */
4220 schedule_work(&adapter->reset_task);
4221 }
4222
4223 static void ixgbe_reset_task(struct work_struct *work)
4224 {
4225 struct ixgbe_adapter *adapter;
4226 adapter = container_of(work, struct ixgbe_adapter, reset_task);
4227
4228 /* If we're already down or resetting, just bail */
4229 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
4230 test_bit(__IXGBE_RESETTING, &adapter->state))
4231 return;
4232
4233 ixgbe_dump(adapter);
4234 netdev_err(adapter->netdev, "Reset adapter\n");
4235 ixgbe_reinit_locked(adapter);
4236 }
4237
4238 #ifdef CONFIG_IXGBE_DCB
4239 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4240 {
4241 bool ret = false;
4242 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
4243
4244 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4245 return ret;
4246
4247 f->mask = 0x7 << 3;
4248 adapter->num_rx_queues = f->indices;
4249 adapter->num_tx_queues = f->indices;
4250 ret = true;
4251
4252 return ret;
4253 }
4254 #endif
4255
4256 /**
4257 * ixgbe_set_rss_queues: Allocate queues for RSS
4258 * @adapter: board private structure to initialize
4259 *
4260 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4261 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4262 *
4263 **/
4264 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4265 {
4266 bool ret = false;
4267 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4268
4269 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4270 f->mask = 0xF;
4271 adapter->num_rx_queues = f->indices;
4272 adapter->num_tx_queues = f->indices;
4273 ret = true;
4274 } else {
4275 ret = false;
4276 }
4277
4278 return ret;
4279 }
4280
4281 /**
4282 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4283 * @adapter: board private structure to initialize
4284 *
4285 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4286 * to the original CPU that initiated the Tx session. This runs in addition
4287 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4288 * Rx load across CPUs using RSS.
4289 *
4290 **/
4291 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4292 {
4293 bool ret = false;
4294 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4295
4296 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4297 f_fdir->mask = 0;
4298
4299 /* Flow Director must have RSS enabled */
4300 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4301 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4302 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4303 adapter->num_tx_queues = f_fdir->indices;
4304 adapter->num_rx_queues = f_fdir->indices;
4305 ret = true;
4306 } else {
4307 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4308 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4309 }
4310 return ret;
4311 }
4312
4313 #ifdef IXGBE_FCOE
4314 /**
4315 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4316 * @adapter: board private structure to initialize
4317 *
4318 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4319 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4320 * rx queues out of the max number of rx queues, instead, it is used as the
4321 * index of the first rx queue used by FCoE.
4322 *
4323 **/
4324 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4325 {
4326 bool ret = false;
4327 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4328
4329 f->indices = min((int)num_online_cpus(), f->indices);
4330 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4331 adapter->num_rx_queues = 1;
4332 adapter->num_tx_queues = 1;
4333 #ifdef CONFIG_IXGBE_DCB
4334 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4335 e_info(probe, "FCoE enabled with DCB\n");
4336 ixgbe_set_dcb_queues(adapter);
4337 }
4338 #endif
4339 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4340 e_info(probe, "FCoE enabled with RSS\n");
4341 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4342 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4343 ixgbe_set_fdir_queues(adapter);
4344 else
4345 ixgbe_set_rss_queues(adapter);
4346 }
4347 /* adding FCoE rx rings to the end */
4348 f->mask = adapter->num_rx_queues;
4349 adapter->num_rx_queues += f->indices;
4350 adapter->num_tx_queues += f->indices;
4351
4352 ret = true;
4353 }
4354
4355 return ret;
4356 }
4357
4358 #endif /* IXGBE_FCOE */
4359 /**
4360 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4361 * @adapter: board private structure to initialize
4362 *
4363 * IOV doesn't actually use anything, so just NAK the
4364 * request for now and let the other queue routines
4365 * figure out what to do.
4366 */
4367 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4368 {
4369 return false;
4370 }
4371
4372 /*
4373 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4374 * @adapter: board private structure to initialize
4375 *
4376 * This is the top level queue allocation routine. The order here is very
4377 * important, starting with the "most" number of features turned on at once,
4378 * and ending with the smallest set of features. This way large combinations
4379 * can be allocated if they're turned on, and smaller combinations are the
4380 * fallthrough conditions.
4381 *
4382 **/
4383 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4384 {
4385 /* Start with base case */
4386 adapter->num_rx_queues = 1;
4387 adapter->num_tx_queues = 1;
4388 adapter->num_rx_pools = adapter->num_rx_queues;
4389 adapter->num_rx_queues_per_pool = 1;
4390
4391 if (ixgbe_set_sriov_queues(adapter))
4392 goto done;
4393
4394 #ifdef IXGBE_FCOE
4395 if (ixgbe_set_fcoe_queues(adapter))
4396 goto done;
4397
4398 #endif /* IXGBE_FCOE */
4399 #ifdef CONFIG_IXGBE_DCB
4400 if (ixgbe_set_dcb_queues(adapter))
4401 goto done;
4402
4403 #endif
4404 if (ixgbe_set_fdir_queues(adapter))
4405 goto done;
4406
4407 if (ixgbe_set_rss_queues(adapter))
4408 goto done;
4409
4410 /* fallback to base case */
4411 adapter->num_rx_queues = 1;
4412 adapter->num_tx_queues = 1;
4413
4414 done:
4415 /* Notify the stack of the (possibly) reduced queue counts. */
4416 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4417 return netif_set_real_num_rx_queues(adapter->netdev,
4418 adapter->num_rx_queues);
4419 }
4420
4421 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4422 int vectors)
4423 {
4424 int err, vector_threshold;
4425
4426 /* We'll want at least 3 (vector_threshold):
4427 * 1) TxQ[0] Cleanup
4428 * 2) RxQ[0] Cleanup
4429 * 3) Other (Link Status Change, etc.)
4430 * 4) TCP Timer (optional)
4431 */
4432 vector_threshold = MIN_MSIX_COUNT;
4433
4434 /* The more we get, the more we will assign to Tx/Rx Cleanup
4435 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4436 * Right now, we simply care about how many we'll get; we'll
4437 * set them up later while requesting irq's.
4438 */
4439 while (vectors >= vector_threshold) {
4440 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4441 vectors);
4442 if (!err) /* Success in acquiring all requested vectors. */
4443 break;
4444 else if (err < 0)
4445 vectors = 0; /* Nasty failure, quit now */
4446 else /* err == number of vectors we should try again with */
4447 vectors = err;
4448 }
4449
4450 if (vectors < vector_threshold) {
4451 /* Can't allocate enough MSI-X interrupts? Oh well.
4452 * This just means we'll go with either a single MSI
4453 * vector or fall back to legacy interrupts.
4454 */
4455 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4456 "Unable to allocate MSI-X interrupts\n");
4457 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4458 kfree(adapter->msix_entries);
4459 adapter->msix_entries = NULL;
4460 } else {
4461 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4462 /*
4463 * Adjust for only the vectors we'll use, which is minimum
4464 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4465 * vectors we were allocated.
4466 */
4467 adapter->num_msix_vectors = min(vectors,
4468 adapter->max_msix_q_vectors + NON_Q_VECTORS);
4469 }
4470 }
4471
4472 /**
4473 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4474 * @adapter: board private structure to initialize
4475 *
4476 * Cache the descriptor ring offsets for RSS to the assigned rings.
4477 *
4478 **/
4479 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4480 {
4481 int i;
4482
4483 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4484 return false;
4485
4486 for (i = 0; i < adapter->num_rx_queues; i++)
4487 adapter->rx_ring[i]->reg_idx = i;
4488 for (i = 0; i < adapter->num_tx_queues; i++)
4489 adapter->tx_ring[i]->reg_idx = i;
4490
4491 return true;
4492 }
4493
4494 #ifdef CONFIG_IXGBE_DCB
4495 /**
4496 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4497 * @adapter: board private structure to initialize
4498 *
4499 * Cache the descriptor ring offsets for DCB to the assigned rings.
4500 *
4501 **/
4502 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4503 {
4504 int i;
4505 bool ret = false;
4506 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4507
4508 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4509 return false;
4510
4511 /* the number of queues is assumed to be symmetric */
4512 switch (adapter->hw.mac.type) {
4513 case ixgbe_mac_82598EB:
4514 for (i = 0; i < dcb_i; i++) {
4515 adapter->rx_ring[i]->reg_idx = i << 3;
4516 adapter->tx_ring[i]->reg_idx = i << 2;
4517 }
4518 ret = true;
4519 break;
4520 case ixgbe_mac_82599EB:
4521 case ixgbe_mac_X540:
4522 if (dcb_i == 8) {
4523 /*
4524 * Tx TC0 starts at: descriptor queue 0
4525 * Tx TC1 starts at: descriptor queue 32
4526 * Tx TC2 starts at: descriptor queue 64
4527 * Tx TC3 starts at: descriptor queue 80
4528 * Tx TC4 starts at: descriptor queue 96
4529 * Tx TC5 starts at: descriptor queue 104
4530 * Tx TC6 starts at: descriptor queue 112
4531 * Tx TC7 starts at: descriptor queue 120
4532 *
4533 * Rx TC0-TC7 are offset by 16 queues each
4534 */
4535 for (i = 0; i < 3; i++) {
4536 adapter->tx_ring[i]->reg_idx = i << 5;
4537 adapter->rx_ring[i]->reg_idx = i << 4;
4538 }
4539 for ( ; i < 5; i++) {
4540 adapter->tx_ring[i]->reg_idx = ((i + 2) << 4);
4541 adapter->rx_ring[i]->reg_idx = i << 4;
4542 }
4543 for ( ; i < dcb_i; i++) {
4544 adapter->tx_ring[i]->reg_idx = ((i + 8) << 3);
4545 adapter->rx_ring[i]->reg_idx = i << 4;
4546 }
4547 ret = true;
4548 } else if (dcb_i == 4) {
4549 /*
4550 * Tx TC0 starts at: descriptor queue 0
4551 * Tx TC1 starts at: descriptor queue 64
4552 * Tx TC2 starts at: descriptor queue 96
4553 * Tx TC3 starts at: descriptor queue 112
4554 *
4555 * Rx TC0-TC3 are offset by 32 queues each
4556 */
4557 adapter->tx_ring[0]->reg_idx = 0;
4558 adapter->tx_ring[1]->reg_idx = 64;
4559 adapter->tx_ring[2]->reg_idx = 96;
4560 adapter->tx_ring[3]->reg_idx = 112;
4561 for (i = 0 ; i < dcb_i; i++)
4562 adapter->rx_ring[i]->reg_idx = i << 5;
4563 ret = true;
4564 }
4565 break;
4566 default:
4567 break;
4568 }
4569 return ret;
4570 }
4571 #endif
4572
4573 /**
4574 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4575 * @adapter: board private structure to initialize
4576 *
4577 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4578 *
4579 **/
4580 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4581 {
4582 int i;
4583 bool ret = false;
4584
4585 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4586 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4587 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4588 for (i = 0; i < adapter->num_rx_queues; i++)
4589 adapter->rx_ring[i]->reg_idx = i;
4590 for (i = 0; i < adapter->num_tx_queues; i++)
4591 adapter->tx_ring[i]->reg_idx = i;
4592 ret = true;
4593 }
4594
4595 return ret;
4596 }
4597
4598 #ifdef IXGBE_FCOE
4599 /**
4600 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4601 * @adapter: board private structure to initialize
4602 *
4603 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4604 *
4605 */
4606 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4607 {
4608 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4609 int i;
4610 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4611
4612 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4613 return false;
4614
4615 #ifdef CONFIG_IXGBE_DCB
4616 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4617 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4618
4619 ixgbe_cache_ring_dcb(adapter);
4620 /* find out queues in TC for FCoE */
4621 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4622 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4623 /*
4624 * In 82599, the number of Tx queues for each traffic
4625 * class for both 8-TC and 4-TC modes are:
4626 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4627 * 8 TCs: 32 32 16 16 8 8 8 8
4628 * 4 TCs: 64 64 32 32
4629 * We have max 8 queues for FCoE, where 8 the is
4630 * FCoE redirection table size. If TC for FCoE is
4631 * less than or equal to TC3, we have enough queues
4632 * to add max of 8 queues for FCoE, so we start FCoE
4633 * Tx queue from the next one, i.e., reg_idx + 1.
4634 * If TC for FCoE is above TC3, implying 8 TC mode,
4635 * and we need 8 for FCoE, we have to take all queues
4636 * in that traffic class for FCoE.
4637 */
4638 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4639 fcoe_tx_i--;
4640 }
4641 #endif /* CONFIG_IXGBE_DCB */
4642 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4643 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4644 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4645 ixgbe_cache_ring_fdir(adapter);
4646 else
4647 ixgbe_cache_ring_rss(adapter);
4648
4649 fcoe_rx_i = f->mask;
4650 fcoe_tx_i = f->mask;
4651 }
4652 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4653 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4654 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4655 }
4656 return true;
4657 }
4658
4659 #endif /* IXGBE_FCOE */
4660 /**
4661 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4662 * @adapter: board private structure to initialize
4663 *
4664 * SR-IOV doesn't use any descriptor rings but changes the default if
4665 * no other mapping is used.
4666 *
4667 */
4668 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4669 {
4670 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4671 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4672 if (adapter->num_vfs)
4673 return true;
4674 else
4675 return false;
4676 }
4677
4678 /**
4679 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4680 * @adapter: board private structure to initialize
4681 *
4682 * Once we know the feature-set enabled for the device, we'll cache
4683 * the register offset the descriptor ring is assigned to.
4684 *
4685 * Note, the order the various feature calls is important. It must start with
4686 * the "most" features enabled at the same time, then trickle down to the
4687 * least amount of features turned on at once.
4688 **/
4689 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4690 {
4691 /* start with default case */
4692 adapter->rx_ring[0]->reg_idx = 0;
4693 adapter->tx_ring[0]->reg_idx = 0;
4694
4695 if (ixgbe_cache_ring_sriov(adapter))
4696 return;
4697
4698 #ifdef IXGBE_FCOE
4699 if (ixgbe_cache_ring_fcoe(adapter))
4700 return;
4701
4702 #endif /* IXGBE_FCOE */
4703 #ifdef CONFIG_IXGBE_DCB
4704 if (ixgbe_cache_ring_dcb(adapter))
4705 return;
4706
4707 #endif
4708 if (ixgbe_cache_ring_fdir(adapter))
4709 return;
4710
4711 if (ixgbe_cache_ring_rss(adapter))
4712 return;
4713 }
4714
4715 /**
4716 * ixgbe_alloc_queues - Allocate memory for all rings
4717 * @adapter: board private structure to initialize
4718 *
4719 * We allocate one ring per queue at run-time since we don't know the
4720 * number of queues at compile-time. The polling_netdev array is
4721 * intended for Multiqueue, but should work fine with a single queue.
4722 **/
4723 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4724 {
4725 int rx = 0, tx = 0, nid = adapter->node;
4726
4727 if (nid < 0 || !node_online(nid))
4728 nid = first_online_node;
4729
4730 for (; tx < adapter->num_tx_queues; tx++) {
4731 struct ixgbe_ring *ring;
4732
4733 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4734 if (!ring)
4735 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4736 if (!ring)
4737 goto err_allocation;
4738 ring->count = adapter->tx_ring_count;
4739 ring->queue_index = tx;
4740 ring->numa_node = nid;
4741 ring->dev = &adapter->pdev->dev;
4742 ring->netdev = adapter->netdev;
4743
4744 adapter->tx_ring[tx] = ring;
4745 }
4746
4747 for (; rx < adapter->num_rx_queues; rx++) {
4748 struct ixgbe_ring *ring;
4749
4750 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4751 if (!ring)
4752 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4753 if (!ring)
4754 goto err_allocation;
4755 ring->count = adapter->rx_ring_count;
4756 ring->queue_index = rx;
4757 ring->numa_node = nid;
4758 ring->dev = &adapter->pdev->dev;
4759 ring->netdev = adapter->netdev;
4760
4761 adapter->rx_ring[rx] = ring;
4762 }
4763
4764 ixgbe_cache_ring_register(adapter);
4765
4766 return 0;
4767
4768 err_allocation:
4769 while (tx)
4770 kfree(adapter->tx_ring[--tx]);
4771
4772 while (rx)
4773 kfree(adapter->rx_ring[--rx]);
4774 return -ENOMEM;
4775 }
4776
4777 /**
4778 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4779 * @adapter: board private structure to initialize
4780 *
4781 * Attempt to configure the interrupts using the best available
4782 * capabilities of the hardware and the kernel.
4783 **/
4784 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4785 {
4786 struct ixgbe_hw *hw = &adapter->hw;
4787 int err = 0;
4788 int vector, v_budget;
4789
4790 /*
4791 * It's easy to be greedy for MSI-X vectors, but it really
4792 * doesn't do us much good if we have a lot more vectors
4793 * than CPU's. So let's be conservative and only ask for
4794 * (roughly) the same number of vectors as there are CPU's.
4795 */
4796 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4797 (int)num_online_cpus()) + NON_Q_VECTORS;
4798
4799 /*
4800 * At the same time, hardware can only support a maximum of
4801 * hw.mac->max_msix_vectors vectors. With features
4802 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4803 * descriptor queues supported by our device. Thus, we cap it off in
4804 * those rare cases where the cpu count also exceeds our vector limit.
4805 */
4806 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4807
4808 /* A failure in MSI-X entry allocation isn't fatal, but it does
4809 * mean we disable MSI-X capabilities of the adapter. */
4810 adapter->msix_entries = kcalloc(v_budget,
4811 sizeof(struct msix_entry), GFP_KERNEL);
4812 if (adapter->msix_entries) {
4813 for (vector = 0; vector < v_budget; vector++)
4814 adapter->msix_entries[vector].entry = vector;
4815
4816 ixgbe_acquire_msix_vectors(adapter, v_budget);
4817
4818 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4819 goto out;
4820 }
4821
4822 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4823 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4824 if (adapter->flags & (IXGBE_FLAG_FDIR_HASH_CAPABLE |
4825 IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
4826 e_err(probe,
4827 "Flow Director is not supported while multiple "
4828 "queues are disabled. Disabling Flow Director\n");
4829 }
4830 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4831 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4832 adapter->atr_sample_rate = 0;
4833 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4834 ixgbe_disable_sriov(adapter);
4835
4836 err = ixgbe_set_num_queues(adapter);
4837 if (err)
4838 return err;
4839
4840 err = pci_enable_msi(adapter->pdev);
4841 if (!err) {
4842 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4843 } else {
4844 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4845 "Unable to allocate MSI interrupt, "
4846 "falling back to legacy. Error: %d\n", err);
4847 /* reset err */
4848 err = 0;
4849 }
4850
4851 out:
4852 return err;
4853 }
4854
4855 /**
4856 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4857 * @adapter: board private structure to initialize
4858 *
4859 * We allocate one q_vector per queue interrupt. If allocation fails we
4860 * return -ENOMEM.
4861 **/
4862 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4863 {
4864 int q_idx, num_q_vectors;
4865 struct ixgbe_q_vector *q_vector;
4866 int napi_vectors;
4867 int (*poll)(struct napi_struct *, int);
4868
4869 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4870 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4871 napi_vectors = adapter->num_rx_queues;
4872 poll = &ixgbe_clean_rxtx_many;
4873 } else {
4874 num_q_vectors = 1;
4875 napi_vectors = 1;
4876 poll = &ixgbe_poll;
4877 }
4878
4879 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4880 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4881 GFP_KERNEL, adapter->node);
4882 if (!q_vector)
4883 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4884 GFP_KERNEL);
4885 if (!q_vector)
4886 goto err_out;
4887 q_vector->adapter = adapter;
4888 if (q_vector->txr_count && !q_vector->rxr_count)
4889 q_vector->eitr = adapter->tx_eitr_param;
4890 else
4891 q_vector->eitr = adapter->rx_eitr_param;
4892 q_vector->v_idx = q_idx;
4893 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4894 adapter->q_vector[q_idx] = q_vector;
4895 }
4896
4897 return 0;
4898
4899 err_out:
4900 while (q_idx) {
4901 q_idx--;
4902 q_vector = adapter->q_vector[q_idx];
4903 netif_napi_del(&q_vector->napi);
4904 kfree(q_vector);
4905 adapter->q_vector[q_idx] = NULL;
4906 }
4907 return -ENOMEM;
4908 }
4909
4910 /**
4911 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4912 * @adapter: board private structure to initialize
4913 *
4914 * This function frees the memory allocated to the q_vectors. In addition if
4915 * NAPI is enabled it will delete any references to the NAPI struct prior
4916 * to freeing the q_vector.
4917 **/
4918 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4919 {
4920 int q_idx, num_q_vectors;
4921
4922 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4923 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4924 else
4925 num_q_vectors = 1;
4926
4927 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4928 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4929 adapter->q_vector[q_idx] = NULL;
4930 netif_napi_del(&q_vector->napi);
4931 kfree(q_vector);
4932 }
4933 }
4934
4935 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4936 {
4937 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4938 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4939 pci_disable_msix(adapter->pdev);
4940 kfree(adapter->msix_entries);
4941 adapter->msix_entries = NULL;
4942 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4943 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4944 pci_disable_msi(adapter->pdev);
4945 }
4946 }
4947
4948 /**
4949 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4950 * @adapter: board private structure to initialize
4951 *
4952 * We determine which interrupt scheme to use based on...
4953 * - Kernel support (MSI, MSI-X)
4954 * - which can be user-defined (via MODULE_PARAM)
4955 * - Hardware queue count (num_*_queues)
4956 * - defined by miscellaneous hardware support/features (RSS, etc.)
4957 **/
4958 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4959 {
4960 int err;
4961
4962 /* Number of supported queues */
4963 err = ixgbe_set_num_queues(adapter);
4964 if (err)
4965 return err;
4966
4967 err = ixgbe_set_interrupt_capability(adapter);
4968 if (err) {
4969 e_dev_err("Unable to setup interrupt capabilities\n");
4970 goto err_set_interrupt;
4971 }
4972
4973 err = ixgbe_alloc_q_vectors(adapter);
4974 if (err) {
4975 e_dev_err("Unable to allocate memory for queue vectors\n");
4976 goto err_alloc_q_vectors;
4977 }
4978
4979 err = ixgbe_alloc_queues(adapter);
4980 if (err) {
4981 e_dev_err("Unable to allocate memory for queues\n");
4982 goto err_alloc_queues;
4983 }
4984
4985 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4986 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4987 adapter->num_rx_queues, adapter->num_tx_queues);
4988
4989 set_bit(__IXGBE_DOWN, &adapter->state);
4990
4991 return 0;
4992
4993 err_alloc_queues:
4994 ixgbe_free_q_vectors(adapter);
4995 err_alloc_q_vectors:
4996 ixgbe_reset_interrupt_capability(adapter);
4997 err_set_interrupt:
4998 return err;
4999 }
5000
5001 static void ring_free_rcu(struct rcu_head *head)
5002 {
5003 kfree(container_of(head, struct ixgbe_ring, rcu));
5004 }
5005
5006 /**
5007 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5008 * @adapter: board private structure to clear interrupt scheme on
5009 *
5010 * We go through and clear interrupt specific resources and reset the structure
5011 * to pre-load conditions
5012 **/
5013 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5014 {
5015 int i;
5016
5017 for (i = 0; i < adapter->num_tx_queues; i++) {
5018 kfree(adapter->tx_ring[i]);
5019 adapter->tx_ring[i] = NULL;
5020 }
5021 for (i = 0; i < adapter->num_rx_queues; i++) {
5022 struct ixgbe_ring *ring = adapter->rx_ring[i];
5023
5024 /* ixgbe_get_stats64() might access this ring, we must wait
5025 * a grace period before freeing it.
5026 */
5027 call_rcu(&ring->rcu, ring_free_rcu);
5028 adapter->rx_ring[i] = NULL;
5029 }
5030
5031 adapter->num_tx_queues = 0;
5032 adapter->num_rx_queues = 0;
5033
5034 ixgbe_free_q_vectors(adapter);
5035 ixgbe_reset_interrupt_capability(adapter);
5036 }
5037
5038 /**
5039 * ixgbe_sfp_timer - worker thread to find a missing module
5040 * @data: pointer to our adapter struct
5041 **/
5042 static void ixgbe_sfp_timer(unsigned long data)
5043 {
5044 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5045
5046 /*
5047 * Do the sfp_timer outside of interrupt context due to the
5048 * delays that sfp+ detection requires
5049 */
5050 schedule_work(&adapter->sfp_task);
5051 }
5052
5053 /**
5054 * ixgbe_sfp_task - worker thread to find a missing module
5055 * @work: pointer to work_struct containing our data
5056 **/
5057 static void ixgbe_sfp_task(struct work_struct *work)
5058 {
5059 struct ixgbe_adapter *adapter = container_of(work,
5060 struct ixgbe_adapter,
5061 sfp_task);
5062 struct ixgbe_hw *hw = &adapter->hw;
5063
5064 if ((hw->phy.type == ixgbe_phy_nl) &&
5065 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
5066 s32 ret = hw->phy.ops.identify_sfp(hw);
5067 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
5068 goto reschedule;
5069 ret = hw->phy.ops.reset(hw);
5070 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5071 e_dev_err("failed to initialize because an unsupported "
5072 "SFP+ module type was detected.\n");
5073 e_dev_err("Reload the driver after installing a "
5074 "supported module.\n");
5075 unregister_netdev(adapter->netdev);
5076 } else {
5077 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5078 }
5079 /* don't need this routine any more */
5080 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5081 }
5082 return;
5083 reschedule:
5084 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
5085 mod_timer(&adapter->sfp_timer,
5086 round_jiffies(jiffies + (2 * HZ)));
5087 }
5088
5089 /**
5090 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5091 * @adapter: board private structure to initialize
5092 *
5093 * ixgbe_sw_init initializes the Adapter private data structure.
5094 * Fields are initialized based on PCI device information and
5095 * OS network device settings (MTU size).
5096 **/
5097 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5098 {
5099 struct ixgbe_hw *hw = &adapter->hw;
5100 struct pci_dev *pdev = adapter->pdev;
5101 struct net_device *dev = adapter->netdev;
5102 unsigned int rss;
5103 #ifdef CONFIG_IXGBE_DCB
5104 int j;
5105 struct tc_configuration *tc;
5106 #endif
5107 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5108
5109 /* PCI config space info */
5110
5111 hw->vendor_id = pdev->vendor;
5112 hw->device_id = pdev->device;
5113 hw->revision_id = pdev->revision;
5114 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5115 hw->subsystem_device_id = pdev->subsystem_device;
5116
5117 /* Set capability flags */
5118 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5119 adapter->ring_feature[RING_F_RSS].indices = rss;
5120 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
5121 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
5122 switch (hw->mac.type) {
5123 case ixgbe_mac_82598EB:
5124 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5125 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5126 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
5127 break;
5128 case ixgbe_mac_82599EB:
5129 case ixgbe_mac_X540:
5130 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
5131 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5132 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5133 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5134 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5135 /* n-tuple support exists, always init our spinlock */
5136 spin_lock_init(&adapter->fdir_perfect_lock);
5137 /* Flow Director hash filters enabled */
5138 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5139 adapter->atr_sample_rate = 20;
5140 adapter->ring_feature[RING_F_FDIR].indices =
5141 IXGBE_MAX_FDIR_INDICES;
5142 adapter->fdir_pballoc = 0;
5143 #ifdef IXGBE_FCOE
5144 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5145 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5146 adapter->ring_feature[RING_F_FCOE].indices = 0;
5147 #ifdef CONFIG_IXGBE_DCB
5148 /* Default traffic class to use for FCoE */
5149 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
5150 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5151 #endif
5152 #endif /* IXGBE_FCOE */
5153 break;
5154 default:
5155 break;
5156 }
5157
5158 #ifdef CONFIG_IXGBE_DCB
5159 /* Configure DCB traffic classes */
5160 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5161 tc = &adapter->dcb_cfg.tc_config[j];
5162 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5163 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5164 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5165 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5166 tc->dcb_pfc = pfc_disabled;
5167 }
5168 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5169 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5170 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
5171 adapter->dcb_cfg.pfc_mode_enable = false;
5172 adapter->dcb_cfg.round_robin_enable = false;
5173 adapter->dcb_set_bitmap = 0x00;
5174 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5175 adapter->ring_feature[RING_F_DCB].indices);
5176
5177 #endif
5178
5179 /* default flow control settings */
5180 hw->fc.requested_mode = ixgbe_fc_full;
5181 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
5182 #ifdef CONFIG_DCB
5183 adapter->last_lfc_mode = hw->fc.current_mode;
5184 #endif
5185 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5186 hw->fc.low_water = FC_LOW_WATER(max_frame);
5187 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5188 hw->fc.send_xon = true;
5189 hw->fc.disable_fc_autoneg = false;
5190
5191 /* enable itr by default in dynamic mode */
5192 adapter->rx_itr_setting = 1;
5193 adapter->rx_eitr_param = 20000;
5194 adapter->tx_itr_setting = 1;
5195 adapter->tx_eitr_param = 10000;
5196
5197 /* set defaults for eitr in MegaBytes */
5198 adapter->eitr_low = 10;
5199 adapter->eitr_high = 20;
5200
5201 /* set default ring sizes */
5202 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5203 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5204
5205 /* initialize eeprom parameters */
5206 if (ixgbe_init_eeprom_params_generic(hw)) {
5207 e_dev_err("EEPROM initialization failed\n");
5208 return -EIO;
5209 }
5210
5211 /* enable rx csum by default */
5212 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5213
5214 /* get assigned NUMA node */
5215 adapter->node = dev_to_node(&pdev->dev);
5216
5217 set_bit(__IXGBE_DOWN, &adapter->state);
5218
5219 return 0;
5220 }
5221
5222 /**
5223 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5224 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5225 *
5226 * Return 0 on success, negative on failure
5227 **/
5228 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5229 {
5230 struct device *dev = tx_ring->dev;
5231 int size;
5232
5233 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5234 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
5235 if (!tx_ring->tx_buffer_info)
5236 tx_ring->tx_buffer_info = vzalloc(size);
5237 if (!tx_ring->tx_buffer_info)
5238 goto err;
5239
5240 /* round up to nearest 4K */
5241 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5242 tx_ring->size = ALIGN(tx_ring->size, 4096);
5243
5244 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5245 &tx_ring->dma, GFP_KERNEL);
5246 if (!tx_ring->desc)
5247 goto err;
5248
5249 tx_ring->next_to_use = 0;
5250 tx_ring->next_to_clean = 0;
5251 tx_ring->work_limit = tx_ring->count;
5252 return 0;
5253
5254 err:
5255 vfree(tx_ring->tx_buffer_info);
5256 tx_ring->tx_buffer_info = NULL;
5257 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5258 return -ENOMEM;
5259 }
5260
5261 /**
5262 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5263 * @adapter: board private structure
5264 *
5265 * If this function returns with an error, then it's possible one or
5266 * more of the rings is populated (while the rest are not). It is the
5267 * callers duty to clean those orphaned rings.
5268 *
5269 * Return 0 on success, negative on failure
5270 **/
5271 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5272 {
5273 int i, err = 0;
5274
5275 for (i = 0; i < adapter->num_tx_queues; i++) {
5276 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5277 if (!err)
5278 continue;
5279 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5280 break;
5281 }
5282
5283 return err;
5284 }
5285
5286 /**
5287 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5288 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5289 *
5290 * Returns 0 on success, negative on failure
5291 **/
5292 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5293 {
5294 struct device *dev = rx_ring->dev;
5295 int size;
5296
5297 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5298 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5299 if (!rx_ring->rx_buffer_info)
5300 rx_ring->rx_buffer_info = vzalloc(size);
5301 if (!rx_ring->rx_buffer_info)
5302 goto err;
5303
5304 /* Round up to nearest 4K */
5305 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5306 rx_ring->size = ALIGN(rx_ring->size, 4096);
5307
5308 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5309 &rx_ring->dma, GFP_KERNEL);
5310
5311 if (!rx_ring->desc)
5312 goto err;
5313
5314 rx_ring->next_to_clean = 0;
5315 rx_ring->next_to_use = 0;
5316
5317 return 0;
5318 err:
5319 vfree(rx_ring->rx_buffer_info);
5320 rx_ring->rx_buffer_info = NULL;
5321 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5322 return -ENOMEM;
5323 }
5324
5325 /**
5326 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5327 * @adapter: board private structure
5328 *
5329 * If this function returns with an error, then it's possible one or
5330 * more of the rings is populated (while the rest are not). It is the
5331 * callers duty to clean those orphaned rings.
5332 *
5333 * Return 0 on success, negative on failure
5334 **/
5335 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5336 {
5337 int i, err = 0;
5338
5339 for (i = 0; i < adapter->num_rx_queues; i++) {
5340 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5341 if (!err)
5342 continue;
5343 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5344 break;
5345 }
5346
5347 return err;
5348 }
5349
5350 /**
5351 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5352 * @tx_ring: Tx descriptor ring for a specific queue
5353 *
5354 * Free all transmit software resources
5355 **/
5356 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5357 {
5358 ixgbe_clean_tx_ring(tx_ring);
5359
5360 vfree(tx_ring->tx_buffer_info);
5361 tx_ring->tx_buffer_info = NULL;
5362
5363 /* if not set, then don't free */
5364 if (!tx_ring->desc)
5365 return;
5366
5367 dma_free_coherent(tx_ring->dev, tx_ring->size,
5368 tx_ring->desc, tx_ring->dma);
5369
5370 tx_ring->desc = NULL;
5371 }
5372
5373 /**
5374 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5375 * @adapter: board private structure
5376 *
5377 * Free all transmit software resources
5378 **/
5379 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5380 {
5381 int i;
5382
5383 for (i = 0; i < adapter->num_tx_queues; i++)
5384 if (adapter->tx_ring[i]->desc)
5385 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5386 }
5387
5388 /**
5389 * ixgbe_free_rx_resources - Free Rx Resources
5390 * @rx_ring: ring to clean the resources from
5391 *
5392 * Free all receive software resources
5393 **/
5394 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5395 {
5396 ixgbe_clean_rx_ring(rx_ring);
5397
5398 vfree(rx_ring->rx_buffer_info);
5399 rx_ring->rx_buffer_info = NULL;
5400
5401 /* if not set, then don't free */
5402 if (!rx_ring->desc)
5403 return;
5404
5405 dma_free_coherent(rx_ring->dev, rx_ring->size,
5406 rx_ring->desc, rx_ring->dma);
5407
5408 rx_ring->desc = NULL;
5409 }
5410
5411 /**
5412 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5413 * @adapter: board private structure
5414 *
5415 * Free all receive software resources
5416 **/
5417 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5418 {
5419 int i;
5420
5421 for (i = 0; i < adapter->num_rx_queues; i++)
5422 if (adapter->rx_ring[i]->desc)
5423 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5424 }
5425
5426 /**
5427 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5428 * @netdev: network interface device structure
5429 * @new_mtu: new value for maximum frame size
5430 *
5431 * Returns 0 on success, negative on failure
5432 **/
5433 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5434 {
5435 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5436 struct ixgbe_hw *hw = &adapter->hw;
5437 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5438
5439 /* MTU < 68 is an error and causes problems on some kernels */
5440 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5441 return -EINVAL;
5442
5443 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5444 /* must set new MTU before calling down or up */
5445 netdev->mtu = new_mtu;
5446
5447 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5448 hw->fc.low_water = FC_LOW_WATER(max_frame);
5449
5450 if (netif_running(netdev))
5451 ixgbe_reinit_locked(adapter);
5452
5453 return 0;
5454 }
5455
5456 /**
5457 * ixgbe_open - Called when a network interface is made active
5458 * @netdev: network interface device structure
5459 *
5460 * Returns 0 on success, negative value on failure
5461 *
5462 * The open entry point is called when a network interface is made
5463 * active by the system (IFF_UP). At this point all resources needed
5464 * for transmit and receive operations are allocated, the interrupt
5465 * handler is registered with the OS, the watchdog timer is started,
5466 * and the stack is notified that the interface is ready.
5467 **/
5468 static int ixgbe_open(struct net_device *netdev)
5469 {
5470 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5471 int err;
5472
5473 /* disallow open during test */
5474 if (test_bit(__IXGBE_TESTING, &adapter->state))
5475 return -EBUSY;
5476
5477 netif_carrier_off(netdev);
5478
5479 /* allocate transmit descriptors */
5480 err = ixgbe_setup_all_tx_resources(adapter);
5481 if (err)
5482 goto err_setup_tx;
5483
5484 /* allocate receive descriptors */
5485 err = ixgbe_setup_all_rx_resources(adapter);
5486 if (err)
5487 goto err_setup_rx;
5488
5489 ixgbe_configure(adapter);
5490
5491 err = ixgbe_request_irq(adapter);
5492 if (err)
5493 goto err_req_irq;
5494
5495 err = ixgbe_up_complete(adapter);
5496 if (err)
5497 goto err_up;
5498
5499 netif_tx_start_all_queues(netdev);
5500
5501 return 0;
5502
5503 err_up:
5504 ixgbe_release_hw_control(adapter);
5505 ixgbe_free_irq(adapter);
5506 err_req_irq:
5507 err_setup_rx:
5508 ixgbe_free_all_rx_resources(adapter);
5509 err_setup_tx:
5510 ixgbe_free_all_tx_resources(adapter);
5511 ixgbe_reset(adapter);
5512
5513 return err;
5514 }
5515
5516 /**
5517 * ixgbe_close - Disables a network interface
5518 * @netdev: network interface device structure
5519 *
5520 * Returns 0, this is not allowed to fail
5521 *
5522 * The close entry point is called when an interface is de-activated
5523 * by the OS. The hardware is still under the drivers control, but
5524 * needs to be disabled. A global MAC reset is issued to stop the
5525 * hardware, and all transmit and receive resources are freed.
5526 **/
5527 static int ixgbe_close(struct net_device *netdev)
5528 {
5529 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5530
5531 ixgbe_down(adapter);
5532 ixgbe_free_irq(adapter);
5533
5534 ixgbe_free_all_tx_resources(adapter);
5535 ixgbe_free_all_rx_resources(adapter);
5536
5537 ixgbe_release_hw_control(adapter);
5538
5539 return 0;
5540 }
5541
5542 #ifdef CONFIG_PM
5543 static int ixgbe_resume(struct pci_dev *pdev)
5544 {
5545 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5546 struct net_device *netdev = adapter->netdev;
5547 u32 err;
5548
5549 pci_set_power_state(pdev, PCI_D0);
5550 pci_restore_state(pdev);
5551 /*
5552 * pci_restore_state clears dev->state_saved so call
5553 * pci_save_state to restore it.
5554 */
5555 pci_save_state(pdev);
5556
5557 err = pci_enable_device_mem(pdev);
5558 if (err) {
5559 e_dev_err("Cannot enable PCI device from suspend\n");
5560 return err;
5561 }
5562 pci_set_master(pdev);
5563
5564 pci_wake_from_d3(pdev, false);
5565
5566 err = ixgbe_init_interrupt_scheme(adapter);
5567 if (err) {
5568 e_dev_err("Cannot initialize interrupts for device\n");
5569 return err;
5570 }
5571
5572 ixgbe_reset(adapter);
5573
5574 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5575
5576 if (netif_running(netdev)) {
5577 err = ixgbe_open(netdev);
5578 if (err)
5579 return err;
5580 }
5581
5582 netif_device_attach(netdev);
5583
5584 return 0;
5585 }
5586 #endif /* CONFIG_PM */
5587
5588 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5589 {
5590 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5591 struct net_device *netdev = adapter->netdev;
5592 struct ixgbe_hw *hw = &adapter->hw;
5593 u32 ctrl, fctrl;
5594 u32 wufc = adapter->wol;
5595 #ifdef CONFIG_PM
5596 int retval = 0;
5597 #endif
5598
5599 netif_device_detach(netdev);
5600
5601 if (netif_running(netdev)) {
5602 ixgbe_down(adapter);
5603 ixgbe_free_irq(adapter);
5604 ixgbe_free_all_tx_resources(adapter);
5605 ixgbe_free_all_rx_resources(adapter);
5606 }
5607
5608 ixgbe_clear_interrupt_scheme(adapter);
5609
5610 #ifdef CONFIG_PM
5611 retval = pci_save_state(pdev);
5612 if (retval)
5613 return retval;
5614
5615 #endif
5616 if (wufc) {
5617 ixgbe_set_rx_mode(netdev);
5618
5619 /* turn on all-multi mode if wake on multicast is enabled */
5620 if (wufc & IXGBE_WUFC_MC) {
5621 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5622 fctrl |= IXGBE_FCTRL_MPE;
5623 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5624 }
5625
5626 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5627 ctrl |= IXGBE_CTRL_GIO_DIS;
5628 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5629
5630 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5631 } else {
5632 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5633 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5634 }
5635
5636 switch (hw->mac.type) {
5637 case ixgbe_mac_82598EB:
5638 pci_wake_from_d3(pdev, false);
5639 break;
5640 case ixgbe_mac_82599EB:
5641 case ixgbe_mac_X540:
5642 pci_wake_from_d3(pdev, !!wufc);
5643 break;
5644 default:
5645 break;
5646 }
5647
5648 *enable_wake = !!wufc;
5649
5650 ixgbe_release_hw_control(adapter);
5651
5652 pci_disable_device(pdev);
5653
5654 return 0;
5655 }
5656
5657 #ifdef CONFIG_PM
5658 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5659 {
5660 int retval;
5661 bool wake;
5662
5663 retval = __ixgbe_shutdown(pdev, &wake);
5664 if (retval)
5665 return retval;
5666
5667 if (wake) {
5668 pci_prepare_to_sleep(pdev);
5669 } else {
5670 pci_wake_from_d3(pdev, false);
5671 pci_set_power_state(pdev, PCI_D3hot);
5672 }
5673
5674 return 0;
5675 }
5676 #endif /* CONFIG_PM */
5677
5678 static void ixgbe_shutdown(struct pci_dev *pdev)
5679 {
5680 bool wake;
5681
5682 __ixgbe_shutdown(pdev, &wake);
5683
5684 if (system_state == SYSTEM_POWER_OFF) {
5685 pci_wake_from_d3(pdev, wake);
5686 pci_set_power_state(pdev, PCI_D3hot);
5687 }
5688 }
5689
5690 /**
5691 * ixgbe_update_stats - Update the board statistics counters.
5692 * @adapter: board private structure
5693 **/
5694 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5695 {
5696 struct net_device *netdev = adapter->netdev;
5697 struct ixgbe_hw *hw = &adapter->hw;
5698 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5699 u64 total_mpc = 0;
5700 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5701 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5702 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5703 u64 bytes = 0, packets = 0;
5704
5705 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5706 test_bit(__IXGBE_RESETTING, &adapter->state))
5707 return;
5708
5709 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5710 u64 rsc_count = 0;
5711 u64 rsc_flush = 0;
5712 for (i = 0; i < 16; i++)
5713 adapter->hw_rx_no_dma_resources +=
5714 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5715 for (i = 0; i < adapter->num_rx_queues; i++) {
5716 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5717 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5718 }
5719 adapter->rsc_total_count = rsc_count;
5720 adapter->rsc_total_flush = rsc_flush;
5721 }
5722
5723 for (i = 0; i < adapter->num_rx_queues; i++) {
5724 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5725 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5726 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5727 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5728 bytes += rx_ring->stats.bytes;
5729 packets += rx_ring->stats.packets;
5730 }
5731 adapter->non_eop_descs = non_eop_descs;
5732 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5733 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5734 netdev->stats.rx_bytes = bytes;
5735 netdev->stats.rx_packets = packets;
5736
5737 bytes = 0;
5738 packets = 0;
5739 /* gather some stats to the adapter struct that are per queue */
5740 for (i = 0; i < adapter->num_tx_queues; i++) {
5741 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5742 restart_queue += tx_ring->tx_stats.restart_queue;
5743 tx_busy += tx_ring->tx_stats.tx_busy;
5744 bytes += tx_ring->stats.bytes;
5745 packets += tx_ring->stats.packets;
5746 }
5747 adapter->restart_queue = restart_queue;
5748 adapter->tx_busy = tx_busy;
5749 netdev->stats.tx_bytes = bytes;
5750 netdev->stats.tx_packets = packets;
5751
5752 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5753 for (i = 0; i < 8; i++) {
5754 /* for packet buffers not used, the register should read 0 */
5755 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5756 missed_rx += mpc;
5757 hwstats->mpc[i] += mpc;
5758 total_mpc += hwstats->mpc[i];
5759 if (hw->mac.type == ixgbe_mac_82598EB)
5760 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5761 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5762 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5763 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5764 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5765 switch (hw->mac.type) {
5766 case ixgbe_mac_82598EB:
5767 hwstats->pxonrxc[i] +=
5768 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5769 break;
5770 case ixgbe_mac_82599EB:
5771 case ixgbe_mac_X540:
5772 hwstats->pxonrxc[i] +=
5773 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5774 break;
5775 default:
5776 break;
5777 }
5778 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5779 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5780 }
5781 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5782 /* work around hardware counting issue */
5783 hwstats->gprc -= missed_rx;
5784
5785 ixgbe_update_xoff_received(adapter);
5786
5787 /* 82598 hardware only has a 32 bit counter in the high register */
5788 switch (hw->mac.type) {
5789 case ixgbe_mac_82598EB:
5790 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5791 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5792 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5793 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5794 break;
5795 case ixgbe_mac_82599EB:
5796 case ixgbe_mac_X540:
5797 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5798 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5799 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5800 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5801 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5802 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5803 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5804 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5805 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5806 #ifdef IXGBE_FCOE
5807 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5808 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5809 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5810 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5811 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5812 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5813 #endif /* IXGBE_FCOE */
5814 break;
5815 default:
5816 break;
5817 }
5818 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5819 hwstats->bprc += bprc;
5820 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5821 if (hw->mac.type == ixgbe_mac_82598EB)
5822 hwstats->mprc -= bprc;
5823 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5824 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5825 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5826 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5827 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5828 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5829 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5830 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5831 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5832 hwstats->lxontxc += lxon;
5833 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5834 hwstats->lxofftxc += lxoff;
5835 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5836 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5837 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5838 /*
5839 * 82598 errata - tx of flow control packets is included in tx counters
5840 */
5841 xon_off_tot = lxon + lxoff;
5842 hwstats->gptc -= xon_off_tot;
5843 hwstats->mptc -= xon_off_tot;
5844 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5845 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5846 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5847 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5848 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5849 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5850 hwstats->ptc64 -= xon_off_tot;
5851 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5852 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5853 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5854 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5855 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5856 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5857
5858 /* Fill out the OS statistics structure */
5859 netdev->stats.multicast = hwstats->mprc;
5860
5861 /* Rx Errors */
5862 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5863 netdev->stats.rx_dropped = 0;
5864 netdev->stats.rx_length_errors = hwstats->rlec;
5865 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5866 netdev->stats.rx_missed_errors = total_mpc;
5867 }
5868
5869 /**
5870 * ixgbe_watchdog - Timer Call-back
5871 * @data: pointer to adapter cast into an unsigned long
5872 **/
5873 static void ixgbe_watchdog(unsigned long data)
5874 {
5875 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5876 struct ixgbe_hw *hw = &adapter->hw;
5877 u64 eics = 0;
5878 int i;
5879
5880 /*
5881 * Do the watchdog outside of interrupt context due to the lovely
5882 * delays that some of the newer hardware requires
5883 */
5884
5885 if (test_bit(__IXGBE_DOWN, &adapter->state))
5886 goto watchdog_short_circuit;
5887
5888 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5889 /*
5890 * for legacy and MSI interrupts don't set any bits
5891 * that are enabled for EIAM, because this operation
5892 * would set *both* EIMS and EICS for any bit in EIAM
5893 */
5894 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5895 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5896 goto watchdog_reschedule;
5897 }
5898
5899 /* get one bit for every active tx/rx interrupt vector */
5900 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5901 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5902 if (qv->rxr_count || qv->txr_count)
5903 eics |= ((u64)1 << i);
5904 }
5905
5906 /* Cause software interrupt to ensure rx rings are cleaned */
5907 ixgbe_irq_rearm_queues(adapter, eics);
5908
5909 watchdog_reschedule:
5910 /* Reset the timer */
5911 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5912
5913 watchdog_short_circuit:
5914 schedule_work(&adapter->watchdog_task);
5915 }
5916
5917 /**
5918 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5919 * @work: pointer to work_struct containing our data
5920 **/
5921 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5922 {
5923 struct ixgbe_adapter *adapter = container_of(work,
5924 struct ixgbe_adapter,
5925 multispeed_fiber_task);
5926 struct ixgbe_hw *hw = &adapter->hw;
5927 u32 autoneg;
5928 bool negotiation;
5929
5930 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5931 autoneg = hw->phy.autoneg_advertised;
5932 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5933 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5934 hw->mac.autotry_restart = false;
5935 if (hw->mac.ops.setup_link)
5936 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5937 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5938 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5939 }
5940
5941 /**
5942 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5943 * @work: pointer to work_struct containing our data
5944 **/
5945 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5946 {
5947 struct ixgbe_adapter *adapter = container_of(work,
5948 struct ixgbe_adapter,
5949 sfp_config_module_task);
5950 struct ixgbe_hw *hw = &adapter->hw;
5951 u32 err;
5952
5953 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5954
5955 /* Time for electrical oscillations to settle down */
5956 msleep(100);
5957 err = hw->phy.ops.identify_sfp(hw);
5958
5959 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5960 e_dev_err("failed to initialize because an unsupported SFP+ "
5961 "module type was detected.\n");
5962 e_dev_err("Reload the driver after installing a supported "
5963 "module.\n");
5964 unregister_netdev(adapter->netdev);
5965 return;
5966 }
5967 hw->mac.ops.setup_sfp(hw);
5968
5969 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5970 /* This will also work for DA Twinax connections */
5971 schedule_work(&adapter->multispeed_fiber_task);
5972 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5973 }
5974
5975 /**
5976 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5977 * @work: pointer to work_struct containing our data
5978 **/
5979 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5980 {
5981 struct ixgbe_adapter *adapter = container_of(work,
5982 struct ixgbe_adapter,
5983 fdir_reinit_task);
5984 struct ixgbe_hw *hw = &adapter->hw;
5985 int i;
5986
5987 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5988 for (i = 0; i < adapter->num_tx_queues; i++)
5989 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5990 &(adapter->tx_ring[i]->state));
5991 } else {
5992 e_err(probe, "failed to finish FDIR re-initialization, "
5993 "ignored adding FDIR ATR filters\n");
5994 }
5995 /* Done FDIR Re-initialization, enable transmits */
5996 netif_tx_start_all_queues(adapter->netdev);
5997 }
5998
5999 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6000 {
6001 u32 ssvpc;
6002
6003 /* Do not perform spoof check for 82598 */
6004 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6005 return;
6006
6007 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6008
6009 /*
6010 * ssvpc register is cleared on read, if zero then no
6011 * spoofed packets in the last interval.
6012 */
6013 if (!ssvpc)
6014 return;
6015
6016 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6017 }
6018
6019 static DEFINE_MUTEX(ixgbe_watchdog_lock);
6020
6021 /**
6022 * ixgbe_watchdog_task - worker thread to bring link up
6023 * @work: pointer to work_struct containing our data
6024 **/
6025 static void ixgbe_watchdog_task(struct work_struct *work)
6026 {
6027 struct ixgbe_adapter *adapter = container_of(work,
6028 struct ixgbe_adapter,
6029 watchdog_task);
6030 struct net_device *netdev = adapter->netdev;
6031 struct ixgbe_hw *hw = &adapter->hw;
6032 u32 link_speed;
6033 bool link_up;
6034 int i;
6035 struct ixgbe_ring *tx_ring;
6036 int some_tx_pending = 0;
6037
6038 mutex_lock(&ixgbe_watchdog_lock);
6039
6040 link_up = adapter->link_up;
6041 link_speed = adapter->link_speed;
6042
6043 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
6044 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
6045 if (link_up) {
6046 #ifdef CONFIG_DCB
6047 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6048 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
6049 hw->mac.ops.fc_enable(hw, i);
6050 } else {
6051 hw->mac.ops.fc_enable(hw, 0);
6052 }
6053 #else
6054 hw->mac.ops.fc_enable(hw, 0);
6055 #endif
6056 }
6057
6058 if (link_up ||
6059 time_after(jiffies, (adapter->link_check_timeout +
6060 IXGBE_TRY_LINK_TIMEOUT))) {
6061 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6062 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6063 }
6064 adapter->link_up = link_up;
6065 adapter->link_speed = link_speed;
6066 }
6067
6068 if (link_up) {
6069 if (!netif_carrier_ok(netdev)) {
6070 bool flow_rx, flow_tx;
6071
6072 switch (hw->mac.type) {
6073 case ixgbe_mac_82598EB: {
6074 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6075 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6076 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6077 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6078 }
6079 break;
6080 case ixgbe_mac_82599EB:
6081 case ixgbe_mac_X540: {
6082 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6083 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6084 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6085 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6086 }
6087 break;
6088 default:
6089 flow_tx = false;
6090 flow_rx = false;
6091 break;
6092 }
6093
6094 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6095 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6096 "10 Gbps" :
6097 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6098 "1 Gbps" : "unknown speed")),
6099 ((flow_rx && flow_tx) ? "RX/TX" :
6100 (flow_rx ? "RX" :
6101 (flow_tx ? "TX" : "None"))));
6102
6103 netif_carrier_on(netdev);
6104 } else {
6105 /* Force detection of hung controller */
6106 for (i = 0; i < adapter->num_tx_queues; i++) {
6107 tx_ring = adapter->tx_ring[i];
6108 set_check_for_tx_hang(tx_ring);
6109 }
6110 }
6111 } else {
6112 adapter->link_up = false;
6113 adapter->link_speed = 0;
6114 if (netif_carrier_ok(netdev)) {
6115 e_info(drv, "NIC Link is Down\n");
6116 netif_carrier_off(netdev);
6117 }
6118 }
6119
6120 if (!netif_carrier_ok(netdev)) {
6121 for (i = 0; i < adapter->num_tx_queues; i++) {
6122 tx_ring = adapter->tx_ring[i];
6123 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6124 some_tx_pending = 1;
6125 break;
6126 }
6127 }
6128
6129 if (some_tx_pending) {
6130 /* We've lost link, so the controller stops DMA,
6131 * but we've got queued Tx work that's never going
6132 * to get done, so reset controller to flush Tx.
6133 * (Do the reset outside of interrupt context).
6134 */
6135 schedule_work(&adapter->reset_task);
6136 }
6137 }
6138
6139 ixgbe_spoof_check(adapter);
6140 ixgbe_update_stats(adapter);
6141 mutex_unlock(&ixgbe_watchdog_lock);
6142 }
6143
6144 static int ixgbe_tso(struct ixgbe_adapter *adapter,
6145 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6146 u32 tx_flags, u8 *hdr_len, __be16 protocol)
6147 {
6148 struct ixgbe_adv_tx_context_desc *context_desc;
6149 unsigned int i;
6150 int err;
6151 struct ixgbe_tx_buffer *tx_buffer_info;
6152 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
6153 u32 mss_l4len_idx, l4len;
6154
6155 if (skb_is_gso(skb)) {
6156 if (skb_header_cloned(skb)) {
6157 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6158 if (err)
6159 return err;
6160 }
6161 l4len = tcp_hdrlen(skb);
6162 *hdr_len += l4len;
6163
6164 if (protocol == htons(ETH_P_IP)) {
6165 struct iphdr *iph = ip_hdr(skb);
6166 iph->tot_len = 0;
6167 iph->check = 0;
6168 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6169 iph->daddr, 0,
6170 IPPROTO_TCP,
6171 0);
6172 } else if (skb_is_gso_v6(skb)) {
6173 ipv6_hdr(skb)->payload_len = 0;
6174 tcp_hdr(skb)->check =
6175 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6176 &ipv6_hdr(skb)->daddr,
6177 0, IPPROTO_TCP, 0);
6178 }
6179
6180 i = tx_ring->next_to_use;
6181
6182 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6183 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6184
6185 /* VLAN MACLEN IPLEN */
6186 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6187 vlan_macip_lens |=
6188 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6189 vlan_macip_lens |= ((skb_network_offset(skb)) <<
6190 IXGBE_ADVTXD_MACLEN_SHIFT);
6191 *hdr_len += skb_network_offset(skb);
6192 vlan_macip_lens |=
6193 (skb_transport_header(skb) - skb_network_header(skb));
6194 *hdr_len +=
6195 (skb_transport_header(skb) - skb_network_header(skb));
6196 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6197 context_desc->seqnum_seed = 0;
6198
6199 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6200 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
6201 IXGBE_ADVTXD_DTYP_CTXT);
6202
6203 if (protocol == htons(ETH_P_IP))
6204 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
6205 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6206 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6207
6208 /* MSS L4LEN IDX */
6209 mss_l4len_idx =
6210 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
6211 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
6212 /* use index 1 for TSO */
6213 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6214 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6215
6216 tx_buffer_info->time_stamp = jiffies;
6217 tx_buffer_info->next_to_watch = i;
6218
6219 i++;
6220 if (i == tx_ring->count)
6221 i = 0;
6222 tx_ring->next_to_use = i;
6223
6224 return true;
6225 }
6226 return false;
6227 }
6228
6229 static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6230 __be16 protocol)
6231 {
6232 u32 rtn = 0;
6233
6234 switch (protocol) {
6235 case cpu_to_be16(ETH_P_IP):
6236 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
6237 switch (ip_hdr(skb)->protocol) {
6238 case IPPROTO_TCP:
6239 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6240 break;
6241 case IPPROTO_SCTP:
6242 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6243 break;
6244 }
6245 break;
6246 case cpu_to_be16(ETH_P_IPV6):
6247 /* XXX what about other V6 headers?? */
6248 switch (ipv6_hdr(skb)->nexthdr) {
6249 case IPPROTO_TCP:
6250 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6251 break;
6252 case IPPROTO_SCTP:
6253 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6254 break;
6255 }
6256 break;
6257 default:
6258 if (unlikely(net_ratelimit()))
6259 e_warn(probe, "partial checksum but proto=%x!\n",
6260 protocol);
6261 break;
6262 }
6263
6264 return rtn;
6265 }
6266
6267 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
6268 struct ixgbe_ring *tx_ring,
6269 struct sk_buff *skb, u32 tx_flags,
6270 __be16 protocol)
6271 {
6272 struct ixgbe_adv_tx_context_desc *context_desc;
6273 unsigned int i;
6274 struct ixgbe_tx_buffer *tx_buffer_info;
6275 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6276
6277 if (skb->ip_summed == CHECKSUM_PARTIAL ||
6278 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6279 i = tx_ring->next_to_use;
6280 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6281 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6282
6283 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6284 vlan_macip_lens |=
6285 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6286 vlan_macip_lens |= (skb_network_offset(skb) <<
6287 IXGBE_ADVTXD_MACLEN_SHIFT);
6288 if (skb->ip_summed == CHECKSUM_PARTIAL)
6289 vlan_macip_lens |= (skb_transport_header(skb) -
6290 skb_network_header(skb));
6291
6292 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6293 context_desc->seqnum_seed = 0;
6294
6295 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
6296 IXGBE_ADVTXD_DTYP_CTXT);
6297
6298 if (skb->ip_summed == CHECKSUM_PARTIAL)
6299 type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
6300
6301 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6302 /* use index zero for tx checksum offload */
6303 context_desc->mss_l4len_idx = 0;
6304
6305 tx_buffer_info->time_stamp = jiffies;
6306 tx_buffer_info->next_to_watch = i;
6307
6308 i++;
6309 if (i == tx_ring->count)
6310 i = 0;
6311 tx_ring->next_to_use = i;
6312
6313 return true;
6314 }
6315
6316 return false;
6317 }
6318
6319 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6320 struct ixgbe_ring *tx_ring,
6321 struct sk_buff *skb, u32 tx_flags,
6322 unsigned int first, const u8 hdr_len)
6323 {
6324 struct device *dev = tx_ring->dev;
6325 struct ixgbe_tx_buffer *tx_buffer_info;
6326 unsigned int len;
6327 unsigned int total = skb->len;
6328 unsigned int offset = 0, size, count = 0, i;
6329 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6330 unsigned int f;
6331 unsigned int bytecount = skb->len;
6332 u16 gso_segs = 1;
6333
6334 i = tx_ring->next_to_use;
6335
6336 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6337 /* excluding fcoe_crc_eof for FCoE */
6338 total -= sizeof(struct fcoe_crc_eof);
6339
6340 len = min(skb_headlen(skb), total);
6341 while (len) {
6342 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6343 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6344
6345 tx_buffer_info->length = size;
6346 tx_buffer_info->mapped_as_page = false;
6347 tx_buffer_info->dma = dma_map_single(dev,
6348 skb->data + offset,
6349 size, DMA_TO_DEVICE);
6350 if (dma_mapping_error(dev, tx_buffer_info->dma))
6351 goto dma_error;
6352 tx_buffer_info->time_stamp = jiffies;
6353 tx_buffer_info->next_to_watch = i;
6354
6355 len -= size;
6356 total -= size;
6357 offset += size;
6358 count++;
6359
6360 if (len) {
6361 i++;
6362 if (i == tx_ring->count)
6363 i = 0;
6364 }
6365 }
6366
6367 for (f = 0; f < nr_frags; f++) {
6368 struct skb_frag_struct *frag;
6369
6370 frag = &skb_shinfo(skb)->frags[f];
6371 len = min((unsigned int)frag->size, total);
6372 offset = frag->page_offset;
6373
6374 while (len) {
6375 i++;
6376 if (i == tx_ring->count)
6377 i = 0;
6378
6379 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6380 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6381
6382 tx_buffer_info->length = size;
6383 tx_buffer_info->dma = dma_map_page(dev,
6384 frag->page,
6385 offset, size,
6386 DMA_TO_DEVICE);
6387 tx_buffer_info->mapped_as_page = true;
6388 if (dma_mapping_error(dev, tx_buffer_info->dma))
6389 goto dma_error;
6390 tx_buffer_info->time_stamp = jiffies;
6391 tx_buffer_info->next_to_watch = i;
6392
6393 len -= size;
6394 total -= size;
6395 offset += size;
6396 count++;
6397 }
6398 if (total == 0)
6399 break;
6400 }
6401
6402 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6403 gso_segs = skb_shinfo(skb)->gso_segs;
6404 #ifdef IXGBE_FCOE
6405 /* adjust for FCoE Sequence Offload */
6406 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6407 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6408 skb_shinfo(skb)->gso_size);
6409 #endif /* IXGBE_FCOE */
6410 bytecount += (gso_segs - 1) * hdr_len;
6411
6412 /* multiply data chunks by size of headers */
6413 tx_ring->tx_buffer_info[i].bytecount = bytecount;
6414 tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6415 tx_ring->tx_buffer_info[i].skb = skb;
6416 tx_ring->tx_buffer_info[first].next_to_watch = i;
6417
6418 return count;
6419
6420 dma_error:
6421 e_dev_err("TX DMA map failed\n");
6422
6423 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6424 tx_buffer_info->dma = 0;
6425 tx_buffer_info->time_stamp = 0;
6426 tx_buffer_info->next_to_watch = 0;
6427 if (count)
6428 count--;
6429
6430 /* clear timestamp and dma mappings for remaining portion of packet */
6431 while (count--) {
6432 if (i == 0)
6433 i += tx_ring->count;
6434 i--;
6435 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6436 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6437 }
6438
6439 return 0;
6440 }
6441
6442 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6443 int tx_flags, int count, u32 paylen, u8 hdr_len)
6444 {
6445 union ixgbe_adv_tx_desc *tx_desc = NULL;
6446 struct ixgbe_tx_buffer *tx_buffer_info;
6447 u32 olinfo_status = 0, cmd_type_len = 0;
6448 unsigned int i;
6449 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6450
6451 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6452
6453 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6454
6455 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6456 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6457
6458 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6459 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6460
6461 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6462 IXGBE_ADVTXD_POPTS_SHIFT;
6463
6464 /* use index 1 context for tso */
6465 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6466 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6467 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6468 IXGBE_ADVTXD_POPTS_SHIFT;
6469
6470 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6471 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6472 IXGBE_ADVTXD_POPTS_SHIFT;
6473
6474 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6475 olinfo_status |= IXGBE_ADVTXD_CC;
6476 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6477 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6478 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6479 }
6480
6481 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6482
6483 i = tx_ring->next_to_use;
6484 while (count--) {
6485 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6486 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6487 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6488 tx_desc->read.cmd_type_len =
6489 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6490 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6491 i++;
6492 if (i == tx_ring->count)
6493 i = 0;
6494 }
6495
6496 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6497
6498 /*
6499 * Force memory writes to complete before letting h/w
6500 * know there are new descriptors to fetch. (Only
6501 * applicable for weak-ordered memory model archs,
6502 * such as IA-64).
6503 */
6504 wmb();
6505
6506 tx_ring->next_to_use = i;
6507 writel(i, tx_ring->tail);
6508 }
6509
6510 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6511 u32 tx_flags, __be16 protocol)
6512 {
6513 struct ixgbe_q_vector *q_vector = ring->q_vector;
6514 union ixgbe_atr_hash_dword input = { .dword = 0 };
6515 union ixgbe_atr_hash_dword common = { .dword = 0 };
6516 union {
6517 unsigned char *network;
6518 struct iphdr *ipv4;
6519 struct ipv6hdr *ipv6;
6520 } hdr;
6521 struct tcphdr *th;
6522 __be16 vlan_id;
6523
6524 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6525 if (!q_vector)
6526 return;
6527
6528 /* do nothing if sampling is disabled */
6529 if (!ring->atr_sample_rate)
6530 return;
6531
6532 ring->atr_count++;
6533
6534 /* snag network header to get L4 type and address */
6535 hdr.network = skb_network_header(skb);
6536
6537 /* Currently only IPv4/IPv6 with TCP is supported */
6538 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6539 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6540 (protocol != __constant_htons(ETH_P_IP) ||
6541 hdr.ipv4->protocol != IPPROTO_TCP))
6542 return;
6543
6544 th = tcp_hdr(skb);
6545
6546 /* skip this packet since the socket is closing */
6547 if (th->fin)
6548 return;
6549
6550 /* sample on all syn packets or once every atr sample count */
6551 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6552 return;
6553
6554 /* reset sample count */
6555 ring->atr_count = 0;
6556
6557 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6558
6559 /*
6560 * src and dst are inverted, think how the receiver sees them
6561 *
6562 * The input is broken into two sections, a non-compressed section
6563 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6564 * is XORed together and stored in the compressed dword.
6565 */
6566 input.formatted.vlan_id = vlan_id;
6567
6568 /*
6569 * since src port and flex bytes occupy the same word XOR them together
6570 * and write the value to source port portion of compressed dword
6571 */
6572 if (vlan_id)
6573 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6574 else
6575 common.port.src ^= th->dest ^ protocol;
6576 common.port.dst ^= th->source;
6577
6578 if (protocol == __constant_htons(ETH_P_IP)) {
6579 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6580 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6581 } else {
6582 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6583 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6584 hdr.ipv6->saddr.s6_addr32[1] ^
6585 hdr.ipv6->saddr.s6_addr32[2] ^
6586 hdr.ipv6->saddr.s6_addr32[3] ^
6587 hdr.ipv6->daddr.s6_addr32[0] ^
6588 hdr.ipv6->daddr.s6_addr32[1] ^
6589 hdr.ipv6->daddr.s6_addr32[2] ^
6590 hdr.ipv6->daddr.s6_addr32[3];
6591 }
6592
6593 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6594 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6595 input, common, ring->queue_index);
6596 }
6597
6598 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6599 {
6600 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6601 /* Herbert's original patch had:
6602 * smp_mb__after_netif_stop_queue();
6603 * but since that doesn't exist yet, just open code it. */
6604 smp_mb();
6605
6606 /* We need to check again in a case another CPU has just
6607 * made room available. */
6608 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6609 return -EBUSY;
6610
6611 /* A reprieve! - use start_queue because it doesn't call schedule */
6612 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6613 ++tx_ring->tx_stats.restart_queue;
6614 return 0;
6615 }
6616
6617 static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6618 {
6619 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6620 return 0;
6621 return __ixgbe_maybe_stop_tx(tx_ring, size);
6622 }
6623
6624 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6625 {
6626 struct ixgbe_adapter *adapter = netdev_priv(dev);
6627 int txq = smp_processor_id();
6628 #ifdef IXGBE_FCOE
6629 __be16 protocol;
6630
6631 protocol = vlan_get_protocol(skb);
6632
6633 if ((protocol == htons(ETH_P_FCOE)) ||
6634 (protocol == htons(ETH_P_FIP))) {
6635 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6636 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6637 txq += adapter->ring_feature[RING_F_FCOE].mask;
6638 return txq;
6639 #ifdef CONFIG_IXGBE_DCB
6640 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6641 txq = adapter->fcoe.up;
6642 return txq;
6643 #endif
6644 }
6645 }
6646 #endif
6647
6648 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6649 while (unlikely(txq >= dev->real_num_tx_queues))
6650 txq -= dev->real_num_tx_queues;
6651 return txq;
6652 }
6653
6654 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6655 if (skb->priority == TC_PRIO_CONTROL)
6656 txq = adapter->ring_feature[RING_F_DCB].indices-1;
6657 else
6658 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6659 >> 13;
6660 return txq;
6661 }
6662
6663 return skb_tx_hash(dev, skb);
6664 }
6665
6666 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6667 struct ixgbe_adapter *adapter,
6668 struct ixgbe_ring *tx_ring)
6669 {
6670 unsigned int first;
6671 unsigned int tx_flags = 0;
6672 u8 hdr_len = 0;
6673 int tso;
6674 int count = 0;
6675 unsigned int f;
6676 __be16 protocol;
6677
6678 protocol = vlan_get_protocol(skb);
6679
6680 if (vlan_tx_tag_present(skb)) {
6681 tx_flags |= vlan_tx_tag_get(skb);
6682 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6683 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6684 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6685 }
6686 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6687 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6688 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6689 skb->priority != TC_PRIO_CONTROL) {
6690 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6691 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6692 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6693 }
6694
6695 #ifdef IXGBE_FCOE
6696 /* for FCoE with DCB, we force the priority to what
6697 * was specified by the switch */
6698 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6699 (protocol == htons(ETH_P_FCOE) ||
6700 protocol == htons(ETH_P_FIP))) {
6701 #ifdef CONFIG_IXGBE_DCB
6702 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6703 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6704 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6705 tx_flags |= ((adapter->fcoe.up << 13)
6706 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6707 }
6708 #endif
6709 /* flag for FCoE offloads */
6710 if (protocol == htons(ETH_P_FCOE))
6711 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6712 }
6713 #endif
6714
6715 /* four things can cause us to need a context descriptor */
6716 if (skb_is_gso(skb) ||
6717 (skb->ip_summed == CHECKSUM_PARTIAL) ||
6718 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6719 (tx_flags & IXGBE_TX_FLAGS_FCOE))
6720 count++;
6721
6722 count += TXD_USE_COUNT(skb_headlen(skb));
6723 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6724 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6725
6726 if (ixgbe_maybe_stop_tx(tx_ring, count)) {
6727 tx_ring->tx_stats.tx_busy++;
6728 return NETDEV_TX_BUSY;
6729 }
6730
6731 first = tx_ring->next_to_use;
6732 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6733 #ifdef IXGBE_FCOE
6734 /* setup tx offload for FCoE */
6735 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6736 if (tso < 0) {
6737 dev_kfree_skb_any(skb);
6738 return NETDEV_TX_OK;
6739 }
6740 if (tso)
6741 tx_flags |= IXGBE_TX_FLAGS_FSO;
6742 #endif /* IXGBE_FCOE */
6743 } else {
6744 if (protocol == htons(ETH_P_IP))
6745 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6746 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6747 protocol);
6748 if (tso < 0) {
6749 dev_kfree_skb_any(skb);
6750 return NETDEV_TX_OK;
6751 }
6752
6753 if (tso)
6754 tx_flags |= IXGBE_TX_FLAGS_TSO;
6755 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6756 protocol) &&
6757 (skb->ip_summed == CHECKSUM_PARTIAL))
6758 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6759 }
6760
6761 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6762 if (count) {
6763 /* add the ATR filter if ATR is on */
6764 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6765 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6766 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
6767 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6768
6769 } else {
6770 dev_kfree_skb_any(skb);
6771 tx_ring->tx_buffer_info[first].time_stamp = 0;
6772 tx_ring->next_to_use = first;
6773 }
6774
6775 return NETDEV_TX_OK;
6776 }
6777
6778 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6779 {
6780 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6781 struct ixgbe_ring *tx_ring;
6782
6783 tx_ring = adapter->tx_ring[skb->queue_mapping];
6784 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6785 }
6786
6787 /**
6788 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6789 * @netdev: network interface device structure
6790 * @p: pointer to an address structure
6791 *
6792 * Returns 0 on success, negative on failure
6793 **/
6794 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6795 {
6796 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6797 struct ixgbe_hw *hw = &adapter->hw;
6798 struct sockaddr *addr = p;
6799
6800 if (!is_valid_ether_addr(addr->sa_data))
6801 return -EADDRNOTAVAIL;
6802
6803 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6804 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6805
6806 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6807 IXGBE_RAH_AV);
6808
6809 return 0;
6810 }
6811
6812 static int
6813 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6814 {
6815 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6816 struct ixgbe_hw *hw = &adapter->hw;
6817 u16 value;
6818 int rc;
6819
6820 if (prtad != hw->phy.mdio.prtad)
6821 return -EINVAL;
6822 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6823 if (!rc)
6824 rc = value;
6825 return rc;
6826 }
6827
6828 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6829 u16 addr, u16 value)
6830 {
6831 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6832 struct ixgbe_hw *hw = &adapter->hw;
6833
6834 if (prtad != hw->phy.mdio.prtad)
6835 return -EINVAL;
6836 return hw->phy.ops.write_reg(hw, addr, devad, value);
6837 }
6838
6839 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6840 {
6841 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6842
6843 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6844 }
6845
6846 /**
6847 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6848 * netdev->dev_addrs
6849 * @netdev: network interface device structure
6850 *
6851 * Returns non-zero on failure
6852 **/
6853 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6854 {
6855 int err = 0;
6856 struct ixgbe_adapter *adapter = netdev_priv(dev);
6857 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6858
6859 if (is_valid_ether_addr(mac->san_addr)) {
6860 rtnl_lock();
6861 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6862 rtnl_unlock();
6863 }
6864 return err;
6865 }
6866
6867 /**
6868 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6869 * netdev->dev_addrs
6870 * @netdev: network interface device structure
6871 *
6872 * Returns non-zero on failure
6873 **/
6874 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6875 {
6876 int err = 0;
6877 struct ixgbe_adapter *adapter = netdev_priv(dev);
6878 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6879
6880 if (is_valid_ether_addr(mac->san_addr)) {
6881 rtnl_lock();
6882 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6883 rtnl_unlock();
6884 }
6885 return err;
6886 }
6887
6888 #ifdef CONFIG_NET_POLL_CONTROLLER
6889 /*
6890 * Polling 'interrupt' - used by things like netconsole to send skbs
6891 * without having to re-enable interrupts. It's not called while
6892 * the interrupt routine is executing.
6893 */
6894 static void ixgbe_netpoll(struct net_device *netdev)
6895 {
6896 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6897 int i;
6898
6899 /* if interface is down do nothing */
6900 if (test_bit(__IXGBE_DOWN, &adapter->state))
6901 return;
6902
6903 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6904 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6905 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6906 for (i = 0; i < num_q_vectors; i++) {
6907 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6908 ixgbe_msix_clean_many(0, q_vector);
6909 }
6910 } else {
6911 ixgbe_intr(adapter->pdev->irq, netdev);
6912 }
6913 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6914 }
6915 #endif
6916
6917 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6918 struct rtnl_link_stats64 *stats)
6919 {
6920 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6921 int i;
6922
6923 rcu_read_lock();
6924 for (i = 0; i < adapter->num_rx_queues; i++) {
6925 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6926 u64 bytes, packets;
6927 unsigned int start;
6928
6929 if (ring) {
6930 do {
6931 start = u64_stats_fetch_begin_bh(&ring->syncp);
6932 packets = ring->stats.packets;
6933 bytes = ring->stats.bytes;
6934 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6935 stats->rx_packets += packets;
6936 stats->rx_bytes += bytes;
6937 }
6938 }
6939
6940 for (i = 0; i < adapter->num_tx_queues; i++) {
6941 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6942 u64 bytes, packets;
6943 unsigned int start;
6944
6945 if (ring) {
6946 do {
6947 start = u64_stats_fetch_begin_bh(&ring->syncp);
6948 packets = ring->stats.packets;
6949 bytes = ring->stats.bytes;
6950 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6951 stats->tx_packets += packets;
6952 stats->tx_bytes += bytes;
6953 }
6954 }
6955 rcu_read_unlock();
6956 /* following stats updated by ixgbe_watchdog_task() */
6957 stats->multicast = netdev->stats.multicast;
6958 stats->rx_errors = netdev->stats.rx_errors;
6959 stats->rx_length_errors = netdev->stats.rx_length_errors;
6960 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6961 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6962 return stats;
6963 }
6964
6965
6966 static const struct net_device_ops ixgbe_netdev_ops = {
6967 .ndo_open = ixgbe_open,
6968 .ndo_stop = ixgbe_close,
6969 .ndo_start_xmit = ixgbe_xmit_frame,
6970 .ndo_select_queue = ixgbe_select_queue,
6971 .ndo_set_rx_mode = ixgbe_set_rx_mode,
6972 .ndo_set_multicast_list = ixgbe_set_rx_mode,
6973 .ndo_validate_addr = eth_validate_addr,
6974 .ndo_set_mac_address = ixgbe_set_mac,
6975 .ndo_change_mtu = ixgbe_change_mtu,
6976 .ndo_tx_timeout = ixgbe_tx_timeout,
6977 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6978 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6979 .ndo_do_ioctl = ixgbe_ioctl,
6980 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6981 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6982 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6983 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
6984 .ndo_get_stats64 = ixgbe_get_stats64,
6985 #ifdef CONFIG_NET_POLL_CONTROLLER
6986 .ndo_poll_controller = ixgbe_netpoll,
6987 #endif
6988 #ifdef IXGBE_FCOE
6989 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6990 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6991 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6992 .ndo_fcoe_disable = ixgbe_fcoe_disable,
6993 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6994 #endif /* IXGBE_FCOE */
6995 };
6996
6997 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6998 const struct ixgbe_info *ii)
6999 {
7000 #ifdef CONFIG_PCI_IOV
7001 struct ixgbe_hw *hw = &adapter->hw;
7002 int err;
7003
7004 if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
7005 return;
7006
7007 /* The 82599 supports up to 64 VFs per physical function
7008 * but this implementation limits allocation to 63 so that
7009 * basic networking resources are still available to the
7010 * physical function
7011 */
7012 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7013 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7014 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7015 if (err) {
7016 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
7017 goto err_novfs;
7018 }
7019 /* If call to enable VFs succeeded then allocate memory
7020 * for per VF control structures.
7021 */
7022 adapter->vfinfo =
7023 kcalloc(adapter->num_vfs,
7024 sizeof(struct vf_data_storage), GFP_KERNEL);
7025 if (adapter->vfinfo) {
7026 /* Now that we're sure SR-IOV is enabled
7027 * and memory allocated set up the mailbox parameters
7028 */
7029 ixgbe_init_mbx_params_pf(hw);
7030 memcpy(&hw->mbx.ops, ii->mbx_ops,
7031 sizeof(hw->mbx.ops));
7032
7033 /* Disable RSC when in SR-IOV mode */
7034 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7035 IXGBE_FLAG2_RSC_ENABLED);
7036 return;
7037 }
7038
7039 /* Oh oh */
7040 e_err(probe, "Unable to allocate memory for VF Data Storage - "
7041 "SRIOV disabled\n");
7042 pci_disable_sriov(adapter->pdev);
7043
7044 err_novfs:
7045 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7046 adapter->num_vfs = 0;
7047 #endif /* CONFIG_PCI_IOV */
7048 }
7049
7050 /**
7051 * ixgbe_probe - Device Initialization Routine
7052 * @pdev: PCI device information struct
7053 * @ent: entry in ixgbe_pci_tbl
7054 *
7055 * Returns 0 on success, negative on failure
7056 *
7057 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7058 * The OS initialization, configuring of the adapter private structure,
7059 * and a hardware reset occur.
7060 **/
7061 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7062 const struct pci_device_id *ent)
7063 {
7064 struct net_device *netdev;
7065 struct ixgbe_adapter *adapter = NULL;
7066 struct ixgbe_hw *hw;
7067 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7068 static int cards_found;
7069 int i, err, pci_using_dac;
7070 u8 part_str[IXGBE_PBANUM_LENGTH];
7071 unsigned int indices = num_possible_cpus();
7072 #ifdef IXGBE_FCOE
7073 u16 device_caps;
7074 #endif
7075 u32 eec;
7076
7077 /* Catch broken hardware that put the wrong VF device ID in
7078 * the PCIe SR-IOV capability.
7079 */
7080 if (pdev->is_virtfn) {
7081 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7082 pci_name(pdev), pdev->vendor, pdev->device);
7083 return -EINVAL;
7084 }
7085
7086 err = pci_enable_device_mem(pdev);
7087 if (err)
7088 return err;
7089
7090 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7091 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7092 pci_using_dac = 1;
7093 } else {
7094 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7095 if (err) {
7096 err = dma_set_coherent_mask(&pdev->dev,
7097 DMA_BIT_MASK(32));
7098 if (err) {
7099 dev_err(&pdev->dev,
7100 "No usable DMA configuration, aborting\n");
7101 goto err_dma;
7102 }
7103 }
7104 pci_using_dac = 0;
7105 }
7106
7107 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7108 IORESOURCE_MEM), ixgbe_driver_name);
7109 if (err) {
7110 dev_err(&pdev->dev,
7111 "pci_request_selected_regions failed 0x%x\n", err);
7112 goto err_pci_reg;
7113 }
7114
7115 pci_enable_pcie_error_reporting(pdev);
7116
7117 pci_set_master(pdev);
7118 pci_save_state(pdev);
7119
7120 if (ii->mac == ixgbe_mac_82598EB)
7121 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7122 else
7123 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7124
7125 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
7126 #ifdef IXGBE_FCOE
7127 indices += min_t(unsigned int, num_possible_cpus(),
7128 IXGBE_MAX_FCOE_INDICES);
7129 #endif
7130 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7131 if (!netdev) {
7132 err = -ENOMEM;
7133 goto err_alloc_etherdev;
7134 }
7135
7136 SET_NETDEV_DEV(netdev, &pdev->dev);
7137
7138 adapter = netdev_priv(netdev);
7139 pci_set_drvdata(pdev, adapter);
7140
7141 adapter->netdev = netdev;
7142 adapter->pdev = pdev;
7143 hw = &adapter->hw;
7144 hw->back = adapter;
7145 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7146
7147 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7148 pci_resource_len(pdev, 0));
7149 if (!hw->hw_addr) {
7150 err = -EIO;
7151 goto err_ioremap;
7152 }
7153
7154 for (i = 1; i <= 5; i++) {
7155 if (pci_resource_len(pdev, i) == 0)
7156 continue;
7157 }
7158
7159 netdev->netdev_ops = &ixgbe_netdev_ops;
7160 ixgbe_set_ethtool_ops(netdev);
7161 netdev->watchdog_timeo = 5 * HZ;
7162 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7163
7164 adapter->bd_number = cards_found;
7165
7166 /* Setup hw api */
7167 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7168 hw->mac.type = ii->mac;
7169
7170 /* EEPROM */
7171 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7172 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7173 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7174 if (!(eec & (1 << 8)))
7175 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7176
7177 /* PHY */
7178 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7179 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7180 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7181 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7182 hw->phy.mdio.mmds = 0;
7183 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7184 hw->phy.mdio.dev = netdev;
7185 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7186 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7187
7188 /* set up this timer and work struct before calling get_invariants
7189 * which might start the timer
7190 */
7191 init_timer(&adapter->sfp_timer);
7192 adapter->sfp_timer.function = ixgbe_sfp_timer;
7193 adapter->sfp_timer.data = (unsigned long) adapter;
7194
7195 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
7196
7197 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
7198 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
7199
7200 /* a new SFP+ module arrival, called from GPI SDP2 context */
7201 INIT_WORK(&adapter->sfp_config_module_task,
7202 ixgbe_sfp_config_module_task);
7203
7204 ii->get_invariants(hw);
7205
7206 /* setup the private structure */
7207 err = ixgbe_sw_init(adapter);
7208 if (err)
7209 goto err_sw_init;
7210
7211 /* Make it possible the adapter to be woken up via WOL */
7212 switch (adapter->hw.mac.type) {
7213 case ixgbe_mac_82599EB:
7214 case ixgbe_mac_X540:
7215 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7216 break;
7217 default:
7218 break;
7219 }
7220
7221 /*
7222 * If there is a fan on this device and it has failed log the
7223 * failure.
7224 */
7225 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7226 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7227 if (esdp & IXGBE_ESDP_SDP1)
7228 e_crit(probe, "Fan has stopped, replace the adapter\n");
7229 }
7230
7231 /* reset_hw fills in the perm_addr as well */
7232 hw->phy.reset_if_overtemp = true;
7233 err = hw->mac.ops.reset_hw(hw);
7234 hw->phy.reset_if_overtemp = false;
7235 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7236 hw->mac.type == ixgbe_mac_82598EB) {
7237 /*
7238 * Start a kernel thread to watch for a module to arrive.
7239 * Only do this for 82598, since 82599 will generate
7240 * interrupts on module arrival.
7241 */
7242 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7243 mod_timer(&adapter->sfp_timer,
7244 round_jiffies(jiffies + (2 * HZ)));
7245 err = 0;
7246 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7247 e_dev_err("failed to initialize because an unsupported SFP+ "
7248 "module type was detected.\n");
7249 e_dev_err("Reload the driver after installing a supported "
7250 "module.\n");
7251 goto err_sw_init;
7252 } else if (err) {
7253 e_dev_err("HW Init failed: %d\n", err);
7254 goto err_sw_init;
7255 }
7256
7257 ixgbe_probe_vf(adapter, ii);
7258
7259 netdev->features = NETIF_F_SG |
7260 NETIF_F_IP_CSUM |
7261 NETIF_F_HW_VLAN_TX |
7262 NETIF_F_HW_VLAN_RX |
7263 NETIF_F_HW_VLAN_FILTER;
7264
7265 netdev->features |= NETIF_F_IPV6_CSUM;
7266 netdev->features |= NETIF_F_TSO;
7267 netdev->features |= NETIF_F_TSO6;
7268 netdev->features |= NETIF_F_GRO;
7269
7270 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
7271 netdev->features |= NETIF_F_SCTP_CSUM;
7272
7273 netdev->vlan_features |= NETIF_F_TSO;
7274 netdev->vlan_features |= NETIF_F_TSO6;
7275 netdev->vlan_features |= NETIF_F_IP_CSUM;
7276 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7277 netdev->vlan_features |= NETIF_F_SG;
7278
7279 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7280 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7281 IXGBE_FLAG_DCB_ENABLED);
7282 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7283 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
7284
7285 #ifdef CONFIG_IXGBE_DCB
7286 netdev->dcbnl_ops = &dcbnl_ops;
7287 #endif
7288
7289 #ifdef IXGBE_FCOE
7290 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7291 if (hw->mac.ops.get_device_caps) {
7292 hw->mac.ops.get_device_caps(hw, &device_caps);
7293 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7294 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7295 }
7296 }
7297 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7298 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7299 netdev->vlan_features |= NETIF_F_FSO;
7300 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7301 }
7302 #endif /* IXGBE_FCOE */
7303 if (pci_using_dac) {
7304 netdev->features |= NETIF_F_HIGHDMA;
7305 netdev->vlan_features |= NETIF_F_HIGHDMA;
7306 }
7307
7308 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7309 netdev->features |= NETIF_F_LRO;
7310
7311 /* make sure the EEPROM is good */
7312 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7313 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7314 err = -EIO;
7315 goto err_eeprom;
7316 }
7317
7318 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7319 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7320
7321 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7322 e_dev_err("invalid MAC address\n");
7323 err = -EIO;
7324 goto err_eeprom;
7325 }
7326
7327 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7328 if (hw->mac.ops.disable_tx_laser &&
7329 ((hw->phy.multispeed_fiber) ||
7330 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7331 (hw->mac.type == ixgbe_mac_82599EB))))
7332 hw->mac.ops.disable_tx_laser(hw);
7333
7334 init_timer(&adapter->watchdog_timer);
7335 adapter->watchdog_timer.function = ixgbe_watchdog;
7336 adapter->watchdog_timer.data = (unsigned long)adapter;
7337
7338 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
7339 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
7340
7341 err = ixgbe_init_interrupt_scheme(adapter);
7342 if (err)
7343 goto err_sw_init;
7344
7345 switch (pdev->device) {
7346 case IXGBE_DEV_ID_82599_SFP:
7347 /* Only this subdevice supports WOL */
7348 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7349 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7350 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7351 break;
7352 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7353 /* All except this subdevice support WOL */
7354 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7355 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7356 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7357 break;
7358 case IXGBE_DEV_ID_82599_KX4:
7359 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7360 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7361 break;
7362 default:
7363 adapter->wol = 0;
7364 break;
7365 }
7366 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7367
7368 /* pick up the PCI bus settings for reporting later */
7369 hw->mac.ops.get_bus_info(hw);
7370
7371 /* print bus type/speed/width info */
7372 e_dev_info("(PCI Express:%s:%s) %pM\n",
7373 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
7374 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
7375 "Unknown"),
7376 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7377 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7378 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7379 "Unknown"),
7380 netdev->dev_addr);
7381
7382 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7383 if (err)
7384 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7385 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7386 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7387 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7388 part_str);
7389 else
7390 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7391 hw->mac.type, hw->phy.type, part_str);
7392
7393 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7394 e_dev_warn("PCI-Express bandwidth available for this card is "
7395 "not sufficient for optimal performance.\n");
7396 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7397 "is required.\n");
7398 }
7399
7400 /* save off EEPROM version number */
7401 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7402
7403 /* reset the hardware with the new settings */
7404 err = hw->mac.ops.start_hw(hw);
7405
7406 if (err == IXGBE_ERR_EEPROM_VERSION) {
7407 /* We are running on a pre-production device, log a warning */
7408 e_dev_warn("This device is a pre-production adapter/LOM. "
7409 "Please be aware there may be issues associated "
7410 "with your hardware. If you are experiencing "
7411 "problems please contact your Intel or hardware "
7412 "representative who provided you with this "
7413 "hardware.\n");
7414 }
7415 strcpy(netdev->name, "eth%d");
7416 err = register_netdev(netdev);
7417 if (err)
7418 goto err_register;
7419
7420 /* carrier off reporting is important to ethtool even BEFORE open */
7421 netif_carrier_off(netdev);
7422
7423 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7424 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7425 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7426
7427 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7428 INIT_WORK(&adapter->check_overtemp_task,
7429 ixgbe_check_overtemp_task);
7430 #ifdef CONFIG_IXGBE_DCA
7431 if (dca_add_requester(&pdev->dev) == 0) {
7432 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7433 ixgbe_setup_dca(adapter);
7434 }
7435 #endif
7436 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7437 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7438 for (i = 0; i < adapter->num_vfs; i++)
7439 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7440 }
7441
7442 /* add san mac addr to netdev */
7443 ixgbe_add_sanmac_netdev(netdev);
7444
7445 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7446 cards_found++;
7447 return 0;
7448
7449 err_register:
7450 ixgbe_release_hw_control(adapter);
7451 ixgbe_clear_interrupt_scheme(adapter);
7452 err_sw_init:
7453 err_eeprom:
7454 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7455 ixgbe_disable_sriov(adapter);
7456 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7457 del_timer_sync(&adapter->sfp_timer);
7458 cancel_work_sync(&adapter->sfp_task);
7459 cancel_work_sync(&adapter->multispeed_fiber_task);
7460 cancel_work_sync(&adapter->sfp_config_module_task);
7461 iounmap(hw->hw_addr);
7462 err_ioremap:
7463 free_netdev(netdev);
7464 err_alloc_etherdev:
7465 pci_release_selected_regions(pdev,
7466 pci_select_bars(pdev, IORESOURCE_MEM));
7467 err_pci_reg:
7468 err_dma:
7469 pci_disable_device(pdev);
7470 return err;
7471 }
7472
7473 /**
7474 * ixgbe_remove - Device Removal Routine
7475 * @pdev: PCI device information struct
7476 *
7477 * ixgbe_remove is called by the PCI subsystem to alert the driver
7478 * that it should release a PCI device. The could be caused by a
7479 * Hot-Plug event, or because the driver is going to be removed from
7480 * memory.
7481 **/
7482 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7483 {
7484 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7485 struct net_device *netdev = adapter->netdev;
7486
7487 set_bit(__IXGBE_DOWN, &adapter->state);
7488
7489 /*
7490 * The timers may be rescheduled, so explicitly disable them
7491 * from being rescheduled.
7492 */
7493 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7494 del_timer_sync(&adapter->watchdog_timer);
7495 del_timer_sync(&adapter->sfp_timer);
7496
7497 cancel_work_sync(&adapter->watchdog_task);
7498 cancel_work_sync(&adapter->sfp_task);
7499 cancel_work_sync(&adapter->multispeed_fiber_task);
7500 cancel_work_sync(&adapter->sfp_config_module_task);
7501 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7502 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7503 cancel_work_sync(&adapter->fdir_reinit_task);
7504 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7505 cancel_work_sync(&adapter->check_overtemp_task);
7506
7507 #ifdef CONFIG_IXGBE_DCA
7508 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7509 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7510 dca_remove_requester(&pdev->dev);
7511 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7512 }
7513
7514 #endif
7515 #ifdef IXGBE_FCOE
7516 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7517 ixgbe_cleanup_fcoe(adapter);
7518
7519 #endif /* IXGBE_FCOE */
7520
7521 /* remove the added san mac */
7522 ixgbe_del_sanmac_netdev(netdev);
7523
7524 if (netdev->reg_state == NETREG_REGISTERED)
7525 unregister_netdev(netdev);
7526
7527 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7528 ixgbe_disable_sriov(adapter);
7529
7530 ixgbe_clear_interrupt_scheme(adapter);
7531
7532 ixgbe_release_hw_control(adapter);
7533
7534 iounmap(adapter->hw.hw_addr);
7535 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7536 IORESOURCE_MEM));
7537
7538 e_dev_info("complete\n");
7539
7540 free_netdev(netdev);
7541
7542 pci_disable_pcie_error_reporting(pdev);
7543
7544 pci_disable_device(pdev);
7545 }
7546
7547 /**
7548 * ixgbe_io_error_detected - called when PCI error is detected
7549 * @pdev: Pointer to PCI device
7550 * @state: The current pci connection state
7551 *
7552 * This function is called after a PCI bus error affecting
7553 * this device has been detected.
7554 */
7555 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7556 pci_channel_state_t state)
7557 {
7558 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7559 struct net_device *netdev = adapter->netdev;
7560
7561 netif_device_detach(netdev);
7562
7563 if (state == pci_channel_io_perm_failure)
7564 return PCI_ERS_RESULT_DISCONNECT;
7565
7566 if (netif_running(netdev))
7567 ixgbe_down(adapter);
7568 pci_disable_device(pdev);
7569
7570 /* Request a slot reset. */
7571 return PCI_ERS_RESULT_NEED_RESET;
7572 }
7573
7574 /**
7575 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7576 * @pdev: Pointer to PCI device
7577 *
7578 * Restart the card from scratch, as if from a cold-boot.
7579 */
7580 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7581 {
7582 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7583 pci_ers_result_t result;
7584 int err;
7585
7586 if (pci_enable_device_mem(pdev)) {
7587 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7588 result = PCI_ERS_RESULT_DISCONNECT;
7589 } else {
7590 pci_set_master(pdev);
7591 pci_restore_state(pdev);
7592 pci_save_state(pdev);
7593
7594 pci_wake_from_d3(pdev, false);
7595
7596 ixgbe_reset(adapter);
7597 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7598 result = PCI_ERS_RESULT_RECOVERED;
7599 }
7600
7601 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7602 if (err) {
7603 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7604 "failed 0x%0x\n", err);
7605 /* non-fatal, continue */
7606 }
7607
7608 return result;
7609 }
7610
7611 /**
7612 * ixgbe_io_resume - called when traffic can start flowing again.
7613 * @pdev: Pointer to PCI device
7614 *
7615 * This callback is called when the error recovery driver tells us that
7616 * its OK to resume normal operation.
7617 */
7618 static void ixgbe_io_resume(struct pci_dev *pdev)
7619 {
7620 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7621 struct net_device *netdev = adapter->netdev;
7622
7623 if (netif_running(netdev)) {
7624 if (ixgbe_up(adapter)) {
7625 e_info(probe, "ixgbe_up failed after reset\n");
7626 return;
7627 }
7628 }
7629
7630 netif_device_attach(netdev);
7631 }
7632
7633 static struct pci_error_handlers ixgbe_err_handler = {
7634 .error_detected = ixgbe_io_error_detected,
7635 .slot_reset = ixgbe_io_slot_reset,
7636 .resume = ixgbe_io_resume,
7637 };
7638
7639 static struct pci_driver ixgbe_driver = {
7640 .name = ixgbe_driver_name,
7641 .id_table = ixgbe_pci_tbl,
7642 .probe = ixgbe_probe,
7643 .remove = __devexit_p(ixgbe_remove),
7644 #ifdef CONFIG_PM
7645 .suspend = ixgbe_suspend,
7646 .resume = ixgbe_resume,
7647 #endif
7648 .shutdown = ixgbe_shutdown,
7649 .err_handler = &ixgbe_err_handler
7650 };
7651
7652 /**
7653 * ixgbe_init_module - Driver Registration Routine
7654 *
7655 * ixgbe_init_module is the first routine called when the driver is
7656 * loaded. All it does is register with the PCI subsystem.
7657 **/
7658 static int __init ixgbe_init_module(void)
7659 {
7660 int ret;
7661 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7662 pr_info("%s\n", ixgbe_copyright);
7663
7664 #ifdef CONFIG_IXGBE_DCA
7665 dca_register_notify(&dca_notifier);
7666 #endif
7667
7668 ret = pci_register_driver(&ixgbe_driver);
7669 return ret;
7670 }
7671
7672 module_init(ixgbe_init_module);
7673
7674 /**
7675 * ixgbe_exit_module - Driver Exit Cleanup Routine
7676 *
7677 * ixgbe_exit_module is called just before the driver is removed
7678 * from memory.
7679 **/
7680 static void __exit ixgbe_exit_module(void)
7681 {
7682 #ifdef CONFIG_IXGBE_DCA
7683 dca_unregister_notify(&dca_notifier);
7684 #endif
7685 pci_unregister_driver(&ixgbe_driver);
7686 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7687 }
7688
7689 #ifdef CONFIG_IXGBE_DCA
7690 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7691 void *p)
7692 {
7693 int ret_val;
7694
7695 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7696 __ixgbe_notify_dca);
7697
7698 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7699 }
7700
7701 #endif /* CONFIG_IXGBE_DCA */
7702
7703 /**
7704 * ixgbe_get_hw_dev return device
7705 * used by hardware layer to print debugging information
7706 **/
7707 struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
7708 {
7709 struct ixgbe_adapter *adapter = hw->back;
7710 return adapter->netdev;
7711 }
7712
7713 module_exit(ixgbe_exit_module);
7714
7715 /* ixgbe_main.c */
Linux kernel - Deliverables
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