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[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <net/checksum.h>
40 #include <net/ip6_checksum.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <scsi/fc/fc_fcoe.h>
44
45 #include "ixgbe.h"
46 #include "ixgbe_common.h"
47 #include "ixgbe_dcb_82599.h"
48 #include "ixgbe_sriov.h"
49
50 char ixgbe_driver_name[] = "ixgbe";
51 static const char ixgbe_driver_string[] =
52 "Intel(R) 10 Gigabit PCI Express Network Driver";
53
54 #define DRV_VERSION "2.0.44-k2"
55 const char ixgbe_driver_version[] = DRV_VERSION;
56 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
57
58 static const struct ixgbe_info *ixgbe_info_tbl[] = {
59 [board_82598] = &ixgbe_82598_info,
60 [board_82599] = &ixgbe_82599_info,
61 };
62
63 /* ixgbe_pci_tbl - PCI Device ID Table
64 *
65 * Wildcard entries (PCI_ANY_ID) should come last
66 * Last entry must be all 0s
67 *
68 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
69 * Class, Class Mask, private data (not used) }
70 */
71 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
72 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
73 board_82598 },
74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
75 board_82598 },
76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
77 board_82598 },
78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
79 board_82598 },
80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
81 board_82598 },
82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
83 board_82598 },
84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
85 board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
87 board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
89 board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
91 board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
93 board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
95 board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
97 board_82599 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
99 board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
101 board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
103 board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
105 board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
107 board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
109 board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
111 board_82599 },
112
113 /* required last entry */
114 {0, }
115 };
116 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
117
118 #ifdef CONFIG_IXGBE_DCA
119 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
120 void *p);
121 static struct notifier_block dca_notifier = {
122 .notifier_call = ixgbe_notify_dca,
123 .next = NULL,
124 .priority = 0
125 };
126 #endif
127
128 #ifdef CONFIG_PCI_IOV
129 static unsigned int max_vfs;
130 module_param(max_vfs, uint, 0);
131 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
132 "per physical function");
133 #endif /* CONFIG_PCI_IOV */
134
135 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
136 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
137 MODULE_LICENSE("GPL");
138 MODULE_VERSION(DRV_VERSION);
139
140 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
141
142 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
143 {
144 struct ixgbe_hw *hw = &adapter->hw;
145 u32 gcr;
146 u32 gpie;
147 u32 vmdctl;
148
149 #ifdef CONFIG_PCI_IOV
150 /* disable iov and allow time for transactions to clear */
151 pci_disable_sriov(adapter->pdev);
152 #endif
153
154 /* turn off device IOV mode */
155 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
156 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
157 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
158 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
159 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
160 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
161
162 /* set default pool back to 0 */
163 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
164 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
165 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
166
167 /* take a breather then clean up driver data */
168 msleep(100);
169 if (adapter->vfinfo)
170 kfree(adapter->vfinfo);
171 adapter->vfinfo = NULL;
172
173 adapter->num_vfs = 0;
174 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
175 }
176
177 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
178 {
179 u32 ctrl_ext;
180
181 /* Let firmware take over control of h/w */
182 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
183 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
184 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
185 }
186
187 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
188 {
189 u32 ctrl_ext;
190
191 /* Let firmware know the driver has taken over */
192 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
193 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
194 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
195 }
196
197 /*
198 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
199 * @adapter: pointer to adapter struct
200 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
201 * @queue: queue to map the corresponding interrupt to
202 * @msix_vector: the vector to map to the corresponding queue
203 *
204 */
205 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
206 u8 queue, u8 msix_vector)
207 {
208 u32 ivar, index;
209 struct ixgbe_hw *hw = &adapter->hw;
210 switch (hw->mac.type) {
211 case ixgbe_mac_82598EB:
212 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
213 if (direction == -1)
214 direction = 0;
215 index = (((direction * 64) + queue) >> 2) & 0x1F;
216 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
217 ivar &= ~(0xFF << (8 * (queue & 0x3)));
218 ivar |= (msix_vector << (8 * (queue & 0x3)));
219 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
220 break;
221 case ixgbe_mac_82599EB:
222 if (direction == -1) {
223 /* other causes */
224 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
225 index = ((queue & 1) * 8);
226 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
227 ivar &= ~(0xFF << index);
228 ivar |= (msix_vector << index);
229 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
230 break;
231 } else {
232 /* tx or rx causes */
233 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
234 index = ((16 * (queue & 1)) + (8 * direction));
235 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
236 ivar &= ~(0xFF << index);
237 ivar |= (msix_vector << index);
238 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
239 break;
240 }
241 default:
242 break;
243 }
244 }
245
246 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
247 u64 qmask)
248 {
249 u32 mask;
250
251 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
252 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
253 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
254 } else {
255 mask = (qmask & 0xFFFFFFFF);
256 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
257 mask = (qmask >> 32);
258 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
259 }
260 }
261
262 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
263 struct ixgbe_tx_buffer
264 *tx_buffer_info)
265 {
266 if (tx_buffer_info->dma) {
267 if (tx_buffer_info->mapped_as_page)
268 pci_unmap_page(adapter->pdev,
269 tx_buffer_info->dma,
270 tx_buffer_info->length,
271 PCI_DMA_TODEVICE);
272 else
273 pci_unmap_single(adapter->pdev,
274 tx_buffer_info->dma,
275 tx_buffer_info->length,
276 PCI_DMA_TODEVICE);
277 tx_buffer_info->dma = 0;
278 }
279 if (tx_buffer_info->skb) {
280 dev_kfree_skb_any(tx_buffer_info->skb);
281 tx_buffer_info->skb = NULL;
282 }
283 tx_buffer_info->time_stamp = 0;
284 /* tx_buffer_info must be completely set up in the transmit path */
285 }
286
287 /**
288 * ixgbe_tx_is_paused - check if the tx ring is paused
289 * @adapter: the ixgbe adapter
290 * @tx_ring: the corresponding tx_ring
291 *
292 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
293 * corresponding TC of this tx_ring when checking TFCS.
294 *
295 * Returns : true if paused
296 */
297 static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter,
298 struct ixgbe_ring *tx_ring)
299 {
300 u32 txoff = IXGBE_TFCS_TXOFF;
301
302 #ifdef CONFIG_IXGBE_DCB
303 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
304 int tc;
305 int reg_idx = tx_ring->reg_idx;
306 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
307
308 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
309 tc = reg_idx >> 2;
310 txoff = IXGBE_TFCS_TXOFF0;
311 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
312 tc = 0;
313 txoff = IXGBE_TFCS_TXOFF;
314 if (dcb_i == 8) {
315 /* TC0, TC1 */
316 tc = reg_idx >> 5;
317 if (tc == 2) /* TC2, TC3 */
318 tc += (reg_idx - 64) >> 4;
319 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
320 tc += 1 + ((reg_idx - 96) >> 3);
321 } else if (dcb_i == 4) {
322 /* TC0, TC1 */
323 tc = reg_idx >> 6;
324 if (tc == 1) {
325 tc += (reg_idx - 64) >> 5;
326 if (tc == 2) /* TC2, TC3 */
327 tc += (reg_idx - 96) >> 4;
328 }
329 }
330 }
331 txoff <<= tc;
332 }
333 #endif
334 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
335 }
336
337 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
338 struct ixgbe_ring *tx_ring,
339 unsigned int eop)
340 {
341 struct ixgbe_hw *hw = &adapter->hw;
342
343 /* Detect a transmit hang in hardware, this serializes the
344 * check with the clearing of time_stamp and movement of eop */
345 adapter->detect_tx_hung = false;
346 if (tx_ring->tx_buffer_info[eop].time_stamp &&
347 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
348 !ixgbe_tx_is_paused(adapter, tx_ring)) {
349 /* detected Tx unit hang */
350 union ixgbe_adv_tx_desc *tx_desc;
351 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
352 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
353 " Tx Queue <%d>\n"
354 " TDH, TDT <%x>, <%x>\n"
355 " next_to_use <%x>\n"
356 " next_to_clean <%x>\n"
357 "tx_buffer_info[next_to_clean]\n"
358 " time_stamp <%lx>\n"
359 " jiffies <%lx>\n",
360 tx_ring->queue_index,
361 IXGBE_READ_REG(hw, tx_ring->head),
362 IXGBE_READ_REG(hw, tx_ring->tail),
363 tx_ring->next_to_use, eop,
364 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
365 return true;
366 }
367
368 return false;
369 }
370
371 #define IXGBE_MAX_TXD_PWR 14
372 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
373
374 /* Tx Descriptors needed, worst case */
375 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
376 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
377 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
378 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
379
380 static void ixgbe_tx_timeout(struct net_device *netdev);
381
382 /**
383 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
384 * @q_vector: structure containing interrupt and ring information
385 * @tx_ring: tx ring to clean
386 **/
387 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
388 struct ixgbe_ring *tx_ring)
389 {
390 struct ixgbe_adapter *adapter = q_vector->adapter;
391 struct net_device *netdev = adapter->netdev;
392 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
393 struct ixgbe_tx_buffer *tx_buffer_info;
394 unsigned int i, eop, count = 0;
395 unsigned int total_bytes = 0, total_packets = 0;
396
397 i = tx_ring->next_to_clean;
398 eop = tx_ring->tx_buffer_info[i].next_to_watch;
399 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
400
401 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
402 (count < tx_ring->work_limit)) {
403 bool cleaned = false;
404 for ( ; !cleaned; count++) {
405 struct sk_buff *skb;
406 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
407 tx_buffer_info = &tx_ring->tx_buffer_info[i];
408 cleaned = (i == eop);
409 skb = tx_buffer_info->skb;
410
411 if (cleaned && skb) {
412 unsigned int segs, bytecount;
413 unsigned int hlen = skb_headlen(skb);
414
415 /* gso_segs is currently only valid for tcp */
416 segs = skb_shinfo(skb)->gso_segs ?: 1;
417 #ifdef IXGBE_FCOE
418 /* adjust for FCoE Sequence Offload */
419 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
420 && (skb->protocol == htons(ETH_P_FCOE)) &&
421 skb_is_gso(skb)) {
422 hlen = skb_transport_offset(skb) +
423 sizeof(struct fc_frame_header) +
424 sizeof(struct fcoe_crc_eof);
425 segs = DIV_ROUND_UP(skb->len - hlen,
426 skb_shinfo(skb)->gso_size);
427 }
428 #endif /* IXGBE_FCOE */
429 /* multiply data chunks by size of headers */
430 bytecount = ((segs - 1) * hlen) + skb->len;
431 total_packets += segs;
432 total_bytes += bytecount;
433 }
434
435 ixgbe_unmap_and_free_tx_resource(adapter,
436 tx_buffer_info);
437
438 tx_desc->wb.status = 0;
439
440 i++;
441 if (i == tx_ring->count)
442 i = 0;
443 }
444
445 eop = tx_ring->tx_buffer_info[i].next_to_watch;
446 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
447 }
448
449 tx_ring->next_to_clean = i;
450
451 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
452 if (unlikely(count && netif_carrier_ok(netdev) &&
453 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
454 /* Make sure that anybody stopping the queue after this
455 * sees the new next_to_clean.
456 */
457 smp_mb();
458 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
459 !test_bit(__IXGBE_DOWN, &adapter->state)) {
460 netif_wake_subqueue(netdev, tx_ring->queue_index);
461 ++tx_ring->restart_queue;
462 }
463 }
464
465 if (adapter->detect_tx_hung) {
466 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
467 /* schedule immediate reset if we believe we hung */
468 DPRINTK(PROBE, INFO,
469 "tx hang %d detected, resetting adapter\n",
470 adapter->tx_timeout_count + 1);
471 ixgbe_tx_timeout(adapter->netdev);
472 }
473 }
474
475 /* re-arm the interrupt */
476 if (count >= tx_ring->work_limit)
477 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
478
479 tx_ring->total_bytes += total_bytes;
480 tx_ring->total_packets += total_packets;
481 tx_ring->stats.packets += total_packets;
482 tx_ring->stats.bytes += total_bytes;
483 return (count < tx_ring->work_limit);
484 }
485
486 #ifdef CONFIG_IXGBE_DCA
487 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
488 struct ixgbe_ring *rx_ring)
489 {
490 u32 rxctrl;
491 int cpu = get_cpu();
492 int q = rx_ring - adapter->rx_ring;
493
494 if (rx_ring->cpu != cpu) {
495 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
496 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
497 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
498 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
499 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
500 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
501 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
502 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
503 }
504 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
505 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
506 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
507 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
508 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
509 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
510 rx_ring->cpu = cpu;
511 }
512 put_cpu();
513 }
514
515 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
516 struct ixgbe_ring *tx_ring)
517 {
518 u32 txctrl;
519 int cpu = get_cpu();
520 int q = tx_ring - adapter->tx_ring;
521 struct ixgbe_hw *hw = &adapter->hw;
522
523 if (tx_ring->cpu != cpu) {
524 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
525 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
526 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
527 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
528 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
529 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
530 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
531 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
532 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
533 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
534 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
535 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
536 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
537 }
538 tx_ring->cpu = cpu;
539 }
540 put_cpu();
541 }
542
543 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
544 {
545 int i;
546
547 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
548 return;
549
550 /* always use CB2 mode, difference is masked in the CB driver */
551 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
552
553 for (i = 0; i < adapter->num_tx_queues; i++) {
554 adapter->tx_ring[i].cpu = -1;
555 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
556 }
557 for (i = 0; i < adapter->num_rx_queues; i++) {
558 adapter->rx_ring[i].cpu = -1;
559 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
560 }
561 }
562
563 static int __ixgbe_notify_dca(struct device *dev, void *data)
564 {
565 struct net_device *netdev = dev_get_drvdata(dev);
566 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567 unsigned long event = *(unsigned long *)data;
568
569 switch (event) {
570 case DCA_PROVIDER_ADD:
571 /* if we're already enabled, don't do it again */
572 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
573 break;
574 if (dca_add_requester(dev) == 0) {
575 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
576 ixgbe_setup_dca(adapter);
577 break;
578 }
579 /* Fall Through since DCA is disabled. */
580 case DCA_PROVIDER_REMOVE:
581 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
582 dca_remove_requester(dev);
583 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
584 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
585 }
586 break;
587 }
588
589 return 0;
590 }
591
592 #endif /* CONFIG_IXGBE_DCA */
593 /**
594 * ixgbe_receive_skb - Send a completed packet up the stack
595 * @adapter: board private structure
596 * @skb: packet to send up
597 * @status: hardware indication of status of receive
598 * @rx_ring: rx descriptor ring (for a specific queue) to setup
599 * @rx_desc: rx descriptor
600 **/
601 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
602 struct sk_buff *skb, u8 status,
603 struct ixgbe_ring *ring,
604 union ixgbe_adv_rx_desc *rx_desc)
605 {
606 struct ixgbe_adapter *adapter = q_vector->adapter;
607 struct napi_struct *napi = &q_vector->napi;
608 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
609 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
610
611 skb_record_rx_queue(skb, ring->queue_index);
612 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
613 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
614 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
615 else
616 napi_gro_receive(napi, skb);
617 } else {
618 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
619 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
620 else
621 netif_rx(skb);
622 }
623 }
624
625 /**
626 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
627 * @adapter: address of board private structure
628 * @status_err: hardware indication of status of receive
629 * @skb: skb currently being received and modified
630 **/
631 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
632 union ixgbe_adv_rx_desc *rx_desc,
633 struct sk_buff *skb)
634 {
635 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
636
637 skb->ip_summed = CHECKSUM_NONE;
638
639 /* Rx csum disabled */
640 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
641 return;
642
643 /* if IP and error */
644 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
645 (status_err & IXGBE_RXDADV_ERR_IPE)) {
646 adapter->hw_csum_rx_error++;
647 return;
648 }
649
650 if (!(status_err & IXGBE_RXD_STAT_L4CS))
651 return;
652
653 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
654 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
655
656 /*
657 * 82599 errata, UDP frames with a 0 checksum can be marked as
658 * checksum errors.
659 */
660 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
661 (adapter->hw.mac.type == ixgbe_mac_82599EB))
662 return;
663
664 adapter->hw_csum_rx_error++;
665 return;
666 }
667
668 /* It must be a TCP or UDP packet with a valid checksum */
669 skb->ip_summed = CHECKSUM_UNNECESSARY;
670 }
671
672 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
673 struct ixgbe_ring *rx_ring, u32 val)
674 {
675 /*
676 * Force memory writes to complete before letting h/w
677 * know there are new descriptors to fetch. (Only
678 * applicable for weak-ordered memory model archs,
679 * such as IA-64).
680 */
681 wmb();
682 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
683 }
684
685 /**
686 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
687 * @adapter: address of board private structure
688 **/
689 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
690 struct ixgbe_ring *rx_ring,
691 int cleaned_count)
692 {
693 struct pci_dev *pdev = adapter->pdev;
694 union ixgbe_adv_rx_desc *rx_desc;
695 struct ixgbe_rx_buffer *bi;
696 unsigned int i;
697
698 i = rx_ring->next_to_use;
699 bi = &rx_ring->rx_buffer_info[i];
700
701 while (cleaned_count--) {
702 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
703
704 if (!bi->page_dma &&
705 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
706 if (!bi->page) {
707 bi->page = alloc_page(GFP_ATOMIC);
708 if (!bi->page) {
709 adapter->alloc_rx_page_failed++;
710 goto no_buffers;
711 }
712 bi->page_offset = 0;
713 } else {
714 /* use a half page if we're re-using */
715 bi->page_offset ^= (PAGE_SIZE / 2);
716 }
717
718 bi->page_dma = pci_map_page(pdev, bi->page,
719 bi->page_offset,
720 (PAGE_SIZE / 2),
721 PCI_DMA_FROMDEVICE);
722 }
723
724 if (!bi->skb) {
725 struct sk_buff *skb;
726 /* netdev_alloc_skb reserves 32 bytes up front!! */
727 uint bufsz = rx_ring->rx_buf_len + SMP_CACHE_BYTES;
728 skb = netdev_alloc_skb(adapter->netdev, bufsz);
729
730 if (!skb) {
731 adapter->alloc_rx_buff_failed++;
732 goto no_buffers;
733 }
734
735 /* advance the data pointer to the next cache line */
736 skb_reserve(skb, (PTR_ALIGN(skb->data, SMP_CACHE_BYTES)
737 - skb->data));
738
739 bi->skb = skb;
740 bi->dma = pci_map_single(pdev, skb->data,
741 rx_ring->rx_buf_len,
742 PCI_DMA_FROMDEVICE);
743 }
744 /* Refresh the desc even if buffer_addrs didn't change because
745 * each write-back erases this info. */
746 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
747 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
748 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
749 } else {
750 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
751 }
752
753 i++;
754 if (i == rx_ring->count)
755 i = 0;
756 bi = &rx_ring->rx_buffer_info[i];
757 }
758
759 no_buffers:
760 if (rx_ring->next_to_use != i) {
761 rx_ring->next_to_use = i;
762 if (i-- == 0)
763 i = (rx_ring->count - 1);
764
765 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
766 }
767 }
768
769 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
770 {
771 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
772 }
773
774 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
775 {
776 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
777 }
778
779 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
780 {
781 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
782 IXGBE_RXDADV_RSCCNT_MASK) >>
783 IXGBE_RXDADV_RSCCNT_SHIFT;
784 }
785
786 /**
787 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
788 * @skb: pointer to the last skb in the rsc queue
789 * @count: pointer to number of packets coalesced in this context
790 *
791 * This function changes a queue full of hw rsc buffers into a completed
792 * packet. It uses the ->prev pointers to find the first packet and then
793 * turns it into the frag list owner.
794 **/
795 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
796 u64 *count)
797 {
798 unsigned int frag_list_size = 0;
799
800 while (skb->prev) {
801 struct sk_buff *prev = skb->prev;
802 frag_list_size += skb->len;
803 skb->prev = NULL;
804 skb = prev;
805 *count += 1;
806 }
807
808 skb_shinfo(skb)->frag_list = skb->next;
809 skb->next = NULL;
810 skb->len += frag_list_size;
811 skb->data_len += frag_list_size;
812 skb->truesize += frag_list_size;
813 return skb;
814 }
815
816 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
817 struct ixgbe_ring *rx_ring,
818 int *work_done, int work_to_do)
819 {
820 struct ixgbe_adapter *adapter = q_vector->adapter;
821 struct net_device *netdev = adapter->netdev;
822 struct pci_dev *pdev = adapter->pdev;
823 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
824 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
825 struct sk_buff *skb;
826 unsigned int i, rsc_count = 0;
827 u32 len, staterr;
828 u16 hdr_info;
829 bool cleaned = false;
830 int cleaned_count = 0;
831 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
832 #ifdef IXGBE_FCOE
833 int ddp_bytes = 0;
834 #endif /* IXGBE_FCOE */
835
836 i = rx_ring->next_to_clean;
837 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
838 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
839 rx_buffer_info = &rx_ring->rx_buffer_info[i];
840
841 while (staterr & IXGBE_RXD_STAT_DD) {
842 u32 upper_len = 0;
843 if (*work_done >= work_to_do)
844 break;
845 (*work_done)++;
846
847 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
848 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
849 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
850 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
851 if (len > IXGBE_RX_HDR_SIZE)
852 len = IXGBE_RX_HDR_SIZE;
853 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
854 } else {
855 len = le16_to_cpu(rx_desc->wb.upper.length);
856 }
857
858 cleaned = true;
859 skb = rx_buffer_info->skb;
860 prefetch(skb->data);
861 rx_buffer_info->skb = NULL;
862
863 if (rx_buffer_info->dma) {
864 pci_unmap_single(pdev, rx_buffer_info->dma,
865 rx_ring->rx_buf_len,
866 PCI_DMA_FROMDEVICE);
867 rx_buffer_info->dma = 0;
868 skb_put(skb, len);
869 }
870
871 if (upper_len) {
872 pci_unmap_page(pdev, rx_buffer_info->page_dma,
873 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
874 rx_buffer_info->page_dma = 0;
875 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
876 rx_buffer_info->page,
877 rx_buffer_info->page_offset,
878 upper_len);
879
880 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
881 (page_count(rx_buffer_info->page) != 1))
882 rx_buffer_info->page = NULL;
883 else
884 get_page(rx_buffer_info->page);
885
886 skb->len += upper_len;
887 skb->data_len += upper_len;
888 skb->truesize += upper_len;
889 }
890
891 i++;
892 if (i == rx_ring->count)
893 i = 0;
894
895 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
896 prefetch(next_rxd);
897 cleaned_count++;
898
899 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
900 rsc_count = ixgbe_get_rsc_count(rx_desc);
901
902 if (rsc_count) {
903 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
904 IXGBE_RXDADV_NEXTP_SHIFT;
905 next_buffer = &rx_ring->rx_buffer_info[nextp];
906 } else {
907 next_buffer = &rx_ring->rx_buffer_info[i];
908 }
909
910 if (staterr & IXGBE_RXD_STAT_EOP) {
911 if (skb->prev)
912 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
913 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
914 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
915 rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
916 else
917 rx_ring->rsc_count++;
918 rx_ring->rsc_flush++;
919 }
920 rx_ring->stats.packets++;
921 rx_ring->stats.bytes += skb->len;
922 } else {
923 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
924 rx_buffer_info->skb = next_buffer->skb;
925 rx_buffer_info->dma = next_buffer->dma;
926 next_buffer->skb = skb;
927 next_buffer->dma = 0;
928 } else {
929 skb->next = next_buffer->skb;
930 skb->next->prev = skb;
931 }
932 rx_ring->non_eop_descs++;
933 goto next_desc;
934 }
935
936 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
937 dev_kfree_skb_irq(skb);
938 goto next_desc;
939 }
940
941 ixgbe_rx_checksum(adapter, rx_desc, skb);
942
943 /* probably a little skewed due to removing CRC */
944 total_rx_bytes += skb->len;
945 total_rx_packets++;
946
947 skb->protocol = eth_type_trans(skb, adapter->netdev);
948 #ifdef IXGBE_FCOE
949 /* if ddp, not passing to ULD unless for FCP_RSP or error */
950 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
951 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
952 if (!ddp_bytes)
953 goto next_desc;
954 }
955 #endif /* IXGBE_FCOE */
956 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
957
958 next_desc:
959 rx_desc->wb.upper.status_error = 0;
960
961 /* return some buffers to hardware, one at a time is too slow */
962 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
963 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
964 cleaned_count = 0;
965 }
966
967 /* use prefetched values */
968 rx_desc = next_rxd;
969 rx_buffer_info = &rx_ring->rx_buffer_info[i];
970
971 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
972 }
973
974 rx_ring->next_to_clean = i;
975 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
976
977 if (cleaned_count)
978 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
979
980 #ifdef IXGBE_FCOE
981 /* include DDPed FCoE data */
982 if (ddp_bytes > 0) {
983 unsigned int mss;
984
985 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
986 sizeof(struct fc_frame_header) -
987 sizeof(struct fcoe_crc_eof);
988 if (mss > 512)
989 mss &= ~511;
990 total_rx_bytes += ddp_bytes;
991 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
992 }
993 #endif /* IXGBE_FCOE */
994
995 rx_ring->total_packets += total_rx_packets;
996 rx_ring->total_bytes += total_rx_bytes;
997 netdev->stats.rx_bytes += total_rx_bytes;
998 netdev->stats.rx_packets += total_rx_packets;
999
1000 return cleaned;
1001 }
1002
1003 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1004 /**
1005 * ixgbe_configure_msix - Configure MSI-X hardware
1006 * @adapter: board private structure
1007 *
1008 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1009 * interrupts.
1010 **/
1011 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1012 {
1013 struct ixgbe_q_vector *q_vector;
1014 int i, j, q_vectors, v_idx, r_idx;
1015 u32 mask;
1016
1017 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1018
1019 /*
1020 * Populate the IVAR table and set the ITR values to the
1021 * corresponding register.
1022 */
1023 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1024 q_vector = adapter->q_vector[v_idx];
1025 /* XXX for_each_bit(...) */
1026 r_idx = find_first_bit(q_vector->rxr_idx,
1027 adapter->num_rx_queues);
1028
1029 for (i = 0; i < q_vector->rxr_count; i++) {
1030 j = adapter->rx_ring[r_idx].reg_idx;
1031 ixgbe_set_ivar(adapter, 0, j, v_idx);
1032 r_idx = find_next_bit(q_vector->rxr_idx,
1033 adapter->num_rx_queues,
1034 r_idx + 1);
1035 }
1036 r_idx = find_first_bit(q_vector->txr_idx,
1037 adapter->num_tx_queues);
1038
1039 for (i = 0; i < q_vector->txr_count; i++) {
1040 j = adapter->tx_ring[r_idx].reg_idx;
1041 ixgbe_set_ivar(adapter, 1, j, v_idx);
1042 r_idx = find_next_bit(q_vector->txr_idx,
1043 adapter->num_tx_queues,
1044 r_idx + 1);
1045 }
1046
1047 if (q_vector->txr_count && !q_vector->rxr_count)
1048 /* tx only */
1049 q_vector->eitr = adapter->tx_eitr_param;
1050 else if (q_vector->rxr_count)
1051 /* rx or mixed */
1052 q_vector->eitr = adapter->rx_eitr_param;
1053
1054 ixgbe_write_eitr(q_vector);
1055 }
1056
1057 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1058 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1059 v_idx);
1060 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1061 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1062 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1063
1064 /* set up to autoclear timer, and the vectors */
1065 mask = IXGBE_EIMS_ENABLE_MASK;
1066 if (adapter->num_vfs)
1067 mask &= ~(IXGBE_EIMS_OTHER |
1068 IXGBE_EIMS_MAILBOX |
1069 IXGBE_EIMS_LSC);
1070 else
1071 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1072 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1073 }
1074
1075 enum latency_range {
1076 lowest_latency = 0,
1077 low_latency = 1,
1078 bulk_latency = 2,
1079 latency_invalid = 255
1080 };
1081
1082 /**
1083 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1084 * @adapter: pointer to adapter
1085 * @eitr: eitr setting (ints per sec) to give last timeslice
1086 * @itr_setting: current throttle rate in ints/second
1087 * @packets: the number of packets during this measurement interval
1088 * @bytes: the number of bytes during this measurement interval
1089 *
1090 * Stores a new ITR value based on packets and byte
1091 * counts during the last interrupt. The advantage of per interrupt
1092 * computation is faster updates and more accurate ITR for the current
1093 * traffic pattern. Constants in this function were computed
1094 * based on theoretical maximum wire speed and thresholds were set based
1095 * on testing data as well as attempting to minimize response time
1096 * while increasing bulk throughput.
1097 * this functionality is controlled by the InterruptThrottleRate module
1098 * parameter (see ixgbe_param.c)
1099 **/
1100 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1101 u32 eitr, u8 itr_setting,
1102 int packets, int bytes)
1103 {
1104 unsigned int retval = itr_setting;
1105 u32 timepassed_us;
1106 u64 bytes_perint;
1107
1108 if (packets == 0)
1109 goto update_itr_done;
1110
1111
1112 /* simple throttlerate management
1113 * 0-20MB/s lowest (100000 ints/s)
1114 * 20-100MB/s low (20000 ints/s)
1115 * 100-1249MB/s bulk (8000 ints/s)
1116 */
1117 /* what was last interrupt timeslice? */
1118 timepassed_us = 1000000/eitr;
1119 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1120
1121 switch (itr_setting) {
1122 case lowest_latency:
1123 if (bytes_perint > adapter->eitr_low)
1124 retval = low_latency;
1125 break;
1126 case low_latency:
1127 if (bytes_perint > adapter->eitr_high)
1128 retval = bulk_latency;
1129 else if (bytes_perint <= adapter->eitr_low)
1130 retval = lowest_latency;
1131 break;
1132 case bulk_latency:
1133 if (bytes_perint <= adapter->eitr_high)
1134 retval = low_latency;
1135 break;
1136 }
1137
1138 update_itr_done:
1139 return retval;
1140 }
1141
1142 /**
1143 * ixgbe_write_eitr - write EITR register in hardware specific way
1144 * @q_vector: structure containing interrupt and ring information
1145 *
1146 * This function is made to be called by ethtool and by the driver
1147 * when it needs to update EITR registers at runtime. Hardware
1148 * specific quirks/differences are taken care of here.
1149 */
1150 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1151 {
1152 struct ixgbe_adapter *adapter = q_vector->adapter;
1153 struct ixgbe_hw *hw = &adapter->hw;
1154 int v_idx = q_vector->v_idx;
1155 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1156
1157 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1158 /* must write high and low 16 bits to reset counter */
1159 itr_reg |= (itr_reg << 16);
1160 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1161 /*
1162 * set the WDIS bit to not clear the timer bits and cause an
1163 * immediate assertion of the interrupt
1164 */
1165 itr_reg |= IXGBE_EITR_CNT_WDIS;
1166 }
1167 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1168 }
1169
1170 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1171 {
1172 struct ixgbe_adapter *adapter = q_vector->adapter;
1173 u32 new_itr;
1174 u8 current_itr, ret_itr;
1175 int i, r_idx;
1176 struct ixgbe_ring *rx_ring, *tx_ring;
1177
1178 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1179 for (i = 0; i < q_vector->txr_count; i++) {
1180 tx_ring = &(adapter->tx_ring[r_idx]);
1181 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1182 q_vector->tx_itr,
1183 tx_ring->total_packets,
1184 tx_ring->total_bytes);
1185 /* if the result for this queue would decrease interrupt
1186 * rate for this vector then use that result */
1187 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1188 q_vector->tx_itr - 1 : ret_itr);
1189 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1190 r_idx + 1);
1191 }
1192
1193 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1194 for (i = 0; i < q_vector->rxr_count; i++) {
1195 rx_ring = &(adapter->rx_ring[r_idx]);
1196 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1197 q_vector->rx_itr,
1198 rx_ring->total_packets,
1199 rx_ring->total_bytes);
1200 /* if the result for this queue would decrease interrupt
1201 * rate for this vector then use that result */
1202 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1203 q_vector->rx_itr - 1 : ret_itr);
1204 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1205 r_idx + 1);
1206 }
1207
1208 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1209
1210 switch (current_itr) {
1211 /* counts and packets in update_itr are dependent on these numbers */
1212 case lowest_latency:
1213 new_itr = 100000;
1214 break;
1215 case low_latency:
1216 new_itr = 20000; /* aka hwitr = ~200 */
1217 break;
1218 case bulk_latency:
1219 default:
1220 new_itr = 8000;
1221 break;
1222 }
1223
1224 if (new_itr != q_vector->eitr) {
1225 /* do an exponential smoothing */
1226 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1227
1228 /* save the algorithm value here, not the smoothed one */
1229 q_vector->eitr = new_itr;
1230
1231 ixgbe_write_eitr(q_vector);
1232 }
1233
1234 return;
1235 }
1236
1237 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1238 {
1239 struct ixgbe_hw *hw = &adapter->hw;
1240
1241 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1242 (eicr & IXGBE_EICR_GPI_SDP1)) {
1243 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1244 /* write to clear the interrupt */
1245 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1246 }
1247 }
1248
1249 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1250 {
1251 struct ixgbe_hw *hw = &adapter->hw;
1252
1253 if (eicr & IXGBE_EICR_GPI_SDP1) {
1254 /* Clear the interrupt */
1255 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1256 schedule_work(&adapter->multispeed_fiber_task);
1257 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1258 /* Clear the interrupt */
1259 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1260 schedule_work(&adapter->sfp_config_module_task);
1261 } else {
1262 /* Interrupt isn't for us... */
1263 return;
1264 }
1265 }
1266
1267 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1268 {
1269 struct ixgbe_hw *hw = &adapter->hw;
1270
1271 adapter->lsc_int++;
1272 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1273 adapter->link_check_timeout = jiffies;
1274 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1275 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1276 IXGBE_WRITE_FLUSH(hw);
1277 schedule_work(&adapter->watchdog_task);
1278 }
1279 }
1280
1281 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1282 {
1283 struct net_device *netdev = data;
1284 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1285 struct ixgbe_hw *hw = &adapter->hw;
1286 u32 eicr;
1287
1288 /*
1289 * Workaround for Silicon errata. Use clear-by-write instead
1290 * of clear-by-read. Reading with EICS will return the
1291 * interrupt causes without clearing, which later be done
1292 * with the write to EICR.
1293 */
1294 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1295 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1296
1297 if (eicr & IXGBE_EICR_LSC)
1298 ixgbe_check_lsc(adapter);
1299
1300 if (eicr & IXGBE_EICR_MAILBOX)
1301 ixgbe_msg_task(adapter);
1302
1303 if (hw->mac.type == ixgbe_mac_82598EB)
1304 ixgbe_check_fan_failure(adapter, eicr);
1305
1306 if (hw->mac.type == ixgbe_mac_82599EB) {
1307 ixgbe_check_sfp_event(adapter, eicr);
1308
1309 /* Handle Flow Director Full threshold interrupt */
1310 if (eicr & IXGBE_EICR_FLOW_DIR) {
1311 int i;
1312 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1313 /* Disable transmits before FDIR Re-initialization */
1314 netif_tx_stop_all_queues(netdev);
1315 for (i = 0; i < adapter->num_tx_queues; i++) {
1316 struct ixgbe_ring *tx_ring =
1317 &adapter->tx_ring[i];
1318 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1319 &tx_ring->reinit_state))
1320 schedule_work(&adapter->fdir_reinit_task);
1321 }
1322 }
1323 }
1324 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1325 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1326
1327 return IRQ_HANDLED;
1328 }
1329
1330 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1331 u64 qmask)
1332 {
1333 u32 mask;
1334
1335 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1336 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1337 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1338 } else {
1339 mask = (qmask & 0xFFFFFFFF);
1340 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1341 mask = (qmask >> 32);
1342 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1343 }
1344 /* skip the flush */
1345 }
1346
1347 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1348 u64 qmask)
1349 {
1350 u32 mask;
1351
1352 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1353 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1354 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1355 } else {
1356 mask = (qmask & 0xFFFFFFFF);
1357 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1358 mask = (qmask >> 32);
1359 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1360 }
1361 /* skip the flush */
1362 }
1363
1364 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1365 {
1366 struct ixgbe_q_vector *q_vector = data;
1367 struct ixgbe_adapter *adapter = q_vector->adapter;
1368 struct ixgbe_ring *tx_ring;
1369 int i, r_idx;
1370
1371 if (!q_vector->txr_count)
1372 return IRQ_HANDLED;
1373
1374 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1375 for (i = 0; i < q_vector->txr_count; i++) {
1376 tx_ring = &(adapter->tx_ring[r_idx]);
1377 tx_ring->total_bytes = 0;
1378 tx_ring->total_packets = 0;
1379 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1380 r_idx + 1);
1381 }
1382
1383 /* EIAM disabled interrupts (on this vector) for us */
1384 napi_schedule(&q_vector->napi);
1385
1386 return IRQ_HANDLED;
1387 }
1388
1389 /**
1390 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1391 * @irq: unused
1392 * @data: pointer to our q_vector struct for this interrupt vector
1393 **/
1394 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1395 {
1396 struct ixgbe_q_vector *q_vector = data;
1397 struct ixgbe_adapter *adapter = q_vector->adapter;
1398 struct ixgbe_ring *rx_ring;
1399 int r_idx;
1400 int i;
1401
1402 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1403 for (i = 0; i < q_vector->rxr_count; i++) {
1404 rx_ring = &(adapter->rx_ring[r_idx]);
1405 rx_ring->total_bytes = 0;
1406 rx_ring->total_packets = 0;
1407 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1408 r_idx + 1);
1409 }
1410
1411 if (!q_vector->rxr_count)
1412 return IRQ_HANDLED;
1413
1414 /* disable interrupts on this vector only */
1415 /* EIAM disabled interrupts (on this vector) for us */
1416 napi_schedule(&q_vector->napi);
1417
1418 return IRQ_HANDLED;
1419 }
1420
1421 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1422 {
1423 struct ixgbe_q_vector *q_vector = data;
1424 struct ixgbe_adapter *adapter = q_vector->adapter;
1425 struct ixgbe_ring *ring;
1426 int r_idx;
1427 int i;
1428
1429 if (!q_vector->txr_count && !q_vector->rxr_count)
1430 return IRQ_HANDLED;
1431
1432 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1433 for (i = 0; i < q_vector->txr_count; i++) {
1434 ring = &(adapter->tx_ring[r_idx]);
1435 ring->total_bytes = 0;
1436 ring->total_packets = 0;
1437 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1438 r_idx + 1);
1439 }
1440
1441 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1442 for (i = 0; i < q_vector->rxr_count; i++) {
1443 ring = &(adapter->rx_ring[r_idx]);
1444 ring->total_bytes = 0;
1445 ring->total_packets = 0;
1446 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1447 r_idx + 1);
1448 }
1449
1450 /* EIAM disabled interrupts (on this vector) for us */
1451 napi_schedule(&q_vector->napi);
1452
1453 return IRQ_HANDLED;
1454 }
1455
1456 /**
1457 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1458 * @napi: napi struct with our devices info in it
1459 * @budget: amount of work driver is allowed to do this pass, in packets
1460 *
1461 * This function is optimized for cleaning one queue only on a single
1462 * q_vector!!!
1463 **/
1464 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1465 {
1466 struct ixgbe_q_vector *q_vector =
1467 container_of(napi, struct ixgbe_q_vector, napi);
1468 struct ixgbe_adapter *adapter = q_vector->adapter;
1469 struct ixgbe_ring *rx_ring = NULL;
1470 int work_done = 0;
1471 long r_idx;
1472
1473 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1474 rx_ring = &(adapter->rx_ring[r_idx]);
1475 #ifdef CONFIG_IXGBE_DCA
1476 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1477 ixgbe_update_rx_dca(adapter, rx_ring);
1478 #endif
1479
1480 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1481
1482 /* If all Rx work done, exit the polling mode */
1483 if (work_done < budget) {
1484 napi_complete(napi);
1485 if (adapter->rx_itr_setting & 1)
1486 ixgbe_set_itr_msix(q_vector);
1487 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1488 ixgbe_irq_enable_queues(adapter,
1489 ((u64)1 << q_vector->v_idx));
1490 }
1491
1492 return work_done;
1493 }
1494
1495 /**
1496 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1497 * @napi: napi struct with our devices info in it
1498 * @budget: amount of work driver is allowed to do this pass, in packets
1499 *
1500 * This function will clean more than one rx queue associated with a
1501 * q_vector.
1502 **/
1503 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1504 {
1505 struct ixgbe_q_vector *q_vector =
1506 container_of(napi, struct ixgbe_q_vector, napi);
1507 struct ixgbe_adapter *adapter = q_vector->adapter;
1508 struct ixgbe_ring *ring = NULL;
1509 int work_done = 0, i;
1510 long r_idx;
1511 bool tx_clean_complete = true;
1512
1513 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1514 for (i = 0; i < q_vector->txr_count; i++) {
1515 ring = &(adapter->tx_ring[r_idx]);
1516 #ifdef CONFIG_IXGBE_DCA
1517 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1518 ixgbe_update_tx_dca(adapter, ring);
1519 #endif
1520 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1521 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1522 r_idx + 1);
1523 }
1524
1525 /* attempt to distribute budget to each queue fairly, but don't allow
1526 * the budget to go below 1 because we'll exit polling */
1527 budget /= (q_vector->rxr_count ?: 1);
1528 budget = max(budget, 1);
1529 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1530 for (i = 0; i < q_vector->rxr_count; i++) {
1531 ring = &(adapter->rx_ring[r_idx]);
1532 #ifdef CONFIG_IXGBE_DCA
1533 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1534 ixgbe_update_rx_dca(adapter, ring);
1535 #endif
1536 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1537 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1538 r_idx + 1);
1539 }
1540
1541 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1542 ring = &(adapter->rx_ring[r_idx]);
1543 /* If all Rx work done, exit the polling mode */
1544 if (work_done < budget) {
1545 napi_complete(napi);
1546 if (adapter->rx_itr_setting & 1)
1547 ixgbe_set_itr_msix(q_vector);
1548 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1549 ixgbe_irq_enable_queues(adapter,
1550 ((u64)1 << q_vector->v_idx));
1551 return 0;
1552 }
1553
1554 return work_done;
1555 }
1556
1557 /**
1558 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1559 * @napi: napi struct with our devices info in it
1560 * @budget: amount of work driver is allowed to do this pass, in packets
1561 *
1562 * This function is optimized for cleaning one queue only on a single
1563 * q_vector!!!
1564 **/
1565 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1566 {
1567 struct ixgbe_q_vector *q_vector =
1568 container_of(napi, struct ixgbe_q_vector, napi);
1569 struct ixgbe_adapter *adapter = q_vector->adapter;
1570 struct ixgbe_ring *tx_ring = NULL;
1571 int work_done = 0;
1572 long r_idx;
1573
1574 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1575 tx_ring = &(adapter->tx_ring[r_idx]);
1576 #ifdef CONFIG_IXGBE_DCA
1577 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1578 ixgbe_update_tx_dca(adapter, tx_ring);
1579 #endif
1580
1581 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1582 work_done = budget;
1583
1584 /* If all Tx work done, exit the polling mode */
1585 if (work_done < budget) {
1586 napi_complete(napi);
1587 if (adapter->tx_itr_setting & 1)
1588 ixgbe_set_itr_msix(q_vector);
1589 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1590 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1591 }
1592
1593 return work_done;
1594 }
1595
1596 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1597 int r_idx)
1598 {
1599 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1600
1601 set_bit(r_idx, q_vector->rxr_idx);
1602 q_vector->rxr_count++;
1603 }
1604
1605 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1606 int t_idx)
1607 {
1608 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1609
1610 set_bit(t_idx, q_vector->txr_idx);
1611 q_vector->txr_count++;
1612 }
1613
1614 /**
1615 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1616 * @adapter: board private structure to initialize
1617 * @vectors: allotted vector count for descriptor rings
1618 *
1619 * This function maps descriptor rings to the queue-specific vectors
1620 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1621 * one vector per ring/queue, but on a constrained vector budget, we
1622 * group the rings as "efficiently" as possible. You would add new
1623 * mapping configurations in here.
1624 **/
1625 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1626 int vectors)
1627 {
1628 int v_start = 0;
1629 int rxr_idx = 0, txr_idx = 0;
1630 int rxr_remaining = adapter->num_rx_queues;
1631 int txr_remaining = adapter->num_tx_queues;
1632 int i, j;
1633 int rqpv, tqpv;
1634 int err = 0;
1635
1636 /* No mapping required if MSI-X is disabled. */
1637 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1638 goto out;
1639
1640 /*
1641 * The ideal configuration...
1642 * We have enough vectors to map one per queue.
1643 */
1644 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1645 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1646 map_vector_to_rxq(adapter, v_start, rxr_idx);
1647
1648 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1649 map_vector_to_txq(adapter, v_start, txr_idx);
1650
1651 goto out;
1652 }
1653
1654 /*
1655 * If we don't have enough vectors for a 1-to-1
1656 * mapping, we'll have to group them so there are
1657 * multiple queues per vector.
1658 */
1659 /* Re-adjusting *qpv takes care of the remainder. */
1660 for (i = v_start; i < vectors; i++) {
1661 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1662 for (j = 0; j < rqpv; j++) {
1663 map_vector_to_rxq(adapter, i, rxr_idx);
1664 rxr_idx++;
1665 rxr_remaining--;
1666 }
1667 }
1668 for (i = v_start; i < vectors; i++) {
1669 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1670 for (j = 0; j < tqpv; j++) {
1671 map_vector_to_txq(adapter, i, txr_idx);
1672 txr_idx++;
1673 txr_remaining--;
1674 }
1675 }
1676
1677 out:
1678 return err;
1679 }
1680
1681 /**
1682 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1683 * @adapter: board private structure
1684 *
1685 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1686 * interrupts from the kernel.
1687 **/
1688 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1689 {
1690 struct net_device *netdev = adapter->netdev;
1691 irqreturn_t (*handler)(int, void *);
1692 int i, vector, q_vectors, err;
1693 int ri=0, ti=0;
1694
1695 /* Decrement for Other and TCP Timer vectors */
1696 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1697
1698 /* Map the Tx/Rx rings to the vectors we were allotted. */
1699 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1700 if (err)
1701 goto out;
1702
1703 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1704 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1705 &ixgbe_msix_clean_many)
1706 for (vector = 0; vector < q_vectors; vector++) {
1707 handler = SET_HANDLER(adapter->q_vector[vector]);
1708
1709 if(handler == &ixgbe_msix_clean_rx) {
1710 sprintf(adapter->name[vector], "%s-%s-%d",
1711 netdev->name, "rx", ri++);
1712 }
1713 else if(handler == &ixgbe_msix_clean_tx) {
1714 sprintf(adapter->name[vector], "%s-%s-%d",
1715 netdev->name, "tx", ti++);
1716 }
1717 else
1718 sprintf(adapter->name[vector], "%s-%s-%d",
1719 netdev->name, "TxRx", vector);
1720
1721 err = request_irq(adapter->msix_entries[vector].vector,
1722 handler, 0, adapter->name[vector],
1723 adapter->q_vector[vector]);
1724 if (err) {
1725 DPRINTK(PROBE, ERR,
1726 "request_irq failed for MSIX interrupt "
1727 "Error: %d\n", err);
1728 goto free_queue_irqs;
1729 }
1730 }
1731
1732 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1733 err = request_irq(adapter->msix_entries[vector].vector,
1734 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1735 if (err) {
1736 DPRINTK(PROBE, ERR,
1737 "request_irq for msix_lsc failed: %d\n", err);
1738 goto free_queue_irqs;
1739 }
1740
1741 return 0;
1742
1743 free_queue_irqs:
1744 for (i = vector - 1; i >= 0; i--)
1745 free_irq(adapter->msix_entries[--vector].vector,
1746 adapter->q_vector[i]);
1747 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1748 pci_disable_msix(adapter->pdev);
1749 kfree(adapter->msix_entries);
1750 adapter->msix_entries = NULL;
1751 out:
1752 return err;
1753 }
1754
1755 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1756 {
1757 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1758 u8 current_itr;
1759 u32 new_itr = q_vector->eitr;
1760 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1761 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1762
1763 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1764 q_vector->tx_itr,
1765 tx_ring->total_packets,
1766 tx_ring->total_bytes);
1767 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1768 q_vector->rx_itr,
1769 rx_ring->total_packets,
1770 rx_ring->total_bytes);
1771
1772 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1773
1774 switch (current_itr) {
1775 /* counts and packets in update_itr are dependent on these numbers */
1776 case lowest_latency:
1777 new_itr = 100000;
1778 break;
1779 case low_latency:
1780 new_itr = 20000; /* aka hwitr = ~200 */
1781 break;
1782 case bulk_latency:
1783 new_itr = 8000;
1784 break;
1785 default:
1786 break;
1787 }
1788
1789 if (new_itr != q_vector->eitr) {
1790 /* do an exponential smoothing */
1791 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1792
1793 /* save the algorithm value here, not the smoothed one */
1794 q_vector->eitr = new_itr;
1795
1796 ixgbe_write_eitr(q_vector);
1797 }
1798
1799 return;
1800 }
1801
1802 /**
1803 * ixgbe_irq_enable - Enable default interrupt generation settings
1804 * @adapter: board private structure
1805 **/
1806 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1807 {
1808 u32 mask;
1809
1810 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1811 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1812 mask |= IXGBE_EIMS_GPI_SDP1;
1813 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1814 mask |= IXGBE_EIMS_ECC;
1815 mask |= IXGBE_EIMS_GPI_SDP1;
1816 mask |= IXGBE_EIMS_GPI_SDP2;
1817 if (adapter->num_vfs)
1818 mask |= IXGBE_EIMS_MAILBOX;
1819 }
1820 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1821 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1822 mask |= IXGBE_EIMS_FLOW_DIR;
1823
1824 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1825 ixgbe_irq_enable_queues(adapter, ~0);
1826 IXGBE_WRITE_FLUSH(&adapter->hw);
1827
1828 if (adapter->num_vfs > 32) {
1829 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1830 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1831 }
1832 }
1833
1834 /**
1835 * ixgbe_intr - legacy mode Interrupt Handler
1836 * @irq: interrupt number
1837 * @data: pointer to a network interface device structure
1838 **/
1839 static irqreturn_t ixgbe_intr(int irq, void *data)
1840 {
1841 struct net_device *netdev = data;
1842 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1843 struct ixgbe_hw *hw = &adapter->hw;
1844 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1845 u32 eicr;
1846
1847 /*
1848 * Workaround for silicon errata. Mask the interrupts
1849 * before the read of EICR.
1850 */
1851 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1852
1853 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1854 * therefore no explict interrupt disable is necessary */
1855 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1856 if (!eicr) {
1857 /* shared interrupt alert!
1858 * make sure interrupts are enabled because the read will
1859 * have disabled interrupts due to EIAM */
1860 ixgbe_irq_enable(adapter);
1861 return IRQ_NONE; /* Not our interrupt */
1862 }
1863
1864 if (eicr & IXGBE_EICR_LSC)
1865 ixgbe_check_lsc(adapter);
1866
1867 if (hw->mac.type == ixgbe_mac_82599EB)
1868 ixgbe_check_sfp_event(adapter, eicr);
1869
1870 ixgbe_check_fan_failure(adapter, eicr);
1871
1872 if (napi_schedule_prep(&(q_vector->napi))) {
1873 adapter->tx_ring[0].total_packets = 0;
1874 adapter->tx_ring[0].total_bytes = 0;
1875 adapter->rx_ring[0].total_packets = 0;
1876 adapter->rx_ring[0].total_bytes = 0;
1877 /* would disable interrupts here but EIAM disabled it */
1878 __napi_schedule(&(q_vector->napi));
1879 }
1880
1881 return IRQ_HANDLED;
1882 }
1883
1884 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1885 {
1886 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1887
1888 for (i = 0; i < q_vectors; i++) {
1889 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1890 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1891 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1892 q_vector->rxr_count = 0;
1893 q_vector->txr_count = 0;
1894 }
1895 }
1896
1897 /**
1898 * ixgbe_request_irq - initialize interrupts
1899 * @adapter: board private structure
1900 *
1901 * Attempts to configure interrupts using the best available
1902 * capabilities of the hardware and kernel.
1903 **/
1904 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1905 {
1906 struct net_device *netdev = adapter->netdev;
1907 int err;
1908
1909 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1910 err = ixgbe_request_msix_irqs(adapter);
1911 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1912 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
1913 netdev->name, netdev);
1914 } else {
1915 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
1916 netdev->name, netdev);
1917 }
1918
1919 if (err)
1920 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1921
1922 return err;
1923 }
1924
1925 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1926 {
1927 struct net_device *netdev = adapter->netdev;
1928
1929 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1930 int i, q_vectors;
1931
1932 q_vectors = adapter->num_msix_vectors;
1933
1934 i = q_vectors - 1;
1935 free_irq(adapter->msix_entries[i].vector, netdev);
1936
1937 i--;
1938 for (; i >= 0; i--) {
1939 free_irq(adapter->msix_entries[i].vector,
1940 adapter->q_vector[i]);
1941 }
1942
1943 ixgbe_reset_q_vectors(adapter);
1944 } else {
1945 free_irq(adapter->pdev->irq, netdev);
1946 }
1947 }
1948
1949 /**
1950 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1951 * @adapter: board private structure
1952 **/
1953 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1954 {
1955 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1956 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1957 } else {
1958 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1959 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1960 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1961 if (adapter->num_vfs > 32)
1962 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
1963 }
1964 IXGBE_WRITE_FLUSH(&adapter->hw);
1965 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1966 int i;
1967 for (i = 0; i < adapter->num_msix_vectors; i++)
1968 synchronize_irq(adapter->msix_entries[i].vector);
1969 } else {
1970 synchronize_irq(adapter->pdev->irq);
1971 }
1972 }
1973
1974 /**
1975 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1976 *
1977 **/
1978 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1979 {
1980 struct ixgbe_hw *hw = &adapter->hw;
1981
1982 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1983 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
1984
1985 ixgbe_set_ivar(adapter, 0, 0, 0);
1986 ixgbe_set_ivar(adapter, 1, 0, 0);
1987
1988 map_vector_to_rxq(adapter, 0, 0);
1989 map_vector_to_txq(adapter, 0, 0);
1990
1991 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1992 }
1993
1994 /**
1995 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1996 * @adapter: board private structure
1997 *
1998 * Configure the Tx unit of the MAC after a reset.
1999 **/
2000 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2001 {
2002 u64 tdba;
2003 struct ixgbe_hw *hw = &adapter->hw;
2004 u32 i, j, tdlen, txctrl;
2005
2006 /* Setup the HW Tx Head and Tail descriptor pointers */
2007 for (i = 0; i < adapter->num_tx_queues; i++) {
2008 struct ixgbe_ring *ring = &adapter->tx_ring[i];
2009 j = ring->reg_idx;
2010 tdba = ring->dma;
2011 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
2012 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
2013 (tdba & DMA_BIT_MASK(32)));
2014 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
2015 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
2016 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
2017 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
2018 adapter->tx_ring[i].head = IXGBE_TDH(j);
2019 adapter->tx_ring[i].tail = IXGBE_TDT(j);
2020 /*
2021 * Disable Tx Head Writeback RO bit, since this hoses
2022 * bookkeeping if things aren't delivered in order.
2023 */
2024 switch (hw->mac.type) {
2025 case ixgbe_mac_82598EB:
2026 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
2027 break;
2028 case ixgbe_mac_82599EB:
2029 default:
2030 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
2031 break;
2032 }
2033 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
2034 switch (hw->mac.type) {
2035 case ixgbe_mac_82598EB:
2036 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
2037 break;
2038 case ixgbe_mac_82599EB:
2039 default:
2040 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
2041 break;
2042 }
2043 }
2044
2045 if (hw->mac.type == ixgbe_mac_82599EB) {
2046 u32 rttdcs;
2047 u32 mask;
2048
2049 /* disable the arbiter while setting MTQC */
2050 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2051 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2052 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2053
2054 /* set transmit pool layout */
2055 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2056 switch (adapter->flags & mask) {
2057
2058 case (IXGBE_FLAG_SRIOV_ENABLED):
2059 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2060 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2061 break;
2062
2063 case (IXGBE_FLAG_DCB_ENABLED):
2064 /* We enable 8 traffic classes, DCB only */
2065 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2066 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2067 break;
2068
2069 default:
2070 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2071 break;
2072 }
2073
2074 /* re-eable the arbiter */
2075 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2076 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2077 }
2078 }
2079
2080 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2081
2082 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2083 struct ixgbe_ring *rx_ring)
2084 {
2085 u32 srrctl;
2086 int index;
2087 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2088
2089 index = rx_ring->reg_idx;
2090 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2091 unsigned long mask;
2092 mask = (unsigned long) feature[RING_F_RSS].mask;
2093 index = index & mask;
2094 }
2095 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2096
2097 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2098 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2099
2100 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2101 IXGBE_SRRCTL_BSIZEHDR_MASK;
2102
2103 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2104 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2105 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2106 #else
2107 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2108 #endif
2109 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2110 } else {
2111 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2112 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2113 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2114 }
2115
2116 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2117 }
2118
2119 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2120 {
2121 u32 mrqc = 0;
2122 int mask;
2123
2124 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2125 return mrqc;
2126
2127 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2128 #ifdef CONFIG_IXGBE_DCB
2129 | IXGBE_FLAG_DCB_ENABLED
2130 #endif
2131 | IXGBE_FLAG_SRIOV_ENABLED
2132 );
2133
2134 switch (mask) {
2135 case (IXGBE_FLAG_RSS_ENABLED):
2136 mrqc = IXGBE_MRQC_RSSEN;
2137 break;
2138 case (IXGBE_FLAG_SRIOV_ENABLED):
2139 mrqc = IXGBE_MRQC_VMDQEN;
2140 break;
2141 #ifdef CONFIG_IXGBE_DCB
2142 case (IXGBE_FLAG_DCB_ENABLED):
2143 mrqc = IXGBE_MRQC_RT8TCEN;
2144 break;
2145 #endif /* CONFIG_IXGBE_DCB */
2146 default:
2147 break;
2148 }
2149
2150 return mrqc;
2151 }
2152
2153 /**
2154 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2155 * @adapter: address of board private structure
2156 * @index: index of ring to set
2157 **/
2158 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
2159 {
2160 struct ixgbe_ring *rx_ring;
2161 struct ixgbe_hw *hw = &adapter->hw;
2162 int j;
2163 u32 rscctrl;
2164 int rx_buf_len;
2165
2166 rx_ring = &adapter->rx_ring[index];
2167 j = rx_ring->reg_idx;
2168 rx_buf_len = rx_ring->rx_buf_len;
2169 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2170 rscctrl |= IXGBE_RSCCTL_RSCEN;
2171 /*
2172 * we must limit the number of descriptors so that the
2173 * total size of max desc * buf_len is not greater
2174 * than 65535
2175 */
2176 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2177 #if (MAX_SKB_FRAGS > 16)
2178 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2179 #elif (MAX_SKB_FRAGS > 8)
2180 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2181 #elif (MAX_SKB_FRAGS > 4)
2182 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2183 #else
2184 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2185 #endif
2186 } else {
2187 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2188 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2189 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2190 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2191 else
2192 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2193 }
2194 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2195 }
2196
2197 /**
2198 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2199 * @adapter: board private structure
2200 *
2201 * Configure the Rx unit of the MAC after a reset.
2202 **/
2203 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2204 {
2205 u64 rdba;
2206 struct ixgbe_hw *hw = &adapter->hw;
2207 struct ixgbe_ring *rx_ring;
2208 struct net_device *netdev = adapter->netdev;
2209 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2210 int i, j;
2211 u32 rdlen, rxctrl, rxcsum;
2212 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2213 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2214 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2215 u32 fctrl, hlreg0;
2216 u32 reta = 0, mrqc = 0;
2217 u32 rdrxctl;
2218 int rx_buf_len;
2219
2220 /* Decide whether to use packet split mode or not */
2221 /* Do not use packet split if we're in SR-IOV Mode */
2222 if (!adapter->num_vfs)
2223 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2224
2225 /* Set the RX buffer length according to the mode */
2226 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2227 rx_buf_len = IXGBE_RX_HDR_SIZE;
2228 if (hw->mac.type == ixgbe_mac_82599EB) {
2229 /* PSRTYPE must be initialized in 82599 */
2230 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2231 IXGBE_PSRTYPE_UDPHDR |
2232 IXGBE_PSRTYPE_IPV4HDR |
2233 IXGBE_PSRTYPE_IPV6HDR |
2234 IXGBE_PSRTYPE_L2HDR;
2235 IXGBE_WRITE_REG(hw,
2236 IXGBE_PSRTYPE(adapter->num_vfs),
2237 psrtype);
2238 }
2239 } else {
2240 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2241 (netdev->mtu <= ETH_DATA_LEN))
2242 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2243 else
2244 rx_buf_len = ALIGN(max_frame, 1024);
2245 }
2246
2247 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2248 fctrl |= IXGBE_FCTRL_BAM;
2249 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2250 fctrl |= IXGBE_FCTRL_PMCF;
2251 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2252
2253 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2254 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2255 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2256 else
2257 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2258 #ifdef IXGBE_FCOE
2259 if (netdev->features & NETIF_F_FCOE_MTU)
2260 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2261 #endif
2262 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2263
2264 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2265 /* disable receives while setting up the descriptors */
2266 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2267 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2268
2269 /*
2270 * Setup the HW Rx Head and Tail Descriptor Pointers and
2271 * the Base and Length of the Rx Descriptor Ring
2272 */
2273 for (i = 0; i < adapter->num_rx_queues; i++) {
2274 rx_ring = &adapter->rx_ring[i];
2275 rdba = rx_ring->dma;
2276 j = rx_ring->reg_idx;
2277 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2278 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2279 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2280 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2281 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2282 rx_ring->head = IXGBE_RDH(j);
2283 rx_ring->tail = IXGBE_RDT(j);
2284 rx_ring->rx_buf_len = rx_buf_len;
2285
2286 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2287 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2288 else
2289 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2290
2291 #ifdef IXGBE_FCOE
2292 if (netdev->features & NETIF_F_FCOE_MTU) {
2293 struct ixgbe_ring_feature *f;
2294 f = &adapter->ring_feature[RING_F_FCOE];
2295 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2296 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2297 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2298 rx_ring->rx_buf_len =
2299 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2300 }
2301 }
2302
2303 #endif /* IXGBE_FCOE */
2304 ixgbe_configure_srrctl(adapter, rx_ring);
2305 }
2306
2307 if (hw->mac.type == ixgbe_mac_82598EB) {
2308 /*
2309 * For VMDq support of different descriptor types or
2310 * buffer sizes through the use of multiple SRRCTL
2311 * registers, RDRXCTL.MVMEN must be set to 1
2312 *
2313 * also, the manual doesn't mention it clearly but DCA hints
2314 * will only use queue 0's tags unless this bit is set. Side
2315 * effects of setting this bit are only that SRRCTL must be
2316 * fully programmed [0..15]
2317 */
2318 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2319 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2320 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2321 }
2322
2323 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2324 u32 vt_reg_bits;
2325 u32 reg_offset, vf_shift;
2326 u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2327 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN
2328 | IXGBE_VT_CTL_REPLEN;
2329 vt_reg_bits |= (adapter->num_vfs <<
2330 IXGBE_VT_CTL_POOL_SHIFT);
2331 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2332 IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0);
2333
2334 vf_shift = adapter->num_vfs % 32;
2335 reg_offset = adapter->num_vfs / 32;
2336 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0);
2337 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0);
2338 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0);
2339 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0);
2340 /* Enable only the PF's pool for Tx/Rx */
2341 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2342 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2343 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2344 ixgbe_set_vmolr(hw, adapter->num_vfs);
2345 }
2346
2347 /* Program MRQC for the distribution of queues */
2348 mrqc = ixgbe_setup_mrqc(adapter);
2349
2350 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2351 /* Fill out redirection table */
2352 for (i = 0, j = 0; i < 128; i++, j++) {
2353 if (j == adapter->ring_feature[RING_F_RSS].indices)
2354 j = 0;
2355 /* reta = 4-byte sliding window of
2356 * 0x00..(indices-1)(indices-1)00..etc. */
2357 reta = (reta << 8) | (j * 0x11);
2358 if ((i & 3) == 3)
2359 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2360 }
2361
2362 /* Fill out hash function seeds */
2363 for (i = 0; i < 10; i++)
2364 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2365
2366 if (hw->mac.type == ixgbe_mac_82598EB)
2367 mrqc |= IXGBE_MRQC_RSSEN;
2368 /* Perform hash on these packet types */
2369 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2370 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2371 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2372 | IXGBE_MRQC_RSS_FIELD_IPV6
2373 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2374 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2375 }
2376 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2377
2378 if (adapter->num_vfs) {
2379 u32 reg;
2380
2381 /* Map PF MAC address in RAR Entry 0 to first pool
2382 * following VFs */
2383 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2384
2385 /* Set up VF register offsets for selected VT Mode, i.e.
2386 * 64 VFs for SR-IOV */
2387 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2388 reg |= IXGBE_GCR_EXT_SRIOV;
2389 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg);
2390 }
2391
2392 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2393
2394 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2395 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2396 /* Disable indicating checksum in descriptor, enables
2397 * RSS hash */
2398 rxcsum |= IXGBE_RXCSUM_PCSD;
2399 }
2400 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2401 /* Enable IPv4 payload checksum for UDP fragments
2402 * if PCSD is not set */
2403 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2404 }
2405
2406 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2407
2408 if (hw->mac.type == ixgbe_mac_82599EB) {
2409 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2410 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2411 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2412 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2413 }
2414
2415 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2416 /* Enable 82599 HW-RSC */
2417 for (i = 0; i < adapter->num_rx_queues; i++)
2418 ixgbe_configure_rscctl(adapter, i);
2419
2420 /* Disable RSC for ACK packets */
2421 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2422 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2423 }
2424 }
2425
2426 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2427 {
2428 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2429 struct ixgbe_hw *hw = &adapter->hw;
2430
2431 /* add VID to filter table */
2432 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2433 }
2434
2435 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2436 {
2437 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2438 struct ixgbe_hw *hw = &adapter->hw;
2439
2440 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2441 ixgbe_irq_disable(adapter);
2442
2443 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2444
2445 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2446 ixgbe_irq_enable(adapter);
2447
2448 /* remove VID from filter table */
2449 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2450 }
2451
2452 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2453 struct vlan_group *grp)
2454 {
2455 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2456 u32 ctrl;
2457 int i, j;
2458
2459 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2460 ixgbe_irq_disable(adapter);
2461 adapter->vlgrp = grp;
2462
2463 /*
2464 * For a DCB driver, always enable VLAN tag stripping so we can
2465 * still receive traffic from a DCB-enabled host even if we're
2466 * not in DCB mode.
2467 */
2468 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2469
2470 /* Disable CFI check */
2471 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2472
2473 /* enable VLAN tag stripping */
2474 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2475 ctrl |= IXGBE_VLNCTRL_VME;
2476 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2477 for (i = 0; i < adapter->num_rx_queues; i++) {
2478 u32 ctrl;
2479 j = adapter->rx_ring[i].reg_idx;
2480 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2481 ctrl |= IXGBE_RXDCTL_VME;
2482 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2483 }
2484 }
2485
2486 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2487
2488 ixgbe_vlan_rx_add_vid(netdev, 0);
2489
2490 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2491 ixgbe_irq_enable(adapter);
2492 }
2493
2494 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2495 {
2496 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2497
2498 if (adapter->vlgrp) {
2499 u16 vid;
2500 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2501 if (!vlan_group_get_device(adapter->vlgrp, vid))
2502 continue;
2503 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2504 }
2505 }
2506 }
2507
2508 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2509 {
2510 struct dev_mc_list *mc_ptr;
2511 u8 *addr = *mc_addr_ptr;
2512 *vmdq = 0;
2513
2514 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2515 if (mc_ptr->next)
2516 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2517 else
2518 *mc_addr_ptr = NULL;
2519
2520 return addr;
2521 }
2522
2523 /**
2524 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2525 * @netdev: network interface device structure
2526 *
2527 * The set_rx_method entry point is called whenever the unicast/multicast
2528 * address list or the network interface flags are updated. This routine is
2529 * responsible for configuring the hardware for proper unicast, multicast and
2530 * promiscuous mode.
2531 **/
2532 void ixgbe_set_rx_mode(struct net_device *netdev)
2533 {
2534 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2535 struct ixgbe_hw *hw = &adapter->hw;
2536 u32 fctrl, vlnctrl;
2537 u8 *addr_list = NULL;
2538 int addr_count = 0;
2539
2540 /* Check for Promiscuous and All Multicast modes */
2541
2542 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2543 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2544
2545 if (netdev->flags & IFF_PROMISC) {
2546 hw->addr_ctrl.user_set_promisc = 1;
2547 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2548 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2549 } else {
2550 if (netdev->flags & IFF_ALLMULTI) {
2551 fctrl |= IXGBE_FCTRL_MPE;
2552 fctrl &= ~IXGBE_FCTRL_UPE;
2553 } else {
2554 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2555 }
2556 vlnctrl |= IXGBE_VLNCTRL_VFE;
2557 hw->addr_ctrl.user_set_promisc = 0;
2558 }
2559
2560 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2561 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2562
2563 /* reprogram secondary unicast list */
2564 hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
2565
2566 /* reprogram multicast list */
2567 addr_count = netdev->mc_count;
2568 if (addr_count)
2569 addr_list = netdev->mc_list->dmi_addr;
2570 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2571 ixgbe_addr_list_itr);
2572 if (adapter->num_vfs)
2573 ixgbe_restore_vf_multicasts(adapter);
2574 }
2575
2576 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2577 {
2578 int q_idx;
2579 struct ixgbe_q_vector *q_vector;
2580 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2581
2582 /* legacy and MSI only use one vector */
2583 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2584 q_vectors = 1;
2585
2586 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2587 struct napi_struct *napi;
2588 q_vector = adapter->q_vector[q_idx];
2589 napi = &q_vector->napi;
2590 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2591 if (!q_vector->rxr_count || !q_vector->txr_count) {
2592 if (q_vector->txr_count == 1)
2593 napi->poll = &ixgbe_clean_txonly;
2594 else if (q_vector->rxr_count == 1)
2595 napi->poll = &ixgbe_clean_rxonly;
2596 }
2597 }
2598
2599 napi_enable(napi);
2600 }
2601 }
2602
2603 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2604 {
2605 int q_idx;
2606 struct ixgbe_q_vector *q_vector;
2607 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2608
2609 /* legacy and MSI only use one vector */
2610 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2611 q_vectors = 1;
2612
2613 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2614 q_vector = adapter->q_vector[q_idx];
2615 napi_disable(&q_vector->napi);
2616 }
2617 }
2618
2619 #ifdef CONFIG_IXGBE_DCB
2620 /*
2621 * ixgbe_configure_dcb - Configure DCB hardware
2622 * @adapter: ixgbe adapter struct
2623 *
2624 * This is called by the driver on open to configure the DCB hardware.
2625 * This is also called by the gennetlink interface when reconfiguring
2626 * the DCB state.
2627 */
2628 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2629 {
2630 struct ixgbe_hw *hw = &adapter->hw;
2631 u32 txdctl, vlnctrl;
2632 int i, j;
2633
2634 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2635 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2636 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2637
2638 /* reconfigure the hardware */
2639 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2640
2641 for (i = 0; i < adapter->num_tx_queues; i++) {
2642 j = adapter->tx_ring[i].reg_idx;
2643 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2644 /* PThresh workaround for Tx hang with DFP enabled. */
2645 txdctl |= 32;
2646 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2647 }
2648 /* Enable VLAN tag insert/strip */
2649 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2650 if (hw->mac.type == ixgbe_mac_82598EB) {
2651 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2652 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2653 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2654 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2655 vlnctrl |= IXGBE_VLNCTRL_VFE;
2656 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2657 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2658 for (i = 0; i < adapter->num_rx_queues; i++) {
2659 j = adapter->rx_ring[i].reg_idx;
2660 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2661 vlnctrl |= IXGBE_RXDCTL_VME;
2662 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2663 }
2664 }
2665 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2666 }
2667
2668 #endif
2669 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2670 {
2671 struct net_device *netdev = adapter->netdev;
2672 struct ixgbe_hw *hw = &adapter->hw;
2673 int i;
2674
2675 ixgbe_set_rx_mode(netdev);
2676
2677 ixgbe_restore_vlan(adapter);
2678 #ifdef CONFIG_IXGBE_DCB
2679 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2680 if (hw->mac.type == ixgbe_mac_82598EB)
2681 netif_set_gso_max_size(netdev, 32768);
2682 else
2683 netif_set_gso_max_size(netdev, 65536);
2684 ixgbe_configure_dcb(adapter);
2685 } else {
2686 netif_set_gso_max_size(netdev, 65536);
2687 }
2688 #else
2689 netif_set_gso_max_size(netdev, 65536);
2690 #endif
2691
2692 #ifdef IXGBE_FCOE
2693 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2694 ixgbe_configure_fcoe(adapter);
2695
2696 #endif /* IXGBE_FCOE */
2697 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2698 for (i = 0; i < adapter->num_tx_queues; i++)
2699 adapter->tx_ring[i].atr_sample_rate =
2700 adapter->atr_sample_rate;
2701 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2702 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2703 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2704 }
2705
2706 ixgbe_configure_tx(adapter);
2707 ixgbe_configure_rx(adapter);
2708 for (i = 0; i < adapter->num_rx_queues; i++)
2709 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2710 (adapter->rx_ring[i].count - 1));
2711 }
2712
2713 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2714 {
2715 switch (hw->phy.type) {
2716 case ixgbe_phy_sfp_avago:
2717 case ixgbe_phy_sfp_ftl:
2718 case ixgbe_phy_sfp_intel:
2719 case ixgbe_phy_sfp_unknown:
2720 case ixgbe_phy_tw_tyco:
2721 case ixgbe_phy_tw_unknown:
2722 return true;
2723 default:
2724 return false;
2725 }
2726 }
2727
2728 /**
2729 * ixgbe_sfp_link_config - set up SFP+ link
2730 * @adapter: pointer to private adapter struct
2731 **/
2732 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2733 {
2734 struct ixgbe_hw *hw = &adapter->hw;
2735
2736 if (hw->phy.multispeed_fiber) {
2737 /*
2738 * In multispeed fiber setups, the device may not have
2739 * had a physical connection when the driver loaded.
2740 * If that's the case, the initial link configuration
2741 * couldn't get the MAC into 10G or 1G mode, so we'll
2742 * never have a link status change interrupt fire.
2743 * We need to try and force an autonegotiation
2744 * session, then bring up link.
2745 */
2746 hw->mac.ops.setup_sfp(hw);
2747 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2748 schedule_work(&adapter->multispeed_fiber_task);
2749 } else {
2750 /*
2751 * Direct Attach Cu and non-multispeed fiber modules
2752 * still need to be configured properly prior to
2753 * attempting link.
2754 */
2755 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2756 schedule_work(&adapter->sfp_config_module_task);
2757 }
2758 }
2759
2760 /**
2761 * ixgbe_non_sfp_link_config - set up non-SFP+ link
2762 * @hw: pointer to private hardware struct
2763 *
2764 * Returns 0 on success, negative on failure
2765 **/
2766 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2767 {
2768 u32 autoneg;
2769 bool negotiation, link_up = false;
2770 u32 ret = IXGBE_ERR_LINK_SETUP;
2771
2772 if (hw->mac.ops.check_link)
2773 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2774
2775 if (ret)
2776 goto link_cfg_out;
2777
2778 if (hw->mac.ops.get_link_capabilities)
2779 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
2780 if (ret)
2781 goto link_cfg_out;
2782
2783 if (hw->mac.ops.setup_link)
2784 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
2785 link_cfg_out:
2786 return ret;
2787 }
2788
2789 #define IXGBE_MAX_RX_DESC_POLL 10
2790 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2791 int rxr)
2792 {
2793 int j = adapter->rx_ring[rxr].reg_idx;
2794 int k;
2795
2796 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2797 if (IXGBE_READ_REG(&adapter->hw,
2798 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2799 break;
2800 else
2801 msleep(1);
2802 }
2803 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2804 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2805 "not set within the polling period\n", rxr);
2806 }
2807 ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2808 (adapter->rx_ring[rxr].count - 1));
2809 }
2810
2811 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2812 {
2813 struct net_device *netdev = adapter->netdev;
2814 struct ixgbe_hw *hw = &adapter->hw;
2815 int i, j = 0;
2816 int num_rx_rings = adapter->num_rx_queues;
2817 int err;
2818 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2819 u32 txdctl, rxdctl, mhadd;
2820 u32 dmatxctl;
2821 u32 gpie;
2822
2823 ixgbe_get_hw_control(adapter);
2824
2825 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2826 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2827 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2828 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2829 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2830 } else {
2831 /* MSI only */
2832 gpie = 0;
2833 }
2834 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2835 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
2836 gpie |= IXGBE_GPIE_VTMODE_64;
2837 }
2838 /* XXX: to interrupt immediately for EICS writes, enable this */
2839 /* gpie |= IXGBE_GPIE_EIMEN; */
2840 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2841 }
2842
2843 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2844 /*
2845 * use EIAM to auto-mask when MSI-X interrupt is asserted
2846 * this saves a register write for every interrupt
2847 */
2848 switch (hw->mac.type) {
2849 case ixgbe_mac_82598EB:
2850 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2851 break;
2852 default:
2853 case ixgbe_mac_82599EB:
2854 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
2855 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
2856 break;
2857 }
2858 } else {
2859 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2860 * specifically only auto mask tx and rx interrupts */
2861 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2862 }
2863
2864 /* Enable fan failure interrupt if media type is copper */
2865 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2866 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2867 gpie |= IXGBE_SDP1_GPIEN;
2868 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2869 }
2870
2871 if (hw->mac.type == ixgbe_mac_82599EB) {
2872 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2873 gpie |= IXGBE_SDP1_GPIEN;
2874 gpie |= IXGBE_SDP2_GPIEN;
2875 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2876 }
2877
2878 #ifdef IXGBE_FCOE
2879 /* adjust max frame to be able to do baby jumbo for FCoE */
2880 if ((netdev->features & NETIF_F_FCOE_MTU) &&
2881 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2882 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2883
2884 #endif /* IXGBE_FCOE */
2885 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2886 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2887 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2888 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2889
2890 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2891 }
2892
2893 for (i = 0; i < adapter->num_tx_queues; i++) {
2894 j = adapter->tx_ring[i].reg_idx;
2895 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2896 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2897 txdctl |= (8 << 16);
2898 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2899 }
2900
2901 if (hw->mac.type == ixgbe_mac_82599EB) {
2902 /* DMATXCTL.EN must be set after all Tx queue config is done */
2903 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2904 dmatxctl |= IXGBE_DMATXCTL_TE;
2905 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2906 }
2907 for (i = 0; i < adapter->num_tx_queues; i++) {
2908 j = adapter->tx_ring[i].reg_idx;
2909 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2910 txdctl |= IXGBE_TXDCTL_ENABLE;
2911 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2912 if (hw->mac.type == ixgbe_mac_82599EB) {
2913 int wait_loop = 10;
2914 /* poll for Tx Enable ready */
2915 do {
2916 msleep(1);
2917 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2918 } while (--wait_loop &&
2919 !(txdctl & IXGBE_TXDCTL_ENABLE));
2920 if (!wait_loop)
2921 DPRINTK(DRV, ERR, "Could not enable "
2922 "Tx Queue %d\n", j);
2923 }
2924 }
2925
2926 for (i = 0; i < num_rx_rings; i++) {
2927 j = adapter->rx_ring[i].reg_idx;
2928 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2929 /* enable PTHRESH=32 descriptors (half the internal cache)
2930 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2931 * this also removes a pesky rx_no_buffer_count increment */
2932 rxdctl |= 0x0020;
2933 rxdctl |= IXGBE_RXDCTL_ENABLE;
2934 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2935 if (hw->mac.type == ixgbe_mac_82599EB)
2936 ixgbe_rx_desc_queue_enable(adapter, i);
2937 }
2938 /* enable all receives */
2939 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2940 if (hw->mac.type == ixgbe_mac_82598EB)
2941 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2942 else
2943 rxdctl |= IXGBE_RXCTRL_RXEN;
2944 hw->mac.ops.enable_rx_dma(hw, rxdctl);
2945
2946 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2947 ixgbe_configure_msix(adapter);
2948 else
2949 ixgbe_configure_msi_and_legacy(adapter);
2950
2951 clear_bit(__IXGBE_DOWN, &adapter->state);
2952 ixgbe_napi_enable_all(adapter);
2953
2954 /* clear any pending interrupts, may auto mask */
2955 IXGBE_READ_REG(hw, IXGBE_EICR);
2956
2957 ixgbe_irq_enable(adapter);
2958
2959 /*
2960 * If this adapter has a fan, check to see if we had a failure
2961 * before we enabled the interrupt.
2962 */
2963 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2964 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2965 if (esdp & IXGBE_ESDP_SDP1)
2966 DPRINTK(DRV, CRIT,
2967 "Fan has stopped, replace the adapter\n");
2968 }
2969
2970 /*
2971 * For hot-pluggable SFP+ devices, a new SFP+ module may have
2972 * arrived before interrupts were enabled but after probe. Such
2973 * devices wouldn't have their type identified yet. We need to
2974 * kick off the SFP+ module setup first, then try to bring up link.
2975 * If we're not hot-pluggable SFP+, we just need to configure link
2976 * and bring it up.
2977 */
2978 if (hw->phy.type == ixgbe_phy_unknown) {
2979 err = hw->phy.ops.identify(hw);
2980 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2981 /*
2982 * Take the device down and schedule the sfp tasklet
2983 * which will unregister_netdev and log it.
2984 */
2985 ixgbe_down(adapter);
2986 schedule_work(&adapter->sfp_config_module_task);
2987 return err;
2988 }
2989 }
2990
2991 if (ixgbe_is_sfp(hw)) {
2992 ixgbe_sfp_link_config(adapter);
2993 } else {
2994 err = ixgbe_non_sfp_link_config(hw);
2995 if (err)
2996 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2997 }
2998
2999 for (i = 0; i < adapter->num_tx_queues; i++)
3000 set_bit(__IXGBE_FDIR_INIT_DONE,
3001 &(adapter->tx_ring[i].reinit_state));
3002
3003 /* enable transmits */
3004 netif_tx_start_all_queues(netdev);
3005
3006 /* bring the link up in the watchdog, this could race with our first
3007 * link up interrupt but shouldn't be a problem */
3008 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3009 adapter->link_check_timeout = jiffies;
3010 mod_timer(&adapter->watchdog_timer, jiffies);
3011 return 0;
3012 }
3013
3014 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3015 {
3016 WARN_ON(in_interrupt());
3017 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3018 msleep(1);
3019 ixgbe_down(adapter);
3020 ixgbe_up(adapter);
3021 clear_bit(__IXGBE_RESETTING, &adapter->state);
3022 }
3023
3024 int ixgbe_up(struct ixgbe_adapter *adapter)
3025 {
3026 /* hardware has been reset, we need to reload some things */
3027 ixgbe_configure(adapter);
3028
3029 return ixgbe_up_complete(adapter);
3030 }
3031
3032 void ixgbe_reset(struct ixgbe_adapter *adapter)
3033 {
3034 struct ixgbe_hw *hw = &adapter->hw;
3035 int err;
3036
3037 err = hw->mac.ops.init_hw(hw);
3038 switch (err) {
3039 case 0:
3040 case IXGBE_ERR_SFP_NOT_PRESENT:
3041 break;
3042 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3043 dev_err(&adapter->pdev->dev, "master disable timed out\n");
3044 break;
3045 case IXGBE_ERR_EEPROM_VERSION:
3046 /* We are running on a pre-production device, log a warning */
3047 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
3048 "adapter/LOM. Please be aware there may be issues "
3049 "associated with your hardware. If you are "
3050 "experiencing problems please contact your Intel or "
3051 "hardware representative who provided you with this "
3052 "hardware.\n");
3053 break;
3054 default:
3055 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
3056 }
3057
3058 /* reprogram the RAR[0] in case user changed it. */
3059 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3060 IXGBE_RAH_AV);
3061 }
3062
3063 /**
3064 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3065 * @adapter: board private structure
3066 * @rx_ring: ring to free buffers from
3067 **/
3068 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
3069 struct ixgbe_ring *rx_ring)
3070 {
3071 struct pci_dev *pdev = adapter->pdev;
3072 unsigned long size;
3073 unsigned int i;
3074
3075 /* Free all the Rx ring sk_buffs */
3076
3077 for (i = 0; i < rx_ring->count; i++) {
3078 struct ixgbe_rx_buffer *rx_buffer_info;
3079
3080 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3081 if (rx_buffer_info->dma) {
3082 pci_unmap_single(pdev, rx_buffer_info->dma,
3083 rx_ring->rx_buf_len,
3084 PCI_DMA_FROMDEVICE);
3085 rx_buffer_info->dma = 0;
3086 }
3087 if (rx_buffer_info->skb) {
3088 struct sk_buff *skb = rx_buffer_info->skb;
3089 rx_buffer_info->skb = NULL;
3090 do {
3091 struct sk_buff *this = skb;
3092 skb = skb->prev;
3093 dev_kfree_skb(this);
3094 } while (skb);
3095 }
3096 if (!rx_buffer_info->page)
3097 continue;
3098 if (rx_buffer_info->page_dma) {
3099 pci_unmap_page(pdev, rx_buffer_info->page_dma,
3100 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
3101 rx_buffer_info->page_dma = 0;
3102 }
3103 put_page(rx_buffer_info->page);
3104 rx_buffer_info->page = NULL;
3105 rx_buffer_info->page_offset = 0;
3106 }
3107
3108 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3109 memset(rx_ring->rx_buffer_info, 0, size);
3110
3111 /* Zero out the descriptor ring */
3112 memset(rx_ring->desc, 0, rx_ring->size);
3113
3114 rx_ring->next_to_clean = 0;
3115 rx_ring->next_to_use = 0;
3116
3117 if (rx_ring->head)
3118 writel(0, adapter->hw.hw_addr + rx_ring->head);
3119 if (rx_ring->tail)
3120 writel(0, adapter->hw.hw_addr + rx_ring->tail);
3121 }
3122
3123 /**
3124 * ixgbe_clean_tx_ring - Free Tx Buffers
3125 * @adapter: board private structure
3126 * @tx_ring: ring to be cleaned
3127 **/
3128 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
3129 struct ixgbe_ring *tx_ring)
3130 {
3131 struct ixgbe_tx_buffer *tx_buffer_info;
3132 unsigned long size;
3133 unsigned int i;
3134
3135 /* Free all the Tx ring sk_buffs */
3136
3137 for (i = 0; i < tx_ring->count; i++) {
3138 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3139 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3140 }
3141
3142 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3143 memset(tx_ring->tx_buffer_info, 0, size);
3144
3145 /* Zero out the descriptor ring */
3146 memset(tx_ring->desc, 0, tx_ring->size);
3147
3148 tx_ring->next_to_use = 0;
3149 tx_ring->next_to_clean = 0;
3150
3151 if (tx_ring->head)
3152 writel(0, adapter->hw.hw_addr + tx_ring->head);
3153 if (tx_ring->tail)
3154 writel(0, adapter->hw.hw_addr + tx_ring->tail);
3155 }
3156
3157 /**
3158 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3159 * @adapter: board private structure
3160 **/
3161 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3162 {
3163 int i;
3164
3165 for (i = 0; i < adapter->num_rx_queues; i++)
3166 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
3167 }
3168
3169 /**
3170 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3171 * @adapter: board private structure
3172 **/
3173 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3174 {
3175 int i;
3176
3177 for (i = 0; i < adapter->num_tx_queues; i++)
3178 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
3179 }
3180
3181 void ixgbe_down(struct ixgbe_adapter *adapter)
3182 {
3183 struct net_device *netdev = adapter->netdev;
3184 struct ixgbe_hw *hw = &adapter->hw;
3185 u32 rxctrl;
3186 u32 txdctl;
3187 int i, j;
3188
3189 /* signal that we are down to the interrupt handler */
3190 set_bit(__IXGBE_DOWN, &adapter->state);
3191
3192 /* disable receives */
3193 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3194 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3195
3196 netif_tx_disable(netdev);
3197
3198 IXGBE_WRITE_FLUSH(hw);
3199 msleep(10);
3200
3201 netif_tx_stop_all_queues(netdev);
3202
3203 ixgbe_irq_disable(adapter);
3204
3205 ixgbe_napi_disable_all(adapter);
3206
3207 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3208 del_timer_sync(&adapter->sfp_timer);
3209 del_timer_sync(&adapter->watchdog_timer);
3210 cancel_work_sync(&adapter->watchdog_task);
3211
3212 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3213 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3214 cancel_work_sync(&adapter->fdir_reinit_task);
3215
3216 /* disable transmits in the hardware now that interrupts are off */
3217 for (i = 0; i < adapter->num_tx_queues; i++) {
3218 j = adapter->tx_ring[i].reg_idx;
3219 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3220 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3221 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3222 }
3223 /* Disable the Tx DMA engine on 82599 */
3224 if (hw->mac.type == ixgbe_mac_82599EB)
3225 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3226 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3227 ~IXGBE_DMATXCTL_TE));
3228
3229 netif_carrier_off(netdev);
3230
3231 if (!pci_channel_offline(adapter->pdev))
3232 ixgbe_reset(adapter);
3233 ixgbe_clean_all_tx_rings(adapter);
3234 ixgbe_clean_all_rx_rings(adapter);
3235
3236 #ifdef CONFIG_IXGBE_DCA
3237 /* since we reset the hardware DCA settings were cleared */
3238 ixgbe_setup_dca(adapter);
3239 #endif
3240 }
3241
3242 /**
3243 * ixgbe_poll - NAPI Rx polling callback
3244 * @napi: structure for representing this polling device
3245 * @budget: how many packets driver is allowed to clean
3246 *
3247 * This function is used for legacy and MSI, NAPI mode
3248 **/
3249 static int ixgbe_poll(struct napi_struct *napi, int budget)
3250 {
3251 struct ixgbe_q_vector *q_vector =
3252 container_of(napi, struct ixgbe_q_vector, napi);
3253 struct ixgbe_adapter *adapter = q_vector->adapter;
3254 int tx_clean_complete, work_done = 0;
3255
3256 #ifdef CONFIG_IXGBE_DCA
3257 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3258 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
3259 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
3260 }
3261 #endif
3262
3263 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
3264 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
3265
3266 if (!tx_clean_complete)
3267 work_done = budget;
3268
3269 /* If budget not fully consumed, exit the polling mode */
3270 if (work_done < budget) {
3271 napi_complete(napi);
3272 if (adapter->rx_itr_setting & 1)
3273 ixgbe_set_itr(adapter);
3274 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3275 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3276 }
3277 return work_done;
3278 }
3279
3280 /**
3281 * ixgbe_tx_timeout - Respond to a Tx Hang
3282 * @netdev: network interface device structure
3283 **/
3284 static void ixgbe_tx_timeout(struct net_device *netdev)
3285 {
3286 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3287
3288 /* Do the reset outside of interrupt context */
3289 schedule_work(&adapter->reset_task);
3290 }
3291
3292 static void ixgbe_reset_task(struct work_struct *work)
3293 {
3294 struct ixgbe_adapter *adapter;
3295 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3296
3297 /* If we're already down or resetting, just bail */
3298 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3299 test_bit(__IXGBE_RESETTING, &adapter->state))
3300 return;
3301
3302 adapter->tx_timeout_count++;
3303
3304 ixgbe_reinit_locked(adapter);
3305 }
3306
3307 #ifdef CONFIG_IXGBE_DCB
3308 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3309 {
3310 bool ret = false;
3311 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3312
3313 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3314 return ret;
3315
3316 f->mask = 0x7 << 3;
3317 adapter->num_rx_queues = f->indices;
3318 adapter->num_tx_queues = f->indices;
3319 ret = true;
3320
3321 return ret;
3322 }
3323 #endif
3324
3325 /**
3326 * ixgbe_set_rss_queues: Allocate queues for RSS
3327 * @adapter: board private structure to initialize
3328 *
3329 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3330 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3331 *
3332 **/
3333 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3334 {
3335 bool ret = false;
3336 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3337
3338 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3339 f->mask = 0xF;
3340 adapter->num_rx_queues = f->indices;
3341 adapter->num_tx_queues = f->indices;
3342 ret = true;
3343 } else {
3344 ret = false;
3345 }
3346
3347 return ret;
3348 }
3349
3350 /**
3351 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3352 * @adapter: board private structure to initialize
3353 *
3354 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3355 * to the original CPU that initiated the Tx session. This runs in addition
3356 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3357 * Rx load across CPUs using RSS.
3358 *
3359 **/
3360 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3361 {
3362 bool ret = false;
3363 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3364
3365 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3366 f_fdir->mask = 0;
3367
3368 /* Flow Director must have RSS enabled */
3369 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3370 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3371 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3372 adapter->num_tx_queues = f_fdir->indices;
3373 adapter->num_rx_queues = f_fdir->indices;
3374 ret = true;
3375 } else {
3376 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3377 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3378 }
3379 return ret;
3380 }
3381
3382 #ifdef IXGBE_FCOE
3383 /**
3384 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3385 * @adapter: board private structure to initialize
3386 *
3387 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3388 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3389 * rx queues out of the max number of rx queues, instead, it is used as the
3390 * index of the first rx queue used by FCoE.
3391 *
3392 **/
3393 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3394 {
3395 bool ret = false;
3396 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3397
3398 f->indices = min((int)num_online_cpus(), f->indices);
3399 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3400 adapter->num_rx_queues = 1;
3401 adapter->num_tx_queues = 1;
3402 #ifdef CONFIG_IXGBE_DCB
3403 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3404 DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n");
3405 ixgbe_set_dcb_queues(adapter);
3406 }
3407 #endif
3408 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3409 DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n");
3410 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3411 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3412 ixgbe_set_fdir_queues(adapter);
3413 else
3414 ixgbe_set_rss_queues(adapter);
3415 }
3416 /* adding FCoE rx rings to the end */
3417 f->mask = adapter->num_rx_queues;
3418 adapter->num_rx_queues += f->indices;
3419 adapter->num_tx_queues += f->indices;
3420
3421 ret = true;
3422 }
3423
3424 return ret;
3425 }
3426
3427 #endif /* IXGBE_FCOE */
3428 /**
3429 * ixgbe_set_sriov_queues: Allocate queues for IOV use
3430 * @adapter: board private structure to initialize
3431 *
3432 * IOV doesn't actually use anything, so just NAK the
3433 * request for now and let the other queue routines
3434 * figure out what to do.
3435 */
3436 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
3437 {
3438 return false;
3439 }
3440
3441 /*
3442 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3443 * @adapter: board private structure to initialize
3444 *
3445 * This is the top level queue allocation routine. The order here is very
3446 * important, starting with the "most" number of features turned on at once,
3447 * and ending with the smallest set of features. This way large combinations
3448 * can be allocated if they're turned on, and smaller combinations are the
3449 * fallthrough conditions.
3450 *
3451 **/
3452 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3453 {
3454 /* Start with base case */
3455 adapter->num_rx_queues = 1;
3456 adapter->num_tx_queues = 1;
3457 adapter->num_rx_pools = adapter->num_rx_queues;
3458 adapter->num_rx_queues_per_pool = 1;
3459
3460 if (ixgbe_set_sriov_queues(adapter))
3461 return;
3462
3463 #ifdef IXGBE_FCOE
3464 if (ixgbe_set_fcoe_queues(adapter))
3465 goto done;
3466
3467 #endif /* IXGBE_FCOE */
3468 #ifdef CONFIG_IXGBE_DCB
3469 if (ixgbe_set_dcb_queues(adapter))
3470 goto done;
3471
3472 #endif
3473 if (ixgbe_set_fdir_queues(adapter))
3474 goto done;
3475
3476 if (ixgbe_set_rss_queues(adapter))
3477 goto done;
3478
3479 /* fallback to base case */
3480 adapter->num_rx_queues = 1;
3481 adapter->num_tx_queues = 1;
3482
3483 done:
3484 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3485 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
3486 }
3487
3488 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
3489 int vectors)
3490 {
3491 int err, vector_threshold;
3492
3493 /* We'll want at least 3 (vector_threshold):
3494 * 1) TxQ[0] Cleanup
3495 * 2) RxQ[0] Cleanup
3496 * 3) Other (Link Status Change, etc.)
3497 * 4) TCP Timer (optional)
3498 */
3499 vector_threshold = MIN_MSIX_COUNT;
3500
3501 /* The more we get, the more we will assign to Tx/Rx Cleanup
3502 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3503 * Right now, we simply care about how many we'll get; we'll
3504 * set them up later while requesting irq's.
3505 */
3506 while (vectors >= vector_threshold) {
3507 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3508 vectors);
3509 if (!err) /* Success in acquiring all requested vectors. */
3510 break;
3511 else if (err < 0)
3512 vectors = 0; /* Nasty failure, quit now */
3513 else /* err == number of vectors we should try again with */
3514 vectors = err;
3515 }
3516
3517 if (vectors < vector_threshold) {
3518 /* Can't allocate enough MSI-X interrupts? Oh well.
3519 * This just means we'll go with either a single MSI
3520 * vector or fall back to legacy interrupts.
3521 */
3522 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3523 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3524 kfree(adapter->msix_entries);
3525 adapter->msix_entries = NULL;
3526 } else {
3527 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3528 /*
3529 * Adjust for only the vectors we'll use, which is minimum
3530 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3531 * vectors we were allocated.
3532 */
3533 adapter->num_msix_vectors = min(vectors,
3534 adapter->max_msix_q_vectors + NON_Q_VECTORS);
3535 }
3536 }
3537
3538 /**
3539 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3540 * @adapter: board private structure to initialize
3541 *
3542 * Cache the descriptor ring offsets for RSS to the assigned rings.
3543 *
3544 **/
3545 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3546 {
3547 int i;
3548 bool ret = false;
3549
3550 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3551 for (i = 0; i < adapter->num_rx_queues; i++)
3552 adapter->rx_ring[i].reg_idx = i;
3553 for (i = 0; i < adapter->num_tx_queues; i++)
3554 adapter->tx_ring[i].reg_idx = i;
3555 ret = true;
3556 } else {
3557 ret = false;
3558 }
3559
3560 return ret;
3561 }
3562
3563 #ifdef CONFIG_IXGBE_DCB
3564 /**
3565 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3566 * @adapter: board private structure to initialize
3567 *
3568 * Cache the descriptor ring offsets for DCB to the assigned rings.
3569 *
3570 **/
3571 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3572 {
3573 int i;
3574 bool ret = false;
3575 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3576
3577 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3578 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3579 /* the number of queues is assumed to be symmetric */
3580 for (i = 0; i < dcb_i; i++) {
3581 adapter->rx_ring[i].reg_idx = i << 3;
3582 adapter->tx_ring[i].reg_idx = i << 2;
3583 }
3584 ret = true;
3585 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3586 if (dcb_i == 8) {
3587 /*
3588 * Tx TC0 starts at: descriptor queue 0
3589 * Tx TC1 starts at: descriptor queue 32
3590 * Tx TC2 starts at: descriptor queue 64
3591 * Tx TC3 starts at: descriptor queue 80
3592 * Tx TC4 starts at: descriptor queue 96
3593 * Tx TC5 starts at: descriptor queue 104
3594 * Tx TC6 starts at: descriptor queue 112
3595 * Tx TC7 starts at: descriptor queue 120
3596 *
3597 * Rx TC0-TC7 are offset by 16 queues each
3598 */
3599 for (i = 0; i < 3; i++) {
3600 adapter->tx_ring[i].reg_idx = i << 5;
3601 adapter->rx_ring[i].reg_idx = i << 4;
3602 }
3603 for ( ; i < 5; i++) {
3604 adapter->tx_ring[i].reg_idx =
3605 ((i + 2) << 4);
3606 adapter->rx_ring[i].reg_idx = i << 4;
3607 }
3608 for ( ; i < dcb_i; i++) {
3609 adapter->tx_ring[i].reg_idx =
3610 ((i + 8) << 3);
3611 adapter->rx_ring[i].reg_idx = i << 4;
3612 }
3613
3614 ret = true;
3615 } else if (dcb_i == 4) {
3616 /*
3617 * Tx TC0 starts at: descriptor queue 0
3618 * Tx TC1 starts at: descriptor queue 64
3619 * Tx TC2 starts at: descriptor queue 96
3620 * Tx TC3 starts at: descriptor queue 112
3621 *
3622 * Rx TC0-TC3 are offset by 32 queues each
3623 */
3624 adapter->tx_ring[0].reg_idx = 0;
3625 adapter->tx_ring[1].reg_idx = 64;
3626 adapter->tx_ring[2].reg_idx = 96;
3627 adapter->tx_ring[3].reg_idx = 112;
3628 for (i = 0 ; i < dcb_i; i++)
3629 adapter->rx_ring[i].reg_idx = i << 5;
3630
3631 ret = true;
3632 } else {
3633 ret = false;
3634 }
3635 } else {
3636 ret = false;
3637 }
3638 } else {
3639 ret = false;
3640 }
3641
3642 return ret;
3643 }
3644 #endif
3645
3646 /**
3647 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3648 * @adapter: board private structure to initialize
3649 *
3650 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3651 *
3652 **/
3653 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3654 {
3655 int i;
3656 bool ret = false;
3657
3658 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3659 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3660 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3661 for (i = 0; i < adapter->num_rx_queues; i++)
3662 adapter->rx_ring[i].reg_idx = i;
3663 for (i = 0; i < adapter->num_tx_queues; i++)
3664 adapter->tx_ring[i].reg_idx = i;
3665 ret = true;
3666 }
3667
3668 return ret;
3669 }
3670
3671 #ifdef IXGBE_FCOE
3672 /**
3673 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3674 * @adapter: board private structure to initialize
3675 *
3676 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3677 *
3678 */
3679 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3680 {
3681 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
3682 bool ret = false;
3683 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3684
3685 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3686 #ifdef CONFIG_IXGBE_DCB
3687 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3688 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3689
3690 ixgbe_cache_ring_dcb(adapter);
3691 /* find out queues in TC for FCoE */
3692 fcoe_rx_i = adapter->rx_ring[fcoe->tc].reg_idx + 1;
3693 fcoe_tx_i = adapter->tx_ring[fcoe->tc].reg_idx + 1;
3694 /*
3695 * In 82599, the number of Tx queues for each traffic
3696 * class for both 8-TC and 4-TC modes are:
3697 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3698 * 8 TCs: 32 32 16 16 8 8 8 8
3699 * 4 TCs: 64 64 32 32
3700 * We have max 8 queues for FCoE, where 8 the is
3701 * FCoE redirection table size. If TC for FCoE is
3702 * less than or equal to TC3, we have enough queues
3703 * to add max of 8 queues for FCoE, so we start FCoE
3704 * tx descriptor from the next one, i.e., reg_idx + 1.
3705 * If TC for FCoE is above TC3, implying 8 TC mode,
3706 * and we need 8 for FCoE, we have to take all queues
3707 * in that traffic class for FCoE.
3708 */
3709 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3710 fcoe_tx_i--;
3711 }
3712 #endif /* CONFIG_IXGBE_DCB */
3713 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3714 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3715 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3716 ixgbe_cache_ring_fdir(adapter);
3717 else
3718 ixgbe_cache_ring_rss(adapter);
3719
3720 fcoe_rx_i = f->mask;
3721 fcoe_tx_i = f->mask;
3722 }
3723 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
3724 adapter->rx_ring[f->mask + i].reg_idx = fcoe_rx_i;
3725 adapter->tx_ring[f->mask + i].reg_idx = fcoe_tx_i;
3726 }
3727 ret = true;
3728 }
3729 return ret;
3730 }
3731
3732 #endif /* IXGBE_FCOE */
3733 /**
3734 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
3735 * @adapter: board private structure to initialize
3736 *
3737 * SR-IOV doesn't use any descriptor rings but changes the default if
3738 * no other mapping is used.
3739 *
3740 */
3741 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
3742 {
3743 adapter->rx_ring[0].reg_idx = adapter->num_vfs * 2;
3744 adapter->tx_ring[0].reg_idx = adapter->num_vfs * 2;
3745 if (adapter->num_vfs)
3746 return true;
3747 else
3748 return false;
3749 }
3750
3751 /**
3752 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3753 * @adapter: board private structure to initialize
3754 *
3755 * Once we know the feature-set enabled for the device, we'll cache
3756 * the register offset the descriptor ring is assigned to.
3757 *
3758 * Note, the order the various feature calls is important. It must start with
3759 * the "most" features enabled at the same time, then trickle down to the
3760 * least amount of features turned on at once.
3761 **/
3762 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3763 {
3764 /* start with default case */
3765 adapter->rx_ring[0].reg_idx = 0;
3766 adapter->tx_ring[0].reg_idx = 0;
3767
3768 if (ixgbe_cache_ring_sriov(adapter))
3769 return;
3770
3771 #ifdef IXGBE_FCOE
3772 if (ixgbe_cache_ring_fcoe(adapter))
3773 return;
3774
3775 #endif /* IXGBE_FCOE */
3776 #ifdef CONFIG_IXGBE_DCB
3777 if (ixgbe_cache_ring_dcb(adapter))
3778 return;
3779
3780 #endif
3781 if (ixgbe_cache_ring_fdir(adapter))
3782 return;
3783
3784 if (ixgbe_cache_ring_rss(adapter))
3785 return;
3786 }
3787
3788 /**
3789 * ixgbe_alloc_queues - Allocate memory for all rings
3790 * @adapter: board private structure to initialize
3791 *
3792 * We allocate one ring per queue at run-time since we don't know the
3793 * number of queues at compile-time. The polling_netdev array is
3794 * intended for Multiqueue, but should work fine with a single queue.
3795 **/
3796 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3797 {
3798 int i;
3799
3800 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
3801 sizeof(struct ixgbe_ring), GFP_KERNEL);
3802 if (!adapter->tx_ring)
3803 goto err_tx_ring_allocation;
3804
3805 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
3806 sizeof(struct ixgbe_ring), GFP_KERNEL);
3807 if (!adapter->rx_ring)
3808 goto err_rx_ring_allocation;
3809
3810 for (i = 0; i < adapter->num_tx_queues; i++) {
3811 adapter->tx_ring[i].count = adapter->tx_ring_count;
3812 adapter->tx_ring[i].queue_index = i;
3813 }
3814
3815 for (i = 0; i < adapter->num_rx_queues; i++) {
3816 adapter->rx_ring[i].count = adapter->rx_ring_count;
3817 adapter->rx_ring[i].queue_index = i;
3818 }
3819
3820 ixgbe_cache_ring_register(adapter);
3821
3822 return 0;
3823
3824 err_rx_ring_allocation:
3825 kfree(adapter->tx_ring);
3826 err_tx_ring_allocation:
3827 return -ENOMEM;
3828 }
3829
3830 /**
3831 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3832 * @adapter: board private structure to initialize
3833 *
3834 * Attempt to configure the interrupts using the best available
3835 * capabilities of the hardware and the kernel.
3836 **/
3837 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3838 {
3839 struct ixgbe_hw *hw = &adapter->hw;
3840 int err = 0;
3841 int vector, v_budget;
3842
3843 /*
3844 * It's easy to be greedy for MSI-X vectors, but it really
3845 * doesn't do us much good if we have a lot more vectors
3846 * than CPU's. So let's be conservative and only ask for
3847 * (roughly) the same number of vectors as there are CPU's.
3848 */
3849 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3850 (int)num_online_cpus()) + NON_Q_VECTORS;
3851
3852 /*
3853 * At the same time, hardware can only support a maximum of
3854 * hw.mac->max_msix_vectors vectors. With features
3855 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3856 * descriptor queues supported by our device. Thus, we cap it off in
3857 * those rare cases where the cpu count also exceeds our vector limit.
3858 */
3859 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3860
3861 /* A failure in MSI-X entry allocation isn't fatal, but it does
3862 * mean we disable MSI-X capabilities of the adapter. */
3863 adapter->msix_entries = kcalloc(v_budget,
3864 sizeof(struct msix_entry), GFP_KERNEL);
3865 if (adapter->msix_entries) {
3866 for (vector = 0; vector < v_budget; vector++)
3867 adapter->msix_entries[vector].entry = vector;
3868
3869 ixgbe_acquire_msix_vectors(adapter, v_budget);
3870
3871 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3872 goto out;
3873 }
3874
3875 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3876 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3877 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3878 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3879 adapter->atr_sample_rate = 0;
3880 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3881 ixgbe_disable_sriov(adapter);
3882
3883 ixgbe_set_num_queues(adapter);
3884
3885 err = pci_enable_msi(adapter->pdev);
3886 if (!err) {
3887 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3888 } else {
3889 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3890 "falling back to legacy. Error: %d\n", err);
3891 /* reset err */
3892 err = 0;
3893 }
3894
3895 out:
3896 return err;
3897 }
3898
3899 /**
3900 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3901 * @adapter: board private structure to initialize
3902 *
3903 * We allocate one q_vector per queue interrupt. If allocation fails we
3904 * return -ENOMEM.
3905 **/
3906 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3907 {
3908 int q_idx, num_q_vectors;
3909 struct ixgbe_q_vector *q_vector;
3910 int napi_vectors;
3911 int (*poll)(struct napi_struct *, int);
3912
3913 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3914 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3915 napi_vectors = adapter->num_rx_queues;
3916 poll = &ixgbe_clean_rxtx_many;
3917 } else {
3918 num_q_vectors = 1;
3919 napi_vectors = 1;
3920 poll = &ixgbe_poll;
3921 }
3922
3923 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3924 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3925 if (!q_vector)
3926 goto err_out;
3927 q_vector->adapter = adapter;
3928 if (q_vector->txr_count && !q_vector->rxr_count)
3929 q_vector->eitr = adapter->tx_eitr_param;
3930 else
3931 q_vector->eitr = adapter->rx_eitr_param;
3932 q_vector->v_idx = q_idx;
3933 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3934 adapter->q_vector[q_idx] = q_vector;
3935 }
3936
3937 return 0;
3938
3939 err_out:
3940 while (q_idx) {
3941 q_idx--;
3942 q_vector = adapter->q_vector[q_idx];
3943 netif_napi_del(&q_vector->napi);
3944 kfree(q_vector);
3945 adapter->q_vector[q_idx] = NULL;
3946 }
3947 return -ENOMEM;
3948 }
3949
3950 /**
3951 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3952 * @adapter: board private structure to initialize
3953 *
3954 * This function frees the memory allocated to the q_vectors. In addition if
3955 * NAPI is enabled it will delete any references to the NAPI struct prior
3956 * to freeing the q_vector.
3957 **/
3958 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3959 {
3960 int q_idx, num_q_vectors;
3961
3962 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3963 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3964 else
3965 num_q_vectors = 1;
3966
3967 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3968 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3969 adapter->q_vector[q_idx] = NULL;
3970 netif_napi_del(&q_vector->napi);
3971 kfree(q_vector);
3972 }
3973 }
3974
3975 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
3976 {
3977 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3978 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3979 pci_disable_msix(adapter->pdev);
3980 kfree(adapter->msix_entries);
3981 adapter->msix_entries = NULL;
3982 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3983 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3984 pci_disable_msi(adapter->pdev);
3985 }
3986 return;
3987 }
3988
3989 /**
3990 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3991 * @adapter: board private structure to initialize
3992 *
3993 * We determine which interrupt scheme to use based on...
3994 * - Kernel support (MSI, MSI-X)
3995 * - which can be user-defined (via MODULE_PARAM)
3996 * - Hardware queue count (num_*_queues)
3997 * - defined by miscellaneous hardware support/features (RSS, etc.)
3998 **/
3999 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4000 {
4001 int err;
4002
4003 /* Number of supported queues */
4004 ixgbe_set_num_queues(adapter);
4005
4006 err = ixgbe_set_interrupt_capability(adapter);
4007 if (err) {
4008 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
4009 goto err_set_interrupt;
4010 }
4011
4012 err = ixgbe_alloc_q_vectors(adapter);
4013 if (err) {
4014 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
4015 "vectors\n");
4016 goto err_alloc_q_vectors;
4017 }
4018
4019 err = ixgbe_alloc_queues(adapter);
4020 if (err) {
4021 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
4022 goto err_alloc_queues;
4023 }
4024
4025 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
4026 "Tx Queue count = %u\n",
4027 (adapter->num_rx_queues > 1) ? "Enabled" :
4028 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
4029
4030 set_bit(__IXGBE_DOWN, &adapter->state);
4031
4032 return 0;
4033
4034 err_alloc_queues:
4035 ixgbe_free_q_vectors(adapter);
4036 err_alloc_q_vectors:
4037 ixgbe_reset_interrupt_capability(adapter);
4038 err_set_interrupt:
4039 return err;
4040 }
4041
4042 /**
4043 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4044 * @adapter: board private structure to clear interrupt scheme on
4045 *
4046 * We go through and clear interrupt specific resources and reset the structure
4047 * to pre-load conditions
4048 **/
4049 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4050 {
4051 kfree(adapter->tx_ring);
4052 kfree(adapter->rx_ring);
4053 adapter->tx_ring = NULL;
4054 adapter->rx_ring = NULL;
4055
4056 ixgbe_free_q_vectors(adapter);
4057 ixgbe_reset_interrupt_capability(adapter);
4058 }
4059
4060 /**
4061 * ixgbe_sfp_timer - worker thread to find a missing module
4062 * @data: pointer to our adapter struct
4063 **/
4064 static void ixgbe_sfp_timer(unsigned long data)
4065 {
4066 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4067
4068 /*
4069 * Do the sfp_timer outside of interrupt context due to the
4070 * delays that sfp+ detection requires
4071 */
4072 schedule_work(&adapter->sfp_task);
4073 }
4074
4075 /**
4076 * ixgbe_sfp_task - worker thread to find a missing module
4077 * @work: pointer to work_struct containing our data
4078 **/
4079 static void ixgbe_sfp_task(struct work_struct *work)
4080 {
4081 struct ixgbe_adapter *adapter = container_of(work,
4082 struct ixgbe_adapter,
4083 sfp_task);
4084 struct ixgbe_hw *hw = &adapter->hw;
4085
4086 if ((hw->phy.type == ixgbe_phy_nl) &&
4087 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4088 s32 ret = hw->phy.ops.identify_sfp(hw);
4089 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4090 goto reschedule;
4091 ret = hw->phy.ops.reset(hw);
4092 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4093 dev_err(&adapter->pdev->dev, "failed to initialize "
4094 "because an unsupported SFP+ module type "
4095 "was detected.\n"
4096 "Reload the driver after installing a "
4097 "supported module.\n");
4098 unregister_netdev(adapter->netdev);
4099 } else {
4100 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
4101 hw->phy.sfp_type);
4102 }
4103 /* don't need this routine any more */
4104 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4105 }
4106 return;
4107 reschedule:
4108 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4109 mod_timer(&adapter->sfp_timer,
4110 round_jiffies(jiffies + (2 * HZ)));
4111 }
4112
4113 /**
4114 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4115 * @adapter: board private structure to initialize
4116 *
4117 * ixgbe_sw_init initializes the Adapter private data structure.
4118 * Fields are initialized based on PCI device information and
4119 * OS network device settings (MTU size).
4120 **/
4121 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4122 {
4123 struct ixgbe_hw *hw = &adapter->hw;
4124 struct pci_dev *pdev = adapter->pdev;
4125 unsigned int rss;
4126 #ifdef CONFIG_IXGBE_DCB
4127 int j;
4128 struct tc_configuration *tc;
4129 #endif
4130
4131 /* PCI config space info */
4132
4133 hw->vendor_id = pdev->vendor;
4134 hw->device_id = pdev->device;
4135 hw->revision_id = pdev->revision;
4136 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4137 hw->subsystem_device_id = pdev->subsystem_device;
4138
4139 /* Set capability flags */
4140 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4141 adapter->ring_feature[RING_F_RSS].indices = rss;
4142 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4143 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4144 if (hw->mac.type == ixgbe_mac_82598EB) {
4145 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4146 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4147 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4148 } else if (hw->mac.type == ixgbe_mac_82599EB) {
4149 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4150 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4151 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4152 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4153 adapter->ring_feature[RING_F_FDIR].indices =
4154 IXGBE_MAX_FDIR_INDICES;
4155 adapter->atr_sample_rate = 20;
4156 adapter->fdir_pballoc = 0;
4157 #ifdef IXGBE_FCOE
4158 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4159 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4160 adapter->ring_feature[RING_F_FCOE].indices = 0;
4161 #ifdef CONFIG_IXGBE_DCB
4162 /* Default traffic class to use for FCoE */
4163 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4164 #endif
4165 #endif /* IXGBE_FCOE */
4166 }
4167
4168 #ifdef CONFIG_IXGBE_DCB
4169 /* Configure DCB traffic classes */
4170 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4171 tc = &adapter->dcb_cfg.tc_config[j];
4172 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4173 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4174 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4175 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4176 tc->dcb_pfc = pfc_disabled;
4177 }
4178 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4179 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4180 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4181 adapter->dcb_cfg.pfc_mode_enable = false;
4182 adapter->dcb_cfg.round_robin_enable = false;
4183 adapter->dcb_set_bitmap = 0x00;
4184 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4185 adapter->ring_feature[RING_F_DCB].indices);
4186
4187 #endif
4188
4189 /* default flow control settings */
4190 hw->fc.requested_mode = ixgbe_fc_full;
4191 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4192 #ifdef CONFIG_DCB
4193 adapter->last_lfc_mode = hw->fc.current_mode;
4194 #endif
4195 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4196 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4197 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4198 hw->fc.send_xon = true;
4199 hw->fc.disable_fc_autoneg = false;
4200
4201 /* enable itr by default in dynamic mode */
4202 adapter->rx_itr_setting = 1;
4203 adapter->rx_eitr_param = 20000;
4204 adapter->tx_itr_setting = 1;
4205 adapter->tx_eitr_param = 10000;
4206
4207 /* set defaults for eitr in MegaBytes */
4208 adapter->eitr_low = 10;
4209 adapter->eitr_high = 20;
4210
4211 /* set default ring sizes */
4212 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4213 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4214
4215 /* initialize eeprom parameters */
4216 if (ixgbe_init_eeprom_params_generic(hw)) {
4217 dev_err(&pdev->dev, "EEPROM initialization failed\n");
4218 return -EIO;
4219 }
4220
4221 /* enable rx csum by default */
4222 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4223
4224 set_bit(__IXGBE_DOWN, &adapter->state);
4225
4226 return 0;
4227 }
4228
4229 /**
4230 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4231 * @adapter: board private structure
4232 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4233 *
4234 * Return 0 on success, negative on failure
4235 **/
4236 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
4237 struct ixgbe_ring *tx_ring)
4238 {
4239 struct pci_dev *pdev = adapter->pdev;
4240 int size;
4241
4242 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4243 tx_ring->tx_buffer_info = vmalloc(size);
4244 if (!tx_ring->tx_buffer_info)
4245 goto err;
4246 memset(tx_ring->tx_buffer_info, 0, size);
4247
4248 /* round up to nearest 4K */
4249 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4250 tx_ring->size = ALIGN(tx_ring->size, 4096);
4251
4252 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
4253 &tx_ring->dma);
4254 if (!tx_ring->desc)
4255 goto err;
4256
4257 tx_ring->next_to_use = 0;
4258 tx_ring->next_to_clean = 0;
4259 tx_ring->work_limit = tx_ring->count;
4260 return 0;
4261
4262 err:
4263 vfree(tx_ring->tx_buffer_info);
4264 tx_ring->tx_buffer_info = NULL;
4265 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
4266 "descriptor ring\n");
4267 return -ENOMEM;
4268 }
4269
4270 /**
4271 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4272 * @adapter: board private structure
4273 *
4274 * If this function returns with an error, then it's possible one or
4275 * more of the rings is populated (while the rest are not). It is the
4276 * callers duty to clean those orphaned rings.
4277 *
4278 * Return 0 on success, negative on failure
4279 **/
4280 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4281 {
4282 int i, err = 0;
4283
4284 for (i = 0; i < adapter->num_tx_queues; i++) {
4285 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
4286 if (!err)
4287 continue;
4288 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4289 break;
4290 }
4291
4292 return err;
4293 }
4294
4295 /**
4296 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4297 * @adapter: board private structure
4298 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4299 *
4300 * Returns 0 on success, negative on failure
4301 **/
4302 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4303 struct ixgbe_ring *rx_ring)
4304 {
4305 struct pci_dev *pdev = adapter->pdev;
4306 int size;
4307
4308 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4309 rx_ring->rx_buffer_info = vmalloc(size);
4310 if (!rx_ring->rx_buffer_info) {
4311 DPRINTK(PROBE, ERR,
4312 "vmalloc allocation failed for the rx desc ring\n");
4313 goto alloc_failed;
4314 }
4315 memset(rx_ring->rx_buffer_info, 0, size);
4316
4317 /* Round up to nearest 4K */
4318 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4319 rx_ring->size = ALIGN(rx_ring->size, 4096);
4320
4321 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
4322
4323 if (!rx_ring->desc) {
4324 DPRINTK(PROBE, ERR,
4325 "Memory allocation failed for the rx desc ring\n");
4326 vfree(rx_ring->rx_buffer_info);
4327 goto alloc_failed;
4328 }
4329
4330 rx_ring->next_to_clean = 0;
4331 rx_ring->next_to_use = 0;
4332
4333 return 0;
4334
4335 alloc_failed:
4336 return -ENOMEM;
4337 }
4338
4339 /**
4340 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4341 * @adapter: board private structure
4342 *
4343 * If this function returns with an error, then it's possible one or
4344 * more of the rings is populated (while the rest are not). It is the
4345 * callers duty to clean those orphaned rings.
4346 *
4347 * Return 0 on success, negative on failure
4348 **/
4349
4350 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4351 {
4352 int i, err = 0;
4353
4354 for (i = 0; i < adapter->num_rx_queues; i++) {
4355 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
4356 if (!err)
4357 continue;
4358 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4359 break;
4360 }
4361
4362 return err;
4363 }
4364
4365 /**
4366 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4367 * @adapter: board private structure
4368 * @tx_ring: Tx descriptor ring for a specific queue
4369 *
4370 * Free all transmit software resources
4371 **/
4372 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4373 struct ixgbe_ring *tx_ring)
4374 {
4375 struct pci_dev *pdev = adapter->pdev;
4376
4377 ixgbe_clean_tx_ring(adapter, tx_ring);
4378
4379 vfree(tx_ring->tx_buffer_info);
4380 tx_ring->tx_buffer_info = NULL;
4381
4382 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4383
4384 tx_ring->desc = NULL;
4385 }
4386
4387 /**
4388 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4389 * @adapter: board private structure
4390 *
4391 * Free all transmit software resources
4392 **/
4393 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4394 {
4395 int i;
4396
4397 for (i = 0; i < adapter->num_tx_queues; i++)
4398 if (adapter->tx_ring[i].desc)
4399 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
4400 }
4401
4402 /**
4403 * ixgbe_free_rx_resources - Free Rx Resources
4404 * @adapter: board private structure
4405 * @rx_ring: ring to clean the resources from
4406 *
4407 * Free all receive software resources
4408 **/
4409 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4410 struct ixgbe_ring *rx_ring)
4411 {
4412 struct pci_dev *pdev = adapter->pdev;
4413
4414 ixgbe_clean_rx_ring(adapter, rx_ring);
4415
4416 vfree(rx_ring->rx_buffer_info);
4417 rx_ring->rx_buffer_info = NULL;
4418
4419 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4420
4421 rx_ring->desc = NULL;
4422 }
4423
4424 /**
4425 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4426 * @adapter: board private structure
4427 *
4428 * Free all receive software resources
4429 **/
4430 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4431 {
4432 int i;
4433
4434 for (i = 0; i < adapter->num_rx_queues; i++)
4435 if (adapter->rx_ring[i].desc)
4436 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
4437 }
4438
4439 /**
4440 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4441 * @netdev: network interface device structure
4442 * @new_mtu: new value for maximum frame size
4443 *
4444 * Returns 0 on success, negative on failure
4445 **/
4446 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4447 {
4448 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4449 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4450
4451 /* MTU < 68 is an error and causes problems on some kernels */
4452 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4453 return -EINVAL;
4454
4455 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
4456 netdev->mtu, new_mtu);
4457 /* must set new MTU before calling down or up */
4458 netdev->mtu = new_mtu;
4459
4460 if (netif_running(netdev))
4461 ixgbe_reinit_locked(adapter);
4462
4463 return 0;
4464 }
4465
4466 /**
4467 * ixgbe_open - Called when a network interface is made active
4468 * @netdev: network interface device structure
4469 *
4470 * Returns 0 on success, negative value on failure
4471 *
4472 * The open entry point is called when a network interface is made
4473 * active by the system (IFF_UP). At this point all resources needed
4474 * for transmit and receive operations are allocated, the interrupt
4475 * handler is registered with the OS, the watchdog timer is started,
4476 * and the stack is notified that the interface is ready.
4477 **/
4478 static int ixgbe_open(struct net_device *netdev)
4479 {
4480 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4481 int err;
4482
4483 /* disallow open during test */
4484 if (test_bit(__IXGBE_TESTING, &adapter->state))
4485 return -EBUSY;
4486
4487 netif_carrier_off(netdev);
4488
4489 /* allocate transmit descriptors */
4490 err = ixgbe_setup_all_tx_resources(adapter);
4491 if (err)
4492 goto err_setup_tx;
4493
4494 /* allocate receive descriptors */
4495 err = ixgbe_setup_all_rx_resources(adapter);
4496 if (err)
4497 goto err_setup_rx;
4498
4499 ixgbe_configure(adapter);
4500
4501 err = ixgbe_request_irq(adapter);
4502 if (err)
4503 goto err_req_irq;
4504
4505 err = ixgbe_up_complete(adapter);
4506 if (err)
4507 goto err_up;
4508
4509 netif_tx_start_all_queues(netdev);
4510
4511 return 0;
4512
4513 err_up:
4514 ixgbe_release_hw_control(adapter);
4515 ixgbe_free_irq(adapter);
4516 err_req_irq:
4517 err_setup_rx:
4518 ixgbe_free_all_rx_resources(adapter);
4519 err_setup_tx:
4520 ixgbe_free_all_tx_resources(adapter);
4521 ixgbe_reset(adapter);
4522
4523 return err;
4524 }
4525
4526 /**
4527 * ixgbe_close - Disables a network interface
4528 * @netdev: network interface device structure
4529 *
4530 * Returns 0, this is not allowed to fail
4531 *
4532 * The close entry point is called when an interface is de-activated
4533 * by the OS. The hardware is still under the drivers control, but
4534 * needs to be disabled. A global MAC reset is issued to stop the
4535 * hardware, and all transmit and receive resources are freed.
4536 **/
4537 static int ixgbe_close(struct net_device *netdev)
4538 {
4539 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4540
4541 ixgbe_down(adapter);
4542 ixgbe_free_irq(adapter);
4543
4544 ixgbe_free_all_tx_resources(adapter);
4545 ixgbe_free_all_rx_resources(adapter);
4546
4547 ixgbe_release_hw_control(adapter);
4548
4549 return 0;
4550 }
4551
4552 #ifdef CONFIG_PM
4553 static int ixgbe_resume(struct pci_dev *pdev)
4554 {
4555 struct net_device *netdev = pci_get_drvdata(pdev);
4556 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4557 u32 err;
4558
4559 pci_set_power_state(pdev, PCI_D0);
4560 pci_restore_state(pdev);
4561
4562 err = pci_enable_device_mem(pdev);
4563 if (err) {
4564 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
4565 "suspend\n");
4566 return err;
4567 }
4568 pci_set_master(pdev);
4569
4570 pci_wake_from_d3(pdev, false);
4571
4572 err = ixgbe_init_interrupt_scheme(adapter);
4573 if (err) {
4574 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4575 "device\n");
4576 return err;
4577 }
4578
4579 ixgbe_reset(adapter);
4580
4581 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4582
4583 if (netif_running(netdev)) {
4584 err = ixgbe_open(adapter->netdev);
4585 if (err)
4586 return err;
4587 }
4588
4589 netif_device_attach(netdev);
4590
4591 return 0;
4592 }
4593 #endif /* CONFIG_PM */
4594
4595 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4596 {
4597 struct net_device *netdev = pci_get_drvdata(pdev);
4598 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4599 struct ixgbe_hw *hw = &adapter->hw;
4600 u32 ctrl, fctrl;
4601 u32 wufc = adapter->wol;
4602 #ifdef CONFIG_PM
4603 int retval = 0;
4604 #endif
4605
4606 netif_device_detach(netdev);
4607
4608 if (netif_running(netdev)) {
4609 ixgbe_down(adapter);
4610 ixgbe_free_irq(adapter);
4611 ixgbe_free_all_tx_resources(adapter);
4612 ixgbe_free_all_rx_resources(adapter);
4613 }
4614 ixgbe_clear_interrupt_scheme(adapter);
4615
4616 #ifdef CONFIG_PM
4617 retval = pci_save_state(pdev);
4618 if (retval)
4619 return retval;
4620
4621 #endif
4622 if (wufc) {
4623 ixgbe_set_rx_mode(netdev);
4624
4625 /* turn on all-multi mode if wake on multicast is enabled */
4626 if (wufc & IXGBE_WUFC_MC) {
4627 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4628 fctrl |= IXGBE_FCTRL_MPE;
4629 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4630 }
4631
4632 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4633 ctrl |= IXGBE_CTRL_GIO_DIS;
4634 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4635
4636 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4637 } else {
4638 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4639 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4640 }
4641
4642 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4643 pci_wake_from_d3(pdev, true);
4644 else
4645 pci_wake_from_d3(pdev, false);
4646
4647 *enable_wake = !!wufc;
4648
4649 ixgbe_release_hw_control(adapter);
4650
4651 pci_disable_device(pdev);
4652
4653 return 0;
4654 }
4655
4656 #ifdef CONFIG_PM
4657 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4658 {
4659 int retval;
4660 bool wake;
4661
4662 retval = __ixgbe_shutdown(pdev, &wake);
4663 if (retval)
4664 return retval;
4665
4666 if (wake) {
4667 pci_prepare_to_sleep(pdev);
4668 } else {
4669 pci_wake_from_d3(pdev, false);
4670 pci_set_power_state(pdev, PCI_D3hot);
4671 }
4672
4673 return 0;
4674 }
4675 #endif /* CONFIG_PM */
4676
4677 static void ixgbe_shutdown(struct pci_dev *pdev)
4678 {
4679 bool wake;
4680
4681 __ixgbe_shutdown(pdev, &wake);
4682
4683 if (system_state == SYSTEM_POWER_OFF) {
4684 pci_wake_from_d3(pdev, wake);
4685 pci_set_power_state(pdev, PCI_D3hot);
4686 }
4687 }
4688
4689 /**
4690 * ixgbe_update_stats - Update the board statistics counters.
4691 * @adapter: board private structure
4692 **/
4693 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4694 {
4695 struct net_device *netdev = adapter->netdev;
4696 struct ixgbe_hw *hw = &adapter->hw;
4697 u64 total_mpc = 0;
4698 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4699 u64 non_eop_descs = 0, restart_queue = 0;
4700
4701 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
4702 u64 rsc_count = 0;
4703 u64 rsc_flush = 0;
4704 for (i = 0; i < 16; i++)
4705 adapter->hw_rx_no_dma_resources +=
4706 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4707 for (i = 0; i < adapter->num_rx_queues; i++) {
4708 rsc_count += adapter->rx_ring[i].rsc_count;
4709 rsc_flush += adapter->rx_ring[i].rsc_flush;
4710 }
4711 adapter->rsc_total_count = rsc_count;
4712 adapter->rsc_total_flush = rsc_flush;
4713 }
4714
4715 /* gather some stats to the adapter struct that are per queue */
4716 for (i = 0; i < adapter->num_tx_queues; i++)
4717 restart_queue += adapter->tx_ring[i].restart_queue;
4718 adapter->restart_queue = restart_queue;
4719
4720 for (i = 0; i < adapter->num_rx_queues; i++)
4721 non_eop_descs += adapter->rx_ring[i].non_eop_descs;
4722 adapter->non_eop_descs = non_eop_descs;
4723
4724 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
4725 for (i = 0; i < 8; i++) {
4726 /* for packet buffers not used, the register should read 0 */
4727 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4728 missed_rx += mpc;
4729 adapter->stats.mpc[i] += mpc;
4730 total_mpc += adapter->stats.mpc[i];
4731 if (hw->mac.type == ixgbe_mac_82598EB)
4732 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
4733 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4734 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4735 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4736 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
4737 if (hw->mac.type == ixgbe_mac_82599EB) {
4738 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4739 IXGBE_PXONRXCNT(i));
4740 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4741 IXGBE_PXOFFRXCNT(i));
4742 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4743 } else {
4744 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4745 IXGBE_PXONRXC(i));
4746 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4747 IXGBE_PXOFFRXC(i));
4748 }
4749 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4750 IXGBE_PXONTXC(i));
4751 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
4752 IXGBE_PXOFFTXC(i));
4753 }
4754 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4755 /* work around hardware counting issue */
4756 adapter->stats.gprc -= missed_rx;
4757
4758 /* 82598 hardware only has a 32 bit counter in the high register */
4759 if (hw->mac.type == ixgbe_mac_82599EB) {
4760 u64 tmp;
4761 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4762 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4763 adapter->stats.gorc += (tmp << 32);
4764 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4765 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4766 adapter->stats.gotc += (tmp << 32);
4767 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4768 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4769 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4770 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
4771 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4772 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
4773 #ifdef IXGBE_FCOE
4774 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4775 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4776 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4777 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4778 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4779 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4780 #endif /* IXGBE_FCOE */
4781 } else {
4782 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4783 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4784 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4785 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4786 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4787 }
4788 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4789 adapter->stats.bprc += bprc;
4790 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4791 if (hw->mac.type == ixgbe_mac_82598EB)
4792 adapter->stats.mprc -= bprc;
4793 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4794 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4795 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4796 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4797 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4798 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4799 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4800 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4801 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4802 adapter->stats.lxontxc += lxon;
4803 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4804 adapter->stats.lxofftxc += lxoff;
4805 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4806 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4807 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4808 /*
4809 * 82598 errata - tx of flow control packets is included in tx counters
4810 */
4811 xon_off_tot = lxon + lxoff;
4812 adapter->stats.gptc -= xon_off_tot;
4813 adapter->stats.mptc -= xon_off_tot;
4814 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4815 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4816 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4817 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4818 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4819 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4820 adapter->stats.ptc64 -= xon_off_tot;
4821 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4822 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4823 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4824 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4825 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4826 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4827
4828 /* Fill out the OS statistics structure */
4829 netdev->stats.multicast = adapter->stats.mprc;
4830
4831 /* Rx Errors */
4832 netdev->stats.rx_errors = adapter->stats.crcerrs +
4833 adapter->stats.rlec;
4834 netdev->stats.rx_dropped = 0;
4835 netdev->stats.rx_length_errors = adapter->stats.rlec;
4836 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4837 netdev->stats.rx_missed_errors = total_mpc;
4838 }
4839
4840 /**
4841 * ixgbe_watchdog - Timer Call-back
4842 * @data: pointer to adapter cast into an unsigned long
4843 **/
4844 static void ixgbe_watchdog(unsigned long data)
4845 {
4846 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4847 struct ixgbe_hw *hw = &adapter->hw;
4848 u64 eics = 0;
4849 int i;
4850
4851 /*
4852 * Do the watchdog outside of interrupt context due to the lovely
4853 * delays that some of the newer hardware requires
4854 */
4855
4856 if (test_bit(__IXGBE_DOWN, &adapter->state))
4857 goto watchdog_short_circuit;
4858
4859 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4860 /*
4861 * for legacy and MSI interrupts don't set any bits
4862 * that are enabled for EIAM, because this operation
4863 * would set *both* EIMS and EICS for any bit in EIAM
4864 */
4865 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4866 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4867 goto watchdog_reschedule;
4868 }
4869
4870 /* get one bit for every active tx/rx interrupt vector */
4871 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4872 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4873 if (qv->rxr_count || qv->txr_count)
4874 eics |= ((u64)1 << i);
4875 }
4876
4877 /* Cause software interrupt to ensure rx rings are cleaned */
4878 ixgbe_irq_rearm_queues(adapter, eics);
4879
4880 watchdog_reschedule:
4881 /* Reset the timer */
4882 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4883
4884 watchdog_short_circuit:
4885 schedule_work(&adapter->watchdog_task);
4886 }
4887
4888 /**
4889 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4890 * @work: pointer to work_struct containing our data
4891 **/
4892 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4893 {
4894 struct ixgbe_adapter *adapter = container_of(work,
4895 struct ixgbe_adapter,
4896 multispeed_fiber_task);
4897 struct ixgbe_hw *hw = &adapter->hw;
4898 u32 autoneg;
4899 bool negotiation;
4900
4901 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4902 autoneg = hw->phy.autoneg_advertised;
4903 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
4904 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
4905 if (hw->mac.ops.setup_link)
4906 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
4907 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4908 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4909 }
4910
4911 /**
4912 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4913 * @work: pointer to work_struct containing our data
4914 **/
4915 static void ixgbe_sfp_config_module_task(struct work_struct *work)
4916 {
4917 struct ixgbe_adapter *adapter = container_of(work,
4918 struct ixgbe_adapter,
4919 sfp_config_module_task);
4920 struct ixgbe_hw *hw = &adapter->hw;
4921 u32 err;
4922
4923 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4924
4925 /* Time for electrical oscillations to settle down */
4926 msleep(100);
4927 err = hw->phy.ops.identify_sfp(hw);
4928
4929 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4930 dev_err(&adapter->pdev->dev, "failed to initialize because "
4931 "an unsupported SFP+ module type was detected.\n"
4932 "Reload the driver after installing a supported "
4933 "module.\n");
4934 unregister_netdev(adapter->netdev);
4935 return;
4936 }
4937 hw->mac.ops.setup_sfp(hw);
4938
4939 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
4940 /* This will also work for DA Twinax connections */
4941 schedule_work(&adapter->multispeed_fiber_task);
4942 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4943 }
4944
4945 /**
4946 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4947 * @work: pointer to work_struct containing our data
4948 **/
4949 static void ixgbe_fdir_reinit_task(struct work_struct *work)
4950 {
4951 struct ixgbe_adapter *adapter = container_of(work,
4952 struct ixgbe_adapter,
4953 fdir_reinit_task);
4954 struct ixgbe_hw *hw = &adapter->hw;
4955 int i;
4956
4957 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4958 for (i = 0; i < adapter->num_tx_queues; i++)
4959 set_bit(__IXGBE_FDIR_INIT_DONE,
4960 &(adapter->tx_ring[i].reinit_state));
4961 } else {
4962 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4963 "ignored adding FDIR ATR filters \n");
4964 }
4965 /* Done FDIR Re-initialization, enable transmits */
4966 netif_tx_start_all_queues(adapter->netdev);
4967 }
4968
4969 /**
4970 * ixgbe_watchdog_task - worker thread to bring link up
4971 * @work: pointer to work_struct containing our data
4972 **/
4973 static void ixgbe_watchdog_task(struct work_struct *work)
4974 {
4975 struct ixgbe_adapter *adapter = container_of(work,
4976 struct ixgbe_adapter,
4977 watchdog_task);
4978 struct net_device *netdev = adapter->netdev;
4979 struct ixgbe_hw *hw = &adapter->hw;
4980 u32 link_speed = adapter->link_speed;
4981 bool link_up = adapter->link_up;
4982 int i;
4983 struct ixgbe_ring *tx_ring;
4984 int some_tx_pending = 0;
4985
4986 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4987
4988 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4989 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4990 if (link_up) {
4991 #ifdef CONFIG_DCB
4992 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4993 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
4994 hw->mac.ops.fc_enable(hw, i);
4995 } else {
4996 hw->mac.ops.fc_enable(hw, 0);
4997 }
4998 #else
4999 hw->mac.ops.fc_enable(hw, 0);
5000 #endif
5001 }
5002
5003 if (link_up ||
5004 time_after(jiffies, (adapter->link_check_timeout +
5005 IXGBE_TRY_LINK_TIMEOUT))) {
5006 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5007 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5008 }
5009 adapter->link_up = link_up;
5010 adapter->link_speed = link_speed;
5011 }
5012
5013 if (link_up) {
5014 if (!netif_carrier_ok(netdev)) {
5015 bool flow_rx, flow_tx;
5016
5017 if (hw->mac.type == ixgbe_mac_82599EB) {
5018 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5019 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5020 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5021 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5022 } else {
5023 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5024 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5025 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5026 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5027 }
5028
5029 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
5030 "Flow Control: %s\n",
5031 netdev->name,
5032 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5033 "10 Gbps" :
5034 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5035 "1 Gbps" : "unknown speed")),
5036 ((flow_rx && flow_tx) ? "RX/TX" :
5037 (flow_rx ? "RX" :
5038 (flow_tx ? "TX" : "None"))));
5039
5040 netif_carrier_on(netdev);
5041 } else {
5042 /* Force detection of hung controller */
5043 adapter->detect_tx_hung = true;
5044 }
5045 } else {
5046 adapter->link_up = false;
5047 adapter->link_speed = 0;
5048 if (netif_carrier_ok(netdev)) {
5049 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
5050 netdev->name);
5051 netif_carrier_off(netdev);
5052 }
5053 }
5054
5055 if (!netif_carrier_ok(netdev)) {
5056 for (i = 0; i < adapter->num_tx_queues; i++) {
5057 tx_ring = &adapter->tx_ring[i];
5058 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5059 some_tx_pending = 1;
5060 break;
5061 }
5062 }
5063
5064 if (some_tx_pending) {
5065 /* We've lost link, so the controller stops DMA,
5066 * but we've got queued Tx work that's never going
5067 * to get done, so reset controller to flush Tx.
5068 * (Do the reset outside of interrupt context).
5069 */
5070 schedule_work(&adapter->reset_task);
5071 }
5072 }
5073
5074 ixgbe_update_stats(adapter);
5075 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
5076 }
5077
5078 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5079 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5080 u32 tx_flags, u8 *hdr_len)
5081 {
5082 struct ixgbe_adv_tx_context_desc *context_desc;
5083 unsigned int i;
5084 int err;
5085 struct ixgbe_tx_buffer *tx_buffer_info;
5086 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5087 u32 mss_l4len_idx, l4len;
5088
5089 if (skb_is_gso(skb)) {
5090 if (skb_header_cloned(skb)) {
5091 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5092 if (err)
5093 return err;
5094 }
5095 l4len = tcp_hdrlen(skb);
5096 *hdr_len += l4len;
5097
5098 if (skb->protocol == htons(ETH_P_IP)) {
5099 struct iphdr *iph = ip_hdr(skb);
5100 iph->tot_len = 0;
5101 iph->check = 0;
5102 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5103 iph->daddr, 0,
5104 IPPROTO_TCP,
5105 0);
5106 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
5107 ipv6_hdr(skb)->payload_len = 0;
5108 tcp_hdr(skb)->check =
5109 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5110 &ipv6_hdr(skb)->daddr,
5111 0, IPPROTO_TCP, 0);
5112 }
5113
5114 i = tx_ring->next_to_use;
5115
5116 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5117 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5118
5119 /* VLAN MACLEN IPLEN */
5120 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5121 vlan_macip_lens |=
5122 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5123 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5124 IXGBE_ADVTXD_MACLEN_SHIFT);
5125 *hdr_len += skb_network_offset(skb);
5126 vlan_macip_lens |=
5127 (skb_transport_header(skb) - skb_network_header(skb));
5128 *hdr_len +=
5129 (skb_transport_header(skb) - skb_network_header(skb));
5130 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5131 context_desc->seqnum_seed = 0;
5132
5133 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5134 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
5135 IXGBE_ADVTXD_DTYP_CTXT);
5136
5137 if (skb->protocol == htons(ETH_P_IP))
5138 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5139 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5140 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5141
5142 /* MSS L4LEN IDX */
5143 mss_l4len_idx =
5144 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5145 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
5146 /* use index 1 for TSO */
5147 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5148 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5149
5150 tx_buffer_info->time_stamp = jiffies;
5151 tx_buffer_info->next_to_watch = i;
5152
5153 i++;
5154 if (i == tx_ring->count)
5155 i = 0;
5156 tx_ring->next_to_use = i;
5157
5158 return true;
5159 }
5160 return false;
5161 }
5162
5163 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
5164 struct ixgbe_ring *tx_ring,
5165 struct sk_buff *skb, u32 tx_flags)
5166 {
5167 struct ixgbe_adv_tx_context_desc *context_desc;
5168 unsigned int i;
5169 struct ixgbe_tx_buffer *tx_buffer_info;
5170 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5171
5172 if (skb->ip_summed == CHECKSUM_PARTIAL ||
5173 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5174 i = tx_ring->next_to_use;
5175 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5176 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5177
5178 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5179 vlan_macip_lens |=
5180 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5181 vlan_macip_lens |= (skb_network_offset(skb) <<
5182 IXGBE_ADVTXD_MACLEN_SHIFT);
5183 if (skb->ip_summed == CHECKSUM_PARTIAL)
5184 vlan_macip_lens |= (skb_transport_header(skb) -
5185 skb_network_header(skb));
5186
5187 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5188 context_desc->seqnum_seed = 0;
5189
5190 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
5191 IXGBE_ADVTXD_DTYP_CTXT);
5192
5193 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5194 __be16 protocol;
5195
5196 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5197 const struct vlan_ethhdr *vhdr =
5198 (const struct vlan_ethhdr *)skb->data;
5199
5200 protocol = vhdr->h_vlan_encapsulated_proto;
5201 } else {
5202 protocol = skb->protocol;
5203 }
5204
5205 switch (protocol) {
5206 case cpu_to_be16(ETH_P_IP):
5207 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5208 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5209 type_tucmd_mlhl |=
5210 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5211 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5212 type_tucmd_mlhl |=
5213 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5214 break;
5215 case cpu_to_be16(ETH_P_IPV6):
5216 /* XXX what about other V6 headers?? */
5217 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5218 type_tucmd_mlhl |=
5219 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5220 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5221 type_tucmd_mlhl |=
5222 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5223 break;
5224 default:
5225 if (unlikely(net_ratelimit())) {
5226 DPRINTK(PROBE, WARNING,
5227 "partial checksum but proto=%x!\n",
5228 skb->protocol);
5229 }
5230 break;
5231 }
5232 }
5233
5234 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5235 /* use index zero for tx checksum offload */
5236 context_desc->mss_l4len_idx = 0;
5237
5238 tx_buffer_info->time_stamp = jiffies;
5239 tx_buffer_info->next_to_watch = i;
5240
5241 i++;
5242 if (i == tx_ring->count)
5243 i = 0;
5244 tx_ring->next_to_use = i;
5245
5246 return true;
5247 }
5248
5249 return false;
5250 }
5251
5252 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
5253 struct ixgbe_ring *tx_ring,
5254 struct sk_buff *skb, u32 tx_flags,
5255 unsigned int first)
5256 {
5257 struct pci_dev *pdev = adapter->pdev;
5258 struct ixgbe_tx_buffer *tx_buffer_info;
5259 unsigned int len;
5260 unsigned int total = skb->len;
5261 unsigned int offset = 0, size, count = 0, i;
5262 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5263 unsigned int f;
5264
5265 i = tx_ring->next_to_use;
5266
5267 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5268 /* excluding fcoe_crc_eof for FCoE */
5269 total -= sizeof(struct fcoe_crc_eof);
5270
5271 len = min(skb_headlen(skb), total);
5272 while (len) {
5273 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5274 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5275
5276 tx_buffer_info->length = size;
5277 tx_buffer_info->mapped_as_page = false;
5278 tx_buffer_info->dma = pci_map_single(pdev,
5279 skb->data + offset,
5280 size, PCI_DMA_TODEVICE);
5281 if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5282 goto dma_error;
5283 tx_buffer_info->time_stamp = jiffies;
5284 tx_buffer_info->next_to_watch = i;
5285
5286 len -= size;
5287 total -= size;
5288 offset += size;
5289 count++;
5290
5291 if (len) {
5292 i++;
5293 if (i == tx_ring->count)
5294 i = 0;
5295 }
5296 }
5297
5298 for (f = 0; f < nr_frags; f++) {
5299 struct skb_frag_struct *frag;
5300
5301 frag = &skb_shinfo(skb)->frags[f];
5302 len = min((unsigned int)frag->size, total);
5303 offset = frag->page_offset;
5304
5305 while (len) {
5306 i++;
5307 if (i == tx_ring->count)
5308 i = 0;
5309
5310 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5311 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5312
5313 tx_buffer_info->length = size;
5314 tx_buffer_info->dma = pci_map_page(adapter->pdev,
5315 frag->page,
5316 offset, size,
5317 PCI_DMA_TODEVICE);
5318 tx_buffer_info->mapped_as_page = true;
5319 if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5320 goto dma_error;
5321 tx_buffer_info->time_stamp = jiffies;
5322 tx_buffer_info->next_to_watch = i;
5323
5324 len -= size;
5325 total -= size;
5326 offset += size;
5327 count++;
5328 }
5329 if (total == 0)
5330 break;
5331 }
5332
5333 tx_ring->tx_buffer_info[i].skb = skb;
5334 tx_ring->tx_buffer_info[first].next_to_watch = i;
5335
5336 return count;
5337
5338 dma_error:
5339 dev_err(&pdev->dev, "TX DMA map failed\n");
5340
5341 /* clear timestamp and dma mappings for failed tx_buffer_info map */
5342 tx_buffer_info->dma = 0;
5343 tx_buffer_info->time_stamp = 0;
5344 tx_buffer_info->next_to_watch = 0;
5345 count--;
5346
5347 /* clear timestamp and dma mappings for remaining portion of packet */
5348 while (count >= 0) {
5349 count--;
5350 i--;
5351 if (i < 0)
5352 i += tx_ring->count;
5353 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5354 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
5355 }
5356
5357 return count;
5358 }
5359
5360 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
5361 struct ixgbe_ring *tx_ring,
5362 int tx_flags, int count, u32 paylen, u8 hdr_len)
5363 {
5364 union ixgbe_adv_tx_desc *tx_desc = NULL;
5365 struct ixgbe_tx_buffer *tx_buffer_info;
5366 u32 olinfo_status = 0, cmd_type_len = 0;
5367 unsigned int i;
5368 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5369
5370 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5371
5372 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5373
5374 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5375 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5376
5377 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5378 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5379
5380 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5381 IXGBE_ADVTXD_POPTS_SHIFT;
5382
5383 /* use index 1 context for tso */
5384 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5385 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5386 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
5387 IXGBE_ADVTXD_POPTS_SHIFT;
5388
5389 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5390 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5391 IXGBE_ADVTXD_POPTS_SHIFT;
5392
5393 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5394 olinfo_status |= IXGBE_ADVTXD_CC;
5395 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5396 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5397 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5398 }
5399
5400 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5401
5402 i = tx_ring->next_to_use;
5403 while (count--) {
5404 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5405 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5406 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5407 tx_desc->read.cmd_type_len =
5408 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
5409 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5410 i++;
5411 if (i == tx_ring->count)
5412 i = 0;
5413 }
5414
5415 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5416
5417 /*
5418 * Force memory writes to complete before letting h/w
5419 * know there are new descriptors to fetch. (Only
5420 * applicable for weak-ordered memory model archs,
5421 * such as IA-64).
5422 */
5423 wmb();
5424
5425 tx_ring->next_to_use = i;
5426 writel(i, adapter->hw.hw_addr + tx_ring->tail);
5427 }
5428
5429 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5430 int queue, u32 tx_flags)
5431 {
5432 /* Right now, we support IPv4 only */
5433 struct ixgbe_atr_input atr_input;
5434 struct tcphdr *th;
5435 struct iphdr *iph = ip_hdr(skb);
5436 struct ethhdr *eth = (struct ethhdr *)skb->data;
5437 u16 vlan_id, src_port, dst_port, flex_bytes;
5438 u32 src_ipv4_addr, dst_ipv4_addr;
5439 u8 l4type = 0;
5440
5441 /* check if we're UDP or TCP */
5442 if (iph->protocol == IPPROTO_TCP) {
5443 th = tcp_hdr(skb);
5444 src_port = th->source;
5445 dst_port = th->dest;
5446 l4type |= IXGBE_ATR_L4TYPE_TCP;
5447 /* l4type IPv4 type is 0, no need to assign */
5448 } else {
5449 /* Unsupported L4 header, just bail here */
5450 return;
5451 }
5452
5453 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5454
5455 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5456 IXGBE_TX_FLAGS_VLAN_SHIFT;
5457 src_ipv4_addr = iph->saddr;
5458 dst_ipv4_addr = iph->daddr;
5459 flex_bytes = eth->h_proto;
5460
5461 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5462 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5463 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5464 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5465 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5466 /* src and dst are inverted, think how the receiver sees them */
5467 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5468 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5469
5470 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5471 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5472 }
5473
5474 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
5475 struct ixgbe_ring *tx_ring, int size)
5476 {
5477 netif_stop_subqueue(netdev, tx_ring->queue_index);
5478 /* Herbert's original patch had:
5479 * smp_mb__after_netif_stop_queue();
5480 * but since that doesn't exist yet, just open code it. */
5481 smp_mb();
5482
5483 /* We need to check again in a case another CPU has just
5484 * made room available. */
5485 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5486 return -EBUSY;
5487
5488 /* A reprieve! - use start_queue because it doesn't call schedule */
5489 netif_start_subqueue(netdev, tx_ring->queue_index);
5490 ++tx_ring->restart_queue;
5491 return 0;
5492 }
5493
5494 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
5495 struct ixgbe_ring *tx_ring, int size)
5496 {
5497 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5498 return 0;
5499 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5500 }
5501
5502 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5503 {
5504 struct ixgbe_adapter *adapter = netdev_priv(dev);
5505 int txq = smp_processor_id();
5506
5507 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5508 return txq;
5509
5510 #ifdef IXGBE_FCOE
5511 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5512 (skb->protocol == htons(ETH_P_FCOE))) {
5513 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5514 txq += adapter->ring_feature[RING_F_FCOE].mask;
5515 return txq;
5516 }
5517 #endif
5518 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5519 return (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) >> 13;
5520
5521 return skb_tx_hash(dev, skb);
5522 }
5523
5524 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5525 struct net_device *netdev)
5526 {
5527 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5528 struct ixgbe_ring *tx_ring;
5529 struct netdev_queue *txq;
5530 unsigned int first;
5531 unsigned int tx_flags = 0;
5532 u8 hdr_len = 0;
5533 int tso;
5534 int count = 0;
5535 unsigned int f;
5536
5537 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5538 tx_flags |= vlan_tx_tag_get(skb);
5539 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5540 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5541 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
5542 }
5543 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5544 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5545 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5546 if (skb->priority != TC_PRIO_CONTROL) {
5547 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
5548 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5549 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5550 } else {
5551 skb->queue_mapping =
5552 adapter->ring_feature[RING_F_DCB].indices-1;
5553 }
5554 }
5555
5556 tx_ring = &adapter->tx_ring[skb->queue_mapping];
5557
5558 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5559 (skb->protocol == htons(ETH_P_FCOE))) {
5560 tx_flags |= IXGBE_TX_FLAGS_FCOE;
5561 #ifdef IXGBE_FCOE
5562 #ifdef CONFIG_IXGBE_DCB
5563 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
5564 << IXGBE_TX_FLAGS_VLAN_SHIFT);
5565 tx_flags |= ((adapter->fcoe.up << 13)
5566 << IXGBE_TX_FLAGS_VLAN_SHIFT);
5567 #endif
5568 #endif
5569 }
5570 /* four things can cause us to need a context descriptor */
5571 if (skb_is_gso(skb) ||
5572 (skb->ip_summed == CHECKSUM_PARTIAL) ||
5573 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5574 (tx_flags & IXGBE_TX_FLAGS_FCOE))
5575 count++;
5576
5577 count += TXD_USE_COUNT(skb_headlen(skb));
5578 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5579 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5580
5581 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
5582 adapter->tx_busy++;
5583 return NETDEV_TX_BUSY;
5584 }
5585
5586 first = tx_ring->next_to_use;
5587 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5588 #ifdef IXGBE_FCOE
5589 /* setup tx offload for FCoE */
5590 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5591 if (tso < 0) {
5592 dev_kfree_skb_any(skb);
5593 return NETDEV_TX_OK;
5594 }
5595 if (tso)
5596 tx_flags |= IXGBE_TX_FLAGS_FSO;
5597 #endif /* IXGBE_FCOE */
5598 } else {
5599 if (skb->protocol == htons(ETH_P_IP))
5600 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5601 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5602 if (tso < 0) {
5603 dev_kfree_skb_any(skb);
5604 return NETDEV_TX_OK;
5605 }
5606
5607 if (tso)
5608 tx_flags |= IXGBE_TX_FLAGS_TSO;
5609 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5610 (skb->ip_summed == CHECKSUM_PARTIAL))
5611 tx_flags |= IXGBE_TX_FLAGS_CSUM;
5612 }
5613
5614 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
5615 if (count) {
5616 /* add the ATR filter if ATR is on */
5617 if (tx_ring->atr_sample_rate) {
5618 ++tx_ring->atr_count;
5619 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5620 test_bit(__IXGBE_FDIR_INIT_DONE,
5621 &tx_ring->reinit_state)) {
5622 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5623 tx_flags);
5624 tx_ring->atr_count = 0;
5625 }
5626 }
5627 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
5628 txq->tx_bytes += skb->len;
5629 txq->tx_packets++;
5630 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5631 hdr_len);
5632 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
5633
5634 } else {
5635 dev_kfree_skb_any(skb);
5636 tx_ring->tx_buffer_info[first].time_stamp = 0;
5637 tx_ring->next_to_use = first;
5638 }
5639
5640 return NETDEV_TX_OK;
5641 }
5642
5643 /**
5644 * ixgbe_set_mac - Change the Ethernet Address of the NIC
5645 * @netdev: network interface device structure
5646 * @p: pointer to an address structure
5647 *
5648 * Returns 0 on success, negative on failure
5649 **/
5650 static int ixgbe_set_mac(struct net_device *netdev, void *p)
5651 {
5652 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5653 struct ixgbe_hw *hw = &adapter->hw;
5654 struct sockaddr *addr = p;
5655
5656 if (!is_valid_ether_addr(addr->sa_data))
5657 return -EADDRNOTAVAIL;
5658
5659 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
5660 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5661
5662 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
5663 IXGBE_RAH_AV);
5664
5665 return 0;
5666 }
5667
5668 static int
5669 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5670 {
5671 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5672 struct ixgbe_hw *hw = &adapter->hw;
5673 u16 value;
5674 int rc;
5675
5676 if (prtad != hw->phy.mdio.prtad)
5677 return -EINVAL;
5678 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5679 if (!rc)
5680 rc = value;
5681 return rc;
5682 }
5683
5684 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5685 u16 addr, u16 value)
5686 {
5687 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5688 struct ixgbe_hw *hw = &adapter->hw;
5689
5690 if (prtad != hw->phy.mdio.prtad)
5691 return -EINVAL;
5692 return hw->phy.ops.write_reg(hw, addr, devad, value);
5693 }
5694
5695 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5696 {
5697 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5698
5699 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5700 }
5701
5702 /**
5703 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5704 * netdev->dev_addrs
5705 * @netdev: network interface device structure
5706 *
5707 * Returns non-zero on failure
5708 **/
5709 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5710 {
5711 int err = 0;
5712 struct ixgbe_adapter *adapter = netdev_priv(dev);
5713 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5714
5715 if (is_valid_ether_addr(mac->san_addr)) {
5716 rtnl_lock();
5717 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5718 rtnl_unlock();
5719 }
5720 return err;
5721 }
5722
5723 /**
5724 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5725 * netdev->dev_addrs
5726 * @netdev: network interface device structure
5727 *
5728 * Returns non-zero on failure
5729 **/
5730 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5731 {
5732 int err = 0;
5733 struct ixgbe_adapter *adapter = netdev_priv(dev);
5734 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5735
5736 if (is_valid_ether_addr(mac->san_addr)) {
5737 rtnl_lock();
5738 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5739 rtnl_unlock();
5740 }
5741 return err;
5742 }
5743
5744 #ifdef CONFIG_NET_POLL_CONTROLLER
5745 /*
5746 * Polling 'interrupt' - used by things like netconsole to send skbs
5747 * without having to re-enable interrupts. It's not called while
5748 * the interrupt routine is executing.
5749 */
5750 static void ixgbe_netpoll(struct net_device *netdev)
5751 {
5752 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5753 int i;
5754
5755 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5756 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5757 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5758 for (i = 0; i < num_q_vectors; i++) {
5759 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5760 ixgbe_msix_clean_many(0, q_vector);
5761 }
5762 } else {
5763 ixgbe_intr(adapter->pdev->irq, netdev);
5764 }
5765 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5766 }
5767 #endif
5768
5769 static const struct net_device_ops ixgbe_netdev_ops = {
5770 .ndo_open = ixgbe_open,
5771 .ndo_stop = ixgbe_close,
5772 .ndo_start_xmit = ixgbe_xmit_frame,
5773 .ndo_select_queue = ixgbe_select_queue,
5774 .ndo_set_rx_mode = ixgbe_set_rx_mode,
5775 .ndo_set_multicast_list = ixgbe_set_rx_mode,
5776 .ndo_validate_addr = eth_validate_addr,
5777 .ndo_set_mac_address = ixgbe_set_mac,
5778 .ndo_change_mtu = ixgbe_change_mtu,
5779 .ndo_tx_timeout = ixgbe_tx_timeout,
5780 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
5781 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
5782 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
5783 .ndo_do_ioctl = ixgbe_ioctl,
5784 #ifdef CONFIG_NET_POLL_CONTROLLER
5785 .ndo_poll_controller = ixgbe_netpoll,
5786 #endif
5787 #ifdef IXGBE_FCOE
5788 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5789 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5790 .ndo_fcoe_enable = ixgbe_fcoe_enable,
5791 .ndo_fcoe_disable = ixgbe_fcoe_disable,
5792 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
5793 #endif /* IXGBE_FCOE */
5794 };
5795
5796 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
5797 const struct ixgbe_info *ii)
5798 {
5799 #ifdef CONFIG_PCI_IOV
5800 struct ixgbe_hw *hw = &adapter->hw;
5801 int err;
5802
5803 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
5804 return;
5805
5806 /* The 82599 supports up to 64 VFs per physical function
5807 * but this implementation limits allocation to 63 so that
5808 * basic networking resources are still available to the
5809 * physical function
5810 */
5811 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
5812 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
5813 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
5814 if (err) {
5815 DPRINTK(PROBE, ERR,
5816 "Failed to enable PCI sriov: %d\n", err);
5817 goto err_novfs;
5818 }
5819 /* If call to enable VFs succeeded then allocate memory
5820 * for per VF control structures.
5821 */
5822 adapter->vfinfo =
5823 kcalloc(adapter->num_vfs,
5824 sizeof(struct vf_data_storage), GFP_KERNEL);
5825 if (adapter->vfinfo) {
5826 /* Now that we're sure SR-IOV is enabled
5827 * and memory allocated set up the mailbox parameters
5828 */
5829 ixgbe_init_mbx_params_pf(hw);
5830 memcpy(&hw->mbx.ops, ii->mbx_ops,
5831 sizeof(hw->mbx.ops));
5832
5833 /* Disable RSC when in SR-IOV mode */
5834 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
5835 IXGBE_FLAG2_RSC_ENABLED);
5836 return;
5837 }
5838
5839 /* Oh oh */
5840 DPRINTK(PROBE, ERR,
5841 "Unable to allocate memory for VF "
5842 "Data Storage - SRIOV disabled\n");
5843 pci_disable_sriov(adapter->pdev);
5844
5845 err_novfs:
5846 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
5847 adapter->num_vfs = 0;
5848 #endif /* CONFIG_PCI_IOV */
5849 }
5850
5851 /**
5852 * ixgbe_probe - Device Initialization Routine
5853 * @pdev: PCI device information struct
5854 * @ent: entry in ixgbe_pci_tbl
5855 *
5856 * Returns 0 on success, negative on failure
5857 *
5858 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5859 * The OS initialization, configuring of the adapter private structure,
5860 * and a hardware reset occur.
5861 **/
5862 static int __devinit ixgbe_probe(struct pci_dev *pdev,
5863 const struct pci_device_id *ent)
5864 {
5865 struct net_device *netdev;
5866 struct ixgbe_adapter *adapter = NULL;
5867 struct ixgbe_hw *hw;
5868 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
5869 static int cards_found;
5870 int i, err, pci_using_dac;
5871 #ifdef IXGBE_FCOE
5872 u16 device_caps;
5873 #endif
5874 u32 part_num, eec;
5875
5876 err = pci_enable_device_mem(pdev);
5877 if (err)
5878 return err;
5879
5880 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5881 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
5882 pci_using_dac = 1;
5883 } else {
5884 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5885 if (err) {
5886 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5887 if (err) {
5888 dev_err(&pdev->dev, "No usable DMA "
5889 "configuration, aborting\n");
5890 goto err_dma;
5891 }
5892 }
5893 pci_using_dac = 0;
5894 }
5895
5896 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5897 IORESOURCE_MEM), ixgbe_driver_name);
5898 if (err) {
5899 dev_err(&pdev->dev,
5900 "pci_request_selected_regions failed 0x%x\n", err);
5901 goto err_pci_reg;
5902 }
5903
5904 pci_enable_pcie_error_reporting(pdev);
5905
5906 pci_set_master(pdev);
5907 pci_save_state(pdev);
5908
5909 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
5910 if (!netdev) {
5911 err = -ENOMEM;
5912 goto err_alloc_etherdev;
5913 }
5914
5915 SET_NETDEV_DEV(netdev, &pdev->dev);
5916
5917 pci_set_drvdata(pdev, netdev);
5918 adapter = netdev_priv(netdev);
5919
5920 adapter->netdev = netdev;
5921 adapter->pdev = pdev;
5922 hw = &adapter->hw;
5923 hw->back = adapter;
5924 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5925
5926 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5927 pci_resource_len(pdev, 0));
5928 if (!hw->hw_addr) {
5929 err = -EIO;
5930 goto err_ioremap;
5931 }
5932
5933 for (i = 1; i <= 5; i++) {
5934 if (pci_resource_len(pdev, i) == 0)
5935 continue;
5936 }
5937
5938 netdev->netdev_ops = &ixgbe_netdev_ops;
5939 ixgbe_set_ethtool_ops(netdev);
5940 netdev->watchdog_timeo = 5 * HZ;
5941 strcpy(netdev->name, pci_name(pdev));
5942
5943 adapter->bd_number = cards_found;
5944
5945 /* Setup hw api */
5946 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
5947 hw->mac.type = ii->mac;
5948
5949 /* EEPROM */
5950 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5951 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5952 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5953 if (!(eec & (1 << 8)))
5954 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5955
5956 /* PHY */
5957 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
5958 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
5959 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5960 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5961 hw->phy.mdio.mmds = 0;
5962 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5963 hw->phy.mdio.dev = netdev;
5964 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5965 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
5966
5967 /* set up this timer and work struct before calling get_invariants
5968 * which might start the timer
5969 */
5970 init_timer(&adapter->sfp_timer);
5971 adapter->sfp_timer.function = &ixgbe_sfp_timer;
5972 adapter->sfp_timer.data = (unsigned long) adapter;
5973
5974 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
5975
5976 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5977 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5978
5979 /* a new SFP+ module arrival, called from GPI SDP2 context */
5980 INIT_WORK(&adapter->sfp_config_module_task,
5981 ixgbe_sfp_config_module_task);
5982
5983 ii->get_invariants(hw);
5984
5985 /* setup the private structure */
5986 err = ixgbe_sw_init(adapter);
5987 if (err)
5988 goto err_sw_init;
5989
5990 /*
5991 * If there is a fan on this device and it has failed log the
5992 * failure.
5993 */
5994 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5995 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5996 if (esdp & IXGBE_ESDP_SDP1)
5997 DPRINTK(PROBE, CRIT,
5998 "Fan has stopped, replace the adapter\n");
5999 }
6000
6001 /* reset_hw fills in the perm_addr as well */
6002 err = hw->mac.ops.reset_hw(hw);
6003 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6004 hw->mac.type == ixgbe_mac_82598EB) {
6005 /*
6006 * Start a kernel thread to watch for a module to arrive.
6007 * Only do this for 82598, since 82599 will generate
6008 * interrupts on module arrival.
6009 */
6010 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6011 mod_timer(&adapter->sfp_timer,
6012 round_jiffies(jiffies + (2 * HZ)));
6013 err = 0;
6014 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6015 dev_err(&adapter->pdev->dev, "failed to initialize because "
6016 "an unsupported SFP+ module type was detected.\n"
6017 "Reload the driver after installing a supported "
6018 "module.\n");
6019 goto err_sw_init;
6020 } else if (err) {
6021 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
6022 goto err_sw_init;
6023 }
6024
6025 ixgbe_probe_vf(adapter, ii);
6026
6027 netdev->features = NETIF_F_SG |
6028 NETIF_F_IP_CSUM |
6029 NETIF_F_HW_VLAN_TX |
6030 NETIF_F_HW_VLAN_RX |
6031 NETIF_F_HW_VLAN_FILTER;
6032
6033 netdev->features |= NETIF_F_IPV6_CSUM;
6034 netdev->features |= NETIF_F_TSO;
6035 netdev->features |= NETIF_F_TSO6;
6036 netdev->features |= NETIF_F_GRO;
6037
6038 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6039 netdev->features |= NETIF_F_SCTP_CSUM;
6040
6041 netdev->vlan_features |= NETIF_F_TSO;
6042 netdev->vlan_features |= NETIF_F_TSO6;
6043 netdev->vlan_features |= NETIF_F_IP_CSUM;
6044 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
6045 netdev->vlan_features |= NETIF_F_SG;
6046
6047 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6048 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6049 IXGBE_FLAG_DCB_ENABLED);
6050 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6051 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6052
6053 #ifdef CONFIG_IXGBE_DCB
6054 netdev->dcbnl_ops = &dcbnl_ops;
6055 #endif
6056
6057 #ifdef IXGBE_FCOE
6058 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6059 if (hw->mac.ops.get_device_caps) {
6060 hw->mac.ops.get_device_caps(hw, &device_caps);
6061 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6062 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6063 }
6064 }
6065 #endif /* IXGBE_FCOE */
6066 if (pci_using_dac)
6067 netdev->features |= NETIF_F_HIGHDMA;
6068
6069 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6070 netdev->features |= NETIF_F_LRO;
6071
6072 /* make sure the EEPROM is good */
6073 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
6074 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
6075 err = -EIO;
6076 goto err_eeprom;
6077 }
6078
6079 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6080 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6081
6082 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6083 dev_err(&pdev->dev, "invalid MAC address\n");
6084 err = -EIO;
6085 goto err_eeprom;
6086 }
6087
6088 init_timer(&adapter->watchdog_timer);
6089 adapter->watchdog_timer.function = &ixgbe_watchdog;
6090 adapter->watchdog_timer.data = (unsigned long)adapter;
6091
6092 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
6093 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
6094
6095 err = ixgbe_init_interrupt_scheme(adapter);
6096 if (err)
6097 goto err_sw_init;
6098
6099 switch (pdev->device) {
6100 case IXGBE_DEV_ID_82599_KX4:
6101 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6102 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
6103 /* Enable ACPI wakeup in GRC */
6104 IXGBE_WRITE_REG(hw, IXGBE_GRC,
6105 (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
6106 break;
6107 default:
6108 adapter->wol = 0;
6109 break;
6110 }
6111 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6112
6113 /* pick up the PCI bus settings for reporting later */
6114 hw->mac.ops.get_bus_info(hw);
6115
6116 /* print bus type/speed/width info */
6117 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
6118 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
6119 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
6120 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
6121 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
6122 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
6123 "Unknown"),
6124 netdev->dev_addr);
6125 ixgbe_read_pba_num_generic(hw, &part_num);
6126 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
6127 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
6128 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6129 (part_num >> 8), (part_num & 0xff));
6130 else
6131 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6132 hw->mac.type, hw->phy.type,
6133 (part_num >> 8), (part_num & 0xff));
6134
6135 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
6136 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
6137 "this card is not sufficient for optimal "
6138 "performance.\n");
6139 dev_warn(&pdev->dev, "For optimal performance a x8 "
6140 "PCI-Express slot is required.\n");
6141 }
6142
6143 /* save off EEPROM version number */
6144 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6145
6146 /* reset the hardware with the new settings */
6147 err = hw->mac.ops.start_hw(hw);
6148
6149 if (err == IXGBE_ERR_EEPROM_VERSION) {
6150 /* We are running on a pre-production device, log a warning */
6151 dev_warn(&pdev->dev, "This device is a pre-production "
6152 "adapter/LOM. Please be aware there may be issues "
6153 "associated with your hardware. If you are "
6154 "experiencing problems please contact your Intel or "
6155 "hardware representative who provided you with this "
6156 "hardware.\n");
6157 }
6158 strcpy(netdev->name, "eth%d");
6159 err = register_netdev(netdev);
6160 if (err)
6161 goto err_register;
6162
6163 /* carrier off reporting is important to ethtool even BEFORE open */
6164 netif_carrier_off(netdev);
6165
6166 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6167 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6168 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6169
6170 #ifdef CONFIG_IXGBE_DCA
6171 if (dca_add_requester(&pdev->dev) == 0) {
6172 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
6173 ixgbe_setup_dca(adapter);
6174 }
6175 #endif
6176 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6177 DPRINTK(PROBE, INFO, "IOV is enabled with %d VFs\n",
6178 adapter->num_vfs);
6179 for (i = 0; i < adapter->num_vfs; i++)
6180 ixgbe_vf_configuration(pdev, (i | 0x10000000));
6181 }
6182
6183 /* add san mac addr to netdev */
6184 ixgbe_add_sanmac_netdev(netdev);
6185
6186 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
6187 cards_found++;
6188 return 0;
6189
6190 err_register:
6191 ixgbe_release_hw_control(adapter);
6192 ixgbe_clear_interrupt_scheme(adapter);
6193 err_sw_init:
6194 err_eeprom:
6195 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6196 ixgbe_disable_sriov(adapter);
6197 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6198 del_timer_sync(&adapter->sfp_timer);
6199 cancel_work_sync(&adapter->sfp_task);
6200 cancel_work_sync(&adapter->multispeed_fiber_task);
6201 cancel_work_sync(&adapter->sfp_config_module_task);
6202 iounmap(hw->hw_addr);
6203 err_ioremap:
6204 free_netdev(netdev);
6205 err_alloc_etherdev:
6206 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6207 IORESOURCE_MEM));
6208 err_pci_reg:
6209 err_dma:
6210 pci_disable_device(pdev);
6211 return err;
6212 }
6213
6214 /**
6215 * ixgbe_remove - Device Removal Routine
6216 * @pdev: PCI device information struct
6217 *
6218 * ixgbe_remove is called by the PCI subsystem to alert the driver
6219 * that it should release a PCI device. The could be caused by a
6220 * Hot-Plug event, or because the driver is going to be removed from
6221 * memory.
6222 **/
6223 static void __devexit ixgbe_remove(struct pci_dev *pdev)
6224 {
6225 struct net_device *netdev = pci_get_drvdata(pdev);
6226 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6227
6228 set_bit(__IXGBE_DOWN, &adapter->state);
6229 /* clear the module not found bit to make sure the worker won't
6230 * reschedule
6231 */
6232 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6233 del_timer_sync(&adapter->watchdog_timer);
6234
6235 del_timer_sync(&adapter->sfp_timer);
6236 cancel_work_sync(&adapter->watchdog_task);
6237 cancel_work_sync(&adapter->sfp_task);
6238 cancel_work_sync(&adapter->multispeed_fiber_task);
6239 cancel_work_sync(&adapter->sfp_config_module_task);
6240 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6241 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6242 cancel_work_sync(&adapter->fdir_reinit_task);
6243 flush_scheduled_work();
6244
6245 #ifdef CONFIG_IXGBE_DCA
6246 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
6247 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
6248 dca_remove_requester(&pdev->dev);
6249 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
6250 }
6251
6252 #endif
6253 #ifdef IXGBE_FCOE
6254 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6255 ixgbe_cleanup_fcoe(adapter);
6256
6257 #endif /* IXGBE_FCOE */
6258
6259 /* remove the added san mac */
6260 ixgbe_del_sanmac_netdev(netdev);
6261
6262 if (netdev->reg_state == NETREG_REGISTERED)
6263 unregister_netdev(netdev);
6264
6265 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6266 ixgbe_disable_sriov(adapter);
6267
6268 ixgbe_clear_interrupt_scheme(adapter);
6269
6270 ixgbe_release_hw_control(adapter);
6271
6272 iounmap(adapter->hw.hw_addr);
6273 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6274 IORESOURCE_MEM));
6275
6276 DPRINTK(PROBE, INFO, "complete\n");
6277
6278 free_netdev(netdev);
6279
6280 pci_disable_pcie_error_reporting(pdev);
6281
6282 pci_disable_device(pdev);
6283 }
6284
6285 /**
6286 * ixgbe_io_error_detected - called when PCI error is detected
6287 * @pdev: Pointer to PCI device
6288 * @state: The current pci connection state
6289 *
6290 * This function is called after a PCI bus error affecting
6291 * this device has been detected.
6292 */
6293 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
6294 pci_channel_state_t state)
6295 {
6296 struct net_device *netdev = pci_get_drvdata(pdev);
6297 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6298
6299 netif_device_detach(netdev);
6300
6301 if (state == pci_channel_io_perm_failure)
6302 return PCI_ERS_RESULT_DISCONNECT;
6303
6304 if (netif_running(netdev))
6305 ixgbe_down(adapter);
6306 pci_disable_device(pdev);
6307
6308 /* Request a slot reset. */
6309 return PCI_ERS_RESULT_NEED_RESET;
6310 }
6311
6312 /**
6313 * ixgbe_io_slot_reset - called after the pci bus has been reset.
6314 * @pdev: Pointer to PCI device
6315 *
6316 * Restart the card from scratch, as if from a cold-boot.
6317 */
6318 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
6319 {
6320 struct net_device *netdev = pci_get_drvdata(pdev);
6321 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6322 pci_ers_result_t result;
6323 int err;
6324
6325 if (pci_enable_device_mem(pdev)) {
6326 DPRINTK(PROBE, ERR,
6327 "Cannot re-enable PCI device after reset.\n");
6328 result = PCI_ERS_RESULT_DISCONNECT;
6329 } else {
6330 pci_set_master(pdev);
6331 pci_restore_state(pdev);
6332 pci_save_state(pdev);
6333
6334 pci_wake_from_d3(pdev, false);
6335
6336 ixgbe_reset(adapter);
6337 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6338 result = PCI_ERS_RESULT_RECOVERED;
6339 }
6340
6341 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6342 if (err) {
6343 dev_err(&pdev->dev,
6344 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
6345 /* non-fatal, continue */
6346 }
6347
6348 return result;
6349 }
6350
6351 /**
6352 * ixgbe_io_resume - called when traffic can start flowing again.
6353 * @pdev: Pointer to PCI device
6354 *
6355 * This callback is called when the error recovery driver tells us that
6356 * its OK to resume normal operation.
6357 */
6358 static void ixgbe_io_resume(struct pci_dev *pdev)
6359 {
6360 struct net_device *netdev = pci_get_drvdata(pdev);
6361 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6362
6363 if (netif_running(netdev)) {
6364 if (ixgbe_up(adapter)) {
6365 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
6366 return;
6367 }
6368 }
6369
6370 netif_device_attach(netdev);
6371 }
6372
6373 static struct pci_error_handlers ixgbe_err_handler = {
6374 .error_detected = ixgbe_io_error_detected,
6375 .slot_reset = ixgbe_io_slot_reset,
6376 .resume = ixgbe_io_resume,
6377 };
6378
6379 static struct pci_driver ixgbe_driver = {
6380 .name = ixgbe_driver_name,
6381 .id_table = ixgbe_pci_tbl,
6382 .probe = ixgbe_probe,
6383 .remove = __devexit_p(ixgbe_remove),
6384 #ifdef CONFIG_PM
6385 .suspend = ixgbe_suspend,
6386 .resume = ixgbe_resume,
6387 #endif
6388 .shutdown = ixgbe_shutdown,
6389 .err_handler = &ixgbe_err_handler
6390 };
6391
6392 /**
6393 * ixgbe_init_module - Driver Registration Routine
6394 *
6395 * ixgbe_init_module is the first routine called when the driver is
6396 * loaded. All it does is register with the PCI subsystem.
6397 **/
6398 static int __init ixgbe_init_module(void)
6399 {
6400 int ret;
6401 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
6402 ixgbe_driver_string, ixgbe_driver_version);
6403
6404 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
6405
6406 #ifdef CONFIG_IXGBE_DCA
6407 dca_register_notify(&dca_notifier);
6408 #endif
6409
6410 ret = pci_register_driver(&ixgbe_driver);
6411 return ret;
6412 }
6413
6414 module_init(ixgbe_init_module);
6415
6416 /**
6417 * ixgbe_exit_module - Driver Exit Cleanup Routine
6418 *
6419 * ixgbe_exit_module is called just before the driver is removed
6420 * from memory.
6421 **/
6422 static void __exit ixgbe_exit_module(void)
6423 {
6424 #ifdef CONFIG_IXGBE_DCA
6425 dca_unregister_notify(&dca_notifier);
6426 #endif
6427 pci_unregister_driver(&ixgbe_driver);
6428 }
6429
6430 #ifdef CONFIG_IXGBE_DCA
6431 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
6432 void *p)
6433 {
6434 int ret_val;
6435
6436 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
6437 __ixgbe_notify_dca);
6438
6439 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6440 }
6441
6442 #endif /* CONFIG_IXGBE_DCA */
6443 #ifdef DEBUG
6444 /**
6445 * ixgbe_get_hw_dev_name - return device name string
6446 * used by hardware layer to print debugging information
6447 **/
6448 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6449 {
6450 struct ixgbe_adapter *adapter = hw->back;
6451 return adapter->netdev->name;
6452 }
6453
6454 #endif
6455 module_exit(ixgbe_exit_module);
6456
6457 /* ixgbe_main.c */
Linux kernel - Deliverables
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