1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <linux/slab.h>
40 #include <net/checksum.h>
41 #include <net/ip6_checksum.h>
42 #include <linux/ethtool.h>
43 #include <linux/if_vlan.h>
44 #include <scsi/fc/fc_fcoe.h>
47 #include "ixgbe_common.h"
48 #include "ixgbe_dcb_82599.h"
49 #include "ixgbe_sriov.h"
51 char ixgbe_driver_name
[] = "ixgbe";
52 static const char ixgbe_driver_string
[] =
53 "Intel(R) 10 Gigabit PCI Express Network Driver";
55 #define DRV_VERSION "2.0.84-k2"
56 const char ixgbe_driver_version
[] = DRV_VERSION
;
57 static char ixgbe_copyright
[] = "Copyright (c) 1999-2010 Intel Corporation.";
59 static const struct ixgbe_info
*ixgbe_info_tbl
[] = {
60 [board_82598
] = &ixgbe_82598_info
,
61 [board_82599
] = &ixgbe_82599_info
,
64 /* ixgbe_pci_tbl - PCI Device ID Table
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl
) = {
73 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598
),
75 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_DUAL_PORT
),
77 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_SINGLE_PORT
),
79 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT
),
81 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT2
),
83 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_CX4
),
85 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_CX4_DUAL_PORT
),
87 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_DA_DUAL_PORT
),
89 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM
),
91 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_XF_LR
),
93 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_SFP_LOM
),
95 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_BX
),
97 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4
),
99 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_XAUI_LOM
),
101 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KR
),
103 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP
),
105 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP_EM
),
107 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4_MEZZ
),
109 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_CX4
),
111 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_T3_LOM
),
113 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_COMBO_BACKPLANE
),
116 /* required last entry */
119 MODULE_DEVICE_TABLE(pci
, ixgbe_pci_tbl
);
121 #ifdef CONFIG_IXGBE_DCA
122 static int ixgbe_notify_dca(struct notifier_block
*, unsigned long event
,
124 static struct notifier_block dca_notifier
= {
125 .notifier_call
= ixgbe_notify_dca
,
131 #ifdef CONFIG_PCI_IOV
132 static unsigned int max_vfs
;
133 module_param(max_vfs
, uint
, 0);
134 MODULE_PARM_DESC(max_vfs
,
135 "Maximum number of virtual functions to allocate per physical function");
136 #endif /* CONFIG_PCI_IOV */
138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
140 MODULE_LICENSE("GPL");
141 MODULE_VERSION(DRV_VERSION
);
143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter
*adapter
)
147 struct ixgbe_hw
*hw
= &adapter
->hw
;
152 #ifdef CONFIG_PCI_IOV
153 /* disable iov and allow time for transactions to clear */
154 pci_disable_sriov(adapter
->pdev
);
157 /* turn off device IOV mode */
158 gcr
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
159 gcr
&= ~(IXGBE_GCR_EXT_SRIOV
);
160 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, gcr
);
161 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
162 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
163 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
165 /* set default pool back to 0 */
166 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
167 vmdctl
&= ~IXGBE_VT_CTL_POOL_MASK
;
168 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
);
170 /* take a breather then clean up driver data */
173 kfree(adapter
->vfinfo
);
174 adapter
->vfinfo
= NULL
;
176 adapter
->num_vfs
= 0;
177 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
180 struct ixgbe_reg_info
{
185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl
[] = {
187 /* General Registers */
188 {IXGBE_CTRL
, "CTRL"},
189 {IXGBE_STATUS
, "STATUS"},
190 {IXGBE_CTRL_EXT
, "CTRL_EXT"},
192 /* Interrupt Registers */
193 {IXGBE_EICR
, "EICR"},
196 {IXGBE_SRRCTL(0), "SRRCTL"},
197 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
198 {IXGBE_RDLEN(0), "RDLEN"},
199 {IXGBE_RDH(0), "RDH"},
200 {IXGBE_RDT(0), "RDT"},
201 {IXGBE_RXDCTL(0), "RXDCTL"},
202 {IXGBE_RDBAL(0), "RDBAL"},
203 {IXGBE_RDBAH(0), "RDBAH"},
206 {IXGBE_TDBAL(0), "TDBAL"},
207 {IXGBE_TDBAH(0), "TDBAH"},
208 {IXGBE_TDLEN(0), "TDLEN"},
209 {IXGBE_TDH(0), "TDH"},
210 {IXGBE_TDT(0), "TDT"},
211 {IXGBE_TXDCTL(0), "TXDCTL"},
213 /* List Terminator */
219 * ixgbe_regdump - register printout routine
221 static void ixgbe_regdump(struct ixgbe_hw
*hw
, struct ixgbe_reg_info
*reginfo
)
227 switch (reginfo
->ofs
) {
228 case IXGBE_SRRCTL(0):
229 for (i
= 0; i
< 64; i
++)
230 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_SRRCTL(i
));
232 case IXGBE_DCA_RXCTRL(0):
233 for (i
= 0; i
< 64; i
++)
234 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_DCA_RXCTRL(i
));
237 for (i
= 0; i
< 64; i
++)
238 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDLEN(i
));
241 for (i
= 0; i
< 64; i
++)
242 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDH(i
));
245 for (i
= 0; i
< 64; i
++)
246 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDT(i
));
248 case IXGBE_RXDCTL(0):
249 for (i
= 0; i
< 64; i
++)
250 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RXDCTL(i
));
253 for (i
= 0; i
< 64; i
++)
254 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDBAL(i
));
257 for (i
= 0; i
< 64; i
++)
258 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDBAH(i
));
261 for (i
= 0; i
< 64; i
++)
262 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDBAL(i
));
265 for (i
= 0; i
< 64; i
++)
266 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDBAH(i
));
269 for (i
= 0; i
< 64; i
++)
270 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDLEN(i
));
273 for (i
= 0; i
< 64; i
++)
274 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDH(i
));
277 for (i
= 0; i
< 64; i
++)
278 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDT(i
));
280 case IXGBE_TXDCTL(0):
281 for (i
= 0; i
< 64; i
++)
282 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TXDCTL(i
));
285 pr_info("%-15s %08x\n", reginfo
->name
,
286 IXGBE_READ_REG(hw
, reginfo
->ofs
));
290 for (i
= 0; i
< 8; i
++) {
291 snprintf(rname
, 16, "%s[%d-%d]", reginfo
->name
, i
*8, i
*8+7);
292 pr_err("%-15s", rname
);
293 for (j
= 0; j
< 8; j
++)
294 pr_cont(" %08x", regs
[i
*8+j
]);
301 * ixgbe_dump - Print registers, tx-rings and rx-rings
303 static void ixgbe_dump(struct ixgbe_adapter
*adapter
)
305 struct net_device
*netdev
= adapter
->netdev
;
306 struct ixgbe_hw
*hw
= &adapter
->hw
;
307 struct ixgbe_reg_info
*reginfo
;
309 struct ixgbe_ring
*tx_ring
;
310 struct ixgbe_tx_buffer
*tx_buffer_info
;
311 union ixgbe_adv_tx_desc
*tx_desc
;
312 struct my_u0
{ u64 a
; u64 b
; } *u0
;
313 struct ixgbe_ring
*rx_ring
;
314 union ixgbe_adv_rx_desc
*rx_desc
;
315 struct ixgbe_rx_buffer
*rx_buffer_info
;
319 if (!netif_msg_hw(adapter
))
322 /* Print netdevice Info */
324 dev_info(&adapter
->pdev
->dev
, "Net device Info\n");
325 pr_info("Device Name state "
326 "trans_start last_rx\n");
327 pr_info("%-15s %016lX %016lX %016lX\n",
334 /* Print Registers */
335 dev_info(&adapter
->pdev
->dev
, "Register Dump\n");
336 pr_info(" Register Name Value\n");
337 for (reginfo
= (struct ixgbe_reg_info
*)ixgbe_reg_info_tbl
;
338 reginfo
->name
; reginfo
++) {
339 ixgbe_regdump(hw
, reginfo
);
342 /* Print TX Ring Summary */
343 if (!netdev
|| !netif_running(netdev
))
346 dev_info(&adapter
->pdev
->dev
, "TX Rings Summary\n");
347 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
348 for (n
= 0; n
< adapter
->num_tx_queues
; n
++) {
349 tx_ring
= adapter
->tx_ring
[n
];
351 &tx_ring
->tx_buffer_info
[tx_ring
->next_to_clean
];
352 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
353 n
, tx_ring
->next_to_use
, tx_ring
->next_to_clean
,
354 (u64
)tx_buffer_info
->dma
,
355 tx_buffer_info
->length
,
356 tx_buffer_info
->next_to_watch
,
357 (u64
)tx_buffer_info
->time_stamp
);
361 if (!netif_msg_tx_done(adapter
))
362 goto rx_ring_summary
;
364 dev_info(&adapter
->pdev
->dev
, "TX Rings Dump\n");
366 /* Transmit Descriptor Formats
368 * Advanced Transmit Descriptor
369 * +--------------------------------------------------------------+
370 * 0 | Buffer Address [63:0] |
371 * +--------------------------------------------------------------+
372 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
373 * +--------------------------------------------------------------+
374 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
377 for (n
= 0; n
< adapter
->num_tx_queues
; n
++) {
378 tx_ring
= adapter
->tx_ring
[n
];
379 pr_info("------------------------------------\n");
380 pr_info("TX QUEUE INDEX = %d\n", tx_ring
->queue_index
);
381 pr_info("------------------------------------\n");
382 pr_info("T [desc] [address 63:0 ] "
383 "[PlPOIdStDDt Ln] [bi->dma ] "
384 "leng ntw timestamp bi->skb\n");
386 for (i
= 0; tx_ring
->desc
&& (i
< tx_ring
->count
); i
++) {
387 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, i
);
388 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
389 u0
= (struct my_u0
*)tx_desc
;
390 pr_info("T [0x%03X] %016llX %016llX %016llX"
391 " %04X %3X %016llX %p", i
,
394 (u64
)tx_buffer_info
->dma
,
395 tx_buffer_info
->length
,
396 tx_buffer_info
->next_to_watch
,
397 (u64
)tx_buffer_info
->time_stamp
,
398 tx_buffer_info
->skb
);
399 if (i
== tx_ring
->next_to_use
&&
400 i
== tx_ring
->next_to_clean
)
402 else if (i
== tx_ring
->next_to_use
)
404 else if (i
== tx_ring
->next_to_clean
)
409 if (netif_msg_pktdata(adapter
) &&
410 tx_buffer_info
->dma
!= 0)
411 print_hex_dump(KERN_INFO
, "",
412 DUMP_PREFIX_ADDRESS
, 16, 1,
413 phys_to_virt(tx_buffer_info
->dma
),
414 tx_buffer_info
->length
, true);
418 /* Print RX Rings Summary */
420 dev_info(&adapter
->pdev
->dev
, "RX Rings Summary\n");
421 pr_info("Queue [NTU] [NTC]\n");
422 for (n
= 0; n
< adapter
->num_rx_queues
; n
++) {
423 rx_ring
= adapter
->rx_ring
[n
];
424 pr_info("%5d %5X %5X\n",
425 n
, rx_ring
->next_to_use
, rx_ring
->next_to_clean
);
429 if (!netif_msg_rx_status(adapter
))
432 dev_info(&adapter
->pdev
->dev
, "RX Rings Dump\n");
434 /* Advanced Receive Descriptor (Read) Format
436 * +-----------------------------------------------------+
437 * 0 | Packet Buffer Address [63:1] |A0/NSE|
438 * +----------------------------------------------+------+
439 * 8 | Header Buffer Address [63:1] | DD |
440 * +-----------------------------------------------------+
443 * Advanced Receive Descriptor (Write-Back) Format
445 * 63 48 47 32 31 30 21 20 16 15 4 3 0
446 * +------------------------------------------------------+
447 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
448 * | Checksum Ident | | | | Type | Type |
449 * +------------------------------------------------------+
450 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
451 * +------------------------------------------------------+
452 * 63 48 47 32 31 20 19 0
454 for (n
= 0; n
< adapter
->num_rx_queues
; n
++) {
455 rx_ring
= adapter
->rx_ring
[n
];
456 pr_info("------------------------------------\n");
457 pr_info("RX QUEUE INDEX = %d\n", rx_ring
->queue_index
);
458 pr_info("------------------------------------\n");
459 pr_info("R [desc] [ PktBuf A0] "
460 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
461 "<-- Adv Rx Read format\n");
462 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
463 "[vl er S cks ln] ---------------- [bi->skb] "
464 "<-- Adv Rx Write-Back format\n");
466 for (i
= 0; i
< rx_ring
->count
; i
++) {
467 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
468 rx_desc
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
469 u0
= (struct my_u0
*)rx_desc
;
470 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
471 if (staterr
& IXGBE_RXD_STAT_DD
) {
472 /* Descriptor Done */
473 pr_info("RWB[0x%03X] %016llX "
474 "%016llX ---------------- %p", i
,
477 rx_buffer_info
->skb
);
479 pr_info("R [0x%03X] %016llX "
480 "%016llX %016llX %p", i
,
483 (u64
)rx_buffer_info
->dma
,
484 rx_buffer_info
->skb
);
486 if (netif_msg_pktdata(adapter
)) {
487 print_hex_dump(KERN_INFO
, "",
488 DUMP_PREFIX_ADDRESS
, 16, 1,
489 phys_to_virt(rx_buffer_info
->dma
),
490 rx_ring
->rx_buf_len
, true);
492 if (rx_ring
->rx_buf_len
493 < IXGBE_RXBUFFER_2048
)
494 print_hex_dump(KERN_INFO
, "",
495 DUMP_PREFIX_ADDRESS
, 16, 1,
497 rx_buffer_info
->page_dma
+
498 rx_buffer_info
->page_offset
504 if (i
== rx_ring
->next_to_use
)
506 else if (i
== rx_ring
->next_to_clean
)
518 static void ixgbe_release_hw_control(struct ixgbe_adapter
*adapter
)
522 /* Let firmware take over control of h/w */
523 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
524 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
525 ctrl_ext
& ~IXGBE_CTRL_EXT_DRV_LOAD
);
528 static void ixgbe_get_hw_control(struct ixgbe_adapter
*adapter
)
532 /* Let firmware know the driver has taken over */
533 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
534 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
535 ctrl_ext
| IXGBE_CTRL_EXT_DRV_LOAD
);
539 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
540 * @adapter: pointer to adapter struct
541 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
542 * @queue: queue to map the corresponding interrupt to
543 * @msix_vector: the vector to map to the corresponding queue
546 static void ixgbe_set_ivar(struct ixgbe_adapter
*adapter
, s8 direction
,
547 u8 queue
, u8 msix_vector
)
550 struct ixgbe_hw
*hw
= &adapter
->hw
;
551 switch (hw
->mac
.type
) {
552 case ixgbe_mac_82598EB
:
553 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
556 index
= (((direction
* 64) + queue
) >> 2) & 0x1F;
557 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(index
));
558 ivar
&= ~(0xFF << (8 * (queue
& 0x3)));
559 ivar
|= (msix_vector
<< (8 * (queue
& 0x3)));
560 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(index
), ivar
);
562 case ixgbe_mac_82599EB
:
563 if (direction
== -1) {
565 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
566 index
= ((queue
& 1) * 8);
567 ivar
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_IVAR_MISC
);
568 ivar
&= ~(0xFF << index
);
569 ivar
|= (msix_vector
<< index
);
570 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_IVAR_MISC
, ivar
);
573 /* tx or rx causes */
574 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
575 index
= ((16 * (queue
& 1)) + (8 * direction
));
576 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(queue
>> 1));
577 ivar
&= ~(0xFF << index
);
578 ivar
|= (msix_vector
<< index
);
579 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(queue
>> 1), ivar
);
587 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter
*adapter
,
592 switch (adapter
->hw
.mac
.type
) {
593 case ixgbe_mac_82598EB
:
594 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
595 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS
, mask
);
597 case ixgbe_mac_82599EB
:
598 mask
= (qmask
& 0xFFFFFFFF);
599 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(0), mask
);
600 mask
= (qmask
>> 32);
601 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(1), mask
);
608 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring
*tx_ring
,
609 struct ixgbe_tx_buffer
*tx_buffer_info
)
611 if (tx_buffer_info
->dma
) {
612 if (tx_buffer_info
->mapped_as_page
)
613 dma_unmap_page(tx_ring
->dev
,
615 tx_buffer_info
->length
,
618 dma_unmap_single(tx_ring
->dev
,
620 tx_buffer_info
->length
,
622 tx_buffer_info
->dma
= 0;
624 if (tx_buffer_info
->skb
) {
625 dev_kfree_skb_any(tx_buffer_info
->skb
);
626 tx_buffer_info
->skb
= NULL
;
628 tx_buffer_info
->time_stamp
= 0;
629 /* tx_buffer_info must be completely set up in the transmit path */
633 * ixgbe_tx_xon_state - check the tx ring xon state
634 * @adapter: the ixgbe adapter
635 * @tx_ring: the corresponding tx_ring
637 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
638 * corresponding TC of this tx_ring when checking TFCS.
640 * Returns : true if in xon state (currently not paused)
642 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter
*adapter
,
643 struct ixgbe_ring
*tx_ring
)
645 u32 txoff
= IXGBE_TFCS_TXOFF
;
647 #ifdef CONFIG_IXGBE_DCB
648 if (adapter
->dcb_cfg
.pfc_mode_enable
) {
650 int reg_idx
= tx_ring
->reg_idx
;
651 int dcb_i
= adapter
->ring_feature
[RING_F_DCB
].indices
;
653 switch (adapter
->hw
.mac
.type
) {
654 case ixgbe_mac_82598EB
:
656 txoff
= IXGBE_TFCS_TXOFF0
;
658 case ixgbe_mac_82599EB
:
660 txoff
= IXGBE_TFCS_TXOFF
;
664 if (tc
== 2) /* TC2, TC3 */
665 tc
+= (reg_idx
- 64) >> 4;
666 else if (tc
== 3) /* TC4, TC5, TC6, TC7 */
667 tc
+= 1 + ((reg_idx
- 96) >> 3);
668 } else if (dcb_i
== 4) {
672 tc
+= (reg_idx
- 64) >> 5;
673 if (tc
== 2) /* TC2, TC3 */
674 tc
+= (reg_idx
- 96) >> 4;
685 return IXGBE_READ_REG(&adapter
->hw
, IXGBE_TFCS
) & txoff
;
688 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter
*adapter
,
689 struct ixgbe_ring
*tx_ring
,
692 struct ixgbe_hw
*hw
= &adapter
->hw
;
694 /* Detect a transmit hang in hardware, this serializes the
695 * check with the clearing of time_stamp and movement of eop */
696 clear_check_for_tx_hang(tx_ring
);
697 if (tx_ring
->tx_buffer_info
[eop
].time_stamp
&&
698 time_after(jiffies
, tx_ring
->tx_buffer_info
[eop
].time_stamp
+ HZ
) &&
699 ixgbe_tx_xon_state(adapter
, tx_ring
)) {
700 /* detected Tx unit hang */
701 union ixgbe_adv_tx_desc
*tx_desc
;
702 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, eop
);
703 e_err(drv
, "Detected Tx Unit Hang\n"
705 " TDH, TDT <%x>, <%x>\n"
706 " next_to_use <%x>\n"
707 " next_to_clean <%x>\n"
708 "tx_buffer_info[next_to_clean]\n"
709 " time_stamp <%lx>\n"
711 tx_ring
->queue_index
,
712 IXGBE_READ_REG(hw
, IXGBE_TDH(tx_ring
->reg_idx
)),
713 IXGBE_READ_REG(hw
, IXGBE_TDT(tx_ring
->reg_idx
)),
714 tx_ring
->next_to_use
, eop
,
715 tx_ring
->tx_buffer_info
[eop
].time_stamp
, jiffies
);
722 #define IXGBE_MAX_TXD_PWR 14
723 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
725 /* Tx Descriptors needed, worst case */
726 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
727 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
728 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
729 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
731 static void ixgbe_tx_timeout(struct net_device
*netdev
);
734 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
735 * @q_vector: structure containing interrupt and ring information
736 * @tx_ring: tx ring to clean
738 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector
*q_vector
,
739 struct ixgbe_ring
*tx_ring
)
741 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
742 union ixgbe_adv_tx_desc
*tx_desc
, *eop_desc
;
743 struct ixgbe_tx_buffer
*tx_buffer_info
;
744 unsigned int total_bytes
= 0, total_packets
= 0;
745 u16 i
, eop
, count
= 0;
747 i
= tx_ring
->next_to_clean
;
748 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
749 eop_desc
= IXGBE_TX_DESC_ADV(tx_ring
, eop
);
751 while ((eop_desc
->wb
.status
& cpu_to_le32(IXGBE_TXD_STAT_DD
)) &&
752 (count
< tx_ring
->work_limit
)) {
753 bool cleaned
= false;
754 rmb(); /* read buffer_info after eop_desc */
755 for ( ; !cleaned
; count
++) {
756 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, i
);
757 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
759 tx_desc
->wb
.status
= 0;
760 cleaned
= (i
== eop
);
763 if (i
== tx_ring
->count
)
766 if (cleaned
&& tx_buffer_info
->skb
) {
767 total_bytes
+= tx_buffer_info
->bytecount
;
768 total_packets
+= tx_buffer_info
->gso_segs
;
771 ixgbe_unmap_and_free_tx_resource(tx_ring
,
775 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
776 eop_desc
= IXGBE_TX_DESC_ADV(tx_ring
, eop
);
779 tx_ring
->next_to_clean
= i
;
780 tx_ring
->total_bytes
+= total_bytes
;
781 tx_ring
->total_packets
+= total_packets
;
782 u64_stats_update_begin(&tx_ring
->syncp
);
783 tx_ring
->stats
.packets
+= total_packets
;
784 tx_ring
->stats
.bytes
+= total_bytes
;
785 u64_stats_update_end(&tx_ring
->syncp
);
787 if (check_for_tx_hang(tx_ring
) &&
788 ixgbe_check_tx_hang(adapter
, tx_ring
, i
)) {
789 /* schedule immediate reset if we believe we hung */
790 e_info(probe
, "tx hang %d detected, resetting "
791 "adapter\n", adapter
->tx_timeout_count
+ 1);
792 ixgbe_tx_timeout(adapter
->netdev
);
794 /* the adapter is about to reset, no point in enabling stuff */
798 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
799 if (unlikely(count
&& netif_carrier_ok(tx_ring
->netdev
) &&
800 (IXGBE_DESC_UNUSED(tx_ring
) >= TX_WAKE_THRESHOLD
))) {
801 /* Make sure that anybody stopping the queue after this
802 * sees the new next_to_clean.
805 if (__netif_subqueue_stopped(tx_ring
->netdev
, tx_ring
->queue_index
) &&
806 !test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
807 netif_wake_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
808 ++tx_ring
->tx_stats
.restart_queue
;
812 return count
< tx_ring
->work_limit
;
815 #ifdef CONFIG_IXGBE_DCA
816 static void ixgbe_update_rx_dca(struct ixgbe_adapter
*adapter
,
817 struct ixgbe_ring
*rx_ring
,
820 struct ixgbe_hw
*hw
= &adapter
->hw
;
822 u8 reg_idx
= rx_ring
->reg_idx
;
824 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_RXCTRL(reg_idx
));
825 switch (hw
->mac
.type
) {
826 case ixgbe_mac_82598EB
:
827 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK
;
828 rxctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
830 case ixgbe_mac_82599EB
:
831 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599
;
832 rxctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
833 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599
);
838 rxctrl
|= IXGBE_DCA_RXCTRL_DESC_DCA_EN
;
839 rxctrl
|= IXGBE_DCA_RXCTRL_HEAD_DCA_EN
;
840 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN
);
841 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN
|
842 IXGBE_DCA_RXCTRL_DESC_HSRO_EN
);
843 IXGBE_WRITE_REG(hw
, IXGBE_DCA_RXCTRL(reg_idx
), rxctrl
);
846 static void ixgbe_update_tx_dca(struct ixgbe_adapter
*adapter
,
847 struct ixgbe_ring
*tx_ring
,
850 struct ixgbe_hw
*hw
= &adapter
->hw
;
852 u8 reg_idx
= tx_ring
->reg_idx
;
854 switch (hw
->mac
.type
) {
855 case ixgbe_mac_82598EB
:
856 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL(reg_idx
));
857 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK
;
858 txctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
859 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
860 txctrl
&= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN
;
861 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL(reg_idx
), txctrl
);
863 case ixgbe_mac_82599EB
:
864 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL_82599(reg_idx
));
865 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599
;
866 txctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
867 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599
);
868 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
869 txctrl
&= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN
;
870 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL_82599(reg_idx
), txctrl
);
877 static void ixgbe_update_dca(struct ixgbe_q_vector
*q_vector
)
879 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
884 if (q_vector
->cpu
== cpu
)
887 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
888 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
889 ixgbe_update_tx_dca(adapter
, adapter
->tx_ring
[r_idx
], cpu
);
890 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
894 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
895 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
896 ixgbe_update_rx_dca(adapter
, adapter
->rx_ring
[r_idx
], cpu
);
897 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
906 static void ixgbe_setup_dca(struct ixgbe_adapter
*adapter
)
911 if (!(adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
))
914 /* always use CB2 mode, difference is masked in the CB driver */
915 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 2);
917 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
918 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
922 for (i
= 0; i
< num_q_vectors
; i
++) {
923 adapter
->q_vector
[i
]->cpu
= -1;
924 ixgbe_update_dca(adapter
->q_vector
[i
]);
928 static int __ixgbe_notify_dca(struct device
*dev
, void *data
)
930 struct ixgbe_adapter
*adapter
= dev_get_drvdata(dev
);
931 unsigned long event
= *(unsigned long *)data
;
933 if (!(adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
))
937 case DCA_PROVIDER_ADD
:
938 /* if we're already enabled, don't do it again */
939 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
941 if (dca_add_requester(dev
) == 0) {
942 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
943 ixgbe_setup_dca(adapter
);
946 /* Fall Through since DCA is disabled. */
947 case DCA_PROVIDER_REMOVE
:
948 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
949 dca_remove_requester(dev
);
950 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
951 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
959 #endif /* CONFIG_IXGBE_DCA */
961 * ixgbe_receive_skb - Send a completed packet up the stack
962 * @adapter: board private structure
963 * @skb: packet to send up
964 * @status: hardware indication of status of receive
965 * @rx_ring: rx descriptor ring (for a specific queue) to setup
966 * @rx_desc: rx descriptor
968 static void ixgbe_receive_skb(struct ixgbe_q_vector
*q_vector
,
969 struct sk_buff
*skb
, u8 status
,
970 struct ixgbe_ring
*ring
,
971 union ixgbe_adv_rx_desc
*rx_desc
)
973 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
974 struct napi_struct
*napi
= &q_vector
->napi
;
975 bool is_vlan
= (status
& IXGBE_RXD_STAT_VP
);
976 u16 tag
= le16_to_cpu(rx_desc
->wb
.upper
.vlan
);
978 if (is_vlan
&& (tag
& VLAN_VID_MASK
))
979 __vlan_hwaccel_put_tag(skb
, tag
);
981 if (!(adapter
->flags
& IXGBE_FLAG_IN_NETPOLL
))
982 napi_gro_receive(napi
, skb
);
988 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
989 * @adapter: address of board private structure
990 * @status_err: hardware indication of status of receive
991 * @skb: skb currently being received and modified
993 static inline void ixgbe_rx_checksum(struct ixgbe_adapter
*adapter
,
994 union ixgbe_adv_rx_desc
*rx_desc
,
997 u32 status_err
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
999 skb_checksum_none_assert(skb
);
1001 /* Rx csum disabled */
1002 if (!(adapter
->flags
& IXGBE_FLAG_RX_CSUM_ENABLED
))
1005 /* if IP and error */
1006 if ((status_err
& IXGBE_RXD_STAT_IPCS
) &&
1007 (status_err
& IXGBE_RXDADV_ERR_IPE
)) {
1008 adapter
->hw_csum_rx_error
++;
1012 if (!(status_err
& IXGBE_RXD_STAT_L4CS
))
1015 if (status_err
& IXGBE_RXDADV_ERR_TCPE
) {
1016 u16 pkt_info
= rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
1019 * 82599 errata, UDP frames with a 0 checksum can be marked as
1022 if ((pkt_info
& IXGBE_RXDADV_PKTTYPE_UDP
) &&
1023 (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
))
1026 adapter
->hw_csum_rx_error
++;
1030 /* It must be a TCP or UDP packet with a valid checksum */
1031 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1034 static inline void ixgbe_release_rx_desc(struct ixgbe_ring
*rx_ring
, u32 val
)
1037 * Force memory writes to complete before letting h/w
1038 * know there are new descriptors to fetch. (Only
1039 * applicable for weak-ordered memory model archs,
1043 writel(val
, rx_ring
->tail
);
1047 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1048 * @rx_ring: ring to place buffers on
1049 * @cleaned_count: number of buffers to replace
1051 void ixgbe_alloc_rx_buffers(struct ixgbe_ring
*rx_ring
, u16 cleaned_count
)
1053 union ixgbe_adv_rx_desc
*rx_desc
;
1054 struct ixgbe_rx_buffer
*bi
;
1055 struct sk_buff
*skb
;
1056 u16 i
= rx_ring
->next_to_use
;
1058 /* do nothing if no valid netdev defined */
1059 if (!rx_ring
->netdev
)
1062 while (cleaned_count
--) {
1063 rx_desc
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
1064 bi
= &rx_ring
->rx_buffer_info
[i
];
1068 skb
= netdev_alloc_skb_ip_align(rx_ring
->netdev
,
1069 rx_ring
->rx_buf_len
);
1071 rx_ring
->rx_stats
.alloc_rx_buff_failed
++;
1074 /* initialize queue mapping */
1075 skb_record_rx_queue(skb
, rx_ring
->queue_index
);
1080 bi
->dma
= dma_map_single(rx_ring
->dev
,
1082 rx_ring
->rx_buf_len
,
1084 if (dma_mapping_error(rx_ring
->dev
, bi
->dma
)) {
1085 rx_ring
->rx_stats
.alloc_rx_buff_failed
++;
1091 if (ring_is_ps_enabled(rx_ring
)) {
1093 bi
->page
= netdev_alloc_page(rx_ring
->netdev
);
1095 rx_ring
->rx_stats
.alloc_rx_page_failed
++;
1100 if (!bi
->page_dma
) {
1101 /* use a half page if we're re-using */
1102 bi
->page_offset
^= PAGE_SIZE
/ 2;
1103 bi
->page_dma
= dma_map_page(rx_ring
->dev
,
1108 if (dma_mapping_error(rx_ring
->dev
,
1110 rx_ring
->rx_stats
.alloc_rx_page_failed
++;
1116 /* Refresh the desc even if buffer_addrs didn't change
1117 * because each write-back erases this info. */
1118 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->page_dma
);
1119 rx_desc
->read
.hdr_addr
= cpu_to_le64(bi
->dma
);
1121 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->dma
);
1122 rx_desc
->read
.hdr_addr
= 0;
1126 if (i
== rx_ring
->count
)
1131 if (rx_ring
->next_to_use
!= i
) {
1132 rx_ring
->next_to_use
= i
;
1133 ixgbe_release_rx_desc(rx_ring
, i
);
1137 static inline u16
ixgbe_get_hlen(union ixgbe_adv_rx_desc
*rx_desc
)
1139 /* HW will not DMA in data larger than the given buffer, even if it
1140 * parses the (NFS, of course) header to be larger. In that case, it
1141 * fills the header buffer and spills the rest into the page.
1143 u16 hdr_info
= le16_to_cpu(rx_desc
->wb
.lower
.lo_dword
.hs_rss
.hdr_info
);
1144 u16 hlen
= (hdr_info
& IXGBE_RXDADV_HDRBUFLEN_MASK
) >>
1145 IXGBE_RXDADV_HDRBUFLEN_SHIFT
;
1146 if (hlen
> IXGBE_RX_HDR_SIZE
)
1147 hlen
= IXGBE_RX_HDR_SIZE
;
1152 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1153 * @skb: pointer to the last skb in the rsc queue
1155 * This function changes a queue full of hw rsc buffers into a completed
1156 * packet. It uses the ->prev pointers to find the first packet and then
1157 * turns it into the frag list owner.
1159 static inline struct sk_buff
*ixgbe_transform_rsc_queue(struct sk_buff
*skb
)
1161 unsigned int frag_list_size
= 0;
1162 unsigned int skb_cnt
= 1;
1165 struct sk_buff
*prev
= skb
->prev
;
1166 frag_list_size
+= skb
->len
;
1172 skb_shinfo(skb
)->frag_list
= skb
->next
;
1174 skb
->len
+= frag_list_size
;
1175 skb
->data_len
+= frag_list_size
;
1176 skb
->truesize
+= frag_list_size
;
1177 IXGBE_RSC_CB(skb
)->skb_cnt
= skb_cnt
;
1182 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc
*rx_desc
)
1184 return !!(le32_to_cpu(rx_desc
->wb
.lower
.lo_dword
.data
) &
1185 IXGBE_RXDADV_RSCCNT_MASK
);
1188 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector
*q_vector
,
1189 struct ixgbe_ring
*rx_ring
,
1190 int *work_done
, int work_to_do
)
1192 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1193 union ixgbe_adv_rx_desc
*rx_desc
, *next_rxd
;
1194 struct ixgbe_rx_buffer
*rx_buffer_info
, *next_buffer
;
1195 struct sk_buff
*skb
;
1196 unsigned int total_rx_bytes
= 0, total_rx_packets
= 0;
1197 const int current_node
= numa_node_id();
1200 #endif /* IXGBE_FCOE */
1203 u16 cleaned_count
= 0;
1204 bool pkt_is_rsc
= false;
1206 i
= rx_ring
->next_to_clean
;
1207 rx_desc
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
1208 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1210 while (staterr
& IXGBE_RXD_STAT_DD
) {
1213 rmb(); /* read descriptor and rx_buffer_info after status DD */
1215 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
1217 skb
= rx_buffer_info
->skb
;
1218 rx_buffer_info
->skb
= NULL
;
1219 prefetch(skb
->data
);
1221 if (ring_is_rsc_enabled(rx_ring
))
1222 pkt_is_rsc
= ixgbe_get_rsc_state(rx_desc
);
1224 /* if this is a skb from previous receive DMA will be 0 */
1225 if (rx_buffer_info
->dma
) {
1228 !(staterr
& IXGBE_RXD_STAT_EOP
) &&
1231 * When HWRSC is enabled, delay unmapping
1232 * of the first packet. It carries the
1233 * header information, HW may still
1234 * access the header after the writeback.
1235 * Only unmap it when EOP is reached
1237 IXGBE_RSC_CB(skb
)->delay_unmap
= true;
1238 IXGBE_RSC_CB(skb
)->dma
= rx_buffer_info
->dma
;
1240 dma_unmap_single(rx_ring
->dev
,
1241 rx_buffer_info
->dma
,
1242 rx_ring
->rx_buf_len
,
1245 rx_buffer_info
->dma
= 0;
1247 if (ring_is_ps_enabled(rx_ring
)) {
1248 hlen
= ixgbe_get_hlen(rx_desc
);
1249 upper_len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1251 hlen
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1256 /* assume packet split since header is unmapped */
1257 upper_len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1261 dma_unmap_page(rx_ring
->dev
,
1262 rx_buffer_info
->page_dma
,
1265 rx_buffer_info
->page_dma
= 0;
1266 skb_fill_page_desc(skb
, skb_shinfo(skb
)->nr_frags
,
1267 rx_buffer_info
->page
,
1268 rx_buffer_info
->page_offset
,
1271 if ((page_count(rx_buffer_info
->page
) == 1) &&
1272 (page_to_nid(rx_buffer_info
->page
) == current_node
))
1273 get_page(rx_buffer_info
->page
);
1275 rx_buffer_info
->page
= NULL
;
1277 skb
->len
+= upper_len
;
1278 skb
->data_len
+= upper_len
;
1279 skb
->truesize
+= upper_len
;
1283 if (i
== rx_ring
->count
)
1286 next_rxd
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
1291 u32 nextp
= (staterr
& IXGBE_RXDADV_NEXTP_MASK
) >>
1292 IXGBE_RXDADV_NEXTP_SHIFT
;
1293 next_buffer
= &rx_ring
->rx_buffer_info
[nextp
];
1295 next_buffer
= &rx_ring
->rx_buffer_info
[i
];
1298 if (!(staterr
& IXGBE_RXD_STAT_EOP
)) {
1299 if (ring_is_ps_enabled(rx_ring
)) {
1300 rx_buffer_info
->skb
= next_buffer
->skb
;
1301 rx_buffer_info
->dma
= next_buffer
->dma
;
1302 next_buffer
->skb
= skb
;
1303 next_buffer
->dma
= 0;
1305 skb
->next
= next_buffer
->skb
;
1306 skb
->next
->prev
= skb
;
1308 rx_ring
->rx_stats
.non_eop_descs
++;
1313 skb
= ixgbe_transform_rsc_queue(skb
);
1314 /* if we got here without RSC the packet is invalid */
1316 __pskb_trim(skb
, 0);
1317 rx_buffer_info
->skb
= skb
;
1322 if (ring_is_rsc_enabled(rx_ring
)) {
1323 if (IXGBE_RSC_CB(skb
)->delay_unmap
) {
1324 dma_unmap_single(rx_ring
->dev
,
1325 IXGBE_RSC_CB(skb
)->dma
,
1326 rx_ring
->rx_buf_len
,
1328 IXGBE_RSC_CB(skb
)->dma
= 0;
1329 IXGBE_RSC_CB(skb
)->delay_unmap
= false;
1333 if (ring_is_ps_enabled(rx_ring
))
1334 rx_ring
->rx_stats
.rsc_count
+=
1335 skb_shinfo(skb
)->nr_frags
;
1337 rx_ring
->rx_stats
.rsc_count
+=
1338 IXGBE_RSC_CB(skb
)->skb_cnt
;
1339 rx_ring
->rx_stats
.rsc_flush
++;
1342 /* ERR_MASK will only have valid bits if EOP set */
1343 if (staterr
& IXGBE_RXDADV_ERR_FRAME_ERR_MASK
) {
1344 /* trim packet back to size 0 and recycle it */
1345 __pskb_trim(skb
, 0);
1346 rx_buffer_info
->skb
= skb
;
1350 ixgbe_rx_checksum(adapter
, rx_desc
, skb
);
1352 /* probably a little skewed due to removing CRC */
1353 total_rx_bytes
+= skb
->len
;
1356 skb
->protocol
= eth_type_trans(skb
, rx_ring
->netdev
);
1358 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1359 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
1360 ddp_bytes
= ixgbe_fcoe_ddp(adapter
, rx_desc
, skb
);
1364 #endif /* IXGBE_FCOE */
1365 ixgbe_receive_skb(q_vector
, skb
, staterr
, rx_ring
, rx_desc
);
1368 rx_desc
->wb
.upper
.status_error
= 0;
1371 if (*work_done
>= work_to_do
)
1374 /* return some buffers to hardware, one at a time is too slow */
1375 if (cleaned_count
>= IXGBE_RX_BUFFER_WRITE
) {
1376 ixgbe_alloc_rx_buffers(rx_ring
, cleaned_count
);
1380 /* use prefetched values */
1382 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1385 rx_ring
->next_to_clean
= i
;
1386 cleaned_count
= IXGBE_DESC_UNUSED(rx_ring
);
1389 ixgbe_alloc_rx_buffers(rx_ring
, cleaned_count
);
1392 /* include DDPed FCoE data */
1393 if (ddp_bytes
> 0) {
1396 mss
= rx_ring
->netdev
->mtu
- sizeof(struct fcoe_hdr
) -
1397 sizeof(struct fc_frame_header
) -
1398 sizeof(struct fcoe_crc_eof
);
1401 total_rx_bytes
+= ddp_bytes
;
1402 total_rx_packets
+= DIV_ROUND_UP(ddp_bytes
, mss
);
1404 #endif /* IXGBE_FCOE */
1406 rx_ring
->total_packets
+= total_rx_packets
;
1407 rx_ring
->total_bytes
+= total_rx_bytes
;
1408 u64_stats_update_begin(&rx_ring
->syncp
);
1409 rx_ring
->stats
.packets
+= total_rx_packets
;
1410 rx_ring
->stats
.bytes
+= total_rx_bytes
;
1411 u64_stats_update_end(&rx_ring
->syncp
);
1414 static int ixgbe_clean_rxonly(struct napi_struct
*, int);
1416 * ixgbe_configure_msix - Configure MSI-X hardware
1417 * @adapter: board private structure
1419 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1422 static void ixgbe_configure_msix(struct ixgbe_adapter
*adapter
)
1424 struct ixgbe_q_vector
*q_vector
;
1425 int i
, j
, q_vectors
, v_idx
, r_idx
;
1428 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1431 * Populate the IVAR table and set the ITR values to the
1432 * corresponding register.
1434 for (v_idx
= 0; v_idx
< q_vectors
; v_idx
++) {
1435 q_vector
= adapter
->q_vector
[v_idx
];
1436 /* XXX for_each_set_bit(...) */
1437 r_idx
= find_first_bit(q_vector
->rxr_idx
,
1438 adapter
->num_rx_queues
);
1440 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1441 j
= adapter
->rx_ring
[r_idx
]->reg_idx
;
1442 ixgbe_set_ivar(adapter
, 0, j
, v_idx
);
1443 r_idx
= find_next_bit(q_vector
->rxr_idx
,
1444 adapter
->num_rx_queues
,
1447 r_idx
= find_first_bit(q_vector
->txr_idx
,
1448 adapter
->num_tx_queues
);
1450 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1451 j
= adapter
->tx_ring
[r_idx
]->reg_idx
;
1452 ixgbe_set_ivar(adapter
, 1, j
, v_idx
);
1453 r_idx
= find_next_bit(q_vector
->txr_idx
,
1454 adapter
->num_tx_queues
,
1458 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
1460 q_vector
->eitr
= adapter
->tx_eitr_param
;
1461 else if (q_vector
->rxr_count
)
1463 q_vector
->eitr
= adapter
->rx_eitr_param
;
1465 ixgbe_write_eitr(q_vector
);
1466 /* If Flow Director is enabled, set interrupt affinity */
1467 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
1468 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)) {
1470 * Allocate the affinity_hint cpumask, assign the mask
1471 * for this vector, and set our affinity_hint for
1474 if (!alloc_cpumask_var(&q_vector
->affinity_mask
,
1477 cpumask_set_cpu(v_idx
, q_vector
->affinity_mask
);
1478 irq_set_affinity_hint(adapter
->msix_entries
[v_idx
].vector
,
1479 q_vector
->affinity_mask
);
1483 switch (adapter
->hw
.mac
.type
) {
1484 case ixgbe_mac_82598EB
:
1485 ixgbe_set_ivar(adapter
, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX
,
1488 case ixgbe_mac_82599EB
:
1489 ixgbe_set_ivar(adapter
, -1, 1, v_idx
);
1495 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITR(v_idx
), 1950);
1497 /* set up to autoclear timer, and the vectors */
1498 mask
= IXGBE_EIMS_ENABLE_MASK
;
1499 if (adapter
->num_vfs
)
1500 mask
&= ~(IXGBE_EIMS_OTHER
|
1501 IXGBE_EIMS_MAILBOX
|
1504 mask
&= ~(IXGBE_EIMS_OTHER
| IXGBE_EIMS_LSC
);
1505 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIAC
, mask
);
1508 enum latency_range
{
1512 latency_invalid
= 255
1516 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1517 * @adapter: pointer to adapter
1518 * @eitr: eitr setting (ints per sec) to give last timeslice
1519 * @itr_setting: current throttle rate in ints/second
1520 * @packets: the number of packets during this measurement interval
1521 * @bytes: the number of bytes during this measurement interval
1523 * Stores a new ITR value based on packets and byte
1524 * counts during the last interrupt. The advantage of per interrupt
1525 * computation is faster updates and more accurate ITR for the current
1526 * traffic pattern. Constants in this function were computed
1527 * based on theoretical maximum wire speed and thresholds were set based
1528 * on testing data as well as attempting to minimize response time
1529 * while increasing bulk throughput.
1530 * this functionality is controlled by the InterruptThrottleRate module
1531 * parameter (see ixgbe_param.c)
1533 static u8
ixgbe_update_itr(struct ixgbe_adapter
*adapter
,
1534 u32 eitr
, u8 itr_setting
,
1535 int packets
, int bytes
)
1537 unsigned int retval
= itr_setting
;
1542 goto update_itr_done
;
1545 /* simple throttlerate management
1546 * 0-20MB/s lowest (100000 ints/s)
1547 * 20-100MB/s low (20000 ints/s)
1548 * 100-1249MB/s bulk (8000 ints/s)
1550 /* what was last interrupt timeslice? */
1551 timepassed_us
= 1000000/eitr
;
1552 bytes_perint
= bytes
/ timepassed_us
; /* bytes/usec */
1554 switch (itr_setting
) {
1555 case lowest_latency
:
1556 if (bytes_perint
> adapter
->eitr_low
)
1557 retval
= low_latency
;
1560 if (bytes_perint
> adapter
->eitr_high
)
1561 retval
= bulk_latency
;
1562 else if (bytes_perint
<= adapter
->eitr_low
)
1563 retval
= lowest_latency
;
1566 if (bytes_perint
<= adapter
->eitr_high
)
1567 retval
= low_latency
;
1576 * ixgbe_write_eitr - write EITR register in hardware specific way
1577 * @q_vector: structure containing interrupt and ring information
1579 * This function is made to be called by ethtool and by the driver
1580 * when it needs to update EITR registers at runtime. Hardware
1581 * specific quirks/differences are taken care of here.
1583 void ixgbe_write_eitr(struct ixgbe_q_vector
*q_vector
)
1585 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1586 struct ixgbe_hw
*hw
= &adapter
->hw
;
1587 int v_idx
= q_vector
->v_idx
;
1588 u32 itr_reg
= EITR_INTS_PER_SEC_TO_REG(q_vector
->eitr
);
1590 switch (adapter
->hw
.mac
.type
) {
1591 case ixgbe_mac_82598EB
:
1592 /* must write high and low 16 bits to reset counter */
1593 itr_reg
|= (itr_reg
<< 16);
1595 case ixgbe_mac_82599EB
:
1597 * 82599 can support a value of zero, so allow it for
1598 * max interrupt rate, but there is an errata where it can
1599 * not be zero with RSC
1602 !(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
))
1606 * set the WDIS bit to not clear the timer bits and cause an
1607 * immediate assertion of the interrupt
1609 itr_reg
|= IXGBE_EITR_CNT_WDIS
;
1614 IXGBE_WRITE_REG(hw
, IXGBE_EITR(v_idx
), itr_reg
);
1617 static void ixgbe_set_itr_msix(struct ixgbe_q_vector
*q_vector
)
1619 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1621 u8 current_itr
, ret_itr
;
1623 struct ixgbe_ring
*rx_ring
, *tx_ring
;
1625 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1626 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1627 tx_ring
= adapter
->tx_ring
[r_idx
];
1628 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1630 tx_ring
->total_packets
,
1631 tx_ring
->total_bytes
);
1632 /* if the result for this queue would decrease interrupt
1633 * rate for this vector then use that result */
1634 q_vector
->tx_itr
= ((q_vector
->tx_itr
> ret_itr
) ?
1635 q_vector
->tx_itr
- 1 : ret_itr
);
1636 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1640 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1641 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1642 rx_ring
= adapter
->rx_ring
[r_idx
];
1643 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1645 rx_ring
->total_packets
,
1646 rx_ring
->total_bytes
);
1647 /* if the result for this queue would decrease interrupt
1648 * rate for this vector then use that result */
1649 q_vector
->rx_itr
= ((q_vector
->rx_itr
> ret_itr
) ?
1650 q_vector
->rx_itr
- 1 : ret_itr
);
1651 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1655 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
1657 switch (current_itr
) {
1658 /* counts and packets in update_itr are dependent on these numbers */
1659 case lowest_latency
:
1663 new_itr
= 20000; /* aka hwitr = ~200 */
1671 if (new_itr
!= q_vector
->eitr
) {
1672 /* do an exponential smoothing */
1673 new_itr
= ((q_vector
->eitr
* 90)/100) + ((new_itr
* 10)/100);
1675 /* save the algorithm value here, not the smoothed one */
1676 q_vector
->eitr
= new_itr
;
1678 ixgbe_write_eitr(q_vector
);
1683 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1684 * @work: pointer to work_struct containing our data
1686 static void ixgbe_check_overtemp_task(struct work_struct
*work
)
1688 struct ixgbe_adapter
*adapter
= container_of(work
,
1689 struct ixgbe_adapter
,
1690 check_overtemp_task
);
1691 struct ixgbe_hw
*hw
= &adapter
->hw
;
1692 u32 eicr
= adapter
->interrupt_event
;
1694 if (!(adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
))
1697 switch (hw
->device_id
) {
1698 case IXGBE_DEV_ID_82599_T3_LOM
: {
1700 bool link_up
= false;
1702 if (hw
->mac
.ops
.check_link
)
1703 hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
1705 if (((eicr
& IXGBE_EICR_GPI_SDP0
) && (!link_up
)) ||
1706 (eicr
& IXGBE_EICR_LSC
))
1707 /* Check if this is due to overtemp */
1708 if (hw
->phy
.ops
.check_overtemp(hw
) == IXGBE_ERR_OVERTEMP
)
1713 if (!(eicr
& IXGBE_EICR_GPI_SDP0
))
1718 "Network adapter has been stopped because it has over heated. "
1719 "Restart the computer. If the problem persists, "
1720 "power off the system and replace the adapter\n");
1721 /* write to clear the interrupt */
1722 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP0
);
1725 static void ixgbe_check_fan_failure(struct ixgbe_adapter
*adapter
, u32 eicr
)
1727 struct ixgbe_hw
*hw
= &adapter
->hw
;
1729 if ((adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) &&
1730 (eicr
& IXGBE_EICR_GPI_SDP1
)) {
1731 e_crit(probe
, "Fan has stopped, replace the adapter\n");
1732 /* write to clear the interrupt */
1733 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1737 static void ixgbe_check_sfp_event(struct ixgbe_adapter
*adapter
, u32 eicr
)
1739 struct ixgbe_hw
*hw
= &adapter
->hw
;
1741 if (eicr
& IXGBE_EICR_GPI_SDP2
) {
1742 /* Clear the interrupt */
1743 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP2
);
1744 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1745 schedule_work(&adapter
->sfp_config_module_task
);
1748 if (eicr
& IXGBE_EICR_GPI_SDP1
) {
1749 /* Clear the interrupt */
1750 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1751 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1752 schedule_work(&adapter
->multispeed_fiber_task
);
1756 static void ixgbe_check_lsc(struct ixgbe_adapter
*adapter
)
1758 struct ixgbe_hw
*hw
= &adapter
->hw
;
1761 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
1762 adapter
->link_check_timeout
= jiffies
;
1763 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1764 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_EIMC_LSC
);
1765 IXGBE_WRITE_FLUSH(hw
);
1766 schedule_work(&adapter
->watchdog_task
);
1770 static irqreturn_t
ixgbe_msix_lsc(int irq
, void *data
)
1772 struct net_device
*netdev
= data
;
1773 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
1774 struct ixgbe_hw
*hw
= &adapter
->hw
;
1778 * Workaround for Silicon errata. Use clear-by-write instead
1779 * of clear-by-read. Reading with EICS will return the
1780 * interrupt causes without clearing, which later be done
1781 * with the write to EICR.
1783 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICS
);
1784 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, eicr
);
1786 if (eicr
& IXGBE_EICR_LSC
)
1787 ixgbe_check_lsc(adapter
);
1789 if (eicr
& IXGBE_EICR_MAILBOX
)
1790 ixgbe_msg_task(adapter
);
1792 switch (hw
->mac
.type
) {
1793 case ixgbe_mac_82599EB
:
1794 /* Handle Flow Director Full threshold interrupt */
1795 if (eicr
& IXGBE_EICR_FLOW_DIR
) {
1797 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_FLOW_DIR
);
1798 /* Disable transmits before FDIR Re-initialization */
1799 netif_tx_stop_all_queues(netdev
);
1800 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
1801 struct ixgbe_ring
*tx_ring
=
1802 adapter
->tx_ring
[i
];
1803 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE
,
1805 schedule_work(&adapter
->fdir_reinit_task
);
1808 ixgbe_check_sfp_event(adapter
, eicr
);
1809 if ((adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) &&
1810 ((eicr
& IXGBE_EICR_GPI_SDP0
) || (eicr
& IXGBE_EICR_LSC
))) {
1811 adapter
->interrupt_event
= eicr
;
1812 schedule_work(&adapter
->check_overtemp_task
);
1819 ixgbe_check_fan_failure(adapter
, eicr
);
1821 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1822 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMS_OTHER
);
1827 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter
*adapter
,
1831 struct ixgbe_hw
*hw
= &adapter
->hw
;
1833 switch (hw
->mac
.type
) {
1834 case ixgbe_mac_82598EB
:
1835 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1836 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, mask
);
1838 case ixgbe_mac_82599EB
:
1839 mask
= (qmask
& 0xFFFFFFFF);
1841 IXGBE_WRITE_REG(hw
, IXGBE_EIMS_EX(0), mask
);
1842 mask
= (qmask
>> 32);
1844 IXGBE_WRITE_REG(hw
, IXGBE_EIMS_EX(1), mask
);
1849 /* skip the flush */
1852 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter
*adapter
,
1856 struct ixgbe_hw
*hw
= &adapter
->hw
;
1858 switch (hw
->mac
.type
) {
1859 case ixgbe_mac_82598EB
:
1860 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1861 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, mask
);
1863 case ixgbe_mac_82599EB
:
1864 mask
= (qmask
& 0xFFFFFFFF);
1866 IXGBE_WRITE_REG(hw
, IXGBE_EIMC_EX(0), mask
);
1867 mask
= (qmask
>> 32);
1869 IXGBE_WRITE_REG(hw
, IXGBE_EIMC_EX(1), mask
);
1874 /* skip the flush */
1877 static irqreturn_t
ixgbe_msix_clean_tx(int irq
, void *data
)
1879 struct ixgbe_q_vector
*q_vector
= data
;
1880 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1881 struct ixgbe_ring
*tx_ring
;
1884 if (!q_vector
->txr_count
)
1887 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1888 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1889 tx_ring
= adapter
->tx_ring
[r_idx
];
1890 tx_ring
->total_bytes
= 0;
1891 tx_ring
->total_packets
= 0;
1892 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1896 /* EIAM disabled interrupts (on this vector) for us */
1897 napi_schedule(&q_vector
->napi
);
1903 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1905 * @data: pointer to our q_vector struct for this interrupt vector
1907 static irqreturn_t
ixgbe_msix_clean_rx(int irq
, void *data
)
1909 struct ixgbe_q_vector
*q_vector
= data
;
1910 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1911 struct ixgbe_ring
*rx_ring
;
1915 #ifdef CONFIG_IXGBE_DCA
1916 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1917 ixgbe_update_dca(q_vector
);
1920 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1921 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1922 rx_ring
= adapter
->rx_ring
[r_idx
];
1923 rx_ring
->total_bytes
= 0;
1924 rx_ring
->total_packets
= 0;
1925 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1929 if (!q_vector
->rxr_count
)
1932 /* EIAM disabled interrupts (on this vector) for us */
1933 napi_schedule(&q_vector
->napi
);
1938 static irqreturn_t
ixgbe_msix_clean_many(int irq
, void *data
)
1940 struct ixgbe_q_vector
*q_vector
= data
;
1941 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1942 struct ixgbe_ring
*ring
;
1946 if (!q_vector
->txr_count
&& !q_vector
->rxr_count
)
1949 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1950 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1951 ring
= adapter
->tx_ring
[r_idx
];
1952 ring
->total_bytes
= 0;
1953 ring
->total_packets
= 0;
1954 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1958 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1959 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1960 ring
= adapter
->rx_ring
[r_idx
];
1961 ring
->total_bytes
= 0;
1962 ring
->total_packets
= 0;
1963 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1967 /* EIAM disabled interrupts (on this vector) for us */
1968 napi_schedule(&q_vector
->napi
);
1974 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1975 * @napi: napi struct with our devices info in it
1976 * @budget: amount of work driver is allowed to do this pass, in packets
1978 * This function is optimized for cleaning one queue only on a single
1981 static int ixgbe_clean_rxonly(struct napi_struct
*napi
, int budget
)
1983 struct ixgbe_q_vector
*q_vector
=
1984 container_of(napi
, struct ixgbe_q_vector
, napi
);
1985 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1986 struct ixgbe_ring
*rx_ring
= NULL
;
1990 #ifdef CONFIG_IXGBE_DCA
1991 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1992 ixgbe_update_dca(q_vector
);
1995 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1996 rx_ring
= adapter
->rx_ring
[r_idx
];
1998 ixgbe_clean_rx_irq(q_vector
, rx_ring
, &work_done
, budget
);
2000 /* If all Rx work done, exit the polling mode */
2001 if (work_done
< budget
) {
2002 napi_complete(napi
);
2003 if (adapter
->rx_itr_setting
& 1)
2004 ixgbe_set_itr_msix(q_vector
);
2005 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2006 ixgbe_irq_enable_queues(adapter
,
2007 ((u64
)1 << q_vector
->v_idx
));
2014 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2015 * @napi: napi struct with our devices info in it
2016 * @budget: amount of work driver is allowed to do this pass, in packets
2018 * This function will clean more than one rx queue associated with a
2021 static int ixgbe_clean_rxtx_many(struct napi_struct
*napi
, int budget
)
2023 struct ixgbe_q_vector
*q_vector
=
2024 container_of(napi
, struct ixgbe_q_vector
, napi
);
2025 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2026 struct ixgbe_ring
*ring
= NULL
;
2027 int work_done
= 0, i
;
2029 bool tx_clean_complete
= true;
2031 #ifdef CONFIG_IXGBE_DCA
2032 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
2033 ixgbe_update_dca(q_vector
);
2036 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
2037 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
2038 ring
= adapter
->tx_ring
[r_idx
];
2039 tx_clean_complete
&= ixgbe_clean_tx_irq(q_vector
, ring
);
2040 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
2044 /* attempt to distribute budget to each queue fairly, but don't allow
2045 * the budget to go below 1 because we'll exit polling */
2046 budget
/= (q_vector
->rxr_count
?: 1);
2047 budget
= max(budget
, 1);
2048 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
2049 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
2050 ring
= adapter
->rx_ring
[r_idx
];
2051 ixgbe_clean_rx_irq(q_vector
, ring
, &work_done
, budget
);
2052 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
2056 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
2057 ring
= adapter
->rx_ring
[r_idx
];
2058 /* If all Rx work done, exit the polling mode */
2059 if (work_done
< budget
) {
2060 napi_complete(napi
);
2061 if (adapter
->rx_itr_setting
& 1)
2062 ixgbe_set_itr_msix(q_vector
);
2063 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2064 ixgbe_irq_enable_queues(adapter
,
2065 ((u64
)1 << q_vector
->v_idx
));
2073 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2074 * @napi: napi struct with our devices info in it
2075 * @budget: amount of work driver is allowed to do this pass, in packets
2077 * This function is optimized for cleaning one queue only on a single
2080 static int ixgbe_clean_txonly(struct napi_struct
*napi
, int budget
)
2082 struct ixgbe_q_vector
*q_vector
=
2083 container_of(napi
, struct ixgbe_q_vector
, napi
);
2084 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2085 struct ixgbe_ring
*tx_ring
= NULL
;
2089 #ifdef CONFIG_IXGBE_DCA
2090 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
2091 ixgbe_update_dca(q_vector
);
2094 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
2095 tx_ring
= adapter
->tx_ring
[r_idx
];
2097 if (!ixgbe_clean_tx_irq(q_vector
, tx_ring
))
2100 /* If all Tx work done, exit the polling mode */
2101 if (work_done
< budget
) {
2102 napi_complete(napi
);
2103 if (adapter
->tx_itr_setting
& 1)
2104 ixgbe_set_itr_msix(q_vector
);
2105 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2106 ixgbe_irq_enable_queues(adapter
,
2107 ((u64
)1 << q_vector
->v_idx
));
2113 static inline void map_vector_to_rxq(struct ixgbe_adapter
*a
, int v_idx
,
2116 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
2118 set_bit(r_idx
, q_vector
->rxr_idx
);
2119 q_vector
->rxr_count
++;
2122 static inline void map_vector_to_txq(struct ixgbe_adapter
*a
, int v_idx
,
2125 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
2127 set_bit(t_idx
, q_vector
->txr_idx
);
2128 q_vector
->txr_count
++;
2132 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2133 * @adapter: board private structure to initialize
2134 * @vectors: allotted vector count for descriptor rings
2136 * This function maps descriptor rings to the queue-specific vectors
2137 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2138 * one vector per ring/queue, but on a constrained vector budget, we
2139 * group the rings as "efficiently" as possible. You would add new
2140 * mapping configurations in here.
2142 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter
*adapter
,
2146 int rxr_idx
= 0, txr_idx
= 0;
2147 int rxr_remaining
= adapter
->num_rx_queues
;
2148 int txr_remaining
= adapter
->num_tx_queues
;
2153 /* No mapping required if MSI-X is disabled. */
2154 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
2158 * The ideal configuration...
2159 * We have enough vectors to map one per queue.
2161 if (vectors
== adapter
->num_rx_queues
+ adapter
->num_tx_queues
) {
2162 for (; rxr_idx
< rxr_remaining
; v_start
++, rxr_idx
++)
2163 map_vector_to_rxq(adapter
, v_start
, rxr_idx
);
2165 for (; txr_idx
< txr_remaining
; v_start
++, txr_idx
++)
2166 map_vector_to_txq(adapter
, v_start
, txr_idx
);
2172 * If we don't have enough vectors for a 1-to-1
2173 * mapping, we'll have to group them so there are
2174 * multiple queues per vector.
2176 /* Re-adjusting *qpv takes care of the remainder. */
2177 for (i
= v_start
; i
< vectors
; i
++) {
2178 rqpv
= DIV_ROUND_UP(rxr_remaining
, vectors
- i
);
2179 for (j
= 0; j
< rqpv
; j
++) {
2180 map_vector_to_rxq(adapter
, i
, rxr_idx
);
2185 for (i
= v_start
; i
< vectors
; i
++) {
2186 tqpv
= DIV_ROUND_UP(txr_remaining
, vectors
- i
);
2187 for (j
= 0; j
< tqpv
; j
++) {
2188 map_vector_to_txq(adapter
, i
, txr_idx
);
2199 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2200 * @adapter: board private structure
2202 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2203 * interrupts from the kernel.
2205 static int ixgbe_request_msix_irqs(struct ixgbe_adapter
*adapter
)
2207 struct net_device
*netdev
= adapter
->netdev
;
2208 irqreturn_t (*handler
)(int, void *);
2209 int i
, vector
, q_vectors
, err
;
2212 /* Decrement for Other and TCP Timer vectors */
2213 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2215 /* Map the Tx/Rx rings to the vectors we were allotted. */
2216 err
= ixgbe_map_rings_to_vectors(adapter
, q_vectors
);
2220 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2221 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2222 &ixgbe_msix_clean_many)
2223 for (vector
= 0; vector
< q_vectors
; vector
++) {
2224 handler
= SET_HANDLER(adapter
->q_vector
[vector
]);
2226 if (handler
== &ixgbe_msix_clean_rx
) {
2227 sprintf(adapter
->name
[vector
], "%s-%s-%d",
2228 netdev
->name
, "rx", ri
++);
2229 } else if (handler
== &ixgbe_msix_clean_tx
) {
2230 sprintf(adapter
->name
[vector
], "%s-%s-%d",
2231 netdev
->name
, "tx", ti
++);
2233 sprintf(adapter
->name
[vector
], "%s-%s-%d",
2234 netdev
->name
, "TxRx", ri
++);
2238 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
2239 handler
, 0, adapter
->name
[vector
],
2240 adapter
->q_vector
[vector
]);
2242 e_err(probe
, "request_irq failed for MSIX interrupt "
2243 "Error: %d\n", err
);
2244 goto free_queue_irqs
;
2248 sprintf(adapter
->name
[vector
], "%s:lsc", netdev
->name
);
2249 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
2250 ixgbe_msix_lsc
, 0, adapter
->name
[vector
], netdev
);
2252 e_err(probe
, "request_irq for msix_lsc failed: %d\n", err
);
2253 goto free_queue_irqs
;
2259 for (i
= vector
- 1; i
>= 0; i
--)
2260 free_irq(adapter
->msix_entries
[--vector
].vector
,
2261 adapter
->q_vector
[i
]);
2262 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
2263 pci_disable_msix(adapter
->pdev
);
2264 kfree(adapter
->msix_entries
);
2265 adapter
->msix_entries
= NULL
;
2270 static void ixgbe_set_itr(struct ixgbe_adapter
*adapter
)
2272 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
2274 u32 new_itr
= q_vector
->eitr
;
2275 struct ixgbe_ring
*rx_ring
= adapter
->rx_ring
[0];
2276 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[0];
2278 q_vector
->tx_itr
= ixgbe_update_itr(adapter
, new_itr
,
2280 tx_ring
->total_packets
,
2281 tx_ring
->total_bytes
);
2282 q_vector
->rx_itr
= ixgbe_update_itr(adapter
, new_itr
,
2284 rx_ring
->total_packets
,
2285 rx_ring
->total_bytes
);
2287 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
2289 switch (current_itr
) {
2290 /* counts and packets in update_itr are dependent on these numbers */
2291 case lowest_latency
:
2295 new_itr
= 20000; /* aka hwitr = ~200 */
2304 if (new_itr
!= q_vector
->eitr
) {
2305 /* do an exponential smoothing */
2306 new_itr
= ((q_vector
->eitr
* 90)/100) + ((new_itr
* 10)/100);
2308 /* save the algorithm value here, not the smoothed one */
2309 q_vector
->eitr
= new_itr
;
2311 ixgbe_write_eitr(q_vector
);
2316 * ixgbe_irq_enable - Enable default interrupt generation settings
2317 * @adapter: board private structure
2319 static inline void ixgbe_irq_enable(struct ixgbe_adapter
*adapter
, bool queues
,
2324 mask
= (IXGBE_EIMS_ENABLE_MASK
& ~IXGBE_EIMS_RTX_QUEUE
);
2325 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
)
2326 mask
|= IXGBE_EIMS_GPI_SDP0
;
2327 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
)
2328 mask
|= IXGBE_EIMS_GPI_SDP1
;
2329 switch (adapter
->hw
.mac
.type
) {
2330 case ixgbe_mac_82599EB
:
2331 mask
|= IXGBE_EIMS_ECC
;
2332 mask
|= IXGBE_EIMS_GPI_SDP1
;
2333 mask
|= IXGBE_EIMS_GPI_SDP2
;
2334 if (adapter
->num_vfs
)
2335 mask
|= IXGBE_EIMS_MAILBOX
;
2340 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
2341 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
2342 mask
|= IXGBE_EIMS_FLOW_DIR
;
2344 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
2346 ixgbe_irq_enable_queues(adapter
, ~0);
2348 IXGBE_WRITE_FLUSH(&adapter
->hw
);
2350 if (adapter
->num_vfs
> 32) {
2351 u32 eitrsel
= (1 << (adapter
->num_vfs
- 32)) - 1;
2352 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, eitrsel
);
2357 * ixgbe_intr - legacy mode Interrupt Handler
2358 * @irq: interrupt number
2359 * @data: pointer to a network interface device structure
2361 static irqreturn_t
ixgbe_intr(int irq
, void *data
)
2363 struct net_device
*netdev
= data
;
2364 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2365 struct ixgbe_hw
*hw
= &adapter
->hw
;
2366 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
2370 * Workaround for silicon errata on 82598. Mask the interrupts
2371 * before the read of EICR.
2373 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_IRQ_CLEAR_MASK
);
2375 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2376 * therefore no explict interrupt disable is necessary */
2377 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICR
);
2380 * shared interrupt alert!
2381 * make sure interrupts are enabled because the read will
2382 * have disabled interrupts due to EIAM
2383 * finish the workaround of silicon errata on 82598. Unmask
2384 * the interrupt that we masked before the EICR read.
2386 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2387 ixgbe_irq_enable(adapter
, true, true);
2388 return IRQ_NONE
; /* Not our interrupt */
2391 if (eicr
& IXGBE_EICR_LSC
)
2392 ixgbe_check_lsc(adapter
);
2394 switch (hw
->mac
.type
) {
2395 case ixgbe_mac_82599EB
:
2396 ixgbe_check_sfp_event(adapter
, eicr
);
2397 if ((adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) &&
2398 ((eicr
& IXGBE_EICR_GPI_SDP0
) || (eicr
& IXGBE_EICR_LSC
))) {
2399 adapter
->interrupt_event
= eicr
;
2400 schedule_work(&adapter
->check_overtemp_task
);
2407 ixgbe_check_fan_failure(adapter
, eicr
);
2409 if (napi_schedule_prep(&(q_vector
->napi
))) {
2410 adapter
->tx_ring
[0]->total_packets
= 0;
2411 adapter
->tx_ring
[0]->total_bytes
= 0;
2412 adapter
->rx_ring
[0]->total_packets
= 0;
2413 adapter
->rx_ring
[0]->total_bytes
= 0;
2414 /* would disable interrupts here but EIAM disabled it */
2415 __napi_schedule(&(q_vector
->napi
));
2419 * re-enable link(maybe) and non-queue interrupts, no flush.
2420 * ixgbe_poll will re-enable the queue interrupts
2423 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2424 ixgbe_irq_enable(adapter
, false, false);
2429 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter
*adapter
)
2431 int i
, q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2433 for (i
= 0; i
< q_vectors
; i
++) {
2434 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
2435 bitmap_zero(q_vector
->rxr_idx
, MAX_RX_QUEUES
);
2436 bitmap_zero(q_vector
->txr_idx
, MAX_TX_QUEUES
);
2437 q_vector
->rxr_count
= 0;
2438 q_vector
->txr_count
= 0;
2443 * ixgbe_request_irq - initialize interrupts
2444 * @adapter: board private structure
2446 * Attempts to configure interrupts using the best available
2447 * capabilities of the hardware and kernel.
2449 static int ixgbe_request_irq(struct ixgbe_adapter
*adapter
)
2451 struct net_device
*netdev
= adapter
->netdev
;
2454 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2455 err
= ixgbe_request_msix_irqs(adapter
);
2456 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
2457 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, 0,
2458 netdev
->name
, netdev
);
2460 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, IRQF_SHARED
,
2461 netdev
->name
, netdev
);
2465 e_err(probe
, "request_irq failed, Error %d\n", err
);
2470 static void ixgbe_free_irq(struct ixgbe_adapter
*adapter
)
2472 struct net_device
*netdev
= adapter
->netdev
;
2474 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2477 q_vectors
= adapter
->num_msix_vectors
;
2480 free_irq(adapter
->msix_entries
[i
].vector
, netdev
);
2483 for (; i
>= 0; i
--) {
2484 free_irq(adapter
->msix_entries
[i
].vector
,
2485 adapter
->q_vector
[i
]);
2488 ixgbe_reset_q_vectors(adapter
);
2490 free_irq(adapter
->pdev
->irq
, netdev
);
2495 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2496 * @adapter: board private structure
2498 static inline void ixgbe_irq_disable(struct ixgbe_adapter
*adapter
)
2500 switch (adapter
->hw
.mac
.type
) {
2501 case ixgbe_mac_82598EB
:
2502 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, ~0);
2504 case ixgbe_mac_82599EB
:
2505 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, 0xFFFF0000);
2506 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), ~0);
2507 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1), ~0);
2508 if (adapter
->num_vfs
> 32)
2509 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, 0);
2514 IXGBE_WRITE_FLUSH(&adapter
->hw
);
2515 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2517 for (i
= 0; i
< adapter
->num_msix_vectors
; i
++)
2518 synchronize_irq(adapter
->msix_entries
[i
].vector
);
2520 synchronize_irq(adapter
->pdev
->irq
);
2525 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2528 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter
*adapter
)
2530 struct ixgbe_hw
*hw
= &adapter
->hw
;
2532 IXGBE_WRITE_REG(hw
, IXGBE_EITR(0),
2533 EITR_INTS_PER_SEC_TO_REG(adapter
->rx_eitr_param
));
2535 ixgbe_set_ivar(adapter
, 0, 0, 0);
2536 ixgbe_set_ivar(adapter
, 1, 0, 0);
2538 map_vector_to_rxq(adapter
, 0, 0);
2539 map_vector_to_txq(adapter
, 0, 0);
2541 e_info(hw
, "Legacy interrupt IVAR setup done\n");
2545 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2546 * @adapter: board private structure
2547 * @ring: structure containing ring specific data
2549 * Configure the Tx descriptor ring after a reset.
2551 void ixgbe_configure_tx_ring(struct ixgbe_adapter
*adapter
,
2552 struct ixgbe_ring
*ring
)
2554 struct ixgbe_hw
*hw
= &adapter
->hw
;
2555 u64 tdba
= ring
->dma
;
2558 u16 reg_idx
= ring
->reg_idx
;
2560 /* disable queue to avoid issues while updating state */
2561 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(reg_idx
));
2562 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(reg_idx
),
2563 txdctl
& ~IXGBE_TXDCTL_ENABLE
);
2564 IXGBE_WRITE_FLUSH(hw
);
2566 IXGBE_WRITE_REG(hw
, IXGBE_TDBAL(reg_idx
),
2567 (tdba
& DMA_BIT_MASK(32)));
2568 IXGBE_WRITE_REG(hw
, IXGBE_TDBAH(reg_idx
), (tdba
>> 32));
2569 IXGBE_WRITE_REG(hw
, IXGBE_TDLEN(reg_idx
),
2570 ring
->count
* sizeof(union ixgbe_adv_tx_desc
));
2571 IXGBE_WRITE_REG(hw
, IXGBE_TDH(reg_idx
), 0);
2572 IXGBE_WRITE_REG(hw
, IXGBE_TDT(reg_idx
), 0);
2573 ring
->tail
= hw
->hw_addr
+ IXGBE_TDT(reg_idx
);
2575 /* configure fetching thresholds */
2576 if (adapter
->rx_itr_setting
== 0) {
2577 /* cannot set wthresh when itr==0 */
2578 txdctl
&= ~0x007F0000;
2580 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2581 txdctl
|= (8 << 16);
2583 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
2584 /* PThresh workaround for Tx hang with DFP enabled. */
2588 /* reinitialize flowdirector state */
2589 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) &&
2590 adapter
->atr_sample_rate
) {
2591 ring
->atr_sample_rate
= adapter
->atr_sample_rate
;
2592 ring
->atr_count
= 0;
2593 set_bit(__IXGBE_TX_FDIR_INIT_DONE
, &ring
->state
);
2595 ring
->atr_sample_rate
= 0;
2599 txdctl
|= IXGBE_TXDCTL_ENABLE
;
2600 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(reg_idx
), txdctl
);
2602 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2603 if (hw
->mac
.type
== ixgbe_mac_82598EB
&&
2604 !(IXGBE_READ_REG(hw
, IXGBE_LINKS
) & IXGBE_LINKS_UP
))
2607 /* poll to verify queue is enabled */
2610 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(reg_idx
));
2611 } while (--wait_loop
&& !(txdctl
& IXGBE_TXDCTL_ENABLE
));
2613 e_err(drv
, "Could not enable Tx Queue %d\n", reg_idx
);
2616 static void ixgbe_setup_mtqc(struct ixgbe_adapter
*adapter
)
2618 struct ixgbe_hw
*hw
= &adapter
->hw
;
2622 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2625 /* disable the arbiter while setting MTQC */
2626 rttdcs
= IXGBE_READ_REG(hw
, IXGBE_RTTDCS
);
2627 rttdcs
|= IXGBE_RTTDCS_ARBDIS
;
2628 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2630 /* set transmit pool layout */
2631 mask
= (IXGBE_FLAG_SRIOV_ENABLED
| IXGBE_FLAG_DCB_ENABLED
);
2632 switch (adapter
->flags
& mask
) {
2634 case (IXGBE_FLAG_SRIOV_ENABLED
):
2635 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
,
2636 (IXGBE_MTQC_VT_ENA
| IXGBE_MTQC_64VF
));
2639 case (IXGBE_FLAG_DCB_ENABLED
):
2640 /* We enable 8 traffic classes, DCB only */
2641 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
,
2642 (IXGBE_MTQC_RT_ENA
| IXGBE_MTQC_8TC_8TQ
));
2646 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
, IXGBE_MTQC_64Q_1PB
);
2650 /* re-enable the arbiter */
2651 rttdcs
&= ~IXGBE_RTTDCS_ARBDIS
;
2652 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2656 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2657 * @adapter: board private structure
2659 * Configure the Tx unit of the MAC after a reset.
2661 static void ixgbe_configure_tx(struct ixgbe_adapter
*adapter
)
2663 struct ixgbe_hw
*hw
= &adapter
->hw
;
2667 ixgbe_setup_mtqc(adapter
);
2669 if (hw
->mac
.type
!= ixgbe_mac_82598EB
) {
2670 /* DMATXCTL.EN must be before Tx queues are enabled */
2671 dmatxctl
= IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
);
2672 dmatxctl
|= IXGBE_DMATXCTL_TE
;
2673 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
, dmatxctl
);
2676 /* Setup the HW Tx Head and Tail descriptor pointers */
2677 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
2678 ixgbe_configure_tx_ring(adapter
, adapter
->tx_ring
[i
]);
2681 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2683 static void ixgbe_configure_srrctl(struct ixgbe_adapter
*adapter
,
2684 struct ixgbe_ring
*rx_ring
)
2687 int index
= rx_ring
->reg_idx
;
2689 switch (adapter
->hw
.mac
.type
) {
2690 case ixgbe_mac_82598EB
: {
2691 struct ixgbe_ring_feature
*feature
= adapter
->ring_feature
;
2692 const int mask
= feature
[RING_F_RSS
].mask
;
2693 index
= index
& mask
;
2696 case ixgbe_mac_82599EB
:
2701 srrctl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_SRRCTL(index
));
2703 srrctl
&= ~IXGBE_SRRCTL_BSIZEHDR_MASK
;
2704 srrctl
&= ~IXGBE_SRRCTL_BSIZEPKT_MASK
;
2705 if (adapter
->num_vfs
)
2706 srrctl
|= IXGBE_SRRCTL_DROP_EN
;
2708 srrctl
|= (IXGBE_RX_HDR_SIZE
<< IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT
) &
2709 IXGBE_SRRCTL_BSIZEHDR_MASK
;
2711 if (ring_is_ps_enabled(rx_ring
)) {
2712 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2713 srrctl
|= IXGBE_MAX_RXBUFFER
>> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2715 srrctl
|= (PAGE_SIZE
/ 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2717 srrctl
|= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS
;
2719 srrctl
|= ALIGN(rx_ring
->rx_buf_len
, 1024) >>
2720 IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2721 srrctl
|= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF
;
2724 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_SRRCTL(index
), srrctl
);
2727 static void ixgbe_setup_mrqc(struct ixgbe_adapter
*adapter
)
2729 struct ixgbe_hw
*hw
= &adapter
->hw
;
2730 static const u32 seed
[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2731 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2732 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2733 u32 mrqc
= 0, reta
= 0;
2738 /* Fill out hash function seeds */
2739 for (i
= 0; i
< 10; i
++)
2740 IXGBE_WRITE_REG(hw
, IXGBE_RSSRK(i
), seed
[i
]);
2742 /* Fill out redirection table */
2743 for (i
= 0, j
= 0; i
< 128; i
++, j
++) {
2744 if (j
== adapter
->ring_feature
[RING_F_RSS
].indices
)
2746 /* reta = 4-byte sliding window of
2747 * 0x00..(indices-1)(indices-1)00..etc. */
2748 reta
= (reta
<< 8) | (j
* 0x11);
2750 IXGBE_WRITE_REG(hw
, IXGBE_RETA(i
>> 2), reta
);
2753 /* Disable indicating checksum in descriptor, enables RSS hash */
2754 rxcsum
= IXGBE_READ_REG(hw
, IXGBE_RXCSUM
);
2755 rxcsum
|= IXGBE_RXCSUM_PCSD
;
2756 IXGBE_WRITE_REG(hw
, IXGBE_RXCSUM
, rxcsum
);
2758 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
2759 mask
= adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
;
2761 mask
= adapter
->flags
& (IXGBE_FLAG_RSS_ENABLED
2762 #ifdef CONFIG_IXGBE_DCB
2763 | IXGBE_FLAG_DCB_ENABLED
2765 | IXGBE_FLAG_SRIOV_ENABLED
2769 case (IXGBE_FLAG_RSS_ENABLED
):
2770 mrqc
= IXGBE_MRQC_RSSEN
;
2772 case (IXGBE_FLAG_SRIOV_ENABLED
):
2773 mrqc
= IXGBE_MRQC_VMDQEN
;
2775 #ifdef CONFIG_IXGBE_DCB
2776 case (IXGBE_FLAG_DCB_ENABLED
):
2777 mrqc
= IXGBE_MRQC_RT8TCEN
;
2779 #endif /* CONFIG_IXGBE_DCB */
2784 /* Perform hash on these packet types */
2785 mrqc
|= IXGBE_MRQC_RSS_FIELD_IPV4
2786 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2787 | IXGBE_MRQC_RSS_FIELD_IPV6
2788 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
;
2790 IXGBE_WRITE_REG(hw
, IXGBE_MRQC
, mrqc
);
2794 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2795 * @adapter: address of board private structure
2796 * @index: index of ring to set
2798 static void ixgbe_configure_rscctl(struct ixgbe_adapter
*adapter
,
2799 struct ixgbe_ring
*ring
)
2801 struct ixgbe_hw
*hw
= &adapter
->hw
;
2804 u16 reg_idx
= ring
->reg_idx
;
2806 if (!ring_is_rsc_enabled(ring
))
2809 rx_buf_len
= ring
->rx_buf_len
;
2810 rscctrl
= IXGBE_READ_REG(hw
, IXGBE_RSCCTL(reg_idx
));
2811 rscctrl
|= IXGBE_RSCCTL_RSCEN
;
2813 * we must limit the number of descriptors so that the
2814 * total size of max desc * buf_len is not greater
2817 if (ring_is_ps_enabled(ring
)) {
2818 #if (MAX_SKB_FRAGS > 16)
2819 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2820 #elif (MAX_SKB_FRAGS > 8)
2821 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2822 #elif (MAX_SKB_FRAGS > 4)
2823 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2825 rscctrl
|= IXGBE_RSCCTL_MAXDESC_1
;
2828 if (rx_buf_len
< IXGBE_RXBUFFER_4096
)
2829 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2830 else if (rx_buf_len
< IXGBE_RXBUFFER_8192
)
2831 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2833 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2835 IXGBE_WRITE_REG(hw
, IXGBE_RSCCTL(reg_idx
), rscctrl
);
2839 * ixgbe_set_uta - Set unicast filter table address
2840 * @adapter: board private structure
2842 * The unicast table address is a register array of 32-bit registers.
2843 * The table is meant to be used in a way similar to how the MTA is used
2844 * however due to certain limitations in the hardware it is necessary to
2845 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2846 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2848 static void ixgbe_set_uta(struct ixgbe_adapter
*adapter
)
2850 struct ixgbe_hw
*hw
= &adapter
->hw
;
2853 /* The UTA table only exists on 82599 hardware and newer */
2854 if (hw
->mac
.type
< ixgbe_mac_82599EB
)
2857 /* we only need to do this if VMDq is enabled */
2858 if (!(adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
))
2861 for (i
= 0; i
< 128; i
++)
2862 IXGBE_WRITE_REG(hw
, IXGBE_UTA(i
), ~0);
2865 #define IXGBE_MAX_RX_DESC_POLL 10
2866 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter
*adapter
,
2867 struct ixgbe_ring
*ring
)
2869 struct ixgbe_hw
*hw
= &adapter
->hw
;
2870 int reg_idx
= ring
->reg_idx
;
2871 int wait_loop
= IXGBE_MAX_RX_DESC_POLL
;
2874 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2875 if (hw
->mac
.type
== ixgbe_mac_82598EB
&&
2876 !(IXGBE_READ_REG(hw
, IXGBE_LINKS
) & IXGBE_LINKS_UP
))
2881 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
2882 } while (--wait_loop
&& !(rxdctl
& IXGBE_RXDCTL_ENABLE
));
2885 e_err(drv
, "RXDCTL.ENABLE on Rx queue %d not set within "
2886 "the polling period\n", reg_idx
);
2890 void ixgbe_configure_rx_ring(struct ixgbe_adapter
*adapter
,
2891 struct ixgbe_ring
*ring
)
2893 struct ixgbe_hw
*hw
= &adapter
->hw
;
2894 u64 rdba
= ring
->dma
;
2896 u16 reg_idx
= ring
->reg_idx
;
2898 /* disable queue to avoid issues while updating state */
2899 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
2900 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(reg_idx
),
2901 rxdctl
& ~IXGBE_RXDCTL_ENABLE
);
2902 IXGBE_WRITE_FLUSH(hw
);
2904 IXGBE_WRITE_REG(hw
, IXGBE_RDBAL(reg_idx
), (rdba
& DMA_BIT_MASK(32)));
2905 IXGBE_WRITE_REG(hw
, IXGBE_RDBAH(reg_idx
), (rdba
>> 32));
2906 IXGBE_WRITE_REG(hw
, IXGBE_RDLEN(reg_idx
),
2907 ring
->count
* sizeof(union ixgbe_adv_rx_desc
));
2908 IXGBE_WRITE_REG(hw
, IXGBE_RDH(reg_idx
), 0);
2909 IXGBE_WRITE_REG(hw
, IXGBE_RDT(reg_idx
), 0);
2910 ring
->tail
= hw
->hw_addr
+ IXGBE_RDT(reg_idx
);
2912 ixgbe_configure_srrctl(adapter
, ring
);
2913 ixgbe_configure_rscctl(adapter
, ring
);
2915 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
2917 * enable cache line friendly hardware writes:
2918 * PTHRESH=32 descriptors (half the internal cache),
2919 * this also removes ugly rx_no_buffer_count increment
2920 * HTHRESH=4 descriptors (to minimize latency on fetch)
2921 * WTHRESH=8 burst writeback up to two cache lines
2923 rxdctl
&= ~0x3FFFFF;
2927 /* enable receive descriptor ring */
2928 rxdctl
|= IXGBE_RXDCTL_ENABLE
;
2929 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(reg_idx
), rxdctl
);
2931 ixgbe_rx_desc_queue_enable(adapter
, ring
);
2932 ixgbe_alloc_rx_buffers(ring
, IXGBE_DESC_UNUSED(ring
));
2935 static void ixgbe_setup_psrtype(struct ixgbe_adapter
*adapter
)
2937 struct ixgbe_hw
*hw
= &adapter
->hw
;
2940 /* PSRTYPE must be initialized in non 82598 adapters */
2941 u32 psrtype
= IXGBE_PSRTYPE_TCPHDR
|
2942 IXGBE_PSRTYPE_UDPHDR
|
2943 IXGBE_PSRTYPE_IPV4HDR
|
2944 IXGBE_PSRTYPE_L2HDR
|
2945 IXGBE_PSRTYPE_IPV6HDR
;
2947 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2950 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
)
2951 psrtype
|= (adapter
->num_rx_queues_per_pool
<< 29);
2953 for (p
= 0; p
< adapter
->num_rx_pools
; p
++)
2954 IXGBE_WRITE_REG(hw
, IXGBE_PSRTYPE(adapter
->num_vfs
+ p
),
2958 static void ixgbe_configure_virtualization(struct ixgbe_adapter
*adapter
)
2960 struct ixgbe_hw
*hw
= &adapter
->hw
;
2963 u32 reg_offset
, vf_shift
;
2966 if (!(adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
))
2969 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
2970 vt_reg_bits
= IXGBE_VMD_CTL_VMDQ_EN
| IXGBE_VT_CTL_REPLEN
;
2971 vt_reg_bits
|= (adapter
->num_vfs
<< IXGBE_VT_CTL_POOL_SHIFT
);
2972 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
| vt_reg_bits
);
2974 vf_shift
= adapter
->num_vfs
% 32;
2975 reg_offset
= (adapter
->num_vfs
> 32) ? 1 : 0;
2977 /* Enable only the PF's pool for Tx/Rx */
2978 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(reg_offset
), (1 << vf_shift
));
2979 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(reg_offset
^ 1), 0);
2980 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(reg_offset
), (1 << vf_shift
));
2981 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(reg_offset
^ 1), 0);
2982 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, IXGBE_PFDTXGSWC_VT_LBEN
);
2984 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2985 hw
->mac
.ops
.set_vmdq(hw
, 0, adapter
->num_vfs
);
2988 * Set up VF register offsets for selected VT Mode,
2989 * i.e. 32 or 64 VFs for SR-IOV
2991 gcr_ext
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
2992 gcr_ext
|= IXGBE_GCR_EXT_MSIX_EN
;
2993 gcr_ext
|= IXGBE_GCR_EXT_VT_MODE_64
;
2994 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, gcr_ext
);
2996 /* enable Tx loopback for VF/PF communication */
2997 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, IXGBE_PFDTXGSWC_VT_LBEN
);
3000 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter
*adapter
)
3002 struct ixgbe_hw
*hw
= &adapter
->hw
;
3003 struct net_device
*netdev
= adapter
->netdev
;
3004 int max_frame
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
3006 struct ixgbe_ring
*rx_ring
;
3010 /* Decide whether to use packet split mode or not */
3011 /* Do not use packet split if we're in SR-IOV Mode */
3012 if (!adapter
->num_vfs
)
3013 adapter
->flags
|= IXGBE_FLAG_RX_PS_ENABLED
;
3015 /* Set the RX buffer length according to the mode */
3016 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
) {
3017 rx_buf_len
= IXGBE_RX_HDR_SIZE
;
3019 if (!(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) &&
3020 (netdev
->mtu
<= ETH_DATA_LEN
))
3021 rx_buf_len
= MAXIMUM_ETHERNET_VLAN_SIZE
;
3023 rx_buf_len
= ALIGN(max_frame
+ VLAN_HLEN
, 1024);
3027 /* adjust max frame to be able to do baby jumbo for FCoE */
3028 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) &&
3029 (max_frame
< IXGBE_FCOE_JUMBO_FRAME_SIZE
))
3030 max_frame
= IXGBE_FCOE_JUMBO_FRAME_SIZE
;
3032 #endif /* IXGBE_FCOE */
3033 mhadd
= IXGBE_READ_REG(hw
, IXGBE_MHADD
);
3034 if (max_frame
!= (mhadd
>> IXGBE_MHADD_MFS_SHIFT
)) {
3035 mhadd
&= ~IXGBE_MHADD_MFS_MASK
;
3036 mhadd
|= max_frame
<< IXGBE_MHADD_MFS_SHIFT
;
3038 IXGBE_WRITE_REG(hw
, IXGBE_MHADD
, mhadd
);
3041 hlreg0
= IXGBE_READ_REG(hw
, IXGBE_HLREG0
);
3042 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3043 hlreg0
|= IXGBE_HLREG0_JUMBOEN
;
3044 IXGBE_WRITE_REG(hw
, IXGBE_HLREG0
, hlreg0
);
3047 * Setup the HW Rx Head and Tail Descriptor Pointers and
3048 * the Base and Length of the Rx Descriptor Ring
3050 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3051 rx_ring
= adapter
->rx_ring
[i
];
3052 rx_ring
->rx_buf_len
= rx_buf_len
;
3054 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
)
3055 set_ring_ps_enabled(rx_ring
);
3057 clear_ring_ps_enabled(rx_ring
);
3059 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
)
3060 set_ring_rsc_enabled(rx_ring
);
3062 clear_ring_rsc_enabled(rx_ring
);
3065 if (netdev
->features
& NETIF_F_FCOE_MTU
) {
3066 struct ixgbe_ring_feature
*f
;
3067 f
= &adapter
->ring_feature
[RING_F_FCOE
];
3068 if ((i
>= f
->mask
) && (i
< f
->mask
+ f
->indices
)) {
3069 clear_ring_ps_enabled(rx_ring
);
3070 if (rx_buf_len
< IXGBE_FCOE_JUMBO_FRAME_SIZE
)
3071 rx_ring
->rx_buf_len
=
3072 IXGBE_FCOE_JUMBO_FRAME_SIZE
;
3073 } else if (!ring_is_rsc_enabled(rx_ring
) &&
3074 !ring_is_ps_enabled(rx_ring
)) {
3075 rx_ring
->rx_buf_len
=
3076 IXGBE_FCOE_JUMBO_FRAME_SIZE
;
3079 #endif /* IXGBE_FCOE */
3083 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter
*adapter
)
3085 struct ixgbe_hw
*hw
= &adapter
->hw
;
3086 u32 rdrxctl
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
3088 switch (hw
->mac
.type
) {
3089 case ixgbe_mac_82598EB
:
3091 * For VMDq support of different descriptor types or
3092 * buffer sizes through the use of multiple SRRCTL
3093 * registers, RDRXCTL.MVMEN must be set to 1
3095 * also, the manual doesn't mention it clearly but DCA hints
3096 * will only use queue 0's tags unless this bit is set. Side
3097 * effects of setting this bit are only that SRRCTL must be
3098 * fully programmed [0..15]
3100 rdrxctl
|= IXGBE_RDRXCTL_MVMEN
;
3102 case ixgbe_mac_82599EB
:
3103 /* Disable RSC for ACK packets */
3104 IXGBE_WRITE_REG(hw
, IXGBE_RSCDBU
,
3105 (IXGBE_RSCDBU_RSCACKDIS
| IXGBE_READ_REG(hw
, IXGBE_RSCDBU
)));
3106 rdrxctl
&= ~IXGBE_RDRXCTL_RSCFRSTSIZE
;
3107 /* hardware requires some bits to be set by default */
3108 rdrxctl
|= (IXGBE_RDRXCTL_RSCACKC
| IXGBE_RDRXCTL_FCOE_WRFIX
);
3109 rdrxctl
|= IXGBE_RDRXCTL_CRCSTRIP
;
3112 /* We should do nothing since we don't know this hardware */
3116 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, rdrxctl
);
3120 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3121 * @adapter: board private structure
3123 * Configure the Rx unit of the MAC after a reset.
3125 static void ixgbe_configure_rx(struct ixgbe_adapter
*adapter
)
3127 struct ixgbe_hw
*hw
= &adapter
->hw
;
3131 /* disable receives while setting up the descriptors */
3132 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
3133 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
3135 ixgbe_setup_psrtype(adapter
);
3136 ixgbe_setup_rdrxctl(adapter
);
3138 /* Program registers for the distribution of queues */
3139 ixgbe_setup_mrqc(adapter
);
3141 ixgbe_set_uta(adapter
);
3143 /* set_rx_buffer_len must be called before ring initialization */
3144 ixgbe_set_rx_buffer_len(adapter
);
3147 * Setup the HW Rx Head and Tail Descriptor Pointers and
3148 * the Base and Length of the Rx Descriptor Ring
3150 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3151 ixgbe_configure_rx_ring(adapter
, adapter
->rx_ring
[i
]);
3153 /* disable drop enable for 82598 parts */
3154 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3155 rxctrl
|= IXGBE_RXCTRL_DMBYPS
;
3157 /* enable all receives */
3158 rxctrl
|= IXGBE_RXCTRL_RXEN
;
3159 hw
->mac
.ops
.enable_rx_dma(hw
, rxctrl
);
3162 static void ixgbe_vlan_rx_add_vid(struct net_device
*netdev
, u16 vid
)
3164 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3165 struct ixgbe_hw
*hw
= &adapter
->hw
;
3166 int pool_ndx
= adapter
->num_vfs
;
3168 /* add VID to filter table */
3169 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, true);
3170 set_bit(vid
, adapter
->active_vlans
);
3173 static void ixgbe_vlan_rx_kill_vid(struct net_device
*netdev
, u16 vid
)
3175 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3176 struct ixgbe_hw
*hw
= &adapter
->hw
;
3177 int pool_ndx
= adapter
->num_vfs
;
3179 /* remove VID from filter table */
3180 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, false);
3181 clear_bit(vid
, adapter
->active_vlans
);
3185 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3186 * @adapter: driver data
3188 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter
*adapter
)
3190 struct ixgbe_hw
*hw
= &adapter
->hw
;
3193 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3194 vlnctrl
&= ~(IXGBE_VLNCTRL_VFE
| IXGBE_VLNCTRL_CFIEN
);
3195 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3199 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3200 * @adapter: driver data
3202 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter
*adapter
)
3204 struct ixgbe_hw
*hw
= &adapter
->hw
;
3207 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3208 vlnctrl
|= IXGBE_VLNCTRL_VFE
;
3209 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
3210 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3214 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3215 * @adapter: driver data
3217 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter
*adapter
)
3219 struct ixgbe_hw
*hw
= &adapter
->hw
;
3223 switch (hw
->mac
.type
) {
3224 case ixgbe_mac_82598EB
:
3225 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3226 vlnctrl
&= ~IXGBE_VLNCTRL_VME
;
3227 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3229 case ixgbe_mac_82599EB
:
3230 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3231 j
= adapter
->rx_ring
[i
]->reg_idx
;
3232 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
3233 vlnctrl
&= ~IXGBE_RXDCTL_VME
;
3234 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
3243 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3244 * @adapter: driver data
3246 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter
*adapter
)
3248 struct ixgbe_hw
*hw
= &adapter
->hw
;
3252 switch (hw
->mac
.type
) {
3253 case ixgbe_mac_82598EB
:
3254 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3255 vlnctrl
|= IXGBE_VLNCTRL_VME
;
3256 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3258 case ixgbe_mac_82599EB
:
3259 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3260 j
= adapter
->rx_ring
[i
]->reg_idx
;
3261 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
3262 vlnctrl
|= IXGBE_RXDCTL_VME
;
3263 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
3271 static void ixgbe_restore_vlan(struct ixgbe_adapter
*adapter
)
3275 ixgbe_vlan_rx_add_vid(adapter
->netdev
, 0);
3277 for_each_set_bit(vid
, adapter
->active_vlans
, VLAN_N_VID
)
3278 ixgbe_vlan_rx_add_vid(adapter
->netdev
, vid
);
3282 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3283 * @netdev: network interface device structure
3285 * Writes unicast address list to the RAR table.
3286 * Returns: -ENOMEM on failure/insufficient address space
3287 * 0 on no addresses written
3288 * X on writing X addresses to the RAR table
3290 static int ixgbe_write_uc_addr_list(struct net_device
*netdev
)
3292 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3293 struct ixgbe_hw
*hw
= &adapter
->hw
;
3294 unsigned int vfn
= adapter
->num_vfs
;
3295 unsigned int rar_entries
= hw
->mac
.num_rar_entries
- (vfn
+ 1);
3298 /* return ENOMEM indicating insufficient memory for addresses */
3299 if (netdev_uc_count(netdev
) > rar_entries
)
3302 if (!netdev_uc_empty(netdev
) && rar_entries
) {
3303 struct netdev_hw_addr
*ha
;
3304 /* return error if we do not support writing to RAR table */
3305 if (!hw
->mac
.ops
.set_rar
)
3308 netdev_for_each_uc_addr(ha
, netdev
) {
3311 hw
->mac
.ops
.set_rar(hw
, rar_entries
--, ha
->addr
,
3316 /* write the addresses in reverse order to avoid write combining */
3317 for (; rar_entries
> 0 ; rar_entries
--)
3318 hw
->mac
.ops
.clear_rar(hw
, rar_entries
);
3324 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3325 * @netdev: network interface device structure
3327 * The set_rx_method entry point is called whenever the unicast/multicast
3328 * address list or the network interface flags are updated. This routine is
3329 * responsible for configuring the hardware for proper unicast, multicast and
3332 void ixgbe_set_rx_mode(struct net_device
*netdev
)
3334 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3335 struct ixgbe_hw
*hw
= &adapter
->hw
;
3336 u32 fctrl
, vmolr
= IXGBE_VMOLR_BAM
| IXGBE_VMOLR_AUPE
;
3339 /* Check for Promiscuous and All Multicast modes */
3341 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
3343 /* set all bits that we expect to always be set */
3344 fctrl
|= IXGBE_FCTRL_BAM
;
3345 fctrl
|= IXGBE_FCTRL_DPF
; /* discard pause frames when FC enabled */
3346 fctrl
|= IXGBE_FCTRL_PMCF
;
3348 /* clear the bits we are changing the status of */
3349 fctrl
&= ~(IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
3351 if (netdev
->flags
& IFF_PROMISC
) {
3352 hw
->addr_ctrl
.user_set_promisc
= true;
3353 fctrl
|= (IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
3354 vmolr
|= (IXGBE_VMOLR_ROPE
| IXGBE_VMOLR_MPE
);
3355 /* don't hardware filter vlans in promisc mode */
3356 ixgbe_vlan_filter_disable(adapter
);
3358 if (netdev
->flags
& IFF_ALLMULTI
) {
3359 fctrl
|= IXGBE_FCTRL_MPE
;
3360 vmolr
|= IXGBE_VMOLR_MPE
;
3363 * Write addresses to the MTA, if the attempt fails
3364 * then we should just turn on promiscous mode so
3365 * that we can at least receive multicast traffic
3367 hw
->mac
.ops
.update_mc_addr_list(hw
, netdev
);
3368 vmolr
|= IXGBE_VMOLR_ROMPE
;
3370 ixgbe_vlan_filter_enable(adapter
);
3371 hw
->addr_ctrl
.user_set_promisc
= false;
3373 * Write addresses to available RAR registers, if there is not
3374 * sufficient space to store all the addresses then enable
3375 * unicast promiscous mode
3377 count
= ixgbe_write_uc_addr_list(netdev
);
3379 fctrl
|= IXGBE_FCTRL_UPE
;
3380 vmolr
|= IXGBE_VMOLR_ROPE
;
3384 if (adapter
->num_vfs
) {
3385 ixgbe_restore_vf_multicasts(adapter
);
3386 vmolr
|= IXGBE_READ_REG(hw
, IXGBE_VMOLR(adapter
->num_vfs
)) &
3387 ~(IXGBE_VMOLR_MPE
| IXGBE_VMOLR_ROMPE
|
3389 IXGBE_WRITE_REG(hw
, IXGBE_VMOLR(adapter
->num_vfs
), vmolr
);
3392 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
3394 if (netdev
->features
& NETIF_F_HW_VLAN_RX
)
3395 ixgbe_vlan_strip_enable(adapter
);
3397 ixgbe_vlan_strip_disable(adapter
);
3400 static void ixgbe_napi_enable_all(struct ixgbe_adapter
*adapter
)
3403 struct ixgbe_q_vector
*q_vector
;
3404 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3406 /* legacy and MSI only use one vector */
3407 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
3410 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
3411 struct napi_struct
*napi
;
3412 q_vector
= adapter
->q_vector
[q_idx
];
3413 napi
= &q_vector
->napi
;
3414 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3415 if (!q_vector
->rxr_count
|| !q_vector
->txr_count
) {
3416 if (q_vector
->txr_count
== 1)
3417 napi
->poll
= &ixgbe_clean_txonly
;
3418 else if (q_vector
->rxr_count
== 1)
3419 napi
->poll
= &ixgbe_clean_rxonly
;
3427 static void ixgbe_napi_disable_all(struct ixgbe_adapter
*adapter
)
3430 struct ixgbe_q_vector
*q_vector
;
3431 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3433 /* legacy and MSI only use one vector */
3434 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
3437 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
3438 q_vector
= adapter
->q_vector
[q_idx
];
3439 napi_disable(&q_vector
->napi
);
3443 #ifdef CONFIG_IXGBE_DCB
3445 * ixgbe_configure_dcb - Configure DCB hardware
3446 * @adapter: ixgbe adapter struct
3448 * This is called by the driver on open to configure the DCB hardware.
3449 * This is also called by the gennetlink interface when reconfiguring
3452 static void ixgbe_configure_dcb(struct ixgbe_adapter
*adapter
)
3454 struct ixgbe_hw
*hw
= &adapter
->hw
;
3455 int max_frame
= adapter
->netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
3457 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)) {
3458 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3459 netif_set_gso_max_size(adapter
->netdev
, 65536);
3463 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3464 netif_set_gso_max_size(adapter
->netdev
, 32768);
3467 if (adapter
->netdev
->features
& NETIF_F_FCOE_MTU
)
3468 max_frame
= max(max_frame
, IXGBE_FCOE_JUMBO_FRAME_SIZE
);
3471 ixgbe_dcb_calculate_tc_credits(hw
, &adapter
->dcb_cfg
, max_frame
,
3473 ixgbe_dcb_calculate_tc_credits(hw
, &adapter
->dcb_cfg
, max_frame
,
3476 /* Enable VLAN tag insert/strip */
3477 adapter
->netdev
->features
|= NETIF_F_HW_VLAN_RX
;
3479 hw
->mac
.ops
.set_vfta(&adapter
->hw
, 0, 0, true);
3481 /* reconfigure the hardware */
3482 ixgbe_dcb_hw_config(hw
, &adapter
->dcb_cfg
);
3486 static void ixgbe_configure(struct ixgbe_adapter
*adapter
)
3488 struct net_device
*netdev
= adapter
->netdev
;
3489 struct ixgbe_hw
*hw
= &adapter
->hw
;
3492 #ifdef CONFIG_IXGBE_DCB
3493 ixgbe_configure_dcb(adapter
);
3496 ixgbe_set_rx_mode(netdev
);
3497 ixgbe_restore_vlan(adapter
);
3500 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
3501 ixgbe_configure_fcoe(adapter
);
3503 #endif /* IXGBE_FCOE */
3504 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
3505 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3506 adapter
->tx_ring
[i
]->atr_sample_rate
=
3507 adapter
->atr_sample_rate
;
3508 ixgbe_init_fdir_signature_82599(hw
, adapter
->fdir_pballoc
);
3509 } else if (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
) {
3510 ixgbe_init_fdir_perfect_82599(hw
, adapter
->fdir_pballoc
);
3512 ixgbe_configure_virtualization(adapter
);
3514 ixgbe_configure_tx(adapter
);
3515 ixgbe_configure_rx(adapter
);
3518 static inline bool ixgbe_is_sfp(struct ixgbe_hw
*hw
)
3520 switch (hw
->phy
.type
) {
3521 case ixgbe_phy_sfp_avago
:
3522 case ixgbe_phy_sfp_ftl
:
3523 case ixgbe_phy_sfp_intel
:
3524 case ixgbe_phy_sfp_unknown
:
3525 case ixgbe_phy_sfp_passive_tyco
:
3526 case ixgbe_phy_sfp_passive_unknown
:
3527 case ixgbe_phy_sfp_active_unknown
:
3528 case ixgbe_phy_sfp_ftl_active
:
3536 * ixgbe_sfp_link_config - set up SFP+ link
3537 * @adapter: pointer to private adapter struct
3539 static void ixgbe_sfp_link_config(struct ixgbe_adapter
*adapter
)
3541 struct ixgbe_hw
*hw
= &adapter
->hw
;
3543 if (hw
->phy
.multispeed_fiber
) {
3545 * In multispeed fiber setups, the device may not have
3546 * had a physical connection when the driver loaded.
3547 * If that's the case, the initial link configuration
3548 * couldn't get the MAC into 10G or 1G mode, so we'll
3549 * never have a link status change interrupt fire.
3550 * We need to try and force an autonegotiation
3551 * session, then bring up link.
3553 hw
->mac
.ops
.setup_sfp(hw
);
3554 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_LINK_TASK
))
3555 schedule_work(&adapter
->multispeed_fiber_task
);
3558 * Direct Attach Cu and non-multispeed fiber modules
3559 * still need to be configured properly prior to
3562 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_MOD_TASK
))
3563 schedule_work(&adapter
->sfp_config_module_task
);
3568 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3569 * @hw: pointer to private hardware struct
3571 * Returns 0 on success, negative on failure
3573 static int ixgbe_non_sfp_link_config(struct ixgbe_hw
*hw
)
3576 bool negotiation
, link_up
= false;
3577 u32 ret
= IXGBE_ERR_LINK_SETUP
;
3579 if (hw
->mac
.ops
.check_link
)
3580 ret
= hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
3585 if (hw
->mac
.ops
.get_link_capabilities
)
3586 ret
= hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
,
3591 if (hw
->mac
.ops
.setup_link
)
3592 ret
= hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, link_up
);
3597 static void ixgbe_setup_gpie(struct ixgbe_adapter
*adapter
)
3599 struct ixgbe_hw
*hw
= &adapter
->hw
;
3602 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3603 gpie
= IXGBE_GPIE_MSIX_MODE
| IXGBE_GPIE_PBA_SUPPORT
|
3605 gpie
|= IXGBE_GPIE_EIAME
;
3607 * use EIAM to auto-mask when MSI-X interrupt is asserted
3608 * this saves a register write for every interrupt
3610 switch (hw
->mac
.type
) {
3611 case ixgbe_mac_82598EB
:
3612 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
3615 case ixgbe_mac_82599EB
:
3616 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3617 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3621 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3622 * specifically only auto mask tx and rx interrupts */
3623 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
3626 /* XXX: to interrupt immediately for EICS writes, enable this */
3627 /* gpie |= IXGBE_GPIE_EIMEN; */
3629 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
3630 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
3631 gpie
|= IXGBE_GPIE_VTMODE_64
;
3634 /* Enable fan failure interrupt */
3635 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
)
3636 gpie
|= IXGBE_SDP1_GPIEN
;
3638 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
3639 gpie
|= IXGBE_SDP1_GPIEN
;
3640 gpie
|= IXGBE_SDP2_GPIEN
;
3642 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
3645 static int ixgbe_up_complete(struct ixgbe_adapter
*adapter
)
3647 struct ixgbe_hw
*hw
= &adapter
->hw
;
3651 ixgbe_get_hw_control(adapter
);
3652 ixgbe_setup_gpie(adapter
);
3654 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
3655 ixgbe_configure_msix(adapter
);
3657 ixgbe_configure_msi_and_legacy(adapter
);
3659 /* enable the optics */
3660 if (hw
->phy
.multispeed_fiber
)
3661 hw
->mac
.ops
.enable_tx_laser(hw
);
3663 clear_bit(__IXGBE_DOWN
, &adapter
->state
);
3664 ixgbe_napi_enable_all(adapter
);
3666 if (ixgbe_is_sfp(hw
)) {
3667 ixgbe_sfp_link_config(adapter
);
3669 err
= ixgbe_non_sfp_link_config(hw
);
3671 e_err(probe
, "link_config FAILED %d\n", err
);
3674 /* clear any pending interrupts, may auto mask */
3675 IXGBE_READ_REG(hw
, IXGBE_EICR
);
3676 ixgbe_irq_enable(adapter
, true, true);
3679 * If this adapter has a fan, check to see if we had a failure
3680 * before we enabled the interrupt.
3682 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
3683 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
3684 if (esdp
& IXGBE_ESDP_SDP1
)
3685 e_crit(drv
, "Fan has stopped, replace the adapter\n");
3689 * For hot-pluggable SFP+ devices, a new SFP+ module may have
3690 * arrived before interrupts were enabled but after probe. Such
3691 * devices wouldn't have their type identified yet. We need to
3692 * kick off the SFP+ module setup first, then try to bring up link.
3693 * If we're not hot-pluggable SFP+, we just need to configure link
3696 if (hw
->phy
.type
== ixgbe_phy_unknown
)
3697 schedule_work(&adapter
->sfp_config_module_task
);
3699 /* enable transmits */
3700 netif_tx_start_all_queues(adapter
->netdev
);
3702 /* bring the link up in the watchdog, this could race with our first
3703 * link up interrupt but shouldn't be a problem */
3704 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
3705 adapter
->link_check_timeout
= jiffies
;
3706 mod_timer(&adapter
->watchdog_timer
, jiffies
);
3708 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3709 ctrl_ext
= IXGBE_READ_REG(hw
, IXGBE_CTRL_EXT
);
3710 ctrl_ext
|= IXGBE_CTRL_EXT_PFRSTD
;
3711 IXGBE_WRITE_REG(hw
, IXGBE_CTRL_EXT
, ctrl_ext
);
3716 void ixgbe_reinit_locked(struct ixgbe_adapter
*adapter
)
3718 WARN_ON(in_interrupt());
3719 while (test_and_set_bit(__IXGBE_RESETTING
, &adapter
->state
))
3721 ixgbe_down(adapter
);
3723 * If SR-IOV enabled then wait a bit before bringing the adapter
3724 * back up to give the VFs time to respond to the reset. The
3725 * two second wait is based upon the watchdog timer cycle in
3728 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
3731 clear_bit(__IXGBE_RESETTING
, &adapter
->state
);
3734 int ixgbe_up(struct ixgbe_adapter
*adapter
)
3736 /* hardware has been reset, we need to reload some things */
3737 ixgbe_configure(adapter
);
3739 return ixgbe_up_complete(adapter
);
3742 void ixgbe_reset(struct ixgbe_adapter
*adapter
)
3744 struct ixgbe_hw
*hw
= &adapter
->hw
;
3747 err
= hw
->mac
.ops
.init_hw(hw
);
3750 case IXGBE_ERR_SFP_NOT_PRESENT
:
3752 case IXGBE_ERR_MASTER_REQUESTS_PENDING
:
3753 e_dev_err("master disable timed out\n");
3755 case IXGBE_ERR_EEPROM_VERSION
:
3756 /* We are running on a pre-production device, log a warning */
3757 e_dev_warn("This device is a pre-production adapter/LOM. "
3758 "Please be aware there may be issuesassociated with "
3759 "your hardware. If you are experiencing problems "
3760 "please contact your Intel or hardware "
3761 "representative who provided you with this "
3765 e_dev_err("Hardware Error: %d\n", err
);
3768 /* reprogram the RAR[0] in case user changed it. */
3769 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
3774 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3775 * @rx_ring: ring to free buffers from
3777 static void ixgbe_clean_rx_ring(struct ixgbe_ring
*rx_ring
)
3779 struct device
*dev
= rx_ring
->dev
;
3783 /* ring already cleared, nothing to do */
3784 if (!rx_ring
->rx_buffer_info
)
3787 /* Free all the Rx ring sk_buffs */
3788 for (i
= 0; i
< rx_ring
->count
; i
++) {
3789 struct ixgbe_rx_buffer
*rx_buffer_info
;
3791 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
3792 if (rx_buffer_info
->dma
) {
3793 dma_unmap_single(rx_ring
->dev
, rx_buffer_info
->dma
,
3794 rx_ring
->rx_buf_len
,
3796 rx_buffer_info
->dma
= 0;
3798 if (rx_buffer_info
->skb
) {
3799 struct sk_buff
*skb
= rx_buffer_info
->skb
;
3800 rx_buffer_info
->skb
= NULL
;
3802 struct sk_buff
*this = skb
;
3803 if (IXGBE_RSC_CB(this)->delay_unmap
) {
3804 dma_unmap_single(dev
,
3805 IXGBE_RSC_CB(this)->dma
,
3806 rx_ring
->rx_buf_len
,
3808 IXGBE_RSC_CB(this)->dma
= 0;
3809 IXGBE_RSC_CB(skb
)->delay_unmap
= false;
3812 dev_kfree_skb(this);
3815 if (!rx_buffer_info
->page
)
3817 if (rx_buffer_info
->page_dma
) {
3818 dma_unmap_page(dev
, rx_buffer_info
->page_dma
,
3819 PAGE_SIZE
/ 2, DMA_FROM_DEVICE
);
3820 rx_buffer_info
->page_dma
= 0;
3822 put_page(rx_buffer_info
->page
);
3823 rx_buffer_info
->page
= NULL
;
3824 rx_buffer_info
->page_offset
= 0;
3827 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
3828 memset(rx_ring
->rx_buffer_info
, 0, size
);
3830 /* Zero out the descriptor ring */
3831 memset(rx_ring
->desc
, 0, rx_ring
->size
);
3833 rx_ring
->next_to_clean
= 0;
3834 rx_ring
->next_to_use
= 0;
3838 * ixgbe_clean_tx_ring - Free Tx Buffers
3839 * @tx_ring: ring to be cleaned
3841 static void ixgbe_clean_tx_ring(struct ixgbe_ring
*tx_ring
)
3843 struct ixgbe_tx_buffer
*tx_buffer_info
;
3847 /* ring already cleared, nothing to do */
3848 if (!tx_ring
->tx_buffer_info
)
3851 /* Free all the Tx ring sk_buffs */
3852 for (i
= 0; i
< tx_ring
->count
; i
++) {
3853 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
3854 ixgbe_unmap_and_free_tx_resource(tx_ring
, tx_buffer_info
);
3857 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
3858 memset(tx_ring
->tx_buffer_info
, 0, size
);
3860 /* Zero out the descriptor ring */
3861 memset(tx_ring
->desc
, 0, tx_ring
->size
);
3863 tx_ring
->next_to_use
= 0;
3864 tx_ring
->next_to_clean
= 0;
3868 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3869 * @adapter: board private structure
3871 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter
*adapter
)
3875 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3876 ixgbe_clean_rx_ring(adapter
->rx_ring
[i
]);
3880 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3881 * @adapter: board private structure
3883 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter
*adapter
)
3887 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3888 ixgbe_clean_tx_ring(adapter
->tx_ring
[i
]);
3891 void ixgbe_down(struct ixgbe_adapter
*adapter
)
3893 struct net_device
*netdev
= adapter
->netdev
;
3894 struct ixgbe_hw
*hw
= &adapter
->hw
;
3898 int num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3900 /* signal that we are down to the interrupt handler */
3901 set_bit(__IXGBE_DOWN
, &adapter
->state
);
3903 /* disable receive for all VFs and wait one second */
3904 if (adapter
->num_vfs
) {
3905 /* ping all the active vfs to let them know we are going down */
3906 ixgbe_ping_all_vfs(adapter
);
3908 /* Disable all VFTE/VFRE TX/RX */
3909 ixgbe_disable_tx_rx(adapter
);
3911 /* Mark all the VFs as inactive */
3912 for (i
= 0 ; i
< adapter
->num_vfs
; i
++)
3913 adapter
->vfinfo
[i
].clear_to_send
= 0;
3916 /* disable receives */
3917 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
3918 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
3920 IXGBE_WRITE_FLUSH(hw
);
3923 netif_tx_stop_all_queues(netdev
);
3925 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
3926 del_timer_sync(&adapter
->sfp_timer
);
3927 del_timer_sync(&adapter
->watchdog_timer
);
3928 cancel_work_sync(&adapter
->watchdog_task
);
3930 netif_carrier_off(netdev
);
3931 netif_tx_disable(netdev
);
3933 ixgbe_irq_disable(adapter
);
3935 ixgbe_napi_disable_all(adapter
);
3937 /* Cleanup the affinity_hint CPU mask memory and callback */
3938 for (i
= 0; i
< num_q_vectors
; i
++) {
3939 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
3940 /* clear the affinity_mask in the IRQ descriptor */
3941 irq_set_affinity_hint(adapter
->msix_entries
[i
]. vector
, NULL
);
3942 /* release the CPU mask memory */
3943 free_cpumask_var(q_vector
->affinity_mask
);
3946 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
3947 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
3948 cancel_work_sync(&adapter
->fdir_reinit_task
);
3950 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
)
3951 cancel_work_sync(&adapter
->check_overtemp_task
);
3953 /* disable transmits in the hardware now that interrupts are off */
3954 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
3955 j
= adapter
->tx_ring
[i
]->reg_idx
;
3956 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
3957 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
),
3958 (txdctl
& ~IXGBE_TXDCTL_ENABLE
));
3960 /* Disable the Tx DMA engine on 82599 */
3961 switch (hw
->mac
.type
) {
3962 case ixgbe_mac_82599EB
:
3963 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
,
3964 (IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
) &
3965 ~IXGBE_DMATXCTL_TE
));
3971 /* power down the optics */
3972 if (hw
->phy
.multispeed_fiber
)
3973 hw
->mac
.ops
.disable_tx_laser(hw
);
3975 /* clear n-tuple filters that are cached */
3976 ethtool_ntuple_flush(netdev
);
3978 if (!pci_channel_offline(adapter
->pdev
))
3979 ixgbe_reset(adapter
);
3980 ixgbe_clean_all_tx_rings(adapter
);
3981 ixgbe_clean_all_rx_rings(adapter
);
3983 #ifdef CONFIG_IXGBE_DCA
3984 /* since we reset the hardware DCA settings were cleared */
3985 ixgbe_setup_dca(adapter
);
3990 * ixgbe_poll - NAPI Rx polling callback
3991 * @napi: structure for representing this polling device
3992 * @budget: how many packets driver is allowed to clean
3994 * This function is used for legacy and MSI, NAPI mode
3996 static int ixgbe_poll(struct napi_struct
*napi
, int budget
)
3998 struct ixgbe_q_vector
*q_vector
=
3999 container_of(napi
, struct ixgbe_q_vector
, napi
);
4000 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
4001 int tx_clean_complete
, work_done
= 0;
4003 #ifdef CONFIG_IXGBE_DCA
4004 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
4005 ixgbe_update_dca(q_vector
);
4008 tx_clean_complete
= ixgbe_clean_tx_irq(q_vector
, adapter
->tx_ring
[0]);
4009 ixgbe_clean_rx_irq(q_vector
, adapter
->rx_ring
[0], &work_done
, budget
);
4011 if (!tx_clean_complete
)
4014 /* If budget not fully consumed, exit the polling mode */
4015 if (work_done
< budget
) {
4016 napi_complete(napi
);
4017 if (adapter
->rx_itr_setting
& 1)
4018 ixgbe_set_itr(adapter
);
4019 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
4020 ixgbe_irq_enable_queues(adapter
, IXGBE_EIMS_RTX_QUEUE
);
4026 * ixgbe_tx_timeout - Respond to a Tx Hang
4027 * @netdev: network interface device structure
4029 static void ixgbe_tx_timeout(struct net_device
*netdev
)
4031 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4033 /* Do the reset outside of interrupt context */
4034 schedule_work(&adapter
->reset_task
);
4037 static void ixgbe_reset_task(struct work_struct
*work
)
4039 struct ixgbe_adapter
*adapter
;
4040 adapter
= container_of(work
, struct ixgbe_adapter
, reset_task
);
4042 /* If we're already down or resetting, just bail */
4043 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
4044 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
4047 adapter
->tx_timeout_count
++;
4049 ixgbe_dump(adapter
);
4050 netdev_err(adapter
->netdev
, "Reset adapter\n");
4051 ixgbe_reinit_locked(adapter
);
4054 #ifdef CONFIG_IXGBE_DCB
4055 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter
*adapter
)
4058 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_DCB
];
4060 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
))
4064 adapter
->num_rx_queues
= f
->indices
;
4065 adapter
->num_tx_queues
= f
->indices
;
4073 * ixgbe_set_rss_queues: Allocate queues for RSS
4074 * @adapter: board private structure to initialize
4076 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4077 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4080 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter
*adapter
)
4083 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_RSS
];
4085 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4087 adapter
->num_rx_queues
= f
->indices
;
4088 adapter
->num_tx_queues
= f
->indices
;
4098 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4099 * @adapter: board private structure to initialize
4101 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4102 * to the original CPU that initiated the Tx session. This runs in addition
4103 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4104 * Rx load across CPUs using RSS.
4107 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter
*adapter
)
4110 struct ixgbe_ring_feature
*f_fdir
= &adapter
->ring_feature
[RING_F_FDIR
];
4112 f_fdir
->indices
= min((int)num_online_cpus(), f_fdir
->indices
);
4115 /* Flow Director must have RSS enabled */
4116 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
&&
4117 ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
4118 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)))) {
4119 adapter
->num_tx_queues
= f_fdir
->indices
;
4120 adapter
->num_rx_queues
= f_fdir
->indices
;
4123 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4124 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
4131 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4132 * @adapter: board private structure to initialize
4134 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4135 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4136 * rx queues out of the max number of rx queues, instead, it is used as the
4137 * index of the first rx queue used by FCoE.
4140 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter
*adapter
)
4143 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
4145 f
->indices
= min((int)num_online_cpus(), f
->indices
);
4146 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
4147 adapter
->num_rx_queues
= 1;
4148 adapter
->num_tx_queues
= 1;
4149 #ifdef CONFIG_IXGBE_DCB
4150 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
4151 e_info(probe
, "FCoE enabled with DCB\n");
4152 ixgbe_set_dcb_queues(adapter
);
4155 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4156 e_info(probe
, "FCoE enabled with RSS\n");
4157 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
4158 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))
4159 ixgbe_set_fdir_queues(adapter
);
4161 ixgbe_set_rss_queues(adapter
);
4163 /* adding FCoE rx rings to the end */
4164 f
->mask
= adapter
->num_rx_queues
;
4165 adapter
->num_rx_queues
+= f
->indices
;
4166 adapter
->num_tx_queues
+= f
->indices
;
4174 #endif /* IXGBE_FCOE */
4176 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4177 * @adapter: board private structure to initialize
4179 * IOV doesn't actually use anything, so just NAK the
4180 * request for now and let the other queue routines
4181 * figure out what to do.
4183 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter
*adapter
)
4189 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4190 * @adapter: board private structure to initialize
4192 * This is the top level queue allocation routine. The order here is very
4193 * important, starting with the "most" number of features turned on at once,
4194 * and ending with the smallest set of features. This way large combinations
4195 * can be allocated if they're turned on, and smaller combinations are the
4196 * fallthrough conditions.
4199 static int ixgbe_set_num_queues(struct ixgbe_adapter
*adapter
)
4201 /* Start with base case */
4202 adapter
->num_rx_queues
= 1;
4203 adapter
->num_tx_queues
= 1;
4204 adapter
->num_rx_pools
= adapter
->num_rx_queues
;
4205 adapter
->num_rx_queues_per_pool
= 1;
4207 if (ixgbe_set_sriov_queues(adapter
))
4211 if (ixgbe_set_fcoe_queues(adapter
))
4214 #endif /* IXGBE_FCOE */
4215 #ifdef CONFIG_IXGBE_DCB
4216 if (ixgbe_set_dcb_queues(adapter
))
4220 if (ixgbe_set_fdir_queues(adapter
))
4223 if (ixgbe_set_rss_queues(adapter
))
4226 /* fallback to base case */
4227 adapter
->num_rx_queues
= 1;
4228 adapter
->num_tx_queues
= 1;
4231 /* Notify the stack of the (possibly) reduced queue counts. */
4232 netif_set_real_num_tx_queues(adapter
->netdev
, adapter
->num_tx_queues
);
4233 return netif_set_real_num_rx_queues(adapter
->netdev
,
4234 adapter
->num_rx_queues
);
4237 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter
*adapter
,
4240 int err
, vector_threshold
;
4242 /* We'll want at least 3 (vector_threshold):
4245 * 3) Other (Link Status Change, etc.)
4246 * 4) TCP Timer (optional)
4248 vector_threshold
= MIN_MSIX_COUNT
;
4250 /* The more we get, the more we will assign to Tx/Rx Cleanup
4251 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4252 * Right now, we simply care about how many we'll get; we'll
4253 * set them up later while requesting irq's.
4255 while (vectors
>= vector_threshold
) {
4256 err
= pci_enable_msix(adapter
->pdev
, adapter
->msix_entries
,
4258 if (!err
) /* Success in acquiring all requested vectors. */
4261 vectors
= 0; /* Nasty failure, quit now */
4262 else /* err == number of vectors we should try again with */
4266 if (vectors
< vector_threshold
) {
4267 /* Can't allocate enough MSI-X interrupts? Oh well.
4268 * This just means we'll go with either a single MSI
4269 * vector or fall back to legacy interrupts.
4271 netif_printk(adapter
, hw
, KERN_DEBUG
, adapter
->netdev
,
4272 "Unable to allocate MSI-X interrupts\n");
4273 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
4274 kfree(adapter
->msix_entries
);
4275 adapter
->msix_entries
= NULL
;
4277 adapter
->flags
|= IXGBE_FLAG_MSIX_ENABLED
; /* Woot! */
4279 * Adjust for only the vectors we'll use, which is minimum
4280 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4281 * vectors we were allocated.
4283 adapter
->num_msix_vectors
= min(vectors
,
4284 adapter
->max_msix_q_vectors
+ NON_Q_VECTORS
);
4289 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4290 * @adapter: board private structure to initialize
4292 * Cache the descriptor ring offsets for RSS to the assigned rings.
4295 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter
*adapter
)
4300 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4301 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4302 adapter
->rx_ring
[i
]->reg_idx
= i
;
4303 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4304 adapter
->tx_ring
[i
]->reg_idx
= i
;
4313 #ifdef CONFIG_IXGBE_DCB
4315 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4316 * @adapter: board private structure to initialize
4318 * Cache the descriptor ring offsets for DCB to the assigned rings.
4321 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter
*adapter
)
4325 int dcb_i
= adapter
->ring_feature
[RING_F_DCB
].indices
;
4327 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
))
4330 /* the number of queues is assumed to be symmetric */
4331 switch (adapter
->hw
.mac
.type
) {
4332 case ixgbe_mac_82598EB
:
4333 for (i
= 0; i
< dcb_i
; i
++) {
4334 adapter
->rx_ring
[i
]->reg_idx
= i
<< 3;
4335 adapter
->tx_ring
[i
]->reg_idx
= i
<< 2;
4339 case ixgbe_mac_82599EB
:
4342 * Tx TC0 starts at: descriptor queue 0
4343 * Tx TC1 starts at: descriptor queue 32
4344 * Tx TC2 starts at: descriptor queue 64
4345 * Tx TC3 starts at: descriptor queue 80
4346 * Tx TC4 starts at: descriptor queue 96
4347 * Tx TC5 starts at: descriptor queue 104
4348 * Tx TC6 starts at: descriptor queue 112
4349 * Tx TC7 starts at: descriptor queue 120
4351 * Rx TC0-TC7 are offset by 16 queues each
4353 for (i
= 0; i
< 3; i
++) {
4354 adapter
->tx_ring
[i
]->reg_idx
= i
<< 5;
4355 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
4357 for ( ; i
< 5; i
++) {
4358 adapter
->tx_ring
[i
]->reg_idx
= ((i
+ 2) << 4);
4359 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
4361 for ( ; i
< dcb_i
; i
++) {
4362 adapter
->tx_ring
[i
]->reg_idx
= ((i
+ 8) << 3);
4363 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
4366 } else if (dcb_i
== 4) {
4368 * Tx TC0 starts at: descriptor queue 0
4369 * Tx TC1 starts at: descriptor queue 64
4370 * Tx TC2 starts at: descriptor queue 96
4371 * Tx TC3 starts at: descriptor queue 112
4373 * Rx TC0-TC3 are offset by 32 queues each
4375 adapter
->tx_ring
[0]->reg_idx
= 0;
4376 adapter
->tx_ring
[1]->reg_idx
= 64;
4377 adapter
->tx_ring
[2]->reg_idx
= 96;
4378 adapter
->tx_ring
[3]->reg_idx
= 112;
4379 for (i
= 0 ; i
< dcb_i
; i
++)
4380 adapter
->rx_ring
[i
]->reg_idx
= i
<< 5;
4392 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4393 * @adapter: board private structure to initialize
4395 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4398 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter
*adapter
)
4403 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
&&
4404 ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
4405 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))) {
4406 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4407 adapter
->rx_ring
[i
]->reg_idx
= i
;
4408 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4409 adapter
->tx_ring
[i
]->reg_idx
= i
;
4418 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4419 * @adapter: board private structure to initialize
4421 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4424 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter
*adapter
)
4426 int i
, fcoe_rx_i
= 0, fcoe_tx_i
= 0;
4428 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
4430 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
4431 #ifdef CONFIG_IXGBE_DCB
4432 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
4433 struct ixgbe_fcoe
*fcoe
= &adapter
->fcoe
;
4435 ixgbe_cache_ring_dcb(adapter
);
4436 /* find out queues in TC for FCoE */
4437 fcoe_rx_i
= adapter
->rx_ring
[fcoe
->tc
]->reg_idx
+ 1;
4438 fcoe_tx_i
= adapter
->tx_ring
[fcoe
->tc
]->reg_idx
+ 1;
4440 * In 82599, the number of Tx queues for each traffic
4441 * class for both 8-TC and 4-TC modes are:
4442 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4443 * 8 TCs: 32 32 16 16 8 8 8 8
4444 * 4 TCs: 64 64 32 32
4445 * We have max 8 queues for FCoE, where 8 the is
4446 * FCoE redirection table size. If TC for FCoE is
4447 * less than or equal to TC3, we have enough queues
4448 * to add max of 8 queues for FCoE, so we start FCoE
4449 * tx descriptor from the next one, i.e., reg_idx + 1.
4450 * If TC for FCoE is above TC3, implying 8 TC mode,
4451 * and we need 8 for FCoE, we have to take all queues
4452 * in that traffic class for FCoE.
4454 if ((f
->indices
== IXGBE_FCRETA_SIZE
) && (fcoe
->tc
> 3))
4457 #endif /* CONFIG_IXGBE_DCB */
4458 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4459 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
4460 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))
4461 ixgbe_cache_ring_fdir(adapter
);
4463 ixgbe_cache_ring_rss(adapter
);
4465 fcoe_rx_i
= f
->mask
;
4466 fcoe_tx_i
= f
->mask
;
4468 for (i
= 0; i
< f
->indices
; i
++, fcoe_rx_i
++, fcoe_tx_i
++) {
4469 adapter
->rx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_rx_i
;
4470 adapter
->tx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_tx_i
;
4477 #endif /* IXGBE_FCOE */
4479 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4480 * @adapter: board private structure to initialize
4482 * SR-IOV doesn't use any descriptor rings but changes the default if
4483 * no other mapping is used.
4486 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter
*adapter
)
4488 adapter
->rx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
4489 adapter
->tx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
4490 if (adapter
->num_vfs
)
4497 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4498 * @adapter: board private structure to initialize
4500 * Once we know the feature-set enabled for the device, we'll cache
4501 * the register offset the descriptor ring is assigned to.
4503 * Note, the order the various feature calls is important. It must start with
4504 * the "most" features enabled at the same time, then trickle down to the
4505 * least amount of features turned on at once.
4507 static void ixgbe_cache_ring_register(struct ixgbe_adapter
*adapter
)
4509 /* start with default case */
4510 adapter
->rx_ring
[0]->reg_idx
= 0;
4511 adapter
->tx_ring
[0]->reg_idx
= 0;
4513 if (ixgbe_cache_ring_sriov(adapter
))
4517 if (ixgbe_cache_ring_fcoe(adapter
))
4520 #endif /* IXGBE_FCOE */
4521 #ifdef CONFIG_IXGBE_DCB
4522 if (ixgbe_cache_ring_dcb(adapter
))
4526 if (ixgbe_cache_ring_fdir(adapter
))
4529 if (ixgbe_cache_ring_rss(adapter
))
4534 * ixgbe_alloc_queues - Allocate memory for all rings
4535 * @adapter: board private structure to initialize
4537 * We allocate one ring per queue at run-time since we don't know the
4538 * number of queues at compile-time. The polling_netdev array is
4539 * intended for Multiqueue, but should work fine with a single queue.
4541 static int ixgbe_alloc_queues(struct ixgbe_adapter
*adapter
)
4545 int orig_node
= adapter
->node
;
4547 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4548 struct ixgbe_ring
*ring
= adapter
->tx_ring
[i
];
4549 if (orig_node
== -1) {
4550 int cur_node
= next_online_node(adapter
->node
);
4551 if (cur_node
== MAX_NUMNODES
)
4552 cur_node
= first_online_node
;
4553 adapter
->node
= cur_node
;
4555 ring
= kzalloc_node(sizeof(struct ixgbe_ring
), GFP_KERNEL
,
4558 ring
= kzalloc(sizeof(struct ixgbe_ring
), GFP_KERNEL
);
4560 goto err_tx_ring_allocation
;
4561 ring
->count
= adapter
->tx_ring_count
;
4562 ring
->queue_index
= i
;
4563 ring
->dev
= &adapter
->pdev
->dev
;
4564 ring
->netdev
= adapter
->netdev
;
4565 ring
->numa_node
= adapter
->node
;
4567 adapter
->tx_ring
[i
] = ring
;
4570 /* Restore the adapter's original node */
4571 adapter
->node
= orig_node
;
4573 rx_count
= adapter
->rx_ring_count
;
4574 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
4575 struct ixgbe_ring
*ring
= adapter
->rx_ring
[i
];
4576 if (orig_node
== -1) {
4577 int cur_node
= next_online_node(adapter
->node
);
4578 if (cur_node
== MAX_NUMNODES
)
4579 cur_node
= first_online_node
;
4580 adapter
->node
= cur_node
;
4582 ring
= kzalloc_node(sizeof(struct ixgbe_ring
), GFP_KERNEL
,
4585 ring
= kzalloc(sizeof(struct ixgbe_ring
), GFP_KERNEL
);
4587 goto err_rx_ring_allocation
;
4588 ring
->count
= rx_count
;
4589 ring
->queue_index
= i
;
4590 ring
->dev
= &adapter
->pdev
->dev
;
4591 ring
->netdev
= adapter
->netdev
;
4592 ring
->numa_node
= adapter
->node
;
4594 adapter
->rx_ring
[i
] = ring
;
4597 /* Restore the adapter's original node */
4598 adapter
->node
= orig_node
;
4600 ixgbe_cache_ring_register(adapter
);
4604 err_rx_ring_allocation
:
4605 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4606 kfree(adapter
->tx_ring
[i
]);
4607 err_tx_ring_allocation
:
4612 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4613 * @adapter: board private structure to initialize
4615 * Attempt to configure the interrupts using the best available
4616 * capabilities of the hardware and the kernel.
4618 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter
*adapter
)
4620 struct ixgbe_hw
*hw
= &adapter
->hw
;
4622 int vector
, v_budget
;
4625 * It's easy to be greedy for MSI-X vectors, but it really
4626 * doesn't do us much good if we have a lot more vectors
4627 * than CPU's. So let's be conservative and only ask for
4628 * (roughly) the same number of vectors as there are CPU's.
4630 v_budget
= min(adapter
->num_rx_queues
+ adapter
->num_tx_queues
,
4631 (int)num_online_cpus()) + NON_Q_VECTORS
;
4634 * At the same time, hardware can only support a maximum of
4635 * hw.mac->max_msix_vectors vectors. With features
4636 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4637 * descriptor queues supported by our device. Thus, we cap it off in
4638 * those rare cases where the cpu count also exceeds our vector limit.
4640 v_budget
= min(v_budget
, (int)hw
->mac
.max_msix_vectors
);
4642 /* A failure in MSI-X entry allocation isn't fatal, but it does
4643 * mean we disable MSI-X capabilities of the adapter. */
4644 adapter
->msix_entries
= kcalloc(v_budget
,
4645 sizeof(struct msix_entry
), GFP_KERNEL
);
4646 if (adapter
->msix_entries
) {
4647 for (vector
= 0; vector
< v_budget
; vector
++)
4648 adapter
->msix_entries
[vector
].entry
= vector
;
4650 ixgbe_acquire_msix_vectors(adapter
, v_budget
);
4652 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
4656 adapter
->flags
&= ~IXGBE_FLAG_DCB_ENABLED
;
4657 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
4658 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4659 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
4660 adapter
->atr_sample_rate
= 0;
4661 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
4662 ixgbe_disable_sriov(adapter
);
4664 err
= ixgbe_set_num_queues(adapter
);
4668 err
= pci_enable_msi(adapter
->pdev
);
4670 adapter
->flags
|= IXGBE_FLAG_MSI_ENABLED
;
4672 netif_printk(adapter
, hw
, KERN_DEBUG
, adapter
->netdev
,
4673 "Unable to allocate MSI interrupt, "
4674 "falling back to legacy. Error: %d\n", err
);
4684 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4685 * @adapter: board private structure to initialize
4687 * We allocate one q_vector per queue interrupt. If allocation fails we
4690 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter
*adapter
)
4692 int q_idx
, num_q_vectors
;
4693 struct ixgbe_q_vector
*q_vector
;
4695 int (*poll
)(struct napi_struct
*, int);
4697 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4698 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4699 napi_vectors
= adapter
->num_rx_queues
;
4700 poll
= &ixgbe_clean_rxtx_many
;
4707 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
4708 q_vector
= kzalloc_node(sizeof(struct ixgbe_q_vector
),
4709 GFP_KERNEL
, adapter
->node
);
4711 q_vector
= kzalloc(sizeof(struct ixgbe_q_vector
),
4715 q_vector
->adapter
= adapter
;
4716 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
4717 q_vector
->eitr
= adapter
->tx_eitr_param
;
4719 q_vector
->eitr
= adapter
->rx_eitr_param
;
4720 q_vector
->v_idx
= q_idx
;
4721 netif_napi_add(adapter
->netdev
, &q_vector
->napi
, (*poll
), 64);
4722 adapter
->q_vector
[q_idx
] = q_vector
;
4730 q_vector
= adapter
->q_vector
[q_idx
];
4731 netif_napi_del(&q_vector
->napi
);
4733 adapter
->q_vector
[q_idx
] = NULL
;
4739 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4740 * @adapter: board private structure to initialize
4742 * This function frees the memory allocated to the q_vectors. In addition if
4743 * NAPI is enabled it will delete any references to the NAPI struct prior
4744 * to freeing the q_vector.
4746 static void ixgbe_free_q_vectors(struct ixgbe_adapter
*adapter
)
4748 int q_idx
, num_q_vectors
;
4750 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
4751 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4755 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
4756 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[q_idx
];
4757 adapter
->q_vector
[q_idx
] = NULL
;
4758 netif_napi_del(&q_vector
->napi
);
4763 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter
*adapter
)
4765 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4766 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
4767 pci_disable_msix(adapter
->pdev
);
4768 kfree(adapter
->msix_entries
);
4769 adapter
->msix_entries
= NULL
;
4770 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
4771 adapter
->flags
&= ~IXGBE_FLAG_MSI_ENABLED
;
4772 pci_disable_msi(adapter
->pdev
);
4777 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4778 * @adapter: board private structure to initialize
4780 * We determine which interrupt scheme to use based on...
4781 * - Kernel support (MSI, MSI-X)
4782 * - which can be user-defined (via MODULE_PARAM)
4783 * - Hardware queue count (num_*_queues)
4784 * - defined by miscellaneous hardware support/features (RSS, etc.)
4786 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter
*adapter
)
4790 /* Number of supported queues */
4791 err
= ixgbe_set_num_queues(adapter
);
4795 err
= ixgbe_set_interrupt_capability(adapter
);
4797 e_dev_err("Unable to setup interrupt capabilities\n");
4798 goto err_set_interrupt
;
4801 err
= ixgbe_alloc_q_vectors(adapter
);
4803 e_dev_err("Unable to allocate memory for queue vectors\n");
4804 goto err_alloc_q_vectors
;
4807 err
= ixgbe_alloc_queues(adapter
);
4809 e_dev_err("Unable to allocate memory for queues\n");
4810 goto err_alloc_queues
;
4813 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4814 (adapter
->num_rx_queues
> 1) ? "Enabled" : "Disabled",
4815 adapter
->num_rx_queues
, adapter
->num_tx_queues
);
4817 set_bit(__IXGBE_DOWN
, &adapter
->state
);
4822 ixgbe_free_q_vectors(adapter
);
4823 err_alloc_q_vectors
:
4824 ixgbe_reset_interrupt_capability(adapter
);
4829 static void ring_free_rcu(struct rcu_head
*head
)
4831 kfree(container_of(head
, struct ixgbe_ring
, rcu
));
4835 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4836 * @adapter: board private structure to clear interrupt scheme on
4838 * We go through and clear interrupt specific resources and reset the structure
4839 * to pre-load conditions
4841 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter
*adapter
)
4845 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4846 kfree(adapter
->tx_ring
[i
]);
4847 adapter
->tx_ring
[i
] = NULL
;
4849 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
4850 struct ixgbe_ring
*ring
= adapter
->rx_ring
[i
];
4852 /* ixgbe_get_stats64() might access this ring, we must wait
4853 * a grace period before freeing it.
4855 call_rcu(&ring
->rcu
, ring_free_rcu
);
4856 adapter
->rx_ring
[i
] = NULL
;
4859 ixgbe_free_q_vectors(adapter
);
4860 ixgbe_reset_interrupt_capability(adapter
);
4864 * ixgbe_sfp_timer - worker thread to find a missing module
4865 * @data: pointer to our adapter struct
4867 static void ixgbe_sfp_timer(unsigned long data
)
4869 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
4872 * Do the sfp_timer outside of interrupt context due to the
4873 * delays that sfp+ detection requires
4875 schedule_work(&adapter
->sfp_task
);
4879 * ixgbe_sfp_task - worker thread to find a missing module
4880 * @work: pointer to work_struct containing our data
4882 static void ixgbe_sfp_task(struct work_struct
*work
)
4884 struct ixgbe_adapter
*adapter
= container_of(work
,
4885 struct ixgbe_adapter
,
4887 struct ixgbe_hw
*hw
= &adapter
->hw
;
4889 if ((hw
->phy
.type
== ixgbe_phy_nl
) &&
4890 (hw
->phy
.sfp_type
== ixgbe_sfp_type_not_present
)) {
4891 s32 ret
= hw
->phy
.ops
.identify_sfp(hw
);
4892 if (ret
== IXGBE_ERR_SFP_NOT_PRESENT
)
4894 ret
= hw
->phy
.ops
.reset(hw
);
4895 if (ret
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
4896 e_dev_err("failed to initialize because an unsupported "
4897 "SFP+ module type was detected.\n");
4898 e_dev_err("Reload the driver after installing a "
4899 "supported module.\n");
4900 unregister_netdev(adapter
->netdev
);
4902 e_info(probe
, "detected SFP+: %d\n", hw
->phy
.sfp_type
);
4904 /* don't need this routine any more */
4905 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
4909 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
))
4910 mod_timer(&adapter
->sfp_timer
,
4911 round_jiffies(jiffies
+ (2 * HZ
)));
4915 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4916 * @adapter: board private structure to initialize
4918 * ixgbe_sw_init initializes the Adapter private data structure.
4919 * Fields are initialized based on PCI device information and
4920 * OS network device settings (MTU size).
4922 static int __devinit
ixgbe_sw_init(struct ixgbe_adapter
*adapter
)
4924 struct ixgbe_hw
*hw
= &adapter
->hw
;
4925 struct pci_dev
*pdev
= adapter
->pdev
;
4926 struct net_device
*dev
= adapter
->netdev
;
4928 #ifdef CONFIG_IXGBE_DCB
4930 struct tc_configuration
*tc
;
4932 int max_frame
= dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
4934 /* PCI config space info */
4936 hw
->vendor_id
= pdev
->vendor
;
4937 hw
->device_id
= pdev
->device
;
4938 hw
->revision_id
= pdev
->revision
;
4939 hw
->subsystem_vendor_id
= pdev
->subsystem_vendor
;
4940 hw
->subsystem_device_id
= pdev
->subsystem_device
;
4942 /* Set capability flags */
4943 rss
= min(IXGBE_MAX_RSS_INDICES
, (int)num_online_cpus());
4944 adapter
->ring_feature
[RING_F_RSS
].indices
= rss
;
4945 adapter
->flags
|= IXGBE_FLAG_RSS_ENABLED
;
4946 adapter
->ring_feature
[RING_F_DCB
].indices
= IXGBE_MAX_DCB_INDICES
;
4947 switch (hw
->mac
.type
) {
4948 case ixgbe_mac_82598EB
:
4949 if (hw
->device_id
== IXGBE_DEV_ID_82598AT
)
4950 adapter
->flags
|= IXGBE_FLAG_FAN_FAIL_CAPABLE
;
4951 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82598
;
4953 case ixgbe_mac_82599EB
:
4954 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82599
;
4955 adapter
->flags2
|= IXGBE_FLAG2_RSC_CAPABLE
;
4956 adapter
->flags2
|= IXGBE_FLAG2_RSC_ENABLED
;
4957 if (hw
->device_id
== IXGBE_DEV_ID_82599_T3_LOM
)
4958 adapter
->flags2
|= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
;
4959 if (dev
->features
& NETIF_F_NTUPLE
) {
4960 /* Flow Director perfect filter enabled */
4961 adapter
->flags
|= IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
4962 adapter
->atr_sample_rate
= 0;
4963 spin_lock_init(&adapter
->fdir_perfect_lock
);
4965 /* Flow Director hash filters enabled */
4966 adapter
->flags
|= IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4967 adapter
->atr_sample_rate
= 20;
4969 adapter
->ring_feature
[RING_F_FDIR
].indices
=
4970 IXGBE_MAX_FDIR_INDICES
;
4971 adapter
->fdir_pballoc
= 0;
4973 adapter
->flags
|= IXGBE_FLAG_FCOE_CAPABLE
;
4974 adapter
->flags
&= ~IXGBE_FLAG_FCOE_ENABLED
;
4975 adapter
->ring_feature
[RING_F_FCOE
].indices
= 0;
4976 #ifdef CONFIG_IXGBE_DCB
4977 /* Default traffic class to use for FCoE */
4978 adapter
->fcoe
.tc
= IXGBE_FCOE_DEFTC
;
4979 adapter
->fcoe
.up
= IXGBE_FCOE_DEFTC
;
4981 #endif /* IXGBE_FCOE */
4987 #ifdef CONFIG_IXGBE_DCB
4988 /* Configure DCB traffic classes */
4989 for (j
= 0; j
< MAX_TRAFFIC_CLASS
; j
++) {
4990 tc
= &adapter
->dcb_cfg
.tc_config
[j
];
4991 tc
->path
[DCB_TX_CONFIG
].bwg_id
= 0;
4992 tc
->path
[DCB_TX_CONFIG
].bwg_percent
= 12 + (j
& 1);
4993 tc
->path
[DCB_RX_CONFIG
].bwg_id
= 0;
4994 tc
->path
[DCB_RX_CONFIG
].bwg_percent
= 12 + (j
& 1);
4995 tc
->dcb_pfc
= pfc_disabled
;
4997 adapter
->dcb_cfg
.bw_percentage
[DCB_TX_CONFIG
][0] = 100;
4998 adapter
->dcb_cfg
.bw_percentage
[DCB_RX_CONFIG
][0] = 100;
4999 adapter
->dcb_cfg
.rx_pba_cfg
= pba_equal
;
5000 adapter
->dcb_cfg
.pfc_mode_enable
= false;
5001 adapter
->dcb_cfg
.round_robin_enable
= false;
5002 adapter
->dcb_set_bitmap
= 0x00;
5003 ixgbe_copy_dcb_cfg(&adapter
->dcb_cfg
, &adapter
->temp_dcb_cfg
,
5004 adapter
->ring_feature
[RING_F_DCB
].indices
);
5008 /* default flow control settings */
5009 hw
->fc
.requested_mode
= ixgbe_fc_full
;
5010 hw
->fc
.current_mode
= ixgbe_fc_full
; /* init for ethtool output */
5012 adapter
->last_lfc_mode
= hw
->fc
.current_mode
;
5014 hw
->fc
.high_water
= FC_HIGH_WATER(max_frame
);
5015 hw
->fc
.low_water
= FC_LOW_WATER(max_frame
);
5016 hw
->fc
.pause_time
= IXGBE_DEFAULT_FCPAUSE
;
5017 hw
->fc
.send_xon
= true;
5018 hw
->fc
.disable_fc_autoneg
= false;
5020 /* enable itr by default in dynamic mode */
5021 adapter
->rx_itr_setting
= 1;
5022 adapter
->rx_eitr_param
= 20000;
5023 adapter
->tx_itr_setting
= 1;
5024 adapter
->tx_eitr_param
= 10000;
5026 /* set defaults for eitr in MegaBytes */
5027 adapter
->eitr_low
= 10;
5028 adapter
->eitr_high
= 20;
5030 /* set default ring sizes */
5031 adapter
->tx_ring_count
= IXGBE_DEFAULT_TXD
;
5032 adapter
->rx_ring_count
= IXGBE_DEFAULT_RXD
;
5034 /* initialize eeprom parameters */
5035 if (ixgbe_init_eeprom_params_generic(hw
)) {
5036 e_dev_err("EEPROM initialization failed\n");
5040 /* enable rx csum by default */
5041 adapter
->flags
|= IXGBE_FLAG_RX_CSUM_ENABLED
;
5043 /* get assigned NUMA node */
5044 adapter
->node
= dev_to_node(&pdev
->dev
);
5046 set_bit(__IXGBE_DOWN
, &adapter
->state
);
5052 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5053 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5055 * Return 0 on success, negative on failure
5057 int ixgbe_setup_tx_resources(struct ixgbe_ring
*tx_ring
)
5059 struct device
*dev
= tx_ring
->dev
;
5062 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
5063 tx_ring
->tx_buffer_info
= vmalloc_node(size
, tx_ring
->numa_node
);
5064 if (!tx_ring
->tx_buffer_info
)
5065 tx_ring
->tx_buffer_info
= vmalloc(size
);
5066 if (!tx_ring
->tx_buffer_info
)
5068 memset(tx_ring
->tx_buffer_info
, 0, size
);
5070 /* round up to nearest 4K */
5071 tx_ring
->size
= tx_ring
->count
* sizeof(union ixgbe_adv_tx_desc
);
5072 tx_ring
->size
= ALIGN(tx_ring
->size
, 4096);
5074 tx_ring
->desc
= dma_alloc_coherent(dev
, tx_ring
->size
,
5075 &tx_ring
->dma
, GFP_KERNEL
);
5079 tx_ring
->next_to_use
= 0;
5080 tx_ring
->next_to_clean
= 0;
5081 tx_ring
->work_limit
= tx_ring
->count
;
5085 vfree(tx_ring
->tx_buffer_info
);
5086 tx_ring
->tx_buffer_info
= NULL
;
5087 dev_err(dev
, "Unable to allocate memory for the Tx descriptor ring\n");
5092 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5093 * @adapter: board private structure
5095 * If this function returns with an error, then it's possible one or
5096 * more of the rings is populated (while the rest are not). It is the
5097 * callers duty to clean those orphaned rings.
5099 * Return 0 on success, negative on failure
5101 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter
*adapter
)
5105 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5106 err
= ixgbe_setup_tx_resources(adapter
->tx_ring
[i
]);
5109 e_err(probe
, "Allocation for Tx Queue %u failed\n", i
);
5117 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5118 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5120 * Returns 0 on success, negative on failure
5122 int ixgbe_setup_rx_resources(struct ixgbe_ring
*rx_ring
)
5124 struct device
*dev
= rx_ring
->dev
;
5127 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
5128 rx_ring
->rx_buffer_info
= vmalloc_node(size
, rx_ring
->numa_node
);
5129 if (!rx_ring
->rx_buffer_info
)
5130 rx_ring
->rx_buffer_info
= vmalloc(size
);
5131 if (!rx_ring
->rx_buffer_info
)
5133 memset(rx_ring
->rx_buffer_info
, 0, size
);
5135 /* Round up to nearest 4K */
5136 rx_ring
->size
= rx_ring
->count
* sizeof(union ixgbe_adv_rx_desc
);
5137 rx_ring
->size
= ALIGN(rx_ring
->size
, 4096);
5139 rx_ring
->desc
= dma_alloc_coherent(dev
, rx_ring
->size
,
5140 &rx_ring
->dma
, GFP_KERNEL
);
5145 rx_ring
->next_to_clean
= 0;
5146 rx_ring
->next_to_use
= 0;
5150 vfree(rx_ring
->rx_buffer_info
);
5151 rx_ring
->rx_buffer_info
= NULL
;
5152 dev_err(dev
, "Unable to allocate memory for the Rx descriptor ring\n");
5157 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5158 * @adapter: board private structure
5160 * If this function returns with an error, then it's possible one or
5161 * more of the rings is populated (while the rest are not). It is the
5162 * callers duty to clean those orphaned rings.
5164 * Return 0 on success, negative on failure
5166 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter
*adapter
)
5170 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5171 err
= ixgbe_setup_rx_resources(adapter
->rx_ring
[i
]);
5174 e_err(probe
, "Allocation for Rx Queue %u failed\n", i
);
5182 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5183 * @tx_ring: Tx descriptor ring for a specific queue
5185 * Free all transmit software resources
5187 void ixgbe_free_tx_resources(struct ixgbe_ring
*tx_ring
)
5189 ixgbe_clean_tx_ring(tx_ring
);
5191 vfree(tx_ring
->tx_buffer_info
);
5192 tx_ring
->tx_buffer_info
= NULL
;
5194 /* if not set, then don't free */
5198 dma_free_coherent(tx_ring
->dev
, tx_ring
->size
,
5199 tx_ring
->desc
, tx_ring
->dma
);
5201 tx_ring
->desc
= NULL
;
5205 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5206 * @adapter: board private structure
5208 * Free all transmit software resources
5210 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter
*adapter
)
5214 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5215 if (adapter
->tx_ring
[i
]->desc
)
5216 ixgbe_free_tx_resources(adapter
->tx_ring
[i
]);
5220 * ixgbe_free_rx_resources - Free Rx Resources
5221 * @rx_ring: ring to clean the resources from
5223 * Free all receive software resources
5225 void ixgbe_free_rx_resources(struct ixgbe_ring
*rx_ring
)
5227 ixgbe_clean_rx_ring(rx_ring
);
5229 vfree(rx_ring
->rx_buffer_info
);
5230 rx_ring
->rx_buffer_info
= NULL
;
5232 /* if not set, then don't free */
5236 dma_free_coherent(rx_ring
->dev
, rx_ring
->size
,
5237 rx_ring
->desc
, rx_ring
->dma
);
5239 rx_ring
->desc
= NULL
;
5243 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5244 * @adapter: board private structure
5246 * Free all receive software resources
5248 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter
*adapter
)
5252 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
5253 if (adapter
->rx_ring
[i
]->desc
)
5254 ixgbe_free_rx_resources(adapter
->rx_ring
[i
]);
5258 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5259 * @netdev: network interface device structure
5260 * @new_mtu: new value for maximum frame size
5262 * Returns 0 on success, negative on failure
5264 static int ixgbe_change_mtu(struct net_device
*netdev
, int new_mtu
)
5266 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5267 struct ixgbe_hw
*hw
= &adapter
->hw
;
5268 int max_frame
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
5270 /* MTU < 68 is an error and causes problems on some kernels */
5271 if ((new_mtu
< 68) || (max_frame
> IXGBE_MAX_JUMBO_FRAME_SIZE
))
5274 e_info(probe
, "changing MTU from %d to %d\n", netdev
->mtu
, new_mtu
);
5275 /* must set new MTU before calling down or up */
5276 netdev
->mtu
= new_mtu
;
5278 hw
->fc
.high_water
= FC_HIGH_WATER(max_frame
);
5279 hw
->fc
.low_water
= FC_LOW_WATER(max_frame
);
5281 if (netif_running(netdev
))
5282 ixgbe_reinit_locked(adapter
);
5288 * ixgbe_open - Called when a network interface is made active
5289 * @netdev: network interface device structure
5291 * Returns 0 on success, negative value on failure
5293 * The open entry point is called when a network interface is made
5294 * active by the system (IFF_UP). At this point all resources needed
5295 * for transmit and receive operations are allocated, the interrupt
5296 * handler is registered with the OS, the watchdog timer is started,
5297 * and the stack is notified that the interface is ready.
5299 static int ixgbe_open(struct net_device
*netdev
)
5301 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5304 /* disallow open during test */
5305 if (test_bit(__IXGBE_TESTING
, &adapter
->state
))
5308 netif_carrier_off(netdev
);
5310 /* allocate transmit descriptors */
5311 err
= ixgbe_setup_all_tx_resources(adapter
);
5315 /* allocate receive descriptors */
5316 err
= ixgbe_setup_all_rx_resources(adapter
);
5320 ixgbe_configure(adapter
);
5322 err
= ixgbe_request_irq(adapter
);
5326 err
= ixgbe_up_complete(adapter
);
5330 netif_tx_start_all_queues(netdev
);
5335 ixgbe_release_hw_control(adapter
);
5336 ixgbe_free_irq(adapter
);
5339 ixgbe_free_all_rx_resources(adapter
);
5341 ixgbe_free_all_tx_resources(adapter
);
5342 ixgbe_reset(adapter
);
5348 * ixgbe_close - Disables a network interface
5349 * @netdev: network interface device structure
5351 * Returns 0, this is not allowed to fail
5353 * The close entry point is called when an interface is de-activated
5354 * by the OS. The hardware is still under the drivers control, but
5355 * needs to be disabled. A global MAC reset is issued to stop the
5356 * hardware, and all transmit and receive resources are freed.
5358 static int ixgbe_close(struct net_device
*netdev
)
5360 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5362 ixgbe_down(adapter
);
5363 ixgbe_free_irq(adapter
);
5365 ixgbe_free_all_tx_resources(adapter
);
5366 ixgbe_free_all_rx_resources(adapter
);
5368 ixgbe_release_hw_control(adapter
);
5374 static int ixgbe_resume(struct pci_dev
*pdev
)
5376 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
5377 struct net_device
*netdev
= adapter
->netdev
;
5380 pci_set_power_state(pdev
, PCI_D0
);
5381 pci_restore_state(pdev
);
5383 * pci_restore_state clears dev->state_saved so call
5384 * pci_save_state to restore it.
5386 pci_save_state(pdev
);
5388 err
= pci_enable_device_mem(pdev
);
5390 e_dev_err("Cannot enable PCI device from suspend\n");
5393 pci_set_master(pdev
);
5395 pci_wake_from_d3(pdev
, false);
5397 err
= ixgbe_init_interrupt_scheme(adapter
);
5399 e_dev_err("Cannot initialize interrupts for device\n");
5403 ixgbe_reset(adapter
);
5405 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
5407 if (netif_running(netdev
)) {
5408 err
= ixgbe_open(netdev
);
5413 netif_device_attach(netdev
);
5417 #endif /* CONFIG_PM */
5419 static int __ixgbe_shutdown(struct pci_dev
*pdev
, bool *enable_wake
)
5421 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
5422 struct net_device
*netdev
= adapter
->netdev
;
5423 struct ixgbe_hw
*hw
= &adapter
->hw
;
5425 u32 wufc
= adapter
->wol
;
5430 netif_device_detach(netdev
);
5432 if (netif_running(netdev
)) {
5433 ixgbe_down(adapter
);
5434 ixgbe_free_irq(adapter
);
5435 ixgbe_free_all_tx_resources(adapter
);
5436 ixgbe_free_all_rx_resources(adapter
);
5439 ixgbe_clear_interrupt_scheme(adapter
);
5442 retval
= pci_save_state(pdev
);
5448 ixgbe_set_rx_mode(netdev
);
5450 /* turn on all-multi mode if wake on multicast is enabled */
5451 if (wufc
& IXGBE_WUFC_MC
) {
5452 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
5453 fctrl
|= IXGBE_FCTRL_MPE
;
5454 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
5457 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
5458 ctrl
|= IXGBE_CTRL_GIO_DIS
;
5459 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, ctrl
);
5461 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, wufc
);
5463 IXGBE_WRITE_REG(hw
, IXGBE_WUC
, 0);
5464 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, 0);
5467 switch (hw
->mac
.type
) {
5468 case ixgbe_mac_82598EB
:
5469 pci_wake_from_d3(pdev
, false);
5471 case ixgbe_mac_82599EB
:
5472 pci_wake_from_d3(pdev
, !!wufc
);
5478 *enable_wake
= !!wufc
;
5480 ixgbe_release_hw_control(adapter
);
5482 pci_disable_device(pdev
);
5488 static int ixgbe_suspend(struct pci_dev
*pdev
, pm_message_t state
)
5493 retval
= __ixgbe_shutdown(pdev
, &wake
);
5498 pci_prepare_to_sleep(pdev
);
5500 pci_wake_from_d3(pdev
, false);
5501 pci_set_power_state(pdev
, PCI_D3hot
);
5506 #endif /* CONFIG_PM */
5508 static void ixgbe_shutdown(struct pci_dev
*pdev
)
5512 __ixgbe_shutdown(pdev
, &wake
);
5514 if (system_state
== SYSTEM_POWER_OFF
) {
5515 pci_wake_from_d3(pdev
, wake
);
5516 pci_set_power_state(pdev
, PCI_D3hot
);
5521 * ixgbe_update_stats - Update the board statistics counters.
5522 * @adapter: board private structure
5524 void ixgbe_update_stats(struct ixgbe_adapter
*adapter
)
5526 struct net_device
*netdev
= adapter
->netdev
;
5527 struct ixgbe_hw
*hw
= &adapter
->hw
;
5528 struct ixgbe_hw_stats
*hwstats
= &adapter
->stats
;
5530 u32 i
, missed_rx
= 0, mpc
, bprc
, lxon
, lxoff
, xon_off_tot
;
5531 u64 non_eop_descs
= 0, restart_queue
= 0, tx_busy
= 0;
5532 u64 alloc_rx_page_failed
= 0, alloc_rx_buff_failed
= 0;
5533 u64 bytes
= 0, packets
= 0;
5535 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
5536 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
5539 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
5542 for (i
= 0; i
< 16; i
++)
5543 adapter
->hw_rx_no_dma_resources
+=
5544 IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
5545 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5546 rsc_count
+= adapter
->rx_ring
[i
]->rx_stats
.rsc_count
;
5547 rsc_flush
+= adapter
->rx_ring
[i
]->rx_stats
.rsc_flush
;
5549 adapter
->rsc_total_count
= rsc_count
;
5550 adapter
->rsc_total_flush
= rsc_flush
;
5553 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5554 struct ixgbe_ring
*rx_ring
= adapter
->rx_ring
[i
];
5555 non_eop_descs
+= rx_ring
->rx_stats
.non_eop_descs
;
5556 alloc_rx_page_failed
+= rx_ring
->rx_stats
.alloc_rx_page_failed
;
5557 alloc_rx_buff_failed
+= rx_ring
->rx_stats
.alloc_rx_buff_failed
;
5558 bytes
+= rx_ring
->stats
.bytes
;
5559 packets
+= rx_ring
->stats
.packets
;
5561 adapter
->non_eop_descs
= non_eop_descs
;
5562 adapter
->alloc_rx_page_failed
= alloc_rx_page_failed
;
5563 adapter
->alloc_rx_buff_failed
= alloc_rx_buff_failed
;
5564 netdev
->stats
.rx_bytes
= bytes
;
5565 netdev
->stats
.rx_packets
= packets
;
5569 /* gather some stats to the adapter struct that are per queue */
5570 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5571 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[i
];
5572 restart_queue
+= tx_ring
->tx_stats
.restart_queue
;
5573 tx_busy
+= tx_ring
->tx_stats
.tx_busy
;
5574 bytes
+= tx_ring
->stats
.bytes
;
5575 packets
+= tx_ring
->stats
.packets
;
5577 adapter
->restart_queue
= restart_queue
;
5578 adapter
->tx_busy
= tx_busy
;
5579 netdev
->stats
.tx_bytes
= bytes
;
5580 netdev
->stats
.tx_packets
= packets
;
5582 hwstats
->crcerrs
+= IXGBE_READ_REG(hw
, IXGBE_CRCERRS
);
5583 for (i
= 0; i
< 8; i
++) {
5584 /* for packet buffers not used, the register should read 0 */
5585 mpc
= IXGBE_READ_REG(hw
, IXGBE_MPC(i
));
5587 hwstats
->mpc
[i
] += mpc
;
5588 total_mpc
+= hwstats
->mpc
[i
];
5589 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
5590 hwstats
->rnbc
[i
] += IXGBE_READ_REG(hw
, IXGBE_RNBC(i
));
5591 hwstats
->qptc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPTC(i
));
5592 hwstats
->qbtc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBTC(i
));
5593 hwstats
->qprc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRC(i
));
5594 hwstats
->qbrc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBRC(i
));
5595 switch (hw
->mac
.type
) {
5596 case ixgbe_mac_82598EB
:
5597 hwstats
->pxonrxc
[i
] +=
5598 IXGBE_READ_REG(hw
, IXGBE_PXONRXC(i
));
5599 hwstats
->pxoffrxc
[i
] +=
5600 IXGBE_READ_REG(hw
, IXGBE_PXOFFRXC(i
));
5602 case ixgbe_mac_82599EB
:
5603 hwstats
->pxonrxc
[i
] +=
5604 IXGBE_READ_REG(hw
, IXGBE_PXONRXCNT(i
));
5605 hwstats
->pxoffrxc
[i
] +=
5606 IXGBE_READ_REG(hw
, IXGBE_PXOFFRXCNT(i
));
5611 hwstats
->pxontxc
[i
] += IXGBE_READ_REG(hw
, IXGBE_PXONTXC(i
));
5612 hwstats
->pxofftxc
[i
] += IXGBE_READ_REG(hw
, IXGBE_PXOFFTXC(i
));
5614 hwstats
->gprc
+= IXGBE_READ_REG(hw
, IXGBE_GPRC
);
5615 /* work around hardware counting issue */
5616 hwstats
->gprc
-= missed_rx
;
5618 /* 82598 hardware only has a 32 bit counter in the high register */
5619 switch (hw
->mac
.type
) {
5620 case ixgbe_mac_82598EB
:
5621 hwstats
->lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXC
);
5622 hwstats
->lxoffrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXC
);
5623 hwstats
->gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCH
);
5624 hwstats
->gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCH
);
5625 hwstats
->tor
+= IXGBE_READ_REG(hw
, IXGBE_TORH
);
5627 case ixgbe_mac_82599EB
:
5628 hwstats
->gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCL
);
5629 IXGBE_READ_REG(hw
, IXGBE_GORCH
); /* to clear */
5630 hwstats
->gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCL
);
5631 IXGBE_READ_REG(hw
, IXGBE_GOTCH
); /* to clear */
5632 hwstats
->tor
+= IXGBE_READ_REG(hw
, IXGBE_TORL
);
5633 IXGBE_READ_REG(hw
, IXGBE_TORH
); /* to clear */
5634 hwstats
->lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXCNT
);
5635 hwstats
->lxoffrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXCNT
);
5636 hwstats
->fdirmatch
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMATCH
);
5637 hwstats
->fdirmiss
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMISS
);
5639 hwstats
->fccrc
+= IXGBE_READ_REG(hw
, IXGBE_FCCRC
);
5640 hwstats
->fcoerpdc
+= IXGBE_READ_REG(hw
, IXGBE_FCOERPDC
);
5641 hwstats
->fcoeprc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPRC
);
5642 hwstats
->fcoeptc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPTC
);
5643 hwstats
->fcoedwrc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWRC
);
5644 hwstats
->fcoedwtc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWTC
);
5645 #endif /* IXGBE_FCOE */
5650 bprc
= IXGBE_READ_REG(hw
, IXGBE_BPRC
);
5651 hwstats
->bprc
+= bprc
;
5652 hwstats
->mprc
+= IXGBE_READ_REG(hw
, IXGBE_MPRC
);
5653 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
5654 hwstats
->mprc
-= bprc
;
5655 hwstats
->roc
+= IXGBE_READ_REG(hw
, IXGBE_ROC
);
5656 hwstats
->prc64
+= IXGBE_READ_REG(hw
, IXGBE_PRC64
);
5657 hwstats
->prc127
+= IXGBE_READ_REG(hw
, IXGBE_PRC127
);
5658 hwstats
->prc255
+= IXGBE_READ_REG(hw
, IXGBE_PRC255
);
5659 hwstats
->prc511
+= IXGBE_READ_REG(hw
, IXGBE_PRC511
);
5660 hwstats
->prc1023
+= IXGBE_READ_REG(hw
, IXGBE_PRC1023
);
5661 hwstats
->prc1522
+= IXGBE_READ_REG(hw
, IXGBE_PRC1522
);
5662 hwstats
->rlec
+= IXGBE_READ_REG(hw
, IXGBE_RLEC
);
5663 lxon
= IXGBE_READ_REG(hw
, IXGBE_LXONTXC
);
5664 hwstats
->lxontxc
+= lxon
;
5665 lxoff
= IXGBE_READ_REG(hw
, IXGBE_LXOFFTXC
);
5666 hwstats
->lxofftxc
+= lxoff
;
5667 hwstats
->ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
5668 hwstats
->gptc
+= IXGBE_READ_REG(hw
, IXGBE_GPTC
);
5669 hwstats
->mptc
+= IXGBE_READ_REG(hw
, IXGBE_MPTC
);
5671 * 82598 errata - tx of flow control packets is included in tx counters
5673 xon_off_tot
= lxon
+ lxoff
;
5674 hwstats
->gptc
-= xon_off_tot
;
5675 hwstats
->mptc
-= xon_off_tot
;
5676 hwstats
->gotc
-= (xon_off_tot
* (ETH_ZLEN
+ ETH_FCS_LEN
));
5677 hwstats
->ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
5678 hwstats
->rfc
+= IXGBE_READ_REG(hw
, IXGBE_RFC
);
5679 hwstats
->rjc
+= IXGBE_READ_REG(hw
, IXGBE_RJC
);
5680 hwstats
->tpr
+= IXGBE_READ_REG(hw
, IXGBE_TPR
);
5681 hwstats
->ptc64
+= IXGBE_READ_REG(hw
, IXGBE_PTC64
);
5682 hwstats
->ptc64
-= xon_off_tot
;
5683 hwstats
->ptc127
+= IXGBE_READ_REG(hw
, IXGBE_PTC127
);
5684 hwstats
->ptc255
+= IXGBE_READ_REG(hw
, IXGBE_PTC255
);
5685 hwstats
->ptc511
+= IXGBE_READ_REG(hw
, IXGBE_PTC511
);
5686 hwstats
->ptc1023
+= IXGBE_READ_REG(hw
, IXGBE_PTC1023
);
5687 hwstats
->ptc1522
+= IXGBE_READ_REG(hw
, IXGBE_PTC1522
);
5688 hwstats
->bptc
+= IXGBE_READ_REG(hw
, IXGBE_BPTC
);
5690 /* Fill out the OS statistics structure */
5691 netdev
->stats
.multicast
= hwstats
->mprc
;
5694 netdev
->stats
.rx_errors
= hwstats
->crcerrs
+ hwstats
->rlec
;
5695 netdev
->stats
.rx_dropped
= 0;
5696 netdev
->stats
.rx_length_errors
= hwstats
->rlec
;
5697 netdev
->stats
.rx_crc_errors
= hwstats
->crcerrs
;
5698 netdev
->stats
.rx_missed_errors
= total_mpc
;
5702 * ixgbe_watchdog - Timer Call-back
5703 * @data: pointer to adapter cast into an unsigned long
5705 static void ixgbe_watchdog(unsigned long data
)
5707 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
5708 struct ixgbe_hw
*hw
= &adapter
->hw
;
5713 * Do the watchdog outside of interrupt context due to the lovely
5714 * delays that some of the newer hardware requires
5717 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
5718 goto watchdog_short_circuit
;
5720 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)) {
5722 * for legacy and MSI interrupts don't set any bits
5723 * that are enabled for EIAM, because this operation
5724 * would set *both* EIMS and EICS for any bit in EIAM
5726 IXGBE_WRITE_REG(hw
, IXGBE_EICS
,
5727 (IXGBE_EICS_TCP_TIMER
| IXGBE_EICS_OTHER
));
5728 goto watchdog_reschedule
;
5731 /* get one bit for every active tx/rx interrupt vector */
5732 for (i
= 0; i
< adapter
->num_msix_vectors
- NON_Q_VECTORS
; i
++) {
5733 struct ixgbe_q_vector
*qv
= adapter
->q_vector
[i
];
5734 if (qv
->rxr_count
|| qv
->txr_count
)
5735 eics
|= ((u64
)1 << i
);
5738 /* Cause software interrupt to ensure rx rings are cleaned */
5739 ixgbe_irq_rearm_queues(adapter
, eics
);
5741 watchdog_reschedule
:
5742 /* Reset the timer */
5743 mod_timer(&adapter
->watchdog_timer
, round_jiffies(jiffies
+ 2 * HZ
));
5745 watchdog_short_circuit
:
5746 schedule_work(&adapter
->watchdog_task
);
5750 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5751 * @work: pointer to work_struct containing our data
5753 static void ixgbe_multispeed_fiber_task(struct work_struct
*work
)
5755 struct ixgbe_adapter
*adapter
= container_of(work
,
5756 struct ixgbe_adapter
,
5757 multispeed_fiber_task
);
5758 struct ixgbe_hw
*hw
= &adapter
->hw
;
5762 adapter
->flags
|= IXGBE_FLAG_IN_SFP_LINK_TASK
;
5763 autoneg
= hw
->phy
.autoneg_advertised
;
5764 if ((!autoneg
) && (hw
->mac
.ops
.get_link_capabilities
))
5765 hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
, &negotiation
);
5766 hw
->mac
.autotry_restart
= false;
5767 if (hw
->mac
.ops
.setup_link
)
5768 hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, true);
5769 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
5770 adapter
->flags
&= ~IXGBE_FLAG_IN_SFP_LINK_TASK
;
5774 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5775 * @work: pointer to work_struct containing our data
5777 static void ixgbe_sfp_config_module_task(struct work_struct
*work
)
5779 struct ixgbe_adapter
*adapter
= container_of(work
,
5780 struct ixgbe_adapter
,
5781 sfp_config_module_task
);
5782 struct ixgbe_hw
*hw
= &adapter
->hw
;
5785 adapter
->flags
|= IXGBE_FLAG_IN_SFP_MOD_TASK
;
5787 /* Time for electrical oscillations to settle down */
5789 err
= hw
->phy
.ops
.identify_sfp(hw
);
5791 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
5792 e_dev_err("failed to initialize because an unsupported SFP+ "
5793 "module type was detected.\n");
5794 e_dev_err("Reload the driver after installing a supported "
5796 unregister_netdev(adapter
->netdev
);
5799 hw
->mac
.ops
.setup_sfp(hw
);
5801 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_LINK_TASK
))
5802 /* This will also work for DA Twinax connections */
5803 schedule_work(&adapter
->multispeed_fiber_task
);
5804 adapter
->flags
&= ~IXGBE_FLAG_IN_SFP_MOD_TASK
;
5808 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5809 * @work: pointer to work_struct containing our data
5811 static void ixgbe_fdir_reinit_task(struct work_struct
*work
)
5813 struct ixgbe_adapter
*adapter
= container_of(work
,
5814 struct ixgbe_adapter
,
5816 struct ixgbe_hw
*hw
= &adapter
->hw
;
5819 if (ixgbe_reinit_fdir_tables_82599(hw
) == 0) {
5820 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5821 set_bit(__IXGBE_TX_FDIR_INIT_DONE
,
5822 &(adapter
->tx_ring
[i
]->state
));
5824 e_err(probe
, "failed to finish FDIR re-initialization, "
5825 "ignored adding FDIR ATR filters\n");
5827 /* Done FDIR Re-initialization, enable transmits */
5828 netif_tx_start_all_queues(adapter
->netdev
);
5831 static DEFINE_MUTEX(ixgbe_watchdog_lock
);
5834 * ixgbe_watchdog_task - worker thread to bring link up
5835 * @work: pointer to work_struct containing our data
5837 static void ixgbe_watchdog_task(struct work_struct
*work
)
5839 struct ixgbe_adapter
*adapter
= container_of(work
,
5840 struct ixgbe_adapter
,
5842 struct net_device
*netdev
= adapter
->netdev
;
5843 struct ixgbe_hw
*hw
= &adapter
->hw
;
5847 struct ixgbe_ring
*tx_ring
;
5848 int some_tx_pending
= 0;
5850 mutex_lock(&ixgbe_watchdog_lock
);
5852 link_up
= adapter
->link_up
;
5853 link_speed
= adapter
->link_speed
;
5855 if (adapter
->flags
& IXGBE_FLAG_NEED_LINK_UPDATE
) {
5856 hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
, false);
5859 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
5860 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++)
5861 hw
->mac
.ops
.fc_enable(hw
, i
);
5863 hw
->mac
.ops
.fc_enable(hw
, 0);
5866 hw
->mac
.ops
.fc_enable(hw
, 0);
5871 time_after(jiffies
, (adapter
->link_check_timeout
+
5872 IXGBE_TRY_LINK_TIMEOUT
))) {
5873 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_UPDATE
;
5874 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMC_LSC
);
5876 adapter
->link_up
= link_up
;
5877 adapter
->link_speed
= link_speed
;
5881 if (!netif_carrier_ok(netdev
)) {
5882 bool flow_rx
, flow_tx
;
5884 switch (hw
->mac
.type
) {
5885 case ixgbe_mac_82598EB
: {
5886 u32 frctl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
5887 u32 rmcs
= IXGBE_READ_REG(hw
, IXGBE_RMCS
);
5888 flow_rx
= !!(frctl
& IXGBE_FCTRL_RFCE
);
5889 flow_tx
= !!(rmcs
& IXGBE_RMCS_TFCE_802_3X
);
5892 case ixgbe_mac_82599EB
: {
5893 u32 mflcn
= IXGBE_READ_REG(hw
, IXGBE_MFLCN
);
5894 u32 fccfg
= IXGBE_READ_REG(hw
, IXGBE_FCCFG
);
5895 flow_rx
= !!(mflcn
& IXGBE_MFLCN_RFCE
);
5896 flow_tx
= !!(fccfg
& IXGBE_FCCFG_TFCE_802_3X
);
5905 e_info(drv
, "NIC Link is Up %s, Flow Control: %s\n",
5906 (link_speed
== IXGBE_LINK_SPEED_10GB_FULL
?
5908 (link_speed
== IXGBE_LINK_SPEED_1GB_FULL
?
5909 "1 Gbps" : "unknown speed")),
5910 ((flow_rx
&& flow_tx
) ? "RX/TX" :
5912 (flow_tx
? "TX" : "None"))));
5914 netif_carrier_on(netdev
);
5916 /* Force detection of hung controller */
5917 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5918 tx_ring
= adapter
->tx_ring
[i
];
5919 set_check_for_tx_hang(tx_ring
);
5923 adapter
->link_up
= false;
5924 adapter
->link_speed
= 0;
5925 if (netif_carrier_ok(netdev
)) {
5926 e_info(drv
, "NIC Link is Down\n");
5927 netif_carrier_off(netdev
);
5931 if (!netif_carrier_ok(netdev
)) {
5932 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5933 tx_ring
= adapter
->tx_ring
[i
];
5934 if (tx_ring
->next_to_use
!= tx_ring
->next_to_clean
) {
5935 some_tx_pending
= 1;
5940 if (some_tx_pending
) {
5941 /* We've lost link, so the controller stops DMA,
5942 * but we've got queued Tx work that's never going
5943 * to get done, so reset controller to flush Tx.
5944 * (Do the reset outside of interrupt context).
5946 schedule_work(&adapter
->reset_task
);
5950 ixgbe_update_stats(adapter
);
5951 mutex_unlock(&ixgbe_watchdog_lock
);
5954 static int ixgbe_tso(struct ixgbe_adapter
*adapter
,
5955 struct ixgbe_ring
*tx_ring
, struct sk_buff
*skb
,
5956 u32 tx_flags
, u8
*hdr_len
, __be16 protocol
)
5958 struct ixgbe_adv_tx_context_desc
*context_desc
;
5961 struct ixgbe_tx_buffer
*tx_buffer_info
;
5962 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
;
5963 u32 mss_l4len_idx
, l4len
;
5965 if (skb_is_gso(skb
)) {
5966 if (skb_header_cloned(skb
)) {
5967 err
= pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
);
5971 l4len
= tcp_hdrlen(skb
);
5974 if (protocol
== htons(ETH_P_IP
)) {
5975 struct iphdr
*iph
= ip_hdr(skb
);
5978 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
5982 } else if (skb_is_gso_v6(skb
)) {
5983 ipv6_hdr(skb
)->payload_len
= 0;
5984 tcp_hdr(skb
)->check
=
5985 ~csum_ipv6_magic(&ipv6_hdr(skb
)->saddr
,
5986 &ipv6_hdr(skb
)->daddr
,
5990 i
= tx_ring
->next_to_use
;
5992 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5993 context_desc
= IXGBE_TX_CTXTDESC_ADV(tx_ring
, i
);
5995 /* VLAN MACLEN IPLEN */
5996 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
5998 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
5999 vlan_macip_lens
|= ((skb_network_offset(skb
)) <<
6000 IXGBE_ADVTXD_MACLEN_SHIFT
);
6001 *hdr_len
+= skb_network_offset(skb
);
6003 (skb_transport_header(skb
) - skb_network_header(skb
));
6005 (skb_transport_header(skb
) - skb_network_header(skb
));
6006 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
6007 context_desc
->seqnum_seed
= 0;
6009 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6010 type_tucmd_mlhl
= (IXGBE_TXD_CMD_DEXT
|
6011 IXGBE_ADVTXD_DTYP_CTXT
);
6013 if (protocol
== htons(ETH_P_IP
))
6014 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_IPV4
;
6015 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
6016 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
6020 (skb_shinfo(skb
)->gso_size
<< IXGBE_ADVTXD_MSS_SHIFT
);
6021 mss_l4len_idx
|= (l4len
<< IXGBE_ADVTXD_L4LEN_SHIFT
);
6022 /* use index 1 for TSO */
6023 mss_l4len_idx
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
6024 context_desc
->mss_l4len_idx
= cpu_to_le32(mss_l4len_idx
);
6026 tx_buffer_info
->time_stamp
= jiffies
;
6027 tx_buffer_info
->next_to_watch
= i
;
6030 if (i
== tx_ring
->count
)
6032 tx_ring
->next_to_use
= i
;
6039 static u32
ixgbe_psum(struct ixgbe_adapter
*adapter
, struct sk_buff
*skb
,
6045 case cpu_to_be16(ETH_P_IP
):
6046 rtn
|= IXGBE_ADVTXD_TUCMD_IPV4
;
6047 switch (ip_hdr(skb
)->protocol
) {
6049 rtn
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
6052 rtn
|= IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
6056 case cpu_to_be16(ETH_P_IPV6
):
6057 /* XXX what about other V6 headers?? */
6058 switch (ipv6_hdr(skb
)->nexthdr
) {
6060 rtn
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
6063 rtn
|= IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
6068 if (unlikely(net_ratelimit()))
6069 e_warn(probe
, "partial checksum but proto=%x!\n",
6077 static bool ixgbe_tx_csum(struct ixgbe_adapter
*adapter
,
6078 struct ixgbe_ring
*tx_ring
,
6079 struct sk_buff
*skb
, u32 tx_flags
,
6082 struct ixgbe_adv_tx_context_desc
*context_desc
;
6084 struct ixgbe_tx_buffer
*tx_buffer_info
;
6085 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
= 0;
6087 if (skb
->ip_summed
== CHECKSUM_PARTIAL
||
6088 (tx_flags
& IXGBE_TX_FLAGS_VLAN
)) {
6089 i
= tx_ring
->next_to_use
;
6090 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6091 context_desc
= IXGBE_TX_CTXTDESC_ADV(tx_ring
, i
);
6093 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
6095 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
6096 vlan_macip_lens
|= (skb_network_offset(skb
) <<
6097 IXGBE_ADVTXD_MACLEN_SHIFT
);
6098 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
6099 vlan_macip_lens
|= (skb_transport_header(skb
) -
6100 skb_network_header(skb
));
6102 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
6103 context_desc
->seqnum_seed
= 0;
6105 type_tucmd_mlhl
|= (IXGBE_TXD_CMD_DEXT
|
6106 IXGBE_ADVTXD_DTYP_CTXT
);
6108 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
6109 type_tucmd_mlhl
|= ixgbe_psum(adapter
, skb
, protocol
);
6111 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
6112 /* use index zero for tx checksum offload */
6113 context_desc
->mss_l4len_idx
= 0;
6115 tx_buffer_info
->time_stamp
= jiffies
;
6116 tx_buffer_info
->next_to_watch
= i
;
6119 if (i
== tx_ring
->count
)
6121 tx_ring
->next_to_use
= i
;
6129 static int ixgbe_tx_map(struct ixgbe_adapter
*adapter
,
6130 struct ixgbe_ring
*tx_ring
,
6131 struct sk_buff
*skb
, u32 tx_flags
,
6132 unsigned int first
, const u8 hdr_len
)
6134 struct device
*dev
= tx_ring
->dev
;
6135 struct ixgbe_tx_buffer
*tx_buffer_info
;
6137 unsigned int total
= skb
->len
;
6138 unsigned int offset
= 0, size
, count
= 0, i
;
6139 unsigned int nr_frags
= skb_shinfo(skb
)->nr_frags
;
6141 unsigned int bytecount
= skb
->len
;
6144 i
= tx_ring
->next_to_use
;
6146 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
)
6147 /* excluding fcoe_crc_eof for FCoE */
6148 total
-= sizeof(struct fcoe_crc_eof
);
6150 len
= min(skb_headlen(skb
), total
);
6152 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6153 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
6155 tx_buffer_info
->length
= size
;
6156 tx_buffer_info
->mapped_as_page
= false;
6157 tx_buffer_info
->dma
= dma_map_single(dev
,
6159 size
, DMA_TO_DEVICE
);
6160 if (dma_mapping_error(dev
, tx_buffer_info
->dma
))
6162 tx_buffer_info
->time_stamp
= jiffies
;
6163 tx_buffer_info
->next_to_watch
= i
;
6172 if (i
== tx_ring
->count
)
6177 for (f
= 0; f
< nr_frags
; f
++) {
6178 struct skb_frag_struct
*frag
;
6180 frag
= &skb_shinfo(skb
)->frags
[f
];
6181 len
= min((unsigned int)frag
->size
, total
);
6182 offset
= frag
->page_offset
;
6186 if (i
== tx_ring
->count
)
6189 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6190 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
6192 tx_buffer_info
->length
= size
;
6193 tx_buffer_info
->dma
= dma_map_page(dev
,
6197 tx_buffer_info
->mapped_as_page
= true;
6198 if (dma_mapping_error(dev
, tx_buffer_info
->dma
))
6200 tx_buffer_info
->time_stamp
= jiffies
;
6201 tx_buffer_info
->next_to_watch
= i
;
6212 if (tx_flags
& IXGBE_TX_FLAGS_TSO
)
6213 gso_segs
= skb_shinfo(skb
)->gso_segs
;
6215 /* adjust for FCoE Sequence Offload */
6216 else if (tx_flags
& IXGBE_TX_FLAGS_FSO
)
6217 gso_segs
= DIV_ROUND_UP(skb
->len
- hdr_len
,
6218 skb_shinfo(skb
)->gso_size
);
6219 #endif /* IXGBE_FCOE */
6220 bytecount
+= (gso_segs
- 1) * hdr_len
;
6222 /* multiply data chunks by size of headers */
6223 tx_ring
->tx_buffer_info
[i
].bytecount
= bytecount
;
6224 tx_ring
->tx_buffer_info
[i
].gso_segs
= gso_segs
;
6225 tx_ring
->tx_buffer_info
[i
].skb
= skb
;
6226 tx_ring
->tx_buffer_info
[first
].next_to_watch
= i
;
6231 e_dev_err("TX DMA map failed\n");
6233 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6234 tx_buffer_info
->dma
= 0;
6235 tx_buffer_info
->time_stamp
= 0;
6236 tx_buffer_info
->next_to_watch
= 0;
6240 /* clear timestamp and dma mappings for remaining portion of packet */
6243 i
+= tx_ring
->count
;
6245 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6246 ixgbe_unmap_and_free_tx_resource(tx_ring
, tx_buffer_info
);
6252 static void ixgbe_tx_queue(struct ixgbe_ring
*tx_ring
,
6253 int tx_flags
, int count
, u32 paylen
, u8 hdr_len
)
6255 union ixgbe_adv_tx_desc
*tx_desc
= NULL
;
6256 struct ixgbe_tx_buffer
*tx_buffer_info
;
6257 u32 olinfo_status
= 0, cmd_type_len
= 0;
6259 u32 txd_cmd
= IXGBE_TXD_CMD_EOP
| IXGBE_TXD_CMD_RS
| IXGBE_TXD_CMD_IFCS
;
6261 cmd_type_len
|= IXGBE_ADVTXD_DTYP_DATA
;
6263 cmd_type_len
|= IXGBE_ADVTXD_DCMD_IFCS
| IXGBE_ADVTXD_DCMD_DEXT
;
6265 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
6266 cmd_type_len
|= IXGBE_ADVTXD_DCMD_VLE
;
6268 if (tx_flags
& IXGBE_TX_FLAGS_TSO
) {
6269 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
6271 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
6272 IXGBE_ADVTXD_POPTS_SHIFT
;
6274 /* use index 1 context for tso */
6275 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
6276 if (tx_flags
& IXGBE_TX_FLAGS_IPV4
)
6277 olinfo_status
|= IXGBE_TXD_POPTS_IXSM
<<
6278 IXGBE_ADVTXD_POPTS_SHIFT
;
6280 } else if (tx_flags
& IXGBE_TX_FLAGS_CSUM
)
6281 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
6282 IXGBE_ADVTXD_POPTS_SHIFT
;
6284 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
6285 olinfo_status
|= IXGBE_ADVTXD_CC
;
6286 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
6287 if (tx_flags
& IXGBE_TX_FLAGS_FSO
)
6288 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
6291 olinfo_status
|= ((paylen
- hdr_len
) << IXGBE_ADVTXD_PAYLEN_SHIFT
);
6293 i
= tx_ring
->next_to_use
;
6295 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6296 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, i
);
6297 tx_desc
->read
.buffer_addr
= cpu_to_le64(tx_buffer_info
->dma
);
6298 tx_desc
->read
.cmd_type_len
=
6299 cpu_to_le32(cmd_type_len
| tx_buffer_info
->length
);
6300 tx_desc
->read
.olinfo_status
= cpu_to_le32(olinfo_status
);
6302 if (i
== tx_ring
->count
)
6306 tx_desc
->read
.cmd_type_len
|= cpu_to_le32(txd_cmd
);
6309 * Force memory writes to complete before letting h/w
6310 * know there are new descriptors to fetch. (Only
6311 * applicable for weak-ordered memory model archs,
6316 tx_ring
->next_to_use
= i
;
6317 writel(i
, tx_ring
->tail
);
6320 static void ixgbe_atr(struct ixgbe_adapter
*adapter
, struct sk_buff
*skb
,
6321 u8 queue
, u32 tx_flags
, __be16 protocol
)
6323 struct ixgbe_atr_input atr_input
;
6324 struct iphdr
*iph
= ip_hdr(skb
);
6325 struct ethhdr
*eth
= (struct ethhdr
*)skb
->data
;
6329 /* Right now, we support IPv4 w/ TCP only */
6330 if (protocol
!= htons(ETH_P_IP
) ||
6331 iph
->protocol
!= IPPROTO_TCP
)
6334 memset(&atr_input
, 0, sizeof(struct ixgbe_atr_input
));
6336 vlan_id
= (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
) >>
6337 IXGBE_TX_FLAGS_VLAN_SHIFT
;
6341 ixgbe_atr_set_vlan_id_82599(&atr_input
, vlan_id
);
6342 ixgbe_atr_set_src_port_82599(&atr_input
, th
->dest
);
6343 ixgbe_atr_set_dst_port_82599(&atr_input
, th
->source
);
6344 ixgbe_atr_set_flex_byte_82599(&atr_input
, eth
->h_proto
);
6345 ixgbe_atr_set_l4type_82599(&atr_input
, IXGBE_ATR_L4TYPE_TCP
);
6346 /* src and dst are inverted, think how the receiver sees them */
6347 ixgbe_atr_set_src_ipv4_82599(&atr_input
, iph
->daddr
);
6348 ixgbe_atr_set_dst_ipv4_82599(&atr_input
, iph
->saddr
);
6350 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6351 ixgbe_fdir_add_signature_filter_82599(&adapter
->hw
, &atr_input
, queue
);
6354 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring
*tx_ring
, int size
)
6356 netif_stop_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
6357 /* Herbert's original patch had:
6358 * smp_mb__after_netif_stop_queue();
6359 * but since that doesn't exist yet, just open code it. */
6362 /* We need to check again in a case another CPU has just
6363 * made room available. */
6364 if (likely(IXGBE_DESC_UNUSED(tx_ring
) < size
))
6367 /* A reprieve! - use start_queue because it doesn't call schedule */
6368 netif_start_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
6369 ++tx_ring
->tx_stats
.restart_queue
;
6373 static int ixgbe_maybe_stop_tx(struct ixgbe_ring
*tx_ring
, int size
)
6375 if (likely(IXGBE_DESC_UNUSED(tx_ring
) >= size
))
6377 return __ixgbe_maybe_stop_tx(tx_ring
, size
);
6380 static u16
ixgbe_select_queue(struct net_device
*dev
, struct sk_buff
*skb
)
6382 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6383 int txq
= smp_processor_id();
6387 protocol
= vlan_get_protocol(skb
);
6389 if ((protocol
== htons(ETH_P_FCOE
)) ||
6390 (protocol
== htons(ETH_P_FIP
))) {
6391 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
6392 txq
&= (adapter
->ring_feature
[RING_F_FCOE
].indices
- 1);
6393 txq
+= adapter
->ring_feature
[RING_F_FCOE
].mask
;
6395 #ifdef CONFIG_IXGBE_DCB
6396 } else if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6397 txq
= adapter
->fcoe
.up
;
6404 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
6405 while (unlikely(txq
>= dev
->real_num_tx_queues
))
6406 txq
-= dev
->real_num_tx_queues
;
6410 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6411 if (skb
->priority
== TC_PRIO_CONTROL
)
6412 txq
= adapter
->ring_feature
[RING_F_DCB
].indices
-1;
6414 txq
= (skb
->vlan_tci
& IXGBE_TX_FLAGS_VLAN_PRIO_MASK
)
6419 return skb_tx_hash(dev
, skb
);
6422 netdev_tx_t
ixgbe_xmit_frame_ring(struct sk_buff
*skb
,
6423 struct ixgbe_adapter
*adapter
,
6424 struct ixgbe_ring
*tx_ring
)
6426 struct net_device
*netdev
= tx_ring
->netdev
;
6427 struct netdev_queue
*txq
;
6429 unsigned int tx_flags
= 0;
6436 protocol
= vlan_get_protocol(skb
);
6438 if (vlan_tx_tag_present(skb
)) {
6439 tx_flags
|= vlan_tx_tag_get(skb
);
6440 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6441 tx_flags
&= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK
;
6442 tx_flags
|= ((skb
->queue_mapping
& 0x7) << 13);
6444 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
6445 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
6446 } else if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
&&
6447 skb
->priority
!= TC_PRIO_CONTROL
) {
6448 tx_flags
|= ((skb
->queue_mapping
& 0x7) << 13);
6449 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
6450 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
6454 /* for FCoE with DCB, we force the priority to what
6455 * was specified by the switch */
6456 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
&&
6457 (protocol
== htons(ETH_P_FCOE
) ||
6458 protocol
== htons(ETH_P_FIP
))) {
6459 #ifdef CONFIG_IXGBE_DCB
6460 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6461 tx_flags
&= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6462 << IXGBE_TX_FLAGS_VLAN_SHIFT
);
6463 tx_flags
|= ((adapter
->fcoe
.up
<< 13)
6464 << IXGBE_TX_FLAGS_VLAN_SHIFT
);
6467 /* flag for FCoE offloads */
6468 if (protocol
== htons(ETH_P_FCOE
))
6469 tx_flags
|= IXGBE_TX_FLAGS_FCOE
;
6473 /* four things can cause us to need a context descriptor */
6474 if (skb_is_gso(skb
) ||
6475 (skb
->ip_summed
== CHECKSUM_PARTIAL
) ||
6476 (tx_flags
& IXGBE_TX_FLAGS_VLAN
) ||
6477 (tx_flags
& IXGBE_TX_FLAGS_FCOE
))
6480 count
+= TXD_USE_COUNT(skb_headlen(skb
));
6481 for (f
= 0; f
< skb_shinfo(skb
)->nr_frags
; f
++)
6482 count
+= TXD_USE_COUNT(skb_shinfo(skb
)->frags
[f
].size
);
6484 if (ixgbe_maybe_stop_tx(tx_ring
, count
)) {
6485 tx_ring
->tx_stats
.tx_busy
++;
6486 return NETDEV_TX_BUSY
;
6489 first
= tx_ring
->next_to_use
;
6490 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
6492 /* setup tx offload for FCoE */
6493 tso
= ixgbe_fso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
);
6495 dev_kfree_skb_any(skb
);
6496 return NETDEV_TX_OK
;
6499 tx_flags
|= IXGBE_TX_FLAGS_FSO
;
6500 #endif /* IXGBE_FCOE */
6502 if (protocol
== htons(ETH_P_IP
))
6503 tx_flags
|= IXGBE_TX_FLAGS_IPV4
;
6504 tso
= ixgbe_tso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
,
6507 dev_kfree_skb_any(skb
);
6508 return NETDEV_TX_OK
;
6512 tx_flags
|= IXGBE_TX_FLAGS_TSO
;
6513 else if (ixgbe_tx_csum(adapter
, tx_ring
, skb
, tx_flags
,
6515 (skb
->ip_summed
== CHECKSUM_PARTIAL
))
6516 tx_flags
|= IXGBE_TX_FLAGS_CSUM
;
6519 count
= ixgbe_tx_map(adapter
, tx_ring
, skb
, tx_flags
, first
, hdr_len
);
6521 /* add the ATR filter if ATR is on */
6522 if (tx_ring
->atr_sample_rate
) {
6523 ++tx_ring
->atr_count
;
6524 if ((tx_ring
->atr_count
>= tx_ring
->atr_sample_rate
) &&
6525 test_bit(__IXGBE_TX_FDIR_INIT_DONE
,
6527 ixgbe_atr(adapter
, skb
, tx_ring
->queue_index
,
6528 tx_flags
, protocol
);
6529 tx_ring
->atr_count
= 0;
6532 txq
= netdev_get_tx_queue(netdev
, tx_ring
->queue_index
);
6533 txq
->tx_bytes
+= skb
->len
;
6535 ixgbe_tx_queue(tx_ring
, tx_flags
, count
, skb
->len
, hdr_len
);
6536 ixgbe_maybe_stop_tx(tx_ring
, DESC_NEEDED
);
6539 dev_kfree_skb_any(skb
);
6540 tx_ring
->tx_buffer_info
[first
].time_stamp
= 0;
6541 tx_ring
->next_to_use
= first
;
6544 return NETDEV_TX_OK
;
6547 static netdev_tx_t
ixgbe_xmit_frame(struct sk_buff
*skb
, struct net_device
*netdev
)
6549 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6550 struct ixgbe_ring
*tx_ring
;
6552 tx_ring
= adapter
->tx_ring
[skb
->queue_mapping
];
6553 return ixgbe_xmit_frame_ring(skb
, adapter
, tx_ring
);
6557 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6558 * @netdev: network interface device structure
6559 * @p: pointer to an address structure
6561 * Returns 0 on success, negative on failure
6563 static int ixgbe_set_mac(struct net_device
*netdev
, void *p
)
6565 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6566 struct ixgbe_hw
*hw
= &adapter
->hw
;
6567 struct sockaddr
*addr
= p
;
6569 if (!is_valid_ether_addr(addr
->sa_data
))
6570 return -EADDRNOTAVAIL
;
6572 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
6573 memcpy(hw
->mac
.addr
, addr
->sa_data
, netdev
->addr_len
);
6575 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
6582 ixgbe_mdio_read(struct net_device
*netdev
, int prtad
, int devad
, u16 addr
)
6584 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6585 struct ixgbe_hw
*hw
= &adapter
->hw
;
6589 if (prtad
!= hw
->phy
.mdio
.prtad
)
6591 rc
= hw
->phy
.ops
.read_reg(hw
, addr
, devad
, &value
);
6597 static int ixgbe_mdio_write(struct net_device
*netdev
, int prtad
, int devad
,
6598 u16 addr
, u16 value
)
6600 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6601 struct ixgbe_hw
*hw
= &adapter
->hw
;
6603 if (prtad
!= hw
->phy
.mdio
.prtad
)
6605 return hw
->phy
.ops
.write_reg(hw
, addr
, devad
, value
);
6608 static int ixgbe_ioctl(struct net_device
*netdev
, struct ifreq
*req
, int cmd
)
6610 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6612 return mdio_mii_ioctl(&adapter
->hw
.phy
.mdio
, if_mii(req
), cmd
);
6616 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6618 * @netdev: network interface device structure
6620 * Returns non-zero on failure
6622 static int ixgbe_add_sanmac_netdev(struct net_device
*dev
)
6625 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6626 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
6628 if (is_valid_ether_addr(mac
->san_addr
)) {
6630 err
= dev_addr_add(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
6637 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6639 * @netdev: network interface device structure
6641 * Returns non-zero on failure
6643 static int ixgbe_del_sanmac_netdev(struct net_device
*dev
)
6646 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6647 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
6649 if (is_valid_ether_addr(mac
->san_addr
)) {
6651 err
= dev_addr_del(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
6657 #ifdef CONFIG_NET_POLL_CONTROLLER
6659 * Polling 'interrupt' - used by things like netconsole to send skbs
6660 * without having to re-enable interrupts. It's not called while
6661 * the interrupt routine is executing.
6663 static void ixgbe_netpoll(struct net_device
*netdev
)
6665 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6668 /* if interface is down do nothing */
6669 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
6672 adapter
->flags
|= IXGBE_FLAG_IN_NETPOLL
;
6673 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
6674 int num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
6675 for (i
= 0; i
< num_q_vectors
; i
++) {
6676 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
6677 ixgbe_msix_clean_many(0, q_vector
);
6680 ixgbe_intr(adapter
->pdev
->irq
, netdev
);
6682 adapter
->flags
&= ~IXGBE_FLAG_IN_NETPOLL
;
6686 static struct rtnl_link_stats64
*ixgbe_get_stats64(struct net_device
*netdev
,
6687 struct rtnl_link_stats64
*stats
)
6689 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6692 /* accurate rx/tx bytes/packets stats */
6693 dev_txq_stats_fold(netdev
, stats
);
6695 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
6696 struct ixgbe_ring
*ring
= ACCESS_ONCE(adapter
->rx_ring
[i
]);
6702 start
= u64_stats_fetch_begin_bh(&ring
->syncp
);
6703 packets
= ring
->stats
.packets
;
6704 bytes
= ring
->stats
.bytes
;
6705 } while (u64_stats_fetch_retry_bh(&ring
->syncp
, start
));
6706 stats
->rx_packets
+= packets
;
6707 stats
->rx_bytes
+= bytes
;
6711 /* following stats updated by ixgbe_watchdog_task() */
6712 stats
->multicast
= netdev
->stats
.multicast
;
6713 stats
->rx_errors
= netdev
->stats
.rx_errors
;
6714 stats
->rx_length_errors
= netdev
->stats
.rx_length_errors
;
6715 stats
->rx_crc_errors
= netdev
->stats
.rx_crc_errors
;
6716 stats
->rx_missed_errors
= netdev
->stats
.rx_missed_errors
;
6721 static const struct net_device_ops ixgbe_netdev_ops
= {
6722 .ndo_open
= ixgbe_open
,
6723 .ndo_stop
= ixgbe_close
,
6724 .ndo_start_xmit
= ixgbe_xmit_frame
,
6725 .ndo_select_queue
= ixgbe_select_queue
,
6726 .ndo_set_rx_mode
= ixgbe_set_rx_mode
,
6727 .ndo_set_multicast_list
= ixgbe_set_rx_mode
,
6728 .ndo_validate_addr
= eth_validate_addr
,
6729 .ndo_set_mac_address
= ixgbe_set_mac
,
6730 .ndo_change_mtu
= ixgbe_change_mtu
,
6731 .ndo_tx_timeout
= ixgbe_tx_timeout
,
6732 .ndo_vlan_rx_add_vid
= ixgbe_vlan_rx_add_vid
,
6733 .ndo_vlan_rx_kill_vid
= ixgbe_vlan_rx_kill_vid
,
6734 .ndo_do_ioctl
= ixgbe_ioctl
,
6735 .ndo_set_vf_mac
= ixgbe_ndo_set_vf_mac
,
6736 .ndo_set_vf_vlan
= ixgbe_ndo_set_vf_vlan
,
6737 .ndo_set_vf_tx_rate
= ixgbe_ndo_set_vf_bw
,
6738 .ndo_get_vf_config
= ixgbe_ndo_get_vf_config
,
6739 .ndo_get_stats64
= ixgbe_get_stats64
,
6740 #ifdef CONFIG_NET_POLL_CONTROLLER
6741 .ndo_poll_controller
= ixgbe_netpoll
,
6744 .ndo_fcoe_ddp_setup
= ixgbe_fcoe_ddp_get
,
6745 .ndo_fcoe_ddp_done
= ixgbe_fcoe_ddp_put
,
6746 .ndo_fcoe_enable
= ixgbe_fcoe_enable
,
6747 .ndo_fcoe_disable
= ixgbe_fcoe_disable
,
6748 .ndo_fcoe_get_wwn
= ixgbe_fcoe_get_wwn
,
6749 #endif /* IXGBE_FCOE */
6752 static void __devinit
ixgbe_probe_vf(struct ixgbe_adapter
*adapter
,
6753 const struct ixgbe_info
*ii
)
6755 #ifdef CONFIG_PCI_IOV
6756 struct ixgbe_hw
*hw
= &adapter
->hw
;
6759 if (hw
->mac
.type
!= ixgbe_mac_82599EB
|| !max_vfs
)
6762 /* The 82599 supports up to 64 VFs per physical function
6763 * but this implementation limits allocation to 63 so that
6764 * basic networking resources are still available to the
6767 adapter
->num_vfs
= (max_vfs
> 63) ? 63 : max_vfs
;
6768 adapter
->flags
|= IXGBE_FLAG_SRIOV_ENABLED
;
6769 err
= pci_enable_sriov(adapter
->pdev
, adapter
->num_vfs
);
6771 e_err(probe
, "Failed to enable PCI sriov: %d\n", err
);
6774 /* If call to enable VFs succeeded then allocate memory
6775 * for per VF control structures.
6778 kcalloc(adapter
->num_vfs
,
6779 sizeof(struct vf_data_storage
), GFP_KERNEL
);
6780 if (adapter
->vfinfo
) {
6781 /* Now that we're sure SR-IOV is enabled
6782 * and memory allocated set up the mailbox parameters
6784 ixgbe_init_mbx_params_pf(hw
);
6785 memcpy(&hw
->mbx
.ops
, ii
->mbx_ops
,
6786 sizeof(hw
->mbx
.ops
));
6788 /* Disable RSC when in SR-IOV mode */
6789 adapter
->flags2
&= ~(IXGBE_FLAG2_RSC_CAPABLE
|
6790 IXGBE_FLAG2_RSC_ENABLED
);
6795 e_err(probe
, "Unable to allocate memory for VF Data Storage - "
6796 "SRIOV disabled\n");
6797 pci_disable_sriov(adapter
->pdev
);
6800 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
6801 adapter
->num_vfs
= 0;
6802 #endif /* CONFIG_PCI_IOV */
6806 * ixgbe_probe - Device Initialization Routine
6807 * @pdev: PCI device information struct
6808 * @ent: entry in ixgbe_pci_tbl
6810 * Returns 0 on success, negative on failure
6812 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6813 * The OS initialization, configuring of the adapter private structure,
6814 * and a hardware reset occur.
6816 static int __devinit
ixgbe_probe(struct pci_dev
*pdev
,
6817 const struct pci_device_id
*ent
)
6819 struct net_device
*netdev
;
6820 struct ixgbe_adapter
*adapter
= NULL
;
6821 struct ixgbe_hw
*hw
;
6822 const struct ixgbe_info
*ii
= ixgbe_info_tbl
[ent
->driver_data
];
6823 static int cards_found
;
6824 int i
, err
, pci_using_dac
;
6825 unsigned int indices
= num_possible_cpus();
6831 /* Catch broken hardware that put the wrong VF device ID in
6832 * the PCIe SR-IOV capability.
6834 if (pdev
->is_virtfn
) {
6835 WARN(1, KERN_ERR
"%s (%hx:%hx) should not be a VF!\n",
6836 pci_name(pdev
), pdev
->vendor
, pdev
->device
);
6840 err
= pci_enable_device_mem(pdev
);
6844 if (!dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(64)) &&
6845 !dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(64))) {
6848 err
= dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(32));
6850 err
= dma_set_coherent_mask(&pdev
->dev
,
6854 "No usable DMA configuration, aborting\n");
6861 err
= pci_request_selected_regions(pdev
, pci_select_bars(pdev
,
6862 IORESOURCE_MEM
), ixgbe_driver_name
);
6865 "pci_request_selected_regions failed 0x%x\n", err
);
6869 pci_enable_pcie_error_reporting(pdev
);
6871 pci_set_master(pdev
);
6872 pci_save_state(pdev
);
6874 if (ii
->mac
== ixgbe_mac_82598EB
)
6875 indices
= min_t(unsigned int, indices
, IXGBE_MAX_RSS_INDICES
);
6877 indices
= min_t(unsigned int, indices
, IXGBE_MAX_FDIR_INDICES
);
6879 indices
= max_t(unsigned int, indices
, IXGBE_MAX_DCB_INDICES
);
6881 indices
+= min_t(unsigned int, num_possible_cpus(),
6882 IXGBE_MAX_FCOE_INDICES
);
6884 netdev
= alloc_etherdev_mq(sizeof(struct ixgbe_adapter
), indices
);
6887 goto err_alloc_etherdev
;
6890 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
6892 adapter
= netdev_priv(netdev
);
6893 pci_set_drvdata(pdev
, adapter
);
6895 adapter
->netdev
= netdev
;
6896 adapter
->pdev
= pdev
;
6899 adapter
->msg_enable
= (1 << DEFAULT_DEBUG_LEVEL_SHIFT
) - 1;
6901 hw
->hw_addr
= ioremap(pci_resource_start(pdev
, 0),
6902 pci_resource_len(pdev
, 0));
6908 for (i
= 1; i
<= 5; i
++) {
6909 if (pci_resource_len(pdev
, i
) == 0)
6913 netdev
->netdev_ops
= &ixgbe_netdev_ops
;
6914 ixgbe_set_ethtool_ops(netdev
);
6915 netdev
->watchdog_timeo
= 5 * HZ
;
6916 strcpy(netdev
->name
, pci_name(pdev
));
6918 adapter
->bd_number
= cards_found
;
6921 memcpy(&hw
->mac
.ops
, ii
->mac_ops
, sizeof(hw
->mac
.ops
));
6922 hw
->mac
.type
= ii
->mac
;
6925 memcpy(&hw
->eeprom
.ops
, ii
->eeprom_ops
, sizeof(hw
->eeprom
.ops
));
6926 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
6927 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6928 if (!(eec
& (1 << 8)))
6929 hw
->eeprom
.ops
.read
= &ixgbe_read_eeprom_bit_bang_generic
;
6932 memcpy(&hw
->phy
.ops
, ii
->phy_ops
, sizeof(hw
->phy
.ops
));
6933 hw
->phy
.sfp_type
= ixgbe_sfp_type_unknown
;
6934 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6935 hw
->phy
.mdio
.prtad
= MDIO_PRTAD_NONE
;
6936 hw
->phy
.mdio
.mmds
= 0;
6937 hw
->phy
.mdio
.mode_support
= MDIO_SUPPORTS_C45
| MDIO_EMULATE_C22
;
6938 hw
->phy
.mdio
.dev
= netdev
;
6939 hw
->phy
.mdio
.mdio_read
= ixgbe_mdio_read
;
6940 hw
->phy
.mdio
.mdio_write
= ixgbe_mdio_write
;
6942 /* set up this timer and work struct before calling get_invariants
6943 * which might start the timer
6945 init_timer(&adapter
->sfp_timer
);
6946 adapter
->sfp_timer
.function
= ixgbe_sfp_timer
;
6947 adapter
->sfp_timer
.data
= (unsigned long) adapter
;
6949 INIT_WORK(&adapter
->sfp_task
, ixgbe_sfp_task
);
6951 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6952 INIT_WORK(&adapter
->multispeed_fiber_task
, ixgbe_multispeed_fiber_task
);
6954 /* a new SFP+ module arrival, called from GPI SDP2 context */
6955 INIT_WORK(&adapter
->sfp_config_module_task
,
6956 ixgbe_sfp_config_module_task
);
6958 ii
->get_invariants(hw
);
6960 /* setup the private structure */
6961 err
= ixgbe_sw_init(adapter
);
6965 /* Make it possible the adapter to be woken up via WOL */
6966 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
6967 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
6970 * If there is a fan on this device and it has failed log the
6973 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
6974 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
6975 if (esdp
& IXGBE_ESDP_SDP1
)
6976 e_crit(probe
, "Fan has stopped, replace the adapter\n");
6979 /* reset_hw fills in the perm_addr as well */
6980 hw
->phy
.reset_if_overtemp
= true;
6981 err
= hw
->mac
.ops
.reset_hw(hw
);
6982 hw
->phy
.reset_if_overtemp
= false;
6983 if (err
== IXGBE_ERR_SFP_NOT_PRESENT
&&
6984 hw
->mac
.type
== ixgbe_mac_82598EB
) {
6986 * Start a kernel thread to watch for a module to arrive.
6987 * Only do this for 82598, since 82599 will generate
6988 * interrupts on module arrival.
6990 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
6991 mod_timer(&adapter
->sfp_timer
,
6992 round_jiffies(jiffies
+ (2 * HZ
)));
6994 } else if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
6995 e_dev_err("failed to initialize because an unsupported SFP+ "
6996 "module type was detected.\n");
6997 e_dev_err("Reload the driver after installing a supported "
7001 e_dev_err("HW Init failed: %d\n", err
);
7005 ixgbe_probe_vf(adapter
, ii
);
7007 netdev
->features
= NETIF_F_SG
|
7009 NETIF_F_HW_VLAN_TX
|
7010 NETIF_F_HW_VLAN_RX
|
7011 NETIF_F_HW_VLAN_FILTER
;
7013 netdev
->features
|= NETIF_F_IPV6_CSUM
;
7014 netdev
->features
|= NETIF_F_TSO
;
7015 netdev
->features
|= NETIF_F_TSO6
;
7016 netdev
->features
|= NETIF_F_GRO
;
7018 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
7019 netdev
->features
|= NETIF_F_SCTP_CSUM
;
7021 netdev
->vlan_features
|= NETIF_F_TSO
;
7022 netdev
->vlan_features
|= NETIF_F_TSO6
;
7023 netdev
->vlan_features
|= NETIF_F_IP_CSUM
;
7024 netdev
->vlan_features
|= NETIF_F_IPV6_CSUM
;
7025 netdev
->vlan_features
|= NETIF_F_SG
;
7027 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
7028 adapter
->flags
&= ~(IXGBE_FLAG_RSS_ENABLED
|
7029 IXGBE_FLAG_DCB_ENABLED
);
7030 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)
7031 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
7033 #ifdef CONFIG_IXGBE_DCB
7034 netdev
->dcbnl_ops
= &dcbnl_ops
;
7038 if (adapter
->flags
& IXGBE_FLAG_FCOE_CAPABLE
) {
7039 if (hw
->mac
.ops
.get_device_caps
) {
7040 hw
->mac
.ops
.get_device_caps(hw
, &device_caps
);
7041 if (device_caps
& IXGBE_DEVICE_CAPS_FCOE_OFFLOADS
)
7042 adapter
->flags
&= ~IXGBE_FLAG_FCOE_CAPABLE
;
7045 if (adapter
->flags
& IXGBE_FLAG_FCOE_CAPABLE
) {
7046 netdev
->vlan_features
|= NETIF_F_FCOE_CRC
;
7047 netdev
->vlan_features
|= NETIF_F_FSO
;
7048 netdev
->vlan_features
|= NETIF_F_FCOE_MTU
;
7050 #endif /* IXGBE_FCOE */
7051 if (pci_using_dac
) {
7052 netdev
->features
|= NETIF_F_HIGHDMA
;
7053 netdev
->vlan_features
|= NETIF_F_HIGHDMA
;
7056 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
)
7057 netdev
->features
|= NETIF_F_LRO
;
7059 /* make sure the EEPROM is good */
7060 if (hw
->eeprom
.ops
.validate_checksum(hw
, NULL
) < 0) {
7061 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7066 memcpy(netdev
->dev_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
7067 memcpy(netdev
->perm_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
7069 if (ixgbe_validate_mac_addr(netdev
->perm_addr
)) {
7070 e_dev_err("invalid MAC address\n");
7075 /* power down the optics */
7076 if (hw
->phy
.multispeed_fiber
)
7077 hw
->mac
.ops
.disable_tx_laser(hw
);
7079 init_timer(&adapter
->watchdog_timer
);
7080 adapter
->watchdog_timer
.function
= ixgbe_watchdog
;
7081 adapter
->watchdog_timer
.data
= (unsigned long)adapter
;
7083 INIT_WORK(&adapter
->reset_task
, ixgbe_reset_task
);
7084 INIT_WORK(&adapter
->watchdog_task
, ixgbe_watchdog_task
);
7086 err
= ixgbe_init_interrupt_scheme(adapter
);
7090 switch (pdev
->device
) {
7091 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE
:
7092 /* All except this subdevice support WOL */
7093 if (pdev
->subsystem_device
==
7094 IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ
) {
7098 case IXGBE_DEV_ID_82599_KX4
:
7099 adapter
->wol
= (IXGBE_WUFC_MAG
| IXGBE_WUFC_EX
|
7100 IXGBE_WUFC_MC
| IXGBE_WUFC_BC
);
7106 device_set_wakeup_enable(&adapter
->pdev
->dev
, adapter
->wol
);
7108 /* pick up the PCI bus settings for reporting later */
7109 hw
->mac
.ops
.get_bus_info(hw
);
7111 /* print bus type/speed/width info */
7112 e_dev_info("(PCI Express:%s:%s) %pM\n",
7113 (hw
->bus
.speed
== ixgbe_bus_speed_5000
? "5.0Gb/s" :
7114 hw
->bus
.speed
== ixgbe_bus_speed_2500
? "2.5Gb/s" :
7116 (hw
->bus
.width
== ixgbe_bus_width_pcie_x8
? "Width x8" :
7117 hw
->bus
.width
== ixgbe_bus_width_pcie_x4
? "Width x4" :
7118 hw
->bus
.width
== ixgbe_bus_width_pcie_x1
? "Width x1" :
7121 ixgbe_read_pba_num_generic(hw
, &part_num
);
7122 if (ixgbe_is_sfp(hw
) && hw
->phy
.sfp_type
!= ixgbe_sfp_type_not_present
)
7123 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
7124 "PBA No: %06x-%03x\n",
7125 hw
->mac
.type
, hw
->phy
.type
, hw
->phy
.sfp_type
,
7126 (part_num
>> 8), (part_num
& 0xff));
7128 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
7129 hw
->mac
.type
, hw
->phy
.type
,
7130 (part_num
>> 8), (part_num
& 0xff));
7132 if (hw
->bus
.width
<= ixgbe_bus_width_pcie_x4
) {
7133 e_dev_warn("PCI-Express bandwidth available for this card is "
7134 "not sufficient for optimal performance.\n");
7135 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7139 /* save off EEPROM version number */
7140 hw
->eeprom
.ops
.read(hw
, 0x29, &adapter
->eeprom_version
);
7142 /* reset the hardware with the new settings */
7143 err
= hw
->mac
.ops
.start_hw(hw
);
7145 if (err
== IXGBE_ERR_EEPROM_VERSION
) {
7146 /* We are running on a pre-production device, log a warning */
7147 e_dev_warn("This device is a pre-production adapter/LOM. "
7148 "Please be aware there may be issues associated "
7149 "with your hardware. If you are experiencing "
7150 "problems please contact your Intel or hardware "
7151 "representative who provided you with this "
7154 strcpy(netdev
->name
, "eth%d");
7155 err
= register_netdev(netdev
);
7159 /* carrier off reporting is important to ethtool even BEFORE open */
7160 netif_carrier_off(netdev
);
7162 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
7163 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
7164 INIT_WORK(&adapter
->fdir_reinit_task
, ixgbe_fdir_reinit_task
);
7166 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
)
7167 INIT_WORK(&adapter
->check_overtemp_task
,
7168 ixgbe_check_overtemp_task
);
7169 #ifdef CONFIG_IXGBE_DCA
7170 if (dca_add_requester(&pdev
->dev
) == 0) {
7171 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
7172 ixgbe_setup_dca(adapter
);
7175 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
7176 e_info(probe
, "IOV is enabled with %d VFs\n", adapter
->num_vfs
);
7177 for (i
= 0; i
< adapter
->num_vfs
; i
++)
7178 ixgbe_vf_configuration(pdev
, (i
| 0x10000000));
7181 /* add san mac addr to netdev */
7182 ixgbe_add_sanmac_netdev(netdev
);
7184 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7189 ixgbe_release_hw_control(adapter
);
7190 ixgbe_clear_interrupt_scheme(adapter
);
7193 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
7194 ixgbe_disable_sriov(adapter
);
7195 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
7196 del_timer_sync(&adapter
->sfp_timer
);
7197 cancel_work_sync(&adapter
->sfp_task
);
7198 cancel_work_sync(&adapter
->multispeed_fiber_task
);
7199 cancel_work_sync(&adapter
->sfp_config_module_task
);
7200 iounmap(hw
->hw_addr
);
7202 free_netdev(netdev
);
7204 pci_release_selected_regions(pdev
,
7205 pci_select_bars(pdev
, IORESOURCE_MEM
));
7208 pci_disable_device(pdev
);
7213 * ixgbe_remove - Device Removal Routine
7214 * @pdev: PCI device information struct
7216 * ixgbe_remove is called by the PCI subsystem to alert the driver
7217 * that it should release a PCI device. The could be caused by a
7218 * Hot-Plug event, or because the driver is going to be removed from
7221 static void __devexit
ixgbe_remove(struct pci_dev
*pdev
)
7223 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7224 struct net_device
*netdev
= adapter
->netdev
;
7226 set_bit(__IXGBE_DOWN
, &adapter
->state
);
7227 /* clear the module not found bit to make sure the worker won't
7230 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
7231 del_timer_sync(&adapter
->watchdog_timer
);
7233 del_timer_sync(&adapter
->sfp_timer
);
7234 cancel_work_sync(&adapter
->watchdog_task
);
7235 cancel_work_sync(&adapter
->sfp_task
);
7236 cancel_work_sync(&adapter
->multispeed_fiber_task
);
7237 cancel_work_sync(&adapter
->sfp_config_module_task
);
7238 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
7239 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
7240 cancel_work_sync(&adapter
->fdir_reinit_task
);
7241 flush_scheduled_work();
7243 #ifdef CONFIG_IXGBE_DCA
7244 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
7245 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
7246 dca_remove_requester(&pdev
->dev
);
7247 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
7252 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
7253 ixgbe_cleanup_fcoe(adapter
);
7255 #endif /* IXGBE_FCOE */
7257 /* remove the added san mac */
7258 ixgbe_del_sanmac_netdev(netdev
);
7260 if (netdev
->reg_state
== NETREG_REGISTERED
)
7261 unregister_netdev(netdev
);
7263 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
7264 ixgbe_disable_sriov(adapter
);
7266 ixgbe_clear_interrupt_scheme(adapter
);
7268 ixgbe_release_hw_control(adapter
);
7270 iounmap(adapter
->hw
.hw_addr
);
7271 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
7274 e_dev_info("complete\n");
7276 free_netdev(netdev
);
7278 pci_disable_pcie_error_reporting(pdev
);
7280 pci_disable_device(pdev
);
7284 * ixgbe_io_error_detected - called when PCI error is detected
7285 * @pdev: Pointer to PCI device
7286 * @state: The current pci connection state
7288 * This function is called after a PCI bus error affecting
7289 * this device has been detected.
7291 static pci_ers_result_t
ixgbe_io_error_detected(struct pci_dev
*pdev
,
7292 pci_channel_state_t state
)
7294 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7295 struct net_device
*netdev
= adapter
->netdev
;
7297 netif_device_detach(netdev
);
7299 if (state
== pci_channel_io_perm_failure
)
7300 return PCI_ERS_RESULT_DISCONNECT
;
7302 if (netif_running(netdev
))
7303 ixgbe_down(adapter
);
7304 pci_disable_device(pdev
);
7306 /* Request a slot reset. */
7307 return PCI_ERS_RESULT_NEED_RESET
;
7311 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7312 * @pdev: Pointer to PCI device
7314 * Restart the card from scratch, as if from a cold-boot.
7316 static pci_ers_result_t
ixgbe_io_slot_reset(struct pci_dev
*pdev
)
7318 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7319 pci_ers_result_t result
;
7322 if (pci_enable_device_mem(pdev
)) {
7323 e_err(probe
, "Cannot re-enable PCI device after reset.\n");
7324 result
= PCI_ERS_RESULT_DISCONNECT
;
7326 pci_set_master(pdev
);
7327 pci_restore_state(pdev
);
7328 pci_save_state(pdev
);
7330 pci_wake_from_d3(pdev
, false);
7332 ixgbe_reset(adapter
);
7333 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
7334 result
= PCI_ERS_RESULT_RECOVERED
;
7337 err
= pci_cleanup_aer_uncorrect_error_status(pdev
);
7339 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7340 "failed 0x%0x\n", err
);
7341 /* non-fatal, continue */
7348 * ixgbe_io_resume - called when traffic can start flowing again.
7349 * @pdev: Pointer to PCI device
7351 * This callback is called when the error recovery driver tells us that
7352 * its OK to resume normal operation.
7354 static void ixgbe_io_resume(struct pci_dev
*pdev
)
7356 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7357 struct net_device
*netdev
= adapter
->netdev
;
7359 if (netif_running(netdev
)) {
7360 if (ixgbe_up(adapter
)) {
7361 e_info(probe
, "ixgbe_up failed after reset\n");
7366 netif_device_attach(netdev
);
7369 static struct pci_error_handlers ixgbe_err_handler
= {
7370 .error_detected
= ixgbe_io_error_detected
,
7371 .slot_reset
= ixgbe_io_slot_reset
,
7372 .resume
= ixgbe_io_resume
,
7375 static struct pci_driver ixgbe_driver
= {
7376 .name
= ixgbe_driver_name
,
7377 .id_table
= ixgbe_pci_tbl
,
7378 .probe
= ixgbe_probe
,
7379 .remove
= __devexit_p(ixgbe_remove
),
7381 .suspend
= ixgbe_suspend
,
7382 .resume
= ixgbe_resume
,
7384 .shutdown
= ixgbe_shutdown
,
7385 .err_handler
= &ixgbe_err_handler
7389 * ixgbe_init_module - Driver Registration Routine
7391 * ixgbe_init_module is the first routine called when the driver is
7392 * loaded. All it does is register with the PCI subsystem.
7394 static int __init
ixgbe_init_module(void)
7397 pr_info("%s - version %s\n", ixgbe_driver_string
, ixgbe_driver_version
);
7398 pr_info("%s\n", ixgbe_copyright
);
7400 #ifdef CONFIG_IXGBE_DCA
7401 dca_register_notify(&dca_notifier
);
7404 ret
= pci_register_driver(&ixgbe_driver
);
7408 module_init(ixgbe_init_module
);
7411 * ixgbe_exit_module - Driver Exit Cleanup Routine
7413 * ixgbe_exit_module is called just before the driver is removed
7416 static void __exit
ixgbe_exit_module(void)
7418 #ifdef CONFIG_IXGBE_DCA
7419 dca_unregister_notify(&dca_notifier
);
7421 pci_unregister_driver(&ixgbe_driver
);
7422 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7425 #ifdef CONFIG_IXGBE_DCA
7426 static int ixgbe_notify_dca(struct notifier_block
*nb
, unsigned long event
,
7431 ret_val
= driver_for_each_device(&ixgbe_driver
.driver
, NULL
, &event
,
7432 __ixgbe_notify_dca
);
7434 return ret_val
? NOTIFY_BAD
: NOTIFY_DONE
;
7437 #endif /* CONFIG_IXGBE_DCA */
7440 * ixgbe_get_hw_dev return device
7441 * used by hardware layer to print debugging information
7443 struct net_device
*ixgbe_get_hw_dev(struct ixgbe_hw
*hw
)
7445 struct ixgbe_adapter
*adapter
= hw
->back
;
7446 return adapter
->netdev
;
7449 module_exit(ixgbe_exit_module
);