1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <net/checksum.h>
40 #include <net/ip6_checksum.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <scsi/fc/fc_fcoe.h>
46 #include "ixgbe_common.h"
47 #include "ixgbe_dcb_82599.h"
48 #include "ixgbe_sriov.h"
50 char ixgbe_driver_name
[] = "ixgbe";
51 static const char ixgbe_driver_string
[] =
52 "Intel(R) 10 Gigabit PCI Express Network Driver";
54 #define DRV_VERSION "2.0.44-k2"
55 const char ixgbe_driver_version
[] = DRV_VERSION
;
56 static char ixgbe_copyright
[] = "Copyright (c) 1999-2010 Intel Corporation.";
58 static const struct ixgbe_info
*ixgbe_info_tbl
[] = {
59 [board_82598
] = &ixgbe_82598_info
,
60 [board_82599
] = &ixgbe_82599_info
,
63 /* ixgbe_pci_tbl - PCI Device ID Table
65 * Wildcard entries (PCI_ANY_ID) should come last
66 * Last entry must be all 0s
68 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
69 * Class, Class Mask, private data (not used) }
71 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl
) = {
72 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598
),
74 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_DUAL_PORT
),
76 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_SINGLE_PORT
),
78 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT
),
80 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT2
),
82 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_CX4
),
84 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_CX4_DUAL_PORT
),
86 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_DA_DUAL_PORT
),
88 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM
),
90 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_XF_LR
),
92 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_SFP_LOM
),
94 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_BX
),
96 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4
),
98 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_XAUI_LOM
),
100 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KR
),
102 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP
),
104 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP_EM
),
106 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4_MEZZ
),
108 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_CX4
),
110 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_COMBO_BACKPLANE
),
113 /* required last entry */
116 MODULE_DEVICE_TABLE(pci
, ixgbe_pci_tbl
);
118 #ifdef CONFIG_IXGBE_DCA
119 static int ixgbe_notify_dca(struct notifier_block
*, unsigned long event
,
121 static struct notifier_block dca_notifier
= {
122 .notifier_call
= ixgbe_notify_dca
,
128 #ifdef CONFIG_PCI_IOV
129 static unsigned int max_vfs
;
130 module_param(max_vfs
, uint
, 0);
131 MODULE_PARM_DESC(max_vfs
, "Maximum number of virtual functions to allocate "
132 "per physical function");
133 #endif /* CONFIG_PCI_IOV */
135 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
136 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
137 MODULE_LICENSE("GPL");
138 MODULE_VERSION(DRV_VERSION
);
140 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
142 static inline void ixgbe_disable_sriov(struct ixgbe_adapter
*adapter
)
144 struct ixgbe_hw
*hw
= &adapter
->hw
;
149 #ifdef CONFIG_PCI_IOV
150 /* disable iov and allow time for transactions to clear */
151 pci_disable_sriov(adapter
->pdev
);
154 /* turn off device IOV mode */
155 gcr
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
156 gcr
&= ~(IXGBE_GCR_EXT_SRIOV
);
157 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, gcr
);
158 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
159 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
160 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
162 /* set default pool back to 0 */
163 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
164 vmdctl
&= ~IXGBE_VT_CTL_POOL_MASK
;
165 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
);
167 /* take a breather then clean up driver data */
170 kfree(adapter
->vfinfo
);
171 adapter
->vfinfo
= NULL
;
173 adapter
->num_vfs
= 0;
174 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
177 static void ixgbe_release_hw_control(struct ixgbe_adapter
*adapter
)
181 /* Let firmware take over control of h/w */
182 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
183 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
184 ctrl_ext
& ~IXGBE_CTRL_EXT_DRV_LOAD
);
187 static void ixgbe_get_hw_control(struct ixgbe_adapter
*adapter
)
191 /* Let firmware know the driver has taken over */
192 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
193 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
194 ctrl_ext
| IXGBE_CTRL_EXT_DRV_LOAD
);
198 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
199 * @adapter: pointer to adapter struct
200 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
201 * @queue: queue to map the corresponding interrupt to
202 * @msix_vector: the vector to map to the corresponding queue
205 static void ixgbe_set_ivar(struct ixgbe_adapter
*adapter
, s8 direction
,
206 u8 queue
, u8 msix_vector
)
209 struct ixgbe_hw
*hw
= &adapter
->hw
;
210 switch (hw
->mac
.type
) {
211 case ixgbe_mac_82598EB
:
212 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
215 index
= (((direction
* 64) + queue
) >> 2) & 0x1F;
216 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(index
));
217 ivar
&= ~(0xFF << (8 * (queue
& 0x3)));
218 ivar
|= (msix_vector
<< (8 * (queue
& 0x3)));
219 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(index
), ivar
);
221 case ixgbe_mac_82599EB
:
222 if (direction
== -1) {
224 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
225 index
= ((queue
& 1) * 8);
226 ivar
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_IVAR_MISC
);
227 ivar
&= ~(0xFF << index
);
228 ivar
|= (msix_vector
<< index
);
229 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_IVAR_MISC
, ivar
);
232 /* tx or rx causes */
233 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
234 index
= ((16 * (queue
& 1)) + (8 * direction
));
235 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(queue
>> 1));
236 ivar
&= ~(0xFF << index
);
237 ivar
|= (msix_vector
<< index
);
238 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(queue
>> 1), ivar
);
246 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter
*adapter
,
251 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
252 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
253 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS
, mask
);
255 mask
= (qmask
& 0xFFFFFFFF);
256 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(0), mask
);
257 mask
= (qmask
>> 32);
258 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(1), mask
);
262 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter
*adapter
,
263 struct ixgbe_tx_buffer
266 if (tx_buffer_info
->dma
) {
267 if (tx_buffer_info
->mapped_as_page
)
268 pci_unmap_page(adapter
->pdev
,
270 tx_buffer_info
->length
,
273 pci_unmap_single(adapter
->pdev
,
275 tx_buffer_info
->length
,
277 tx_buffer_info
->dma
= 0;
279 if (tx_buffer_info
->skb
) {
280 dev_kfree_skb_any(tx_buffer_info
->skb
);
281 tx_buffer_info
->skb
= NULL
;
283 tx_buffer_info
->time_stamp
= 0;
284 /* tx_buffer_info must be completely set up in the transmit path */
288 * ixgbe_tx_is_paused - check if the tx ring is paused
289 * @adapter: the ixgbe adapter
290 * @tx_ring: the corresponding tx_ring
292 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
293 * corresponding TC of this tx_ring when checking TFCS.
295 * Returns : true if paused
297 static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter
*adapter
,
298 struct ixgbe_ring
*tx_ring
)
300 u32 txoff
= IXGBE_TFCS_TXOFF
;
302 #ifdef CONFIG_IXGBE_DCB
303 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
305 int reg_idx
= tx_ring
->reg_idx
;
306 int dcb_i
= adapter
->ring_feature
[RING_F_DCB
].indices
;
308 switch (adapter
->hw
.mac
.type
) {
309 case ixgbe_mac_82598EB
:
311 txoff
= IXGBE_TFCS_TXOFF0
;
313 case ixgbe_mac_82599EB
:
315 txoff
= IXGBE_TFCS_TXOFF
;
319 if (tc
== 2) /* TC2, TC3 */
320 tc
+= (reg_idx
- 64) >> 4;
321 else if (tc
== 3) /* TC4, TC5, TC6, TC7 */
322 tc
+= 1 + ((reg_idx
- 96) >> 3);
323 } else if (dcb_i
== 4) {
327 tc
+= (reg_idx
- 64) >> 5;
328 if (tc
== 2) /* TC2, TC3 */
329 tc
+= (reg_idx
- 96) >> 4;
339 return IXGBE_READ_REG(&adapter
->hw
, IXGBE_TFCS
) & txoff
;
342 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter
*adapter
,
343 struct ixgbe_ring
*tx_ring
,
346 struct ixgbe_hw
*hw
= &adapter
->hw
;
348 /* Detect a transmit hang in hardware, this serializes the
349 * check with the clearing of time_stamp and movement of eop */
350 adapter
->detect_tx_hung
= false;
351 if (tx_ring
->tx_buffer_info
[eop
].time_stamp
&&
352 time_after(jiffies
, tx_ring
->tx_buffer_info
[eop
].time_stamp
+ HZ
) &&
353 !ixgbe_tx_is_paused(adapter
, tx_ring
)) {
354 /* detected Tx unit hang */
355 union ixgbe_adv_tx_desc
*tx_desc
;
356 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, eop
);
357 DPRINTK(DRV
, ERR
, "Detected Tx Unit Hang\n"
359 " TDH, TDT <%x>, <%x>\n"
360 " next_to_use <%x>\n"
361 " next_to_clean <%x>\n"
362 "tx_buffer_info[next_to_clean]\n"
363 " time_stamp <%lx>\n"
365 tx_ring
->queue_index
,
366 IXGBE_READ_REG(hw
, tx_ring
->head
),
367 IXGBE_READ_REG(hw
, tx_ring
->tail
),
368 tx_ring
->next_to_use
, eop
,
369 tx_ring
->tx_buffer_info
[eop
].time_stamp
, jiffies
);
376 #define IXGBE_MAX_TXD_PWR 14
377 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
379 /* Tx Descriptors needed, worst case */
380 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
381 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
382 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
383 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
385 static void ixgbe_tx_timeout(struct net_device
*netdev
);
388 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
389 * @q_vector: structure containing interrupt and ring information
390 * @tx_ring: tx ring to clean
392 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector
*q_vector
,
393 struct ixgbe_ring
*tx_ring
)
395 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
396 struct net_device
*netdev
= adapter
->netdev
;
397 union ixgbe_adv_tx_desc
*tx_desc
, *eop_desc
;
398 struct ixgbe_tx_buffer
*tx_buffer_info
;
399 unsigned int i
, eop
, count
= 0;
400 unsigned int total_bytes
= 0, total_packets
= 0;
402 i
= tx_ring
->next_to_clean
;
403 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
404 eop_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, eop
);
406 while ((eop_desc
->wb
.status
& cpu_to_le32(IXGBE_TXD_STAT_DD
)) &&
407 (count
< tx_ring
->work_limit
)) {
408 bool cleaned
= false;
409 for ( ; !cleaned
; count
++) {
411 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, i
);
412 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
413 cleaned
= (i
== eop
);
414 skb
= tx_buffer_info
->skb
;
416 if (cleaned
&& skb
) {
417 unsigned int segs
, bytecount
;
418 unsigned int hlen
= skb_headlen(skb
);
420 /* gso_segs is currently only valid for tcp */
421 segs
= skb_shinfo(skb
)->gso_segs
?: 1;
423 /* adjust for FCoE Sequence Offload */
424 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
425 && (skb
->protocol
== htons(ETH_P_FCOE
)) &&
427 hlen
= skb_transport_offset(skb
) +
428 sizeof(struct fc_frame_header
) +
429 sizeof(struct fcoe_crc_eof
);
430 segs
= DIV_ROUND_UP(skb
->len
- hlen
,
431 skb_shinfo(skb
)->gso_size
);
433 #endif /* IXGBE_FCOE */
434 /* multiply data chunks by size of headers */
435 bytecount
= ((segs
- 1) * hlen
) + skb
->len
;
436 total_packets
+= segs
;
437 total_bytes
+= bytecount
;
440 ixgbe_unmap_and_free_tx_resource(adapter
,
443 tx_desc
->wb
.status
= 0;
446 if (i
== tx_ring
->count
)
450 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
451 eop_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, eop
);
454 tx_ring
->next_to_clean
= i
;
456 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
457 if (unlikely(count
&& netif_carrier_ok(netdev
) &&
458 (IXGBE_DESC_UNUSED(tx_ring
) >= TX_WAKE_THRESHOLD
))) {
459 /* Make sure that anybody stopping the queue after this
460 * sees the new next_to_clean.
463 if (__netif_subqueue_stopped(netdev
, tx_ring
->queue_index
) &&
464 !test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
465 netif_wake_subqueue(netdev
, tx_ring
->queue_index
);
466 ++tx_ring
->restart_queue
;
470 if (adapter
->detect_tx_hung
) {
471 if (ixgbe_check_tx_hang(adapter
, tx_ring
, i
)) {
472 /* schedule immediate reset if we believe we hung */
474 "tx hang %d detected, resetting adapter\n",
475 adapter
->tx_timeout_count
+ 1);
476 ixgbe_tx_timeout(adapter
->netdev
);
480 /* re-arm the interrupt */
481 if (count
>= tx_ring
->work_limit
)
482 ixgbe_irq_rearm_queues(adapter
, ((u64
)1 << q_vector
->v_idx
));
484 tx_ring
->total_bytes
+= total_bytes
;
485 tx_ring
->total_packets
+= total_packets
;
486 tx_ring
->stats
.packets
+= total_packets
;
487 tx_ring
->stats
.bytes
+= total_bytes
;
488 return (count
< tx_ring
->work_limit
);
491 #ifdef CONFIG_IXGBE_DCA
492 static void ixgbe_update_rx_dca(struct ixgbe_adapter
*adapter
,
493 struct ixgbe_ring
*rx_ring
)
497 int q
= rx_ring
- adapter
->rx_ring
;
499 if (rx_ring
->cpu
!= cpu
) {
500 rxctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_DCA_RXCTRL(q
));
501 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
502 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK
;
503 rxctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
504 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
505 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599
;
506 rxctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
507 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599
);
509 rxctrl
|= IXGBE_DCA_RXCTRL_DESC_DCA_EN
;
510 rxctrl
|= IXGBE_DCA_RXCTRL_HEAD_DCA_EN
;
511 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN
);
512 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN
|
513 IXGBE_DCA_RXCTRL_DESC_HSRO_EN
);
514 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_RXCTRL(q
), rxctrl
);
520 static void ixgbe_update_tx_dca(struct ixgbe_adapter
*adapter
,
521 struct ixgbe_ring
*tx_ring
)
525 int q
= tx_ring
- adapter
->tx_ring
;
526 struct ixgbe_hw
*hw
= &adapter
->hw
;
528 if (tx_ring
->cpu
!= cpu
) {
529 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
530 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL(q
));
531 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK
;
532 txctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
533 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
534 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL(q
), txctrl
);
535 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
536 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL_82599(q
));
537 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599
;
538 txctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
539 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599
);
540 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
541 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL_82599(q
), txctrl
);
548 static void ixgbe_setup_dca(struct ixgbe_adapter
*adapter
)
552 if (!(adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
))
555 /* always use CB2 mode, difference is masked in the CB driver */
556 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 2);
558 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
559 adapter
->tx_ring
[i
].cpu
= -1;
560 ixgbe_update_tx_dca(adapter
, &adapter
->tx_ring
[i
]);
562 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
563 adapter
->rx_ring
[i
].cpu
= -1;
564 ixgbe_update_rx_dca(adapter
, &adapter
->rx_ring
[i
]);
568 static int __ixgbe_notify_dca(struct device
*dev
, void *data
)
570 struct net_device
*netdev
= dev_get_drvdata(dev
);
571 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
572 unsigned long event
= *(unsigned long *)data
;
575 case DCA_PROVIDER_ADD
:
576 /* if we're already enabled, don't do it again */
577 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
579 if (dca_add_requester(dev
) == 0) {
580 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
581 ixgbe_setup_dca(adapter
);
584 /* Fall Through since DCA is disabled. */
585 case DCA_PROVIDER_REMOVE
:
586 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
587 dca_remove_requester(dev
);
588 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
589 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
597 #endif /* CONFIG_IXGBE_DCA */
599 * ixgbe_receive_skb - Send a completed packet up the stack
600 * @adapter: board private structure
601 * @skb: packet to send up
602 * @status: hardware indication of status of receive
603 * @rx_ring: rx descriptor ring (for a specific queue) to setup
604 * @rx_desc: rx descriptor
606 static void ixgbe_receive_skb(struct ixgbe_q_vector
*q_vector
,
607 struct sk_buff
*skb
, u8 status
,
608 struct ixgbe_ring
*ring
,
609 union ixgbe_adv_rx_desc
*rx_desc
)
611 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
612 struct napi_struct
*napi
= &q_vector
->napi
;
613 bool is_vlan
= (status
& IXGBE_RXD_STAT_VP
);
614 u16 tag
= le16_to_cpu(rx_desc
->wb
.upper
.vlan
);
616 skb_record_rx_queue(skb
, ring
->queue_index
);
617 if (!(adapter
->flags
& IXGBE_FLAG_IN_NETPOLL
)) {
618 if (adapter
->vlgrp
&& is_vlan
&& (tag
& VLAN_VID_MASK
))
619 vlan_gro_receive(napi
, adapter
->vlgrp
, tag
, skb
);
621 napi_gro_receive(napi
, skb
);
623 if (adapter
->vlgrp
&& is_vlan
&& (tag
& VLAN_VID_MASK
))
624 vlan_hwaccel_rx(skb
, adapter
->vlgrp
, tag
);
631 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
632 * @adapter: address of board private structure
633 * @status_err: hardware indication of status of receive
634 * @skb: skb currently being received and modified
636 static inline void ixgbe_rx_checksum(struct ixgbe_adapter
*adapter
,
637 union ixgbe_adv_rx_desc
*rx_desc
,
640 u32 status_err
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
642 skb
->ip_summed
= CHECKSUM_NONE
;
644 /* Rx csum disabled */
645 if (!(adapter
->flags
& IXGBE_FLAG_RX_CSUM_ENABLED
))
648 /* if IP and error */
649 if ((status_err
& IXGBE_RXD_STAT_IPCS
) &&
650 (status_err
& IXGBE_RXDADV_ERR_IPE
)) {
651 adapter
->hw_csum_rx_error
++;
655 if (!(status_err
& IXGBE_RXD_STAT_L4CS
))
658 if (status_err
& IXGBE_RXDADV_ERR_TCPE
) {
659 u16 pkt_info
= rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
662 * 82599 errata, UDP frames with a 0 checksum can be marked as
665 if ((pkt_info
& IXGBE_RXDADV_PKTTYPE_UDP
) &&
666 (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
))
669 adapter
->hw_csum_rx_error
++;
673 /* It must be a TCP or UDP packet with a valid checksum */
674 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
677 static inline void ixgbe_release_rx_desc(struct ixgbe_hw
*hw
,
678 struct ixgbe_ring
*rx_ring
, u32 val
)
681 * Force memory writes to complete before letting h/w
682 * know there are new descriptors to fetch. (Only
683 * applicable for weak-ordered memory model archs,
687 IXGBE_WRITE_REG(hw
, IXGBE_RDT(rx_ring
->reg_idx
), val
);
691 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
692 * @adapter: address of board private structure
694 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter
*adapter
,
695 struct ixgbe_ring
*rx_ring
,
698 struct pci_dev
*pdev
= adapter
->pdev
;
699 union ixgbe_adv_rx_desc
*rx_desc
;
700 struct ixgbe_rx_buffer
*bi
;
703 i
= rx_ring
->next_to_use
;
704 bi
= &rx_ring
->rx_buffer_info
[i
];
706 while (cleaned_count
--) {
707 rx_desc
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
710 (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
)) {
712 bi
->page
= alloc_page(GFP_ATOMIC
);
714 adapter
->alloc_rx_page_failed
++;
719 /* use a half page if we're re-using */
720 bi
->page_offset
^= (PAGE_SIZE
/ 2);
723 bi
->page_dma
= pci_map_page(pdev
, bi
->page
,
731 /* netdev_alloc_skb reserves 32 bytes up front!! */
732 uint bufsz
= rx_ring
->rx_buf_len
+ SMP_CACHE_BYTES
;
733 skb
= netdev_alloc_skb(adapter
->netdev
, bufsz
);
736 adapter
->alloc_rx_buff_failed
++;
740 /* advance the data pointer to the next cache line */
741 skb_reserve(skb
, (PTR_ALIGN(skb
->data
, SMP_CACHE_BYTES
)
745 bi
->dma
= pci_map_single(pdev
, skb
->data
,
749 /* Refresh the desc even if buffer_addrs didn't change because
750 * each write-back erases this info. */
751 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
752 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->page_dma
);
753 rx_desc
->read
.hdr_addr
= cpu_to_le64(bi
->dma
);
755 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->dma
);
759 if (i
== rx_ring
->count
)
761 bi
= &rx_ring
->rx_buffer_info
[i
];
765 if (rx_ring
->next_to_use
!= i
) {
766 rx_ring
->next_to_use
= i
;
768 i
= (rx_ring
->count
- 1);
770 ixgbe_release_rx_desc(&adapter
->hw
, rx_ring
, i
);
774 static inline u16
ixgbe_get_hdr_info(union ixgbe_adv_rx_desc
*rx_desc
)
776 return rx_desc
->wb
.lower
.lo_dword
.hs_rss
.hdr_info
;
779 static inline u16
ixgbe_get_pkt_info(union ixgbe_adv_rx_desc
*rx_desc
)
781 return rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
784 static inline u32
ixgbe_get_rsc_count(union ixgbe_adv_rx_desc
*rx_desc
)
786 return (le32_to_cpu(rx_desc
->wb
.lower
.lo_dword
.data
) &
787 IXGBE_RXDADV_RSCCNT_MASK
) >>
788 IXGBE_RXDADV_RSCCNT_SHIFT
;
792 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
793 * @skb: pointer to the last skb in the rsc queue
794 * @count: pointer to number of packets coalesced in this context
796 * This function changes a queue full of hw rsc buffers into a completed
797 * packet. It uses the ->prev pointers to find the first packet and then
798 * turns it into the frag list owner.
800 static inline struct sk_buff
*ixgbe_transform_rsc_queue(struct sk_buff
*skb
,
803 unsigned int frag_list_size
= 0;
806 struct sk_buff
*prev
= skb
->prev
;
807 frag_list_size
+= skb
->len
;
813 skb_shinfo(skb
)->frag_list
= skb
->next
;
815 skb
->len
+= frag_list_size
;
816 skb
->data_len
+= frag_list_size
;
817 skb
->truesize
+= frag_list_size
;
821 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector
*q_vector
,
822 struct ixgbe_ring
*rx_ring
,
823 int *work_done
, int work_to_do
)
825 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
826 struct net_device
*netdev
= adapter
->netdev
;
827 struct pci_dev
*pdev
= adapter
->pdev
;
828 union ixgbe_adv_rx_desc
*rx_desc
, *next_rxd
;
829 struct ixgbe_rx_buffer
*rx_buffer_info
, *next_buffer
;
831 unsigned int i
, rsc_count
= 0;
834 bool cleaned
= false;
835 int cleaned_count
= 0;
836 unsigned int total_rx_bytes
= 0, total_rx_packets
= 0;
839 #endif /* IXGBE_FCOE */
841 i
= rx_ring
->next_to_clean
;
842 rx_desc
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
843 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
844 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
846 while (staterr
& IXGBE_RXD_STAT_DD
) {
848 if (*work_done
>= work_to_do
)
852 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
853 hdr_info
= le16_to_cpu(ixgbe_get_hdr_info(rx_desc
));
854 len
= (hdr_info
& IXGBE_RXDADV_HDRBUFLEN_MASK
) >>
855 IXGBE_RXDADV_HDRBUFLEN_SHIFT
;
856 if (len
> IXGBE_RX_HDR_SIZE
)
857 len
= IXGBE_RX_HDR_SIZE
;
858 upper_len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
860 len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
864 skb
= rx_buffer_info
->skb
;
866 rx_buffer_info
->skb
= NULL
;
868 if (rx_buffer_info
->dma
) {
869 pci_unmap_single(pdev
, rx_buffer_info
->dma
,
872 rx_buffer_info
->dma
= 0;
877 pci_unmap_page(pdev
, rx_buffer_info
->page_dma
,
878 PAGE_SIZE
/ 2, PCI_DMA_FROMDEVICE
);
879 rx_buffer_info
->page_dma
= 0;
880 skb_fill_page_desc(skb
, skb_shinfo(skb
)->nr_frags
,
881 rx_buffer_info
->page
,
882 rx_buffer_info
->page_offset
,
885 if ((rx_ring
->rx_buf_len
> (PAGE_SIZE
/ 2)) ||
886 (page_count(rx_buffer_info
->page
) != 1))
887 rx_buffer_info
->page
= NULL
;
889 get_page(rx_buffer_info
->page
);
891 skb
->len
+= upper_len
;
892 skb
->data_len
+= upper_len
;
893 skb
->truesize
+= upper_len
;
897 if (i
== rx_ring
->count
)
900 next_rxd
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
904 if (adapter
->flags2
& IXGBE_FLAG2_RSC_CAPABLE
)
905 rsc_count
= ixgbe_get_rsc_count(rx_desc
);
908 u32 nextp
= (staterr
& IXGBE_RXDADV_NEXTP_MASK
) >>
909 IXGBE_RXDADV_NEXTP_SHIFT
;
910 next_buffer
= &rx_ring
->rx_buffer_info
[nextp
];
912 next_buffer
= &rx_ring
->rx_buffer_info
[i
];
915 if (staterr
& IXGBE_RXD_STAT_EOP
) {
917 skb
= ixgbe_transform_rsc_queue(skb
, &(rx_ring
->rsc_count
));
918 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
919 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
)
920 rx_ring
->rsc_count
+= skb_shinfo(skb
)->nr_frags
;
922 rx_ring
->rsc_count
++;
923 rx_ring
->rsc_flush
++;
925 rx_ring
->stats
.packets
++;
926 rx_ring
->stats
.bytes
+= skb
->len
;
928 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
929 rx_buffer_info
->skb
= next_buffer
->skb
;
930 rx_buffer_info
->dma
= next_buffer
->dma
;
931 next_buffer
->skb
= skb
;
932 next_buffer
->dma
= 0;
934 skb
->next
= next_buffer
->skb
;
935 skb
->next
->prev
= skb
;
937 rx_ring
->non_eop_descs
++;
941 if (staterr
& IXGBE_RXDADV_ERR_FRAME_ERR_MASK
) {
942 dev_kfree_skb_irq(skb
);
946 ixgbe_rx_checksum(adapter
, rx_desc
, skb
);
948 /* probably a little skewed due to removing CRC */
949 total_rx_bytes
+= skb
->len
;
952 skb
->protocol
= eth_type_trans(skb
, adapter
->netdev
);
954 /* if ddp, not passing to ULD unless for FCP_RSP or error */
955 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
956 ddp_bytes
= ixgbe_fcoe_ddp(adapter
, rx_desc
, skb
);
960 #endif /* IXGBE_FCOE */
961 ixgbe_receive_skb(q_vector
, skb
, staterr
, rx_ring
, rx_desc
);
964 rx_desc
->wb
.upper
.status_error
= 0;
966 /* return some buffers to hardware, one at a time is too slow */
967 if (cleaned_count
>= IXGBE_RX_BUFFER_WRITE
) {
968 ixgbe_alloc_rx_buffers(adapter
, rx_ring
, cleaned_count
);
972 /* use prefetched values */
974 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
976 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
979 rx_ring
->next_to_clean
= i
;
980 cleaned_count
= IXGBE_DESC_UNUSED(rx_ring
);
983 ixgbe_alloc_rx_buffers(adapter
, rx_ring
, cleaned_count
);
986 /* include DDPed FCoE data */
990 mss
= adapter
->netdev
->mtu
- sizeof(struct fcoe_hdr
) -
991 sizeof(struct fc_frame_header
) -
992 sizeof(struct fcoe_crc_eof
);
995 total_rx_bytes
+= ddp_bytes
;
996 total_rx_packets
+= DIV_ROUND_UP(ddp_bytes
, mss
);
998 #endif /* IXGBE_FCOE */
1000 rx_ring
->total_packets
+= total_rx_packets
;
1001 rx_ring
->total_bytes
+= total_rx_bytes
;
1002 netdev
->stats
.rx_bytes
+= total_rx_bytes
;
1003 netdev
->stats
.rx_packets
+= total_rx_packets
;
1008 static int ixgbe_clean_rxonly(struct napi_struct
*, int);
1010 * ixgbe_configure_msix - Configure MSI-X hardware
1011 * @adapter: board private structure
1013 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1016 static void ixgbe_configure_msix(struct ixgbe_adapter
*adapter
)
1018 struct ixgbe_q_vector
*q_vector
;
1019 int i
, j
, q_vectors
, v_idx
, r_idx
;
1022 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1025 * Populate the IVAR table and set the ITR values to the
1026 * corresponding register.
1028 for (v_idx
= 0; v_idx
< q_vectors
; v_idx
++) {
1029 q_vector
= adapter
->q_vector
[v_idx
];
1030 /* XXX for_each_bit(...) */
1031 r_idx
= find_first_bit(q_vector
->rxr_idx
,
1032 adapter
->num_rx_queues
);
1034 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1035 j
= adapter
->rx_ring
[r_idx
].reg_idx
;
1036 ixgbe_set_ivar(adapter
, 0, j
, v_idx
);
1037 r_idx
= find_next_bit(q_vector
->rxr_idx
,
1038 adapter
->num_rx_queues
,
1041 r_idx
= find_first_bit(q_vector
->txr_idx
,
1042 adapter
->num_tx_queues
);
1044 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1045 j
= adapter
->tx_ring
[r_idx
].reg_idx
;
1046 ixgbe_set_ivar(adapter
, 1, j
, v_idx
);
1047 r_idx
= find_next_bit(q_vector
->txr_idx
,
1048 adapter
->num_tx_queues
,
1052 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
1054 q_vector
->eitr
= adapter
->tx_eitr_param
;
1055 else if (q_vector
->rxr_count
)
1057 q_vector
->eitr
= adapter
->rx_eitr_param
;
1059 ixgbe_write_eitr(q_vector
);
1062 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
1063 ixgbe_set_ivar(adapter
, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX
,
1065 else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
1066 ixgbe_set_ivar(adapter
, -1, 1, v_idx
);
1067 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITR(v_idx
), 1950);
1069 /* set up to autoclear timer, and the vectors */
1070 mask
= IXGBE_EIMS_ENABLE_MASK
;
1071 if (adapter
->num_vfs
)
1072 mask
&= ~(IXGBE_EIMS_OTHER
|
1073 IXGBE_EIMS_MAILBOX
|
1076 mask
&= ~(IXGBE_EIMS_OTHER
| IXGBE_EIMS_LSC
);
1077 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIAC
, mask
);
1080 enum latency_range
{
1084 latency_invalid
= 255
1088 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1089 * @adapter: pointer to adapter
1090 * @eitr: eitr setting (ints per sec) to give last timeslice
1091 * @itr_setting: current throttle rate in ints/second
1092 * @packets: the number of packets during this measurement interval
1093 * @bytes: the number of bytes during this measurement interval
1095 * Stores a new ITR value based on packets and byte
1096 * counts during the last interrupt. The advantage of per interrupt
1097 * computation is faster updates and more accurate ITR for the current
1098 * traffic pattern. Constants in this function were computed
1099 * based on theoretical maximum wire speed and thresholds were set based
1100 * on testing data as well as attempting to minimize response time
1101 * while increasing bulk throughput.
1102 * this functionality is controlled by the InterruptThrottleRate module
1103 * parameter (see ixgbe_param.c)
1105 static u8
ixgbe_update_itr(struct ixgbe_adapter
*adapter
,
1106 u32 eitr
, u8 itr_setting
,
1107 int packets
, int bytes
)
1109 unsigned int retval
= itr_setting
;
1114 goto update_itr_done
;
1117 /* simple throttlerate management
1118 * 0-20MB/s lowest (100000 ints/s)
1119 * 20-100MB/s low (20000 ints/s)
1120 * 100-1249MB/s bulk (8000 ints/s)
1122 /* what was last interrupt timeslice? */
1123 timepassed_us
= 1000000/eitr
;
1124 bytes_perint
= bytes
/ timepassed_us
; /* bytes/usec */
1126 switch (itr_setting
) {
1127 case lowest_latency
:
1128 if (bytes_perint
> adapter
->eitr_low
)
1129 retval
= low_latency
;
1132 if (bytes_perint
> adapter
->eitr_high
)
1133 retval
= bulk_latency
;
1134 else if (bytes_perint
<= adapter
->eitr_low
)
1135 retval
= lowest_latency
;
1138 if (bytes_perint
<= adapter
->eitr_high
)
1139 retval
= low_latency
;
1148 * ixgbe_write_eitr - write EITR register in hardware specific way
1149 * @q_vector: structure containing interrupt and ring information
1151 * This function is made to be called by ethtool and by the driver
1152 * when it needs to update EITR registers at runtime. Hardware
1153 * specific quirks/differences are taken care of here.
1155 void ixgbe_write_eitr(struct ixgbe_q_vector
*q_vector
)
1157 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1158 struct ixgbe_hw
*hw
= &adapter
->hw
;
1159 int v_idx
= q_vector
->v_idx
;
1160 u32 itr_reg
= EITR_INTS_PER_SEC_TO_REG(q_vector
->eitr
);
1162 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1163 /* must write high and low 16 bits to reset counter */
1164 itr_reg
|= (itr_reg
<< 16);
1165 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
1167 * set the WDIS bit to not clear the timer bits and cause an
1168 * immediate assertion of the interrupt
1170 itr_reg
|= IXGBE_EITR_CNT_WDIS
;
1172 IXGBE_WRITE_REG(hw
, IXGBE_EITR(v_idx
), itr_reg
);
1175 static void ixgbe_set_itr_msix(struct ixgbe_q_vector
*q_vector
)
1177 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1179 u8 current_itr
, ret_itr
;
1181 struct ixgbe_ring
*rx_ring
, *tx_ring
;
1183 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1184 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1185 tx_ring
= &(adapter
->tx_ring
[r_idx
]);
1186 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1188 tx_ring
->total_packets
,
1189 tx_ring
->total_bytes
);
1190 /* if the result for this queue would decrease interrupt
1191 * rate for this vector then use that result */
1192 q_vector
->tx_itr
= ((q_vector
->tx_itr
> ret_itr
) ?
1193 q_vector
->tx_itr
- 1 : ret_itr
);
1194 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1198 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1199 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1200 rx_ring
= &(adapter
->rx_ring
[r_idx
]);
1201 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1203 rx_ring
->total_packets
,
1204 rx_ring
->total_bytes
);
1205 /* if the result for this queue would decrease interrupt
1206 * rate for this vector then use that result */
1207 q_vector
->rx_itr
= ((q_vector
->rx_itr
> ret_itr
) ?
1208 q_vector
->rx_itr
- 1 : ret_itr
);
1209 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1213 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
1215 switch (current_itr
) {
1216 /* counts and packets in update_itr are dependent on these numbers */
1217 case lowest_latency
:
1221 new_itr
= 20000; /* aka hwitr = ~200 */
1229 if (new_itr
!= q_vector
->eitr
) {
1230 /* do an exponential smoothing */
1231 new_itr
= ((q_vector
->eitr
* 90)/100) + ((new_itr
* 10)/100);
1233 /* save the algorithm value here, not the smoothed one */
1234 q_vector
->eitr
= new_itr
;
1236 ixgbe_write_eitr(q_vector
);
1242 static void ixgbe_check_fan_failure(struct ixgbe_adapter
*adapter
, u32 eicr
)
1244 struct ixgbe_hw
*hw
= &adapter
->hw
;
1246 if ((adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) &&
1247 (eicr
& IXGBE_EICR_GPI_SDP1
)) {
1248 DPRINTK(PROBE
, CRIT
, "Fan has stopped, replace the adapter\n");
1249 /* write to clear the interrupt */
1250 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1254 static void ixgbe_check_sfp_event(struct ixgbe_adapter
*adapter
, u32 eicr
)
1256 struct ixgbe_hw
*hw
= &adapter
->hw
;
1258 if (eicr
& IXGBE_EICR_GPI_SDP1
) {
1259 /* Clear the interrupt */
1260 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1261 schedule_work(&adapter
->multispeed_fiber_task
);
1262 } else if (eicr
& IXGBE_EICR_GPI_SDP2
) {
1263 /* Clear the interrupt */
1264 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP2
);
1265 schedule_work(&adapter
->sfp_config_module_task
);
1267 /* Interrupt isn't for us... */
1272 static void ixgbe_check_lsc(struct ixgbe_adapter
*adapter
)
1274 struct ixgbe_hw
*hw
= &adapter
->hw
;
1277 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
1278 adapter
->link_check_timeout
= jiffies
;
1279 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1280 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_EIMC_LSC
);
1281 IXGBE_WRITE_FLUSH(hw
);
1282 schedule_work(&adapter
->watchdog_task
);
1286 static irqreturn_t
ixgbe_msix_lsc(int irq
, void *data
)
1288 struct net_device
*netdev
= data
;
1289 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
1290 struct ixgbe_hw
*hw
= &adapter
->hw
;
1294 * Workaround for Silicon errata. Use clear-by-write instead
1295 * of clear-by-read. Reading with EICS will return the
1296 * interrupt causes without clearing, which later be done
1297 * with the write to EICR.
1299 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICS
);
1300 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, eicr
);
1302 if (eicr
& IXGBE_EICR_LSC
)
1303 ixgbe_check_lsc(adapter
);
1305 if (eicr
& IXGBE_EICR_MAILBOX
)
1306 ixgbe_msg_task(adapter
);
1308 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
1309 ixgbe_check_fan_failure(adapter
, eicr
);
1311 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
1312 ixgbe_check_sfp_event(adapter
, eicr
);
1314 /* Handle Flow Director Full threshold interrupt */
1315 if (eicr
& IXGBE_EICR_FLOW_DIR
) {
1317 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_FLOW_DIR
);
1318 /* Disable transmits before FDIR Re-initialization */
1319 netif_tx_stop_all_queues(netdev
);
1320 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
1321 struct ixgbe_ring
*tx_ring
=
1322 &adapter
->tx_ring
[i
];
1323 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE
,
1324 &tx_ring
->reinit_state
))
1325 schedule_work(&adapter
->fdir_reinit_task
);
1329 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1330 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMS_OTHER
);
1335 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter
*adapter
,
1340 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1341 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1342 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
1344 mask
= (qmask
& 0xFFFFFFFF);
1345 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS_EX(0), mask
);
1346 mask
= (qmask
>> 32);
1347 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS_EX(1), mask
);
1349 /* skip the flush */
1352 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter
*adapter
,
1357 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1358 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1359 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, mask
);
1361 mask
= (qmask
& 0xFFFFFFFF);
1362 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), mask
);
1363 mask
= (qmask
>> 32);
1364 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1), mask
);
1366 /* skip the flush */
1369 static irqreturn_t
ixgbe_msix_clean_tx(int irq
, void *data
)
1371 struct ixgbe_q_vector
*q_vector
= data
;
1372 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1373 struct ixgbe_ring
*tx_ring
;
1376 if (!q_vector
->txr_count
)
1379 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1380 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1381 tx_ring
= &(adapter
->tx_ring
[r_idx
]);
1382 tx_ring
->total_bytes
= 0;
1383 tx_ring
->total_packets
= 0;
1384 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1388 /* EIAM disabled interrupts (on this vector) for us */
1389 napi_schedule(&q_vector
->napi
);
1395 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1397 * @data: pointer to our q_vector struct for this interrupt vector
1399 static irqreturn_t
ixgbe_msix_clean_rx(int irq
, void *data
)
1401 struct ixgbe_q_vector
*q_vector
= data
;
1402 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1403 struct ixgbe_ring
*rx_ring
;
1407 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1408 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1409 rx_ring
= &(adapter
->rx_ring
[r_idx
]);
1410 rx_ring
->total_bytes
= 0;
1411 rx_ring
->total_packets
= 0;
1412 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1416 if (!q_vector
->rxr_count
)
1419 /* disable interrupts on this vector only */
1420 /* EIAM disabled interrupts (on this vector) for us */
1421 napi_schedule(&q_vector
->napi
);
1426 static irqreturn_t
ixgbe_msix_clean_many(int irq
, void *data
)
1428 struct ixgbe_q_vector
*q_vector
= data
;
1429 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1430 struct ixgbe_ring
*ring
;
1434 if (!q_vector
->txr_count
&& !q_vector
->rxr_count
)
1437 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1438 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1439 ring
= &(adapter
->tx_ring
[r_idx
]);
1440 ring
->total_bytes
= 0;
1441 ring
->total_packets
= 0;
1442 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1446 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1447 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1448 ring
= &(adapter
->rx_ring
[r_idx
]);
1449 ring
->total_bytes
= 0;
1450 ring
->total_packets
= 0;
1451 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1455 /* EIAM disabled interrupts (on this vector) for us */
1456 napi_schedule(&q_vector
->napi
);
1462 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1463 * @napi: napi struct with our devices info in it
1464 * @budget: amount of work driver is allowed to do this pass, in packets
1466 * This function is optimized for cleaning one queue only on a single
1469 static int ixgbe_clean_rxonly(struct napi_struct
*napi
, int budget
)
1471 struct ixgbe_q_vector
*q_vector
=
1472 container_of(napi
, struct ixgbe_q_vector
, napi
);
1473 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1474 struct ixgbe_ring
*rx_ring
= NULL
;
1478 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1479 rx_ring
= &(adapter
->rx_ring
[r_idx
]);
1480 #ifdef CONFIG_IXGBE_DCA
1481 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1482 ixgbe_update_rx_dca(adapter
, rx_ring
);
1485 ixgbe_clean_rx_irq(q_vector
, rx_ring
, &work_done
, budget
);
1487 /* If all Rx work done, exit the polling mode */
1488 if (work_done
< budget
) {
1489 napi_complete(napi
);
1490 if (adapter
->rx_itr_setting
& 1)
1491 ixgbe_set_itr_msix(q_vector
);
1492 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1493 ixgbe_irq_enable_queues(adapter
,
1494 ((u64
)1 << q_vector
->v_idx
));
1501 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1502 * @napi: napi struct with our devices info in it
1503 * @budget: amount of work driver is allowed to do this pass, in packets
1505 * This function will clean more than one rx queue associated with a
1508 static int ixgbe_clean_rxtx_many(struct napi_struct
*napi
, int budget
)
1510 struct ixgbe_q_vector
*q_vector
=
1511 container_of(napi
, struct ixgbe_q_vector
, napi
);
1512 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1513 struct ixgbe_ring
*ring
= NULL
;
1514 int work_done
= 0, i
;
1516 bool tx_clean_complete
= true;
1518 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1519 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1520 ring
= &(adapter
->tx_ring
[r_idx
]);
1521 #ifdef CONFIG_IXGBE_DCA
1522 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1523 ixgbe_update_tx_dca(adapter
, ring
);
1525 tx_clean_complete
&= ixgbe_clean_tx_irq(q_vector
, ring
);
1526 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1530 /* attempt to distribute budget to each queue fairly, but don't allow
1531 * the budget to go below 1 because we'll exit polling */
1532 budget
/= (q_vector
->rxr_count
?: 1);
1533 budget
= max(budget
, 1);
1534 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1535 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1536 ring
= &(adapter
->rx_ring
[r_idx
]);
1537 #ifdef CONFIG_IXGBE_DCA
1538 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1539 ixgbe_update_rx_dca(adapter
, ring
);
1541 ixgbe_clean_rx_irq(q_vector
, ring
, &work_done
, budget
);
1542 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1546 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1547 ring
= &(adapter
->rx_ring
[r_idx
]);
1548 /* If all Rx work done, exit the polling mode */
1549 if (work_done
< budget
) {
1550 napi_complete(napi
);
1551 if (adapter
->rx_itr_setting
& 1)
1552 ixgbe_set_itr_msix(q_vector
);
1553 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1554 ixgbe_irq_enable_queues(adapter
,
1555 ((u64
)1 << q_vector
->v_idx
));
1563 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1564 * @napi: napi struct with our devices info in it
1565 * @budget: amount of work driver is allowed to do this pass, in packets
1567 * This function is optimized for cleaning one queue only on a single
1570 static int ixgbe_clean_txonly(struct napi_struct
*napi
, int budget
)
1572 struct ixgbe_q_vector
*q_vector
=
1573 container_of(napi
, struct ixgbe_q_vector
, napi
);
1574 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1575 struct ixgbe_ring
*tx_ring
= NULL
;
1579 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1580 tx_ring
= &(adapter
->tx_ring
[r_idx
]);
1581 #ifdef CONFIG_IXGBE_DCA
1582 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1583 ixgbe_update_tx_dca(adapter
, tx_ring
);
1586 if (!ixgbe_clean_tx_irq(q_vector
, tx_ring
))
1589 /* If all Tx work done, exit the polling mode */
1590 if (work_done
< budget
) {
1591 napi_complete(napi
);
1592 if (adapter
->tx_itr_setting
& 1)
1593 ixgbe_set_itr_msix(q_vector
);
1594 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1595 ixgbe_irq_enable_queues(adapter
, ((u64
)1 << q_vector
->v_idx
));
1601 static inline void map_vector_to_rxq(struct ixgbe_adapter
*a
, int v_idx
,
1604 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
1606 set_bit(r_idx
, q_vector
->rxr_idx
);
1607 q_vector
->rxr_count
++;
1610 static inline void map_vector_to_txq(struct ixgbe_adapter
*a
, int v_idx
,
1613 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
1615 set_bit(t_idx
, q_vector
->txr_idx
);
1616 q_vector
->txr_count
++;
1620 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1621 * @adapter: board private structure to initialize
1622 * @vectors: allotted vector count for descriptor rings
1624 * This function maps descriptor rings to the queue-specific vectors
1625 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1626 * one vector per ring/queue, but on a constrained vector budget, we
1627 * group the rings as "efficiently" as possible. You would add new
1628 * mapping configurations in here.
1630 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter
*adapter
,
1634 int rxr_idx
= 0, txr_idx
= 0;
1635 int rxr_remaining
= adapter
->num_rx_queues
;
1636 int txr_remaining
= adapter
->num_tx_queues
;
1641 /* No mapping required if MSI-X is disabled. */
1642 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
1646 * The ideal configuration...
1647 * We have enough vectors to map one per queue.
1649 if (vectors
== adapter
->num_rx_queues
+ adapter
->num_tx_queues
) {
1650 for (; rxr_idx
< rxr_remaining
; v_start
++, rxr_idx
++)
1651 map_vector_to_rxq(adapter
, v_start
, rxr_idx
);
1653 for (; txr_idx
< txr_remaining
; v_start
++, txr_idx
++)
1654 map_vector_to_txq(adapter
, v_start
, txr_idx
);
1660 * If we don't have enough vectors for a 1-to-1
1661 * mapping, we'll have to group them so there are
1662 * multiple queues per vector.
1664 /* Re-adjusting *qpv takes care of the remainder. */
1665 for (i
= v_start
; i
< vectors
; i
++) {
1666 rqpv
= DIV_ROUND_UP(rxr_remaining
, vectors
- i
);
1667 for (j
= 0; j
< rqpv
; j
++) {
1668 map_vector_to_rxq(adapter
, i
, rxr_idx
);
1673 for (i
= v_start
; i
< vectors
; i
++) {
1674 tqpv
= DIV_ROUND_UP(txr_remaining
, vectors
- i
);
1675 for (j
= 0; j
< tqpv
; j
++) {
1676 map_vector_to_txq(adapter
, i
, txr_idx
);
1687 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1688 * @adapter: board private structure
1690 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1691 * interrupts from the kernel.
1693 static int ixgbe_request_msix_irqs(struct ixgbe_adapter
*adapter
)
1695 struct net_device
*netdev
= adapter
->netdev
;
1696 irqreturn_t (*handler
)(int, void *);
1697 int i
, vector
, q_vectors
, err
;
1700 /* Decrement for Other and TCP Timer vectors */
1701 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1703 /* Map the Tx/Rx rings to the vectors we were allotted. */
1704 err
= ixgbe_map_rings_to_vectors(adapter
, q_vectors
);
1708 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1709 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1710 &ixgbe_msix_clean_many)
1711 for (vector
= 0; vector
< q_vectors
; vector
++) {
1712 handler
= SET_HANDLER(adapter
->q_vector
[vector
]);
1714 if(handler
== &ixgbe_msix_clean_rx
) {
1715 sprintf(adapter
->name
[vector
], "%s-%s-%d",
1716 netdev
->name
, "rx", ri
++);
1718 else if(handler
== &ixgbe_msix_clean_tx
) {
1719 sprintf(adapter
->name
[vector
], "%s-%s-%d",
1720 netdev
->name
, "tx", ti
++);
1723 sprintf(adapter
->name
[vector
], "%s-%s-%d",
1724 netdev
->name
, "TxRx", vector
);
1726 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
1727 handler
, 0, adapter
->name
[vector
],
1728 adapter
->q_vector
[vector
]);
1731 "request_irq failed for MSIX interrupt "
1732 "Error: %d\n", err
);
1733 goto free_queue_irqs
;
1737 sprintf(adapter
->name
[vector
], "%s:lsc", netdev
->name
);
1738 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
1739 ixgbe_msix_lsc
, 0, adapter
->name
[vector
], netdev
);
1742 "request_irq for msix_lsc failed: %d\n", err
);
1743 goto free_queue_irqs
;
1749 for (i
= vector
- 1; i
>= 0; i
--)
1750 free_irq(adapter
->msix_entries
[--vector
].vector
,
1751 adapter
->q_vector
[i
]);
1752 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
1753 pci_disable_msix(adapter
->pdev
);
1754 kfree(adapter
->msix_entries
);
1755 adapter
->msix_entries
= NULL
;
1760 static void ixgbe_set_itr(struct ixgbe_adapter
*adapter
)
1762 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
1764 u32 new_itr
= q_vector
->eitr
;
1765 struct ixgbe_ring
*rx_ring
= &adapter
->rx_ring
[0];
1766 struct ixgbe_ring
*tx_ring
= &adapter
->tx_ring
[0];
1768 q_vector
->tx_itr
= ixgbe_update_itr(adapter
, new_itr
,
1770 tx_ring
->total_packets
,
1771 tx_ring
->total_bytes
);
1772 q_vector
->rx_itr
= ixgbe_update_itr(adapter
, new_itr
,
1774 rx_ring
->total_packets
,
1775 rx_ring
->total_bytes
);
1777 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
1779 switch (current_itr
) {
1780 /* counts and packets in update_itr are dependent on these numbers */
1781 case lowest_latency
:
1785 new_itr
= 20000; /* aka hwitr = ~200 */
1794 if (new_itr
!= q_vector
->eitr
) {
1795 /* do an exponential smoothing */
1796 new_itr
= ((q_vector
->eitr
* 90)/100) + ((new_itr
* 10)/100);
1798 /* save the algorithm value here, not the smoothed one */
1799 q_vector
->eitr
= new_itr
;
1801 ixgbe_write_eitr(q_vector
);
1808 * ixgbe_irq_enable - Enable default interrupt generation settings
1809 * @adapter: board private structure
1811 static inline void ixgbe_irq_enable(struct ixgbe_adapter
*adapter
)
1815 mask
= (IXGBE_EIMS_ENABLE_MASK
& ~IXGBE_EIMS_RTX_QUEUE
);
1816 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
)
1817 mask
|= IXGBE_EIMS_GPI_SDP1
;
1818 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
1819 mask
|= IXGBE_EIMS_ECC
;
1820 mask
|= IXGBE_EIMS_GPI_SDP1
;
1821 mask
|= IXGBE_EIMS_GPI_SDP2
;
1822 if (adapter
->num_vfs
)
1823 mask
|= IXGBE_EIMS_MAILBOX
;
1825 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
1826 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
1827 mask
|= IXGBE_EIMS_FLOW_DIR
;
1829 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
1830 ixgbe_irq_enable_queues(adapter
, ~0);
1831 IXGBE_WRITE_FLUSH(&adapter
->hw
);
1833 if (adapter
->num_vfs
> 32) {
1834 u32 eitrsel
= (1 << (adapter
->num_vfs
- 32)) - 1;
1835 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, eitrsel
);
1840 * ixgbe_intr - legacy mode Interrupt Handler
1841 * @irq: interrupt number
1842 * @data: pointer to a network interface device structure
1844 static irqreturn_t
ixgbe_intr(int irq
, void *data
)
1846 struct net_device
*netdev
= data
;
1847 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
1848 struct ixgbe_hw
*hw
= &adapter
->hw
;
1849 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
1853 * Workaround for silicon errata. Mask the interrupts
1854 * before the read of EICR.
1856 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_IRQ_CLEAR_MASK
);
1858 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1859 * therefore no explict interrupt disable is necessary */
1860 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICR
);
1862 /* shared interrupt alert!
1863 * make sure interrupts are enabled because the read will
1864 * have disabled interrupts due to EIAM */
1865 ixgbe_irq_enable(adapter
);
1866 return IRQ_NONE
; /* Not our interrupt */
1869 if (eicr
& IXGBE_EICR_LSC
)
1870 ixgbe_check_lsc(adapter
);
1872 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
1873 ixgbe_check_sfp_event(adapter
, eicr
);
1875 ixgbe_check_fan_failure(adapter
, eicr
);
1877 if (napi_schedule_prep(&(q_vector
->napi
))) {
1878 adapter
->tx_ring
[0].total_packets
= 0;
1879 adapter
->tx_ring
[0].total_bytes
= 0;
1880 adapter
->rx_ring
[0].total_packets
= 0;
1881 adapter
->rx_ring
[0].total_bytes
= 0;
1882 /* would disable interrupts here but EIAM disabled it */
1883 __napi_schedule(&(q_vector
->napi
));
1889 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter
*adapter
)
1891 int i
, q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1893 for (i
= 0; i
< q_vectors
; i
++) {
1894 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
1895 bitmap_zero(q_vector
->rxr_idx
, MAX_RX_QUEUES
);
1896 bitmap_zero(q_vector
->txr_idx
, MAX_TX_QUEUES
);
1897 q_vector
->rxr_count
= 0;
1898 q_vector
->txr_count
= 0;
1903 * ixgbe_request_irq - initialize interrupts
1904 * @adapter: board private structure
1906 * Attempts to configure interrupts using the best available
1907 * capabilities of the hardware and kernel.
1909 static int ixgbe_request_irq(struct ixgbe_adapter
*adapter
)
1911 struct net_device
*netdev
= adapter
->netdev
;
1914 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
1915 err
= ixgbe_request_msix_irqs(adapter
);
1916 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
1917 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, 0,
1918 netdev
->name
, netdev
);
1920 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, IRQF_SHARED
,
1921 netdev
->name
, netdev
);
1925 DPRINTK(PROBE
, ERR
, "request_irq failed, Error %d\n", err
);
1930 static void ixgbe_free_irq(struct ixgbe_adapter
*adapter
)
1932 struct net_device
*netdev
= adapter
->netdev
;
1934 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
1937 q_vectors
= adapter
->num_msix_vectors
;
1940 free_irq(adapter
->msix_entries
[i
].vector
, netdev
);
1943 for (; i
>= 0; i
--) {
1944 free_irq(adapter
->msix_entries
[i
].vector
,
1945 adapter
->q_vector
[i
]);
1948 ixgbe_reset_q_vectors(adapter
);
1950 free_irq(adapter
->pdev
->irq
, netdev
);
1955 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1956 * @adapter: board private structure
1958 static inline void ixgbe_irq_disable(struct ixgbe_adapter
*adapter
)
1960 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1961 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, ~0);
1963 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, 0xFFFF0000);
1964 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), ~0);
1965 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1), ~0);
1966 if (adapter
->num_vfs
> 32)
1967 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, 0);
1969 IXGBE_WRITE_FLUSH(&adapter
->hw
);
1970 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
1972 for (i
= 0; i
< adapter
->num_msix_vectors
; i
++)
1973 synchronize_irq(adapter
->msix_entries
[i
].vector
);
1975 synchronize_irq(adapter
->pdev
->irq
);
1980 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1983 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter
*adapter
)
1985 struct ixgbe_hw
*hw
= &adapter
->hw
;
1987 IXGBE_WRITE_REG(hw
, IXGBE_EITR(0),
1988 EITR_INTS_PER_SEC_TO_REG(adapter
->rx_eitr_param
));
1990 ixgbe_set_ivar(adapter
, 0, 0, 0);
1991 ixgbe_set_ivar(adapter
, 1, 0, 0);
1993 map_vector_to_rxq(adapter
, 0, 0);
1994 map_vector_to_txq(adapter
, 0, 0);
1996 DPRINTK(HW
, INFO
, "Legacy interrupt IVAR setup done\n");
2000 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2001 * @adapter: board private structure
2003 * Configure the Tx unit of the MAC after a reset.
2005 static void ixgbe_configure_tx(struct ixgbe_adapter
*adapter
)
2008 struct ixgbe_hw
*hw
= &adapter
->hw
;
2009 u32 i
, j
, tdlen
, txctrl
;
2011 /* Setup the HW Tx Head and Tail descriptor pointers */
2012 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2013 struct ixgbe_ring
*ring
= &adapter
->tx_ring
[i
];
2016 tdlen
= ring
->count
* sizeof(union ixgbe_adv_tx_desc
);
2017 IXGBE_WRITE_REG(hw
, IXGBE_TDBAL(j
),
2018 (tdba
& DMA_BIT_MASK(32)));
2019 IXGBE_WRITE_REG(hw
, IXGBE_TDBAH(j
), (tdba
>> 32));
2020 IXGBE_WRITE_REG(hw
, IXGBE_TDLEN(j
), tdlen
);
2021 IXGBE_WRITE_REG(hw
, IXGBE_TDH(j
), 0);
2022 IXGBE_WRITE_REG(hw
, IXGBE_TDT(j
), 0);
2023 adapter
->tx_ring
[i
].head
= IXGBE_TDH(j
);
2024 adapter
->tx_ring
[i
].tail
= IXGBE_TDT(j
);
2026 * Disable Tx Head Writeback RO bit, since this hoses
2027 * bookkeeping if things aren't delivered in order.
2029 switch (hw
->mac
.type
) {
2030 case ixgbe_mac_82598EB
:
2031 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL(j
));
2033 case ixgbe_mac_82599EB
:
2035 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL_82599(j
));
2038 txctrl
&= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN
;
2039 switch (hw
->mac
.type
) {
2040 case ixgbe_mac_82598EB
:
2041 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL(j
), txctrl
);
2043 case ixgbe_mac_82599EB
:
2045 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL_82599(j
), txctrl
);
2050 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2054 /* disable the arbiter while setting MTQC */
2055 rttdcs
= IXGBE_READ_REG(hw
, IXGBE_RTTDCS
);
2056 rttdcs
|= IXGBE_RTTDCS_ARBDIS
;
2057 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2059 /* set transmit pool layout */
2060 mask
= (IXGBE_FLAG_SRIOV_ENABLED
| IXGBE_FLAG_DCB_ENABLED
);
2061 switch (adapter
->flags
& mask
) {
2063 case (IXGBE_FLAG_SRIOV_ENABLED
):
2064 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
,
2065 (IXGBE_MTQC_VT_ENA
| IXGBE_MTQC_64VF
));
2068 case (IXGBE_FLAG_DCB_ENABLED
):
2069 /* We enable 8 traffic classes, DCB only */
2070 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
,
2071 (IXGBE_MTQC_RT_ENA
| IXGBE_MTQC_8TC_8TQ
));
2075 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
, IXGBE_MTQC_64Q_1PB
);
2079 /* re-eable the arbiter */
2080 rttdcs
&= ~IXGBE_RTTDCS_ARBDIS
;
2081 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2085 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2087 static void ixgbe_configure_srrctl(struct ixgbe_adapter
*adapter
,
2088 struct ixgbe_ring
*rx_ring
)
2092 struct ixgbe_ring_feature
*feature
= adapter
->ring_feature
;
2094 index
= rx_ring
->reg_idx
;
2095 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
2097 mask
= (unsigned long) feature
[RING_F_RSS
].mask
;
2098 index
= index
& mask
;
2100 srrctl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_SRRCTL(index
));
2102 srrctl
&= ~IXGBE_SRRCTL_BSIZEHDR_MASK
;
2103 srrctl
&= ~IXGBE_SRRCTL_BSIZEPKT_MASK
;
2105 srrctl
|= (IXGBE_RX_HDR_SIZE
<< IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT
) &
2106 IXGBE_SRRCTL_BSIZEHDR_MASK
;
2108 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
2109 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2110 srrctl
|= IXGBE_MAX_RXBUFFER
>> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2112 srrctl
|= (PAGE_SIZE
/ 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2114 srrctl
|= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS
;
2116 srrctl
|= ALIGN(rx_ring
->rx_buf_len
, 1024) >>
2117 IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2118 srrctl
|= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF
;
2121 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_SRRCTL(index
), srrctl
);
2124 static u32
ixgbe_setup_mrqc(struct ixgbe_adapter
*adapter
)
2129 if (!(adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
))
2132 mask
= adapter
->flags
& (IXGBE_FLAG_RSS_ENABLED
2133 #ifdef CONFIG_IXGBE_DCB
2134 | IXGBE_FLAG_DCB_ENABLED
2136 | IXGBE_FLAG_SRIOV_ENABLED
2140 case (IXGBE_FLAG_RSS_ENABLED
):
2141 mrqc
= IXGBE_MRQC_RSSEN
;
2143 case (IXGBE_FLAG_SRIOV_ENABLED
):
2144 mrqc
= IXGBE_MRQC_VMDQEN
;
2146 #ifdef CONFIG_IXGBE_DCB
2147 case (IXGBE_FLAG_DCB_ENABLED
):
2148 mrqc
= IXGBE_MRQC_RT8TCEN
;
2150 #endif /* CONFIG_IXGBE_DCB */
2159 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2160 * @adapter: address of board private structure
2161 * @index: index of ring to set
2163 static void ixgbe_configure_rscctl(struct ixgbe_adapter
*adapter
, int index
)
2165 struct ixgbe_ring
*rx_ring
;
2166 struct ixgbe_hw
*hw
= &adapter
->hw
;
2171 rx_ring
= &adapter
->rx_ring
[index
];
2172 j
= rx_ring
->reg_idx
;
2173 rx_buf_len
= rx_ring
->rx_buf_len
;
2174 rscctrl
= IXGBE_READ_REG(hw
, IXGBE_RSCCTL(j
));
2175 rscctrl
|= IXGBE_RSCCTL_RSCEN
;
2177 * we must limit the number of descriptors so that the
2178 * total size of max desc * buf_len is not greater
2181 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
2182 #if (MAX_SKB_FRAGS > 16)
2183 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2184 #elif (MAX_SKB_FRAGS > 8)
2185 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2186 #elif (MAX_SKB_FRAGS > 4)
2187 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2189 rscctrl
|= IXGBE_RSCCTL_MAXDESC_1
;
2192 if (rx_buf_len
< IXGBE_RXBUFFER_4096
)
2193 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2194 else if (rx_buf_len
< IXGBE_RXBUFFER_8192
)
2195 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2197 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2199 IXGBE_WRITE_REG(hw
, IXGBE_RSCCTL(j
), rscctrl
);
2203 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2204 * @adapter: board private structure
2206 * Configure the Rx unit of the MAC after a reset.
2208 static void ixgbe_configure_rx(struct ixgbe_adapter
*adapter
)
2211 struct ixgbe_hw
*hw
= &adapter
->hw
;
2212 struct ixgbe_ring
*rx_ring
;
2213 struct net_device
*netdev
= adapter
->netdev
;
2214 int max_frame
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
2216 u32 rdlen
, rxctrl
, rxcsum
;
2217 static const u32 seed
[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2218 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2219 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2221 u32 reta
= 0, mrqc
= 0;
2225 /* Decide whether to use packet split mode or not */
2226 /* Do not use packet split if we're in SR-IOV Mode */
2227 if (!adapter
->num_vfs
)
2228 adapter
->flags
|= IXGBE_FLAG_RX_PS_ENABLED
;
2230 /* Set the RX buffer length according to the mode */
2231 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
) {
2232 rx_buf_len
= IXGBE_RX_HDR_SIZE
;
2233 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2234 /* PSRTYPE must be initialized in 82599 */
2235 u32 psrtype
= IXGBE_PSRTYPE_TCPHDR
|
2236 IXGBE_PSRTYPE_UDPHDR
|
2237 IXGBE_PSRTYPE_IPV4HDR
|
2238 IXGBE_PSRTYPE_IPV6HDR
|
2239 IXGBE_PSRTYPE_L2HDR
;
2241 IXGBE_PSRTYPE(adapter
->num_vfs
),
2245 if (!(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) &&
2246 (netdev
->mtu
<= ETH_DATA_LEN
))
2247 rx_buf_len
= MAXIMUM_ETHERNET_VLAN_SIZE
;
2249 rx_buf_len
= ALIGN(max_frame
, 1024);
2252 fctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_FCTRL
);
2253 fctrl
|= IXGBE_FCTRL_BAM
;
2254 fctrl
|= IXGBE_FCTRL_DPF
; /* discard pause frames when FC enabled */
2255 fctrl
|= IXGBE_FCTRL_PMCF
;
2256 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_FCTRL
, fctrl
);
2258 hlreg0
= IXGBE_READ_REG(hw
, IXGBE_HLREG0
);
2259 if (adapter
->netdev
->mtu
<= ETH_DATA_LEN
)
2260 hlreg0
&= ~IXGBE_HLREG0_JUMBOEN
;
2262 hlreg0
|= IXGBE_HLREG0_JUMBOEN
;
2264 if (netdev
->features
& NETIF_F_FCOE_MTU
)
2265 hlreg0
|= IXGBE_HLREG0_JUMBOEN
;
2267 IXGBE_WRITE_REG(hw
, IXGBE_HLREG0
, hlreg0
);
2269 rdlen
= adapter
->rx_ring
[0].count
* sizeof(union ixgbe_adv_rx_desc
);
2270 /* disable receives while setting up the descriptors */
2271 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
2272 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
2275 * Setup the HW Rx Head and Tail Descriptor Pointers and
2276 * the Base and Length of the Rx Descriptor Ring
2278 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2279 rx_ring
= &adapter
->rx_ring
[i
];
2280 rdba
= rx_ring
->dma
;
2281 j
= rx_ring
->reg_idx
;
2282 IXGBE_WRITE_REG(hw
, IXGBE_RDBAL(j
), (rdba
& DMA_BIT_MASK(32)));
2283 IXGBE_WRITE_REG(hw
, IXGBE_RDBAH(j
), (rdba
>> 32));
2284 IXGBE_WRITE_REG(hw
, IXGBE_RDLEN(j
), rdlen
);
2285 IXGBE_WRITE_REG(hw
, IXGBE_RDH(j
), 0);
2286 IXGBE_WRITE_REG(hw
, IXGBE_RDT(j
), 0);
2287 rx_ring
->head
= IXGBE_RDH(j
);
2288 rx_ring
->tail
= IXGBE_RDT(j
);
2289 rx_ring
->rx_buf_len
= rx_buf_len
;
2291 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
)
2292 rx_ring
->flags
|= IXGBE_RING_RX_PS_ENABLED
;
2294 rx_ring
->flags
&= ~IXGBE_RING_RX_PS_ENABLED
;
2297 if (netdev
->features
& NETIF_F_FCOE_MTU
) {
2298 struct ixgbe_ring_feature
*f
;
2299 f
= &adapter
->ring_feature
[RING_F_FCOE
];
2300 if ((i
>= f
->mask
) && (i
< f
->mask
+ f
->indices
)) {
2301 rx_ring
->flags
&= ~IXGBE_RING_RX_PS_ENABLED
;
2302 if (rx_buf_len
< IXGBE_FCOE_JUMBO_FRAME_SIZE
)
2303 rx_ring
->rx_buf_len
=
2304 IXGBE_FCOE_JUMBO_FRAME_SIZE
;
2308 #endif /* IXGBE_FCOE */
2309 ixgbe_configure_srrctl(adapter
, rx_ring
);
2312 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
2314 * For VMDq support of different descriptor types or
2315 * buffer sizes through the use of multiple SRRCTL
2316 * registers, RDRXCTL.MVMEN must be set to 1
2318 * also, the manual doesn't mention it clearly but DCA hints
2319 * will only use queue 0's tags unless this bit is set. Side
2320 * effects of setting this bit are only that SRRCTL must be
2321 * fully programmed [0..15]
2323 rdrxctl
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
2324 rdrxctl
|= IXGBE_RDRXCTL_MVMEN
;
2325 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, rdrxctl
);
2328 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
2330 u32 reg_offset
, vf_shift
;
2331 u32 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
2332 vt_reg_bits
= IXGBE_VMD_CTL_VMDQ_EN
2333 | IXGBE_VT_CTL_REPLEN
;
2334 vt_reg_bits
|= (adapter
->num_vfs
<<
2335 IXGBE_VT_CTL_POOL_SHIFT
);
2336 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
| vt_reg_bits
);
2337 IXGBE_WRITE_REG(hw
, IXGBE_MRQC
, 0);
2339 vf_shift
= adapter
->num_vfs
% 32;
2340 reg_offset
= adapter
->num_vfs
/ 32;
2341 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(0), 0);
2342 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(1), 0);
2343 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(0), 0);
2344 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(1), 0);
2345 /* Enable only the PF's pool for Tx/Rx */
2346 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(reg_offset
), (1 << vf_shift
));
2347 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(reg_offset
), (1 << vf_shift
));
2348 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, IXGBE_PFDTXGSWC_VT_LBEN
);
2349 ixgbe_set_vmolr(hw
, adapter
->num_vfs
);
2352 /* Program MRQC for the distribution of queues */
2353 mrqc
= ixgbe_setup_mrqc(adapter
);
2355 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
2356 /* Fill out redirection table */
2357 for (i
= 0, j
= 0; i
< 128; i
++, j
++) {
2358 if (j
== adapter
->ring_feature
[RING_F_RSS
].indices
)
2360 /* reta = 4-byte sliding window of
2361 * 0x00..(indices-1)(indices-1)00..etc. */
2362 reta
= (reta
<< 8) | (j
* 0x11);
2364 IXGBE_WRITE_REG(hw
, IXGBE_RETA(i
>> 2), reta
);
2367 /* Fill out hash function seeds */
2368 for (i
= 0; i
< 10; i
++)
2369 IXGBE_WRITE_REG(hw
, IXGBE_RSSRK(i
), seed
[i
]);
2371 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2372 mrqc
|= IXGBE_MRQC_RSSEN
;
2373 /* Perform hash on these packet types */
2374 mrqc
|= IXGBE_MRQC_RSS_FIELD_IPV4
2375 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2376 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2377 | IXGBE_MRQC_RSS_FIELD_IPV6
2378 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2379 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP
;
2381 IXGBE_WRITE_REG(hw
, IXGBE_MRQC
, mrqc
);
2383 if (adapter
->num_vfs
) {
2386 /* Map PF MAC address in RAR Entry 0 to first pool
2388 hw
->mac
.ops
.set_vmdq(hw
, 0, adapter
->num_vfs
);
2390 /* Set up VF register offsets for selected VT Mode, i.e.
2391 * 64 VFs for SR-IOV */
2392 reg
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
2393 reg
|= IXGBE_GCR_EXT_SRIOV
;
2394 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, reg
);
2397 rxcsum
= IXGBE_READ_REG(hw
, IXGBE_RXCSUM
);
2399 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
||
2400 adapter
->flags
& IXGBE_FLAG_RX_CSUM_ENABLED
) {
2401 /* Disable indicating checksum in descriptor, enables
2403 rxcsum
|= IXGBE_RXCSUM_PCSD
;
2405 if (!(rxcsum
& IXGBE_RXCSUM_PCSD
)) {
2406 /* Enable IPv4 payload checksum for UDP fragments
2407 * if PCSD is not set */
2408 rxcsum
|= IXGBE_RXCSUM_IPPCSE
;
2411 IXGBE_WRITE_REG(hw
, IXGBE_RXCSUM
, rxcsum
);
2413 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2414 rdrxctl
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
2415 rdrxctl
|= IXGBE_RDRXCTL_CRCSTRIP
;
2416 rdrxctl
&= ~IXGBE_RDRXCTL_RSCFRSTSIZE
;
2417 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, rdrxctl
);
2420 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
2421 /* Enable 82599 HW-RSC */
2422 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
2423 ixgbe_configure_rscctl(adapter
, i
);
2425 /* Disable RSC for ACK packets */
2426 IXGBE_WRITE_REG(hw
, IXGBE_RSCDBU
,
2427 (IXGBE_RSCDBU_RSCACKDIS
| IXGBE_READ_REG(hw
, IXGBE_RSCDBU
)));
2431 static void ixgbe_vlan_rx_add_vid(struct net_device
*netdev
, u16 vid
)
2433 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2434 struct ixgbe_hw
*hw
= &adapter
->hw
;
2435 int pool_ndx
= adapter
->num_vfs
;
2437 /* add VID to filter table */
2438 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, true);
2441 static void ixgbe_vlan_rx_kill_vid(struct net_device
*netdev
, u16 vid
)
2443 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2444 struct ixgbe_hw
*hw
= &adapter
->hw
;
2445 int pool_ndx
= adapter
->num_vfs
;
2447 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2448 ixgbe_irq_disable(adapter
);
2450 vlan_group_set_device(adapter
->vlgrp
, vid
, NULL
);
2452 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2453 ixgbe_irq_enable(adapter
);
2455 /* remove VID from filter table */
2456 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, false);
2459 static void ixgbe_vlan_rx_register(struct net_device
*netdev
,
2460 struct vlan_group
*grp
)
2462 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2466 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2467 ixgbe_irq_disable(adapter
);
2468 adapter
->vlgrp
= grp
;
2471 * For a DCB driver, always enable VLAN tag stripping so we can
2472 * still receive traffic from a DCB-enabled host even if we're
2475 ctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_VLNCTRL
);
2477 /* Disable CFI check */
2478 ctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2480 /* enable VLAN tag stripping */
2481 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
2482 ctrl
|= IXGBE_VLNCTRL_VME
;
2483 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
2484 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2486 j
= adapter
->rx_ring
[i
].reg_idx
;
2487 ctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_RXDCTL(j
));
2488 ctrl
|= IXGBE_RXDCTL_VME
;
2489 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_RXDCTL(j
), ctrl
);
2493 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_VLNCTRL
, ctrl
);
2495 ixgbe_vlan_rx_add_vid(netdev
, 0);
2497 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2498 ixgbe_irq_enable(adapter
);
2501 static void ixgbe_restore_vlan(struct ixgbe_adapter
*adapter
)
2503 ixgbe_vlan_rx_register(adapter
->netdev
, adapter
->vlgrp
);
2505 if (adapter
->vlgrp
) {
2507 for (vid
= 0; vid
< VLAN_GROUP_ARRAY_LEN
; vid
++) {
2508 if (!vlan_group_get_device(adapter
->vlgrp
, vid
))
2510 ixgbe_vlan_rx_add_vid(adapter
->netdev
, vid
);
2515 static u8
*ixgbe_addr_list_itr(struct ixgbe_hw
*hw
, u8
**mc_addr_ptr
, u32
*vmdq
)
2517 struct dev_mc_list
*mc_ptr
;
2518 u8
*addr
= *mc_addr_ptr
;
2521 mc_ptr
= container_of(addr
, struct dev_mc_list
, dmi_addr
[0]);
2523 *mc_addr_ptr
= mc_ptr
->next
->dmi_addr
;
2525 *mc_addr_ptr
= NULL
;
2531 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2532 * @netdev: network interface device structure
2534 * The set_rx_method entry point is called whenever the unicast/multicast
2535 * address list or the network interface flags are updated. This routine is
2536 * responsible for configuring the hardware for proper unicast, multicast and
2539 void ixgbe_set_rx_mode(struct net_device
*netdev
)
2541 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2542 struct ixgbe_hw
*hw
= &adapter
->hw
;
2544 u8
*addr_list
= NULL
;
2547 /* Check for Promiscuous and All Multicast modes */
2549 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
2550 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
2552 if (netdev
->flags
& IFF_PROMISC
) {
2553 hw
->addr_ctrl
.user_set_promisc
= 1;
2554 fctrl
|= (IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
2555 vlnctrl
&= ~IXGBE_VLNCTRL_VFE
;
2557 if (netdev
->flags
& IFF_ALLMULTI
) {
2558 fctrl
|= IXGBE_FCTRL_MPE
;
2559 fctrl
&= ~IXGBE_FCTRL_UPE
;
2561 fctrl
&= ~(IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
2563 vlnctrl
|= IXGBE_VLNCTRL_VFE
;
2564 hw
->addr_ctrl
.user_set_promisc
= 0;
2567 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
2568 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2570 /* reprogram secondary unicast list */
2571 hw
->mac
.ops
.update_uc_addr_list(hw
, &netdev
->uc
.list
);
2573 /* reprogram multicast list */
2574 addr_count
= netdev
->mc_count
;
2576 addr_list
= netdev
->mc_list
->dmi_addr
;
2577 hw
->mac
.ops
.update_mc_addr_list(hw
, addr_list
, addr_count
,
2578 ixgbe_addr_list_itr
);
2579 if (adapter
->num_vfs
)
2580 ixgbe_restore_vf_multicasts(adapter
);
2583 static void ixgbe_napi_enable_all(struct ixgbe_adapter
*adapter
)
2586 struct ixgbe_q_vector
*q_vector
;
2587 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2589 /* legacy and MSI only use one vector */
2590 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
2593 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
2594 struct napi_struct
*napi
;
2595 q_vector
= adapter
->q_vector
[q_idx
];
2596 napi
= &q_vector
->napi
;
2597 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2598 if (!q_vector
->rxr_count
|| !q_vector
->txr_count
) {
2599 if (q_vector
->txr_count
== 1)
2600 napi
->poll
= &ixgbe_clean_txonly
;
2601 else if (q_vector
->rxr_count
== 1)
2602 napi
->poll
= &ixgbe_clean_rxonly
;
2610 static void ixgbe_napi_disable_all(struct ixgbe_adapter
*adapter
)
2613 struct ixgbe_q_vector
*q_vector
;
2614 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2616 /* legacy and MSI only use one vector */
2617 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
2620 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
2621 q_vector
= adapter
->q_vector
[q_idx
];
2622 napi_disable(&q_vector
->napi
);
2626 #ifdef CONFIG_IXGBE_DCB
2628 * ixgbe_configure_dcb - Configure DCB hardware
2629 * @adapter: ixgbe adapter struct
2631 * This is called by the driver on open to configure the DCB hardware.
2632 * This is also called by the gennetlink interface when reconfiguring
2635 static void ixgbe_configure_dcb(struct ixgbe_adapter
*adapter
)
2637 struct ixgbe_hw
*hw
= &adapter
->hw
;
2638 u32 txdctl
, vlnctrl
;
2641 ixgbe_dcb_check_config(&adapter
->dcb_cfg
);
2642 ixgbe_dcb_calculate_tc_credits(&adapter
->dcb_cfg
, DCB_TX_CONFIG
);
2643 ixgbe_dcb_calculate_tc_credits(&adapter
->dcb_cfg
, DCB_RX_CONFIG
);
2645 /* reconfigure the hardware */
2646 ixgbe_dcb_hw_config(&adapter
->hw
, &adapter
->dcb_cfg
);
2648 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2649 j
= adapter
->tx_ring
[i
].reg_idx
;
2650 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
2651 /* PThresh workaround for Tx hang with DFP enabled. */
2653 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
), txdctl
);
2655 /* Enable VLAN tag insert/strip */
2656 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
2657 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
2658 vlnctrl
|= IXGBE_VLNCTRL_VME
| IXGBE_VLNCTRL_VFE
;
2659 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2660 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2661 } else if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2662 vlnctrl
|= IXGBE_VLNCTRL_VFE
;
2663 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2664 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2665 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2666 j
= adapter
->rx_ring
[i
].reg_idx
;
2667 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
2668 vlnctrl
|= IXGBE_RXDCTL_VME
;
2669 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
2672 hw
->mac
.ops
.set_vfta(&adapter
->hw
, 0, 0, true);
2676 static void ixgbe_configure(struct ixgbe_adapter
*adapter
)
2678 struct net_device
*netdev
= adapter
->netdev
;
2679 struct ixgbe_hw
*hw
= &adapter
->hw
;
2682 ixgbe_set_rx_mode(netdev
);
2684 ixgbe_restore_vlan(adapter
);
2685 #ifdef CONFIG_IXGBE_DCB
2686 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
2687 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2688 netif_set_gso_max_size(netdev
, 32768);
2690 netif_set_gso_max_size(netdev
, 65536);
2691 ixgbe_configure_dcb(adapter
);
2693 netif_set_gso_max_size(netdev
, 65536);
2696 netif_set_gso_max_size(netdev
, 65536);
2700 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
2701 ixgbe_configure_fcoe(adapter
);
2703 #endif /* IXGBE_FCOE */
2704 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
2705 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
2706 adapter
->tx_ring
[i
].atr_sample_rate
=
2707 adapter
->atr_sample_rate
;
2708 ixgbe_init_fdir_signature_82599(hw
, adapter
->fdir_pballoc
);
2709 } else if (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
) {
2710 ixgbe_init_fdir_perfect_82599(hw
, adapter
->fdir_pballoc
);
2713 ixgbe_configure_tx(adapter
);
2714 ixgbe_configure_rx(adapter
);
2715 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
2716 ixgbe_alloc_rx_buffers(adapter
, &adapter
->rx_ring
[i
],
2717 (adapter
->rx_ring
[i
].count
- 1));
2720 static inline bool ixgbe_is_sfp(struct ixgbe_hw
*hw
)
2722 switch (hw
->phy
.type
) {
2723 case ixgbe_phy_sfp_avago
:
2724 case ixgbe_phy_sfp_ftl
:
2725 case ixgbe_phy_sfp_intel
:
2726 case ixgbe_phy_sfp_unknown
:
2727 case ixgbe_phy_tw_tyco
:
2728 case ixgbe_phy_tw_unknown
:
2736 * ixgbe_sfp_link_config - set up SFP+ link
2737 * @adapter: pointer to private adapter struct
2739 static void ixgbe_sfp_link_config(struct ixgbe_adapter
*adapter
)
2741 struct ixgbe_hw
*hw
= &adapter
->hw
;
2743 if (hw
->phy
.multispeed_fiber
) {
2745 * In multispeed fiber setups, the device may not have
2746 * had a physical connection when the driver loaded.
2747 * If that's the case, the initial link configuration
2748 * couldn't get the MAC into 10G or 1G mode, so we'll
2749 * never have a link status change interrupt fire.
2750 * We need to try and force an autonegotiation
2751 * session, then bring up link.
2753 hw
->mac
.ops
.setup_sfp(hw
);
2754 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_LINK_TASK
))
2755 schedule_work(&adapter
->multispeed_fiber_task
);
2758 * Direct Attach Cu and non-multispeed fiber modules
2759 * still need to be configured properly prior to
2762 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_MOD_TASK
))
2763 schedule_work(&adapter
->sfp_config_module_task
);
2768 * ixgbe_non_sfp_link_config - set up non-SFP+ link
2769 * @hw: pointer to private hardware struct
2771 * Returns 0 on success, negative on failure
2773 static int ixgbe_non_sfp_link_config(struct ixgbe_hw
*hw
)
2776 bool negotiation
, link_up
= false;
2777 u32 ret
= IXGBE_ERR_LINK_SETUP
;
2779 if (hw
->mac
.ops
.check_link
)
2780 ret
= hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
2785 if (hw
->mac
.ops
.get_link_capabilities
)
2786 ret
= hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
, &negotiation
);
2790 if (hw
->mac
.ops
.setup_link
)
2791 ret
= hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, link_up
);
2796 #define IXGBE_MAX_RX_DESC_POLL 10
2797 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter
*adapter
,
2800 int j
= adapter
->rx_ring
[rxr
].reg_idx
;
2803 for (k
= 0; k
< IXGBE_MAX_RX_DESC_POLL
; k
++) {
2804 if (IXGBE_READ_REG(&adapter
->hw
,
2805 IXGBE_RXDCTL(j
)) & IXGBE_RXDCTL_ENABLE
)
2810 if (k
>= IXGBE_MAX_RX_DESC_POLL
) {
2811 DPRINTK(DRV
, ERR
, "RXDCTL.ENABLE on Rx queue %d "
2812 "not set within the polling period\n", rxr
);
2814 ixgbe_release_rx_desc(&adapter
->hw
, &adapter
->rx_ring
[rxr
],
2815 (adapter
->rx_ring
[rxr
].count
- 1));
2818 static int ixgbe_up_complete(struct ixgbe_adapter
*adapter
)
2820 struct net_device
*netdev
= adapter
->netdev
;
2821 struct ixgbe_hw
*hw
= &adapter
->hw
;
2823 int num_rx_rings
= adapter
->num_rx_queues
;
2825 int max_frame
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
2826 u32 txdctl
, rxdctl
, mhadd
;
2830 ixgbe_get_hw_control(adapter
);
2832 if ((adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) ||
2833 (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
)) {
2834 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2835 gpie
= (IXGBE_GPIE_MSIX_MODE
| IXGBE_GPIE_EIAME
|
2836 IXGBE_GPIE_PBA_SUPPORT
| IXGBE_GPIE_OCD
);
2841 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
2842 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
2843 gpie
|= IXGBE_GPIE_VTMODE_64
;
2845 /* XXX: to interrupt immediately for EICS writes, enable this */
2846 /* gpie |= IXGBE_GPIE_EIMEN; */
2847 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
2850 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2852 * use EIAM to auto-mask when MSI-X interrupt is asserted
2853 * this saves a register write for every interrupt
2855 switch (hw
->mac
.type
) {
2856 case ixgbe_mac_82598EB
:
2857 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
2860 case ixgbe_mac_82599EB
:
2861 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
2862 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
2866 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2867 * specifically only auto mask tx and rx interrupts */
2868 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
2871 /* Enable fan failure interrupt if media type is copper */
2872 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
2873 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
2874 gpie
|= IXGBE_SDP1_GPIEN
;
2875 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
2878 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2879 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
2880 gpie
|= IXGBE_SDP1_GPIEN
;
2881 gpie
|= IXGBE_SDP2_GPIEN
;
2882 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
2886 /* adjust max frame to be able to do baby jumbo for FCoE */
2887 if ((netdev
->features
& NETIF_F_FCOE_MTU
) &&
2888 (max_frame
< IXGBE_FCOE_JUMBO_FRAME_SIZE
))
2889 max_frame
= IXGBE_FCOE_JUMBO_FRAME_SIZE
;
2891 #endif /* IXGBE_FCOE */
2892 mhadd
= IXGBE_READ_REG(hw
, IXGBE_MHADD
);
2893 if (max_frame
!= (mhadd
>> IXGBE_MHADD_MFS_SHIFT
)) {
2894 mhadd
&= ~IXGBE_MHADD_MFS_MASK
;
2895 mhadd
|= max_frame
<< IXGBE_MHADD_MFS_SHIFT
;
2897 IXGBE_WRITE_REG(hw
, IXGBE_MHADD
, mhadd
);
2900 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2901 j
= adapter
->tx_ring
[i
].reg_idx
;
2902 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
2903 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2904 txdctl
|= (8 << 16);
2905 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
), txdctl
);
2908 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2909 /* DMATXCTL.EN must be set after all Tx queue config is done */
2910 dmatxctl
= IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
);
2911 dmatxctl
|= IXGBE_DMATXCTL_TE
;
2912 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
, dmatxctl
);
2914 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2915 j
= adapter
->tx_ring
[i
].reg_idx
;
2916 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
2917 txdctl
|= IXGBE_TXDCTL_ENABLE
;
2918 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
), txdctl
);
2919 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2921 /* poll for Tx Enable ready */
2924 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
2925 } while (--wait_loop
&&
2926 !(txdctl
& IXGBE_TXDCTL_ENABLE
));
2928 DPRINTK(DRV
, ERR
, "Could not enable "
2929 "Tx Queue %d\n", j
);
2933 for (i
= 0; i
< num_rx_rings
; i
++) {
2934 j
= adapter
->rx_ring
[i
].reg_idx
;
2935 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
2936 /* enable PTHRESH=32 descriptors (half the internal cache)
2937 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2938 * this also removes a pesky rx_no_buffer_count increment */
2940 rxdctl
|= IXGBE_RXDCTL_ENABLE
;
2941 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), rxdctl
);
2942 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
2943 ixgbe_rx_desc_queue_enable(adapter
, i
);
2945 /* enable all receives */
2946 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
2947 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2948 rxdctl
|= (IXGBE_RXCTRL_DMBYPS
| IXGBE_RXCTRL_RXEN
);
2950 rxdctl
|= IXGBE_RXCTRL_RXEN
;
2951 hw
->mac
.ops
.enable_rx_dma(hw
, rxdctl
);
2953 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
2954 ixgbe_configure_msix(adapter
);
2956 ixgbe_configure_msi_and_legacy(adapter
);
2958 clear_bit(__IXGBE_DOWN
, &adapter
->state
);
2959 ixgbe_napi_enable_all(adapter
);
2961 /* clear any pending interrupts, may auto mask */
2962 IXGBE_READ_REG(hw
, IXGBE_EICR
);
2964 ixgbe_irq_enable(adapter
);
2967 * If this adapter has a fan, check to see if we had a failure
2968 * before we enabled the interrupt.
2970 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
2971 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
2972 if (esdp
& IXGBE_ESDP_SDP1
)
2974 "Fan has stopped, replace the adapter\n");
2978 * For hot-pluggable SFP+ devices, a new SFP+ module may have
2979 * arrived before interrupts were enabled but after probe. Such
2980 * devices wouldn't have their type identified yet. We need to
2981 * kick off the SFP+ module setup first, then try to bring up link.
2982 * If we're not hot-pluggable SFP+, we just need to configure link
2985 if (hw
->phy
.type
== ixgbe_phy_unknown
) {
2986 err
= hw
->phy
.ops
.identify(hw
);
2987 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
2989 * Take the device down and schedule the sfp tasklet
2990 * which will unregister_netdev and log it.
2992 ixgbe_down(adapter
);
2993 schedule_work(&adapter
->sfp_config_module_task
);
2998 if (ixgbe_is_sfp(hw
)) {
2999 ixgbe_sfp_link_config(adapter
);
3001 err
= ixgbe_non_sfp_link_config(hw
);
3003 DPRINTK(PROBE
, ERR
, "link_config FAILED %d\n", err
);
3006 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3007 set_bit(__IXGBE_FDIR_INIT_DONE
,
3008 &(adapter
->tx_ring
[i
].reinit_state
));
3010 /* enable transmits */
3011 netif_tx_start_all_queues(netdev
);
3013 /* bring the link up in the watchdog, this could race with our first
3014 * link up interrupt but shouldn't be a problem */
3015 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
3016 adapter
->link_check_timeout
= jiffies
;
3017 mod_timer(&adapter
->watchdog_timer
, jiffies
);
3021 void ixgbe_reinit_locked(struct ixgbe_adapter
*adapter
)
3023 WARN_ON(in_interrupt());
3024 while (test_and_set_bit(__IXGBE_RESETTING
, &adapter
->state
))
3026 ixgbe_down(adapter
);
3028 clear_bit(__IXGBE_RESETTING
, &adapter
->state
);
3031 int ixgbe_up(struct ixgbe_adapter
*adapter
)
3033 /* hardware has been reset, we need to reload some things */
3034 ixgbe_configure(adapter
);
3036 return ixgbe_up_complete(adapter
);
3039 void ixgbe_reset(struct ixgbe_adapter
*adapter
)
3041 struct ixgbe_hw
*hw
= &adapter
->hw
;
3044 err
= hw
->mac
.ops
.init_hw(hw
);
3047 case IXGBE_ERR_SFP_NOT_PRESENT
:
3049 case IXGBE_ERR_MASTER_REQUESTS_PENDING
:
3050 dev_err(&adapter
->pdev
->dev
, "master disable timed out\n");
3052 case IXGBE_ERR_EEPROM_VERSION
:
3053 /* We are running on a pre-production device, log a warning */
3054 dev_warn(&adapter
->pdev
->dev
, "This device is a pre-production "
3055 "adapter/LOM. Please be aware there may be issues "
3056 "associated with your hardware. If you are "
3057 "experiencing problems please contact your Intel or "
3058 "hardware representative who provided you with this "
3062 dev_err(&adapter
->pdev
->dev
, "Hardware Error: %d\n", err
);
3065 /* reprogram the RAR[0] in case user changed it. */
3066 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
3071 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3072 * @adapter: board private structure
3073 * @rx_ring: ring to free buffers from
3075 static void ixgbe_clean_rx_ring(struct ixgbe_adapter
*adapter
,
3076 struct ixgbe_ring
*rx_ring
)
3078 struct pci_dev
*pdev
= adapter
->pdev
;
3082 /* Free all the Rx ring sk_buffs */
3084 for (i
= 0; i
< rx_ring
->count
; i
++) {
3085 struct ixgbe_rx_buffer
*rx_buffer_info
;
3087 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
3088 if (rx_buffer_info
->dma
) {
3089 pci_unmap_single(pdev
, rx_buffer_info
->dma
,
3090 rx_ring
->rx_buf_len
,
3091 PCI_DMA_FROMDEVICE
);
3092 rx_buffer_info
->dma
= 0;
3094 if (rx_buffer_info
->skb
) {
3095 struct sk_buff
*skb
= rx_buffer_info
->skb
;
3096 rx_buffer_info
->skb
= NULL
;
3098 struct sk_buff
*this = skb
;
3100 dev_kfree_skb(this);
3103 if (!rx_buffer_info
->page
)
3105 if (rx_buffer_info
->page_dma
) {
3106 pci_unmap_page(pdev
, rx_buffer_info
->page_dma
,
3107 PAGE_SIZE
/ 2, PCI_DMA_FROMDEVICE
);
3108 rx_buffer_info
->page_dma
= 0;
3110 put_page(rx_buffer_info
->page
);
3111 rx_buffer_info
->page
= NULL
;
3112 rx_buffer_info
->page_offset
= 0;
3115 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
3116 memset(rx_ring
->rx_buffer_info
, 0, size
);
3118 /* Zero out the descriptor ring */
3119 memset(rx_ring
->desc
, 0, rx_ring
->size
);
3121 rx_ring
->next_to_clean
= 0;
3122 rx_ring
->next_to_use
= 0;
3125 writel(0, adapter
->hw
.hw_addr
+ rx_ring
->head
);
3127 writel(0, adapter
->hw
.hw_addr
+ rx_ring
->tail
);
3131 * ixgbe_clean_tx_ring - Free Tx Buffers
3132 * @adapter: board private structure
3133 * @tx_ring: ring to be cleaned
3135 static void ixgbe_clean_tx_ring(struct ixgbe_adapter
*adapter
,
3136 struct ixgbe_ring
*tx_ring
)
3138 struct ixgbe_tx_buffer
*tx_buffer_info
;
3142 /* Free all the Tx ring sk_buffs */
3144 for (i
= 0; i
< tx_ring
->count
; i
++) {
3145 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
3146 ixgbe_unmap_and_free_tx_resource(adapter
, tx_buffer_info
);
3149 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
3150 memset(tx_ring
->tx_buffer_info
, 0, size
);
3152 /* Zero out the descriptor ring */
3153 memset(tx_ring
->desc
, 0, tx_ring
->size
);
3155 tx_ring
->next_to_use
= 0;
3156 tx_ring
->next_to_clean
= 0;
3159 writel(0, adapter
->hw
.hw_addr
+ tx_ring
->head
);
3161 writel(0, adapter
->hw
.hw_addr
+ tx_ring
->tail
);
3165 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3166 * @adapter: board private structure
3168 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter
*adapter
)
3172 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3173 ixgbe_clean_rx_ring(adapter
, &adapter
->rx_ring
[i
]);
3177 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3178 * @adapter: board private structure
3180 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter
*adapter
)
3184 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3185 ixgbe_clean_tx_ring(adapter
, &adapter
->tx_ring
[i
]);
3188 void ixgbe_down(struct ixgbe_adapter
*adapter
)
3190 struct net_device
*netdev
= adapter
->netdev
;
3191 struct ixgbe_hw
*hw
= &adapter
->hw
;
3196 /* signal that we are down to the interrupt handler */
3197 set_bit(__IXGBE_DOWN
, &adapter
->state
);
3199 /* disable receives */
3200 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
3201 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
3203 netif_tx_disable(netdev
);
3205 IXGBE_WRITE_FLUSH(hw
);
3208 netif_tx_stop_all_queues(netdev
);
3210 ixgbe_irq_disable(adapter
);
3212 ixgbe_napi_disable_all(adapter
);
3214 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
3215 del_timer_sync(&adapter
->sfp_timer
);
3216 del_timer_sync(&adapter
->watchdog_timer
);
3217 cancel_work_sync(&adapter
->watchdog_task
);
3219 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
3220 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
3221 cancel_work_sync(&adapter
->fdir_reinit_task
);
3223 /* disable transmits in the hardware now that interrupts are off */
3224 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
3225 j
= adapter
->tx_ring
[i
].reg_idx
;
3226 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
3227 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
),
3228 (txdctl
& ~IXGBE_TXDCTL_ENABLE
));
3230 /* Disable the Tx DMA engine on 82599 */
3231 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
3232 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
,
3233 (IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
) &
3234 ~IXGBE_DMATXCTL_TE
));
3236 netif_carrier_off(netdev
);
3238 if (!pci_channel_offline(adapter
->pdev
))
3239 ixgbe_reset(adapter
);
3240 ixgbe_clean_all_tx_rings(adapter
);
3241 ixgbe_clean_all_rx_rings(adapter
);
3243 #ifdef CONFIG_IXGBE_DCA
3244 /* since we reset the hardware DCA settings were cleared */
3245 ixgbe_setup_dca(adapter
);
3250 * ixgbe_poll - NAPI Rx polling callback
3251 * @napi: structure for representing this polling device
3252 * @budget: how many packets driver is allowed to clean
3254 * This function is used for legacy and MSI, NAPI mode
3256 static int ixgbe_poll(struct napi_struct
*napi
, int budget
)
3258 struct ixgbe_q_vector
*q_vector
=
3259 container_of(napi
, struct ixgbe_q_vector
, napi
);
3260 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
3261 int tx_clean_complete
, work_done
= 0;
3263 #ifdef CONFIG_IXGBE_DCA
3264 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
3265 ixgbe_update_tx_dca(adapter
, adapter
->tx_ring
);
3266 ixgbe_update_rx_dca(adapter
, adapter
->rx_ring
);
3270 tx_clean_complete
= ixgbe_clean_tx_irq(q_vector
, adapter
->tx_ring
);
3271 ixgbe_clean_rx_irq(q_vector
, adapter
->rx_ring
, &work_done
, budget
);
3273 if (!tx_clean_complete
)
3276 /* If budget not fully consumed, exit the polling mode */
3277 if (work_done
< budget
) {
3278 napi_complete(napi
);
3279 if (adapter
->rx_itr_setting
& 1)
3280 ixgbe_set_itr(adapter
);
3281 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
3282 ixgbe_irq_enable_queues(adapter
, IXGBE_EIMS_RTX_QUEUE
);
3288 * ixgbe_tx_timeout - Respond to a Tx Hang
3289 * @netdev: network interface device structure
3291 static void ixgbe_tx_timeout(struct net_device
*netdev
)
3293 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3295 /* Do the reset outside of interrupt context */
3296 schedule_work(&adapter
->reset_task
);
3299 static void ixgbe_reset_task(struct work_struct
*work
)
3301 struct ixgbe_adapter
*adapter
;
3302 adapter
= container_of(work
, struct ixgbe_adapter
, reset_task
);
3304 /* If we're already down or resetting, just bail */
3305 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
3306 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
3309 adapter
->tx_timeout_count
++;
3311 ixgbe_reinit_locked(adapter
);
3314 #ifdef CONFIG_IXGBE_DCB
3315 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter
*adapter
)
3318 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_DCB
];
3320 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
))
3324 adapter
->num_rx_queues
= f
->indices
;
3325 adapter
->num_tx_queues
= f
->indices
;
3333 * ixgbe_set_rss_queues: Allocate queues for RSS
3334 * @adapter: board private structure to initialize
3336 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3337 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3340 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter
*adapter
)
3343 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_RSS
];
3345 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3347 adapter
->num_rx_queues
= f
->indices
;
3348 adapter
->num_tx_queues
= f
->indices
;
3358 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3359 * @adapter: board private structure to initialize
3361 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3362 * to the original CPU that initiated the Tx session. This runs in addition
3363 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3364 * Rx load across CPUs using RSS.
3367 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter
*adapter
)
3370 struct ixgbe_ring_feature
*f_fdir
= &adapter
->ring_feature
[RING_F_FDIR
];
3372 f_fdir
->indices
= min((int)num_online_cpus(), f_fdir
->indices
);
3375 /* Flow Director must have RSS enabled */
3376 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
&&
3377 ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
3378 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)))) {
3379 adapter
->num_tx_queues
= f_fdir
->indices
;
3380 adapter
->num_rx_queues
= f_fdir
->indices
;
3383 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
3384 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
3391 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3392 * @adapter: board private structure to initialize
3394 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3395 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3396 * rx queues out of the max number of rx queues, instead, it is used as the
3397 * index of the first rx queue used by FCoE.
3400 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter
*adapter
)
3403 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
3405 f
->indices
= min((int)num_online_cpus(), f
->indices
);
3406 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
3407 adapter
->num_rx_queues
= 1;
3408 adapter
->num_tx_queues
= 1;
3409 #ifdef CONFIG_IXGBE_DCB
3410 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
3411 DPRINTK(PROBE
, INFO
, "FCoE enabled with DCB \n");
3412 ixgbe_set_dcb_queues(adapter
);
3415 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3416 DPRINTK(PROBE
, INFO
, "FCoE enabled with RSS \n");
3417 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
3418 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))
3419 ixgbe_set_fdir_queues(adapter
);
3421 ixgbe_set_rss_queues(adapter
);
3423 /* adding FCoE rx rings to the end */
3424 f
->mask
= adapter
->num_rx_queues
;
3425 adapter
->num_rx_queues
+= f
->indices
;
3426 adapter
->num_tx_queues
+= f
->indices
;
3434 #endif /* IXGBE_FCOE */
3436 * ixgbe_set_sriov_queues: Allocate queues for IOV use
3437 * @adapter: board private structure to initialize
3439 * IOV doesn't actually use anything, so just NAK the
3440 * request for now and let the other queue routines
3441 * figure out what to do.
3443 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter
*adapter
)
3449 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3450 * @adapter: board private structure to initialize
3452 * This is the top level queue allocation routine. The order here is very
3453 * important, starting with the "most" number of features turned on at once,
3454 * and ending with the smallest set of features. This way large combinations
3455 * can be allocated if they're turned on, and smaller combinations are the
3456 * fallthrough conditions.
3459 static void ixgbe_set_num_queues(struct ixgbe_adapter
*adapter
)
3461 /* Start with base case */
3462 adapter
->num_rx_queues
= 1;
3463 adapter
->num_tx_queues
= 1;
3464 adapter
->num_rx_pools
= adapter
->num_rx_queues
;
3465 adapter
->num_rx_queues_per_pool
= 1;
3467 if (ixgbe_set_sriov_queues(adapter
))
3471 if (ixgbe_set_fcoe_queues(adapter
))
3474 #endif /* IXGBE_FCOE */
3475 #ifdef CONFIG_IXGBE_DCB
3476 if (ixgbe_set_dcb_queues(adapter
))
3480 if (ixgbe_set_fdir_queues(adapter
))
3483 if (ixgbe_set_rss_queues(adapter
))
3486 /* fallback to base case */
3487 adapter
->num_rx_queues
= 1;
3488 adapter
->num_tx_queues
= 1;
3491 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3492 adapter
->netdev
->real_num_tx_queues
= adapter
->num_tx_queues
;
3495 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter
*adapter
,
3498 int err
, vector_threshold
;
3500 /* We'll want at least 3 (vector_threshold):
3503 * 3) Other (Link Status Change, etc.)
3504 * 4) TCP Timer (optional)
3506 vector_threshold
= MIN_MSIX_COUNT
;
3508 /* The more we get, the more we will assign to Tx/Rx Cleanup
3509 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3510 * Right now, we simply care about how many we'll get; we'll
3511 * set them up later while requesting irq's.
3513 while (vectors
>= vector_threshold
) {
3514 err
= pci_enable_msix(adapter
->pdev
, adapter
->msix_entries
,
3516 if (!err
) /* Success in acquiring all requested vectors. */
3519 vectors
= 0; /* Nasty failure, quit now */
3520 else /* err == number of vectors we should try again with */
3524 if (vectors
< vector_threshold
) {
3525 /* Can't allocate enough MSI-X interrupts? Oh well.
3526 * This just means we'll go with either a single MSI
3527 * vector or fall back to legacy interrupts.
3529 DPRINTK(HW
, DEBUG
, "Unable to allocate MSI-X interrupts\n");
3530 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
3531 kfree(adapter
->msix_entries
);
3532 adapter
->msix_entries
= NULL
;
3534 adapter
->flags
|= IXGBE_FLAG_MSIX_ENABLED
; /* Woot! */
3536 * Adjust for only the vectors we'll use, which is minimum
3537 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3538 * vectors we were allocated.
3540 adapter
->num_msix_vectors
= min(vectors
,
3541 adapter
->max_msix_q_vectors
+ NON_Q_VECTORS
);
3546 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3547 * @adapter: board private structure to initialize
3549 * Cache the descriptor ring offsets for RSS to the assigned rings.
3552 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter
*adapter
)
3557 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3558 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3559 adapter
->rx_ring
[i
].reg_idx
= i
;
3560 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3561 adapter
->tx_ring
[i
].reg_idx
= i
;
3570 #ifdef CONFIG_IXGBE_DCB
3572 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3573 * @adapter: board private structure to initialize
3575 * Cache the descriptor ring offsets for DCB to the assigned rings.
3578 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter
*adapter
)
3582 int dcb_i
= adapter
->ring_feature
[RING_F_DCB
].indices
;
3584 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
3585 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
3586 /* the number of queues is assumed to be symmetric */
3587 for (i
= 0; i
< dcb_i
; i
++) {
3588 adapter
->rx_ring
[i
].reg_idx
= i
<< 3;
3589 adapter
->tx_ring
[i
].reg_idx
= i
<< 2;
3592 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
3595 * Tx TC0 starts at: descriptor queue 0
3596 * Tx TC1 starts at: descriptor queue 32
3597 * Tx TC2 starts at: descriptor queue 64
3598 * Tx TC3 starts at: descriptor queue 80
3599 * Tx TC4 starts at: descriptor queue 96
3600 * Tx TC5 starts at: descriptor queue 104
3601 * Tx TC6 starts at: descriptor queue 112
3602 * Tx TC7 starts at: descriptor queue 120
3604 * Rx TC0-TC7 are offset by 16 queues each
3606 for (i
= 0; i
< 3; i
++) {
3607 adapter
->tx_ring
[i
].reg_idx
= i
<< 5;
3608 adapter
->rx_ring
[i
].reg_idx
= i
<< 4;
3610 for ( ; i
< 5; i
++) {
3611 adapter
->tx_ring
[i
].reg_idx
=
3613 adapter
->rx_ring
[i
].reg_idx
= i
<< 4;
3615 for ( ; i
< dcb_i
; i
++) {
3616 adapter
->tx_ring
[i
].reg_idx
=
3618 adapter
->rx_ring
[i
].reg_idx
= i
<< 4;
3622 } else if (dcb_i
== 4) {
3624 * Tx TC0 starts at: descriptor queue 0
3625 * Tx TC1 starts at: descriptor queue 64
3626 * Tx TC2 starts at: descriptor queue 96
3627 * Tx TC3 starts at: descriptor queue 112
3629 * Rx TC0-TC3 are offset by 32 queues each
3631 adapter
->tx_ring
[0].reg_idx
= 0;
3632 adapter
->tx_ring
[1].reg_idx
= 64;
3633 adapter
->tx_ring
[2].reg_idx
= 96;
3634 adapter
->tx_ring
[3].reg_idx
= 112;
3635 for (i
= 0 ; i
< dcb_i
; i
++)
3636 adapter
->rx_ring
[i
].reg_idx
= i
<< 5;
3654 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3655 * @adapter: board private structure to initialize
3657 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3660 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter
*adapter
)
3665 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
&&
3666 ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
3667 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))) {
3668 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3669 adapter
->rx_ring
[i
].reg_idx
= i
;
3670 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3671 adapter
->tx_ring
[i
].reg_idx
= i
;
3680 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3681 * @adapter: board private structure to initialize
3683 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3686 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter
*adapter
)
3688 int i
, fcoe_rx_i
= 0, fcoe_tx_i
= 0;
3690 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
3692 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
3693 #ifdef CONFIG_IXGBE_DCB
3694 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
3695 struct ixgbe_fcoe
*fcoe
= &adapter
->fcoe
;
3697 ixgbe_cache_ring_dcb(adapter
);
3698 /* find out queues in TC for FCoE */
3699 fcoe_rx_i
= adapter
->rx_ring
[fcoe
->tc
].reg_idx
+ 1;
3700 fcoe_tx_i
= adapter
->tx_ring
[fcoe
->tc
].reg_idx
+ 1;
3702 * In 82599, the number of Tx queues for each traffic
3703 * class for both 8-TC and 4-TC modes are:
3704 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3705 * 8 TCs: 32 32 16 16 8 8 8 8
3706 * 4 TCs: 64 64 32 32
3707 * We have max 8 queues for FCoE, where 8 the is
3708 * FCoE redirection table size. If TC for FCoE is
3709 * less than or equal to TC3, we have enough queues
3710 * to add max of 8 queues for FCoE, so we start FCoE
3711 * tx descriptor from the next one, i.e., reg_idx + 1.
3712 * If TC for FCoE is above TC3, implying 8 TC mode,
3713 * and we need 8 for FCoE, we have to take all queues
3714 * in that traffic class for FCoE.
3716 if ((f
->indices
== IXGBE_FCRETA_SIZE
) && (fcoe
->tc
> 3))
3719 #endif /* CONFIG_IXGBE_DCB */
3720 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3721 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
3722 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))
3723 ixgbe_cache_ring_fdir(adapter
);
3725 ixgbe_cache_ring_rss(adapter
);
3727 fcoe_rx_i
= f
->mask
;
3728 fcoe_tx_i
= f
->mask
;
3730 for (i
= 0; i
< f
->indices
; i
++, fcoe_rx_i
++, fcoe_tx_i
++) {
3731 adapter
->rx_ring
[f
->mask
+ i
].reg_idx
= fcoe_rx_i
;
3732 adapter
->tx_ring
[f
->mask
+ i
].reg_idx
= fcoe_tx_i
;
3739 #endif /* IXGBE_FCOE */
3741 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
3742 * @adapter: board private structure to initialize
3744 * SR-IOV doesn't use any descriptor rings but changes the default if
3745 * no other mapping is used.
3748 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter
*adapter
)
3750 adapter
->rx_ring
[0].reg_idx
= adapter
->num_vfs
* 2;
3751 adapter
->tx_ring
[0].reg_idx
= adapter
->num_vfs
* 2;
3752 if (adapter
->num_vfs
)
3759 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3760 * @adapter: board private structure to initialize
3762 * Once we know the feature-set enabled for the device, we'll cache
3763 * the register offset the descriptor ring is assigned to.
3765 * Note, the order the various feature calls is important. It must start with
3766 * the "most" features enabled at the same time, then trickle down to the
3767 * least amount of features turned on at once.
3769 static void ixgbe_cache_ring_register(struct ixgbe_adapter
*adapter
)
3771 /* start with default case */
3772 adapter
->rx_ring
[0].reg_idx
= 0;
3773 adapter
->tx_ring
[0].reg_idx
= 0;
3775 if (ixgbe_cache_ring_sriov(adapter
))
3779 if (ixgbe_cache_ring_fcoe(adapter
))
3782 #endif /* IXGBE_FCOE */
3783 #ifdef CONFIG_IXGBE_DCB
3784 if (ixgbe_cache_ring_dcb(adapter
))
3788 if (ixgbe_cache_ring_fdir(adapter
))
3791 if (ixgbe_cache_ring_rss(adapter
))
3796 * ixgbe_alloc_queues - Allocate memory for all rings
3797 * @adapter: board private structure to initialize
3799 * We allocate one ring per queue at run-time since we don't know the
3800 * number of queues at compile-time. The polling_netdev array is
3801 * intended for Multiqueue, but should work fine with a single queue.
3803 static int ixgbe_alloc_queues(struct ixgbe_adapter
*adapter
)
3807 adapter
->tx_ring
= kcalloc(adapter
->num_tx_queues
,
3808 sizeof(struct ixgbe_ring
), GFP_KERNEL
);
3809 if (!adapter
->tx_ring
)
3810 goto err_tx_ring_allocation
;
3812 adapter
->rx_ring
= kcalloc(adapter
->num_rx_queues
,
3813 sizeof(struct ixgbe_ring
), GFP_KERNEL
);
3814 if (!adapter
->rx_ring
)
3815 goto err_rx_ring_allocation
;
3817 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
3818 adapter
->tx_ring
[i
].count
= adapter
->tx_ring_count
;
3819 adapter
->tx_ring
[i
].queue_index
= i
;
3822 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3823 adapter
->rx_ring
[i
].count
= adapter
->rx_ring_count
;
3824 adapter
->rx_ring
[i
].queue_index
= i
;
3827 ixgbe_cache_ring_register(adapter
);
3831 err_rx_ring_allocation
:
3832 kfree(adapter
->tx_ring
);
3833 err_tx_ring_allocation
:
3838 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3839 * @adapter: board private structure to initialize
3841 * Attempt to configure the interrupts using the best available
3842 * capabilities of the hardware and the kernel.
3844 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter
*adapter
)
3846 struct ixgbe_hw
*hw
= &adapter
->hw
;
3848 int vector
, v_budget
;
3851 * It's easy to be greedy for MSI-X vectors, but it really
3852 * doesn't do us much good if we have a lot more vectors
3853 * than CPU's. So let's be conservative and only ask for
3854 * (roughly) the same number of vectors as there are CPU's.
3856 v_budget
= min(adapter
->num_rx_queues
+ adapter
->num_tx_queues
,
3857 (int)num_online_cpus()) + NON_Q_VECTORS
;
3860 * At the same time, hardware can only support a maximum of
3861 * hw.mac->max_msix_vectors vectors. With features
3862 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3863 * descriptor queues supported by our device. Thus, we cap it off in
3864 * those rare cases where the cpu count also exceeds our vector limit.
3866 v_budget
= min(v_budget
, (int)hw
->mac
.max_msix_vectors
);
3868 /* A failure in MSI-X entry allocation isn't fatal, but it does
3869 * mean we disable MSI-X capabilities of the adapter. */
3870 adapter
->msix_entries
= kcalloc(v_budget
,
3871 sizeof(struct msix_entry
), GFP_KERNEL
);
3872 if (adapter
->msix_entries
) {
3873 for (vector
= 0; vector
< v_budget
; vector
++)
3874 adapter
->msix_entries
[vector
].entry
= vector
;
3876 ixgbe_acquire_msix_vectors(adapter
, v_budget
);
3878 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
3882 adapter
->flags
&= ~IXGBE_FLAG_DCB_ENABLED
;
3883 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
3884 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
3885 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
3886 adapter
->atr_sample_rate
= 0;
3887 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
3888 ixgbe_disable_sriov(adapter
);
3890 ixgbe_set_num_queues(adapter
);
3892 err
= pci_enable_msi(adapter
->pdev
);
3894 adapter
->flags
|= IXGBE_FLAG_MSI_ENABLED
;
3896 DPRINTK(HW
, DEBUG
, "Unable to allocate MSI interrupt, "
3897 "falling back to legacy. Error: %d\n", err
);
3907 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3908 * @adapter: board private structure to initialize
3910 * We allocate one q_vector per queue interrupt. If allocation fails we
3913 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter
*adapter
)
3915 int q_idx
, num_q_vectors
;
3916 struct ixgbe_q_vector
*q_vector
;
3918 int (*poll
)(struct napi_struct
*, int);
3920 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3921 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3922 napi_vectors
= adapter
->num_rx_queues
;
3923 poll
= &ixgbe_clean_rxtx_many
;
3930 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
3931 q_vector
= kzalloc(sizeof(struct ixgbe_q_vector
), GFP_KERNEL
);
3934 q_vector
->adapter
= adapter
;
3935 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
3936 q_vector
->eitr
= adapter
->tx_eitr_param
;
3938 q_vector
->eitr
= adapter
->rx_eitr_param
;
3939 q_vector
->v_idx
= q_idx
;
3940 netif_napi_add(adapter
->netdev
, &q_vector
->napi
, (*poll
), 64);
3941 adapter
->q_vector
[q_idx
] = q_vector
;
3949 q_vector
= adapter
->q_vector
[q_idx
];
3950 netif_napi_del(&q_vector
->napi
);
3952 adapter
->q_vector
[q_idx
] = NULL
;
3958 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3959 * @adapter: board private structure to initialize
3961 * This function frees the memory allocated to the q_vectors. In addition if
3962 * NAPI is enabled it will delete any references to the NAPI struct prior
3963 * to freeing the q_vector.
3965 static void ixgbe_free_q_vectors(struct ixgbe_adapter
*adapter
)
3967 int q_idx
, num_q_vectors
;
3969 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
3970 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3974 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
3975 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[q_idx
];
3976 adapter
->q_vector
[q_idx
] = NULL
;
3977 netif_napi_del(&q_vector
->napi
);
3982 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter
*adapter
)
3984 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3985 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
3986 pci_disable_msix(adapter
->pdev
);
3987 kfree(adapter
->msix_entries
);
3988 adapter
->msix_entries
= NULL
;
3989 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
3990 adapter
->flags
&= ~IXGBE_FLAG_MSI_ENABLED
;
3991 pci_disable_msi(adapter
->pdev
);
3997 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3998 * @adapter: board private structure to initialize
4000 * We determine which interrupt scheme to use based on...
4001 * - Kernel support (MSI, MSI-X)
4002 * - which can be user-defined (via MODULE_PARAM)
4003 * - Hardware queue count (num_*_queues)
4004 * - defined by miscellaneous hardware support/features (RSS, etc.)
4006 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter
*adapter
)
4010 /* Number of supported queues */
4011 ixgbe_set_num_queues(adapter
);
4013 err
= ixgbe_set_interrupt_capability(adapter
);
4015 DPRINTK(PROBE
, ERR
, "Unable to setup interrupt capabilities\n");
4016 goto err_set_interrupt
;
4019 err
= ixgbe_alloc_q_vectors(adapter
);
4021 DPRINTK(PROBE
, ERR
, "Unable to allocate memory for queue "
4023 goto err_alloc_q_vectors
;
4026 err
= ixgbe_alloc_queues(adapter
);
4028 DPRINTK(PROBE
, ERR
, "Unable to allocate memory for queues\n");
4029 goto err_alloc_queues
;
4032 DPRINTK(DRV
, INFO
, "Multiqueue %s: Rx Queue count = %u, "
4033 "Tx Queue count = %u\n",
4034 (adapter
->num_rx_queues
> 1) ? "Enabled" :
4035 "Disabled", adapter
->num_rx_queues
, adapter
->num_tx_queues
);
4037 set_bit(__IXGBE_DOWN
, &adapter
->state
);
4042 ixgbe_free_q_vectors(adapter
);
4043 err_alloc_q_vectors
:
4044 ixgbe_reset_interrupt_capability(adapter
);
4050 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4051 * @adapter: board private structure to clear interrupt scheme on
4053 * We go through and clear interrupt specific resources and reset the structure
4054 * to pre-load conditions
4056 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter
*adapter
)
4058 kfree(adapter
->tx_ring
);
4059 kfree(adapter
->rx_ring
);
4060 adapter
->tx_ring
= NULL
;
4061 adapter
->rx_ring
= NULL
;
4063 ixgbe_free_q_vectors(adapter
);
4064 ixgbe_reset_interrupt_capability(adapter
);
4068 * ixgbe_sfp_timer - worker thread to find a missing module
4069 * @data: pointer to our adapter struct
4071 static void ixgbe_sfp_timer(unsigned long data
)
4073 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
4076 * Do the sfp_timer outside of interrupt context due to the
4077 * delays that sfp+ detection requires
4079 schedule_work(&adapter
->sfp_task
);
4083 * ixgbe_sfp_task - worker thread to find a missing module
4084 * @work: pointer to work_struct containing our data
4086 static void ixgbe_sfp_task(struct work_struct
*work
)
4088 struct ixgbe_adapter
*adapter
= container_of(work
,
4089 struct ixgbe_adapter
,
4091 struct ixgbe_hw
*hw
= &adapter
->hw
;
4093 if ((hw
->phy
.type
== ixgbe_phy_nl
) &&
4094 (hw
->phy
.sfp_type
== ixgbe_sfp_type_not_present
)) {
4095 s32 ret
= hw
->phy
.ops
.identify_sfp(hw
);
4096 if (ret
== IXGBE_ERR_SFP_NOT_PRESENT
)
4098 ret
= hw
->phy
.ops
.reset(hw
);
4099 if (ret
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
4100 dev_err(&adapter
->pdev
->dev
, "failed to initialize "
4101 "because an unsupported SFP+ module type "
4103 "Reload the driver after installing a "
4104 "supported module.\n");
4105 unregister_netdev(adapter
->netdev
);
4107 DPRINTK(PROBE
, INFO
, "detected SFP+: %d\n",
4110 /* don't need this routine any more */
4111 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
4115 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
))
4116 mod_timer(&adapter
->sfp_timer
,
4117 round_jiffies(jiffies
+ (2 * HZ
)));
4121 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4122 * @adapter: board private structure to initialize
4124 * ixgbe_sw_init initializes the Adapter private data structure.
4125 * Fields are initialized based on PCI device information and
4126 * OS network device settings (MTU size).
4128 static int __devinit
ixgbe_sw_init(struct ixgbe_adapter
*adapter
)
4130 struct ixgbe_hw
*hw
= &adapter
->hw
;
4131 struct pci_dev
*pdev
= adapter
->pdev
;
4133 #ifdef CONFIG_IXGBE_DCB
4135 struct tc_configuration
*tc
;
4138 /* PCI config space info */
4140 hw
->vendor_id
= pdev
->vendor
;
4141 hw
->device_id
= pdev
->device
;
4142 hw
->revision_id
= pdev
->revision
;
4143 hw
->subsystem_vendor_id
= pdev
->subsystem_vendor
;
4144 hw
->subsystem_device_id
= pdev
->subsystem_device
;
4146 /* Set capability flags */
4147 rss
= min(IXGBE_MAX_RSS_INDICES
, (int)num_online_cpus());
4148 adapter
->ring_feature
[RING_F_RSS
].indices
= rss
;
4149 adapter
->flags
|= IXGBE_FLAG_RSS_ENABLED
;
4150 adapter
->ring_feature
[RING_F_DCB
].indices
= IXGBE_MAX_DCB_INDICES
;
4151 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
4152 if (hw
->device_id
== IXGBE_DEV_ID_82598AT
)
4153 adapter
->flags
|= IXGBE_FLAG_FAN_FAIL_CAPABLE
;
4154 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82598
;
4155 } else if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
4156 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82599
;
4157 adapter
->flags2
|= IXGBE_FLAG2_RSC_CAPABLE
;
4158 adapter
->flags2
|= IXGBE_FLAG2_RSC_ENABLED
;
4159 adapter
->flags
|= IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4160 adapter
->ring_feature
[RING_F_FDIR
].indices
=
4161 IXGBE_MAX_FDIR_INDICES
;
4162 adapter
->atr_sample_rate
= 20;
4163 adapter
->fdir_pballoc
= 0;
4165 adapter
->flags
|= IXGBE_FLAG_FCOE_CAPABLE
;
4166 adapter
->flags
&= ~IXGBE_FLAG_FCOE_ENABLED
;
4167 adapter
->ring_feature
[RING_F_FCOE
].indices
= 0;
4168 #ifdef CONFIG_IXGBE_DCB
4169 /* Default traffic class to use for FCoE */
4170 adapter
->fcoe
.tc
= IXGBE_FCOE_DEFTC
;
4172 #endif /* IXGBE_FCOE */
4175 #ifdef CONFIG_IXGBE_DCB
4176 /* Configure DCB traffic classes */
4177 for (j
= 0; j
< MAX_TRAFFIC_CLASS
; j
++) {
4178 tc
= &adapter
->dcb_cfg
.tc_config
[j
];
4179 tc
->path
[DCB_TX_CONFIG
].bwg_id
= 0;
4180 tc
->path
[DCB_TX_CONFIG
].bwg_percent
= 12 + (j
& 1);
4181 tc
->path
[DCB_RX_CONFIG
].bwg_id
= 0;
4182 tc
->path
[DCB_RX_CONFIG
].bwg_percent
= 12 + (j
& 1);
4183 tc
->dcb_pfc
= pfc_disabled
;
4185 adapter
->dcb_cfg
.bw_percentage
[DCB_TX_CONFIG
][0] = 100;
4186 adapter
->dcb_cfg
.bw_percentage
[DCB_RX_CONFIG
][0] = 100;
4187 adapter
->dcb_cfg
.rx_pba_cfg
= pba_equal
;
4188 adapter
->dcb_cfg
.pfc_mode_enable
= false;
4189 adapter
->dcb_cfg
.round_robin_enable
= false;
4190 adapter
->dcb_set_bitmap
= 0x00;
4191 ixgbe_copy_dcb_cfg(&adapter
->dcb_cfg
, &adapter
->temp_dcb_cfg
,
4192 adapter
->ring_feature
[RING_F_DCB
].indices
);
4196 /* default flow control settings */
4197 hw
->fc
.requested_mode
= ixgbe_fc_full
;
4198 hw
->fc
.current_mode
= ixgbe_fc_full
; /* init for ethtool output */
4200 adapter
->last_lfc_mode
= hw
->fc
.current_mode
;
4202 hw
->fc
.high_water
= IXGBE_DEFAULT_FCRTH
;
4203 hw
->fc
.low_water
= IXGBE_DEFAULT_FCRTL
;
4204 hw
->fc
.pause_time
= IXGBE_DEFAULT_FCPAUSE
;
4205 hw
->fc
.send_xon
= true;
4206 hw
->fc
.disable_fc_autoneg
= false;
4208 /* enable itr by default in dynamic mode */
4209 adapter
->rx_itr_setting
= 1;
4210 adapter
->rx_eitr_param
= 20000;
4211 adapter
->tx_itr_setting
= 1;
4212 adapter
->tx_eitr_param
= 10000;
4214 /* set defaults for eitr in MegaBytes */
4215 adapter
->eitr_low
= 10;
4216 adapter
->eitr_high
= 20;
4218 /* set default ring sizes */
4219 adapter
->tx_ring_count
= IXGBE_DEFAULT_TXD
;
4220 adapter
->rx_ring_count
= IXGBE_DEFAULT_RXD
;
4222 /* initialize eeprom parameters */
4223 if (ixgbe_init_eeprom_params_generic(hw
)) {
4224 dev_err(&pdev
->dev
, "EEPROM initialization failed\n");
4228 /* enable rx csum by default */
4229 adapter
->flags
|= IXGBE_FLAG_RX_CSUM_ENABLED
;
4231 set_bit(__IXGBE_DOWN
, &adapter
->state
);
4237 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4238 * @adapter: board private structure
4239 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4241 * Return 0 on success, negative on failure
4243 int ixgbe_setup_tx_resources(struct ixgbe_adapter
*adapter
,
4244 struct ixgbe_ring
*tx_ring
)
4246 struct pci_dev
*pdev
= adapter
->pdev
;
4249 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
4250 tx_ring
->tx_buffer_info
= vmalloc(size
);
4251 if (!tx_ring
->tx_buffer_info
)
4253 memset(tx_ring
->tx_buffer_info
, 0, size
);
4255 /* round up to nearest 4K */
4256 tx_ring
->size
= tx_ring
->count
* sizeof(union ixgbe_adv_tx_desc
);
4257 tx_ring
->size
= ALIGN(tx_ring
->size
, 4096);
4259 tx_ring
->desc
= pci_alloc_consistent(pdev
, tx_ring
->size
,
4264 tx_ring
->next_to_use
= 0;
4265 tx_ring
->next_to_clean
= 0;
4266 tx_ring
->work_limit
= tx_ring
->count
;
4270 vfree(tx_ring
->tx_buffer_info
);
4271 tx_ring
->tx_buffer_info
= NULL
;
4272 DPRINTK(PROBE
, ERR
, "Unable to allocate memory for the transmit "
4273 "descriptor ring\n");
4278 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4279 * @adapter: board private structure
4281 * If this function returns with an error, then it's possible one or
4282 * more of the rings is populated (while the rest are not). It is the
4283 * callers duty to clean those orphaned rings.
4285 * Return 0 on success, negative on failure
4287 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter
*adapter
)
4291 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4292 err
= ixgbe_setup_tx_resources(adapter
, &adapter
->tx_ring
[i
]);
4295 DPRINTK(PROBE
, ERR
, "Allocation for Tx Queue %u failed\n", i
);
4303 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4304 * @adapter: board private structure
4305 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4307 * Returns 0 on success, negative on failure
4309 int ixgbe_setup_rx_resources(struct ixgbe_adapter
*adapter
,
4310 struct ixgbe_ring
*rx_ring
)
4312 struct pci_dev
*pdev
= adapter
->pdev
;
4315 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
4316 rx_ring
->rx_buffer_info
= vmalloc(size
);
4317 if (!rx_ring
->rx_buffer_info
) {
4319 "vmalloc allocation failed for the rx desc ring\n");
4322 memset(rx_ring
->rx_buffer_info
, 0, size
);
4324 /* Round up to nearest 4K */
4325 rx_ring
->size
= rx_ring
->count
* sizeof(union ixgbe_adv_rx_desc
);
4326 rx_ring
->size
= ALIGN(rx_ring
->size
, 4096);
4328 rx_ring
->desc
= pci_alloc_consistent(pdev
, rx_ring
->size
, &rx_ring
->dma
);
4330 if (!rx_ring
->desc
) {
4332 "Memory allocation failed for the rx desc ring\n");
4333 vfree(rx_ring
->rx_buffer_info
);
4337 rx_ring
->next_to_clean
= 0;
4338 rx_ring
->next_to_use
= 0;
4347 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4348 * @adapter: board private structure
4350 * If this function returns with an error, then it's possible one or
4351 * more of the rings is populated (while the rest are not). It is the
4352 * callers duty to clean those orphaned rings.
4354 * Return 0 on success, negative on failure
4357 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter
*adapter
)
4361 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
4362 err
= ixgbe_setup_rx_resources(adapter
, &adapter
->rx_ring
[i
]);
4365 DPRINTK(PROBE
, ERR
, "Allocation for Rx Queue %u failed\n", i
);
4373 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4374 * @adapter: board private structure
4375 * @tx_ring: Tx descriptor ring for a specific queue
4377 * Free all transmit software resources
4379 void ixgbe_free_tx_resources(struct ixgbe_adapter
*adapter
,
4380 struct ixgbe_ring
*tx_ring
)
4382 struct pci_dev
*pdev
= adapter
->pdev
;
4384 ixgbe_clean_tx_ring(adapter
, tx_ring
);
4386 vfree(tx_ring
->tx_buffer_info
);
4387 tx_ring
->tx_buffer_info
= NULL
;
4389 pci_free_consistent(pdev
, tx_ring
->size
, tx_ring
->desc
, tx_ring
->dma
);
4391 tx_ring
->desc
= NULL
;
4395 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4396 * @adapter: board private structure
4398 * Free all transmit software resources
4400 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter
*adapter
)
4404 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4405 if (adapter
->tx_ring
[i
].desc
)
4406 ixgbe_free_tx_resources(adapter
, &adapter
->tx_ring
[i
]);
4410 * ixgbe_free_rx_resources - Free Rx Resources
4411 * @adapter: board private structure
4412 * @rx_ring: ring to clean the resources from
4414 * Free all receive software resources
4416 void ixgbe_free_rx_resources(struct ixgbe_adapter
*adapter
,
4417 struct ixgbe_ring
*rx_ring
)
4419 struct pci_dev
*pdev
= adapter
->pdev
;
4421 ixgbe_clean_rx_ring(adapter
, rx_ring
);
4423 vfree(rx_ring
->rx_buffer_info
);
4424 rx_ring
->rx_buffer_info
= NULL
;
4426 pci_free_consistent(pdev
, rx_ring
->size
, rx_ring
->desc
, rx_ring
->dma
);
4428 rx_ring
->desc
= NULL
;
4432 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4433 * @adapter: board private structure
4435 * Free all receive software resources
4437 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter
*adapter
)
4441 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4442 if (adapter
->rx_ring
[i
].desc
)
4443 ixgbe_free_rx_resources(adapter
, &adapter
->rx_ring
[i
]);
4447 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4448 * @netdev: network interface device structure
4449 * @new_mtu: new value for maximum frame size
4451 * Returns 0 on success, negative on failure
4453 static int ixgbe_change_mtu(struct net_device
*netdev
, int new_mtu
)
4455 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4456 int max_frame
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
4458 /* MTU < 68 is an error and causes problems on some kernels */
4459 if ((new_mtu
< 68) || (max_frame
> IXGBE_MAX_JUMBO_FRAME_SIZE
))
4462 DPRINTK(PROBE
, INFO
, "changing MTU from %d to %d\n",
4463 netdev
->mtu
, new_mtu
);
4464 /* must set new MTU before calling down or up */
4465 netdev
->mtu
= new_mtu
;
4467 if (netif_running(netdev
))
4468 ixgbe_reinit_locked(adapter
);
4474 * ixgbe_open - Called when a network interface is made active
4475 * @netdev: network interface device structure
4477 * Returns 0 on success, negative value on failure
4479 * The open entry point is called when a network interface is made
4480 * active by the system (IFF_UP). At this point all resources needed
4481 * for transmit and receive operations are allocated, the interrupt
4482 * handler is registered with the OS, the watchdog timer is started,
4483 * and the stack is notified that the interface is ready.
4485 static int ixgbe_open(struct net_device
*netdev
)
4487 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4490 /* disallow open during test */
4491 if (test_bit(__IXGBE_TESTING
, &adapter
->state
))
4494 netif_carrier_off(netdev
);
4496 /* allocate transmit descriptors */
4497 err
= ixgbe_setup_all_tx_resources(adapter
);
4501 /* allocate receive descriptors */
4502 err
= ixgbe_setup_all_rx_resources(adapter
);
4506 ixgbe_configure(adapter
);
4508 err
= ixgbe_request_irq(adapter
);
4512 err
= ixgbe_up_complete(adapter
);
4516 netif_tx_start_all_queues(netdev
);
4521 ixgbe_release_hw_control(adapter
);
4522 ixgbe_free_irq(adapter
);
4525 ixgbe_free_all_rx_resources(adapter
);
4527 ixgbe_free_all_tx_resources(adapter
);
4528 ixgbe_reset(adapter
);
4534 * ixgbe_close - Disables a network interface
4535 * @netdev: network interface device structure
4537 * Returns 0, this is not allowed to fail
4539 * The close entry point is called when an interface is de-activated
4540 * by the OS. The hardware is still under the drivers control, but
4541 * needs to be disabled. A global MAC reset is issued to stop the
4542 * hardware, and all transmit and receive resources are freed.
4544 static int ixgbe_close(struct net_device
*netdev
)
4546 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4548 ixgbe_down(adapter
);
4549 ixgbe_free_irq(adapter
);
4551 ixgbe_free_all_tx_resources(adapter
);
4552 ixgbe_free_all_rx_resources(adapter
);
4554 ixgbe_release_hw_control(adapter
);
4560 static int ixgbe_resume(struct pci_dev
*pdev
)
4562 struct net_device
*netdev
= pci_get_drvdata(pdev
);
4563 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4566 pci_set_power_state(pdev
, PCI_D0
);
4567 pci_restore_state(pdev
);
4569 * pci_restore_state clears dev->state_saved so call
4570 * pci_save_state to restore it.
4572 pci_save_state(pdev
);
4574 err
= pci_enable_device_mem(pdev
);
4576 printk(KERN_ERR
"ixgbe: Cannot enable PCI device from "
4580 pci_set_master(pdev
);
4582 pci_wake_from_d3(pdev
, false);
4584 err
= ixgbe_init_interrupt_scheme(adapter
);
4586 printk(KERN_ERR
"ixgbe: Cannot initialize interrupts for "
4591 ixgbe_reset(adapter
);
4593 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
4595 if (netif_running(netdev
)) {
4596 err
= ixgbe_open(adapter
->netdev
);
4601 netif_device_attach(netdev
);
4605 #endif /* CONFIG_PM */
4607 static int __ixgbe_shutdown(struct pci_dev
*pdev
, bool *enable_wake
)
4609 struct net_device
*netdev
= pci_get_drvdata(pdev
);
4610 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4611 struct ixgbe_hw
*hw
= &adapter
->hw
;
4613 u32 wufc
= adapter
->wol
;
4618 netif_device_detach(netdev
);
4620 if (netif_running(netdev
)) {
4621 ixgbe_down(adapter
);
4622 ixgbe_free_irq(adapter
);
4623 ixgbe_free_all_tx_resources(adapter
);
4624 ixgbe_free_all_rx_resources(adapter
);
4626 ixgbe_clear_interrupt_scheme(adapter
);
4629 retval
= pci_save_state(pdev
);
4635 ixgbe_set_rx_mode(netdev
);
4637 /* turn on all-multi mode if wake on multicast is enabled */
4638 if (wufc
& IXGBE_WUFC_MC
) {
4639 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
4640 fctrl
|= IXGBE_FCTRL_MPE
;
4641 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
4644 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
4645 ctrl
|= IXGBE_CTRL_GIO_DIS
;
4646 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, ctrl
);
4648 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, wufc
);
4650 IXGBE_WRITE_REG(hw
, IXGBE_WUC
, 0);
4651 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, 0);
4654 if (wufc
&& hw
->mac
.type
== ixgbe_mac_82599EB
)
4655 pci_wake_from_d3(pdev
, true);
4657 pci_wake_from_d3(pdev
, false);
4659 *enable_wake
= !!wufc
;
4661 ixgbe_release_hw_control(adapter
);
4663 pci_disable_device(pdev
);
4669 static int ixgbe_suspend(struct pci_dev
*pdev
, pm_message_t state
)
4674 retval
= __ixgbe_shutdown(pdev
, &wake
);
4679 pci_prepare_to_sleep(pdev
);
4681 pci_wake_from_d3(pdev
, false);
4682 pci_set_power_state(pdev
, PCI_D3hot
);
4687 #endif /* CONFIG_PM */
4689 static void ixgbe_shutdown(struct pci_dev
*pdev
)
4693 __ixgbe_shutdown(pdev
, &wake
);
4695 if (system_state
== SYSTEM_POWER_OFF
) {
4696 pci_wake_from_d3(pdev
, wake
);
4697 pci_set_power_state(pdev
, PCI_D3hot
);
4702 * ixgbe_update_stats - Update the board statistics counters.
4703 * @adapter: board private structure
4705 void ixgbe_update_stats(struct ixgbe_adapter
*adapter
)
4707 struct net_device
*netdev
= adapter
->netdev
;
4708 struct ixgbe_hw
*hw
= &adapter
->hw
;
4710 u32 i
, missed_rx
= 0, mpc
, bprc
, lxon
, lxoff
, xon_off_tot
;
4711 u64 non_eop_descs
= 0, restart_queue
= 0;
4713 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
4716 for (i
= 0; i
< 16; i
++)
4717 adapter
->hw_rx_no_dma_resources
+=
4718 IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
4719 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
4720 rsc_count
+= adapter
->rx_ring
[i
].rsc_count
;
4721 rsc_flush
+= adapter
->rx_ring
[i
].rsc_flush
;
4723 adapter
->rsc_total_count
= rsc_count
;
4724 adapter
->rsc_total_flush
= rsc_flush
;
4727 /* gather some stats to the adapter struct that are per queue */
4728 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4729 restart_queue
+= adapter
->tx_ring
[i
].restart_queue
;
4730 adapter
->restart_queue
= restart_queue
;
4732 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4733 non_eop_descs
+= adapter
->rx_ring
[i
].non_eop_descs
;
4734 adapter
->non_eop_descs
= non_eop_descs
;
4736 adapter
->stats
.crcerrs
+= IXGBE_READ_REG(hw
, IXGBE_CRCERRS
);
4737 for (i
= 0; i
< 8; i
++) {
4738 /* for packet buffers not used, the register should read 0 */
4739 mpc
= IXGBE_READ_REG(hw
, IXGBE_MPC(i
));
4741 adapter
->stats
.mpc
[i
] += mpc
;
4742 total_mpc
+= adapter
->stats
.mpc
[i
];
4743 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
4744 adapter
->stats
.rnbc
[i
] += IXGBE_READ_REG(hw
, IXGBE_RNBC(i
));
4745 adapter
->stats
.qptc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPTC(i
));
4746 adapter
->stats
.qbtc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBTC(i
));
4747 adapter
->stats
.qprc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRC(i
));
4748 adapter
->stats
.qbrc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBRC(i
));
4749 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
4750 adapter
->stats
.pxonrxc
[i
] += IXGBE_READ_REG(hw
,
4751 IXGBE_PXONRXCNT(i
));
4752 adapter
->stats
.pxoffrxc
[i
] += IXGBE_READ_REG(hw
,
4753 IXGBE_PXOFFRXCNT(i
));
4754 adapter
->stats
.qprdc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
4756 adapter
->stats
.pxonrxc
[i
] += IXGBE_READ_REG(hw
,
4758 adapter
->stats
.pxoffrxc
[i
] += IXGBE_READ_REG(hw
,
4761 adapter
->stats
.pxontxc
[i
] += IXGBE_READ_REG(hw
,
4763 adapter
->stats
.pxofftxc
[i
] += IXGBE_READ_REG(hw
,
4766 adapter
->stats
.gprc
+= IXGBE_READ_REG(hw
, IXGBE_GPRC
);
4767 /* work around hardware counting issue */
4768 adapter
->stats
.gprc
-= missed_rx
;
4770 /* 82598 hardware only has a 32 bit counter in the high register */
4771 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
4773 adapter
->stats
.gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCL
);
4774 tmp
= IXGBE_READ_REG(hw
, IXGBE_GORCH
) & 0xF; /* 4 high bits of GORC */
4775 adapter
->stats
.gorc
+= (tmp
<< 32);
4776 adapter
->stats
.gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCL
);
4777 tmp
= IXGBE_READ_REG(hw
, IXGBE_GOTCH
) & 0xF; /* 4 high bits of GOTC */
4778 adapter
->stats
.gotc
+= (tmp
<< 32);
4779 adapter
->stats
.tor
+= IXGBE_READ_REG(hw
, IXGBE_TORL
);
4780 IXGBE_READ_REG(hw
, IXGBE_TORH
); /* to clear */
4781 adapter
->stats
.lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXCNT
);
4782 adapter
->stats
.lxoffrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXCNT
);
4783 adapter
->stats
.fdirmatch
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMATCH
);
4784 adapter
->stats
.fdirmiss
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMISS
);
4786 adapter
->stats
.fccrc
+= IXGBE_READ_REG(hw
, IXGBE_FCCRC
);
4787 adapter
->stats
.fcoerpdc
+= IXGBE_READ_REG(hw
, IXGBE_FCOERPDC
);
4788 adapter
->stats
.fcoeprc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPRC
);
4789 adapter
->stats
.fcoeptc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPTC
);
4790 adapter
->stats
.fcoedwrc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWRC
);
4791 adapter
->stats
.fcoedwtc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWTC
);
4792 #endif /* IXGBE_FCOE */
4794 adapter
->stats
.lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXC
);
4795 adapter
->stats
.lxoffrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXC
);
4796 adapter
->stats
.gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCH
);
4797 adapter
->stats
.gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCH
);
4798 adapter
->stats
.tor
+= IXGBE_READ_REG(hw
, IXGBE_TORH
);
4800 bprc
= IXGBE_READ_REG(hw
, IXGBE_BPRC
);
4801 adapter
->stats
.bprc
+= bprc
;
4802 adapter
->stats
.mprc
+= IXGBE_READ_REG(hw
, IXGBE_MPRC
);
4803 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
4804 adapter
->stats
.mprc
-= bprc
;
4805 adapter
->stats
.roc
+= IXGBE_READ_REG(hw
, IXGBE_ROC
);
4806 adapter
->stats
.prc64
+= IXGBE_READ_REG(hw
, IXGBE_PRC64
);
4807 adapter
->stats
.prc127
+= IXGBE_READ_REG(hw
, IXGBE_PRC127
);
4808 adapter
->stats
.prc255
+= IXGBE_READ_REG(hw
, IXGBE_PRC255
);
4809 adapter
->stats
.prc511
+= IXGBE_READ_REG(hw
, IXGBE_PRC511
);
4810 adapter
->stats
.prc1023
+= IXGBE_READ_REG(hw
, IXGBE_PRC1023
);
4811 adapter
->stats
.prc1522
+= IXGBE_READ_REG(hw
, IXGBE_PRC1522
);
4812 adapter
->stats
.rlec
+= IXGBE_READ_REG(hw
, IXGBE_RLEC
);
4813 lxon
= IXGBE_READ_REG(hw
, IXGBE_LXONTXC
);
4814 adapter
->stats
.lxontxc
+= lxon
;
4815 lxoff
= IXGBE_READ_REG(hw
, IXGBE_LXOFFTXC
);
4816 adapter
->stats
.lxofftxc
+= lxoff
;
4817 adapter
->stats
.ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
4818 adapter
->stats
.gptc
+= IXGBE_READ_REG(hw
, IXGBE_GPTC
);
4819 adapter
->stats
.mptc
+= IXGBE_READ_REG(hw
, IXGBE_MPTC
);
4821 * 82598 errata - tx of flow control packets is included in tx counters
4823 xon_off_tot
= lxon
+ lxoff
;
4824 adapter
->stats
.gptc
-= xon_off_tot
;
4825 adapter
->stats
.mptc
-= xon_off_tot
;
4826 adapter
->stats
.gotc
-= (xon_off_tot
* (ETH_ZLEN
+ ETH_FCS_LEN
));
4827 adapter
->stats
.ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
4828 adapter
->stats
.rfc
+= IXGBE_READ_REG(hw
, IXGBE_RFC
);
4829 adapter
->stats
.rjc
+= IXGBE_READ_REG(hw
, IXGBE_RJC
);
4830 adapter
->stats
.tpr
+= IXGBE_READ_REG(hw
, IXGBE_TPR
);
4831 adapter
->stats
.ptc64
+= IXGBE_READ_REG(hw
, IXGBE_PTC64
);
4832 adapter
->stats
.ptc64
-= xon_off_tot
;
4833 adapter
->stats
.ptc127
+= IXGBE_READ_REG(hw
, IXGBE_PTC127
);
4834 adapter
->stats
.ptc255
+= IXGBE_READ_REG(hw
, IXGBE_PTC255
);
4835 adapter
->stats
.ptc511
+= IXGBE_READ_REG(hw
, IXGBE_PTC511
);
4836 adapter
->stats
.ptc1023
+= IXGBE_READ_REG(hw
, IXGBE_PTC1023
);
4837 adapter
->stats
.ptc1522
+= IXGBE_READ_REG(hw
, IXGBE_PTC1522
);
4838 adapter
->stats
.bptc
+= IXGBE_READ_REG(hw
, IXGBE_BPTC
);
4840 /* Fill out the OS statistics structure */
4841 netdev
->stats
.multicast
= adapter
->stats
.mprc
;
4844 netdev
->stats
.rx_errors
= adapter
->stats
.crcerrs
+
4845 adapter
->stats
.rlec
;
4846 netdev
->stats
.rx_dropped
= 0;
4847 netdev
->stats
.rx_length_errors
= adapter
->stats
.rlec
;
4848 netdev
->stats
.rx_crc_errors
= adapter
->stats
.crcerrs
;
4849 netdev
->stats
.rx_missed_errors
= total_mpc
;
4853 * ixgbe_watchdog - Timer Call-back
4854 * @data: pointer to adapter cast into an unsigned long
4856 static void ixgbe_watchdog(unsigned long data
)
4858 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
4859 struct ixgbe_hw
*hw
= &adapter
->hw
;
4864 * Do the watchdog outside of interrupt context due to the lovely
4865 * delays that some of the newer hardware requires
4868 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
4869 goto watchdog_short_circuit
;
4871 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)) {
4873 * for legacy and MSI interrupts don't set any bits
4874 * that are enabled for EIAM, because this operation
4875 * would set *both* EIMS and EICS for any bit in EIAM
4877 IXGBE_WRITE_REG(hw
, IXGBE_EICS
,
4878 (IXGBE_EICS_TCP_TIMER
| IXGBE_EICS_OTHER
));
4879 goto watchdog_reschedule
;
4882 /* get one bit for every active tx/rx interrupt vector */
4883 for (i
= 0; i
< adapter
->num_msix_vectors
- NON_Q_VECTORS
; i
++) {
4884 struct ixgbe_q_vector
*qv
= adapter
->q_vector
[i
];
4885 if (qv
->rxr_count
|| qv
->txr_count
)
4886 eics
|= ((u64
)1 << i
);
4889 /* Cause software interrupt to ensure rx rings are cleaned */
4890 ixgbe_irq_rearm_queues(adapter
, eics
);
4892 watchdog_reschedule
:
4893 /* Reset the timer */
4894 mod_timer(&adapter
->watchdog_timer
, round_jiffies(jiffies
+ 2 * HZ
));
4896 watchdog_short_circuit
:
4897 schedule_work(&adapter
->watchdog_task
);
4901 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4902 * @work: pointer to work_struct containing our data
4904 static void ixgbe_multispeed_fiber_task(struct work_struct
*work
)
4906 struct ixgbe_adapter
*adapter
= container_of(work
,
4907 struct ixgbe_adapter
,
4908 multispeed_fiber_task
);
4909 struct ixgbe_hw
*hw
= &adapter
->hw
;
4913 adapter
->flags
|= IXGBE_FLAG_IN_SFP_LINK_TASK
;
4914 autoneg
= hw
->phy
.autoneg_advertised
;
4915 if ((!autoneg
) && (hw
->mac
.ops
.get_link_capabilities
))
4916 hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
, &negotiation
);
4917 if (hw
->mac
.ops
.setup_link
)
4918 hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, true);
4919 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
4920 adapter
->flags
&= ~IXGBE_FLAG_IN_SFP_LINK_TASK
;
4924 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4925 * @work: pointer to work_struct containing our data
4927 static void ixgbe_sfp_config_module_task(struct work_struct
*work
)
4929 struct ixgbe_adapter
*adapter
= container_of(work
,
4930 struct ixgbe_adapter
,
4931 sfp_config_module_task
);
4932 struct ixgbe_hw
*hw
= &adapter
->hw
;
4935 adapter
->flags
|= IXGBE_FLAG_IN_SFP_MOD_TASK
;
4937 /* Time for electrical oscillations to settle down */
4939 err
= hw
->phy
.ops
.identify_sfp(hw
);
4941 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
4942 dev_err(&adapter
->pdev
->dev
, "failed to initialize because "
4943 "an unsupported SFP+ module type was detected.\n"
4944 "Reload the driver after installing a supported "
4946 unregister_netdev(adapter
->netdev
);
4949 hw
->mac
.ops
.setup_sfp(hw
);
4951 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_LINK_TASK
))
4952 /* This will also work for DA Twinax connections */
4953 schedule_work(&adapter
->multispeed_fiber_task
);
4954 adapter
->flags
&= ~IXGBE_FLAG_IN_SFP_MOD_TASK
;
4958 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4959 * @work: pointer to work_struct containing our data
4961 static void ixgbe_fdir_reinit_task(struct work_struct
*work
)
4963 struct ixgbe_adapter
*adapter
= container_of(work
,
4964 struct ixgbe_adapter
,
4966 struct ixgbe_hw
*hw
= &adapter
->hw
;
4969 if (ixgbe_reinit_fdir_tables_82599(hw
) == 0) {
4970 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4971 set_bit(__IXGBE_FDIR_INIT_DONE
,
4972 &(adapter
->tx_ring
[i
].reinit_state
));
4974 DPRINTK(PROBE
, ERR
, "failed to finish FDIR re-initialization, "
4975 "ignored adding FDIR ATR filters \n");
4977 /* Done FDIR Re-initialization, enable transmits */
4978 netif_tx_start_all_queues(adapter
->netdev
);
4982 * ixgbe_watchdog_task - worker thread to bring link up
4983 * @work: pointer to work_struct containing our data
4985 static void ixgbe_watchdog_task(struct work_struct
*work
)
4987 struct ixgbe_adapter
*adapter
= container_of(work
,
4988 struct ixgbe_adapter
,
4990 struct net_device
*netdev
= adapter
->netdev
;
4991 struct ixgbe_hw
*hw
= &adapter
->hw
;
4992 u32 link_speed
= adapter
->link_speed
;
4993 bool link_up
= adapter
->link_up
;
4995 struct ixgbe_ring
*tx_ring
;
4996 int some_tx_pending
= 0;
4998 adapter
->flags
|= IXGBE_FLAG_IN_WATCHDOG_TASK
;
5000 if (adapter
->flags
& IXGBE_FLAG_NEED_LINK_UPDATE
) {
5001 hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
, false);
5004 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
5005 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++)
5006 hw
->mac
.ops
.fc_enable(hw
, i
);
5008 hw
->mac
.ops
.fc_enable(hw
, 0);
5011 hw
->mac
.ops
.fc_enable(hw
, 0);
5016 time_after(jiffies
, (adapter
->link_check_timeout
+
5017 IXGBE_TRY_LINK_TIMEOUT
))) {
5018 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_UPDATE
;
5019 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMC_LSC
);
5021 adapter
->link_up
= link_up
;
5022 adapter
->link_speed
= link_speed
;
5026 if (!netif_carrier_ok(netdev
)) {
5027 bool flow_rx
, flow_tx
;
5029 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
5030 u32 mflcn
= IXGBE_READ_REG(hw
, IXGBE_MFLCN
);
5031 u32 fccfg
= IXGBE_READ_REG(hw
, IXGBE_FCCFG
);
5032 flow_rx
= !!(mflcn
& IXGBE_MFLCN_RFCE
);
5033 flow_tx
= !!(fccfg
& IXGBE_FCCFG_TFCE_802_3X
);
5035 u32 frctl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
5036 u32 rmcs
= IXGBE_READ_REG(hw
, IXGBE_RMCS
);
5037 flow_rx
= !!(frctl
& IXGBE_FCTRL_RFCE
);
5038 flow_tx
= !!(rmcs
& IXGBE_RMCS_TFCE_802_3X
);
5041 printk(KERN_INFO
"ixgbe: %s NIC Link is Up %s, "
5042 "Flow Control: %s\n",
5044 (link_speed
== IXGBE_LINK_SPEED_10GB_FULL
?
5046 (link_speed
== IXGBE_LINK_SPEED_1GB_FULL
?
5047 "1 Gbps" : "unknown speed")),
5048 ((flow_rx
&& flow_tx
) ? "RX/TX" :
5050 (flow_tx
? "TX" : "None"))));
5052 netif_carrier_on(netdev
);
5054 /* Force detection of hung controller */
5055 adapter
->detect_tx_hung
= true;
5058 adapter
->link_up
= false;
5059 adapter
->link_speed
= 0;
5060 if (netif_carrier_ok(netdev
)) {
5061 printk(KERN_INFO
"ixgbe: %s NIC Link is Down\n",
5063 netif_carrier_off(netdev
);
5067 if (!netif_carrier_ok(netdev
)) {
5068 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5069 tx_ring
= &adapter
->tx_ring
[i
];
5070 if (tx_ring
->next_to_use
!= tx_ring
->next_to_clean
) {
5071 some_tx_pending
= 1;
5076 if (some_tx_pending
) {
5077 /* We've lost link, so the controller stops DMA,
5078 * but we've got queued Tx work that's never going
5079 * to get done, so reset controller to flush Tx.
5080 * (Do the reset outside of interrupt context).
5082 schedule_work(&adapter
->reset_task
);
5086 ixgbe_update_stats(adapter
);
5087 adapter
->flags
&= ~IXGBE_FLAG_IN_WATCHDOG_TASK
;
5090 static int ixgbe_tso(struct ixgbe_adapter
*adapter
,
5091 struct ixgbe_ring
*tx_ring
, struct sk_buff
*skb
,
5092 u32 tx_flags
, u8
*hdr_len
)
5094 struct ixgbe_adv_tx_context_desc
*context_desc
;
5097 struct ixgbe_tx_buffer
*tx_buffer_info
;
5098 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
;
5099 u32 mss_l4len_idx
, l4len
;
5101 if (skb_is_gso(skb
)) {
5102 if (skb_header_cloned(skb
)) {
5103 err
= pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
);
5107 l4len
= tcp_hdrlen(skb
);
5110 if (skb
->protocol
== htons(ETH_P_IP
)) {
5111 struct iphdr
*iph
= ip_hdr(skb
);
5114 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
5118 } else if (skb_shinfo(skb
)->gso_type
== SKB_GSO_TCPV6
) {
5119 ipv6_hdr(skb
)->payload_len
= 0;
5120 tcp_hdr(skb
)->check
=
5121 ~csum_ipv6_magic(&ipv6_hdr(skb
)->saddr
,
5122 &ipv6_hdr(skb
)->daddr
,
5126 i
= tx_ring
->next_to_use
;
5128 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5129 context_desc
= IXGBE_TX_CTXTDESC_ADV(*tx_ring
, i
);
5131 /* VLAN MACLEN IPLEN */
5132 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
5134 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
5135 vlan_macip_lens
|= ((skb_network_offset(skb
)) <<
5136 IXGBE_ADVTXD_MACLEN_SHIFT
);
5137 *hdr_len
+= skb_network_offset(skb
);
5139 (skb_transport_header(skb
) - skb_network_header(skb
));
5141 (skb_transport_header(skb
) - skb_network_header(skb
));
5142 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
5143 context_desc
->seqnum_seed
= 0;
5145 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5146 type_tucmd_mlhl
= (IXGBE_TXD_CMD_DEXT
|
5147 IXGBE_ADVTXD_DTYP_CTXT
);
5149 if (skb
->protocol
== htons(ETH_P_IP
))
5150 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_IPV4
;
5151 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
5152 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
5156 (skb_shinfo(skb
)->gso_size
<< IXGBE_ADVTXD_MSS_SHIFT
);
5157 mss_l4len_idx
|= (l4len
<< IXGBE_ADVTXD_L4LEN_SHIFT
);
5158 /* use index 1 for TSO */
5159 mss_l4len_idx
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
5160 context_desc
->mss_l4len_idx
= cpu_to_le32(mss_l4len_idx
);
5162 tx_buffer_info
->time_stamp
= jiffies
;
5163 tx_buffer_info
->next_to_watch
= i
;
5166 if (i
== tx_ring
->count
)
5168 tx_ring
->next_to_use
= i
;
5175 static bool ixgbe_tx_csum(struct ixgbe_adapter
*adapter
,
5176 struct ixgbe_ring
*tx_ring
,
5177 struct sk_buff
*skb
, u32 tx_flags
)
5179 struct ixgbe_adv_tx_context_desc
*context_desc
;
5181 struct ixgbe_tx_buffer
*tx_buffer_info
;
5182 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
= 0;
5184 if (skb
->ip_summed
== CHECKSUM_PARTIAL
||
5185 (tx_flags
& IXGBE_TX_FLAGS_VLAN
)) {
5186 i
= tx_ring
->next_to_use
;
5187 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5188 context_desc
= IXGBE_TX_CTXTDESC_ADV(*tx_ring
, i
);
5190 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
5192 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
5193 vlan_macip_lens
|= (skb_network_offset(skb
) <<
5194 IXGBE_ADVTXD_MACLEN_SHIFT
);
5195 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
5196 vlan_macip_lens
|= (skb_transport_header(skb
) -
5197 skb_network_header(skb
));
5199 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
5200 context_desc
->seqnum_seed
= 0;
5202 type_tucmd_mlhl
|= (IXGBE_TXD_CMD_DEXT
|
5203 IXGBE_ADVTXD_DTYP_CTXT
);
5205 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5208 if (skb
->protocol
== cpu_to_be16(ETH_P_8021Q
)) {
5209 const struct vlan_ethhdr
*vhdr
=
5210 (const struct vlan_ethhdr
*)skb
->data
;
5212 protocol
= vhdr
->h_vlan_encapsulated_proto
;
5214 protocol
= skb
->protocol
;
5218 case cpu_to_be16(ETH_P_IP
):
5219 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_IPV4
;
5220 if (ip_hdr(skb
)->protocol
== IPPROTO_TCP
)
5222 IXGBE_ADVTXD_TUCMD_L4T_TCP
;
5223 else if (ip_hdr(skb
)->protocol
== IPPROTO_SCTP
)
5225 IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
5227 case cpu_to_be16(ETH_P_IPV6
):
5228 /* XXX what about other V6 headers?? */
5229 if (ipv6_hdr(skb
)->nexthdr
== IPPROTO_TCP
)
5231 IXGBE_ADVTXD_TUCMD_L4T_TCP
;
5232 else if (ipv6_hdr(skb
)->nexthdr
== IPPROTO_SCTP
)
5234 IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
5237 if (unlikely(net_ratelimit())) {
5238 DPRINTK(PROBE
, WARNING
,
5239 "partial checksum but proto=%x!\n",
5246 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
5247 /* use index zero for tx checksum offload */
5248 context_desc
->mss_l4len_idx
= 0;
5250 tx_buffer_info
->time_stamp
= jiffies
;
5251 tx_buffer_info
->next_to_watch
= i
;
5254 if (i
== tx_ring
->count
)
5256 tx_ring
->next_to_use
= i
;
5264 static int ixgbe_tx_map(struct ixgbe_adapter
*adapter
,
5265 struct ixgbe_ring
*tx_ring
,
5266 struct sk_buff
*skb
, u32 tx_flags
,
5269 struct pci_dev
*pdev
= adapter
->pdev
;
5270 struct ixgbe_tx_buffer
*tx_buffer_info
;
5272 unsigned int total
= skb
->len
;
5273 unsigned int offset
= 0, size
, count
= 0, i
;
5274 unsigned int nr_frags
= skb_shinfo(skb
)->nr_frags
;
5277 i
= tx_ring
->next_to_use
;
5279 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
)
5280 /* excluding fcoe_crc_eof for FCoE */
5281 total
-= sizeof(struct fcoe_crc_eof
);
5283 len
= min(skb_headlen(skb
), total
);
5285 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5286 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
5288 tx_buffer_info
->length
= size
;
5289 tx_buffer_info
->mapped_as_page
= false;
5290 tx_buffer_info
->dma
= pci_map_single(pdev
,
5292 size
, PCI_DMA_TODEVICE
);
5293 if (pci_dma_mapping_error(pdev
, tx_buffer_info
->dma
))
5295 tx_buffer_info
->time_stamp
= jiffies
;
5296 tx_buffer_info
->next_to_watch
= i
;
5305 if (i
== tx_ring
->count
)
5310 for (f
= 0; f
< nr_frags
; f
++) {
5311 struct skb_frag_struct
*frag
;
5313 frag
= &skb_shinfo(skb
)->frags
[f
];
5314 len
= min((unsigned int)frag
->size
, total
);
5315 offset
= frag
->page_offset
;
5319 if (i
== tx_ring
->count
)
5322 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5323 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
5325 tx_buffer_info
->length
= size
;
5326 tx_buffer_info
->dma
= pci_map_page(adapter
->pdev
,
5330 tx_buffer_info
->mapped_as_page
= true;
5331 if (pci_dma_mapping_error(pdev
, tx_buffer_info
->dma
))
5333 tx_buffer_info
->time_stamp
= jiffies
;
5334 tx_buffer_info
->next_to_watch
= i
;
5345 tx_ring
->tx_buffer_info
[i
].skb
= skb
;
5346 tx_ring
->tx_buffer_info
[first
].next_to_watch
= i
;
5351 dev_err(&pdev
->dev
, "TX DMA map failed\n");
5353 /* clear timestamp and dma mappings for failed tx_buffer_info map */
5354 tx_buffer_info
->dma
= 0;
5355 tx_buffer_info
->time_stamp
= 0;
5356 tx_buffer_info
->next_to_watch
= 0;
5360 /* clear timestamp and dma mappings for remaining portion of packet */
5363 i
+= tx_ring
->count
;
5365 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5366 ixgbe_unmap_and_free_tx_resource(adapter
, tx_buffer_info
);
5372 static void ixgbe_tx_queue(struct ixgbe_adapter
*adapter
,
5373 struct ixgbe_ring
*tx_ring
,
5374 int tx_flags
, int count
, u32 paylen
, u8 hdr_len
)
5376 union ixgbe_adv_tx_desc
*tx_desc
= NULL
;
5377 struct ixgbe_tx_buffer
*tx_buffer_info
;
5378 u32 olinfo_status
= 0, cmd_type_len
= 0;
5380 u32 txd_cmd
= IXGBE_TXD_CMD_EOP
| IXGBE_TXD_CMD_RS
| IXGBE_TXD_CMD_IFCS
;
5382 cmd_type_len
|= IXGBE_ADVTXD_DTYP_DATA
;
5384 cmd_type_len
|= IXGBE_ADVTXD_DCMD_IFCS
| IXGBE_ADVTXD_DCMD_DEXT
;
5386 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
5387 cmd_type_len
|= IXGBE_ADVTXD_DCMD_VLE
;
5389 if (tx_flags
& IXGBE_TX_FLAGS_TSO
) {
5390 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
5392 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
5393 IXGBE_ADVTXD_POPTS_SHIFT
;
5395 /* use index 1 context for tso */
5396 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
5397 if (tx_flags
& IXGBE_TX_FLAGS_IPV4
)
5398 olinfo_status
|= IXGBE_TXD_POPTS_IXSM
<<
5399 IXGBE_ADVTXD_POPTS_SHIFT
;
5401 } else if (tx_flags
& IXGBE_TX_FLAGS_CSUM
)
5402 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
5403 IXGBE_ADVTXD_POPTS_SHIFT
;
5405 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
5406 olinfo_status
|= IXGBE_ADVTXD_CC
;
5407 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
5408 if (tx_flags
& IXGBE_TX_FLAGS_FSO
)
5409 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
5412 olinfo_status
|= ((paylen
- hdr_len
) << IXGBE_ADVTXD_PAYLEN_SHIFT
);
5414 i
= tx_ring
->next_to_use
;
5416 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5417 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, i
);
5418 tx_desc
->read
.buffer_addr
= cpu_to_le64(tx_buffer_info
->dma
);
5419 tx_desc
->read
.cmd_type_len
=
5420 cpu_to_le32(cmd_type_len
| tx_buffer_info
->length
);
5421 tx_desc
->read
.olinfo_status
= cpu_to_le32(olinfo_status
);
5423 if (i
== tx_ring
->count
)
5427 tx_desc
->read
.cmd_type_len
|= cpu_to_le32(txd_cmd
);
5430 * Force memory writes to complete before letting h/w
5431 * know there are new descriptors to fetch. (Only
5432 * applicable for weak-ordered memory model archs,
5437 tx_ring
->next_to_use
= i
;
5438 writel(i
, adapter
->hw
.hw_addr
+ tx_ring
->tail
);
5441 static void ixgbe_atr(struct ixgbe_adapter
*adapter
, struct sk_buff
*skb
,
5442 int queue
, u32 tx_flags
)
5444 /* Right now, we support IPv4 only */
5445 struct ixgbe_atr_input atr_input
;
5447 struct iphdr
*iph
= ip_hdr(skb
);
5448 struct ethhdr
*eth
= (struct ethhdr
*)skb
->data
;
5449 u16 vlan_id
, src_port
, dst_port
, flex_bytes
;
5450 u32 src_ipv4_addr
, dst_ipv4_addr
;
5453 /* check if we're UDP or TCP */
5454 if (iph
->protocol
== IPPROTO_TCP
) {
5456 src_port
= th
->source
;
5457 dst_port
= th
->dest
;
5458 l4type
|= IXGBE_ATR_L4TYPE_TCP
;
5459 /* l4type IPv4 type is 0, no need to assign */
5461 /* Unsupported L4 header, just bail here */
5465 memset(&atr_input
, 0, sizeof(struct ixgbe_atr_input
));
5467 vlan_id
= (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
) >>
5468 IXGBE_TX_FLAGS_VLAN_SHIFT
;
5469 src_ipv4_addr
= iph
->saddr
;
5470 dst_ipv4_addr
= iph
->daddr
;
5471 flex_bytes
= eth
->h_proto
;
5473 ixgbe_atr_set_vlan_id_82599(&atr_input
, vlan_id
);
5474 ixgbe_atr_set_src_port_82599(&atr_input
, dst_port
);
5475 ixgbe_atr_set_dst_port_82599(&atr_input
, src_port
);
5476 ixgbe_atr_set_flex_byte_82599(&atr_input
, flex_bytes
);
5477 ixgbe_atr_set_l4type_82599(&atr_input
, l4type
);
5478 /* src and dst are inverted, think how the receiver sees them */
5479 ixgbe_atr_set_src_ipv4_82599(&atr_input
, dst_ipv4_addr
);
5480 ixgbe_atr_set_dst_ipv4_82599(&atr_input
, src_ipv4_addr
);
5482 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5483 ixgbe_fdir_add_signature_filter_82599(&adapter
->hw
, &atr_input
, queue
);
5486 static int __ixgbe_maybe_stop_tx(struct net_device
*netdev
,
5487 struct ixgbe_ring
*tx_ring
, int size
)
5489 netif_stop_subqueue(netdev
, tx_ring
->queue_index
);
5490 /* Herbert's original patch had:
5491 * smp_mb__after_netif_stop_queue();
5492 * but since that doesn't exist yet, just open code it. */
5495 /* We need to check again in a case another CPU has just
5496 * made room available. */
5497 if (likely(IXGBE_DESC_UNUSED(tx_ring
) < size
))
5500 /* A reprieve! - use start_queue because it doesn't call schedule */
5501 netif_start_subqueue(netdev
, tx_ring
->queue_index
);
5502 ++tx_ring
->restart_queue
;
5506 static int ixgbe_maybe_stop_tx(struct net_device
*netdev
,
5507 struct ixgbe_ring
*tx_ring
, int size
)
5509 if (likely(IXGBE_DESC_UNUSED(tx_ring
) >= size
))
5511 return __ixgbe_maybe_stop_tx(netdev
, tx_ring
, size
);
5514 static u16
ixgbe_select_queue(struct net_device
*dev
, struct sk_buff
*skb
)
5516 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
5517 int txq
= smp_processor_id();
5519 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
)
5523 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) &&
5524 (skb
->protocol
== htons(ETH_P_FCOE
))) {
5525 txq
&= (adapter
->ring_feature
[RING_F_FCOE
].indices
- 1);
5526 txq
+= adapter
->ring_feature
[RING_F_FCOE
].mask
;
5530 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)
5531 return (skb
->vlan_tci
& IXGBE_TX_FLAGS_VLAN_PRIO_MASK
) >> 13;
5533 return skb_tx_hash(dev
, skb
);
5536 static netdev_tx_t
ixgbe_xmit_frame(struct sk_buff
*skb
,
5537 struct net_device
*netdev
)
5539 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5540 struct ixgbe_ring
*tx_ring
;
5541 struct netdev_queue
*txq
;
5543 unsigned int tx_flags
= 0;
5549 if (adapter
->vlgrp
&& vlan_tx_tag_present(skb
)) {
5550 tx_flags
|= vlan_tx_tag_get(skb
);
5551 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
5552 tx_flags
&= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK
;
5553 tx_flags
|= ((skb
->queue_mapping
& 0x7) << 13);
5555 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
5556 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
5557 } else if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
5558 if (skb
->priority
!= TC_PRIO_CONTROL
) {
5559 tx_flags
|= ((skb
->queue_mapping
& 0x7) << 13);
5560 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
5561 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
5563 skb
->queue_mapping
=
5564 adapter
->ring_feature
[RING_F_DCB
].indices
-1;
5568 tx_ring
= &adapter
->tx_ring
[skb
->queue_mapping
];
5570 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) &&
5571 (skb
->protocol
== htons(ETH_P_FCOE
))) {
5572 tx_flags
|= IXGBE_TX_FLAGS_FCOE
;
5574 #ifdef CONFIG_IXGBE_DCB
5575 tx_flags
&= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
5576 << IXGBE_TX_FLAGS_VLAN_SHIFT
);
5577 tx_flags
|= ((adapter
->fcoe
.up
<< 13)
5578 << IXGBE_TX_FLAGS_VLAN_SHIFT
);
5582 /* four things can cause us to need a context descriptor */
5583 if (skb_is_gso(skb
) ||
5584 (skb
->ip_summed
== CHECKSUM_PARTIAL
) ||
5585 (tx_flags
& IXGBE_TX_FLAGS_VLAN
) ||
5586 (tx_flags
& IXGBE_TX_FLAGS_FCOE
))
5589 count
+= TXD_USE_COUNT(skb_headlen(skb
));
5590 for (f
= 0; f
< skb_shinfo(skb
)->nr_frags
; f
++)
5591 count
+= TXD_USE_COUNT(skb_shinfo(skb
)->frags
[f
].size
);
5593 if (ixgbe_maybe_stop_tx(netdev
, tx_ring
, count
)) {
5595 return NETDEV_TX_BUSY
;
5598 first
= tx_ring
->next_to_use
;
5599 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
5601 /* setup tx offload for FCoE */
5602 tso
= ixgbe_fso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
);
5604 dev_kfree_skb_any(skb
);
5605 return NETDEV_TX_OK
;
5608 tx_flags
|= IXGBE_TX_FLAGS_FSO
;
5609 #endif /* IXGBE_FCOE */
5611 if (skb
->protocol
== htons(ETH_P_IP
))
5612 tx_flags
|= IXGBE_TX_FLAGS_IPV4
;
5613 tso
= ixgbe_tso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
);
5615 dev_kfree_skb_any(skb
);
5616 return NETDEV_TX_OK
;
5620 tx_flags
|= IXGBE_TX_FLAGS_TSO
;
5621 else if (ixgbe_tx_csum(adapter
, tx_ring
, skb
, tx_flags
) &&
5622 (skb
->ip_summed
== CHECKSUM_PARTIAL
))
5623 tx_flags
|= IXGBE_TX_FLAGS_CSUM
;
5626 count
= ixgbe_tx_map(adapter
, tx_ring
, skb
, tx_flags
, first
);
5628 /* add the ATR filter if ATR is on */
5629 if (tx_ring
->atr_sample_rate
) {
5630 ++tx_ring
->atr_count
;
5631 if ((tx_ring
->atr_count
>= tx_ring
->atr_sample_rate
) &&
5632 test_bit(__IXGBE_FDIR_INIT_DONE
,
5633 &tx_ring
->reinit_state
)) {
5634 ixgbe_atr(adapter
, skb
, tx_ring
->queue_index
,
5636 tx_ring
->atr_count
= 0;
5639 txq
= netdev_get_tx_queue(netdev
, tx_ring
->queue_index
);
5640 txq
->tx_bytes
+= skb
->len
;
5642 ixgbe_tx_queue(adapter
, tx_ring
, tx_flags
, count
, skb
->len
,
5644 ixgbe_maybe_stop_tx(netdev
, tx_ring
, DESC_NEEDED
);
5647 dev_kfree_skb_any(skb
);
5648 tx_ring
->tx_buffer_info
[first
].time_stamp
= 0;
5649 tx_ring
->next_to_use
= first
;
5652 return NETDEV_TX_OK
;
5656 * ixgbe_set_mac - Change the Ethernet Address of the NIC
5657 * @netdev: network interface device structure
5658 * @p: pointer to an address structure
5660 * Returns 0 on success, negative on failure
5662 static int ixgbe_set_mac(struct net_device
*netdev
, void *p
)
5664 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5665 struct ixgbe_hw
*hw
= &adapter
->hw
;
5666 struct sockaddr
*addr
= p
;
5668 if (!is_valid_ether_addr(addr
->sa_data
))
5669 return -EADDRNOTAVAIL
;
5671 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
5672 memcpy(hw
->mac
.addr
, addr
->sa_data
, netdev
->addr_len
);
5674 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
5681 ixgbe_mdio_read(struct net_device
*netdev
, int prtad
, int devad
, u16 addr
)
5683 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5684 struct ixgbe_hw
*hw
= &adapter
->hw
;
5688 if (prtad
!= hw
->phy
.mdio
.prtad
)
5690 rc
= hw
->phy
.ops
.read_reg(hw
, addr
, devad
, &value
);
5696 static int ixgbe_mdio_write(struct net_device
*netdev
, int prtad
, int devad
,
5697 u16 addr
, u16 value
)
5699 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5700 struct ixgbe_hw
*hw
= &adapter
->hw
;
5702 if (prtad
!= hw
->phy
.mdio
.prtad
)
5704 return hw
->phy
.ops
.write_reg(hw
, addr
, devad
, value
);
5707 static int ixgbe_ioctl(struct net_device
*netdev
, struct ifreq
*req
, int cmd
)
5709 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5711 return mdio_mii_ioctl(&adapter
->hw
.phy
.mdio
, if_mii(req
), cmd
);
5715 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5717 * @netdev: network interface device structure
5719 * Returns non-zero on failure
5721 static int ixgbe_add_sanmac_netdev(struct net_device
*dev
)
5724 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
5725 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
5727 if (is_valid_ether_addr(mac
->san_addr
)) {
5729 err
= dev_addr_add(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
5736 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5738 * @netdev: network interface device structure
5740 * Returns non-zero on failure
5742 static int ixgbe_del_sanmac_netdev(struct net_device
*dev
)
5745 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
5746 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
5748 if (is_valid_ether_addr(mac
->san_addr
)) {
5750 err
= dev_addr_del(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
5756 #ifdef CONFIG_NET_POLL_CONTROLLER
5758 * Polling 'interrupt' - used by things like netconsole to send skbs
5759 * without having to re-enable interrupts. It's not called while
5760 * the interrupt routine is executing.
5762 static void ixgbe_netpoll(struct net_device
*netdev
)
5764 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5767 /* if interface is down do nothing */
5768 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
5771 adapter
->flags
|= IXGBE_FLAG_IN_NETPOLL
;
5772 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
5773 int num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
5774 for (i
= 0; i
< num_q_vectors
; i
++) {
5775 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
5776 ixgbe_msix_clean_many(0, q_vector
);
5779 ixgbe_intr(adapter
->pdev
->irq
, netdev
);
5781 adapter
->flags
&= ~IXGBE_FLAG_IN_NETPOLL
;
5785 static const struct net_device_ops ixgbe_netdev_ops
= {
5786 .ndo_open
= ixgbe_open
,
5787 .ndo_stop
= ixgbe_close
,
5788 .ndo_start_xmit
= ixgbe_xmit_frame
,
5789 .ndo_select_queue
= ixgbe_select_queue
,
5790 .ndo_set_rx_mode
= ixgbe_set_rx_mode
,
5791 .ndo_set_multicast_list
= ixgbe_set_rx_mode
,
5792 .ndo_validate_addr
= eth_validate_addr
,
5793 .ndo_set_mac_address
= ixgbe_set_mac
,
5794 .ndo_change_mtu
= ixgbe_change_mtu
,
5795 .ndo_tx_timeout
= ixgbe_tx_timeout
,
5796 .ndo_vlan_rx_register
= ixgbe_vlan_rx_register
,
5797 .ndo_vlan_rx_add_vid
= ixgbe_vlan_rx_add_vid
,
5798 .ndo_vlan_rx_kill_vid
= ixgbe_vlan_rx_kill_vid
,
5799 .ndo_do_ioctl
= ixgbe_ioctl
,
5800 #ifdef CONFIG_NET_POLL_CONTROLLER
5801 .ndo_poll_controller
= ixgbe_netpoll
,
5804 .ndo_fcoe_ddp_setup
= ixgbe_fcoe_ddp_get
,
5805 .ndo_fcoe_ddp_done
= ixgbe_fcoe_ddp_put
,
5806 .ndo_fcoe_enable
= ixgbe_fcoe_enable
,
5807 .ndo_fcoe_disable
= ixgbe_fcoe_disable
,
5808 .ndo_fcoe_get_wwn
= ixgbe_fcoe_get_wwn
,
5809 #endif /* IXGBE_FCOE */
5812 static void __devinit
ixgbe_probe_vf(struct ixgbe_adapter
*adapter
,
5813 const struct ixgbe_info
*ii
)
5815 #ifdef CONFIG_PCI_IOV
5816 struct ixgbe_hw
*hw
= &adapter
->hw
;
5819 if (hw
->mac
.type
!= ixgbe_mac_82599EB
|| !max_vfs
)
5822 /* The 82599 supports up to 64 VFs per physical function
5823 * but this implementation limits allocation to 63 so that
5824 * basic networking resources are still available to the
5827 adapter
->num_vfs
= (max_vfs
> 63) ? 63 : max_vfs
;
5828 adapter
->flags
|= IXGBE_FLAG_SRIOV_ENABLED
;
5829 err
= pci_enable_sriov(adapter
->pdev
, adapter
->num_vfs
);
5832 "Failed to enable PCI sriov: %d\n", err
);
5835 /* If call to enable VFs succeeded then allocate memory
5836 * for per VF control structures.
5839 kcalloc(adapter
->num_vfs
,
5840 sizeof(struct vf_data_storage
), GFP_KERNEL
);
5841 if (adapter
->vfinfo
) {
5842 /* Now that we're sure SR-IOV is enabled
5843 * and memory allocated set up the mailbox parameters
5845 ixgbe_init_mbx_params_pf(hw
);
5846 memcpy(&hw
->mbx
.ops
, ii
->mbx_ops
,
5847 sizeof(hw
->mbx
.ops
));
5849 /* Disable RSC when in SR-IOV mode */
5850 adapter
->flags2
&= ~(IXGBE_FLAG2_RSC_CAPABLE
|
5851 IXGBE_FLAG2_RSC_ENABLED
);
5857 "Unable to allocate memory for VF "
5858 "Data Storage - SRIOV disabled\n");
5859 pci_disable_sriov(adapter
->pdev
);
5862 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
5863 adapter
->num_vfs
= 0;
5864 #endif /* CONFIG_PCI_IOV */
5868 * ixgbe_probe - Device Initialization Routine
5869 * @pdev: PCI device information struct
5870 * @ent: entry in ixgbe_pci_tbl
5872 * Returns 0 on success, negative on failure
5874 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5875 * The OS initialization, configuring of the adapter private structure,
5876 * and a hardware reset occur.
5878 static int __devinit
ixgbe_probe(struct pci_dev
*pdev
,
5879 const struct pci_device_id
*ent
)
5881 struct net_device
*netdev
;
5882 struct ixgbe_adapter
*adapter
= NULL
;
5883 struct ixgbe_hw
*hw
;
5884 const struct ixgbe_info
*ii
= ixgbe_info_tbl
[ent
->driver_data
];
5885 static int cards_found
;
5886 int i
, err
, pci_using_dac
;
5892 err
= pci_enable_device_mem(pdev
);
5896 if (!pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) &&
5897 !pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64))) {
5900 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
5902 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
5904 dev_err(&pdev
->dev
, "No usable DMA "
5905 "configuration, aborting\n");
5912 err
= pci_request_selected_regions(pdev
, pci_select_bars(pdev
,
5913 IORESOURCE_MEM
), ixgbe_driver_name
);
5916 "pci_request_selected_regions failed 0x%x\n", err
);
5920 pci_enable_pcie_error_reporting(pdev
);
5922 pci_set_master(pdev
);
5923 pci_save_state(pdev
);
5925 netdev
= alloc_etherdev_mq(sizeof(struct ixgbe_adapter
), MAX_TX_QUEUES
);
5928 goto err_alloc_etherdev
;
5931 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
5933 pci_set_drvdata(pdev
, netdev
);
5934 adapter
= netdev_priv(netdev
);
5936 adapter
->netdev
= netdev
;
5937 adapter
->pdev
= pdev
;
5940 adapter
->msg_enable
= (1 << DEFAULT_DEBUG_LEVEL_SHIFT
) - 1;
5942 hw
->hw_addr
= ioremap(pci_resource_start(pdev
, 0),
5943 pci_resource_len(pdev
, 0));
5949 for (i
= 1; i
<= 5; i
++) {
5950 if (pci_resource_len(pdev
, i
) == 0)
5954 netdev
->netdev_ops
= &ixgbe_netdev_ops
;
5955 ixgbe_set_ethtool_ops(netdev
);
5956 netdev
->watchdog_timeo
= 5 * HZ
;
5957 strcpy(netdev
->name
, pci_name(pdev
));
5959 adapter
->bd_number
= cards_found
;
5962 memcpy(&hw
->mac
.ops
, ii
->mac_ops
, sizeof(hw
->mac
.ops
));
5963 hw
->mac
.type
= ii
->mac
;
5966 memcpy(&hw
->eeprom
.ops
, ii
->eeprom_ops
, sizeof(hw
->eeprom
.ops
));
5967 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
5968 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5969 if (!(eec
& (1 << 8)))
5970 hw
->eeprom
.ops
.read
= &ixgbe_read_eeprom_bit_bang_generic
;
5973 memcpy(&hw
->phy
.ops
, ii
->phy_ops
, sizeof(hw
->phy
.ops
));
5974 hw
->phy
.sfp_type
= ixgbe_sfp_type_unknown
;
5975 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5976 hw
->phy
.mdio
.prtad
= MDIO_PRTAD_NONE
;
5977 hw
->phy
.mdio
.mmds
= 0;
5978 hw
->phy
.mdio
.mode_support
= MDIO_SUPPORTS_C45
| MDIO_EMULATE_C22
;
5979 hw
->phy
.mdio
.dev
= netdev
;
5980 hw
->phy
.mdio
.mdio_read
= ixgbe_mdio_read
;
5981 hw
->phy
.mdio
.mdio_write
= ixgbe_mdio_write
;
5983 /* set up this timer and work struct before calling get_invariants
5984 * which might start the timer
5986 init_timer(&adapter
->sfp_timer
);
5987 adapter
->sfp_timer
.function
= &ixgbe_sfp_timer
;
5988 adapter
->sfp_timer
.data
= (unsigned long) adapter
;
5990 INIT_WORK(&adapter
->sfp_task
, ixgbe_sfp_task
);
5992 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5993 INIT_WORK(&adapter
->multispeed_fiber_task
, ixgbe_multispeed_fiber_task
);
5995 /* a new SFP+ module arrival, called from GPI SDP2 context */
5996 INIT_WORK(&adapter
->sfp_config_module_task
,
5997 ixgbe_sfp_config_module_task
);
5999 ii
->get_invariants(hw
);
6001 /* setup the private structure */
6002 err
= ixgbe_sw_init(adapter
);
6007 * If there is a fan on this device and it has failed log the
6010 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
6011 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
6012 if (esdp
& IXGBE_ESDP_SDP1
)
6013 DPRINTK(PROBE
, CRIT
,
6014 "Fan has stopped, replace the adapter\n");
6017 /* reset_hw fills in the perm_addr as well */
6018 err
= hw
->mac
.ops
.reset_hw(hw
);
6019 if (err
== IXGBE_ERR_SFP_NOT_PRESENT
&&
6020 hw
->mac
.type
== ixgbe_mac_82598EB
) {
6022 * Start a kernel thread to watch for a module to arrive.
6023 * Only do this for 82598, since 82599 will generate
6024 * interrupts on module arrival.
6026 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
6027 mod_timer(&adapter
->sfp_timer
,
6028 round_jiffies(jiffies
+ (2 * HZ
)));
6030 } else if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
6031 dev_err(&adapter
->pdev
->dev
, "failed to initialize because "
6032 "an unsupported SFP+ module type was detected.\n"
6033 "Reload the driver after installing a supported "
6037 dev_err(&adapter
->pdev
->dev
, "HW Init failed: %d\n", err
);
6041 ixgbe_probe_vf(adapter
, ii
);
6043 netdev
->features
= NETIF_F_SG
|
6045 NETIF_F_HW_VLAN_TX
|
6046 NETIF_F_HW_VLAN_RX
|
6047 NETIF_F_HW_VLAN_FILTER
;
6049 netdev
->features
|= NETIF_F_IPV6_CSUM
;
6050 netdev
->features
|= NETIF_F_TSO
;
6051 netdev
->features
|= NETIF_F_TSO6
;
6052 netdev
->features
|= NETIF_F_GRO
;
6054 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
6055 netdev
->features
|= NETIF_F_SCTP_CSUM
;
6057 netdev
->vlan_features
|= NETIF_F_TSO
;
6058 netdev
->vlan_features
|= NETIF_F_TSO6
;
6059 netdev
->vlan_features
|= NETIF_F_IP_CSUM
;
6060 netdev
->vlan_features
|= NETIF_F_IPV6_CSUM
;
6061 netdev
->vlan_features
|= NETIF_F_SG
;
6063 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
6064 adapter
->flags
&= ~(IXGBE_FLAG_RSS_ENABLED
|
6065 IXGBE_FLAG_DCB_ENABLED
);
6066 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)
6067 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
6069 #ifdef CONFIG_IXGBE_DCB
6070 netdev
->dcbnl_ops
= &dcbnl_ops
;
6074 if (adapter
->flags
& IXGBE_FLAG_FCOE_CAPABLE
) {
6075 if (hw
->mac
.ops
.get_device_caps
) {
6076 hw
->mac
.ops
.get_device_caps(hw
, &device_caps
);
6077 if (device_caps
& IXGBE_DEVICE_CAPS_FCOE_OFFLOADS
)
6078 adapter
->flags
&= ~IXGBE_FLAG_FCOE_CAPABLE
;
6081 #endif /* IXGBE_FCOE */
6083 netdev
->features
|= NETIF_F_HIGHDMA
;
6085 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
)
6086 netdev
->features
|= NETIF_F_LRO
;
6088 /* make sure the EEPROM is good */
6089 if (hw
->eeprom
.ops
.validate_checksum(hw
, NULL
) < 0) {
6090 dev_err(&pdev
->dev
, "The EEPROM Checksum Is Not Valid\n");
6095 memcpy(netdev
->dev_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
6096 memcpy(netdev
->perm_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
6098 if (ixgbe_validate_mac_addr(netdev
->perm_addr
)) {
6099 dev_err(&pdev
->dev
, "invalid MAC address\n");
6104 init_timer(&adapter
->watchdog_timer
);
6105 adapter
->watchdog_timer
.function
= &ixgbe_watchdog
;
6106 adapter
->watchdog_timer
.data
= (unsigned long)adapter
;
6108 INIT_WORK(&adapter
->reset_task
, ixgbe_reset_task
);
6109 INIT_WORK(&adapter
->watchdog_task
, ixgbe_watchdog_task
);
6111 err
= ixgbe_init_interrupt_scheme(adapter
);
6115 switch (pdev
->device
) {
6116 case IXGBE_DEV_ID_82599_KX4
:
6117 adapter
->wol
= (IXGBE_WUFC_MAG
| IXGBE_WUFC_EX
|
6118 IXGBE_WUFC_MC
| IXGBE_WUFC_BC
);
6119 /* Enable ACPI wakeup in GRC */
6120 IXGBE_WRITE_REG(hw
, IXGBE_GRC
,
6121 (IXGBE_READ_REG(hw
, IXGBE_GRC
) & ~IXGBE_GRC_APME
));
6127 device_set_wakeup_enable(&adapter
->pdev
->dev
, adapter
->wol
);
6129 /* pick up the PCI bus settings for reporting later */
6130 hw
->mac
.ops
.get_bus_info(hw
);
6132 /* print bus type/speed/width info */
6133 dev_info(&pdev
->dev
, "(PCI Express:%s:%s) %pM\n",
6134 ((hw
->bus
.speed
== ixgbe_bus_speed_5000
) ? "5.0Gb/s":
6135 (hw
->bus
.speed
== ixgbe_bus_speed_2500
) ? "2.5Gb/s":"Unknown"),
6136 ((hw
->bus
.width
== ixgbe_bus_width_pcie_x8
) ? "Width x8" :
6137 (hw
->bus
.width
== ixgbe_bus_width_pcie_x4
) ? "Width x4" :
6138 (hw
->bus
.width
== ixgbe_bus_width_pcie_x1
) ? "Width x1" :
6141 ixgbe_read_pba_num_generic(hw
, &part_num
);
6142 if (ixgbe_is_sfp(hw
) && hw
->phy
.sfp_type
!= ixgbe_sfp_type_not_present
)
6143 dev_info(&pdev
->dev
, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
6144 hw
->mac
.type
, hw
->phy
.type
, hw
->phy
.sfp_type
,
6145 (part_num
>> 8), (part_num
& 0xff));
6147 dev_info(&pdev
->dev
, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6148 hw
->mac
.type
, hw
->phy
.type
,
6149 (part_num
>> 8), (part_num
& 0xff));
6151 if (hw
->bus
.width
<= ixgbe_bus_width_pcie_x4
) {
6152 dev_warn(&pdev
->dev
, "PCI-Express bandwidth available for "
6153 "this card is not sufficient for optimal "
6155 dev_warn(&pdev
->dev
, "For optimal performance a x8 "
6156 "PCI-Express slot is required.\n");
6159 /* save off EEPROM version number */
6160 hw
->eeprom
.ops
.read(hw
, 0x29, &adapter
->eeprom_version
);
6162 /* reset the hardware with the new settings */
6163 err
= hw
->mac
.ops
.start_hw(hw
);
6165 if (err
== IXGBE_ERR_EEPROM_VERSION
) {
6166 /* We are running on a pre-production device, log a warning */
6167 dev_warn(&pdev
->dev
, "This device is a pre-production "
6168 "adapter/LOM. Please be aware there may be issues "
6169 "associated with your hardware. If you are "
6170 "experiencing problems please contact your Intel or "
6171 "hardware representative who provided you with this "
6174 strcpy(netdev
->name
, "eth%d");
6175 err
= register_netdev(netdev
);
6179 /* carrier off reporting is important to ethtool even BEFORE open */
6180 netif_carrier_off(netdev
);
6182 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
6183 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
6184 INIT_WORK(&adapter
->fdir_reinit_task
, ixgbe_fdir_reinit_task
);
6186 #ifdef CONFIG_IXGBE_DCA
6187 if (dca_add_requester(&pdev
->dev
) == 0) {
6188 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
6189 ixgbe_setup_dca(adapter
);
6192 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
6193 DPRINTK(PROBE
, INFO
, "IOV is enabled with %d VFs\n",
6195 for (i
= 0; i
< adapter
->num_vfs
; i
++)
6196 ixgbe_vf_configuration(pdev
, (i
| 0x10000000));
6199 /* add san mac addr to netdev */
6200 ixgbe_add_sanmac_netdev(netdev
);
6202 dev_info(&pdev
->dev
, "Intel(R) 10 Gigabit Network Connection\n");
6207 ixgbe_release_hw_control(adapter
);
6208 ixgbe_clear_interrupt_scheme(adapter
);
6211 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
6212 ixgbe_disable_sriov(adapter
);
6213 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
6214 del_timer_sync(&adapter
->sfp_timer
);
6215 cancel_work_sync(&adapter
->sfp_task
);
6216 cancel_work_sync(&adapter
->multispeed_fiber_task
);
6217 cancel_work_sync(&adapter
->sfp_config_module_task
);
6218 iounmap(hw
->hw_addr
);
6220 free_netdev(netdev
);
6222 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
6226 pci_disable_device(pdev
);
6231 * ixgbe_remove - Device Removal Routine
6232 * @pdev: PCI device information struct
6234 * ixgbe_remove is called by the PCI subsystem to alert the driver
6235 * that it should release a PCI device. The could be caused by a
6236 * Hot-Plug event, or because the driver is going to be removed from
6239 static void __devexit
ixgbe_remove(struct pci_dev
*pdev
)
6241 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6242 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6244 set_bit(__IXGBE_DOWN
, &adapter
->state
);
6245 /* clear the module not found bit to make sure the worker won't
6248 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
6249 del_timer_sync(&adapter
->watchdog_timer
);
6251 del_timer_sync(&adapter
->sfp_timer
);
6252 cancel_work_sync(&adapter
->watchdog_task
);
6253 cancel_work_sync(&adapter
->sfp_task
);
6254 cancel_work_sync(&adapter
->multispeed_fiber_task
);
6255 cancel_work_sync(&adapter
->sfp_config_module_task
);
6256 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
6257 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
6258 cancel_work_sync(&adapter
->fdir_reinit_task
);
6259 flush_scheduled_work();
6261 #ifdef CONFIG_IXGBE_DCA
6262 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
6263 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
6264 dca_remove_requester(&pdev
->dev
);
6265 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
6270 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
6271 ixgbe_cleanup_fcoe(adapter
);
6273 #endif /* IXGBE_FCOE */
6275 /* remove the added san mac */
6276 ixgbe_del_sanmac_netdev(netdev
);
6278 if (netdev
->reg_state
== NETREG_REGISTERED
)
6279 unregister_netdev(netdev
);
6281 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
6282 ixgbe_disable_sriov(adapter
);
6284 ixgbe_clear_interrupt_scheme(adapter
);
6286 ixgbe_release_hw_control(adapter
);
6288 iounmap(adapter
->hw
.hw_addr
);
6289 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
6292 DPRINTK(PROBE
, INFO
, "complete\n");
6294 free_netdev(netdev
);
6296 pci_disable_pcie_error_reporting(pdev
);
6298 pci_disable_device(pdev
);
6302 * ixgbe_io_error_detected - called when PCI error is detected
6303 * @pdev: Pointer to PCI device
6304 * @state: The current pci connection state
6306 * This function is called after a PCI bus error affecting
6307 * this device has been detected.
6309 static pci_ers_result_t
ixgbe_io_error_detected(struct pci_dev
*pdev
,
6310 pci_channel_state_t state
)
6312 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6313 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6315 netif_device_detach(netdev
);
6317 if (state
== pci_channel_io_perm_failure
)
6318 return PCI_ERS_RESULT_DISCONNECT
;
6320 if (netif_running(netdev
))
6321 ixgbe_down(adapter
);
6322 pci_disable_device(pdev
);
6324 /* Request a slot reset. */
6325 return PCI_ERS_RESULT_NEED_RESET
;
6329 * ixgbe_io_slot_reset - called after the pci bus has been reset.
6330 * @pdev: Pointer to PCI device
6332 * Restart the card from scratch, as if from a cold-boot.
6334 static pci_ers_result_t
ixgbe_io_slot_reset(struct pci_dev
*pdev
)
6336 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6337 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6338 pci_ers_result_t result
;
6341 if (pci_enable_device_mem(pdev
)) {
6343 "Cannot re-enable PCI device after reset.\n");
6344 result
= PCI_ERS_RESULT_DISCONNECT
;
6346 pci_set_master(pdev
);
6347 pci_restore_state(pdev
);
6348 pci_save_state(pdev
);
6350 pci_wake_from_d3(pdev
, false);
6352 ixgbe_reset(adapter
);
6353 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
6354 result
= PCI_ERS_RESULT_RECOVERED
;
6357 err
= pci_cleanup_aer_uncorrect_error_status(pdev
);
6360 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err
);
6361 /* non-fatal, continue */
6368 * ixgbe_io_resume - called when traffic can start flowing again.
6369 * @pdev: Pointer to PCI device
6371 * This callback is called when the error recovery driver tells us that
6372 * its OK to resume normal operation.
6374 static void ixgbe_io_resume(struct pci_dev
*pdev
)
6376 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6377 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6379 if (netif_running(netdev
)) {
6380 if (ixgbe_up(adapter
)) {
6381 DPRINTK(PROBE
, INFO
, "ixgbe_up failed after reset\n");
6386 netif_device_attach(netdev
);
6389 static struct pci_error_handlers ixgbe_err_handler
= {
6390 .error_detected
= ixgbe_io_error_detected
,
6391 .slot_reset
= ixgbe_io_slot_reset
,
6392 .resume
= ixgbe_io_resume
,
6395 static struct pci_driver ixgbe_driver
= {
6396 .name
= ixgbe_driver_name
,
6397 .id_table
= ixgbe_pci_tbl
,
6398 .probe
= ixgbe_probe
,
6399 .remove
= __devexit_p(ixgbe_remove
),
6401 .suspend
= ixgbe_suspend
,
6402 .resume
= ixgbe_resume
,
6404 .shutdown
= ixgbe_shutdown
,
6405 .err_handler
= &ixgbe_err_handler
6409 * ixgbe_init_module - Driver Registration Routine
6411 * ixgbe_init_module is the first routine called when the driver is
6412 * loaded. All it does is register with the PCI subsystem.
6414 static int __init
ixgbe_init_module(void)
6417 printk(KERN_INFO
"%s: %s - version %s\n", ixgbe_driver_name
,
6418 ixgbe_driver_string
, ixgbe_driver_version
);
6420 printk(KERN_INFO
"%s: %s\n", ixgbe_driver_name
, ixgbe_copyright
);
6422 #ifdef CONFIG_IXGBE_DCA
6423 dca_register_notify(&dca_notifier
);
6426 ret
= pci_register_driver(&ixgbe_driver
);
6430 module_init(ixgbe_init_module
);
6433 * ixgbe_exit_module - Driver Exit Cleanup Routine
6435 * ixgbe_exit_module is called just before the driver is removed
6438 static void __exit
ixgbe_exit_module(void)
6440 #ifdef CONFIG_IXGBE_DCA
6441 dca_unregister_notify(&dca_notifier
);
6443 pci_unregister_driver(&ixgbe_driver
);
6446 #ifdef CONFIG_IXGBE_DCA
6447 static int ixgbe_notify_dca(struct notifier_block
*nb
, unsigned long event
,
6452 ret_val
= driver_for_each_device(&ixgbe_driver
.driver
, NULL
, &event
,
6453 __ixgbe_notify_dca
);
6455 return ret_val
? NOTIFY_BAD
: NOTIFY_DONE
;
6458 #endif /* CONFIG_IXGBE_DCA */
6461 * ixgbe_get_hw_dev_name - return device name string
6462 * used by hardware layer to print debugging information
6464 char *ixgbe_get_hw_dev_name(struct ixgbe_hw
*hw
)
6466 struct ixgbe_adapter
*adapter
= hw
->back
;
6467 return adapter
->netdev
->name
;
6471 module_exit(ixgbe_exit_module
);