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ixgbe: fix automatic LRO/RSC settings for low latency
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <linux/slab.h>
40 #include <net/checksum.h>
41 #include <net/ip6_checksum.h>
42 #include <linux/ethtool.h>
43 #include <linux/if_vlan.h>
44 #include <scsi/fc/fc_fcoe.h>
45
46 #include "ixgbe.h"
47 #include "ixgbe_common.h"
48 #include "ixgbe_dcb_82599.h"
49 #include "ixgbe_sriov.h"
50
51 char ixgbe_driver_name[] = "ixgbe";
52 static const char ixgbe_driver_string[] =
53 "Intel(R) 10 Gigabit PCI Express Network Driver";
54
55 #define DRV_VERSION "2.0.62-k2"
56 const char ixgbe_driver_version[] = DRV_VERSION;
57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
58
59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
60 [board_82598] = &ixgbe_82598_info,
61 [board_82599] = &ixgbe_82599_info,
62 };
63
64 /* ixgbe_pci_tbl - PCI Device ID Table
65 *
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
68 *
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
71 */
72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
74 board_82598 },
75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
76 board_82598 },
77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
78 board_82598 },
79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
80 board_82598 },
81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
82 board_82598 },
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
84 board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
86 board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
88 board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
90 board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
92 board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
94 board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
96 board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
98 board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
100 board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
102 board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
104 board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
106 board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
108 board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
110 board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
112 board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
114 board_82599 },
115
116 /* required last entry */
117 {0, }
118 };
119 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
120
121 #ifdef CONFIG_IXGBE_DCA
122 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
123 void *p);
124 static struct notifier_block dca_notifier = {
125 .notifier_call = ixgbe_notify_dca,
126 .next = NULL,
127 .priority = 0
128 };
129 #endif
130
131 #ifdef CONFIG_PCI_IOV
132 static unsigned int max_vfs;
133 module_param(max_vfs, uint, 0);
134 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
135 "per physical function");
136 #endif /* CONFIG_PCI_IOV */
137
138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
140 MODULE_LICENSE("GPL");
141 MODULE_VERSION(DRV_VERSION);
142
143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
144
145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
146 {
147 struct ixgbe_hw *hw = &adapter->hw;
148 u32 gcr;
149 u32 gpie;
150 u32 vmdctl;
151
152 #ifdef CONFIG_PCI_IOV
153 /* disable iov and allow time for transactions to clear */
154 pci_disable_sriov(adapter->pdev);
155 #endif
156
157 /* turn off device IOV mode */
158 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
159 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
160 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
161 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
162 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
163 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
164
165 /* set default pool back to 0 */
166 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
167 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
168 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
169
170 /* take a breather then clean up driver data */
171 msleep(100);
172 if (adapter->vfinfo)
173 kfree(adapter->vfinfo);
174 adapter->vfinfo = NULL;
175
176 adapter->num_vfs = 0;
177 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
178 }
179
180 struct ixgbe_reg_info {
181 u32 ofs;
182 char *name;
183 };
184
185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
186
187 /* General Registers */
188 {IXGBE_CTRL, "CTRL"},
189 {IXGBE_STATUS, "STATUS"},
190 {IXGBE_CTRL_EXT, "CTRL_EXT"},
191
192 /* Interrupt Registers */
193 {IXGBE_EICR, "EICR"},
194
195 /* RX Registers */
196 {IXGBE_SRRCTL(0), "SRRCTL"},
197 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
198 {IXGBE_RDLEN(0), "RDLEN"},
199 {IXGBE_RDH(0), "RDH"},
200 {IXGBE_RDT(0), "RDT"},
201 {IXGBE_RXDCTL(0), "RXDCTL"},
202 {IXGBE_RDBAL(0), "RDBAL"},
203 {IXGBE_RDBAH(0), "RDBAH"},
204
205 /* TX Registers */
206 {IXGBE_TDBAL(0), "TDBAL"},
207 {IXGBE_TDBAH(0), "TDBAH"},
208 {IXGBE_TDLEN(0), "TDLEN"},
209 {IXGBE_TDH(0), "TDH"},
210 {IXGBE_TDT(0), "TDT"},
211 {IXGBE_TXDCTL(0), "TXDCTL"},
212
213 /* List Terminator */
214 {}
215 };
216
217
218 /*
219 * ixgbe_regdump - register printout routine
220 */
221 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
222 {
223 int i = 0, j = 0;
224 char rname[16];
225 u32 regs[64];
226
227 switch (reginfo->ofs) {
228 case IXGBE_SRRCTL(0):
229 for (i = 0; i < 64; i++)
230 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
231 break;
232 case IXGBE_DCA_RXCTRL(0):
233 for (i = 0; i < 64; i++)
234 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
235 break;
236 case IXGBE_RDLEN(0):
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
239 break;
240 case IXGBE_RDH(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
243 break;
244 case IXGBE_RDT(0):
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
247 break;
248 case IXGBE_RXDCTL(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
251 break;
252 case IXGBE_RDBAL(0):
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
255 break;
256 case IXGBE_RDBAH(0):
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
259 break;
260 case IXGBE_TDBAL(0):
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
263 break;
264 case IXGBE_TDBAH(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
267 break;
268 case IXGBE_TDLEN(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
271 break;
272 case IXGBE_TDH(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
275 break;
276 case IXGBE_TDT(0):
277 for (i = 0; i < 64; i++)
278 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
279 break;
280 case IXGBE_TXDCTL(0):
281 for (i = 0; i < 64; i++)
282 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
283 break;
284 default:
285 printk(KERN_INFO "%-15s %08x\n", reginfo->name,
286 IXGBE_READ_REG(hw, reginfo->ofs));
287 return;
288 }
289
290 for (i = 0; i < 8; i++) {
291 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
292 printk(KERN_ERR "%-15s ", rname);
293 for (j = 0; j < 8; j++)
294 printk(KERN_CONT "%08x ", regs[i*8+j]);
295 printk(KERN_CONT "\n");
296 }
297
298 }
299
300 /*
301 * ixgbe_dump - Print registers, tx-rings and rx-rings
302 */
303 static void ixgbe_dump(struct ixgbe_adapter *adapter)
304 {
305 struct net_device *netdev = adapter->netdev;
306 struct ixgbe_hw *hw = &adapter->hw;
307 struct ixgbe_reg_info *reginfo;
308 int n = 0;
309 struct ixgbe_ring *tx_ring;
310 struct ixgbe_tx_buffer *tx_buffer_info;
311 union ixgbe_adv_tx_desc *tx_desc;
312 struct my_u0 { u64 a; u64 b; } *u0;
313 struct ixgbe_ring *rx_ring;
314 union ixgbe_adv_rx_desc *rx_desc;
315 struct ixgbe_rx_buffer *rx_buffer_info;
316 u32 staterr;
317 int i = 0;
318
319 if (!netif_msg_hw(adapter))
320 return;
321
322 /* Print netdevice Info */
323 if (netdev) {
324 dev_info(&adapter->pdev->dev, "Net device Info\n");
325 printk(KERN_INFO "Device Name state "
326 "trans_start last_rx\n");
327 printk(KERN_INFO "%-15s %016lX %016lX %016lX\n",
328 netdev->name,
329 netdev->state,
330 netdev->trans_start,
331 netdev->last_rx);
332 }
333
334 /* Print Registers */
335 dev_info(&adapter->pdev->dev, "Register Dump\n");
336 printk(KERN_INFO " Register Name Value\n");
337 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
338 reginfo->name; reginfo++) {
339 ixgbe_regdump(hw, reginfo);
340 }
341
342 /* Print TX Ring Summary */
343 if (!netdev || !netif_running(netdev))
344 goto exit;
345
346 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
347 printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma ] "
348 "leng ntw timestamp\n");
349 for (n = 0; n < adapter->num_tx_queues; n++) {
350 tx_ring = adapter->tx_ring[n];
351 tx_buffer_info =
352 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
353 printk(KERN_INFO " %5d %5X %5X %016llX %04X %3X %016llX\n",
354 n, tx_ring->next_to_use, tx_ring->next_to_clean,
355 (u64)tx_buffer_info->dma,
356 tx_buffer_info->length,
357 tx_buffer_info->next_to_watch,
358 (u64)tx_buffer_info->time_stamp);
359 }
360
361 /* Print TX Rings */
362 if (!netif_msg_tx_done(adapter))
363 goto rx_ring_summary;
364
365 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
366
367 /* Transmit Descriptor Formats
368 *
369 * Advanced Transmit Descriptor
370 * +--------------------------------------------------------------+
371 * 0 | Buffer Address [63:0] |
372 * +--------------------------------------------------------------+
373 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
374 * +--------------------------------------------------------------+
375 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
376 */
377
378 for (n = 0; n < adapter->num_tx_queues; n++) {
379 tx_ring = adapter->tx_ring[n];
380 printk(KERN_INFO "------------------------------------\n");
381 printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index);
382 printk(KERN_INFO "------------------------------------\n");
383 printk(KERN_INFO "T [desc] [address 63:0 ] "
384 "[PlPOIdStDDt Ln] [bi->dma ] "
385 "leng ntw timestamp bi->skb\n");
386
387 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
388 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
389 tx_buffer_info = &tx_ring->tx_buffer_info[i];
390 u0 = (struct my_u0 *)tx_desc;
391 printk(KERN_INFO "T [0x%03X] %016llX %016llX %016llX"
392 " %04X %3X %016llX %p", i,
393 le64_to_cpu(u0->a),
394 le64_to_cpu(u0->b),
395 (u64)tx_buffer_info->dma,
396 tx_buffer_info->length,
397 tx_buffer_info->next_to_watch,
398 (u64)tx_buffer_info->time_stamp,
399 tx_buffer_info->skb);
400 if (i == tx_ring->next_to_use &&
401 i == tx_ring->next_to_clean)
402 printk(KERN_CONT " NTC/U\n");
403 else if (i == tx_ring->next_to_use)
404 printk(KERN_CONT " NTU\n");
405 else if (i == tx_ring->next_to_clean)
406 printk(KERN_CONT " NTC\n");
407 else
408 printk(KERN_CONT "\n");
409
410 if (netif_msg_pktdata(adapter) &&
411 tx_buffer_info->dma != 0)
412 print_hex_dump(KERN_INFO, "",
413 DUMP_PREFIX_ADDRESS, 16, 1,
414 phys_to_virt(tx_buffer_info->dma),
415 tx_buffer_info->length, true);
416 }
417 }
418
419 /* Print RX Rings Summary */
420 rx_ring_summary:
421 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
422 printk(KERN_INFO "Queue [NTU] [NTC]\n");
423 for (n = 0; n < adapter->num_rx_queues; n++) {
424 rx_ring = adapter->rx_ring[n];
425 printk(KERN_INFO "%5d %5X %5X\n", n,
426 rx_ring->next_to_use, rx_ring->next_to_clean);
427 }
428
429 /* Print RX Rings */
430 if (!netif_msg_rx_status(adapter))
431 goto exit;
432
433 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
434
435 /* Advanced Receive Descriptor (Read) Format
436 * 63 1 0
437 * +-----------------------------------------------------+
438 * 0 | Packet Buffer Address [63:1] |A0/NSE|
439 * +----------------------------------------------+------+
440 * 8 | Header Buffer Address [63:1] | DD |
441 * +-----------------------------------------------------+
442 *
443 *
444 * Advanced Receive Descriptor (Write-Back) Format
445 *
446 * 63 48 47 32 31 30 21 20 16 15 4 3 0
447 * +------------------------------------------------------+
448 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
449 * | Checksum Ident | | | | Type | Type |
450 * +------------------------------------------------------+
451 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
452 * +------------------------------------------------------+
453 * 63 48 47 32 31 20 19 0
454 */
455 for (n = 0; n < adapter->num_rx_queues; n++) {
456 rx_ring = adapter->rx_ring[n];
457 printk(KERN_INFO "------------------------------------\n");
458 printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index);
459 printk(KERN_INFO "------------------------------------\n");
460 printk(KERN_INFO "R [desc] [ PktBuf A0] "
461 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
462 "<-- Adv Rx Read format\n");
463 printk(KERN_INFO "RWB[desc] [PcsmIpSHl PtRs] "
464 "[vl er S cks ln] ---------------- [bi->skb] "
465 "<-- Adv Rx Write-Back format\n");
466
467 for (i = 0; i < rx_ring->count; i++) {
468 rx_buffer_info = &rx_ring->rx_buffer_info[i];
469 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
470 u0 = (struct my_u0 *)rx_desc;
471 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
472 if (staterr & IXGBE_RXD_STAT_DD) {
473 /* Descriptor Done */
474 printk(KERN_INFO "RWB[0x%03X] %016llX "
475 "%016llX ---------------- %p", i,
476 le64_to_cpu(u0->a),
477 le64_to_cpu(u0->b),
478 rx_buffer_info->skb);
479 } else {
480 printk(KERN_INFO "R [0x%03X] %016llX "
481 "%016llX %016llX %p", i,
482 le64_to_cpu(u0->a),
483 le64_to_cpu(u0->b),
484 (u64)rx_buffer_info->dma,
485 rx_buffer_info->skb);
486
487 if (netif_msg_pktdata(adapter)) {
488 print_hex_dump(KERN_INFO, "",
489 DUMP_PREFIX_ADDRESS, 16, 1,
490 phys_to_virt(rx_buffer_info->dma),
491 rx_ring->rx_buf_len, true);
492
493 if (rx_ring->rx_buf_len
494 < IXGBE_RXBUFFER_2048)
495 print_hex_dump(KERN_INFO, "",
496 DUMP_PREFIX_ADDRESS, 16, 1,
497 phys_to_virt(
498 rx_buffer_info->page_dma +
499 rx_buffer_info->page_offset
500 ),
501 PAGE_SIZE/2, true);
502 }
503 }
504
505 if (i == rx_ring->next_to_use)
506 printk(KERN_CONT " NTU\n");
507 else if (i == rx_ring->next_to_clean)
508 printk(KERN_CONT " NTC\n");
509 else
510 printk(KERN_CONT "\n");
511
512 }
513 }
514
515 exit:
516 return;
517 }
518
519 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
520 {
521 u32 ctrl_ext;
522
523 /* Let firmware take over control of h/w */
524 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
525 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
526 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
527 }
528
529 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
530 {
531 u32 ctrl_ext;
532
533 /* Let firmware know the driver has taken over */
534 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
535 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
536 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
537 }
538
539 /*
540 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
541 * @adapter: pointer to adapter struct
542 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
543 * @queue: queue to map the corresponding interrupt to
544 * @msix_vector: the vector to map to the corresponding queue
545 *
546 */
547 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
548 u8 queue, u8 msix_vector)
549 {
550 u32 ivar, index;
551 struct ixgbe_hw *hw = &adapter->hw;
552 switch (hw->mac.type) {
553 case ixgbe_mac_82598EB:
554 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
555 if (direction == -1)
556 direction = 0;
557 index = (((direction * 64) + queue) >> 2) & 0x1F;
558 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
559 ivar &= ~(0xFF << (8 * (queue & 0x3)));
560 ivar |= (msix_vector << (8 * (queue & 0x3)));
561 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
562 break;
563 case ixgbe_mac_82599EB:
564 if (direction == -1) {
565 /* other causes */
566 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
567 index = ((queue & 1) * 8);
568 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
569 ivar &= ~(0xFF << index);
570 ivar |= (msix_vector << index);
571 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
572 break;
573 } else {
574 /* tx or rx causes */
575 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
576 index = ((16 * (queue & 1)) + (8 * direction));
577 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
578 ivar &= ~(0xFF << index);
579 ivar |= (msix_vector << index);
580 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
581 break;
582 }
583 default:
584 break;
585 }
586 }
587
588 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
589 u64 qmask)
590 {
591 u32 mask;
592
593 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
594 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
595 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
596 } else {
597 mask = (qmask & 0xFFFFFFFF);
598 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
599 mask = (qmask >> 32);
600 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
601 }
602 }
603
604 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
605 struct ixgbe_tx_buffer
606 *tx_buffer_info)
607 {
608 if (tx_buffer_info->dma) {
609 if (tx_buffer_info->mapped_as_page)
610 dma_unmap_page(&adapter->pdev->dev,
611 tx_buffer_info->dma,
612 tx_buffer_info->length,
613 DMA_TO_DEVICE);
614 else
615 dma_unmap_single(&adapter->pdev->dev,
616 tx_buffer_info->dma,
617 tx_buffer_info->length,
618 DMA_TO_DEVICE);
619 tx_buffer_info->dma = 0;
620 }
621 if (tx_buffer_info->skb) {
622 dev_kfree_skb_any(tx_buffer_info->skb);
623 tx_buffer_info->skb = NULL;
624 }
625 tx_buffer_info->time_stamp = 0;
626 /* tx_buffer_info must be completely set up in the transmit path */
627 }
628
629 /**
630 * ixgbe_tx_xon_state - check the tx ring xon state
631 * @adapter: the ixgbe adapter
632 * @tx_ring: the corresponding tx_ring
633 *
634 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
635 * corresponding TC of this tx_ring when checking TFCS.
636 *
637 * Returns : true if in xon state (currently not paused)
638 */
639 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
640 struct ixgbe_ring *tx_ring)
641 {
642 u32 txoff = IXGBE_TFCS_TXOFF;
643
644 #ifdef CONFIG_IXGBE_DCB
645 if (adapter->dcb_cfg.pfc_mode_enable) {
646 int tc;
647 int reg_idx = tx_ring->reg_idx;
648 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
649
650 switch (adapter->hw.mac.type) {
651 case ixgbe_mac_82598EB:
652 tc = reg_idx >> 2;
653 txoff = IXGBE_TFCS_TXOFF0;
654 break;
655 case ixgbe_mac_82599EB:
656 tc = 0;
657 txoff = IXGBE_TFCS_TXOFF;
658 if (dcb_i == 8) {
659 /* TC0, TC1 */
660 tc = reg_idx >> 5;
661 if (tc == 2) /* TC2, TC3 */
662 tc += (reg_idx - 64) >> 4;
663 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
664 tc += 1 + ((reg_idx - 96) >> 3);
665 } else if (dcb_i == 4) {
666 /* TC0, TC1 */
667 tc = reg_idx >> 6;
668 if (tc == 1) {
669 tc += (reg_idx - 64) >> 5;
670 if (tc == 2) /* TC2, TC3 */
671 tc += (reg_idx - 96) >> 4;
672 }
673 }
674 break;
675 default:
676 tc = 0;
677 }
678 txoff <<= tc;
679 }
680 #endif
681 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
682 }
683
684 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
685 struct ixgbe_ring *tx_ring,
686 unsigned int eop)
687 {
688 struct ixgbe_hw *hw = &adapter->hw;
689
690 /* Detect a transmit hang in hardware, this serializes the
691 * check with the clearing of time_stamp and movement of eop */
692 adapter->detect_tx_hung = false;
693 if (tx_ring->tx_buffer_info[eop].time_stamp &&
694 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
695 ixgbe_tx_xon_state(adapter, tx_ring)) {
696 /* detected Tx unit hang */
697 union ixgbe_adv_tx_desc *tx_desc;
698 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
699 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
700 " Tx Queue <%d>\n"
701 " TDH, TDT <%x>, <%x>\n"
702 " next_to_use <%x>\n"
703 " next_to_clean <%x>\n"
704 "tx_buffer_info[next_to_clean]\n"
705 " time_stamp <%lx>\n"
706 " jiffies <%lx>\n",
707 tx_ring->queue_index,
708 IXGBE_READ_REG(hw, tx_ring->head),
709 IXGBE_READ_REG(hw, tx_ring->tail),
710 tx_ring->next_to_use, eop,
711 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
712 return true;
713 }
714
715 return false;
716 }
717
718 #define IXGBE_MAX_TXD_PWR 14
719 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
720
721 /* Tx Descriptors needed, worst case */
722 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
723 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
724 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
725 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
726
727 static void ixgbe_tx_timeout(struct net_device *netdev);
728
729 /**
730 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
731 * @q_vector: structure containing interrupt and ring information
732 * @tx_ring: tx ring to clean
733 **/
734 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
735 struct ixgbe_ring *tx_ring)
736 {
737 struct ixgbe_adapter *adapter = q_vector->adapter;
738 struct net_device *netdev = adapter->netdev;
739 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
740 struct ixgbe_tx_buffer *tx_buffer_info;
741 unsigned int i, eop, count = 0;
742 unsigned int total_bytes = 0, total_packets = 0;
743
744 i = tx_ring->next_to_clean;
745 eop = tx_ring->tx_buffer_info[i].next_to_watch;
746 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
747
748 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
749 (count < tx_ring->work_limit)) {
750 bool cleaned = false;
751 for ( ; !cleaned; count++) {
752 struct sk_buff *skb;
753 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
754 tx_buffer_info = &tx_ring->tx_buffer_info[i];
755 cleaned = (i == eop);
756 skb = tx_buffer_info->skb;
757
758 if (cleaned && skb) {
759 unsigned int segs, bytecount;
760 unsigned int hlen = skb_headlen(skb);
761
762 /* gso_segs is currently only valid for tcp */
763 segs = skb_shinfo(skb)->gso_segs ?: 1;
764 #ifdef IXGBE_FCOE
765 /* adjust for FCoE Sequence Offload */
766 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
767 && (skb->protocol == htons(ETH_P_FCOE)) &&
768 skb_is_gso(skb)) {
769 hlen = skb_transport_offset(skb) +
770 sizeof(struct fc_frame_header) +
771 sizeof(struct fcoe_crc_eof);
772 segs = DIV_ROUND_UP(skb->len - hlen,
773 skb_shinfo(skb)->gso_size);
774 }
775 #endif /* IXGBE_FCOE */
776 /* multiply data chunks by size of headers */
777 bytecount = ((segs - 1) * hlen) + skb->len;
778 total_packets += segs;
779 total_bytes += bytecount;
780 }
781
782 ixgbe_unmap_and_free_tx_resource(adapter,
783 tx_buffer_info);
784
785 tx_desc->wb.status = 0;
786
787 i++;
788 if (i == tx_ring->count)
789 i = 0;
790 }
791
792 eop = tx_ring->tx_buffer_info[i].next_to_watch;
793 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
794 }
795
796 tx_ring->next_to_clean = i;
797
798 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
799 if (unlikely(count && netif_carrier_ok(netdev) &&
800 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
801 /* Make sure that anybody stopping the queue after this
802 * sees the new next_to_clean.
803 */
804 smp_mb();
805 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
806 !test_bit(__IXGBE_DOWN, &adapter->state)) {
807 netif_wake_subqueue(netdev, tx_ring->queue_index);
808 ++tx_ring->restart_queue;
809 }
810 }
811
812 if (adapter->detect_tx_hung) {
813 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
814 /* schedule immediate reset if we believe we hung */
815 DPRINTK(PROBE, INFO,
816 "tx hang %d detected, resetting adapter\n",
817 adapter->tx_timeout_count + 1);
818 ixgbe_tx_timeout(adapter->netdev);
819 }
820 }
821
822 /* re-arm the interrupt */
823 if (count >= tx_ring->work_limit)
824 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
825
826 tx_ring->total_bytes += total_bytes;
827 tx_ring->total_packets += total_packets;
828 tx_ring->stats.packets += total_packets;
829 tx_ring->stats.bytes += total_bytes;
830 return (count < tx_ring->work_limit);
831 }
832
833 #ifdef CONFIG_IXGBE_DCA
834 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
835 struct ixgbe_ring *rx_ring)
836 {
837 u32 rxctrl;
838 int cpu = get_cpu();
839 int q = rx_ring->reg_idx;
840
841 if (rx_ring->cpu != cpu) {
842 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
843 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
844 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
845 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
846 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
847 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
848 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
849 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
850 }
851 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
852 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
853 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
854 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
855 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
856 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
857 rx_ring->cpu = cpu;
858 }
859 put_cpu();
860 }
861
862 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
863 struct ixgbe_ring *tx_ring)
864 {
865 u32 txctrl;
866 int cpu = get_cpu();
867 int q = tx_ring->reg_idx;
868 struct ixgbe_hw *hw = &adapter->hw;
869
870 if (tx_ring->cpu != cpu) {
871 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
872 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
873 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
874 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
875 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
876 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
877 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
878 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
879 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
880 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
881 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
882 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
883 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
884 }
885 tx_ring->cpu = cpu;
886 }
887 put_cpu();
888 }
889
890 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
891 {
892 int i;
893
894 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
895 return;
896
897 /* always use CB2 mode, difference is masked in the CB driver */
898 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
899
900 for (i = 0; i < adapter->num_tx_queues; i++) {
901 adapter->tx_ring[i]->cpu = -1;
902 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
903 }
904 for (i = 0; i < adapter->num_rx_queues; i++) {
905 adapter->rx_ring[i]->cpu = -1;
906 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
907 }
908 }
909
910 static int __ixgbe_notify_dca(struct device *dev, void *data)
911 {
912 struct net_device *netdev = dev_get_drvdata(dev);
913 struct ixgbe_adapter *adapter = netdev_priv(netdev);
914 unsigned long event = *(unsigned long *)data;
915
916 switch (event) {
917 case DCA_PROVIDER_ADD:
918 /* if we're already enabled, don't do it again */
919 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
920 break;
921 if (dca_add_requester(dev) == 0) {
922 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
923 ixgbe_setup_dca(adapter);
924 break;
925 }
926 /* Fall Through since DCA is disabled. */
927 case DCA_PROVIDER_REMOVE:
928 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
929 dca_remove_requester(dev);
930 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
931 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
932 }
933 break;
934 }
935
936 return 0;
937 }
938
939 #endif /* CONFIG_IXGBE_DCA */
940 /**
941 * ixgbe_receive_skb - Send a completed packet up the stack
942 * @adapter: board private structure
943 * @skb: packet to send up
944 * @status: hardware indication of status of receive
945 * @rx_ring: rx descriptor ring (for a specific queue) to setup
946 * @rx_desc: rx descriptor
947 **/
948 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
949 struct sk_buff *skb, u8 status,
950 struct ixgbe_ring *ring,
951 union ixgbe_adv_rx_desc *rx_desc)
952 {
953 struct ixgbe_adapter *adapter = q_vector->adapter;
954 struct napi_struct *napi = &q_vector->napi;
955 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
956 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
957
958 skb_record_rx_queue(skb, ring->queue_index);
959 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
960 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
961 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
962 else
963 napi_gro_receive(napi, skb);
964 } else {
965 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
966 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
967 else
968 netif_rx(skb);
969 }
970 }
971
972 /**
973 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
974 * @adapter: address of board private structure
975 * @status_err: hardware indication of status of receive
976 * @skb: skb currently being received and modified
977 **/
978 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
979 union ixgbe_adv_rx_desc *rx_desc,
980 struct sk_buff *skb)
981 {
982 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
983
984 skb->ip_summed = CHECKSUM_NONE;
985
986 /* Rx csum disabled */
987 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
988 return;
989
990 /* if IP and error */
991 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
992 (status_err & IXGBE_RXDADV_ERR_IPE)) {
993 adapter->hw_csum_rx_error++;
994 return;
995 }
996
997 if (!(status_err & IXGBE_RXD_STAT_L4CS))
998 return;
999
1000 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1001 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1002
1003 /*
1004 * 82599 errata, UDP frames with a 0 checksum can be marked as
1005 * checksum errors.
1006 */
1007 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1008 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1009 return;
1010
1011 adapter->hw_csum_rx_error++;
1012 return;
1013 }
1014
1015 /* It must be a TCP or UDP packet with a valid checksum */
1016 skb->ip_summed = CHECKSUM_UNNECESSARY;
1017 }
1018
1019 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
1020 struct ixgbe_ring *rx_ring, u32 val)
1021 {
1022 /*
1023 * Force memory writes to complete before letting h/w
1024 * know there are new descriptors to fetch. (Only
1025 * applicable for weak-ordered memory model archs,
1026 * such as IA-64).
1027 */
1028 wmb();
1029 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
1030 }
1031
1032 /**
1033 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1034 * @adapter: address of board private structure
1035 **/
1036 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
1037 struct ixgbe_ring *rx_ring,
1038 int cleaned_count)
1039 {
1040 struct pci_dev *pdev = adapter->pdev;
1041 union ixgbe_adv_rx_desc *rx_desc;
1042 struct ixgbe_rx_buffer *bi;
1043 unsigned int i;
1044
1045 i = rx_ring->next_to_use;
1046 bi = &rx_ring->rx_buffer_info[i];
1047
1048 while (cleaned_count--) {
1049 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1050
1051 if (!bi->page_dma &&
1052 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
1053 if (!bi->page) {
1054 bi->page = alloc_page(GFP_ATOMIC);
1055 if (!bi->page) {
1056 adapter->alloc_rx_page_failed++;
1057 goto no_buffers;
1058 }
1059 bi->page_offset = 0;
1060 } else {
1061 /* use a half page if we're re-using */
1062 bi->page_offset ^= (PAGE_SIZE / 2);
1063 }
1064
1065 bi->page_dma = dma_map_page(&pdev->dev, bi->page,
1066 bi->page_offset,
1067 (PAGE_SIZE / 2),
1068 DMA_FROM_DEVICE);
1069 }
1070
1071 if (!bi->skb) {
1072 struct sk_buff *skb;
1073 /* netdev_alloc_skb reserves 32 bytes up front!! */
1074 uint bufsz = rx_ring->rx_buf_len + SMP_CACHE_BYTES;
1075 skb = netdev_alloc_skb(adapter->netdev, bufsz);
1076
1077 if (!skb) {
1078 adapter->alloc_rx_buff_failed++;
1079 goto no_buffers;
1080 }
1081
1082 /* advance the data pointer to the next cache line */
1083 skb_reserve(skb, (PTR_ALIGN(skb->data, SMP_CACHE_BYTES)
1084 - skb->data));
1085
1086 bi->skb = skb;
1087 bi->dma = dma_map_single(&pdev->dev, skb->data,
1088 rx_ring->rx_buf_len,
1089 DMA_FROM_DEVICE);
1090 }
1091 /* Refresh the desc even if buffer_addrs didn't change because
1092 * each write-back erases this info. */
1093 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1094 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1095 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1096 } else {
1097 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1098 }
1099
1100 i++;
1101 if (i == rx_ring->count)
1102 i = 0;
1103 bi = &rx_ring->rx_buffer_info[i];
1104 }
1105
1106 no_buffers:
1107 if (rx_ring->next_to_use != i) {
1108 rx_ring->next_to_use = i;
1109 if (i-- == 0)
1110 i = (rx_ring->count - 1);
1111
1112 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
1113 }
1114 }
1115
1116 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1117 {
1118 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1119 }
1120
1121 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1122 {
1123 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1124 }
1125
1126 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1127 {
1128 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1129 IXGBE_RXDADV_RSCCNT_MASK) >>
1130 IXGBE_RXDADV_RSCCNT_SHIFT;
1131 }
1132
1133 /**
1134 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1135 * @skb: pointer to the last skb in the rsc queue
1136 * @count: pointer to number of packets coalesced in this context
1137 *
1138 * This function changes a queue full of hw rsc buffers into a completed
1139 * packet. It uses the ->prev pointers to find the first packet and then
1140 * turns it into the frag list owner.
1141 **/
1142 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
1143 u64 *count)
1144 {
1145 unsigned int frag_list_size = 0;
1146
1147 while (skb->prev) {
1148 struct sk_buff *prev = skb->prev;
1149 frag_list_size += skb->len;
1150 skb->prev = NULL;
1151 skb = prev;
1152 *count += 1;
1153 }
1154
1155 skb_shinfo(skb)->frag_list = skb->next;
1156 skb->next = NULL;
1157 skb->len += frag_list_size;
1158 skb->data_len += frag_list_size;
1159 skb->truesize += frag_list_size;
1160 return skb;
1161 }
1162
1163 struct ixgbe_rsc_cb {
1164 dma_addr_t dma;
1165 bool delay_unmap;
1166 };
1167
1168 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1169
1170 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1171 struct ixgbe_ring *rx_ring,
1172 int *work_done, int work_to_do)
1173 {
1174 struct ixgbe_adapter *adapter = q_vector->adapter;
1175 struct net_device *netdev = adapter->netdev;
1176 struct pci_dev *pdev = adapter->pdev;
1177 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1178 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1179 struct sk_buff *skb;
1180 unsigned int i, rsc_count = 0;
1181 u32 len, staterr;
1182 u16 hdr_info;
1183 bool cleaned = false;
1184 int cleaned_count = 0;
1185 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1186 #ifdef IXGBE_FCOE
1187 int ddp_bytes = 0;
1188 #endif /* IXGBE_FCOE */
1189
1190 i = rx_ring->next_to_clean;
1191 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1192 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1193 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1194
1195 while (staterr & IXGBE_RXD_STAT_DD) {
1196 u32 upper_len = 0;
1197 if (*work_done >= work_to_do)
1198 break;
1199 (*work_done)++;
1200
1201 rmb(); /* read descriptor and rx_buffer_info after status DD */
1202 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1203 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1204 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1205 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1206 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1207 if ((len > IXGBE_RX_HDR_SIZE) ||
1208 (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1209 len = IXGBE_RX_HDR_SIZE;
1210 } else {
1211 len = le16_to_cpu(rx_desc->wb.upper.length);
1212 }
1213
1214 cleaned = true;
1215 skb = rx_buffer_info->skb;
1216 prefetch(skb->data);
1217 rx_buffer_info->skb = NULL;
1218
1219 if (rx_buffer_info->dma) {
1220 if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1221 (!(staterr & IXGBE_RXD_STAT_EOP)) &&
1222 (!(skb->prev))) {
1223 /*
1224 * When HWRSC is enabled, delay unmapping
1225 * of the first packet. It carries the
1226 * header information, HW may still
1227 * access the header after the writeback.
1228 * Only unmap it when EOP is reached
1229 */
1230 IXGBE_RSC_CB(skb)->delay_unmap = true;
1231 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1232 } else {
1233 dma_unmap_single(&pdev->dev,
1234 rx_buffer_info->dma,
1235 rx_ring->rx_buf_len,
1236 DMA_FROM_DEVICE);
1237 }
1238 rx_buffer_info->dma = 0;
1239 skb_put(skb, len);
1240 }
1241
1242 if (upper_len) {
1243 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
1244 PAGE_SIZE / 2, DMA_FROM_DEVICE);
1245 rx_buffer_info->page_dma = 0;
1246 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1247 rx_buffer_info->page,
1248 rx_buffer_info->page_offset,
1249 upper_len);
1250
1251 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1252 (page_count(rx_buffer_info->page) != 1))
1253 rx_buffer_info->page = NULL;
1254 else
1255 get_page(rx_buffer_info->page);
1256
1257 skb->len += upper_len;
1258 skb->data_len += upper_len;
1259 skb->truesize += upper_len;
1260 }
1261
1262 i++;
1263 if (i == rx_ring->count)
1264 i = 0;
1265
1266 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
1267 prefetch(next_rxd);
1268 cleaned_count++;
1269
1270 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
1271 rsc_count = ixgbe_get_rsc_count(rx_desc);
1272
1273 if (rsc_count) {
1274 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1275 IXGBE_RXDADV_NEXTP_SHIFT;
1276 next_buffer = &rx_ring->rx_buffer_info[nextp];
1277 } else {
1278 next_buffer = &rx_ring->rx_buffer_info[i];
1279 }
1280
1281 if (staterr & IXGBE_RXD_STAT_EOP) {
1282 if (skb->prev)
1283 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
1284 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
1285 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1286 dma_unmap_single(&pdev->dev,
1287 IXGBE_RSC_CB(skb)->dma,
1288 rx_ring->rx_buf_len,
1289 DMA_FROM_DEVICE);
1290 IXGBE_RSC_CB(skb)->dma = 0;
1291 IXGBE_RSC_CB(skb)->delay_unmap = false;
1292 }
1293 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
1294 rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
1295 else
1296 rx_ring->rsc_count++;
1297 rx_ring->rsc_flush++;
1298 }
1299 rx_ring->stats.packets++;
1300 rx_ring->stats.bytes += skb->len;
1301 } else {
1302 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1303 rx_buffer_info->skb = next_buffer->skb;
1304 rx_buffer_info->dma = next_buffer->dma;
1305 next_buffer->skb = skb;
1306 next_buffer->dma = 0;
1307 } else {
1308 skb->next = next_buffer->skb;
1309 skb->next->prev = skb;
1310 }
1311 rx_ring->non_eop_descs++;
1312 goto next_desc;
1313 }
1314
1315 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1316 dev_kfree_skb_irq(skb);
1317 goto next_desc;
1318 }
1319
1320 ixgbe_rx_checksum(adapter, rx_desc, skb);
1321
1322 /* probably a little skewed due to removing CRC */
1323 total_rx_bytes += skb->len;
1324 total_rx_packets++;
1325
1326 skb->protocol = eth_type_trans(skb, adapter->netdev);
1327 #ifdef IXGBE_FCOE
1328 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1329 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1330 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1331 if (!ddp_bytes)
1332 goto next_desc;
1333 }
1334 #endif /* IXGBE_FCOE */
1335 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1336
1337 next_desc:
1338 rx_desc->wb.upper.status_error = 0;
1339
1340 /* return some buffers to hardware, one at a time is too slow */
1341 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1342 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1343 cleaned_count = 0;
1344 }
1345
1346 /* use prefetched values */
1347 rx_desc = next_rxd;
1348 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1349
1350 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1351 }
1352
1353 rx_ring->next_to_clean = i;
1354 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1355
1356 if (cleaned_count)
1357 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1358
1359 #ifdef IXGBE_FCOE
1360 /* include DDPed FCoE data */
1361 if (ddp_bytes > 0) {
1362 unsigned int mss;
1363
1364 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1365 sizeof(struct fc_frame_header) -
1366 sizeof(struct fcoe_crc_eof);
1367 if (mss > 512)
1368 mss &= ~511;
1369 total_rx_bytes += ddp_bytes;
1370 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1371 }
1372 #endif /* IXGBE_FCOE */
1373
1374 rx_ring->total_packets += total_rx_packets;
1375 rx_ring->total_bytes += total_rx_bytes;
1376 netdev->stats.rx_bytes += total_rx_bytes;
1377 netdev->stats.rx_packets += total_rx_packets;
1378
1379 return cleaned;
1380 }
1381
1382 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1383 /**
1384 * ixgbe_configure_msix - Configure MSI-X hardware
1385 * @adapter: board private structure
1386 *
1387 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1388 * interrupts.
1389 **/
1390 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1391 {
1392 struct ixgbe_q_vector *q_vector;
1393 int i, j, q_vectors, v_idx, r_idx;
1394 u32 mask;
1395
1396 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1397
1398 /*
1399 * Populate the IVAR table and set the ITR values to the
1400 * corresponding register.
1401 */
1402 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1403 q_vector = adapter->q_vector[v_idx];
1404 /* XXX for_each_set_bit(...) */
1405 r_idx = find_first_bit(q_vector->rxr_idx,
1406 adapter->num_rx_queues);
1407
1408 for (i = 0; i < q_vector->rxr_count; i++) {
1409 j = adapter->rx_ring[r_idx]->reg_idx;
1410 ixgbe_set_ivar(adapter, 0, j, v_idx);
1411 r_idx = find_next_bit(q_vector->rxr_idx,
1412 adapter->num_rx_queues,
1413 r_idx + 1);
1414 }
1415 r_idx = find_first_bit(q_vector->txr_idx,
1416 adapter->num_tx_queues);
1417
1418 for (i = 0; i < q_vector->txr_count; i++) {
1419 j = adapter->tx_ring[r_idx]->reg_idx;
1420 ixgbe_set_ivar(adapter, 1, j, v_idx);
1421 r_idx = find_next_bit(q_vector->txr_idx,
1422 adapter->num_tx_queues,
1423 r_idx + 1);
1424 }
1425
1426 if (q_vector->txr_count && !q_vector->rxr_count)
1427 /* tx only */
1428 q_vector->eitr = adapter->tx_eitr_param;
1429 else if (q_vector->rxr_count)
1430 /* rx or mixed */
1431 q_vector->eitr = adapter->rx_eitr_param;
1432
1433 ixgbe_write_eitr(q_vector);
1434 }
1435
1436 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1437 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1438 v_idx);
1439 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1440 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1441 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1442
1443 /* set up to autoclear timer, and the vectors */
1444 mask = IXGBE_EIMS_ENABLE_MASK;
1445 if (adapter->num_vfs)
1446 mask &= ~(IXGBE_EIMS_OTHER |
1447 IXGBE_EIMS_MAILBOX |
1448 IXGBE_EIMS_LSC);
1449 else
1450 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1451 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1452 }
1453
1454 enum latency_range {
1455 lowest_latency = 0,
1456 low_latency = 1,
1457 bulk_latency = 2,
1458 latency_invalid = 255
1459 };
1460
1461 /**
1462 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1463 * @adapter: pointer to adapter
1464 * @eitr: eitr setting (ints per sec) to give last timeslice
1465 * @itr_setting: current throttle rate in ints/second
1466 * @packets: the number of packets during this measurement interval
1467 * @bytes: the number of bytes during this measurement interval
1468 *
1469 * Stores a new ITR value based on packets and byte
1470 * counts during the last interrupt. The advantage of per interrupt
1471 * computation is faster updates and more accurate ITR for the current
1472 * traffic pattern. Constants in this function were computed
1473 * based on theoretical maximum wire speed and thresholds were set based
1474 * on testing data as well as attempting to minimize response time
1475 * while increasing bulk throughput.
1476 * this functionality is controlled by the InterruptThrottleRate module
1477 * parameter (see ixgbe_param.c)
1478 **/
1479 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1480 u32 eitr, u8 itr_setting,
1481 int packets, int bytes)
1482 {
1483 unsigned int retval = itr_setting;
1484 u32 timepassed_us;
1485 u64 bytes_perint;
1486
1487 if (packets == 0)
1488 goto update_itr_done;
1489
1490
1491 /* simple throttlerate management
1492 * 0-20MB/s lowest (100000 ints/s)
1493 * 20-100MB/s low (20000 ints/s)
1494 * 100-1249MB/s bulk (8000 ints/s)
1495 */
1496 /* what was last interrupt timeslice? */
1497 timepassed_us = 1000000/eitr;
1498 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1499
1500 switch (itr_setting) {
1501 case lowest_latency:
1502 if (bytes_perint > adapter->eitr_low)
1503 retval = low_latency;
1504 break;
1505 case low_latency:
1506 if (bytes_perint > adapter->eitr_high)
1507 retval = bulk_latency;
1508 else if (bytes_perint <= adapter->eitr_low)
1509 retval = lowest_latency;
1510 break;
1511 case bulk_latency:
1512 if (bytes_perint <= adapter->eitr_high)
1513 retval = low_latency;
1514 break;
1515 }
1516
1517 update_itr_done:
1518 return retval;
1519 }
1520
1521 /**
1522 * ixgbe_write_eitr - write EITR register in hardware specific way
1523 * @q_vector: structure containing interrupt and ring information
1524 *
1525 * This function is made to be called by ethtool and by the driver
1526 * when it needs to update EITR registers at runtime. Hardware
1527 * specific quirks/differences are taken care of here.
1528 */
1529 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1530 {
1531 struct ixgbe_adapter *adapter = q_vector->adapter;
1532 struct ixgbe_hw *hw = &adapter->hw;
1533 int v_idx = q_vector->v_idx;
1534 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1535
1536 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1537 /* must write high and low 16 bits to reset counter */
1538 itr_reg |= (itr_reg << 16);
1539 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1540 /*
1541 * 82599 can support a value of zero, so allow it for
1542 * max interrupt rate, but there is an errata where it can
1543 * not be zero with RSC
1544 */
1545 if (itr_reg == 8 &&
1546 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1547 itr_reg = 0;
1548
1549 /*
1550 * set the WDIS bit to not clear the timer bits and cause an
1551 * immediate assertion of the interrupt
1552 */
1553 itr_reg |= IXGBE_EITR_CNT_WDIS;
1554 }
1555 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1556 }
1557
1558 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1559 {
1560 struct ixgbe_adapter *adapter = q_vector->adapter;
1561 u32 new_itr;
1562 u8 current_itr, ret_itr;
1563 int i, r_idx;
1564 struct ixgbe_ring *rx_ring, *tx_ring;
1565
1566 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1567 for (i = 0; i < q_vector->txr_count; i++) {
1568 tx_ring = adapter->tx_ring[r_idx];
1569 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1570 q_vector->tx_itr,
1571 tx_ring->total_packets,
1572 tx_ring->total_bytes);
1573 /* if the result for this queue would decrease interrupt
1574 * rate for this vector then use that result */
1575 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1576 q_vector->tx_itr - 1 : ret_itr);
1577 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1578 r_idx + 1);
1579 }
1580
1581 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1582 for (i = 0; i < q_vector->rxr_count; i++) {
1583 rx_ring = adapter->rx_ring[r_idx];
1584 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1585 q_vector->rx_itr,
1586 rx_ring->total_packets,
1587 rx_ring->total_bytes);
1588 /* if the result for this queue would decrease interrupt
1589 * rate for this vector then use that result */
1590 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1591 q_vector->rx_itr - 1 : ret_itr);
1592 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1593 r_idx + 1);
1594 }
1595
1596 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1597
1598 switch (current_itr) {
1599 /* counts and packets in update_itr are dependent on these numbers */
1600 case lowest_latency:
1601 new_itr = 100000;
1602 break;
1603 case low_latency:
1604 new_itr = 20000; /* aka hwitr = ~200 */
1605 break;
1606 case bulk_latency:
1607 default:
1608 new_itr = 8000;
1609 break;
1610 }
1611
1612 if (new_itr != q_vector->eitr) {
1613 /* do an exponential smoothing */
1614 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1615
1616 /* save the algorithm value here, not the smoothed one */
1617 q_vector->eitr = new_itr;
1618
1619 ixgbe_write_eitr(q_vector);
1620 }
1621 }
1622
1623 /**
1624 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1625 * @work: pointer to work_struct containing our data
1626 **/
1627 static void ixgbe_check_overtemp_task(struct work_struct *work)
1628 {
1629 struct ixgbe_adapter *adapter = container_of(work,
1630 struct ixgbe_adapter,
1631 check_overtemp_task);
1632 struct ixgbe_hw *hw = &adapter->hw;
1633 u32 eicr = adapter->interrupt_event;
1634
1635 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
1636 switch (hw->device_id) {
1637 case IXGBE_DEV_ID_82599_T3_LOM: {
1638 u32 autoneg;
1639 bool link_up = false;
1640
1641 if (hw->mac.ops.check_link)
1642 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1643
1644 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1645 (eicr & IXGBE_EICR_LSC))
1646 /* Check if this is due to overtemp */
1647 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1648 break;
1649 }
1650 return;
1651 default:
1652 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1653 return;
1654 break;
1655 }
1656 DPRINTK(DRV, ERR, "Network adapter has been stopped because it "
1657 "has over heated. Restart the computer. If the problem "
1658 "persists, power off the system and replace the "
1659 "adapter\n");
1660 /* write to clear the interrupt */
1661 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1662 }
1663 }
1664
1665 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1666 {
1667 struct ixgbe_hw *hw = &adapter->hw;
1668
1669 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1670 (eicr & IXGBE_EICR_GPI_SDP1)) {
1671 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1672 /* write to clear the interrupt */
1673 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1674 }
1675 }
1676
1677 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1678 {
1679 struct ixgbe_hw *hw = &adapter->hw;
1680
1681 if (eicr & IXGBE_EICR_GPI_SDP1) {
1682 /* Clear the interrupt */
1683 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1684 schedule_work(&adapter->multispeed_fiber_task);
1685 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1686 /* Clear the interrupt */
1687 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1688 schedule_work(&adapter->sfp_config_module_task);
1689 } else {
1690 /* Interrupt isn't for us... */
1691 return;
1692 }
1693 }
1694
1695 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1696 {
1697 struct ixgbe_hw *hw = &adapter->hw;
1698
1699 adapter->lsc_int++;
1700 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1701 adapter->link_check_timeout = jiffies;
1702 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1703 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1704 IXGBE_WRITE_FLUSH(hw);
1705 schedule_work(&adapter->watchdog_task);
1706 }
1707 }
1708
1709 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1710 {
1711 struct net_device *netdev = data;
1712 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1713 struct ixgbe_hw *hw = &adapter->hw;
1714 u32 eicr;
1715
1716 /*
1717 * Workaround for Silicon errata. Use clear-by-write instead
1718 * of clear-by-read. Reading with EICS will return the
1719 * interrupt causes without clearing, which later be done
1720 * with the write to EICR.
1721 */
1722 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1723 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1724
1725 if (eicr & IXGBE_EICR_LSC)
1726 ixgbe_check_lsc(adapter);
1727
1728 if (eicr & IXGBE_EICR_MAILBOX)
1729 ixgbe_msg_task(adapter);
1730
1731 if (hw->mac.type == ixgbe_mac_82598EB)
1732 ixgbe_check_fan_failure(adapter, eicr);
1733
1734 if (hw->mac.type == ixgbe_mac_82599EB) {
1735 ixgbe_check_sfp_event(adapter, eicr);
1736 adapter->interrupt_event = eicr;
1737 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1738 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1739 schedule_work(&adapter->check_overtemp_task);
1740
1741 /* Handle Flow Director Full threshold interrupt */
1742 if (eicr & IXGBE_EICR_FLOW_DIR) {
1743 int i;
1744 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1745 /* Disable transmits before FDIR Re-initialization */
1746 netif_tx_stop_all_queues(netdev);
1747 for (i = 0; i < adapter->num_tx_queues; i++) {
1748 struct ixgbe_ring *tx_ring =
1749 adapter->tx_ring[i];
1750 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1751 &tx_ring->reinit_state))
1752 schedule_work(&adapter->fdir_reinit_task);
1753 }
1754 }
1755 }
1756 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1757 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1758
1759 return IRQ_HANDLED;
1760 }
1761
1762 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1763 u64 qmask)
1764 {
1765 u32 mask;
1766
1767 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1768 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1769 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1770 } else {
1771 mask = (qmask & 0xFFFFFFFF);
1772 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1773 mask = (qmask >> 32);
1774 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1775 }
1776 /* skip the flush */
1777 }
1778
1779 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1780 u64 qmask)
1781 {
1782 u32 mask;
1783
1784 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1785 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1786 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1787 } else {
1788 mask = (qmask & 0xFFFFFFFF);
1789 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1790 mask = (qmask >> 32);
1791 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1792 }
1793 /* skip the flush */
1794 }
1795
1796 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1797 {
1798 struct ixgbe_q_vector *q_vector = data;
1799 struct ixgbe_adapter *adapter = q_vector->adapter;
1800 struct ixgbe_ring *tx_ring;
1801 int i, r_idx;
1802
1803 if (!q_vector->txr_count)
1804 return IRQ_HANDLED;
1805
1806 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1807 for (i = 0; i < q_vector->txr_count; i++) {
1808 tx_ring = adapter->tx_ring[r_idx];
1809 tx_ring->total_bytes = 0;
1810 tx_ring->total_packets = 0;
1811 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1812 r_idx + 1);
1813 }
1814
1815 /* EIAM disabled interrupts (on this vector) for us */
1816 napi_schedule(&q_vector->napi);
1817
1818 return IRQ_HANDLED;
1819 }
1820
1821 /**
1822 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1823 * @irq: unused
1824 * @data: pointer to our q_vector struct for this interrupt vector
1825 **/
1826 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1827 {
1828 struct ixgbe_q_vector *q_vector = data;
1829 struct ixgbe_adapter *adapter = q_vector->adapter;
1830 struct ixgbe_ring *rx_ring;
1831 int r_idx;
1832 int i;
1833
1834 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1835 for (i = 0; i < q_vector->rxr_count; i++) {
1836 rx_ring = adapter->rx_ring[r_idx];
1837 rx_ring->total_bytes = 0;
1838 rx_ring->total_packets = 0;
1839 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1840 r_idx + 1);
1841 }
1842
1843 if (!q_vector->rxr_count)
1844 return IRQ_HANDLED;
1845
1846 /* disable interrupts on this vector only */
1847 /* EIAM disabled interrupts (on this vector) for us */
1848 napi_schedule(&q_vector->napi);
1849
1850 return IRQ_HANDLED;
1851 }
1852
1853 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1854 {
1855 struct ixgbe_q_vector *q_vector = data;
1856 struct ixgbe_adapter *adapter = q_vector->adapter;
1857 struct ixgbe_ring *ring;
1858 int r_idx;
1859 int i;
1860
1861 if (!q_vector->txr_count && !q_vector->rxr_count)
1862 return IRQ_HANDLED;
1863
1864 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1865 for (i = 0; i < q_vector->txr_count; i++) {
1866 ring = adapter->tx_ring[r_idx];
1867 ring->total_bytes = 0;
1868 ring->total_packets = 0;
1869 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1870 r_idx + 1);
1871 }
1872
1873 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1874 for (i = 0; i < q_vector->rxr_count; i++) {
1875 ring = adapter->rx_ring[r_idx];
1876 ring->total_bytes = 0;
1877 ring->total_packets = 0;
1878 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1879 r_idx + 1);
1880 }
1881
1882 /* EIAM disabled interrupts (on this vector) for us */
1883 napi_schedule(&q_vector->napi);
1884
1885 return IRQ_HANDLED;
1886 }
1887
1888 /**
1889 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1890 * @napi: napi struct with our devices info in it
1891 * @budget: amount of work driver is allowed to do this pass, in packets
1892 *
1893 * This function is optimized for cleaning one queue only on a single
1894 * q_vector!!!
1895 **/
1896 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1897 {
1898 struct ixgbe_q_vector *q_vector =
1899 container_of(napi, struct ixgbe_q_vector, napi);
1900 struct ixgbe_adapter *adapter = q_vector->adapter;
1901 struct ixgbe_ring *rx_ring = NULL;
1902 int work_done = 0;
1903 long r_idx;
1904
1905 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1906 rx_ring = adapter->rx_ring[r_idx];
1907 #ifdef CONFIG_IXGBE_DCA
1908 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1909 ixgbe_update_rx_dca(adapter, rx_ring);
1910 #endif
1911
1912 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1913
1914 /* If all Rx work done, exit the polling mode */
1915 if (work_done < budget) {
1916 napi_complete(napi);
1917 if (adapter->rx_itr_setting & 1)
1918 ixgbe_set_itr_msix(q_vector);
1919 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1920 ixgbe_irq_enable_queues(adapter,
1921 ((u64)1 << q_vector->v_idx));
1922 }
1923
1924 return work_done;
1925 }
1926
1927 /**
1928 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1929 * @napi: napi struct with our devices info in it
1930 * @budget: amount of work driver is allowed to do this pass, in packets
1931 *
1932 * This function will clean more than one rx queue associated with a
1933 * q_vector.
1934 **/
1935 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1936 {
1937 struct ixgbe_q_vector *q_vector =
1938 container_of(napi, struct ixgbe_q_vector, napi);
1939 struct ixgbe_adapter *adapter = q_vector->adapter;
1940 struct ixgbe_ring *ring = NULL;
1941 int work_done = 0, i;
1942 long r_idx;
1943 bool tx_clean_complete = true;
1944
1945 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1946 for (i = 0; i < q_vector->txr_count; i++) {
1947 ring = adapter->tx_ring[r_idx];
1948 #ifdef CONFIG_IXGBE_DCA
1949 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1950 ixgbe_update_tx_dca(adapter, ring);
1951 #endif
1952 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1953 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1954 r_idx + 1);
1955 }
1956
1957 /* attempt to distribute budget to each queue fairly, but don't allow
1958 * the budget to go below 1 because we'll exit polling */
1959 budget /= (q_vector->rxr_count ?: 1);
1960 budget = max(budget, 1);
1961 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1962 for (i = 0; i < q_vector->rxr_count; i++) {
1963 ring = adapter->rx_ring[r_idx];
1964 #ifdef CONFIG_IXGBE_DCA
1965 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1966 ixgbe_update_rx_dca(adapter, ring);
1967 #endif
1968 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1969 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1970 r_idx + 1);
1971 }
1972
1973 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1974 ring = adapter->rx_ring[r_idx];
1975 /* If all Rx work done, exit the polling mode */
1976 if (work_done < budget) {
1977 napi_complete(napi);
1978 if (adapter->rx_itr_setting & 1)
1979 ixgbe_set_itr_msix(q_vector);
1980 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1981 ixgbe_irq_enable_queues(adapter,
1982 ((u64)1 << q_vector->v_idx));
1983 return 0;
1984 }
1985
1986 return work_done;
1987 }
1988
1989 /**
1990 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1991 * @napi: napi struct with our devices info in it
1992 * @budget: amount of work driver is allowed to do this pass, in packets
1993 *
1994 * This function is optimized for cleaning one queue only on a single
1995 * q_vector!!!
1996 **/
1997 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1998 {
1999 struct ixgbe_q_vector *q_vector =
2000 container_of(napi, struct ixgbe_q_vector, napi);
2001 struct ixgbe_adapter *adapter = q_vector->adapter;
2002 struct ixgbe_ring *tx_ring = NULL;
2003 int work_done = 0;
2004 long r_idx;
2005
2006 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2007 tx_ring = adapter->tx_ring[r_idx];
2008 #ifdef CONFIG_IXGBE_DCA
2009 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2010 ixgbe_update_tx_dca(adapter, tx_ring);
2011 #endif
2012
2013 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2014 work_done = budget;
2015
2016 /* If all Tx work done, exit the polling mode */
2017 if (work_done < budget) {
2018 napi_complete(napi);
2019 if (adapter->tx_itr_setting & 1)
2020 ixgbe_set_itr_msix(q_vector);
2021 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2022 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2023 }
2024
2025 return work_done;
2026 }
2027
2028 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2029 int r_idx)
2030 {
2031 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2032
2033 set_bit(r_idx, q_vector->rxr_idx);
2034 q_vector->rxr_count++;
2035 }
2036
2037 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2038 int t_idx)
2039 {
2040 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2041
2042 set_bit(t_idx, q_vector->txr_idx);
2043 q_vector->txr_count++;
2044 }
2045
2046 /**
2047 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2048 * @adapter: board private structure to initialize
2049 * @vectors: allotted vector count for descriptor rings
2050 *
2051 * This function maps descriptor rings to the queue-specific vectors
2052 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2053 * one vector per ring/queue, but on a constrained vector budget, we
2054 * group the rings as "efficiently" as possible. You would add new
2055 * mapping configurations in here.
2056 **/
2057 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
2058 int vectors)
2059 {
2060 int v_start = 0;
2061 int rxr_idx = 0, txr_idx = 0;
2062 int rxr_remaining = adapter->num_rx_queues;
2063 int txr_remaining = adapter->num_tx_queues;
2064 int i, j;
2065 int rqpv, tqpv;
2066 int err = 0;
2067
2068 /* No mapping required if MSI-X is disabled. */
2069 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2070 goto out;
2071
2072 /*
2073 * The ideal configuration...
2074 * We have enough vectors to map one per queue.
2075 */
2076 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2077 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2078 map_vector_to_rxq(adapter, v_start, rxr_idx);
2079
2080 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2081 map_vector_to_txq(adapter, v_start, txr_idx);
2082
2083 goto out;
2084 }
2085
2086 /*
2087 * If we don't have enough vectors for a 1-to-1
2088 * mapping, we'll have to group them so there are
2089 * multiple queues per vector.
2090 */
2091 /* Re-adjusting *qpv takes care of the remainder. */
2092 for (i = v_start; i < vectors; i++) {
2093 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2094 for (j = 0; j < rqpv; j++) {
2095 map_vector_to_rxq(adapter, i, rxr_idx);
2096 rxr_idx++;
2097 rxr_remaining--;
2098 }
2099 }
2100 for (i = v_start; i < vectors; i++) {
2101 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2102 for (j = 0; j < tqpv; j++) {
2103 map_vector_to_txq(adapter, i, txr_idx);
2104 txr_idx++;
2105 txr_remaining--;
2106 }
2107 }
2108
2109 out:
2110 return err;
2111 }
2112
2113 /**
2114 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2115 * @adapter: board private structure
2116 *
2117 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2118 * interrupts from the kernel.
2119 **/
2120 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2121 {
2122 struct net_device *netdev = adapter->netdev;
2123 irqreturn_t (*handler)(int, void *);
2124 int i, vector, q_vectors, err;
2125 int ri=0, ti=0;
2126
2127 /* Decrement for Other and TCP Timer vectors */
2128 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2129
2130 /* Map the Tx/Rx rings to the vectors we were allotted. */
2131 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2132 if (err)
2133 goto out;
2134
2135 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2136 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2137 &ixgbe_msix_clean_many)
2138 for (vector = 0; vector < q_vectors; vector++) {
2139 handler = SET_HANDLER(adapter->q_vector[vector]);
2140
2141 if(handler == &ixgbe_msix_clean_rx) {
2142 sprintf(adapter->name[vector], "%s-%s-%d",
2143 netdev->name, "rx", ri++);
2144 }
2145 else if(handler == &ixgbe_msix_clean_tx) {
2146 sprintf(adapter->name[vector], "%s-%s-%d",
2147 netdev->name, "tx", ti++);
2148 }
2149 else
2150 sprintf(adapter->name[vector], "%s-%s-%d",
2151 netdev->name, "TxRx", vector);
2152
2153 err = request_irq(adapter->msix_entries[vector].vector,
2154 handler, 0, adapter->name[vector],
2155 adapter->q_vector[vector]);
2156 if (err) {
2157 DPRINTK(PROBE, ERR,
2158 "request_irq failed for MSIX interrupt "
2159 "Error: %d\n", err);
2160 goto free_queue_irqs;
2161 }
2162 }
2163
2164 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2165 err = request_irq(adapter->msix_entries[vector].vector,
2166 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
2167 if (err) {
2168 DPRINTK(PROBE, ERR,
2169 "request_irq for msix_lsc failed: %d\n", err);
2170 goto free_queue_irqs;
2171 }
2172
2173 return 0;
2174
2175 free_queue_irqs:
2176 for (i = vector - 1; i >= 0; i--)
2177 free_irq(adapter->msix_entries[--vector].vector,
2178 adapter->q_vector[i]);
2179 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2180 pci_disable_msix(adapter->pdev);
2181 kfree(adapter->msix_entries);
2182 adapter->msix_entries = NULL;
2183 out:
2184 return err;
2185 }
2186
2187 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2188 {
2189 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2190 u8 current_itr;
2191 u32 new_itr = q_vector->eitr;
2192 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2193 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2194
2195 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2196 q_vector->tx_itr,
2197 tx_ring->total_packets,
2198 tx_ring->total_bytes);
2199 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2200 q_vector->rx_itr,
2201 rx_ring->total_packets,
2202 rx_ring->total_bytes);
2203
2204 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2205
2206 switch (current_itr) {
2207 /* counts and packets in update_itr are dependent on these numbers */
2208 case lowest_latency:
2209 new_itr = 100000;
2210 break;
2211 case low_latency:
2212 new_itr = 20000; /* aka hwitr = ~200 */
2213 break;
2214 case bulk_latency:
2215 new_itr = 8000;
2216 break;
2217 default:
2218 break;
2219 }
2220
2221 if (new_itr != q_vector->eitr) {
2222 /* do an exponential smoothing */
2223 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
2224
2225 /* save the algorithm value here, not the smoothed one */
2226 q_vector->eitr = new_itr;
2227
2228 ixgbe_write_eitr(q_vector);
2229 }
2230 }
2231
2232 /**
2233 * ixgbe_irq_enable - Enable default interrupt generation settings
2234 * @adapter: board private structure
2235 **/
2236 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
2237 {
2238 u32 mask;
2239
2240 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2241 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2242 mask |= IXGBE_EIMS_GPI_SDP0;
2243 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2244 mask |= IXGBE_EIMS_GPI_SDP1;
2245 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2246 mask |= IXGBE_EIMS_ECC;
2247 mask |= IXGBE_EIMS_GPI_SDP1;
2248 mask |= IXGBE_EIMS_GPI_SDP2;
2249 if (adapter->num_vfs)
2250 mask |= IXGBE_EIMS_MAILBOX;
2251 }
2252 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2253 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2254 mask |= IXGBE_EIMS_FLOW_DIR;
2255
2256 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2257 ixgbe_irq_enable_queues(adapter, ~0);
2258 IXGBE_WRITE_FLUSH(&adapter->hw);
2259
2260 if (adapter->num_vfs > 32) {
2261 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2262 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2263 }
2264 }
2265
2266 /**
2267 * ixgbe_intr - legacy mode Interrupt Handler
2268 * @irq: interrupt number
2269 * @data: pointer to a network interface device structure
2270 **/
2271 static irqreturn_t ixgbe_intr(int irq, void *data)
2272 {
2273 struct net_device *netdev = data;
2274 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2275 struct ixgbe_hw *hw = &adapter->hw;
2276 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2277 u32 eicr;
2278
2279 /*
2280 * Workaround for silicon errata. Mask the interrupts
2281 * before the read of EICR.
2282 */
2283 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2284
2285 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2286 * therefore no explict interrupt disable is necessary */
2287 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2288 if (!eicr) {
2289 /* shared interrupt alert!
2290 * make sure interrupts are enabled because the read will
2291 * have disabled interrupts due to EIAM */
2292 ixgbe_irq_enable(adapter);
2293 return IRQ_NONE; /* Not our interrupt */
2294 }
2295
2296 if (eicr & IXGBE_EICR_LSC)
2297 ixgbe_check_lsc(adapter);
2298
2299 if (hw->mac.type == ixgbe_mac_82599EB)
2300 ixgbe_check_sfp_event(adapter, eicr);
2301
2302 ixgbe_check_fan_failure(adapter, eicr);
2303 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2304 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2305 schedule_work(&adapter->check_overtemp_task);
2306
2307 if (napi_schedule_prep(&(q_vector->napi))) {
2308 adapter->tx_ring[0]->total_packets = 0;
2309 adapter->tx_ring[0]->total_bytes = 0;
2310 adapter->rx_ring[0]->total_packets = 0;
2311 adapter->rx_ring[0]->total_bytes = 0;
2312 /* would disable interrupts here but EIAM disabled it */
2313 __napi_schedule(&(q_vector->napi));
2314 }
2315
2316 return IRQ_HANDLED;
2317 }
2318
2319 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2320 {
2321 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2322
2323 for (i = 0; i < q_vectors; i++) {
2324 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2325 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2326 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2327 q_vector->rxr_count = 0;
2328 q_vector->txr_count = 0;
2329 }
2330 }
2331
2332 /**
2333 * ixgbe_request_irq - initialize interrupts
2334 * @adapter: board private structure
2335 *
2336 * Attempts to configure interrupts using the best available
2337 * capabilities of the hardware and kernel.
2338 **/
2339 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2340 {
2341 struct net_device *netdev = adapter->netdev;
2342 int err;
2343
2344 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2345 err = ixgbe_request_msix_irqs(adapter);
2346 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2347 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2348 netdev->name, netdev);
2349 } else {
2350 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2351 netdev->name, netdev);
2352 }
2353
2354 if (err)
2355 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
2356
2357 return err;
2358 }
2359
2360 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2361 {
2362 struct net_device *netdev = adapter->netdev;
2363
2364 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2365 int i, q_vectors;
2366
2367 q_vectors = adapter->num_msix_vectors;
2368
2369 i = q_vectors - 1;
2370 free_irq(adapter->msix_entries[i].vector, netdev);
2371
2372 i--;
2373 for (; i >= 0; i--) {
2374 free_irq(adapter->msix_entries[i].vector,
2375 adapter->q_vector[i]);
2376 }
2377
2378 ixgbe_reset_q_vectors(adapter);
2379 } else {
2380 free_irq(adapter->pdev->irq, netdev);
2381 }
2382 }
2383
2384 /**
2385 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2386 * @adapter: board private structure
2387 **/
2388 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2389 {
2390 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2391 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2392 } else {
2393 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2394 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2395 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2396 if (adapter->num_vfs > 32)
2397 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2398 }
2399 IXGBE_WRITE_FLUSH(&adapter->hw);
2400 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2401 int i;
2402 for (i = 0; i < adapter->num_msix_vectors; i++)
2403 synchronize_irq(adapter->msix_entries[i].vector);
2404 } else {
2405 synchronize_irq(adapter->pdev->irq);
2406 }
2407 }
2408
2409 /**
2410 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2411 *
2412 **/
2413 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2414 {
2415 struct ixgbe_hw *hw = &adapter->hw;
2416
2417 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2418 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2419
2420 ixgbe_set_ivar(adapter, 0, 0, 0);
2421 ixgbe_set_ivar(adapter, 1, 0, 0);
2422
2423 map_vector_to_rxq(adapter, 0, 0);
2424 map_vector_to_txq(adapter, 0, 0);
2425
2426 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
2427 }
2428
2429 /**
2430 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2431 * @adapter: board private structure
2432 *
2433 * Configure the Tx unit of the MAC after a reset.
2434 **/
2435 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2436 {
2437 u64 tdba;
2438 struct ixgbe_hw *hw = &adapter->hw;
2439 u32 i, j, tdlen, txctrl;
2440
2441 /* Setup the HW Tx Head and Tail descriptor pointers */
2442 for (i = 0; i < adapter->num_tx_queues; i++) {
2443 struct ixgbe_ring *ring = adapter->tx_ring[i];
2444 j = ring->reg_idx;
2445 tdba = ring->dma;
2446 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
2447 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
2448 (tdba & DMA_BIT_MASK(32)));
2449 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
2450 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
2451 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
2452 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
2453 adapter->tx_ring[i]->head = IXGBE_TDH(j);
2454 adapter->tx_ring[i]->tail = IXGBE_TDT(j);
2455 /*
2456 * Disable Tx Head Writeback RO bit, since this hoses
2457 * bookkeeping if things aren't delivered in order.
2458 */
2459 switch (hw->mac.type) {
2460 case ixgbe_mac_82598EB:
2461 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
2462 break;
2463 case ixgbe_mac_82599EB:
2464 default:
2465 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
2466 break;
2467 }
2468 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
2469 switch (hw->mac.type) {
2470 case ixgbe_mac_82598EB:
2471 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
2472 break;
2473 case ixgbe_mac_82599EB:
2474 default:
2475 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
2476 break;
2477 }
2478 }
2479
2480 if (hw->mac.type == ixgbe_mac_82599EB) {
2481 u32 rttdcs;
2482 u32 mask;
2483
2484 /* disable the arbiter while setting MTQC */
2485 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2486 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2487 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2488
2489 /* set transmit pool layout */
2490 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2491 switch (adapter->flags & mask) {
2492
2493 case (IXGBE_FLAG_SRIOV_ENABLED):
2494 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2495 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2496 break;
2497
2498 case (IXGBE_FLAG_DCB_ENABLED):
2499 /* We enable 8 traffic classes, DCB only */
2500 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2501 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2502 break;
2503
2504 default:
2505 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2506 break;
2507 }
2508
2509 /* re-eable the arbiter */
2510 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2511 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2512 }
2513 }
2514
2515 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2516
2517 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2518 struct ixgbe_ring *rx_ring)
2519 {
2520 u32 srrctl;
2521 int index;
2522 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2523
2524 index = rx_ring->reg_idx;
2525 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2526 unsigned long mask;
2527 mask = (unsigned long) feature[RING_F_RSS].mask;
2528 index = index & mask;
2529 }
2530 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2531
2532 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2533 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2534
2535 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2536 IXGBE_SRRCTL_BSIZEHDR_MASK;
2537
2538 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2539 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2540 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2541 #else
2542 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2543 #endif
2544 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2545 } else {
2546 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2547 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2548 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2549 }
2550
2551 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2552 }
2553
2554 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2555 {
2556 u32 mrqc = 0;
2557 int mask;
2558
2559 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2560 return mrqc;
2561
2562 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2563 #ifdef CONFIG_IXGBE_DCB
2564 | IXGBE_FLAG_DCB_ENABLED
2565 #endif
2566 | IXGBE_FLAG_SRIOV_ENABLED
2567 );
2568
2569 switch (mask) {
2570 case (IXGBE_FLAG_RSS_ENABLED):
2571 mrqc = IXGBE_MRQC_RSSEN;
2572 break;
2573 case (IXGBE_FLAG_SRIOV_ENABLED):
2574 mrqc = IXGBE_MRQC_VMDQEN;
2575 break;
2576 #ifdef CONFIG_IXGBE_DCB
2577 case (IXGBE_FLAG_DCB_ENABLED):
2578 mrqc = IXGBE_MRQC_RT8TCEN;
2579 break;
2580 #endif /* CONFIG_IXGBE_DCB */
2581 default:
2582 break;
2583 }
2584
2585 return mrqc;
2586 }
2587
2588 /**
2589 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2590 * @adapter: address of board private structure
2591 * @index: index of ring to set
2592 **/
2593 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
2594 {
2595 struct ixgbe_ring *rx_ring;
2596 struct ixgbe_hw *hw = &adapter->hw;
2597 int j;
2598 u32 rscctrl;
2599 int rx_buf_len;
2600
2601 rx_ring = adapter->rx_ring[index];
2602 j = rx_ring->reg_idx;
2603 rx_buf_len = rx_ring->rx_buf_len;
2604 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2605 rscctrl |= IXGBE_RSCCTL_RSCEN;
2606 /*
2607 * we must limit the number of descriptors so that the
2608 * total size of max desc * buf_len is not greater
2609 * than 65535
2610 */
2611 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2612 #if (MAX_SKB_FRAGS > 16)
2613 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2614 #elif (MAX_SKB_FRAGS > 8)
2615 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2616 #elif (MAX_SKB_FRAGS > 4)
2617 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2618 #else
2619 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2620 #endif
2621 } else {
2622 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2623 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2624 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2625 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2626 else
2627 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2628 }
2629 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2630 }
2631
2632 /**
2633 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2634 * @adapter: board private structure
2635 *
2636 * Configure the Rx unit of the MAC after a reset.
2637 **/
2638 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2639 {
2640 u64 rdba;
2641 struct ixgbe_hw *hw = &adapter->hw;
2642 struct ixgbe_ring *rx_ring;
2643 struct net_device *netdev = adapter->netdev;
2644 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2645 int i, j;
2646 u32 rdlen, rxctrl, rxcsum;
2647 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2648 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2649 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2650 u32 fctrl, hlreg0;
2651 u32 reta = 0, mrqc = 0;
2652 u32 rdrxctl;
2653 int rx_buf_len;
2654
2655 /* Decide whether to use packet split mode or not */
2656 /* Do not use packet split if we're in SR-IOV Mode */
2657 if (!adapter->num_vfs)
2658 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2659
2660 /* Set the RX buffer length according to the mode */
2661 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2662 rx_buf_len = IXGBE_RX_HDR_SIZE;
2663 if (hw->mac.type == ixgbe_mac_82599EB) {
2664 /* PSRTYPE must be initialized in 82599 */
2665 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2666 IXGBE_PSRTYPE_UDPHDR |
2667 IXGBE_PSRTYPE_IPV4HDR |
2668 IXGBE_PSRTYPE_IPV6HDR |
2669 IXGBE_PSRTYPE_L2HDR;
2670 IXGBE_WRITE_REG(hw,
2671 IXGBE_PSRTYPE(adapter->num_vfs),
2672 psrtype);
2673 }
2674 } else {
2675 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2676 (netdev->mtu <= ETH_DATA_LEN))
2677 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2678 else
2679 rx_buf_len = ALIGN(max_frame, 1024);
2680 }
2681
2682 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2683 fctrl |= IXGBE_FCTRL_BAM;
2684 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2685 fctrl |= IXGBE_FCTRL_PMCF;
2686 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2687
2688 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2689 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2690 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2691 else
2692 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2693 #ifdef IXGBE_FCOE
2694 if (netdev->features & NETIF_F_FCOE_MTU)
2695 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2696 #endif
2697 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2698
2699 rdlen = adapter->rx_ring[0]->count * sizeof(union ixgbe_adv_rx_desc);
2700 /* disable receives while setting up the descriptors */
2701 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2702 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2703
2704 /*
2705 * Setup the HW Rx Head and Tail Descriptor Pointers and
2706 * the Base and Length of the Rx Descriptor Ring
2707 */
2708 for (i = 0; i < adapter->num_rx_queues; i++) {
2709 rx_ring = adapter->rx_ring[i];
2710 rdba = rx_ring->dma;
2711 j = rx_ring->reg_idx;
2712 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2713 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2714 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2715 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2716 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2717 rx_ring->head = IXGBE_RDH(j);
2718 rx_ring->tail = IXGBE_RDT(j);
2719 rx_ring->rx_buf_len = rx_buf_len;
2720
2721 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2722 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2723 else
2724 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2725
2726 #ifdef IXGBE_FCOE
2727 if (netdev->features & NETIF_F_FCOE_MTU) {
2728 struct ixgbe_ring_feature *f;
2729 f = &adapter->ring_feature[RING_F_FCOE];
2730 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2731 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2732 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2733 rx_ring->rx_buf_len =
2734 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2735 }
2736 }
2737
2738 #endif /* IXGBE_FCOE */
2739 ixgbe_configure_srrctl(adapter, rx_ring);
2740 }
2741
2742 if (hw->mac.type == ixgbe_mac_82598EB) {
2743 /*
2744 * For VMDq support of different descriptor types or
2745 * buffer sizes through the use of multiple SRRCTL
2746 * registers, RDRXCTL.MVMEN must be set to 1
2747 *
2748 * also, the manual doesn't mention it clearly but DCA hints
2749 * will only use queue 0's tags unless this bit is set. Side
2750 * effects of setting this bit are only that SRRCTL must be
2751 * fully programmed [0..15]
2752 */
2753 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2754 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2755 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2756 }
2757
2758 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2759 u32 vt_reg_bits;
2760 u32 reg_offset, vf_shift;
2761 u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2762 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN
2763 | IXGBE_VT_CTL_REPLEN;
2764 vt_reg_bits |= (adapter->num_vfs <<
2765 IXGBE_VT_CTL_POOL_SHIFT);
2766 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2767 IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0);
2768
2769 vf_shift = adapter->num_vfs % 32;
2770 reg_offset = adapter->num_vfs / 32;
2771 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0);
2772 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0);
2773 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0);
2774 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0);
2775 /* Enable only the PF's pool for Tx/Rx */
2776 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2777 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2778 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2779 ixgbe_set_vmolr(hw, adapter->num_vfs, true);
2780 }
2781
2782 /* Program MRQC for the distribution of queues */
2783 mrqc = ixgbe_setup_mrqc(adapter);
2784
2785 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2786 /* Fill out redirection table */
2787 for (i = 0, j = 0; i < 128; i++, j++) {
2788 if (j == adapter->ring_feature[RING_F_RSS].indices)
2789 j = 0;
2790 /* reta = 4-byte sliding window of
2791 * 0x00..(indices-1)(indices-1)00..etc. */
2792 reta = (reta << 8) | (j * 0x11);
2793 if ((i & 3) == 3)
2794 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2795 }
2796
2797 /* Fill out hash function seeds */
2798 for (i = 0; i < 10; i++)
2799 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2800
2801 if (hw->mac.type == ixgbe_mac_82598EB)
2802 mrqc |= IXGBE_MRQC_RSSEN;
2803 /* Perform hash on these packet types */
2804 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2805 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2806 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2807 | IXGBE_MRQC_RSS_FIELD_IPV6
2808 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2809 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2810 }
2811 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2812
2813 if (adapter->num_vfs) {
2814 u32 reg;
2815
2816 /* Map PF MAC address in RAR Entry 0 to first pool
2817 * following VFs */
2818 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2819
2820 /* Set up VF register offsets for selected VT Mode, i.e.
2821 * 64 VFs for SR-IOV */
2822 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2823 reg |= IXGBE_GCR_EXT_SRIOV;
2824 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg);
2825 }
2826
2827 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2828
2829 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2830 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2831 /* Disable indicating checksum in descriptor, enables
2832 * RSS hash */
2833 rxcsum |= IXGBE_RXCSUM_PCSD;
2834 }
2835 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2836 /* Enable IPv4 payload checksum for UDP fragments
2837 * if PCSD is not set */
2838 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2839 }
2840
2841 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2842
2843 if (hw->mac.type == ixgbe_mac_82599EB) {
2844 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2845 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2846 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2847 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2848 }
2849
2850 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2851 /* Enable 82599 HW-RSC */
2852 for (i = 0; i < adapter->num_rx_queues; i++)
2853 ixgbe_configure_rscctl(adapter, i);
2854
2855 /* Disable RSC for ACK packets */
2856 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2857 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2858 }
2859 }
2860
2861 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2862 {
2863 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2864 struct ixgbe_hw *hw = &adapter->hw;
2865 int pool_ndx = adapter->num_vfs;
2866
2867 /* add VID to filter table */
2868 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
2869 }
2870
2871 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2872 {
2873 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2874 struct ixgbe_hw *hw = &adapter->hw;
2875 int pool_ndx = adapter->num_vfs;
2876
2877 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2878 ixgbe_irq_disable(adapter);
2879
2880 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2881
2882 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2883 ixgbe_irq_enable(adapter);
2884
2885 /* remove VID from filter table */
2886 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
2887 }
2888
2889 /**
2890 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
2891 * @adapter: driver data
2892 */
2893 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
2894 {
2895 struct ixgbe_hw *hw = &adapter->hw;
2896 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2897 int i, j;
2898
2899 switch (hw->mac.type) {
2900 case ixgbe_mac_82598EB:
2901 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2902 #ifdef CONFIG_IXGBE_DCB
2903 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
2904 vlnctrl &= ~IXGBE_VLNCTRL_VME;
2905 #endif
2906 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2907 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2908 break;
2909 case ixgbe_mac_82599EB:
2910 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2911 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2912 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2913 #ifdef CONFIG_IXGBE_DCB
2914 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
2915 break;
2916 #endif
2917 for (i = 0; i < adapter->num_rx_queues; i++) {
2918 j = adapter->rx_ring[i]->reg_idx;
2919 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2920 vlnctrl &= ~IXGBE_RXDCTL_VME;
2921 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2922 }
2923 break;
2924 default:
2925 break;
2926 }
2927 }
2928
2929 /**
2930 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
2931 * @adapter: driver data
2932 */
2933 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
2934 {
2935 struct ixgbe_hw *hw = &adapter->hw;
2936 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2937 int i, j;
2938
2939 switch (hw->mac.type) {
2940 case ixgbe_mac_82598EB:
2941 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2942 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2943 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2944 break;
2945 case ixgbe_mac_82599EB:
2946 vlnctrl |= IXGBE_VLNCTRL_VFE;
2947 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2948 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2949 for (i = 0; i < adapter->num_rx_queues; i++) {
2950 j = adapter->rx_ring[i]->reg_idx;
2951 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2952 vlnctrl |= IXGBE_RXDCTL_VME;
2953 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2954 }
2955 break;
2956 default:
2957 break;
2958 }
2959 }
2960
2961 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2962 struct vlan_group *grp)
2963 {
2964 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2965
2966 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2967 ixgbe_irq_disable(adapter);
2968 adapter->vlgrp = grp;
2969
2970 /*
2971 * For a DCB driver, always enable VLAN tag stripping so we can
2972 * still receive traffic from a DCB-enabled host even if we're
2973 * not in DCB mode.
2974 */
2975 ixgbe_vlan_filter_enable(adapter);
2976
2977 ixgbe_vlan_rx_add_vid(netdev, 0);
2978
2979 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2980 ixgbe_irq_enable(adapter);
2981 }
2982
2983 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2984 {
2985 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2986
2987 if (adapter->vlgrp) {
2988 u16 vid;
2989 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2990 if (!vlan_group_get_device(adapter->vlgrp, vid))
2991 continue;
2992 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2993 }
2994 }
2995 }
2996
2997 /**
2998 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2999 * @netdev: network interface device structure
3000 *
3001 * The set_rx_method entry point is called whenever the unicast/multicast
3002 * address list or the network interface flags are updated. This routine is
3003 * responsible for configuring the hardware for proper unicast, multicast and
3004 * promiscuous mode.
3005 **/
3006 void ixgbe_set_rx_mode(struct net_device *netdev)
3007 {
3008 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3009 struct ixgbe_hw *hw = &adapter->hw;
3010 u32 fctrl;
3011
3012 /* Check for Promiscuous and All Multicast modes */
3013
3014 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3015
3016 if (netdev->flags & IFF_PROMISC) {
3017 hw->addr_ctrl.user_set_promisc = true;
3018 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3019 /* don't hardware filter vlans in promisc mode */
3020 ixgbe_vlan_filter_disable(adapter);
3021 } else {
3022 if (netdev->flags & IFF_ALLMULTI) {
3023 fctrl |= IXGBE_FCTRL_MPE;
3024 fctrl &= ~IXGBE_FCTRL_UPE;
3025 } else if (!hw->addr_ctrl.uc_set_promisc) {
3026 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3027 }
3028 ixgbe_vlan_filter_enable(adapter);
3029 hw->addr_ctrl.user_set_promisc = false;
3030 }
3031
3032 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3033
3034 /* reprogram secondary unicast list */
3035 hw->mac.ops.update_uc_addr_list(hw, netdev);
3036
3037 /* reprogram multicast list */
3038 hw->mac.ops.update_mc_addr_list(hw, netdev);
3039
3040 if (adapter->num_vfs)
3041 ixgbe_restore_vf_multicasts(adapter);
3042 }
3043
3044 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3045 {
3046 int q_idx;
3047 struct ixgbe_q_vector *q_vector;
3048 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3049
3050 /* legacy and MSI only use one vector */
3051 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3052 q_vectors = 1;
3053
3054 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3055 struct napi_struct *napi;
3056 q_vector = adapter->q_vector[q_idx];
3057 napi = &q_vector->napi;
3058 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3059 if (!q_vector->rxr_count || !q_vector->txr_count) {
3060 if (q_vector->txr_count == 1)
3061 napi->poll = &ixgbe_clean_txonly;
3062 else if (q_vector->rxr_count == 1)
3063 napi->poll = &ixgbe_clean_rxonly;
3064 }
3065 }
3066
3067 napi_enable(napi);
3068 }
3069 }
3070
3071 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3072 {
3073 int q_idx;
3074 struct ixgbe_q_vector *q_vector;
3075 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3076
3077 /* legacy and MSI only use one vector */
3078 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3079 q_vectors = 1;
3080
3081 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3082 q_vector = adapter->q_vector[q_idx];
3083 napi_disable(&q_vector->napi);
3084 }
3085 }
3086
3087 #ifdef CONFIG_IXGBE_DCB
3088 /*
3089 * ixgbe_configure_dcb - Configure DCB hardware
3090 * @adapter: ixgbe adapter struct
3091 *
3092 * This is called by the driver on open to configure the DCB hardware.
3093 * This is also called by the gennetlink interface when reconfiguring
3094 * the DCB state.
3095 */
3096 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3097 {
3098 struct ixgbe_hw *hw = &adapter->hw;
3099 u32 txdctl;
3100 int i, j;
3101
3102 ixgbe_dcb_check_config(&adapter->dcb_cfg);
3103 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
3104 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
3105
3106 /* reconfigure the hardware */
3107 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
3108
3109 for (i = 0; i < adapter->num_tx_queues; i++) {
3110 j = adapter->tx_ring[i]->reg_idx;
3111 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3112 /* PThresh workaround for Tx hang with DFP enabled. */
3113 txdctl |= 32;
3114 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3115 }
3116 /* Enable VLAN tag insert/strip */
3117 ixgbe_vlan_filter_enable(adapter);
3118
3119 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3120 }
3121
3122 #endif
3123 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3124 {
3125 struct net_device *netdev = adapter->netdev;
3126 struct ixgbe_hw *hw = &adapter->hw;
3127 int i;
3128
3129 ixgbe_set_rx_mode(netdev);
3130
3131 ixgbe_restore_vlan(adapter);
3132 #ifdef CONFIG_IXGBE_DCB
3133 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3134 if (hw->mac.type == ixgbe_mac_82598EB)
3135 netif_set_gso_max_size(netdev, 32768);
3136 else
3137 netif_set_gso_max_size(netdev, 65536);
3138 ixgbe_configure_dcb(adapter);
3139 } else {
3140 netif_set_gso_max_size(netdev, 65536);
3141 }
3142 #else
3143 netif_set_gso_max_size(netdev, 65536);
3144 #endif
3145
3146 #ifdef IXGBE_FCOE
3147 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3148 ixgbe_configure_fcoe(adapter);
3149
3150 #endif /* IXGBE_FCOE */
3151 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3152 for (i = 0; i < adapter->num_tx_queues; i++)
3153 adapter->tx_ring[i]->atr_sample_rate =
3154 adapter->atr_sample_rate;
3155 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3156 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3157 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3158 }
3159
3160 ixgbe_configure_tx(adapter);
3161 ixgbe_configure_rx(adapter);
3162 for (i = 0; i < adapter->num_rx_queues; i++)
3163 ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i],
3164 (adapter->rx_ring[i]->count - 1));
3165 }
3166
3167 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3168 {
3169 switch (hw->phy.type) {
3170 case ixgbe_phy_sfp_avago:
3171 case ixgbe_phy_sfp_ftl:
3172 case ixgbe_phy_sfp_intel:
3173 case ixgbe_phy_sfp_unknown:
3174 case ixgbe_phy_sfp_passive_tyco:
3175 case ixgbe_phy_sfp_passive_unknown:
3176 case ixgbe_phy_sfp_active_unknown:
3177 case ixgbe_phy_sfp_ftl_active:
3178 return true;
3179 default:
3180 return false;
3181 }
3182 }
3183
3184 /**
3185 * ixgbe_sfp_link_config - set up SFP+ link
3186 * @adapter: pointer to private adapter struct
3187 **/
3188 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3189 {
3190 struct ixgbe_hw *hw = &adapter->hw;
3191
3192 if (hw->phy.multispeed_fiber) {
3193 /*
3194 * In multispeed fiber setups, the device may not have
3195 * had a physical connection when the driver loaded.
3196 * If that's the case, the initial link configuration
3197 * couldn't get the MAC into 10G or 1G mode, so we'll
3198 * never have a link status change interrupt fire.
3199 * We need to try and force an autonegotiation
3200 * session, then bring up link.
3201 */
3202 hw->mac.ops.setup_sfp(hw);
3203 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3204 schedule_work(&adapter->multispeed_fiber_task);
3205 } else {
3206 /*
3207 * Direct Attach Cu and non-multispeed fiber modules
3208 * still need to be configured properly prior to
3209 * attempting link.
3210 */
3211 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3212 schedule_work(&adapter->sfp_config_module_task);
3213 }
3214 }
3215
3216 /**
3217 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3218 * @hw: pointer to private hardware struct
3219 *
3220 * Returns 0 on success, negative on failure
3221 **/
3222 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3223 {
3224 u32 autoneg;
3225 bool negotiation, link_up = false;
3226 u32 ret = IXGBE_ERR_LINK_SETUP;
3227
3228 if (hw->mac.ops.check_link)
3229 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3230
3231 if (ret)
3232 goto link_cfg_out;
3233
3234 if (hw->mac.ops.get_link_capabilities)
3235 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
3236 if (ret)
3237 goto link_cfg_out;
3238
3239 if (hw->mac.ops.setup_link)
3240 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3241 link_cfg_out:
3242 return ret;
3243 }
3244
3245 #define IXGBE_MAX_RX_DESC_POLL 10
3246 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3247 int rxr)
3248 {
3249 int j = adapter->rx_ring[rxr]->reg_idx;
3250 int k;
3251
3252 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
3253 if (IXGBE_READ_REG(&adapter->hw,
3254 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
3255 break;
3256 else
3257 msleep(1);
3258 }
3259 if (k >= IXGBE_MAX_RX_DESC_POLL) {
3260 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
3261 "not set within the polling period\n", rxr);
3262 }
3263 ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr],
3264 (adapter->rx_ring[rxr]->count - 1));
3265 }
3266
3267 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3268 {
3269 struct net_device *netdev = adapter->netdev;
3270 struct ixgbe_hw *hw = &adapter->hw;
3271 int i, j = 0;
3272 int num_rx_rings = adapter->num_rx_queues;
3273 int err;
3274 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3275 u32 txdctl, rxdctl, mhadd;
3276 u32 dmatxctl;
3277 u32 gpie;
3278 u32 ctrl_ext;
3279
3280 ixgbe_get_hw_control(adapter);
3281
3282 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
3283 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
3284 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3285 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
3286 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
3287 } else {
3288 /* MSI only */
3289 gpie = 0;
3290 }
3291 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3292 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3293 gpie |= IXGBE_GPIE_VTMODE_64;
3294 }
3295 /* XXX: to interrupt immediately for EICS writes, enable this */
3296 /* gpie |= IXGBE_GPIE_EIMEN; */
3297 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3298 }
3299
3300 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3301 /*
3302 * use EIAM to auto-mask when MSI-X interrupt is asserted
3303 * this saves a register write for every interrupt
3304 */
3305 switch (hw->mac.type) {
3306 case ixgbe_mac_82598EB:
3307 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3308 break;
3309 default:
3310 case ixgbe_mac_82599EB:
3311 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3312 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3313 break;
3314 }
3315 } else {
3316 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3317 * specifically only auto mask tx and rx interrupts */
3318 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3319 }
3320
3321 /* Enable Thermal over heat sensor interrupt */
3322 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3323 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3324 gpie |= IXGBE_SDP0_GPIEN;
3325 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3326 }
3327
3328 /* Enable fan failure interrupt if media type is copper */
3329 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3330 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3331 gpie |= IXGBE_SDP1_GPIEN;
3332 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3333 }
3334
3335 if (hw->mac.type == ixgbe_mac_82599EB) {
3336 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3337 gpie |= IXGBE_SDP1_GPIEN;
3338 gpie |= IXGBE_SDP2_GPIEN;
3339 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3340 }
3341
3342 #ifdef IXGBE_FCOE
3343 /* adjust max frame to be able to do baby jumbo for FCoE */
3344 if ((netdev->features & NETIF_F_FCOE_MTU) &&
3345 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3346 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3347
3348 #endif /* IXGBE_FCOE */
3349 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3350 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3351 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3352 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3353
3354 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3355 }
3356
3357 for (i = 0; i < adapter->num_tx_queues; i++) {
3358 j = adapter->tx_ring[i]->reg_idx;
3359 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3360 if (adapter->rx_itr_setting == 0) {
3361 /* cannot set wthresh when itr==0 */
3362 txdctl &= ~0x007F0000;
3363 } else {
3364 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
3365 txdctl |= (8 << 16);
3366 }
3367 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3368 }
3369
3370 if (hw->mac.type == ixgbe_mac_82599EB) {
3371 /* DMATXCTL.EN must be set after all Tx queue config is done */
3372 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3373 dmatxctl |= IXGBE_DMATXCTL_TE;
3374 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3375 }
3376 for (i = 0; i < adapter->num_tx_queues; i++) {
3377 j = adapter->tx_ring[i]->reg_idx;
3378 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3379 txdctl |= IXGBE_TXDCTL_ENABLE;
3380 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3381 if (hw->mac.type == ixgbe_mac_82599EB) {
3382 int wait_loop = 10;
3383 /* poll for Tx Enable ready */
3384 do {
3385 msleep(1);
3386 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3387 } while (--wait_loop &&
3388 !(txdctl & IXGBE_TXDCTL_ENABLE));
3389 if (!wait_loop)
3390 DPRINTK(DRV, ERR, "Could not enable "
3391 "Tx Queue %d\n", j);
3392 }
3393 }
3394
3395 for (i = 0; i < num_rx_rings; i++) {
3396 j = adapter->rx_ring[i]->reg_idx;
3397 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3398 /* enable PTHRESH=32 descriptors (half the internal cache)
3399 * and HTHRESH=0 descriptors (to minimize latency on fetch),
3400 * this also removes a pesky rx_no_buffer_count increment */
3401 rxdctl |= 0x0020;
3402 rxdctl |= IXGBE_RXDCTL_ENABLE;
3403 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
3404 if (hw->mac.type == ixgbe_mac_82599EB)
3405 ixgbe_rx_desc_queue_enable(adapter, i);
3406 }
3407 /* enable all receives */
3408 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3409 if (hw->mac.type == ixgbe_mac_82598EB)
3410 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
3411 else
3412 rxdctl |= IXGBE_RXCTRL_RXEN;
3413 hw->mac.ops.enable_rx_dma(hw, rxdctl);
3414
3415 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3416 ixgbe_configure_msix(adapter);
3417 else
3418 ixgbe_configure_msi_and_legacy(adapter);
3419
3420 /* enable the optics */
3421 if (hw->phy.multispeed_fiber)
3422 hw->mac.ops.enable_tx_laser(hw);
3423
3424 clear_bit(__IXGBE_DOWN, &adapter->state);
3425 ixgbe_napi_enable_all(adapter);
3426
3427 /* clear any pending interrupts, may auto mask */
3428 IXGBE_READ_REG(hw, IXGBE_EICR);
3429
3430 ixgbe_irq_enable(adapter);
3431
3432 /*
3433 * If this adapter has a fan, check to see if we had a failure
3434 * before we enabled the interrupt.
3435 */
3436 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3437 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3438 if (esdp & IXGBE_ESDP_SDP1)
3439 DPRINTK(DRV, CRIT,
3440 "Fan has stopped, replace the adapter\n");
3441 }
3442
3443 /*
3444 * For hot-pluggable SFP+ devices, a new SFP+ module may have
3445 * arrived before interrupts were enabled but after probe. Such
3446 * devices wouldn't have their type identified yet. We need to
3447 * kick off the SFP+ module setup first, then try to bring up link.
3448 * If we're not hot-pluggable SFP+, we just need to configure link
3449 * and bring it up.
3450 */
3451 if (hw->phy.type == ixgbe_phy_unknown) {
3452 err = hw->phy.ops.identify(hw);
3453 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3454 /*
3455 * Take the device down and schedule the sfp tasklet
3456 * which will unregister_netdev and log it.
3457 */
3458 ixgbe_down(adapter);
3459 schedule_work(&adapter->sfp_config_module_task);
3460 return err;
3461 }
3462 }
3463
3464 if (ixgbe_is_sfp(hw)) {
3465 ixgbe_sfp_link_config(adapter);
3466 } else {
3467 err = ixgbe_non_sfp_link_config(hw);
3468 if (err)
3469 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
3470 }
3471
3472 for (i = 0; i < adapter->num_tx_queues; i++)
3473 set_bit(__IXGBE_FDIR_INIT_DONE,
3474 &(adapter->tx_ring[i]->reinit_state));
3475
3476 /* enable transmits */
3477 netif_tx_start_all_queues(netdev);
3478
3479 /* bring the link up in the watchdog, this could race with our first
3480 * link up interrupt but shouldn't be a problem */
3481 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3482 adapter->link_check_timeout = jiffies;
3483 mod_timer(&adapter->watchdog_timer, jiffies);
3484
3485 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3486 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3487 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3488 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3489
3490 return 0;
3491 }
3492
3493 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3494 {
3495 WARN_ON(in_interrupt());
3496 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3497 msleep(1);
3498 ixgbe_down(adapter);
3499 /*
3500 * If SR-IOV enabled then wait a bit before bringing the adapter
3501 * back up to give the VFs time to respond to the reset. The
3502 * two second wait is based upon the watchdog timer cycle in
3503 * the VF driver.
3504 */
3505 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3506 msleep(2000);
3507 ixgbe_up(adapter);
3508 clear_bit(__IXGBE_RESETTING, &adapter->state);
3509 }
3510
3511 int ixgbe_up(struct ixgbe_adapter *adapter)
3512 {
3513 /* hardware has been reset, we need to reload some things */
3514 ixgbe_configure(adapter);
3515
3516 return ixgbe_up_complete(adapter);
3517 }
3518
3519 void ixgbe_reset(struct ixgbe_adapter *adapter)
3520 {
3521 struct ixgbe_hw *hw = &adapter->hw;
3522 int err;
3523
3524 err = hw->mac.ops.init_hw(hw);
3525 switch (err) {
3526 case 0:
3527 case IXGBE_ERR_SFP_NOT_PRESENT:
3528 break;
3529 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3530 dev_err(&adapter->pdev->dev, "master disable timed out\n");
3531 break;
3532 case IXGBE_ERR_EEPROM_VERSION:
3533 /* We are running on a pre-production device, log a warning */
3534 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
3535 "adapter/LOM. Please be aware there may be issues "
3536 "associated with your hardware. If you are "
3537 "experiencing problems please contact your Intel or "
3538 "hardware representative who provided you with this "
3539 "hardware.\n");
3540 break;
3541 default:
3542 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
3543 }
3544
3545 /* reprogram the RAR[0] in case user changed it. */
3546 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3547 IXGBE_RAH_AV);
3548 }
3549
3550 /**
3551 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3552 * @adapter: board private structure
3553 * @rx_ring: ring to free buffers from
3554 **/
3555 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
3556 struct ixgbe_ring *rx_ring)
3557 {
3558 struct pci_dev *pdev = adapter->pdev;
3559 unsigned long size;
3560 unsigned int i;
3561
3562 /* Free all the Rx ring sk_buffs */
3563
3564 for (i = 0; i < rx_ring->count; i++) {
3565 struct ixgbe_rx_buffer *rx_buffer_info;
3566
3567 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3568 if (rx_buffer_info->dma) {
3569 dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
3570 rx_ring->rx_buf_len,
3571 DMA_FROM_DEVICE);
3572 rx_buffer_info->dma = 0;
3573 }
3574 if (rx_buffer_info->skb) {
3575 struct sk_buff *skb = rx_buffer_info->skb;
3576 rx_buffer_info->skb = NULL;
3577 do {
3578 struct sk_buff *this = skb;
3579 if (IXGBE_RSC_CB(this)->delay_unmap) {
3580 dma_unmap_single(&pdev->dev,
3581 IXGBE_RSC_CB(this)->dma,
3582 rx_ring->rx_buf_len,
3583 DMA_FROM_DEVICE);
3584 IXGBE_RSC_CB(this)->dma = 0;
3585 IXGBE_RSC_CB(skb)->delay_unmap = false;
3586 }
3587 skb = skb->prev;
3588 dev_kfree_skb(this);
3589 } while (skb);
3590 }
3591 if (!rx_buffer_info->page)
3592 continue;
3593 if (rx_buffer_info->page_dma) {
3594 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
3595 PAGE_SIZE / 2, DMA_FROM_DEVICE);
3596 rx_buffer_info->page_dma = 0;
3597 }
3598 put_page(rx_buffer_info->page);
3599 rx_buffer_info->page = NULL;
3600 rx_buffer_info->page_offset = 0;
3601 }
3602
3603 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3604 memset(rx_ring->rx_buffer_info, 0, size);
3605
3606 /* Zero out the descriptor ring */
3607 memset(rx_ring->desc, 0, rx_ring->size);
3608
3609 rx_ring->next_to_clean = 0;
3610 rx_ring->next_to_use = 0;
3611
3612 if (rx_ring->head)
3613 writel(0, adapter->hw.hw_addr + rx_ring->head);
3614 if (rx_ring->tail)
3615 writel(0, adapter->hw.hw_addr + rx_ring->tail);
3616 }
3617
3618 /**
3619 * ixgbe_clean_tx_ring - Free Tx Buffers
3620 * @adapter: board private structure
3621 * @tx_ring: ring to be cleaned
3622 **/
3623 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
3624 struct ixgbe_ring *tx_ring)
3625 {
3626 struct ixgbe_tx_buffer *tx_buffer_info;
3627 unsigned long size;
3628 unsigned int i;
3629
3630 /* Free all the Tx ring sk_buffs */
3631
3632 for (i = 0; i < tx_ring->count; i++) {
3633 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3634 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3635 }
3636
3637 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3638 memset(tx_ring->tx_buffer_info, 0, size);
3639
3640 /* Zero out the descriptor ring */
3641 memset(tx_ring->desc, 0, tx_ring->size);
3642
3643 tx_ring->next_to_use = 0;
3644 tx_ring->next_to_clean = 0;
3645
3646 if (tx_ring->head)
3647 writel(0, adapter->hw.hw_addr + tx_ring->head);
3648 if (tx_ring->tail)
3649 writel(0, adapter->hw.hw_addr + tx_ring->tail);
3650 }
3651
3652 /**
3653 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3654 * @adapter: board private structure
3655 **/
3656 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3657 {
3658 int i;
3659
3660 for (i = 0; i < adapter->num_rx_queues; i++)
3661 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
3662 }
3663
3664 /**
3665 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3666 * @adapter: board private structure
3667 **/
3668 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3669 {
3670 int i;
3671
3672 for (i = 0; i < adapter->num_tx_queues; i++)
3673 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
3674 }
3675
3676 void ixgbe_down(struct ixgbe_adapter *adapter)
3677 {
3678 struct net_device *netdev = adapter->netdev;
3679 struct ixgbe_hw *hw = &adapter->hw;
3680 u32 rxctrl;
3681 u32 txdctl;
3682 int i, j;
3683
3684 /* signal that we are down to the interrupt handler */
3685 set_bit(__IXGBE_DOWN, &adapter->state);
3686
3687 /* power down the optics */
3688 if (hw->phy.multispeed_fiber)
3689 hw->mac.ops.disable_tx_laser(hw);
3690
3691 /* disable receive for all VFs and wait one second */
3692 if (adapter->num_vfs) {
3693 /* ping all the active vfs to let them know we are going down */
3694 ixgbe_ping_all_vfs(adapter);
3695
3696 /* Disable all VFTE/VFRE TX/RX */
3697 ixgbe_disable_tx_rx(adapter);
3698
3699 /* Mark all the VFs as inactive */
3700 for (i = 0 ; i < adapter->num_vfs; i++)
3701 adapter->vfinfo[i].clear_to_send = 0;
3702 }
3703
3704 /* disable receives */
3705 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3706 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3707
3708 IXGBE_WRITE_FLUSH(hw);
3709 msleep(10);
3710
3711 netif_tx_stop_all_queues(netdev);
3712
3713 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3714 del_timer_sync(&adapter->sfp_timer);
3715 del_timer_sync(&adapter->watchdog_timer);
3716 cancel_work_sync(&adapter->watchdog_task);
3717
3718 netif_carrier_off(netdev);
3719 netif_tx_disable(netdev);
3720
3721 ixgbe_irq_disable(adapter);
3722
3723 ixgbe_napi_disable_all(adapter);
3724
3725 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3726 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3727 cancel_work_sync(&adapter->fdir_reinit_task);
3728
3729 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3730 cancel_work_sync(&adapter->check_overtemp_task);
3731
3732 /* disable transmits in the hardware now that interrupts are off */
3733 for (i = 0; i < adapter->num_tx_queues; i++) {
3734 j = adapter->tx_ring[i]->reg_idx;
3735 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3736 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3737 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3738 }
3739 /* Disable the Tx DMA engine on 82599 */
3740 if (hw->mac.type == ixgbe_mac_82599EB)
3741 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3742 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3743 ~IXGBE_DMATXCTL_TE));
3744
3745 /* clear n-tuple filters that are cached */
3746 ethtool_ntuple_flush(netdev);
3747
3748 if (!pci_channel_offline(adapter->pdev))
3749 ixgbe_reset(adapter);
3750 ixgbe_clean_all_tx_rings(adapter);
3751 ixgbe_clean_all_rx_rings(adapter);
3752
3753 #ifdef CONFIG_IXGBE_DCA
3754 /* since we reset the hardware DCA settings were cleared */
3755 ixgbe_setup_dca(adapter);
3756 #endif
3757 }
3758
3759 /**
3760 * ixgbe_poll - NAPI Rx polling callback
3761 * @napi: structure for representing this polling device
3762 * @budget: how many packets driver is allowed to clean
3763 *
3764 * This function is used for legacy and MSI, NAPI mode
3765 **/
3766 static int ixgbe_poll(struct napi_struct *napi, int budget)
3767 {
3768 struct ixgbe_q_vector *q_vector =
3769 container_of(napi, struct ixgbe_q_vector, napi);
3770 struct ixgbe_adapter *adapter = q_vector->adapter;
3771 int tx_clean_complete, work_done = 0;
3772
3773 #ifdef CONFIG_IXGBE_DCA
3774 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3775 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3776 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
3777 }
3778 #endif
3779
3780 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3781 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
3782
3783 if (!tx_clean_complete)
3784 work_done = budget;
3785
3786 /* If budget not fully consumed, exit the polling mode */
3787 if (work_done < budget) {
3788 napi_complete(napi);
3789 if (adapter->rx_itr_setting & 1)
3790 ixgbe_set_itr(adapter);
3791 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3792 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3793 }
3794 return work_done;
3795 }
3796
3797 /**
3798 * ixgbe_tx_timeout - Respond to a Tx Hang
3799 * @netdev: network interface device structure
3800 **/
3801 static void ixgbe_tx_timeout(struct net_device *netdev)
3802 {
3803 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3804
3805 /* Do the reset outside of interrupt context */
3806 schedule_work(&adapter->reset_task);
3807 }
3808
3809 static void ixgbe_reset_task(struct work_struct *work)
3810 {
3811 struct ixgbe_adapter *adapter;
3812 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3813
3814 /* If we're already down or resetting, just bail */
3815 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3816 test_bit(__IXGBE_RESETTING, &adapter->state))
3817 return;
3818
3819 adapter->tx_timeout_count++;
3820
3821 ixgbe_dump(adapter);
3822 netdev_err(adapter->netdev, "Reset adapter\n");
3823 ixgbe_reinit_locked(adapter);
3824 }
3825
3826 #ifdef CONFIG_IXGBE_DCB
3827 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3828 {
3829 bool ret = false;
3830 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3831
3832 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3833 return ret;
3834
3835 f->mask = 0x7 << 3;
3836 adapter->num_rx_queues = f->indices;
3837 adapter->num_tx_queues = f->indices;
3838 ret = true;
3839
3840 return ret;
3841 }
3842 #endif
3843
3844 /**
3845 * ixgbe_set_rss_queues: Allocate queues for RSS
3846 * @adapter: board private structure to initialize
3847 *
3848 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3849 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3850 *
3851 **/
3852 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3853 {
3854 bool ret = false;
3855 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3856
3857 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3858 f->mask = 0xF;
3859 adapter->num_rx_queues = f->indices;
3860 adapter->num_tx_queues = f->indices;
3861 ret = true;
3862 } else {
3863 ret = false;
3864 }
3865
3866 return ret;
3867 }
3868
3869 /**
3870 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3871 * @adapter: board private structure to initialize
3872 *
3873 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3874 * to the original CPU that initiated the Tx session. This runs in addition
3875 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3876 * Rx load across CPUs using RSS.
3877 *
3878 **/
3879 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3880 {
3881 bool ret = false;
3882 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3883
3884 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3885 f_fdir->mask = 0;
3886
3887 /* Flow Director must have RSS enabled */
3888 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3889 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3890 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3891 adapter->num_tx_queues = f_fdir->indices;
3892 adapter->num_rx_queues = f_fdir->indices;
3893 ret = true;
3894 } else {
3895 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3896 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3897 }
3898 return ret;
3899 }
3900
3901 #ifdef IXGBE_FCOE
3902 /**
3903 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3904 * @adapter: board private structure to initialize
3905 *
3906 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3907 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3908 * rx queues out of the max number of rx queues, instead, it is used as the
3909 * index of the first rx queue used by FCoE.
3910 *
3911 **/
3912 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3913 {
3914 bool ret = false;
3915 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3916
3917 f->indices = min((int)num_online_cpus(), f->indices);
3918 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3919 adapter->num_rx_queues = 1;
3920 adapter->num_tx_queues = 1;
3921 #ifdef CONFIG_IXGBE_DCB
3922 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3923 DPRINTK(PROBE, INFO, "FCoE enabled with DCB\n");
3924 ixgbe_set_dcb_queues(adapter);
3925 }
3926 #endif
3927 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3928 DPRINTK(PROBE, INFO, "FCoE enabled with RSS\n");
3929 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3930 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3931 ixgbe_set_fdir_queues(adapter);
3932 else
3933 ixgbe_set_rss_queues(adapter);
3934 }
3935 /* adding FCoE rx rings to the end */
3936 f->mask = adapter->num_rx_queues;
3937 adapter->num_rx_queues += f->indices;
3938 adapter->num_tx_queues += f->indices;
3939
3940 ret = true;
3941 }
3942
3943 return ret;
3944 }
3945
3946 #endif /* IXGBE_FCOE */
3947 /**
3948 * ixgbe_set_sriov_queues: Allocate queues for IOV use
3949 * @adapter: board private structure to initialize
3950 *
3951 * IOV doesn't actually use anything, so just NAK the
3952 * request for now and let the other queue routines
3953 * figure out what to do.
3954 */
3955 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
3956 {
3957 return false;
3958 }
3959
3960 /*
3961 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3962 * @adapter: board private structure to initialize
3963 *
3964 * This is the top level queue allocation routine. The order here is very
3965 * important, starting with the "most" number of features turned on at once,
3966 * and ending with the smallest set of features. This way large combinations
3967 * can be allocated if they're turned on, and smaller combinations are the
3968 * fallthrough conditions.
3969 *
3970 **/
3971 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3972 {
3973 /* Start with base case */
3974 adapter->num_rx_queues = 1;
3975 adapter->num_tx_queues = 1;
3976 adapter->num_rx_pools = adapter->num_rx_queues;
3977 adapter->num_rx_queues_per_pool = 1;
3978
3979 if (ixgbe_set_sriov_queues(adapter))
3980 return;
3981
3982 #ifdef IXGBE_FCOE
3983 if (ixgbe_set_fcoe_queues(adapter))
3984 goto done;
3985
3986 #endif /* IXGBE_FCOE */
3987 #ifdef CONFIG_IXGBE_DCB
3988 if (ixgbe_set_dcb_queues(adapter))
3989 goto done;
3990
3991 #endif
3992 if (ixgbe_set_fdir_queues(adapter))
3993 goto done;
3994
3995 if (ixgbe_set_rss_queues(adapter))
3996 goto done;
3997
3998 /* fallback to base case */
3999 adapter->num_rx_queues = 1;
4000 adapter->num_tx_queues = 1;
4001
4002 done:
4003 /* Notify the stack of the (possibly) reduced Tx Queue count. */
4004 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
4005 }
4006
4007 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4008 int vectors)
4009 {
4010 int err, vector_threshold;
4011
4012 /* We'll want at least 3 (vector_threshold):
4013 * 1) TxQ[0] Cleanup
4014 * 2) RxQ[0] Cleanup
4015 * 3) Other (Link Status Change, etc.)
4016 * 4) TCP Timer (optional)
4017 */
4018 vector_threshold = MIN_MSIX_COUNT;
4019
4020 /* The more we get, the more we will assign to Tx/Rx Cleanup
4021 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4022 * Right now, we simply care about how many we'll get; we'll
4023 * set them up later while requesting irq's.
4024 */
4025 while (vectors >= vector_threshold) {
4026 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4027 vectors);
4028 if (!err) /* Success in acquiring all requested vectors. */
4029 break;
4030 else if (err < 0)
4031 vectors = 0; /* Nasty failure, quit now */
4032 else /* err == number of vectors we should try again with */
4033 vectors = err;
4034 }
4035
4036 if (vectors < vector_threshold) {
4037 /* Can't allocate enough MSI-X interrupts? Oh well.
4038 * This just means we'll go with either a single MSI
4039 * vector or fall back to legacy interrupts.
4040 */
4041 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
4042 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4043 kfree(adapter->msix_entries);
4044 adapter->msix_entries = NULL;
4045 } else {
4046 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4047 /*
4048 * Adjust for only the vectors we'll use, which is minimum
4049 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4050 * vectors we were allocated.
4051 */
4052 adapter->num_msix_vectors = min(vectors,
4053 adapter->max_msix_q_vectors + NON_Q_VECTORS);
4054 }
4055 }
4056
4057 /**
4058 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4059 * @adapter: board private structure to initialize
4060 *
4061 * Cache the descriptor ring offsets for RSS to the assigned rings.
4062 *
4063 **/
4064 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4065 {
4066 int i;
4067 bool ret = false;
4068
4069 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4070 for (i = 0; i < adapter->num_rx_queues; i++)
4071 adapter->rx_ring[i]->reg_idx = i;
4072 for (i = 0; i < adapter->num_tx_queues; i++)
4073 adapter->tx_ring[i]->reg_idx = i;
4074 ret = true;
4075 } else {
4076 ret = false;
4077 }
4078
4079 return ret;
4080 }
4081
4082 #ifdef CONFIG_IXGBE_DCB
4083 /**
4084 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4085 * @adapter: board private structure to initialize
4086 *
4087 * Cache the descriptor ring offsets for DCB to the assigned rings.
4088 *
4089 **/
4090 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4091 {
4092 int i;
4093 bool ret = false;
4094 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4095
4096 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4097 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
4098 /* the number of queues is assumed to be symmetric */
4099 for (i = 0; i < dcb_i; i++) {
4100 adapter->rx_ring[i]->reg_idx = i << 3;
4101 adapter->tx_ring[i]->reg_idx = i << 2;
4102 }
4103 ret = true;
4104 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
4105 if (dcb_i == 8) {
4106 /*
4107 * Tx TC0 starts at: descriptor queue 0
4108 * Tx TC1 starts at: descriptor queue 32
4109 * Tx TC2 starts at: descriptor queue 64
4110 * Tx TC3 starts at: descriptor queue 80
4111 * Tx TC4 starts at: descriptor queue 96
4112 * Tx TC5 starts at: descriptor queue 104
4113 * Tx TC6 starts at: descriptor queue 112
4114 * Tx TC7 starts at: descriptor queue 120
4115 *
4116 * Rx TC0-TC7 are offset by 16 queues each
4117 */
4118 for (i = 0; i < 3; i++) {
4119 adapter->tx_ring[i]->reg_idx = i << 5;
4120 adapter->rx_ring[i]->reg_idx = i << 4;
4121 }
4122 for ( ; i < 5; i++) {
4123 adapter->tx_ring[i]->reg_idx =
4124 ((i + 2) << 4);
4125 adapter->rx_ring[i]->reg_idx = i << 4;
4126 }
4127 for ( ; i < dcb_i; i++) {
4128 adapter->tx_ring[i]->reg_idx =
4129 ((i + 8) << 3);
4130 adapter->rx_ring[i]->reg_idx = i << 4;
4131 }
4132
4133 ret = true;
4134 } else if (dcb_i == 4) {
4135 /*
4136 * Tx TC0 starts at: descriptor queue 0
4137 * Tx TC1 starts at: descriptor queue 64
4138 * Tx TC2 starts at: descriptor queue 96
4139 * Tx TC3 starts at: descriptor queue 112
4140 *
4141 * Rx TC0-TC3 are offset by 32 queues each
4142 */
4143 adapter->tx_ring[0]->reg_idx = 0;
4144 adapter->tx_ring[1]->reg_idx = 64;
4145 adapter->tx_ring[2]->reg_idx = 96;
4146 adapter->tx_ring[3]->reg_idx = 112;
4147 for (i = 0 ; i < dcb_i; i++)
4148 adapter->rx_ring[i]->reg_idx = i << 5;
4149
4150 ret = true;
4151 } else {
4152 ret = false;
4153 }
4154 } else {
4155 ret = false;
4156 }
4157 } else {
4158 ret = false;
4159 }
4160
4161 return ret;
4162 }
4163 #endif
4164
4165 /**
4166 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4167 * @adapter: board private structure to initialize
4168 *
4169 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4170 *
4171 **/
4172 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4173 {
4174 int i;
4175 bool ret = false;
4176
4177 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4178 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4179 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4180 for (i = 0; i < adapter->num_rx_queues; i++)
4181 adapter->rx_ring[i]->reg_idx = i;
4182 for (i = 0; i < adapter->num_tx_queues; i++)
4183 adapter->tx_ring[i]->reg_idx = i;
4184 ret = true;
4185 }
4186
4187 return ret;
4188 }
4189
4190 #ifdef IXGBE_FCOE
4191 /**
4192 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4193 * @adapter: board private structure to initialize
4194 *
4195 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4196 *
4197 */
4198 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4199 {
4200 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
4201 bool ret = false;
4202 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4203
4204 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4205 #ifdef CONFIG_IXGBE_DCB
4206 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4207 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4208
4209 ixgbe_cache_ring_dcb(adapter);
4210 /* find out queues in TC for FCoE */
4211 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4212 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4213 /*
4214 * In 82599, the number of Tx queues for each traffic
4215 * class for both 8-TC and 4-TC modes are:
4216 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4217 * 8 TCs: 32 32 16 16 8 8 8 8
4218 * 4 TCs: 64 64 32 32
4219 * We have max 8 queues for FCoE, where 8 the is
4220 * FCoE redirection table size. If TC for FCoE is
4221 * less than or equal to TC3, we have enough queues
4222 * to add max of 8 queues for FCoE, so we start FCoE
4223 * tx descriptor from the next one, i.e., reg_idx + 1.
4224 * If TC for FCoE is above TC3, implying 8 TC mode,
4225 * and we need 8 for FCoE, we have to take all queues
4226 * in that traffic class for FCoE.
4227 */
4228 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4229 fcoe_tx_i--;
4230 }
4231 #endif /* CONFIG_IXGBE_DCB */
4232 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4233 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4234 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4235 ixgbe_cache_ring_fdir(adapter);
4236 else
4237 ixgbe_cache_ring_rss(adapter);
4238
4239 fcoe_rx_i = f->mask;
4240 fcoe_tx_i = f->mask;
4241 }
4242 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4243 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4244 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4245 }
4246 ret = true;
4247 }
4248 return ret;
4249 }
4250
4251 #endif /* IXGBE_FCOE */
4252 /**
4253 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4254 * @adapter: board private structure to initialize
4255 *
4256 * SR-IOV doesn't use any descriptor rings but changes the default if
4257 * no other mapping is used.
4258 *
4259 */
4260 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4261 {
4262 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4263 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4264 if (adapter->num_vfs)
4265 return true;
4266 else
4267 return false;
4268 }
4269
4270 /**
4271 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4272 * @adapter: board private structure to initialize
4273 *
4274 * Once we know the feature-set enabled for the device, we'll cache
4275 * the register offset the descriptor ring is assigned to.
4276 *
4277 * Note, the order the various feature calls is important. It must start with
4278 * the "most" features enabled at the same time, then trickle down to the
4279 * least amount of features turned on at once.
4280 **/
4281 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4282 {
4283 /* start with default case */
4284 adapter->rx_ring[0]->reg_idx = 0;
4285 adapter->tx_ring[0]->reg_idx = 0;
4286
4287 if (ixgbe_cache_ring_sriov(adapter))
4288 return;
4289
4290 #ifdef IXGBE_FCOE
4291 if (ixgbe_cache_ring_fcoe(adapter))
4292 return;
4293
4294 #endif /* IXGBE_FCOE */
4295 #ifdef CONFIG_IXGBE_DCB
4296 if (ixgbe_cache_ring_dcb(adapter))
4297 return;
4298
4299 #endif
4300 if (ixgbe_cache_ring_fdir(adapter))
4301 return;
4302
4303 if (ixgbe_cache_ring_rss(adapter))
4304 return;
4305 }
4306
4307 /**
4308 * ixgbe_alloc_queues - Allocate memory for all rings
4309 * @adapter: board private structure to initialize
4310 *
4311 * We allocate one ring per queue at run-time since we don't know the
4312 * number of queues at compile-time. The polling_netdev array is
4313 * intended for Multiqueue, but should work fine with a single queue.
4314 **/
4315 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4316 {
4317 int i;
4318 int orig_node = adapter->node;
4319
4320 for (i = 0; i < adapter->num_tx_queues; i++) {
4321 struct ixgbe_ring *ring = adapter->tx_ring[i];
4322 if (orig_node == -1) {
4323 int cur_node = next_online_node(adapter->node);
4324 if (cur_node == MAX_NUMNODES)
4325 cur_node = first_online_node;
4326 adapter->node = cur_node;
4327 }
4328 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4329 adapter->node);
4330 if (!ring)
4331 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4332 if (!ring)
4333 goto err_tx_ring_allocation;
4334 ring->count = adapter->tx_ring_count;
4335 ring->queue_index = i;
4336 ring->numa_node = adapter->node;
4337
4338 adapter->tx_ring[i] = ring;
4339 }
4340
4341 /* Restore the adapter's original node */
4342 adapter->node = orig_node;
4343
4344 for (i = 0; i < adapter->num_rx_queues; i++) {
4345 struct ixgbe_ring *ring = adapter->rx_ring[i];
4346 if (orig_node == -1) {
4347 int cur_node = next_online_node(adapter->node);
4348 if (cur_node == MAX_NUMNODES)
4349 cur_node = first_online_node;
4350 adapter->node = cur_node;
4351 }
4352 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4353 adapter->node);
4354 if (!ring)
4355 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4356 if (!ring)
4357 goto err_rx_ring_allocation;
4358 ring->count = adapter->rx_ring_count;
4359 ring->queue_index = i;
4360 ring->numa_node = adapter->node;
4361
4362 adapter->rx_ring[i] = ring;
4363 }
4364
4365 /* Restore the adapter's original node */
4366 adapter->node = orig_node;
4367
4368 ixgbe_cache_ring_register(adapter);
4369
4370 return 0;
4371
4372 err_rx_ring_allocation:
4373 for (i = 0; i < adapter->num_tx_queues; i++)
4374 kfree(adapter->tx_ring[i]);
4375 err_tx_ring_allocation:
4376 return -ENOMEM;
4377 }
4378
4379 /**
4380 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4381 * @adapter: board private structure to initialize
4382 *
4383 * Attempt to configure the interrupts using the best available
4384 * capabilities of the hardware and the kernel.
4385 **/
4386 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4387 {
4388 struct ixgbe_hw *hw = &adapter->hw;
4389 int err = 0;
4390 int vector, v_budget;
4391
4392 /*
4393 * It's easy to be greedy for MSI-X vectors, but it really
4394 * doesn't do us much good if we have a lot more vectors
4395 * than CPU's. So let's be conservative and only ask for
4396 * (roughly) the same number of vectors as there are CPU's.
4397 */
4398 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4399 (int)num_online_cpus()) + NON_Q_VECTORS;
4400
4401 /*
4402 * At the same time, hardware can only support a maximum of
4403 * hw.mac->max_msix_vectors vectors. With features
4404 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4405 * descriptor queues supported by our device. Thus, we cap it off in
4406 * those rare cases where the cpu count also exceeds our vector limit.
4407 */
4408 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4409
4410 /* A failure in MSI-X entry allocation isn't fatal, but it does
4411 * mean we disable MSI-X capabilities of the adapter. */
4412 adapter->msix_entries = kcalloc(v_budget,
4413 sizeof(struct msix_entry), GFP_KERNEL);
4414 if (adapter->msix_entries) {
4415 for (vector = 0; vector < v_budget; vector++)
4416 adapter->msix_entries[vector].entry = vector;
4417
4418 ixgbe_acquire_msix_vectors(adapter, v_budget);
4419
4420 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4421 goto out;
4422 }
4423
4424 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4425 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4426 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4427 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4428 adapter->atr_sample_rate = 0;
4429 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4430 ixgbe_disable_sriov(adapter);
4431
4432 ixgbe_set_num_queues(adapter);
4433
4434 err = pci_enable_msi(adapter->pdev);
4435 if (!err) {
4436 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4437 } else {
4438 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
4439 "falling back to legacy. Error: %d\n", err);
4440 /* reset err */
4441 err = 0;
4442 }
4443
4444 out:
4445 return err;
4446 }
4447
4448 /**
4449 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4450 * @adapter: board private structure to initialize
4451 *
4452 * We allocate one q_vector per queue interrupt. If allocation fails we
4453 * return -ENOMEM.
4454 **/
4455 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4456 {
4457 int q_idx, num_q_vectors;
4458 struct ixgbe_q_vector *q_vector;
4459 int napi_vectors;
4460 int (*poll)(struct napi_struct *, int);
4461
4462 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4463 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4464 napi_vectors = adapter->num_rx_queues;
4465 poll = &ixgbe_clean_rxtx_many;
4466 } else {
4467 num_q_vectors = 1;
4468 napi_vectors = 1;
4469 poll = &ixgbe_poll;
4470 }
4471
4472 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4473 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4474 GFP_KERNEL, adapter->node);
4475 if (!q_vector)
4476 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4477 GFP_KERNEL);
4478 if (!q_vector)
4479 goto err_out;
4480 q_vector->adapter = adapter;
4481 if (q_vector->txr_count && !q_vector->rxr_count)
4482 q_vector->eitr = adapter->tx_eitr_param;
4483 else
4484 q_vector->eitr = adapter->rx_eitr_param;
4485 q_vector->v_idx = q_idx;
4486 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4487 adapter->q_vector[q_idx] = q_vector;
4488 }
4489
4490 return 0;
4491
4492 err_out:
4493 while (q_idx) {
4494 q_idx--;
4495 q_vector = adapter->q_vector[q_idx];
4496 netif_napi_del(&q_vector->napi);
4497 kfree(q_vector);
4498 adapter->q_vector[q_idx] = NULL;
4499 }
4500 return -ENOMEM;
4501 }
4502
4503 /**
4504 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4505 * @adapter: board private structure to initialize
4506 *
4507 * This function frees the memory allocated to the q_vectors. In addition if
4508 * NAPI is enabled it will delete any references to the NAPI struct prior
4509 * to freeing the q_vector.
4510 **/
4511 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4512 {
4513 int q_idx, num_q_vectors;
4514
4515 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4516 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4517 else
4518 num_q_vectors = 1;
4519
4520 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4521 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4522 adapter->q_vector[q_idx] = NULL;
4523 netif_napi_del(&q_vector->napi);
4524 kfree(q_vector);
4525 }
4526 }
4527
4528 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4529 {
4530 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4531 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4532 pci_disable_msix(adapter->pdev);
4533 kfree(adapter->msix_entries);
4534 adapter->msix_entries = NULL;
4535 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4536 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4537 pci_disable_msi(adapter->pdev);
4538 }
4539 }
4540
4541 /**
4542 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4543 * @adapter: board private structure to initialize
4544 *
4545 * We determine which interrupt scheme to use based on...
4546 * - Kernel support (MSI, MSI-X)
4547 * - which can be user-defined (via MODULE_PARAM)
4548 * - Hardware queue count (num_*_queues)
4549 * - defined by miscellaneous hardware support/features (RSS, etc.)
4550 **/
4551 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4552 {
4553 int err;
4554
4555 /* Number of supported queues */
4556 ixgbe_set_num_queues(adapter);
4557
4558 err = ixgbe_set_interrupt_capability(adapter);
4559 if (err) {
4560 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
4561 goto err_set_interrupt;
4562 }
4563
4564 err = ixgbe_alloc_q_vectors(adapter);
4565 if (err) {
4566 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
4567 "vectors\n");
4568 goto err_alloc_q_vectors;
4569 }
4570
4571 err = ixgbe_alloc_queues(adapter);
4572 if (err) {
4573 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
4574 goto err_alloc_queues;
4575 }
4576
4577 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
4578 "Tx Queue count = %u\n",
4579 (adapter->num_rx_queues > 1) ? "Enabled" :
4580 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
4581
4582 set_bit(__IXGBE_DOWN, &adapter->state);
4583
4584 return 0;
4585
4586 err_alloc_queues:
4587 ixgbe_free_q_vectors(adapter);
4588 err_alloc_q_vectors:
4589 ixgbe_reset_interrupt_capability(adapter);
4590 err_set_interrupt:
4591 return err;
4592 }
4593
4594 /**
4595 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4596 * @adapter: board private structure to clear interrupt scheme on
4597 *
4598 * We go through and clear interrupt specific resources and reset the structure
4599 * to pre-load conditions
4600 **/
4601 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4602 {
4603 int i;
4604
4605 for (i = 0; i < adapter->num_tx_queues; i++) {
4606 kfree(adapter->tx_ring[i]);
4607 adapter->tx_ring[i] = NULL;
4608 }
4609 for (i = 0; i < adapter->num_rx_queues; i++) {
4610 kfree(adapter->rx_ring[i]);
4611 adapter->rx_ring[i] = NULL;
4612 }
4613
4614 ixgbe_free_q_vectors(adapter);
4615 ixgbe_reset_interrupt_capability(adapter);
4616 }
4617
4618 /**
4619 * ixgbe_sfp_timer - worker thread to find a missing module
4620 * @data: pointer to our adapter struct
4621 **/
4622 static void ixgbe_sfp_timer(unsigned long data)
4623 {
4624 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4625
4626 /*
4627 * Do the sfp_timer outside of interrupt context due to the
4628 * delays that sfp+ detection requires
4629 */
4630 schedule_work(&adapter->sfp_task);
4631 }
4632
4633 /**
4634 * ixgbe_sfp_task - worker thread to find a missing module
4635 * @work: pointer to work_struct containing our data
4636 **/
4637 static void ixgbe_sfp_task(struct work_struct *work)
4638 {
4639 struct ixgbe_adapter *adapter = container_of(work,
4640 struct ixgbe_adapter,
4641 sfp_task);
4642 struct ixgbe_hw *hw = &adapter->hw;
4643
4644 if ((hw->phy.type == ixgbe_phy_nl) &&
4645 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4646 s32 ret = hw->phy.ops.identify_sfp(hw);
4647 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4648 goto reschedule;
4649 ret = hw->phy.ops.reset(hw);
4650 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4651 dev_err(&adapter->pdev->dev, "failed to initialize "
4652 "because an unsupported SFP+ module type "
4653 "was detected.\n"
4654 "Reload the driver after installing a "
4655 "supported module.\n");
4656 unregister_netdev(adapter->netdev);
4657 } else {
4658 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
4659 hw->phy.sfp_type);
4660 }
4661 /* don't need this routine any more */
4662 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4663 }
4664 return;
4665 reschedule:
4666 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4667 mod_timer(&adapter->sfp_timer,
4668 round_jiffies(jiffies + (2 * HZ)));
4669 }
4670
4671 /**
4672 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4673 * @adapter: board private structure to initialize
4674 *
4675 * ixgbe_sw_init initializes the Adapter private data structure.
4676 * Fields are initialized based on PCI device information and
4677 * OS network device settings (MTU size).
4678 **/
4679 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4680 {
4681 struct ixgbe_hw *hw = &adapter->hw;
4682 struct pci_dev *pdev = adapter->pdev;
4683 struct net_device *dev = adapter->netdev;
4684 unsigned int rss;
4685 #ifdef CONFIG_IXGBE_DCB
4686 int j;
4687 struct tc_configuration *tc;
4688 #endif
4689
4690 /* PCI config space info */
4691
4692 hw->vendor_id = pdev->vendor;
4693 hw->device_id = pdev->device;
4694 hw->revision_id = pdev->revision;
4695 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4696 hw->subsystem_device_id = pdev->subsystem_device;
4697
4698 /* Set capability flags */
4699 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4700 adapter->ring_feature[RING_F_RSS].indices = rss;
4701 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4702 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4703 if (hw->mac.type == ixgbe_mac_82598EB) {
4704 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4705 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4706 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4707 } else if (hw->mac.type == ixgbe_mac_82599EB) {
4708 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4709 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4710 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4711 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4712 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4713 if (dev->features & NETIF_F_NTUPLE) {
4714 /* Flow Director perfect filter enabled */
4715 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4716 adapter->atr_sample_rate = 0;
4717 spin_lock_init(&adapter->fdir_perfect_lock);
4718 } else {
4719 /* Flow Director hash filters enabled */
4720 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4721 adapter->atr_sample_rate = 20;
4722 }
4723 adapter->ring_feature[RING_F_FDIR].indices =
4724 IXGBE_MAX_FDIR_INDICES;
4725 adapter->fdir_pballoc = 0;
4726 #ifdef IXGBE_FCOE
4727 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4728 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4729 adapter->ring_feature[RING_F_FCOE].indices = 0;
4730 #ifdef CONFIG_IXGBE_DCB
4731 /* Default traffic class to use for FCoE */
4732 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4733 #endif
4734 #endif /* IXGBE_FCOE */
4735 }
4736
4737 #ifdef CONFIG_IXGBE_DCB
4738 /* Configure DCB traffic classes */
4739 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4740 tc = &adapter->dcb_cfg.tc_config[j];
4741 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4742 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4743 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4744 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4745 tc->dcb_pfc = pfc_disabled;
4746 }
4747 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4748 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4749 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4750 adapter->dcb_cfg.pfc_mode_enable = false;
4751 adapter->dcb_cfg.round_robin_enable = false;
4752 adapter->dcb_set_bitmap = 0x00;
4753 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4754 adapter->ring_feature[RING_F_DCB].indices);
4755
4756 #endif
4757
4758 /* default flow control settings */
4759 hw->fc.requested_mode = ixgbe_fc_full;
4760 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4761 #ifdef CONFIG_DCB
4762 adapter->last_lfc_mode = hw->fc.current_mode;
4763 #endif
4764 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4765 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4766 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4767 hw->fc.send_xon = true;
4768 hw->fc.disable_fc_autoneg = false;
4769
4770 /* enable itr by default in dynamic mode */
4771 adapter->rx_itr_setting = 1;
4772 adapter->rx_eitr_param = 20000;
4773 adapter->tx_itr_setting = 1;
4774 adapter->tx_eitr_param = 10000;
4775
4776 /* set defaults for eitr in MegaBytes */
4777 adapter->eitr_low = 10;
4778 adapter->eitr_high = 20;
4779
4780 /* set default ring sizes */
4781 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4782 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4783
4784 /* initialize eeprom parameters */
4785 if (ixgbe_init_eeprom_params_generic(hw)) {
4786 dev_err(&pdev->dev, "EEPROM initialization failed\n");
4787 return -EIO;
4788 }
4789
4790 /* enable rx csum by default */
4791 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4792
4793 /* get assigned NUMA node */
4794 adapter->node = dev_to_node(&pdev->dev);
4795
4796 set_bit(__IXGBE_DOWN, &adapter->state);
4797
4798 return 0;
4799 }
4800
4801 /**
4802 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4803 * @adapter: board private structure
4804 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4805 *
4806 * Return 0 on success, negative on failure
4807 **/
4808 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
4809 struct ixgbe_ring *tx_ring)
4810 {
4811 struct pci_dev *pdev = adapter->pdev;
4812 int size;
4813
4814 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4815 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
4816 if (!tx_ring->tx_buffer_info)
4817 tx_ring->tx_buffer_info = vmalloc(size);
4818 if (!tx_ring->tx_buffer_info)
4819 goto err;
4820 memset(tx_ring->tx_buffer_info, 0, size);
4821
4822 /* round up to nearest 4K */
4823 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4824 tx_ring->size = ALIGN(tx_ring->size, 4096);
4825
4826 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
4827 &tx_ring->dma, GFP_KERNEL);
4828 if (!tx_ring->desc)
4829 goto err;
4830
4831 tx_ring->next_to_use = 0;
4832 tx_ring->next_to_clean = 0;
4833 tx_ring->work_limit = tx_ring->count;
4834 return 0;
4835
4836 err:
4837 vfree(tx_ring->tx_buffer_info);
4838 tx_ring->tx_buffer_info = NULL;
4839 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
4840 "descriptor ring\n");
4841 return -ENOMEM;
4842 }
4843
4844 /**
4845 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4846 * @adapter: board private structure
4847 *
4848 * If this function returns with an error, then it's possible one or
4849 * more of the rings is populated (while the rest are not). It is the
4850 * callers duty to clean those orphaned rings.
4851 *
4852 * Return 0 on success, negative on failure
4853 **/
4854 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4855 {
4856 int i, err = 0;
4857
4858 for (i = 0; i < adapter->num_tx_queues; i++) {
4859 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
4860 if (!err)
4861 continue;
4862 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4863 break;
4864 }
4865
4866 return err;
4867 }
4868
4869 /**
4870 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4871 * @adapter: board private structure
4872 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4873 *
4874 * Returns 0 on success, negative on failure
4875 **/
4876 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4877 struct ixgbe_ring *rx_ring)
4878 {
4879 struct pci_dev *pdev = adapter->pdev;
4880 int size;
4881
4882 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4883 rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
4884 if (!rx_ring->rx_buffer_info)
4885 rx_ring->rx_buffer_info = vmalloc(size);
4886 if (!rx_ring->rx_buffer_info) {
4887 DPRINTK(PROBE, ERR,
4888 "vmalloc allocation failed for the rx desc ring\n");
4889 goto alloc_failed;
4890 }
4891 memset(rx_ring->rx_buffer_info, 0, size);
4892
4893 /* Round up to nearest 4K */
4894 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4895 rx_ring->size = ALIGN(rx_ring->size, 4096);
4896
4897 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
4898 &rx_ring->dma, GFP_KERNEL);
4899
4900 if (!rx_ring->desc) {
4901 DPRINTK(PROBE, ERR,
4902 "Memory allocation failed for the rx desc ring\n");
4903 vfree(rx_ring->rx_buffer_info);
4904 goto alloc_failed;
4905 }
4906
4907 rx_ring->next_to_clean = 0;
4908 rx_ring->next_to_use = 0;
4909
4910 return 0;
4911
4912 alloc_failed:
4913 return -ENOMEM;
4914 }
4915
4916 /**
4917 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4918 * @adapter: board private structure
4919 *
4920 * If this function returns with an error, then it's possible one or
4921 * more of the rings is populated (while the rest are not). It is the
4922 * callers duty to clean those orphaned rings.
4923 *
4924 * Return 0 on success, negative on failure
4925 **/
4926
4927 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4928 {
4929 int i, err = 0;
4930
4931 for (i = 0; i < adapter->num_rx_queues; i++) {
4932 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
4933 if (!err)
4934 continue;
4935 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4936 break;
4937 }
4938
4939 return err;
4940 }
4941
4942 /**
4943 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4944 * @adapter: board private structure
4945 * @tx_ring: Tx descriptor ring for a specific queue
4946 *
4947 * Free all transmit software resources
4948 **/
4949 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4950 struct ixgbe_ring *tx_ring)
4951 {
4952 struct pci_dev *pdev = adapter->pdev;
4953
4954 ixgbe_clean_tx_ring(adapter, tx_ring);
4955
4956 vfree(tx_ring->tx_buffer_info);
4957 tx_ring->tx_buffer_info = NULL;
4958
4959 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
4960 tx_ring->dma);
4961
4962 tx_ring->desc = NULL;
4963 }
4964
4965 /**
4966 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4967 * @adapter: board private structure
4968 *
4969 * Free all transmit software resources
4970 **/
4971 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4972 {
4973 int i;
4974
4975 for (i = 0; i < adapter->num_tx_queues; i++)
4976 if (adapter->tx_ring[i]->desc)
4977 ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
4978 }
4979
4980 /**
4981 * ixgbe_free_rx_resources - Free Rx Resources
4982 * @adapter: board private structure
4983 * @rx_ring: ring to clean the resources from
4984 *
4985 * Free all receive software resources
4986 **/
4987 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4988 struct ixgbe_ring *rx_ring)
4989 {
4990 struct pci_dev *pdev = adapter->pdev;
4991
4992 ixgbe_clean_rx_ring(adapter, rx_ring);
4993
4994 vfree(rx_ring->rx_buffer_info);
4995 rx_ring->rx_buffer_info = NULL;
4996
4997 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
4998 rx_ring->dma);
4999
5000 rx_ring->desc = NULL;
5001 }
5002
5003 /**
5004 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5005 * @adapter: board private structure
5006 *
5007 * Free all receive software resources
5008 **/
5009 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5010 {
5011 int i;
5012
5013 for (i = 0; i < adapter->num_rx_queues; i++)
5014 if (adapter->rx_ring[i]->desc)
5015 ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
5016 }
5017
5018 /**
5019 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5020 * @netdev: network interface device structure
5021 * @new_mtu: new value for maximum frame size
5022 *
5023 * Returns 0 on success, negative on failure
5024 **/
5025 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5026 {
5027 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5028 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5029
5030 /* MTU < 68 is an error and causes problems on some kernels */
5031 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5032 return -EINVAL;
5033
5034 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
5035 netdev->mtu, new_mtu);
5036 /* must set new MTU before calling down or up */
5037 netdev->mtu = new_mtu;
5038
5039 if (netif_running(netdev))
5040 ixgbe_reinit_locked(adapter);
5041
5042 return 0;
5043 }
5044
5045 /**
5046 * ixgbe_open - Called when a network interface is made active
5047 * @netdev: network interface device structure
5048 *
5049 * Returns 0 on success, negative value on failure
5050 *
5051 * The open entry point is called when a network interface is made
5052 * active by the system (IFF_UP). At this point all resources needed
5053 * for transmit and receive operations are allocated, the interrupt
5054 * handler is registered with the OS, the watchdog timer is started,
5055 * and the stack is notified that the interface is ready.
5056 **/
5057 static int ixgbe_open(struct net_device *netdev)
5058 {
5059 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5060 int err;
5061
5062 /* disallow open during test */
5063 if (test_bit(__IXGBE_TESTING, &adapter->state))
5064 return -EBUSY;
5065
5066 netif_carrier_off(netdev);
5067
5068 /* allocate transmit descriptors */
5069 err = ixgbe_setup_all_tx_resources(adapter);
5070 if (err)
5071 goto err_setup_tx;
5072
5073 /* allocate receive descriptors */
5074 err = ixgbe_setup_all_rx_resources(adapter);
5075 if (err)
5076 goto err_setup_rx;
5077
5078 ixgbe_configure(adapter);
5079
5080 err = ixgbe_request_irq(adapter);
5081 if (err)
5082 goto err_req_irq;
5083
5084 err = ixgbe_up_complete(adapter);
5085 if (err)
5086 goto err_up;
5087
5088 netif_tx_start_all_queues(netdev);
5089
5090 return 0;
5091
5092 err_up:
5093 ixgbe_release_hw_control(adapter);
5094 ixgbe_free_irq(adapter);
5095 err_req_irq:
5096 err_setup_rx:
5097 ixgbe_free_all_rx_resources(adapter);
5098 err_setup_tx:
5099 ixgbe_free_all_tx_resources(adapter);
5100 ixgbe_reset(adapter);
5101
5102 return err;
5103 }
5104
5105 /**
5106 * ixgbe_close - Disables a network interface
5107 * @netdev: network interface device structure
5108 *
5109 * Returns 0, this is not allowed to fail
5110 *
5111 * The close entry point is called when an interface is de-activated
5112 * by the OS. The hardware is still under the drivers control, but
5113 * needs to be disabled. A global MAC reset is issued to stop the
5114 * hardware, and all transmit and receive resources are freed.
5115 **/
5116 static int ixgbe_close(struct net_device *netdev)
5117 {
5118 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5119
5120 ixgbe_down(adapter);
5121 ixgbe_free_irq(adapter);
5122
5123 ixgbe_free_all_tx_resources(adapter);
5124 ixgbe_free_all_rx_resources(adapter);
5125
5126 ixgbe_release_hw_control(adapter);
5127
5128 return 0;
5129 }
5130
5131 #ifdef CONFIG_PM
5132 static int ixgbe_resume(struct pci_dev *pdev)
5133 {
5134 struct net_device *netdev = pci_get_drvdata(pdev);
5135 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5136 u32 err;
5137
5138 pci_set_power_state(pdev, PCI_D0);
5139 pci_restore_state(pdev);
5140 /*
5141 * pci_restore_state clears dev->state_saved so call
5142 * pci_save_state to restore it.
5143 */
5144 pci_save_state(pdev);
5145
5146 err = pci_enable_device_mem(pdev);
5147 if (err) {
5148 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
5149 "suspend\n");
5150 return err;
5151 }
5152 pci_set_master(pdev);
5153
5154 pci_wake_from_d3(pdev, false);
5155
5156 err = ixgbe_init_interrupt_scheme(adapter);
5157 if (err) {
5158 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
5159 "device\n");
5160 return err;
5161 }
5162
5163 ixgbe_reset(adapter);
5164
5165 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5166
5167 if (netif_running(netdev)) {
5168 err = ixgbe_open(adapter->netdev);
5169 if (err)
5170 return err;
5171 }
5172
5173 netif_device_attach(netdev);
5174
5175 return 0;
5176 }
5177 #endif /* CONFIG_PM */
5178
5179 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5180 {
5181 struct net_device *netdev = pci_get_drvdata(pdev);
5182 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5183 struct ixgbe_hw *hw = &adapter->hw;
5184 u32 ctrl, fctrl;
5185 u32 wufc = adapter->wol;
5186 #ifdef CONFIG_PM
5187 int retval = 0;
5188 #endif
5189
5190 netif_device_detach(netdev);
5191
5192 if (netif_running(netdev)) {
5193 ixgbe_down(adapter);
5194 ixgbe_free_irq(adapter);
5195 ixgbe_free_all_tx_resources(adapter);
5196 ixgbe_free_all_rx_resources(adapter);
5197 }
5198 ixgbe_clear_interrupt_scheme(adapter);
5199
5200 #ifdef CONFIG_PM
5201 retval = pci_save_state(pdev);
5202 if (retval)
5203 return retval;
5204
5205 #endif
5206 if (wufc) {
5207 ixgbe_set_rx_mode(netdev);
5208
5209 /* turn on all-multi mode if wake on multicast is enabled */
5210 if (wufc & IXGBE_WUFC_MC) {
5211 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5212 fctrl |= IXGBE_FCTRL_MPE;
5213 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5214 }
5215
5216 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5217 ctrl |= IXGBE_CTRL_GIO_DIS;
5218 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5219
5220 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5221 } else {
5222 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5223 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5224 }
5225
5226 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5227 pci_wake_from_d3(pdev, true);
5228 else
5229 pci_wake_from_d3(pdev, false);
5230
5231 *enable_wake = !!wufc;
5232
5233 ixgbe_release_hw_control(adapter);
5234
5235 pci_disable_device(pdev);
5236
5237 return 0;
5238 }
5239
5240 #ifdef CONFIG_PM
5241 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5242 {
5243 int retval;
5244 bool wake;
5245
5246 retval = __ixgbe_shutdown(pdev, &wake);
5247 if (retval)
5248 return retval;
5249
5250 if (wake) {
5251 pci_prepare_to_sleep(pdev);
5252 } else {
5253 pci_wake_from_d3(pdev, false);
5254 pci_set_power_state(pdev, PCI_D3hot);
5255 }
5256
5257 return 0;
5258 }
5259 #endif /* CONFIG_PM */
5260
5261 static void ixgbe_shutdown(struct pci_dev *pdev)
5262 {
5263 bool wake;
5264
5265 __ixgbe_shutdown(pdev, &wake);
5266
5267 if (system_state == SYSTEM_POWER_OFF) {
5268 pci_wake_from_d3(pdev, wake);
5269 pci_set_power_state(pdev, PCI_D3hot);
5270 }
5271 }
5272
5273 /**
5274 * ixgbe_update_stats - Update the board statistics counters.
5275 * @adapter: board private structure
5276 **/
5277 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5278 {
5279 struct net_device *netdev = adapter->netdev;
5280 struct ixgbe_hw *hw = &adapter->hw;
5281 u64 total_mpc = 0;
5282 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5283 u64 non_eop_descs = 0, restart_queue = 0;
5284
5285 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5286 test_bit(__IXGBE_RESETTING, &adapter->state))
5287 return;
5288
5289 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5290 u64 rsc_count = 0;
5291 u64 rsc_flush = 0;
5292 for (i = 0; i < 16; i++)
5293 adapter->hw_rx_no_dma_resources +=
5294 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5295 for (i = 0; i < adapter->num_rx_queues; i++) {
5296 rsc_count += adapter->rx_ring[i]->rsc_count;
5297 rsc_flush += adapter->rx_ring[i]->rsc_flush;
5298 }
5299 adapter->rsc_total_count = rsc_count;
5300 adapter->rsc_total_flush = rsc_flush;
5301 }
5302
5303 /* gather some stats to the adapter struct that are per queue */
5304 for (i = 0; i < adapter->num_tx_queues; i++)
5305 restart_queue += adapter->tx_ring[i]->restart_queue;
5306 adapter->restart_queue = restart_queue;
5307
5308 for (i = 0; i < adapter->num_rx_queues; i++)
5309 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
5310 adapter->non_eop_descs = non_eop_descs;
5311
5312 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5313 for (i = 0; i < 8; i++) {
5314 /* for packet buffers not used, the register should read 0 */
5315 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5316 missed_rx += mpc;
5317 adapter->stats.mpc[i] += mpc;
5318 total_mpc += adapter->stats.mpc[i];
5319 if (hw->mac.type == ixgbe_mac_82598EB)
5320 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5321 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5322 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5323 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5324 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5325 if (hw->mac.type == ixgbe_mac_82599EB) {
5326 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5327 IXGBE_PXONRXCNT(i));
5328 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5329 IXGBE_PXOFFRXCNT(i));
5330 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5331 } else {
5332 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5333 IXGBE_PXONRXC(i));
5334 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5335 IXGBE_PXOFFRXC(i));
5336 }
5337 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
5338 IXGBE_PXONTXC(i));
5339 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
5340 IXGBE_PXOFFTXC(i));
5341 }
5342 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5343 /* work around hardware counting issue */
5344 adapter->stats.gprc -= missed_rx;
5345
5346 /* 82598 hardware only has a 32 bit counter in the high register */
5347 if (hw->mac.type == ixgbe_mac_82599EB) {
5348 u64 tmp;
5349 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5350 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
5351 adapter->stats.gorc += (tmp << 32);
5352 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5353 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
5354 adapter->stats.gotc += (tmp << 32);
5355 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5356 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5357 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5358 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5359 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5360 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5361 #ifdef IXGBE_FCOE
5362 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5363 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5364 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5365 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5366 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5367 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5368 #endif /* IXGBE_FCOE */
5369 } else {
5370 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5371 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5372 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5373 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5374 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5375 }
5376 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5377 adapter->stats.bprc += bprc;
5378 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5379 if (hw->mac.type == ixgbe_mac_82598EB)
5380 adapter->stats.mprc -= bprc;
5381 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5382 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5383 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5384 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5385 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5386 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5387 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5388 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5389 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5390 adapter->stats.lxontxc += lxon;
5391 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5392 adapter->stats.lxofftxc += lxoff;
5393 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5394 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5395 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5396 /*
5397 * 82598 errata - tx of flow control packets is included in tx counters
5398 */
5399 xon_off_tot = lxon + lxoff;
5400 adapter->stats.gptc -= xon_off_tot;
5401 adapter->stats.mptc -= xon_off_tot;
5402 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5403 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5404 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5405 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5406 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5407 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5408 adapter->stats.ptc64 -= xon_off_tot;
5409 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5410 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5411 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5412 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5413 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5414 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5415
5416 /* Fill out the OS statistics structure */
5417 netdev->stats.multicast = adapter->stats.mprc;
5418
5419 /* Rx Errors */
5420 netdev->stats.rx_errors = adapter->stats.crcerrs +
5421 adapter->stats.rlec;
5422 netdev->stats.rx_dropped = 0;
5423 netdev->stats.rx_length_errors = adapter->stats.rlec;
5424 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5425 netdev->stats.rx_missed_errors = total_mpc;
5426 }
5427
5428 /**
5429 * ixgbe_watchdog - Timer Call-back
5430 * @data: pointer to adapter cast into an unsigned long
5431 **/
5432 static void ixgbe_watchdog(unsigned long data)
5433 {
5434 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5435 struct ixgbe_hw *hw = &adapter->hw;
5436 u64 eics = 0;
5437 int i;
5438
5439 /*
5440 * Do the watchdog outside of interrupt context due to the lovely
5441 * delays that some of the newer hardware requires
5442 */
5443
5444 if (test_bit(__IXGBE_DOWN, &adapter->state))
5445 goto watchdog_short_circuit;
5446
5447 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5448 /*
5449 * for legacy and MSI interrupts don't set any bits
5450 * that are enabled for EIAM, because this operation
5451 * would set *both* EIMS and EICS for any bit in EIAM
5452 */
5453 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5454 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5455 goto watchdog_reschedule;
5456 }
5457
5458 /* get one bit for every active tx/rx interrupt vector */
5459 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5460 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5461 if (qv->rxr_count || qv->txr_count)
5462 eics |= ((u64)1 << i);
5463 }
5464
5465 /* Cause software interrupt to ensure rx rings are cleaned */
5466 ixgbe_irq_rearm_queues(adapter, eics);
5467
5468 watchdog_reschedule:
5469 /* Reset the timer */
5470 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5471
5472 watchdog_short_circuit:
5473 schedule_work(&adapter->watchdog_task);
5474 }
5475
5476 /**
5477 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5478 * @work: pointer to work_struct containing our data
5479 **/
5480 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5481 {
5482 struct ixgbe_adapter *adapter = container_of(work,
5483 struct ixgbe_adapter,
5484 multispeed_fiber_task);
5485 struct ixgbe_hw *hw = &adapter->hw;
5486 u32 autoneg;
5487 bool negotiation;
5488
5489 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5490 autoneg = hw->phy.autoneg_advertised;
5491 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5492 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5493 hw->mac.autotry_restart = false;
5494 if (hw->mac.ops.setup_link)
5495 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5496 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5497 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5498 }
5499
5500 /**
5501 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5502 * @work: pointer to work_struct containing our data
5503 **/
5504 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5505 {
5506 struct ixgbe_adapter *adapter = container_of(work,
5507 struct ixgbe_adapter,
5508 sfp_config_module_task);
5509 struct ixgbe_hw *hw = &adapter->hw;
5510 u32 err;
5511
5512 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5513
5514 /* Time for electrical oscillations to settle down */
5515 msleep(100);
5516 err = hw->phy.ops.identify_sfp(hw);
5517
5518 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5519 dev_err(&adapter->pdev->dev, "failed to initialize because "
5520 "an unsupported SFP+ module type was detected.\n"
5521 "Reload the driver after installing a supported "
5522 "module.\n");
5523 unregister_netdev(adapter->netdev);
5524 return;
5525 }
5526 hw->mac.ops.setup_sfp(hw);
5527
5528 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5529 /* This will also work for DA Twinax connections */
5530 schedule_work(&adapter->multispeed_fiber_task);
5531 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5532 }
5533
5534 /**
5535 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5536 * @work: pointer to work_struct containing our data
5537 **/
5538 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5539 {
5540 struct ixgbe_adapter *adapter = container_of(work,
5541 struct ixgbe_adapter,
5542 fdir_reinit_task);
5543 struct ixgbe_hw *hw = &adapter->hw;
5544 int i;
5545
5546 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5547 for (i = 0; i < adapter->num_tx_queues; i++)
5548 set_bit(__IXGBE_FDIR_INIT_DONE,
5549 &(adapter->tx_ring[i]->reinit_state));
5550 } else {
5551 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
5552 "ignored adding FDIR ATR filters\n");
5553 }
5554 /* Done FDIR Re-initialization, enable transmits */
5555 netif_tx_start_all_queues(adapter->netdev);
5556 }
5557
5558 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5559
5560 /**
5561 * ixgbe_watchdog_task - worker thread to bring link up
5562 * @work: pointer to work_struct containing our data
5563 **/
5564 static void ixgbe_watchdog_task(struct work_struct *work)
5565 {
5566 struct ixgbe_adapter *adapter = container_of(work,
5567 struct ixgbe_adapter,
5568 watchdog_task);
5569 struct net_device *netdev = adapter->netdev;
5570 struct ixgbe_hw *hw = &adapter->hw;
5571 u32 link_speed;
5572 bool link_up;
5573 int i;
5574 struct ixgbe_ring *tx_ring;
5575 int some_tx_pending = 0;
5576
5577 mutex_lock(&ixgbe_watchdog_lock);
5578
5579 link_up = adapter->link_up;
5580 link_speed = adapter->link_speed;
5581
5582 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5583 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5584 if (link_up) {
5585 #ifdef CONFIG_DCB
5586 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5587 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5588 hw->mac.ops.fc_enable(hw, i);
5589 } else {
5590 hw->mac.ops.fc_enable(hw, 0);
5591 }
5592 #else
5593 hw->mac.ops.fc_enable(hw, 0);
5594 #endif
5595 }
5596
5597 if (link_up ||
5598 time_after(jiffies, (adapter->link_check_timeout +
5599 IXGBE_TRY_LINK_TIMEOUT))) {
5600 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5601 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5602 }
5603 adapter->link_up = link_up;
5604 adapter->link_speed = link_speed;
5605 }
5606
5607 if (link_up) {
5608 if (!netif_carrier_ok(netdev)) {
5609 bool flow_rx, flow_tx;
5610
5611 if (hw->mac.type == ixgbe_mac_82599EB) {
5612 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5613 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5614 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5615 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5616 } else {
5617 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5618 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5619 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5620 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5621 }
5622
5623 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
5624 "Flow Control: %s\n",
5625 netdev->name,
5626 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5627 "10 Gbps" :
5628 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5629 "1 Gbps" : "unknown speed")),
5630 ((flow_rx && flow_tx) ? "RX/TX" :
5631 (flow_rx ? "RX" :
5632 (flow_tx ? "TX" : "None"))));
5633
5634 netif_carrier_on(netdev);
5635 } else {
5636 /* Force detection of hung controller */
5637 adapter->detect_tx_hung = true;
5638 }
5639 } else {
5640 adapter->link_up = false;
5641 adapter->link_speed = 0;
5642 if (netif_carrier_ok(netdev)) {
5643 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
5644 netdev->name);
5645 netif_carrier_off(netdev);
5646 }
5647 }
5648
5649 if (!netif_carrier_ok(netdev)) {
5650 for (i = 0; i < adapter->num_tx_queues; i++) {
5651 tx_ring = adapter->tx_ring[i];
5652 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5653 some_tx_pending = 1;
5654 break;
5655 }
5656 }
5657
5658 if (some_tx_pending) {
5659 /* We've lost link, so the controller stops DMA,
5660 * but we've got queued Tx work that's never going
5661 * to get done, so reset controller to flush Tx.
5662 * (Do the reset outside of interrupt context).
5663 */
5664 schedule_work(&adapter->reset_task);
5665 }
5666 }
5667
5668 ixgbe_update_stats(adapter);
5669 mutex_unlock(&ixgbe_watchdog_lock);
5670 }
5671
5672 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5673 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5674 u32 tx_flags, u8 *hdr_len)
5675 {
5676 struct ixgbe_adv_tx_context_desc *context_desc;
5677 unsigned int i;
5678 int err;
5679 struct ixgbe_tx_buffer *tx_buffer_info;
5680 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5681 u32 mss_l4len_idx, l4len;
5682
5683 if (skb_is_gso(skb)) {
5684 if (skb_header_cloned(skb)) {
5685 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5686 if (err)
5687 return err;
5688 }
5689 l4len = tcp_hdrlen(skb);
5690 *hdr_len += l4len;
5691
5692 if (skb->protocol == htons(ETH_P_IP)) {
5693 struct iphdr *iph = ip_hdr(skb);
5694 iph->tot_len = 0;
5695 iph->check = 0;
5696 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5697 iph->daddr, 0,
5698 IPPROTO_TCP,
5699 0);
5700 } else if (skb_is_gso_v6(skb)) {
5701 ipv6_hdr(skb)->payload_len = 0;
5702 tcp_hdr(skb)->check =
5703 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5704 &ipv6_hdr(skb)->daddr,
5705 0, IPPROTO_TCP, 0);
5706 }
5707
5708 i = tx_ring->next_to_use;
5709
5710 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5711 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5712
5713 /* VLAN MACLEN IPLEN */
5714 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5715 vlan_macip_lens |=
5716 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5717 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5718 IXGBE_ADVTXD_MACLEN_SHIFT);
5719 *hdr_len += skb_network_offset(skb);
5720 vlan_macip_lens |=
5721 (skb_transport_header(skb) - skb_network_header(skb));
5722 *hdr_len +=
5723 (skb_transport_header(skb) - skb_network_header(skb));
5724 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5725 context_desc->seqnum_seed = 0;
5726
5727 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5728 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
5729 IXGBE_ADVTXD_DTYP_CTXT);
5730
5731 if (skb->protocol == htons(ETH_P_IP))
5732 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5733 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5734 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5735
5736 /* MSS L4LEN IDX */
5737 mss_l4len_idx =
5738 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5739 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
5740 /* use index 1 for TSO */
5741 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5742 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5743
5744 tx_buffer_info->time_stamp = jiffies;
5745 tx_buffer_info->next_to_watch = i;
5746
5747 i++;
5748 if (i == tx_ring->count)
5749 i = 0;
5750 tx_ring->next_to_use = i;
5751
5752 return true;
5753 }
5754 return false;
5755 }
5756
5757 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
5758 struct ixgbe_ring *tx_ring,
5759 struct sk_buff *skb, u32 tx_flags)
5760 {
5761 struct ixgbe_adv_tx_context_desc *context_desc;
5762 unsigned int i;
5763 struct ixgbe_tx_buffer *tx_buffer_info;
5764 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5765
5766 if (skb->ip_summed == CHECKSUM_PARTIAL ||
5767 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5768 i = tx_ring->next_to_use;
5769 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5770 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5771
5772 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5773 vlan_macip_lens |=
5774 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5775 vlan_macip_lens |= (skb_network_offset(skb) <<
5776 IXGBE_ADVTXD_MACLEN_SHIFT);
5777 if (skb->ip_summed == CHECKSUM_PARTIAL)
5778 vlan_macip_lens |= (skb_transport_header(skb) -
5779 skb_network_header(skb));
5780
5781 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5782 context_desc->seqnum_seed = 0;
5783
5784 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
5785 IXGBE_ADVTXD_DTYP_CTXT);
5786
5787 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5788 __be16 protocol;
5789
5790 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5791 const struct vlan_ethhdr *vhdr =
5792 (const struct vlan_ethhdr *)skb->data;
5793
5794 protocol = vhdr->h_vlan_encapsulated_proto;
5795 } else {
5796 protocol = skb->protocol;
5797 }
5798
5799 switch (protocol) {
5800 case cpu_to_be16(ETH_P_IP):
5801 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5802 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5803 type_tucmd_mlhl |=
5804 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5805 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5806 type_tucmd_mlhl |=
5807 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5808 break;
5809 case cpu_to_be16(ETH_P_IPV6):
5810 /* XXX what about other V6 headers?? */
5811 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5812 type_tucmd_mlhl |=
5813 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5814 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5815 type_tucmd_mlhl |=
5816 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5817 break;
5818 default:
5819 if (unlikely(net_ratelimit())) {
5820 DPRINTK(PROBE, WARNING,
5821 "partial checksum but proto=%x!\n",
5822 skb->protocol);
5823 }
5824 break;
5825 }
5826 }
5827
5828 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5829 /* use index zero for tx checksum offload */
5830 context_desc->mss_l4len_idx = 0;
5831
5832 tx_buffer_info->time_stamp = jiffies;
5833 tx_buffer_info->next_to_watch = i;
5834
5835 i++;
5836 if (i == tx_ring->count)
5837 i = 0;
5838 tx_ring->next_to_use = i;
5839
5840 return true;
5841 }
5842
5843 return false;
5844 }
5845
5846 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
5847 struct ixgbe_ring *tx_ring,
5848 struct sk_buff *skb, u32 tx_flags,
5849 unsigned int first)
5850 {
5851 struct pci_dev *pdev = adapter->pdev;
5852 struct ixgbe_tx_buffer *tx_buffer_info;
5853 unsigned int len;
5854 unsigned int total = skb->len;
5855 unsigned int offset = 0, size, count = 0, i;
5856 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5857 unsigned int f;
5858
5859 i = tx_ring->next_to_use;
5860
5861 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5862 /* excluding fcoe_crc_eof for FCoE */
5863 total -= sizeof(struct fcoe_crc_eof);
5864
5865 len = min(skb_headlen(skb), total);
5866 while (len) {
5867 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5868 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5869
5870 tx_buffer_info->length = size;
5871 tx_buffer_info->mapped_as_page = false;
5872 tx_buffer_info->dma = dma_map_single(&pdev->dev,
5873 skb->data + offset,
5874 size, DMA_TO_DEVICE);
5875 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
5876 goto dma_error;
5877 tx_buffer_info->time_stamp = jiffies;
5878 tx_buffer_info->next_to_watch = i;
5879
5880 len -= size;
5881 total -= size;
5882 offset += size;
5883 count++;
5884
5885 if (len) {
5886 i++;
5887 if (i == tx_ring->count)
5888 i = 0;
5889 }
5890 }
5891
5892 for (f = 0; f < nr_frags; f++) {
5893 struct skb_frag_struct *frag;
5894
5895 frag = &skb_shinfo(skb)->frags[f];
5896 len = min((unsigned int)frag->size, total);
5897 offset = frag->page_offset;
5898
5899 while (len) {
5900 i++;
5901 if (i == tx_ring->count)
5902 i = 0;
5903
5904 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5905 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5906
5907 tx_buffer_info->length = size;
5908 tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev,
5909 frag->page,
5910 offset, size,
5911 DMA_TO_DEVICE);
5912 tx_buffer_info->mapped_as_page = true;
5913 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
5914 goto dma_error;
5915 tx_buffer_info->time_stamp = jiffies;
5916 tx_buffer_info->next_to_watch = i;
5917
5918 len -= size;
5919 total -= size;
5920 offset += size;
5921 count++;
5922 }
5923 if (total == 0)
5924 break;
5925 }
5926
5927 tx_ring->tx_buffer_info[i].skb = skb;
5928 tx_ring->tx_buffer_info[first].next_to_watch = i;
5929
5930 return count;
5931
5932 dma_error:
5933 dev_err(&pdev->dev, "TX DMA map failed\n");
5934
5935 /* clear timestamp and dma mappings for failed tx_buffer_info map */
5936 tx_buffer_info->dma = 0;
5937 tx_buffer_info->time_stamp = 0;
5938 tx_buffer_info->next_to_watch = 0;
5939 if (count)
5940 count--;
5941
5942 /* clear timestamp and dma mappings for remaining portion of packet */
5943 while (count--) {
5944 if (i==0)
5945 i += tx_ring->count;
5946 i--;
5947 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5948 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
5949 }
5950
5951 return 0;
5952 }
5953
5954 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
5955 struct ixgbe_ring *tx_ring,
5956 int tx_flags, int count, u32 paylen, u8 hdr_len)
5957 {
5958 union ixgbe_adv_tx_desc *tx_desc = NULL;
5959 struct ixgbe_tx_buffer *tx_buffer_info;
5960 u32 olinfo_status = 0, cmd_type_len = 0;
5961 unsigned int i;
5962 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5963
5964 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5965
5966 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5967
5968 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5969 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5970
5971 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5972 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5973
5974 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5975 IXGBE_ADVTXD_POPTS_SHIFT;
5976
5977 /* use index 1 context for tso */
5978 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5979 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5980 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
5981 IXGBE_ADVTXD_POPTS_SHIFT;
5982
5983 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5984 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5985 IXGBE_ADVTXD_POPTS_SHIFT;
5986
5987 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5988 olinfo_status |= IXGBE_ADVTXD_CC;
5989 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5990 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5991 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5992 }
5993
5994 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5995
5996 i = tx_ring->next_to_use;
5997 while (count--) {
5998 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5999 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
6000 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6001 tx_desc->read.cmd_type_len =
6002 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6003 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6004 i++;
6005 if (i == tx_ring->count)
6006 i = 0;
6007 }
6008
6009 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6010
6011 /*
6012 * Force memory writes to complete before letting h/w
6013 * know there are new descriptors to fetch. (Only
6014 * applicable for weak-ordered memory model archs,
6015 * such as IA-64).
6016 */
6017 wmb();
6018
6019 tx_ring->next_to_use = i;
6020 writel(i, adapter->hw.hw_addr + tx_ring->tail);
6021 }
6022
6023 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6024 int queue, u32 tx_flags)
6025 {
6026 /* Right now, we support IPv4 only */
6027 struct ixgbe_atr_input atr_input;
6028 struct tcphdr *th;
6029 struct iphdr *iph = ip_hdr(skb);
6030 struct ethhdr *eth = (struct ethhdr *)skb->data;
6031 u16 vlan_id, src_port, dst_port, flex_bytes;
6032 u32 src_ipv4_addr, dst_ipv4_addr;
6033 u8 l4type = 0;
6034
6035 /* check if we're UDP or TCP */
6036 if (iph->protocol == IPPROTO_TCP) {
6037 th = tcp_hdr(skb);
6038 src_port = th->source;
6039 dst_port = th->dest;
6040 l4type |= IXGBE_ATR_L4TYPE_TCP;
6041 /* l4type IPv4 type is 0, no need to assign */
6042 } else {
6043 /* Unsupported L4 header, just bail here */
6044 return;
6045 }
6046
6047 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6048
6049 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6050 IXGBE_TX_FLAGS_VLAN_SHIFT;
6051 src_ipv4_addr = iph->saddr;
6052 dst_ipv4_addr = iph->daddr;
6053 flex_bytes = eth->h_proto;
6054
6055 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6056 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
6057 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
6058 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
6059 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
6060 /* src and dst are inverted, think how the receiver sees them */
6061 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
6062 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
6063
6064 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6065 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6066 }
6067
6068 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
6069 struct ixgbe_ring *tx_ring, int size)
6070 {
6071 netif_stop_subqueue(netdev, tx_ring->queue_index);
6072 /* Herbert's original patch had:
6073 * smp_mb__after_netif_stop_queue();
6074 * but since that doesn't exist yet, just open code it. */
6075 smp_mb();
6076
6077 /* We need to check again in a case another CPU has just
6078 * made room available. */
6079 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6080 return -EBUSY;
6081
6082 /* A reprieve! - use start_queue because it doesn't call schedule */
6083 netif_start_subqueue(netdev, tx_ring->queue_index);
6084 ++tx_ring->restart_queue;
6085 return 0;
6086 }
6087
6088 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
6089 struct ixgbe_ring *tx_ring, int size)
6090 {
6091 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6092 return 0;
6093 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
6094 }
6095
6096 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6097 {
6098 struct ixgbe_adapter *adapter = netdev_priv(dev);
6099 int txq = smp_processor_id();
6100
6101 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6102 while (unlikely(txq >= dev->real_num_tx_queues))
6103 txq -= dev->real_num_tx_queues;
6104 return txq;
6105 }
6106
6107 #ifdef IXGBE_FCOE
6108 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
6109 ((skb->protocol == htons(ETH_P_FCOE)) ||
6110 (skb->protocol == htons(ETH_P_FIP)))) {
6111 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6112 txq += adapter->ring_feature[RING_F_FCOE].mask;
6113 return txq;
6114 }
6115 #endif
6116 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6117 if (skb->priority == TC_PRIO_CONTROL)
6118 txq = adapter->ring_feature[RING_F_DCB].indices-1;
6119 else
6120 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6121 >> 13;
6122 return txq;
6123 }
6124
6125 return skb_tx_hash(dev, skb);
6126 }
6127
6128 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6129 struct net_device *netdev)
6130 {
6131 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6132 struct ixgbe_ring *tx_ring;
6133 struct netdev_queue *txq;
6134 unsigned int first;
6135 unsigned int tx_flags = 0;
6136 u8 hdr_len = 0;
6137 int tso;
6138 int count = 0;
6139 unsigned int f;
6140
6141 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
6142 tx_flags |= vlan_tx_tag_get(skb);
6143 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6144 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6145 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6146 }
6147 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6148 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6149 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6150 skb->priority != TC_PRIO_CONTROL) {
6151 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6152 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6153 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6154 }
6155
6156 tx_ring = adapter->tx_ring[skb->queue_mapping];
6157
6158 #ifdef IXGBE_FCOE
6159 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6160 #ifdef CONFIG_IXGBE_DCB
6161 /* for FCoE with DCB, we force the priority to what
6162 * was specified by the switch */
6163 if ((skb->protocol == htons(ETH_P_FCOE)) ||
6164 (skb->protocol == htons(ETH_P_FIP))) {
6165 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6166 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6167 tx_flags |= ((adapter->fcoe.up << 13)
6168 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6169 }
6170 #endif
6171 /* flag for FCoE offloads */
6172 if (skb->protocol == htons(ETH_P_FCOE))
6173 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6174 }
6175 #endif
6176
6177 /* four things can cause us to need a context descriptor */
6178 if (skb_is_gso(skb) ||
6179 (skb->ip_summed == CHECKSUM_PARTIAL) ||
6180 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6181 (tx_flags & IXGBE_TX_FLAGS_FCOE))
6182 count++;
6183
6184 count += TXD_USE_COUNT(skb_headlen(skb));
6185 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6186 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6187
6188 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
6189 adapter->tx_busy++;
6190 return NETDEV_TX_BUSY;
6191 }
6192
6193 first = tx_ring->next_to_use;
6194 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6195 #ifdef IXGBE_FCOE
6196 /* setup tx offload for FCoE */
6197 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6198 if (tso < 0) {
6199 dev_kfree_skb_any(skb);
6200 return NETDEV_TX_OK;
6201 }
6202 if (tso)
6203 tx_flags |= IXGBE_TX_FLAGS_FSO;
6204 #endif /* IXGBE_FCOE */
6205 } else {
6206 if (skb->protocol == htons(ETH_P_IP))
6207 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6208 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6209 if (tso < 0) {
6210 dev_kfree_skb_any(skb);
6211 return NETDEV_TX_OK;
6212 }
6213
6214 if (tso)
6215 tx_flags |= IXGBE_TX_FLAGS_TSO;
6216 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
6217 (skb->ip_summed == CHECKSUM_PARTIAL))
6218 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6219 }
6220
6221 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
6222 if (count) {
6223 /* add the ATR filter if ATR is on */
6224 if (tx_ring->atr_sample_rate) {
6225 ++tx_ring->atr_count;
6226 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6227 test_bit(__IXGBE_FDIR_INIT_DONE,
6228 &tx_ring->reinit_state)) {
6229 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6230 tx_flags);
6231 tx_ring->atr_count = 0;
6232 }
6233 }
6234 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6235 txq->tx_bytes += skb->len;
6236 txq->tx_packets++;
6237 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
6238 hdr_len);
6239 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
6240
6241 } else {
6242 dev_kfree_skb_any(skb);
6243 tx_ring->tx_buffer_info[first].time_stamp = 0;
6244 tx_ring->next_to_use = first;
6245 }
6246
6247 return NETDEV_TX_OK;
6248 }
6249
6250 /**
6251 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6252 * @netdev: network interface device structure
6253 * @p: pointer to an address structure
6254 *
6255 * Returns 0 on success, negative on failure
6256 **/
6257 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6258 {
6259 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6260 struct ixgbe_hw *hw = &adapter->hw;
6261 struct sockaddr *addr = p;
6262
6263 if (!is_valid_ether_addr(addr->sa_data))
6264 return -EADDRNOTAVAIL;
6265
6266 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6267 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6268
6269 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6270 IXGBE_RAH_AV);
6271
6272 return 0;
6273 }
6274
6275 static int
6276 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6277 {
6278 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6279 struct ixgbe_hw *hw = &adapter->hw;
6280 u16 value;
6281 int rc;
6282
6283 if (prtad != hw->phy.mdio.prtad)
6284 return -EINVAL;
6285 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6286 if (!rc)
6287 rc = value;
6288 return rc;
6289 }
6290
6291 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6292 u16 addr, u16 value)
6293 {
6294 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6295 struct ixgbe_hw *hw = &adapter->hw;
6296
6297 if (prtad != hw->phy.mdio.prtad)
6298 return -EINVAL;
6299 return hw->phy.ops.write_reg(hw, addr, devad, value);
6300 }
6301
6302 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6303 {
6304 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6305
6306 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6307 }
6308
6309 /**
6310 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6311 * netdev->dev_addrs
6312 * @netdev: network interface device structure
6313 *
6314 * Returns non-zero on failure
6315 **/
6316 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6317 {
6318 int err = 0;
6319 struct ixgbe_adapter *adapter = netdev_priv(dev);
6320 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6321
6322 if (is_valid_ether_addr(mac->san_addr)) {
6323 rtnl_lock();
6324 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6325 rtnl_unlock();
6326 }
6327 return err;
6328 }
6329
6330 /**
6331 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6332 * netdev->dev_addrs
6333 * @netdev: network interface device structure
6334 *
6335 * Returns non-zero on failure
6336 **/
6337 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6338 {
6339 int err = 0;
6340 struct ixgbe_adapter *adapter = netdev_priv(dev);
6341 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6342
6343 if (is_valid_ether_addr(mac->san_addr)) {
6344 rtnl_lock();
6345 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6346 rtnl_unlock();
6347 }
6348 return err;
6349 }
6350
6351 #ifdef CONFIG_NET_POLL_CONTROLLER
6352 /*
6353 * Polling 'interrupt' - used by things like netconsole to send skbs
6354 * without having to re-enable interrupts. It's not called while
6355 * the interrupt routine is executing.
6356 */
6357 static void ixgbe_netpoll(struct net_device *netdev)
6358 {
6359 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6360 int i;
6361
6362 /* if interface is down do nothing */
6363 if (test_bit(__IXGBE_DOWN, &adapter->state))
6364 return;
6365
6366 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6367 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6368 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6369 for (i = 0; i < num_q_vectors; i++) {
6370 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6371 ixgbe_msix_clean_many(0, q_vector);
6372 }
6373 } else {
6374 ixgbe_intr(adapter->pdev->irq, netdev);
6375 }
6376 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6377 }
6378 #endif
6379
6380 static const struct net_device_ops ixgbe_netdev_ops = {
6381 .ndo_open = ixgbe_open,
6382 .ndo_stop = ixgbe_close,
6383 .ndo_start_xmit = ixgbe_xmit_frame,
6384 .ndo_select_queue = ixgbe_select_queue,
6385 .ndo_set_rx_mode = ixgbe_set_rx_mode,
6386 .ndo_set_multicast_list = ixgbe_set_rx_mode,
6387 .ndo_validate_addr = eth_validate_addr,
6388 .ndo_set_mac_address = ixgbe_set_mac,
6389 .ndo_change_mtu = ixgbe_change_mtu,
6390 .ndo_tx_timeout = ixgbe_tx_timeout,
6391 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
6392 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6393 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6394 .ndo_do_ioctl = ixgbe_ioctl,
6395 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6396 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6397 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6398 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
6399 #ifdef CONFIG_NET_POLL_CONTROLLER
6400 .ndo_poll_controller = ixgbe_netpoll,
6401 #endif
6402 #ifdef IXGBE_FCOE
6403 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6404 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6405 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6406 .ndo_fcoe_disable = ixgbe_fcoe_disable,
6407 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6408 #endif /* IXGBE_FCOE */
6409 };
6410
6411 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6412 const struct ixgbe_info *ii)
6413 {
6414 #ifdef CONFIG_PCI_IOV
6415 struct ixgbe_hw *hw = &adapter->hw;
6416 int err;
6417
6418 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6419 return;
6420
6421 /* The 82599 supports up to 64 VFs per physical function
6422 * but this implementation limits allocation to 63 so that
6423 * basic networking resources are still available to the
6424 * physical function
6425 */
6426 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6427 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6428 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6429 if (err) {
6430 DPRINTK(PROBE, ERR,
6431 "Failed to enable PCI sriov: %d\n", err);
6432 goto err_novfs;
6433 }
6434 /* If call to enable VFs succeeded then allocate memory
6435 * for per VF control structures.
6436 */
6437 adapter->vfinfo =
6438 kcalloc(adapter->num_vfs,
6439 sizeof(struct vf_data_storage), GFP_KERNEL);
6440 if (adapter->vfinfo) {
6441 /* Now that we're sure SR-IOV is enabled
6442 * and memory allocated set up the mailbox parameters
6443 */
6444 ixgbe_init_mbx_params_pf(hw);
6445 memcpy(&hw->mbx.ops, ii->mbx_ops,
6446 sizeof(hw->mbx.ops));
6447
6448 /* Disable RSC when in SR-IOV mode */
6449 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6450 IXGBE_FLAG2_RSC_ENABLED);
6451 return;
6452 }
6453
6454 /* Oh oh */
6455 DPRINTK(PROBE, ERR,
6456 "Unable to allocate memory for VF "
6457 "Data Storage - SRIOV disabled\n");
6458 pci_disable_sriov(adapter->pdev);
6459
6460 err_novfs:
6461 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6462 adapter->num_vfs = 0;
6463 #endif /* CONFIG_PCI_IOV */
6464 }
6465
6466 /**
6467 * ixgbe_probe - Device Initialization Routine
6468 * @pdev: PCI device information struct
6469 * @ent: entry in ixgbe_pci_tbl
6470 *
6471 * Returns 0 on success, negative on failure
6472 *
6473 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6474 * The OS initialization, configuring of the adapter private structure,
6475 * and a hardware reset occur.
6476 **/
6477 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6478 const struct pci_device_id *ent)
6479 {
6480 struct net_device *netdev;
6481 struct ixgbe_adapter *adapter = NULL;
6482 struct ixgbe_hw *hw;
6483 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6484 static int cards_found;
6485 int i, err, pci_using_dac;
6486 unsigned int indices = num_possible_cpus();
6487 #ifdef IXGBE_FCOE
6488 u16 device_caps;
6489 #endif
6490 u32 part_num, eec;
6491
6492 err = pci_enable_device_mem(pdev);
6493 if (err)
6494 return err;
6495
6496 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6497 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6498 pci_using_dac = 1;
6499 } else {
6500 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6501 if (err) {
6502 err = dma_set_coherent_mask(&pdev->dev,
6503 DMA_BIT_MASK(32));
6504 if (err) {
6505 dev_err(&pdev->dev, "No usable DMA "
6506 "configuration, aborting\n");
6507 goto err_dma;
6508 }
6509 }
6510 pci_using_dac = 0;
6511 }
6512
6513 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6514 IORESOURCE_MEM), ixgbe_driver_name);
6515 if (err) {
6516 dev_err(&pdev->dev,
6517 "pci_request_selected_regions failed 0x%x\n", err);
6518 goto err_pci_reg;
6519 }
6520
6521 pci_enable_pcie_error_reporting(pdev);
6522
6523 pci_set_master(pdev);
6524 pci_save_state(pdev);
6525
6526 if (ii->mac == ixgbe_mac_82598EB)
6527 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6528 else
6529 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6530
6531 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6532 #ifdef IXGBE_FCOE
6533 indices += min_t(unsigned int, num_possible_cpus(),
6534 IXGBE_MAX_FCOE_INDICES);
6535 #endif
6536 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6537 if (!netdev) {
6538 err = -ENOMEM;
6539 goto err_alloc_etherdev;
6540 }
6541
6542 SET_NETDEV_DEV(netdev, &pdev->dev);
6543
6544 pci_set_drvdata(pdev, netdev);
6545 adapter = netdev_priv(netdev);
6546
6547 adapter->netdev = netdev;
6548 adapter->pdev = pdev;
6549 hw = &adapter->hw;
6550 hw->back = adapter;
6551 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6552
6553 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6554 pci_resource_len(pdev, 0));
6555 if (!hw->hw_addr) {
6556 err = -EIO;
6557 goto err_ioremap;
6558 }
6559
6560 for (i = 1; i <= 5; i++) {
6561 if (pci_resource_len(pdev, i) == 0)
6562 continue;
6563 }
6564
6565 netdev->netdev_ops = &ixgbe_netdev_ops;
6566 ixgbe_set_ethtool_ops(netdev);
6567 netdev->watchdog_timeo = 5 * HZ;
6568 strcpy(netdev->name, pci_name(pdev));
6569
6570 adapter->bd_number = cards_found;
6571
6572 /* Setup hw api */
6573 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6574 hw->mac.type = ii->mac;
6575
6576 /* EEPROM */
6577 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6578 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6579 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6580 if (!(eec & (1 << 8)))
6581 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6582
6583 /* PHY */
6584 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6585 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6586 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6587 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6588 hw->phy.mdio.mmds = 0;
6589 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6590 hw->phy.mdio.dev = netdev;
6591 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6592 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6593
6594 /* set up this timer and work struct before calling get_invariants
6595 * which might start the timer
6596 */
6597 init_timer(&adapter->sfp_timer);
6598 adapter->sfp_timer.function = &ixgbe_sfp_timer;
6599 adapter->sfp_timer.data = (unsigned long) adapter;
6600
6601 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
6602
6603 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6604 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6605
6606 /* a new SFP+ module arrival, called from GPI SDP2 context */
6607 INIT_WORK(&adapter->sfp_config_module_task,
6608 ixgbe_sfp_config_module_task);
6609
6610 ii->get_invariants(hw);
6611
6612 /* setup the private structure */
6613 err = ixgbe_sw_init(adapter);
6614 if (err)
6615 goto err_sw_init;
6616
6617 /* Make it possible the adapter to be woken up via WOL */
6618 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6619 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6620
6621 /*
6622 * If there is a fan on this device and it has failed log the
6623 * failure.
6624 */
6625 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6626 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6627 if (esdp & IXGBE_ESDP_SDP1)
6628 DPRINTK(PROBE, CRIT,
6629 "Fan has stopped, replace the adapter\n");
6630 }
6631
6632 /* reset_hw fills in the perm_addr as well */
6633 hw->phy.reset_if_overtemp = true;
6634 err = hw->mac.ops.reset_hw(hw);
6635 hw->phy.reset_if_overtemp = false;
6636 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6637 hw->mac.type == ixgbe_mac_82598EB) {
6638 /*
6639 * Start a kernel thread to watch for a module to arrive.
6640 * Only do this for 82598, since 82599 will generate
6641 * interrupts on module arrival.
6642 */
6643 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6644 mod_timer(&adapter->sfp_timer,
6645 round_jiffies(jiffies + (2 * HZ)));
6646 err = 0;
6647 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6648 dev_err(&adapter->pdev->dev, "failed to initialize because "
6649 "an unsupported SFP+ module type was detected.\n"
6650 "Reload the driver after installing a supported "
6651 "module.\n");
6652 goto err_sw_init;
6653 } else if (err) {
6654 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
6655 goto err_sw_init;
6656 }
6657
6658 ixgbe_probe_vf(adapter, ii);
6659
6660 netdev->features = NETIF_F_SG |
6661 NETIF_F_IP_CSUM |
6662 NETIF_F_HW_VLAN_TX |
6663 NETIF_F_HW_VLAN_RX |
6664 NETIF_F_HW_VLAN_FILTER;
6665
6666 netdev->features |= NETIF_F_IPV6_CSUM;
6667 netdev->features |= NETIF_F_TSO;
6668 netdev->features |= NETIF_F_TSO6;
6669 netdev->features |= NETIF_F_GRO;
6670
6671 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6672 netdev->features |= NETIF_F_SCTP_CSUM;
6673
6674 netdev->vlan_features |= NETIF_F_TSO;
6675 netdev->vlan_features |= NETIF_F_TSO6;
6676 netdev->vlan_features |= NETIF_F_IP_CSUM;
6677 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
6678 netdev->vlan_features |= NETIF_F_SG;
6679
6680 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6681 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6682 IXGBE_FLAG_DCB_ENABLED);
6683 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6684 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6685
6686 #ifdef CONFIG_IXGBE_DCB
6687 netdev->dcbnl_ops = &dcbnl_ops;
6688 #endif
6689
6690 #ifdef IXGBE_FCOE
6691 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6692 if (hw->mac.ops.get_device_caps) {
6693 hw->mac.ops.get_device_caps(hw, &device_caps);
6694 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6695 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6696 }
6697 }
6698 #endif /* IXGBE_FCOE */
6699 if (pci_using_dac)
6700 netdev->features |= NETIF_F_HIGHDMA;
6701
6702 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6703 netdev->features |= NETIF_F_LRO;
6704
6705 /* make sure the EEPROM is good */
6706 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
6707 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
6708 err = -EIO;
6709 goto err_eeprom;
6710 }
6711
6712 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6713 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6714
6715 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6716 dev_err(&pdev->dev, "invalid MAC address\n");
6717 err = -EIO;
6718 goto err_eeprom;
6719 }
6720
6721 /* power down the optics */
6722 if (hw->phy.multispeed_fiber)
6723 hw->mac.ops.disable_tx_laser(hw);
6724
6725 init_timer(&adapter->watchdog_timer);
6726 adapter->watchdog_timer.function = &ixgbe_watchdog;
6727 adapter->watchdog_timer.data = (unsigned long)adapter;
6728
6729 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
6730 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
6731
6732 err = ixgbe_init_interrupt_scheme(adapter);
6733 if (err)
6734 goto err_sw_init;
6735
6736 switch (pdev->device) {
6737 case IXGBE_DEV_ID_82599_KX4:
6738 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6739 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
6740 break;
6741 default:
6742 adapter->wol = 0;
6743 break;
6744 }
6745 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6746
6747 /* pick up the PCI bus settings for reporting later */
6748 hw->mac.ops.get_bus_info(hw);
6749
6750 /* print bus type/speed/width info */
6751 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
6752 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
6753 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
6754 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
6755 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
6756 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
6757 "Unknown"),
6758 netdev->dev_addr);
6759 ixgbe_read_pba_num_generic(hw, &part_num);
6760 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
6761 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
6762 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6763 (part_num >> 8), (part_num & 0xff));
6764 else
6765 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6766 hw->mac.type, hw->phy.type,
6767 (part_num >> 8), (part_num & 0xff));
6768
6769 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
6770 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
6771 "this card is not sufficient for optimal "
6772 "performance.\n");
6773 dev_warn(&pdev->dev, "For optimal performance a x8 "
6774 "PCI-Express slot is required.\n");
6775 }
6776
6777 /* save off EEPROM version number */
6778 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6779
6780 /* reset the hardware with the new settings */
6781 err = hw->mac.ops.start_hw(hw);
6782
6783 if (err == IXGBE_ERR_EEPROM_VERSION) {
6784 /* We are running on a pre-production device, log a warning */
6785 dev_warn(&pdev->dev, "This device is a pre-production "
6786 "adapter/LOM. Please be aware there may be issues "
6787 "associated with your hardware. If you are "
6788 "experiencing problems please contact your Intel or "
6789 "hardware representative who provided you with this "
6790 "hardware.\n");
6791 }
6792 strcpy(netdev->name, "eth%d");
6793 err = register_netdev(netdev);
6794 if (err)
6795 goto err_register;
6796
6797 /* carrier off reporting is important to ethtool even BEFORE open */
6798 netif_carrier_off(netdev);
6799
6800 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6801 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6802 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6803
6804 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
6805 INIT_WORK(&adapter->check_overtemp_task, ixgbe_check_overtemp_task);
6806 #ifdef CONFIG_IXGBE_DCA
6807 if (dca_add_requester(&pdev->dev) == 0) {
6808 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
6809 ixgbe_setup_dca(adapter);
6810 }
6811 #endif
6812 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6813 DPRINTK(PROBE, INFO, "IOV is enabled with %d VFs\n",
6814 adapter->num_vfs);
6815 for (i = 0; i < adapter->num_vfs; i++)
6816 ixgbe_vf_configuration(pdev, (i | 0x10000000));
6817 }
6818
6819 /* add san mac addr to netdev */
6820 ixgbe_add_sanmac_netdev(netdev);
6821
6822 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
6823 cards_found++;
6824 return 0;
6825
6826 err_register:
6827 ixgbe_release_hw_control(adapter);
6828 ixgbe_clear_interrupt_scheme(adapter);
6829 err_sw_init:
6830 err_eeprom:
6831 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6832 ixgbe_disable_sriov(adapter);
6833 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6834 del_timer_sync(&adapter->sfp_timer);
6835 cancel_work_sync(&adapter->sfp_task);
6836 cancel_work_sync(&adapter->multispeed_fiber_task);
6837 cancel_work_sync(&adapter->sfp_config_module_task);
6838 iounmap(hw->hw_addr);
6839 err_ioremap:
6840 free_netdev(netdev);
6841 err_alloc_etherdev:
6842 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6843 IORESOURCE_MEM));
6844 err_pci_reg:
6845 err_dma:
6846 pci_disable_device(pdev);
6847 return err;
6848 }
6849
6850 /**
6851 * ixgbe_remove - Device Removal Routine
6852 * @pdev: PCI device information struct
6853 *
6854 * ixgbe_remove is called by the PCI subsystem to alert the driver
6855 * that it should release a PCI device. The could be caused by a
6856 * Hot-Plug event, or because the driver is going to be removed from
6857 * memory.
6858 **/
6859 static void __devexit ixgbe_remove(struct pci_dev *pdev)
6860 {
6861 struct net_device *netdev = pci_get_drvdata(pdev);
6862 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6863
6864 set_bit(__IXGBE_DOWN, &adapter->state);
6865 /* clear the module not found bit to make sure the worker won't
6866 * reschedule
6867 */
6868 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6869 del_timer_sync(&adapter->watchdog_timer);
6870
6871 del_timer_sync(&adapter->sfp_timer);
6872 cancel_work_sync(&adapter->watchdog_task);
6873 cancel_work_sync(&adapter->sfp_task);
6874 cancel_work_sync(&adapter->multispeed_fiber_task);
6875 cancel_work_sync(&adapter->sfp_config_module_task);
6876 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6877 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6878 cancel_work_sync(&adapter->fdir_reinit_task);
6879 flush_scheduled_work();
6880
6881 #ifdef CONFIG_IXGBE_DCA
6882 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
6883 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
6884 dca_remove_requester(&pdev->dev);
6885 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
6886 }
6887
6888 #endif
6889 #ifdef IXGBE_FCOE
6890 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6891 ixgbe_cleanup_fcoe(adapter);
6892
6893 #endif /* IXGBE_FCOE */
6894
6895 /* remove the added san mac */
6896 ixgbe_del_sanmac_netdev(netdev);
6897
6898 if (netdev->reg_state == NETREG_REGISTERED)
6899 unregister_netdev(netdev);
6900
6901 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6902 ixgbe_disable_sriov(adapter);
6903
6904 ixgbe_clear_interrupt_scheme(adapter);
6905
6906 ixgbe_release_hw_control(adapter);
6907
6908 iounmap(adapter->hw.hw_addr);
6909 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6910 IORESOURCE_MEM));
6911
6912 DPRINTK(PROBE, INFO, "complete\n");
6913
6914 free_netdev(netdev);
6915
6916 pci_disable_pcie_error_reporting(pdev);
6917
6918 pci_disable_device(pdev);
6919 }
6920
6921 /**
6922 * ixgbe_io_error_detected - called when PCI error is detected
6923 * @pdev: Pointer to PCI device
6924 * @state: The current pci connection state
6925 *
6926 * This function is called after a PCI bus error affecting
6927 * this device has been detected.
6928 */
6929 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
6930 pci_channel_state_t state)
6931 {
6932 struct net_device *netdev = pci_get_drvdata(pdev);
6933 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6934
6935 netif_device_detach(netdev);
6936
6937 if (state == pci_channel_io_perm_failure)
6938 return PCI_ERS_RESULT_DISCONNECT;
6939
6940 if (netif_running(netdev))
6941 ixgbe_down(adapter);
6942 pci_disable_device(pdev);
6943
6944 /* Request a slot reset. */
6945 return PCI_ERS_RESULT_NEED_RESET;
6946 }
6947
6948 /**
6949 * ixgbe_io_slot_reset - called after the pci bus has been reset.
6950 * @pdev: Pointer to PCI device
6951 *
6952 * Restart the card from scratch, as if from a cold-boot.
6953 */
6954 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
6955 {
6956 struct net_device *netdev = pci_get_drvdata(pdev);
6957 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6958 pci_ers_result_t result;
6959 int err;
6960
6961 if (pci_enable_device_mem(pdev)) {
6962 DPRINTK(PROBE, ERR,
6963 "Cannot re-enable PCI device after reset.\n");
6964 result = PCI_ERS_RESULT_DISCONNECT;
6965 } else {
6966 pci_set_master(pdev);
6967 pci_restore_state(pdev);
6968 pci_save_state(pdev);
6969
6970 pci_wake_from_d3(pdev, false);
6971
6972 ixgbe_reset(adapter);
6973 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6974 result = PCI_ERS_RESULT_RECOVERED;
6975 }
6976
6977 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6978 if (err) {
6979 dev_err(&pdev->dev,
6980 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
6981 /* non-fatal, continue */
6982 }
6983
6984 return result;
6985 }
6986
6987 /**
6988 * ixgbe_io_resume - called when traffic can start flowing again.
6989 * @pdev: Pointer to PCI device
6990 *
6991 * This callback is called when the error recovery driver tells us that
6992 * its OK to resume normal operation.
6993 */
6994 static void ixgbe_io_resume(struct pci_dev *pdev)
6995 {
6996 struct net_device *netdev = pci_get_drvdata(pdev);
6997 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6998
6999 if (netif_running(netdev)) {
7000 if (ixgbe_up(adapter)) {
7001 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
7002 return;
7003 }
7004 }
7005
7006 netif_device_attach(netdev);
7007 }
7008
7009 static struct pci_error_handlers ixgbe_err_handler = {
7010 .error_detected = ixgbe_io_error_detected,
7011 .slot_reset = ixgbe_io_slot_reset,
7012 .resume = ixgbe_io_resume,
7013 };
7014
7015 static struct pci_driver ixgbe_driver = {
7016 .name = ixgbe_driver_name,
7017 .id_table = ixgbe_pci_tbl,
7018 .probe = ixgbe_probe,
7019 .remove = __devexit_p(ixgbe_remove),
7020 #ifdef CONFIG_PM
7021 .suspend = ixgbe_suspend,
7022 .resume = ixgbe_resume,
7023 #endif
7024 .shutdown = ixgbe_shutdown,
7025 .err_handler = &ixgbe_err_handler
7026 };
7027
7028 /**
7029 * ixgbe_init_module - Driver Registration Routine
7030 *
7031 * ixgbe_init_module is the first routine called when the driver is
7032 * loaded. All it does is register with the PCI subsystem.
7033 **/
7034 static int __init ixgbe_init_module(void)
7035 {
7036 int ret;
7037 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
7038 ixgbe_driver_string, ixgbe_driver_version);
7039
7040 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
7041
7042 #ifdef CONFIG_IXGBE_DCA
7043 dca_register_notify(&dca_notifier);
7044 #endif
7045
7046 ret = pci_register_driver(&ixgbe_driver);
7047 return ret;
7048 }
7049
7050 module_init(ixgbe_init_module);
7051
7052 /**
7053 * ixgbe_exit_module - Driver Exit Cleanup Routine
7054 *
7055 * ixgbe_exit_module is called just before the driver is removed
7056 * from memory.
7057 **/
7058 static void __exit ixgbe_exit_module(void)
7059 {
7060 #ifdef CONFIG_IXGBE_DCA
7061 dca_unregister_notify(&dca_notifier);
7062 #endif
7063 pci_unregister_driver(&ixgbe_driver);
7064 }
7065
7066 #ifdef CONFIG_IXGBE_DCA
7067 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7068 void *p)
7069 {
7070 int ret_val;
7071
7072 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7073 __ixgbe_notify_dca);
7074
7075 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7076 }
7077
7078 #endif /* CONFIG_IXGBE_DCA */
7079 #ifdef DEBUG
7080 /**
7081 * ixgbe_get_hw_dev_name - return device name string
7082 * used by hardware layer to print debugging information
7083 **/
7084 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
7085 {
7086 struct ixgbe_adapter *adapter = hw->back;
7087 return adapter->netdev->name;
7088 }
7089
7090 #endif
7091 module_exit(ixgbe_exit_module);
7092
7093 /* ixgbe_main.c */
Linux kernel - Deliverables
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