1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <linux/slab.h>
40 #include <net/checksum.h>
41 #include <net/ip6_checksum.h>
42 #include <linux/ethtool.h>
43 #include <linux/if_vlan.h>
44 #include <scsi/fc/fc_fcoe.h>
47 #include "ixgbe_common.h"
48 #include "ixgbe_dcb_82599.h"
49 #include "ixgbe_sriov.h"
51 char ixgbe_driver_name
[] = "ixgbe";
52 static const char ixgbe_driver_string
[] =
53 "Intel(R) 10 Gigabit PCI Express Network Driver";
55 #define DRV_VERSION "2.0.84-k2"
56 const char ixgbe_driver_version
[] = DRV_VERSION
;
57 static char ixgbe_copyright
[] = "Copyright (c) 1999-2010 Intel Corporation.";
59 static const struct ixgbe_info
*ixgbe_info_tbl
[] = {
60 [board_82598
] = &ixgbe_82598_info
,
61 [board_82599
] = &ixgbe_82599_info
,
64 /* ixgbe_pci_tbl - PCI Device ID Table
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl
) = {
73 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598
),
75 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_DUAL_PORT
),
77 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_SINGLE_PORT
),
79 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT
),
81 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT2
),
83 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_CX4
),
85 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_CX4_DUAL_PORT
),
87 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_DA_DUAL_PORT
),
89 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM
),
91 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_XF_LR
),
93 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_SFP_LOM
),
95 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_BX
),
97 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4
),
99 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_XAUI_LOM
),
101 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KR
),
103 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP
),
105 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP_EM
),
107 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4_MEZZ
),
109 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_CX4
),
111 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_T3_LOM
),
113 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_COMBO_BACKPLANE
),
116 /* required last entry */
119 MODULE_DEVICE_TABLE(pci
, ixgbe_pci_tbl
);
121 #ifdef CONFIG_IXGBE_DCA
122 static int ixgbe_notify_dca(struct notifier_block
*, unsigned long event
,
124 static struct notifier_block dca_notifier
= {
125 .notifier_call
= ixgbe_notify_dca
,
131 #ifdef CONFIG_PCI_IOV
132 static unsigned int max_vfs
;
133 module_param(max_vfs
, uint
, 0);
134 MODULE_PARM_DESC(max_vfs
,
135 "Maximum number of virtual functions to allocate per physical function");
136 #endif /* CONFIG_PCI_IOV */
138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
140 MODULE_LICENSE("GPL");
141 MODULE_VERSION(DRV_VERSION
);
143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter
*adapter
)
147 struct ixgbe_hw
*hw
= &adapter
->hw
;
152 #ifdef CONFIG_PCI_IOV
153 /* disable iov and allow time for transactions to clear */
154 pci_disable_sriov(adapter
->pdev
);
157 /* turn off device IOV mode */
158 gcr
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
159 gcr
&= ~(IXGBE_GCR_EXT_SRIOV
);
160 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, gcr
);
161 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
162 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
163 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
165 /* set default pool back to 0 */
166 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
167 vmdctl
&= ~IXGBE_VT_CTL_POOL_MASK
;
168 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
);
170 /* take a breather then clean up driver data */
173 kfree(adapter
->vfinfo
);
174 adapter
->vfinfo
= NULL
;
176 adapter
->num_vfs
= 0;
177 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
180 struct ixgbe_reg_info
{
185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl
[] = {
187 /* General Registers */
188 {IXGBE_CTRL
, "CTRL"},
189 {IXGBE_STATUS
, "STATUS"},
190 {IXGBE_CTRL_EXT
, "CTRL_EXT"},
192 /* Interrupt Registers */
193 {IXGBE_EICR
, "EICR"},
196 {IXGBE_SRRCTL(0), "SRRCTL"},
197 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
198 {IXGBE_RDLEN(0), "RDLEN"},
199 {IXGBE_RDH(0), "RDH"},
200 {IXGBE_RDT(0), "RDT"},
201 {IXGBE_RXDCTL(0), "RXDCTL"},
202 {IXGBE_RDBAL(0), "RDBAL"},
203 {IXGBE_RDBAH(0), "RDBAH"},
206 {IXGBE_TDBAL(0), "TDBAL"},
207 {IXGBE_TDBAH(0), "TDBAH"},
208 {IXGBE_TDLEN(0), "TDLEN"},
209 {IXGBE_TDH(0), "TDH"},
210 {IXGBE_TDT(0), "TDT"},
211 {IXGBE_TXDCTL(0), "TXDCTL"},
213 /* List Terminator */
219 * ixgbe_regdump - register printout routine
221 static void ixgbe_regdump(struct ixgbe_hw
*hw
, struct ixgbe_reg_info
*reginfo
)
227 switch (reginfo
->ofs
) {
228 case IXGBE_SRRCTL(0):
229 for (i
= 0; i
< 64; i
++)
230 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_SRRCTL(i
));
232 case IXGBE_DCA_RXCTRL(0):
233 for (i
= 0; i
< 64; i
++)
234 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_DCA_RXCTRL(i
));
237 for (i
= 0; i
< 64; i
++)
238 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDLEN(i
));
241 for (i
= 0; i
< 64; i
++)
242 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDH(i
));
245 for (i
= 0; i
< 64; i
++)
246 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDT(i
));
248 case IXGBE_RXDCTL(0):
249 for (i
= 0; i
< 64; i
++)
250 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RXDCTL(i
));
253 for (i
= 0; i
< 64; i
++)
254 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDBAL(i
));
257 for (i
= 0; i
< 64; i
++)
258 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDBAH(i
));
261 for (i
= 0; i
< 64; i
++)
262 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDBAL(i
));
265 for (i
= 0; i
< 64; i
++)
266 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDBAH(i
));
269 for (i
= 0; i
< 64; i
++)
270 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDLEN(i
));
273 for (i
= 0; i
< 64; i
++)
274 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDH(i
));
277 for (i
= 0; i
< 64; i
++)
278 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDT(i
));
280 case IXGBE_TXDCTL(0):
281 for (i
= 0; i
< 64; i
++)
282 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TXDCTL(i
));
285 pr_info("%-15s %08x\n", reginfo
->name
,
286 IXGBE_READ_REG(hw
, reginfo
->ofs
));
290 for (i
= 0; i
< 8; i
++) {
291 snprintf(rname
, 16, "%s[%d-%d]", reginfo
->name
, i
*8, i
*8+7);
292 pr_err("%-15s", rname
);
293 for (j
= 0; j
< 8; j
++)
294 pr_cont(" %08x", regs
[i
*8+j
]);
301 * ixgbe_dump - Print registers, tx-rings and rx-rings
303 static void ixgbe_dump(struct ixgbe_adapter
*adapter
)
305 struct net_device
*netdev
= adapter
->netdev
;
306 struct ixgbe_hw
*hw
= &adapter
->hw
;
307 struct ixgbe_reg_info
*reginfo
;
309 struct ixgbe_ring
*tx_ring
;
310 struct ixgbe_tx_buffer
*tx_buffer_info
;
311 union ixgbe_adv_tx_desc
*tx_desc
;
312 struct my_u0
{ u64 a
; u64 b
; } *u0
;
313 struct ixgbe_ring
*rx_ring
;
314 union ixgbe_adv_rx_desc
*rx_desc
;
315 struct ixgbe_rx_buffer
*rx_buffer_info
;
319 if (!netif_msg_hw(adapter
))
322 /* Print netdevice Info */
324 dev_info(&adapter
->pdev
->dev
, "Net device Info\n");
325 pr_info("Device Name state "
326 "trans_start last_rx\n");
327 pr_info("%-15s %016lX %016lX %016lX\n",
334 /* Print Registers */
335 dev_info(&adapter
->pdev
->dev
, "Register Dump\n");
336 pr_info(" Register Name Value\n");
337 for (reginfo
= (struct ixgbe_reg_info
*)ixgbe_reg_info_tbl
;
338 reginfo
->name
; reginfo
++) {
339 ixgbe_regdump(hw
, reginfo
);
342 /* Print TX Ring Summary */
343 if (!netdev
|| !netif_running(netdev
))
346 dev_info(&adapter
->pdev
->dev
, "TX Rings Summary\n");
347 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
348 for (n
= 0; n
< adapter
->num_tx_queues
; n
++) {
349 tx_ring
= adapter
->tx_ring
[n
];
351 &tx_ring
->tx_buffer_info
[tx_ring
->next_to_clean
];
352 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
353 n
, tx_ring
->next_to_use
, tx_ring
->next_to_clean
,
354 (u64
)tx_buffer_info
->dma
,
355 tx_buffer_info
->length
,
356 tx_buffer_info
->next_to_watch
,
357 (u64
)tx_buffer_info
->time_stamp
);
361 if (!netif_msg_tx_done(adapter
))
362 goto rx_ring_summary
;
364 dev_info(&adapter
->pdev
->dev
, "TX Rings Dump\n");
366 /* Transmit Descriptor Formats
368 * Advanced Transmit Descriptor
369 * +--------------------------------------------------------------+
370 * 0 | Buffer Address [63:0] |
371 * +--------------------------------------------------------------+
372 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
373 * +--------------------------------------------------------------+
374 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
377 for (n
= 0; n
< adapter
->num_tx_queues
; n
++) {
378 tx_ring
= adapter
->tx_ring
[n
];
379 pr_info("------------------------------------\n");
380 pr_info("TX QUEUE INDEX = %d\n", tx_ring
->queue_index
);
381 pr_info("------------------------------------\n");
382 pr_info("T [desc] [address 63:0 ] "
383 "[PlPOIdStDDt Ln] [bi->dma ] "
384 "leng ntw timestamp bi->skb\n");
386 for (i
= 0; tx_ring
->desc
&& (i
< tx_ring
->count
); i
++) {
387 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, i
);
388 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
389 u0
= (struct my_u0
*)tx_desc
;
390 pr_info("T [0x%03X] %016llX %016llX %016llX"
391 " %04X %3X %016llX %p", i
,
394 (u64
)tx_buffer_info
->dma
,
395 tx_buffer_info
->length
,
396 tx_buffer_info
->next_to_watch
,
397 (u64
)tx_buffer_info
->time_stamp
,
398 tx_buffer_info
->skb
);
399 if (i
== tx_ring
->next_to_use
&&
400 i
== tx_ring
->next_to_clean
)
402 else if (i
== tx_ring
->next_to_use
)
404 else if (i
== tx_ring
->next_to_clean
)
409 if (netif_msg_pktdata(adapter
) &&
410 tx_buffer_info
->dma
!= 0)
411 print_hex_dump(KERN_INFO
, "",
412 DUMP_PREFIX_ADDRESS
, 16, 1,
413 phys_to_virt(tx_buffer_info
->dma
),
414 tx_buffer_info
->length
, true);
418 /* Print RX Rings Summary */
420 dev_info(&adapter
->pdev
->dev
, "RX Rings Summary\n");
421 pr_info("Queue [NTU] [NTC]\n");
422 for (n
= 0; n
< adapter
->num_rx_queues
; n
++) {
423 rx_ring
= adapter
->rx_ring
[n
];
424 pr_info("%5d %5X %5X\n",
425 n
, rx_ring
->next_to_use
, rx_ring
->next_to_clean
);
429 if (!netif_msg_rx_status(adapter
))
432 dev_info(&adapter
->pdev
->dev
, "RX Rings Dump\n");
434 /* Advanced Receive Descriptor (Read) Format
436 * +-----------------------------------------------------+
437 * 0 | Packet Buffer Address [63:1] |A0/NSE|
438 * +----------------------------------------------+------+
439 * 8 | Header Buffer Address [63:1] | DD |
440 * +-----------------------------------------------------+
443 * Advanced Receive Descriptor (Write-Back) Format
445 * 63 48 47 32 31 30 21 20 16 15 4 3 0
446 * +------------------------------------------------------+
447 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
448 * | Checksum Ident | | | | Type | Type |
449 * +------------------------------------------------------+
450 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
451 * +------------------------------------------------------+
452 * 63 48 47 32 31 20 19 0
454 for (n
= 0; n
< adapter
->num_rx_queues
; n
++) {
455 rx_ring
= adapter
->rx_ring
[n
];
456 pr_info("------------------------------------\n");
457 pr_info("RX QUEUE INDEX = %d\n", rx_ring
->queue_index
);
458 pr_info("------------------------------------\n");
459 pr_info("R [desc] [ PktBuf A0] "
460 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
461 "<-- Adv Rx Read format\n");
462 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
463 "[vl er S cks ln] ---------------- [bi->skb] "
464 "<-- Adv Rx Write-Back format\n");
466 for (i
= 0; i
< rx_ring
->count
; i
++) {
467 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
468 rx_desc
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
469 u0
= (struct my_u0
*)rx_desc
;
470 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
471 if (staterr
& IXGBE_RXD_STAT_DD
) {
472 /* Descriptor Done */
473 pr_info("RWB[0x%03X] %016llX "
474 "%016llX ---------------- %p", i
,
477 rx_buffer_info
->skb
);
479 pr_info("R [0x%03X] %016llX "
480 "%016llX %016llX %p", i
,
483 (u64
)rx_buffer_info
->dma
,
484 rx_buffer_info
->skb
);
486 if (netif_msg_pktdata(adapter
)) {
487 print_hex_dump(KERN_INFO
, "",
488 DUMP_PREFIX_ADDRESS
, 16, 1,
489 phys_to_virt(rx_buffer_info
->dma
),
490 rx_ring
->rx_buf_len
, true);
492 if (rx_ring
->rx_buf_len
493 < IXGBE_RXBUFFER_2048
)
494 print_hex_dump(KERN_INFO
, "",
495 DUMP_PREFIX_ADDRESS
, 16, 1,
497 rx_buffer_info
->page_dma
+
498 rx_buffer_info
->page_offset
504 if (i
== rx_ring
->next_to_use
)
506 else if (i
== rx_ring
->next_to_clean
)
518 static void ixgbe_release_hw_control(struct ixgbe_adapter
*adapter
)
522 /* Let firmware take over control of h/w */
523 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
524 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
525 ctrl_ext
& ~IXGBE_CTRL_EXT_DRV_LOAD
);
528 static void ixgbe_get_hw_control(struct ixgbe_adapter
*adapter
)
532 /* Let firmware know the driver has taken over */
533 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
534 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
535 ctrl_ext
| IXGBE_CTRL_EXT_DRV_LOAD
);
539 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
540 * @adapter: pointer to adapter struct
541 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
542 * @queue: queue to map the corresponding interrupt to
543 * @msix_vector: the vector to map to the corresponding queue
546 static void ixgbe_set_ivar(struct ixgbe_adapter
*adapter
, s8 direction
,
547 u8 queue
, u8 msix_vector
)
550 struct ixgbe_hw
*hw
= &adapter
->hw
;
551 switch (hw
->mac
.type
) {
552 case ixgbe_mac_82598EB
:
553 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
556 index
= (((direction
* 64) + queue
) >> 2) & 0x1F;
557 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(index
));
558 ivar
&= ~(0xFF << (8 * (queue
& 0x3)));
559 ivar
|= (msix_vector
<< (8 * (queue
& 0x3)));
560 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(index
), ivar
);
562 case ixgbe_mac_82599EB
:
563 if (direction
== -1) {
565 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
566 index
= ((queue
& 1) * 8);
567 ivar
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_IVAR_MISC
);
568 ivar
&= ~(0xFF << index
);
569 ivar
|= (msix_vector
<< index
);
570 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_IVAR_MISC
, ivar
);
573 /* tx or rx causes */
574 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
575 index
= ((16 * (queue
& 1)) + (8 * direction
));
576 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(queue
>> 1));
577 ivar
&= ~(0xFF << index
);
578 ivar
|= (msix_vector
<< index
);
579 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(queue
>> 1), ivar
);
587 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter
*adapter
,
592 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
593 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
594 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS
, mask
);
596 mask
= (qmask
& 0xFFFFFFFF);
597 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(0), mask
);
598 mask
= (qmask
>> 32);
599 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(1), mask
);
603 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter
*adapter
,
604 struct ixgbe_tx_buffer
607 if (tx_buffer_info
->dma
) {
608 if (tx_buffer_info
->mapped_as_page
)
609 dma_unmap_page(&adapter
->pdev
->dev
,
611 tx_buffer_info
->length
,
614 dma_unmap_single(&adapter
->pdev
->dev
,
616 tx_buffer_info
->length
,
618 tx_buffer_info
->dma
= 0;
620 if (tx_buffer_info
->skb
) {
621 dev_kfree_skb_any(tx_buffer_info
->skb
);
622 tx_buffer_info
->skb
= NULL
;
624 tx_buffer_info
->time_stamp
= 0;
625 /* tx_buffer_info must be completely set up in the transmit path */
629 * ixgbe_tx_xon_state - check the tx ring xon state
630 * @adapter: the ixgbe adapter
631 * @tx_ring: the corresponding tx_ring
633 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
634 * corresponding TC of this tx_ring when checking TFCS.
636 * Returns : true if in xon state (currently not paused)
638 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter
*adapter
,
639 struct ixgbe_ring
*tx_ring
)
641 u32 txoff
= IXGBE_TFCS_TXOFF
;
643 #ifdef CONFIG_IXGBE_DCB
644 if (adapter
->dcb_cfg
.pfc_mode_enable
) {
646 int reg_idx
= tx_ring
->reg_idx
;
647 int dcb_i
= adapter
->ring_feature
[RING_F_DCB
].indices
;
649 switch (adapter
->hw
.mac
.type
) {
650 case ixgbe_mac_82598EB
:
652 txoff
= IXGBE_TFCS_TXOFF0
;
654 case ixgbe_mac_82599EB
:
656 txoff
= IXGBE_TFCS_TXOFF
;
660 if (tc
== 2) /* TC2, TC3 */
661 tc
+= (reg_idx
- 64) >> 4;
662 else if (tc
== 3) /* TC4, TC5, TC6, TC7 */
663 tc
+= 1 + ((reg_idx
- 96) >> 3);
664 } else if (dcb_i
== 4) {
668 tc
+= (reg_idx
- 64) >> 5;
669 if (tc
== 2) /* TC2, TC3 */
670 tc
+= (reg_idx
- 96) >> 4;
680 return IXGBE_READ_REG(&adapter
->hw
, IXGBE_TFCS
) & txoff
;
683 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter
*adapter
,
684 struct ixgbe_ring
*tx_ring
,
687 struct ixgbe_hw
*hw
= &adapter
->hw
;
689 /* Detect a transmit hang in hardware, this serializes the
690 * check with the clearing of time_stamp and movement of eop */
691 adapter
->detect_tx_hung
= false;
692 if (tx_ring
->tx_buffer_info
[eop
].time_stamp
&&
693 time_after(jiffies
, tx_ring
->tx_buffer_info
[eop
].time_stamp
+ HZ
) &&
694 ixgbe_tx_xon_state(adapter
, tx_ring
)) {
695 /* detected Tx unit hang */
696 union ixgbe_adv_tx_desc
*tx_desc
;
697 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, eop
);
698 e_err(drv
, "Detected Tx Unit Hang\n"
700 " TDH, TDT <%x>, <%x>\n"
701 " next_to_use <%x>\n"
702 " next_to_clean <%x>\n"
703 "tx_buffer_info[next_to_clean]\n"
704 " time_stamp <%lx>\n"
706 tx_ring
->queue_index
,
707 IXGBE_READ_REG(hw
, tx_ring
->head
),
708 IXGBE_READ_REG(hw
, tx_ring
->tail
),
709 tx_ring
->next_to_use
, eop
,
710 tx_ring
->tx_buffer_info
[eop
].time_stamp
, jiffies
);
717 #define IXGBE_MAX_TXD_PWR 14
718 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
720 /* Tx Descriptors needed, worst case */
721 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
722 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
723 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
724 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
726 static void ixgbe_tx_timeout(struct net_device
*netdev
);
729 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
730 * @q_vector: structure containing interrupt and ring information
731 * @tx_ring: tx ring to clean
733 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector
*q_vector
,
734 struct ixgbe_ring
*tx_ring
)
736 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
737 struct net_device
*netdev
= adapter
->netdev
;
738 union ixgbe_adv_tx_desc
*tx_desc
, *eop_desc
;
739 struct ixgbe_tx_buffer
*tx_buffer_info
;
740 unsigned int i
, eop
, count
= 0;
741 unsigned int total_bytes
= 0, total_packets
= 0;
743 i
= tx_ring
->next_to_clean
;
744 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
745 eop_desc
= IXGBE_TX_DESC_ADV(tx_ring
, eop
);
747 while ((eop_desc
->wb
.status
& cpu_to_le32(IXGBE_TXD_STAT_DD
)) &&
748 (count
< tx_ring
->work_limit
)) {
749 bool cleaned
= false;
750 rmb(); /* read buffer_info after eop_desc */
751 for ( ; !cleaned
; count
++) {
753 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, i
);
754 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
755 cleaned
= (i
== eop
);
756 skb
= tx_buffer_info
->skb
;
758 if (cleaned
&& skb
) {
759 unsigned int segs
, bytecount
;
760 unsigned int hlen
= skb_headlen(skb
);
762 /* gso_segs is currently only valid for tcp */
763 segs
= skb_shinfo(skb
)->gso_segs
?: 1;
765 /* adjust for FCoE Sequence Offload */
766 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
768 && vlan_get_protocol(skb
) ==
770 hlen
= skb_transport_offset(skb
) +
771 sizeof(struct fc_frame_header
) +
772 sizeof(struct fcoe_crc_eof
);
773 segs
= DIV_ROUND_UP(skb
->len
- hlen
,
774 skb_shinfo(skb
)->gso_size
);
776 #endif /* IXGBE_FCOE */
777 /* multiply data chunks by size of headers */
778 bytecount
= ((segs
- 1) * hlen
) + skb
->len
;
779 total_packets
+= segs
;
780 total_bytes
+= bytecount
;
783 ixgbe_unmap_and_free_tx_resource(adapter
,
786 tx_desc
->wb
.status
= 0;
789 if (i
== tx_ring
->count
)
793 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
794 eop_desc
= IXGBE_TX_DESC_ADV(tx_ring
, eop
);
797 tx_ring
->next_to_clean
= i
;
799 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
800 if (unlikely(count
&& netif_carrier_ok(netdev
) &&
801 (IXGBE_DESC_UNUSED(tx_ring
) >= TX_WAKE_THRESHOLD
))) {
802 /* Make sure that anybody stopping the queue after this
803 * sees the new next_to_clean.
806 if (__netif_subqueue_stopped(netdev
, tx_ring
->queue_index
) &&
807 !test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
808 netif_wake_subqueue(netdev
, tx_ring
->queue_index
);
809 ++tx_ring
->restart_queue
;
813 if (adapter
->detect_tx_hung
) {
814 if (ixgbe_check_tx_hang(adapter
, tx_ring
, i
)) {
815 /* schedule immediate reset if we believe we hung */
816 e_info(probe
, "tx hang %d detected, resetting "
817 "adapter\n", adapter
->tx_timeout_count
+ 1);
818 ixgbe_tx_timeout(adapter
->netdev
);
822 /* re-arm the interrupt */
823 if (count
>= tx_ring
->work_limit
)
824 ixgbe_irq_rearm_queues(adapter
, ((u64
)1 << q_vector
->v_idx
));
826 tx_ring
->total_bytes
+= total_bytes
;
827 tx_ring
->total_packets
+= total_packets
;
828 u64_stats_update_begin(&tx_ring
->syncp
);
829 tx_ring
->stats
.packets
+= total_packets
;
830 tx_ring
->stats
.bytes
+= total_bytes
;
831 u64_stats_update_end(&tx_ring
->syncp
);
832 return count
< tx_ring
->work_limit
;
835 #ifdef CONFIG_IXGBE_DCA
836 static void ixgbe_update_rx_dca(struct ixgbe_adapter
*adapter
,
837 struct ixgbe_ring
*rx_ring
)
841 int q
= rx_ring
->reg_idx
;
843 if (rx_ring
->cpu
!= cpu
) {
844 rxctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_DCA_RXCTRL(q
));
845 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
846 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK
;
847 rxctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
848 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
849 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599
;
850 rxctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
851 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599
);
853 rxctrl
|= IXGBE_DCA_RXCTRL_DESC_DCA_EN
;
854 rxctrl
|= IXGBE_DCA_RXCTRL_HEAD_DCA_EN
;
855 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN
);
856 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN
|
857 IXGBE_DCA_RXCTRL_DESC_HSRO_EN
);
858 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_RXCTRL(q
), rxctrl
);
864 static void ixgbe_update_tx_dca(struct ixgbe_adapter
*adapter
,
865 struct ixgbe_ring
*tx_ring
)
869 int q
= tx_ring
->reg_idx
;
870 struct ixgbe_hw
*hw
= &adapter
->hw
;
872 if (tx_ring
->cpu
!= cpu
) {
873 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
874 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL(q
));
875 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK
;
876 txctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
877 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
878 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL(q
), txctrl
);
879 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
880 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL_82599(q
));
881 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599
;
882 txctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
883 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599
);
884 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
885 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL_82599(q
), txctrl
);
892 static void ixgbe_setup_dca(struct ixgbe_adapter
*adapter
)
896 if (!(adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
))
899 /* always use CB2 mode, difference is masked in the CB driver */
900 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 2);
902 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
903 adapter
->tx_ring
[i
]->cpu
= -1;
904 ixgbe_update_tx_dca(adapter
, adapter
->tx_ring
[i
]);
906 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
907 adapter
->rx_ring
[i
]->cpu
= -1;
908 ixgbe_update_rx_dca(adapter
, adapter
->rx_ring
[i
]);
912 static int __ixgbe_notify_dca(struct device
*dev
, void *data
)
914 struct net_device
*netdev
= dev_get_drvdata(dev
);
915 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
916 unsigned long event
= *(unsigned long *)data
;
919 case DCA_PROVIDER_ADD
:
920 /* if we're already enabled, don't do it again */
921 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
923 if (dca_add_requester(dev
) == 0) {
924 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
925 ixgbe_setup_dca(adapter
);
928 /* Fall Through since DCA is disabled. */
929 case DCA_PROVIDER_REMOVE
:
930 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
931 dca_remove_requester(dev
);
932 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
933 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
941 #endif /* CONFIG_IXGBE_DCA */
943 * ixgbe_receive_skb - Send a completed packet up the stack
944 * @adapter: board private structure
945 * @skb: packet to send up
946 * @status: hardware indication of status of receive
947 * @rx_ring: rx descriptor ring (for a specific queue) to setup
948 * @rx_desc: rx descriptor
950 static void ixgbe_receive_skb(struct ixgbe_q_vector
*q_vector
,
951 struct sk_buff
*skb
, u8 status
,
952 struct ixgbe_ring
*ring
,
953 union ixgbe_adv_rx_desc
*rx_desc
)
955 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
956 struct napi_struct
*napi
= &q_vector
->napi
;
957 bool is_vlan
= (status
& IXGBE_RXD_STAT_VP
);
958 u16 tag
= le16_to_cpu(rx_desc
->wb
.upper
.vlan
);
960 if (is_vlan
&& (tag
& VLAN_VID_MASK
))
961 __vlan_hwaccel_put_tag(skb
, tag
);
963 if (!(adapter
->flags
& IXGBE_FLAG_IN_NETPOLL
))
964 napi_gro_receive(napi
, skb
);
970 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
971 * @adapter: address of board private structure
972 * @status_err: hardware indication of status of receive
973 * @skb: skb currently being received and modified
975 static inline void ixgbe_rx_checksum(struct ixgbe_adapter
*adapter
,
976 union ixgbe_adv_rx_desc
*rx_desc
,
979 u32 status_err
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
981 skb_checksum_none_assert(skb
);
983 /* Rx csum disabled */
984 if (!(adapter
->flags
& IXGBE_FLAG_RX_CSUM_ENABLED
))
987 /* if IP and error */
988 if ((status_err
& IXGBE_RXD_STAT_IPCS
) &&
989 (status_err
& IXGBE_RXDADV_ERR_IPE
)) {
990 adapter
->hw_csum_rx_error
++;
994 if (!(status_err
& IXGBE_RXD_STAT_L4CS
))
997 if (status_err
& IXGBE_RXDADV_ERR_TCPE
) {
998 u16 pkt_info
= rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
1001 * 82599 errata, UDP frames with a 0 checksum can be marked as
1004 if ((pkt_info
& IXGBE_RXDADV_PKTTYPE_UDP
) &&
1005 (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
))
1008 adapter
->hw_csum_rx_error
++;
1012 /* It must be a TCP or UDP packet with a valid checksum */
1013 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1016 static inline void ixgbe_release_rx_desc(struct ixgbe_hw
*hw
,
1017 struct ixgbe_ring
*rx_ring
, u32 val
)
1020 * Force memory writes to complete before letting h/w
1021 * know there are new descriptors to fetch. (Only
1022 * applicable for weak-ordered memory model archs,
1026 IXGBE_WRITE_REG(hw
, IXGBE_RDT(rx_ring
->reg_idx
), val
);
1030 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1031 * @adapter: address of board private structure
1033 void ixgbe_alloc_rx_buffers(struct ixgbe_adapter
*adapter
,
1034 struct ixgbe_ring
*rx_ring
,
1037 struct net_device
*netdev
= adapter
->netdev
;
1038 struct pci_dev
*pdev
= adapter
->pdev
;
1039 union ixgbe_adv_rx_desc
*rx_desc
;
1040 struct ixgbe_rx_buffer
*bi
;
1042 unsigned int bufsz
= rx_ring
->rx_buf_len
;
1044 i
= rx_ring
->next_to_use
;
1045 bi
= &rx_ring
->rx_buffer_info
[i
];
1047 while (cleaned_count
--) {
1048 rx_desc
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
1050 if (!bi
->page_dma
&&
1051 (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
)) {
1053 bi
->page
= netdev_alloc_page(netdev
);
1055 adapter
->alloc_rx_page_failed
++;
1058 bi
->page_offset
= 0;
1060 /* use a half page if we're re-using */
1061 bi
->page_offset
^= (PAGE_SIZE
/ 2);
1064 bi
->page_dma
= dma_map_page(&pdev
->dev
, bi
->page
,
1071 struct sk_buff
*skb
= netdev_alloc_skb_ip_align(netdev
,
1076 adapter
->alloc_rx_buff_failed
++;
1079 /* initialize queue mapping */
1080 skb_record_rx_queue(skb
, rx_ring
->queue_index
);
1084 bi
->dma
= dma_map_single(&pdev
->dev
,
1086 rx_ring
->rx_buf_len
,
1089 /* Refresh the desc even if buffer_addrs didn't change because
1090 * each write-back erases this info. */
1091 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
1092 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->page_dma
);
1093 rx_desc
->read
.hdr_addr
= cpu_to_le64(bi
->dma
);
1095 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->dma
);
1096 rx_desc
->read
.hdr_addr
= 0;
1100 if (i
== rx_ring
->count
)
1102 bi
= &rx_ring
->rx_buffer_info
[i
];
1106 if (rx_ring
->next_to_use
!= i
) {
1107 rx_ring
->next_to_use
= i
;
1109 i
= (rx_ring
->count
- 1);
1111 ixgbe_release_rx_desc(&adapter
->hw
, rx_ring
, i
);
1115 static inline u16
ixgbe_get_hdr_info(union ixgbe_adv_rx_desc
*rx_desc
)
1117 return rx_desc
->wb
.lower
.lo_dword
.hs_rss
.hdr_info
;
1120 static inline u16
ixgbe_get_pkt_info(union ixgbe_adv_rx_desc
*rx_desc
)
1122 return rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
1125 static inline u32
ixgbe_get_rsc_count(union ixgbe_adv_rx_desc
*rx_desc
)
1127 return (le32_to_cpu(rx_desc
->wb
.lower
.lo_dword
.data
) &
1128 IXGBE_RXDADV_RSCCNT_MASK
) >>
1129 IXGBE_RXDADV_RSCCNT_SHIFT
;
1133 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1134 * @skb: pointer to the last skb in the rsc queue
1135 * @count: pointer to number of packets coalesced in this context
1137 * This function changes a queue full of hw rsc buffers into a completed
1138 * packet. It uses the ->prev pointers to find the first packet and then
1139 * turns it into the frag list owner.
1141 static inline struct sk_buff
*ixgbe_transform_rsc_queue(struct sk_buff
*skb
,
1144 unsigned int frag_list_size
= 0;
1147 struct sk_buff
*prev
= skb
->prev
;
1148 frag_list_size
+= skb
->len
;
1154 skb_shinfo(skb
)->frag_list
= skb
->next
;
1156 skb
->len
+= frag_list_size
;
1157 skb
->data_len
+= frag_list_size
;
1158 skb
->truesize
+= frag_list_size
;
1162 struct ixgbe_rsc_cb
{
1167 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1169 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector
*q_vector
,
1170 struct ixgbe_ring
*rx_ring
,
1171 int *work_done
, int work_to_do
)
1173 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1174 struct pci_dev
*pdev
= adapter
->pdev
;
1175 union ixgbe_adv_rx_desc
*rx_desc
, *next_rxd
;
1176 struct ixgbe_rx_buffer
*rx_buffer_info
, *next_buffer
;
1177 struct sk_buff
*skb
;
1178 unsigned int i
, rsc_count
= 0;
1181 bool cleaned
= false;
1182 int cleaned_count
= 0;
1183 unsigned int total_rx_bytes
= 0, total_rx_packets
= 0;
1186 #endif /* IXGBE_FCOE */
1188 i
= rx_ring
->next_to_clean
;
1189 rx_desc
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
1190 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1191 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
1193 while (staterr
& IXGBE_RXD_STAT_DD
) {
1195 if (*work_done
>= work_to_do
)
1199 rmb(); /* read descriptor and rx_buffer_info after status DD */
1200 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
1201 hdr_info
= le16_to_cpu(ixgbe_get_hdr_info(rx_desc
));
1202 len
= (hdr_info
& IXGBE_RXDADV_HDRBUFLEN_MASK
) >>
1203 IXGBE_RXDADV_HDRBUFLEN_SHIFT
;
1204 upper_len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1205 if ((len
> IXGBE_RX_HDR_SIZE
) ||
1206 (upper_len
&& !(hdr_info
& IXGBE_RXDADV_SPH
)))
1207 len
= IXGBE_RX_HDR_SIZE
;
1209 len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1213 skb
= rx_buffer_info
->skb
;
1214 prefetch(skb
->data
);
1215 rx_buffer_info
->skb
= NULL
;
1217 if (rx_buffer_info
->dma
) {
1218 if ((adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) &&
1219 (!(staterr
& IXGBE_RXD_STAT_EOP
)) &&
1222 * When HWRSC is enabled, delay unmapping
1223 * of the first packet. It carries the
1224 * header information, HW may still
1225 * access the header after the writeback.
1226 * Only unmap it when EOP is reached
1228 IXGBE_RSC_CB(skb
)->delay_unmap
= true;
1229 IXGBE_RSC_CB(skb
)->dma
= rx_buffer_info
->dma
;
1231 dma_unmap_single(&pdev
->dev
,
1232 rx_buffer_info
->dma
,
1233 rx_ring
->rx_buf_len
,
1236 rx_buffer_info
->dma
= 0;
1241 dma_unmap_page(&pdev
->dev
, rx_buffer_info
->page_dma
,
1242 PAGE_SIZE
/ 2, DMA_FROM_DEVICE
);
1243 rx_buffer_info
->page_dma
= 0;
1244 skb_fill_page_desc(skb
, skb_shinfo(skb
)->nr_frags
,
1245 rx_buffer_info
->page
,
1246 rx_buffer_info
->page_offset
,
1249 if ((rx_ring
->rx_buf_len
> (PAGE_SIZE
/ 2)) ||
1250 (page_count(rx_buffer_info
->page
) != 1))
1251 rx_buffer_info
->page
= NULL
;
1253 get_page(rx_buffer_info
->page
);
1255 skb
->len
+= upper_len
;
1256 skb
->data_len
+= upper_len
;
1257 skb
->truesize
+= upper_len
;
1261 if (i
== rx_ring
->count
)
1264 next_rxd
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
1268 if (adapter
->flags2
& IXGBE_FLAG2_RSC_CAPABLE
)
1269 rsc_count
= ixgbe_get_rsc_count(rx_desc
);
1272 u32 nextp
= (staterr
& IXGBE_RXDADV_NEXTP_MASK
) >>
1273 IXGBE_RXDADV_NEXTP_SHIFT
;
1274 next_buffer
= &rx_ring
->rx_buffer_info
[nextp
];
1276 next_buffer
= &rx_ring
->rx_buffer_info
[i
];
1279 if (staterr
& IXGBE_RXD_STAT_EOP
) {
1281 skb
= ixgbe_transform_rsc_queue(skb
,
1282 &(rx_ring
->rsc_count
));
1283 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
1284 if (IXGBE_RSC_CB(skb
)->delay_unmap
) {
1285 dma_unmap_single(&pdev
->dev
,
1286 IXGBE_RSC_CB(skb
)->dma
,
1287 rx_ring
->rx_buf_len
,
1289 IXGBE_RSC_CB(skb
)->dma
= 0;
1290 IXGBE_RSC_CB(skb
)->delay_unmap
= false;
1292 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
)
1293 rx_ring
->rsc_count
+=
1294 skb_shinfo(skb
)->nr_frags
;
1296 rx_ring
->rsc_count
++;
1297 rx_ring
->rsc_flush
++;
1299 u64_stats_update_begin(&rx_ring
->syncp
);
1300 rx_ring
->stats
.packets
++;
1301 rx_ring
->stats
.bytes
+= skb
->len
;
1302 u64_stats_update_end(&rx_ring
->syncp
);
1304 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
1305 rx_buffer_info
->skb
= next_buffer
->skb
;
1306 rx_buffer_info
->dma
= next_buffer
->dma
;
1307 next_buffer
->skb
= skb
;
1308 next_buffer
->dma
= 0;
1310 skb
->next
= next_buffer
->skb
;
1311 skb
->next
->prev
= skb
;
1313 rx_ring
->non_eop_descs
++;
1317 if (staterr
& IXGBE_RXDADV_ERR_FRAME_ERR_MASK
) {
1318 dev_kfree_skb_irq(skb
);
1322 ixgbe_rx_checksum(adapter
, rx_desc
, skb
);
1324 /* probably a little skewed due to removing CRC */
1325 total_rx_bytes
+= skb
->len
;
1328 skb
->protocol
= eth_type_trans(skb
, adapter
->netdev
);
1330 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1331 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
1332 ddp_bytes
= ixgbe_fcoe_ddp(adapter
, rx_desc
, skb
);
1336 #endif /* IXGBE_FCOE */
1337 ixgbe_receive_skb(q_vector
, skb
, staterr
, rx_ring
, rx_desc
);
1340 rx_desc
->wb
.upper
.status_error
= 0;
1342 /* return some buffers to hardware, one at a time is too slow */
1343 if (cleaned_count
>= IXGBE_RX_BUFFER_WRITE
) {
1344 ixgbe_alloc_rx_buffers(adapter
, rx_ring
, cleaned_count
);
1348 /* use prefetched values */
1350 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
1352 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1355 rx_ring
->next_to_clean
= i
;
1356 cleaned_count
= IXGBE_DESC_UNUSED(rx_ring
);
1359 ixgbe_alloc_rx_buffers(adapter
, rx_ring
, cleaned_count
);
1362 /* include DDPed FCoE data */
1363 if (ddp_bytes
> 0) {
1366 mss
= adapter
->netdev
->mtu
- sizeof(struct fcoe_hdr
) -
1367 sizeof(struct fc_frame_header
) -
1368 sizeof(struct fcoe_crc_eof
);
1371 total_rx_bytes
+= ddp_bytes
;
1372 total_rx_packets
+= DIV_ROUND_UP(ddp_bytes
, mss
);
1374 #endif /* IXGBE_FCOE */
1376 rx_ring
->total_packets
+= total_rx_packets
;
1377 rx_ring
->total_bytes
+= total_rx_bytes
;
1382 static int ixgbe_clean_rxonly(struct napi_struct
*, int);
1384 * ixgbe_configure_msix - Configure MSI-X hardware
1385 * @adapter: board private structure
1387 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1390 static void ixgbe_configure_msix(struct ixgbe_adapter
*adapter
)
1392 struct ixgbe_q_vector
*q_vector
;
1393 int i
, j
, q_vectors
, v_idx
, r_idx
;
1396 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1399 * Populate the IVAR table and set the ITR values to the
1400 * corresponding register.
1402 for (v_idx
= 0; v_idx
< q_vectors
; v_idx
++) {
1403 q_vector
= adapter
->q_vector
[v_idx
];
1404 /* XXX for_each_set_bit(...) */
1405 r_idx
= find_first_bit(q_vector
->rxr_idx
,
1406 adapter
->num_rx_queues
);
1408 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1409 j
= adapter
->rx_ring
[r_idx
]->reg_idx
;
1410 ixgbe_set_ivar(adapter
, 0, j
, v_idx
);
1411 r_idx
= find_next_bit(q_vector
->rxr_idx
,
1412 adapter
->num_rx_queues
,
1415 r_idx
= find_first_bit(q_vector
->txr_idx
,
1416 adapter
->num_tx_queues
);
1418 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1419 j
= adapter
->tx_ring
[r_idx
]->reg_idx
;
1420 ixgbe_set_ivar(adapter
, 1, j
, v_idx
);
1421 r_idx
= find_next_bit(q_vector
->txr_idx
,
1422 adapter
->num_tx_queues
,
1426 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
1428 q_vector
->eitr
= adapter
->tx_eitr_param
;
1429 else if (q_vector
->rxr_count
)
1431 q_vector
->eitr
= adapter
->rx_eitr_param
;
1433 ixgbe_write_eitr(q_vector
);
1434 /* If Flow Director is enabled, set interrupt affinity */
1435 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
1436 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)) {
1438 * Allocate the affinity_hint cpumask, assign the mask
1439 * for this vector, and set our affinity_hint for
1442 if (!alloc_cpumask_var(&q_vector
->affinity_mask
,
1445 cpumask_set_cpu(v_idx
, q_vector
->affinity_mask
);
1446 irq_set_affinity_hint(adapter
->msix_entries
[v_idx
].vector
,
1447 q_vector
->affinity_mask
);
1451 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
1452 ixgbe_set_ivar(adapter
, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX
,
1454 else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
1455 ixgbe_set_ivar(adapter
, -1, 1, v_idx
);
1456 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITR(v_idx
), 1950);
1458 /* set up to autoclear timer, and the vectors */
1459 mask
= IXGBE_EIMS_ENABLE_MASK
;
1460 if (adapter
->num_vfs
)
1461 mask
&= ~(IXGBE_EIMS_OTHER
|
1462 IXGBE_EIMS_MAILBOX
|
1465 mask
&= ~(IXGBE_EIMS_OTHER
| IXGBE_EIMS_LSC
);
1466 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIAC
, mask
);
1469 enum latency_range
{
1473 latency_invalid
= 255
1477 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1478 * @adapter: pointer to adapter
1479 * @eitr: eitr setting (ints per sec) to give last timeslice
1480 * @itr_setting: current throttle rate in ints/second
1481 * @packets: the number of packets during this measurement interval
1482 * @bytes: the number of bytes during this measurement interval
1484 * Stores a new ITR value based on packets and byte
1485 * counts during the last interrupt. The advantage of per interrupt
1486 * computation is faster updates and more accurate ITR for the current
1487 * traffic pattern. Constants in this function were computed
1488 * based on theoretical maximum wire speed and thresholds were set based
1489 * on testing data as well as attempting to minimize response time
1490 * while increasing bulk throughput.
1491 * this functionality is controlled by the InterruptThrottleRate module
1492 * parameter (see ixgbe_param.c)
1494 static u8
ixgbe_update_itr(struct ixgbe_adapter
*adapter
,
1495 u32 eitr
, u8 itr_setting
,
1496 int packets
, int bytes
)
1498 unsigned int retval
= itr_setting
;
1503 goto update_itr_done
;
1506 /* simple throttlerate management
1507 * 0-20MB/s lowest (100000 ints/s)
1508 * 20-100MB/s low (20000 ints/s)
1509 * 100-1249MB/s bulk (8000 ints/s)
1511 /* what was last interrupt timeslice? */
1512 timepassed_us
= 1000000/eitr
;
1513 bytes_perint
= bytes
/ timepassed_us
; /* bytes/usec */
1515 switch (itr_setting
) {
1516 case lowest_latency
:
1517 if (bytes_perint
> adapter
->eitr_low
)
1518 retval
= low_latency
;
1521 if (bytes_perint
> adapter
->eitr_high
)
1522 retval
= bulk_latency
;
1523 else if (bytes_perint
<= adapter
->eitr_low
)
1524 retval
= lowest_latency
;
1527 if (bytes_perint
<= adapter
->eitr_high
)
1528 retval
= low_latency
;
1537 * ixgbe_write_eitr - write EITR register in hardware specific way
1538 * @q_vector: structure containing interrupt and ring information
1540 * This function is made to be called by ethtool and by the driver
1541 * when it needs to update EITR registers at runtime. Hardware
1542 * specific quirks/differences are taken care of here.
1544 void ixgbe_write_eitr(struct ixgbe_q_vector
*q_vector
)
1546 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1547 struct ixgbe_hw
*hw
= &adapter
->hw
;
1548 int v_idx
= q_vector
->v_idx
;
1549 u32 itr_reg
= EITR_INTS_PER_SEC_TO_REG(q_vector
->eitr
);
1551 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1552 /* must write high and low 16 bits to reset counter */
1553 itr_reg
|= (itr_reg
<< 16);
1554 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
1556 * 82599 can support a value of zero, so allow it for
1557 * max interrupt rate, but there is an errata where it can
1558 * not be zero with RSC
1561 !(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
))
1565 * set the WDIS bit to not clear the timer bits and cause an
1566 * immediate assertion of the interrupt
1568 itr_reg
|= IXGBE_EITR_CNT_WDIS
;
1570 IXGBE_WRITE_REG(hw
, IXGBE_EITR(v_idx
), itr_reg
);
1573 static void ixgbe_set_itr_msix(struct ixgbe_q_vector
*q_vector
)
1575 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1577 u8 current_itr
, ret_itr
;
1579 struct ixgbe_ring
*rx_ring
, *tx_ring
;
1581 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1582 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1583 tx_ring
= adapter
->tx_ring
[r_idx
];
1584 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1586 tx_ring
->total_packets
,
1587 tx_ring
->total_bytes
);
1588 /* if the result for this queue would decrease interrupt
1589 * rate for this vector then use that result */
1590 q_vector
->tx_itr
= ((q_vector
->tx_itr
> ret_itr
) ?
1591 q_vector
->tx_itr
- 1 : ret_itr
);
1592 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1596 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1597 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1598 rx_ring
= adapter
->rx_ring
[r_idx
];
1599 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1601 rx_ring
->total_packets
,
1602 rx_ring
->total_bytes
);
1603 /* if the result for this queue would decrease interrupt
1604 * rate for this vector then use that result */
1605 q_vector
->rx_itr
= ((q_vector
->rx_itr
> ret_itr
) ?
1606 q_vector
->rx_itr
- 1 : ret_itr
);
1607 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1611 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
1613 switch (current_itr
) {
1614 /* counts and packets in update_itr are dependent on these numbers */
1615 case lowest_latency
:
1619 new_itr
= 20000; /* aka hwitr = ~200 */
1627 if (new_itr
!= q_vector
->eitr
) {
1628 /* do an exponential smoothing */
1629 new_itr
= ((q_vector
->eitr
* 90)/100) + ((new_itr
* 10)/100);
1631 /* save the algorithm value here, not the smoothed one */
1632 q_vector
->eitr
= new_itr
;
1634 ixgbe_write_eitr(q_vector
);
1639 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1640 * @work: pointer to work_struct containing our data
1642 static void ixgbe_check_overtemp_task(struct work_struct
*work
)
1644 struct ixgbe_adapter
*adapter
= container_of(work
,
1645 struct ixgbe_adapter
,
1646 check_overtemp_task
);
1647 struct ixgbe_hw
*hw
= &adapter
->hw
;
1648 u32 eicr
= adapter
->interrupt_event
;
1650 if (!(adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
))
1653 switch (hw
->device_id
) {
1654 case IXGBE_DEV_ID_82599_T3_LOM
: {
1656 bool link_up
= false;
1658 if (hw
->mac
.ops
.check_link
)
1659 hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
1661 if (((eicr
& IXGBE_EICR_GPI_SDP0
) && (!link_up
)) ||
1662 (eicr
& IXGBE_EICR_LSC
))
1663 /* Check if this is due to overtemp */
1664 if (hw
->phy
.ops
.check_overtemp(hw
) == IXGBE_ERR_OVERTEMP
)
1669 if (!(eicr
& IXGBE_EICR_GPI_SDP0
))
1674 "Network adapter has been stopped because it has over heated. "
1675 "Restart the computer. If the problem persists, "
1676 "power off the system and replace the adapter\n");
1677 /* write to clear the interrupt */
1678 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP0
);
1681 static void ixgbe_check_fan_failure(struct ixgbe_adapter
*adapter
, u32 eicr
)
1683 struct ixgbe_hw
*hw
= &adapter
->hw
;
1685 if ((adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) &&
1686 (eicr
& IXGBE_EICR_GPI_SDP1
)) {
1687 e_crit(probe
, "Fan has stopped, replace the adapter\n");
1688 /* write to clear the interrupt */
1689 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1693 static void ixgbe_check_sfp_event(struct ixgbe_adapter
*adapter
, u32 eicr
)
1695 struct ixgbe_hw
*hw
= &adapter
->hw
;
1697 if (eicr
& IXGBE_EICR_GPI_SDP1
) {
1698 /* Clear the interrupt */
1699 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1700 schedule_work(&adapter
->multispeed_fiber_task
);
1701 } else if (eicr
& IXGBE_EICR_GPI_SDP2
) {
1702 /* Clear the interrupt */
1703 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP2
);
1704 schedule_work(&adapter
->sfp_config_module_task
);
1706 /* Interrupt isn't for us... */
1711 static void ixgbe_check_lsc(struct ixgbe_adapter
*adapter
)
1713 struct ixgbe_hw
*hw
= &adapter
->hw
;
1716 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
1717 adapter
->link_check_timeout
= jiffies
;
1718 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1719 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_EIMC_LSC
);
1720 IXGBE_WRITE_FLUSH(hw
);
1721 schedule_work(&adapter
->watchdog_task
);
1725 static irqreturn_t
ixgbe_msix_lsc(int irq
, void *data
)
1727 struct net_device
*netdev
= data
;
1728 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
1729 struct ixgbe_hw
*hw
= &adapter
->hw
;
1733 * Workaround for Silicon errata. Use clear-by-write instead
1734 * of clear-by-read. Reading with EICS will return the
1735 * interrupt causes without clearing, which later be done
1736 * with the write to EICR.
1738 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICS
);
1739 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, eicr
);
1741 if (eicr
& IXGBE_EICR_LSC
)
1742 ixgbe_check_lsc(adapter
);
1744 if (eicr
& IXGBE_EICR_MAILBOX
)
1745 ixgbe_msg_task(adapter
);
1747 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
1748 ixgbe_check_fan_failure(adapter
, eicr
);
1750 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
1751 ixgbe_check_sfp_event(adapter
, eicr
);
1752 adapter
->interrupt_event
= eicr
;
1753 if ((adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) &&
1754 ((eicr
& IXGBE_EICR_GPI_SDP0
) || (eicr
& IXGBE_EICR_LSC
)))
1755 schedule_work(&adapter
->check_overtemp_task
);
1757 /* Handle Flow Director Full threshold interrupt */
1758 if (eicr
& IXGBE_EICR_FLOW_DIR
) {
1760 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_FLOW_DIR
);
1761 /* Disable transmits before FDIR Re-initialization */
1762 netif_tx_stop_all_queues(netdev
);
1763 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
1764 struct ixgbe_ring
*tx_ring
=
1765 adapter
->tx_ring
[i
];
1766 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE
,
1767 &tx_ring
->reinit_state
))
1768 schedule_work(&adapter
->fdir_reinit_task
);
1772 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1773 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMS_OTHER
);
1778 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter
*adapter
,
1783 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1784 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1785 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
1787 mask
= (qmask
& 0xFFFFFFFF);
1788 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS_EX(0), mask
);
1789 mask
= (qmask
>> 32);
1790 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS_EX(1), mask
);
1792 /* skip the flush */
1795 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter
*adapter
,
1800 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1801 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1802 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, mask
);
1804 mask
= (qmask
& 0xFFFFFFFF);
1805 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), mask
);
1806 mask
= (qmask
>> 32);
1807 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1), mask
);
1809 /* skip the flush */
1812 static irqreturn_t
ixgbe_msix_clean_tx(int irq
, void *data
)
1814 struct ixgbe_q_vector
*q_vector
= data
;
1815 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1816 struct ixgbe_ring
*tx_ring
;
1819 if (!q_vector
->txr_count
)
1822 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1823 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1824 tx_ring
= adapter
->tx_ring
[r_idx
];
1825 tx_ring
->total_bytes
= 0;
1826 tx_ring
->total_packets
= 0;
1827 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1831 /* EIAM disabled interrupts (on this vector) for us */
1832 napi_schedule(&q_vector
->napi
);
1838 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1840 * @data: pointer to our q_vector struct for this interrupt vector
1842 static irqreturn_t
ixgbe_msix_clean_rx(int irq
, void *data
)
1844 struct ixgbe_q_vector
*q_vector
= data
;
1845 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1846 struct ixgbe_ring
*rx_ring
;
1850 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1851 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1852 rx_ring
= adapter
->rx_ring
[r_idx
];
1853 rx_ring
->total_bytes
= 0;
1854 rx_ring
->total_packets
= 0;
1855 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1859 if (!q_vector
->rxr_count
)
1862 /* disable interrupts on this vector only */
1863 /* EIAM disabled interrupts (on this vector) for us */
1864 napi_schedule(&q_vector
->napi
);
1869 static irqreturn_t
ixgbe_msix_clean_many(int irq
, void *data
)
1871 struct ixgbe_q_vector
*q_vector
= data
;
1872 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1873 struct ixgbe_ring
*ring
;
1877 if (!q_vector
->txr_count
&& !q_vector
->rxr_count
)
1880 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1881 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1882 ring
= adapter
->tx_ring
[r_idx
];
1883 ring
->total_bytes
= 0;
1884 ring
->total_packets
= 0;
1885 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1889 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1890 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1891 ring
= adapter
->rx_ring
[r_idx
];
1892 ring
->total_bytes
= 0;
1893 ring
->total_packets
= 0;
1894 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1898 /* EIAM disabled interrupts (on this vector) for us */
1899 napi_schedule(&q_vector
->napi
);
1905 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1906 * @napi: napi struct with our devices info in it
1907 * @budget: amount of work driver is allowed to do this pass, in packets
1909 * This function is optimized for cleaning one queue only on a single
1912 static int ixgbe_clean_rxonly(struct napi_struct
*napi
, int budget
)
1914 struct ixgbe_q_vector
*q_vector
=
1915 container_of(napi
, struct ixgbe_q_vector
, napi
);
1916 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1917 struct ixgbe_ring
*rx_ring
= NULL
;
1921 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1922 rx_ring
= adapter
->rx_ring
[r_idx
];
1923 #ifdef CONFIG_IXGBE_DCA
1924 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1925 ixgbe_update_rx_dca(adapter
, rx_ring
);
1928 ixgbe_clean_rx_irq(q_vector
, rx_ring
, &work_done
, budget
);
1930 /* If all Rx work done, exit the polling mode */
1931 if (work_done
< budget
) {
1932 napi_complete(napi
);
1933 if (adapter
->rx_itr_setting
& 1)
1934 ixgbe_set_itr_msix(q_vector
);
1935 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1936 ixgbe_irq_enable_queues(adapter
,
1937 ((u64
)1 << q_vector
->v_idx
));
1944 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1945 * @napi: napi struct with our devices info in it
1946 * @budget: amount of work driver is allowed to do this pass, in packets
1948 * This function will clean more than one rx queue associated with a
1951 static int ixgbe_clean_rxtx_many(struct napi_struct
*napi
, int budget
)
1953 struct ixgbe_q_vector
*q_vector
=
1954 container_of(napi
, struct ixgbe_q_vector
, napi
);
1955 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1956 struct ixgbe_ring
*ring
= NULL
;
1957 int work_done
= 0, i
;
1959 bool tx_clean_complete
= true;
1961 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1962 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1963 ring
= adapter
->tx_ring
[r_idx
];
1964 #ifdef CONFIG_IXGBE_DCA
1965 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1966 ixgbe_update_tx_dca(adapter
, ring
);
1968 tx_clean_complete
&= ixgbe_clean_tx_irq(q_vector
, ring
);
1969 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1973 /* attempt to distribute budget to each queue fairly, but don't allow
1974 * the budget to go below 1 because we'll exit polling */
1975 budget
/= (q_vector
->rxr_count
?: 1);
1976 budget
= max(budget
, 1);
1977 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1978 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1979 ring
= adapter
->rx_ring
[r_idx
];
1980 #ifdef CONFIG_IXGBE_DCA
1981 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1982 ixgbe_update_rx_dca(adapter
, ring
);
1984 ixgbe_clean_rx_irq(q_vector
, ring
, &work_done
, budget
);
1985 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1989 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1990 ring
= adapter
->rx_ring
[r_idx
];
1991 /* If all Rx work done, exit the polling mode */
1992 if (work_done
< budget
) {
1993 napi_complete(napi
);
1994 if (adapter
->rx_itr_setting
& 1)
1995 ixgbe_set_itr_msix(q_vector
);
1996 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1997 ixgbe_irq_enable_queues(adapter
,
1998 ((u64
)1 << q_vector
->v_idx
));
2006 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2007 * @napi: napi struct with our devices info in it
2008 * @budget: amount of work driver is allowed to do this pass, in packets
2010 * This function is optimized for cleaning one queue only on a single
2013 static int ixgbe_clean_txonly(struct napi_struct
*napi
, int budget
)
2015 struct ixgbe_q_vector
*q_vector
=
2016 container_of(napi
, struct ixgbe_q_vector
, napi
);
2017 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2018 struct ixgbe_ring
*tx_ring
= NULL
;
2022 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
2023 tx_ring
= adapter
->tx_ring
[r_idx
];
2024 #ifdef CONFIG_IXGBE_DCA
2025 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
2026 ixgbe_update_tx_dca(adapter
, tx_ring
);
2029 if (!ixgbe_clean_tx_irq(q_vector
, tx_ring
))
2032 /* If all Tx work done, exit the polling mode */
2033 if (work_done
< budget
) {
2034 napi_complete(napi
);
2035 if (adapter
->tx_itr_setting
& 1)
2036 ixgbe_set_itr_msix(q_vector
);
2037 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2038 ixgbe_irq_enable_queues(adapter
,
2039 ((u64
)1 << q_vector
->v_idx
));
2045 static inline void map_vector_to_rxq(struct ixgbe_adapter
*a
, int v_idx
,
2048 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
2050 set_bit(r_idx
, q_vector
->rxr_idx
);
2051 q_vector
->rxr_count
++;
2054 static inline void map_vector_to_txq(struct ixgbe_adapter
*a
, int v_idx
,
2057 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
2059 set_bit(t_idx
, q_vector
->txr_idx
);
2060 q_vector
->txr_count
++;
2064 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2065 * @adapter: board private structure to initialize
2066 * @vectors: allotted vector count for descriptor rings
2068 * This function maps descriptor rings to the queue-specific vectors
2069 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2070 * one vector per ring/queue, but on a constrained vector budget, we
2071 * group the rings as "efficiently" as possible. You would add new
2072 * mapping configurations in here.
2074 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter
*adapter
,
2078 int rxr_idx
= 0, txr_idx
= 0;
2079 int rxr_remaining
= adapter
->num_rx_queues
;
2080 int txr_remaining
= adapter
->num_tx_queues
;
2085 /* No mapping required if MSI-X is disabled. */
2086 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
2090 * The ideal configuration...
2091 * We have enough vectors to map one per queue.
2093 if (vectors
== adapter
->num_rx_queues
+ adapter
->num_tx_queues
) {
2094 for (; rxr_idx
< rxr_remaining
; v_start
++, rxr_idx
++)
2095 map_vector_to_rxq(adapter
, v_start
, rxr_idx
);
2097 for (; txr_idx
< txr_remaining
; v_start
++, txr_idx
++)
2098 map_vector_to_txq(adapter
, v_start
, txr_idx
);
2104 * If we don't have enough vectors for a 1-to-1
2105 * mapping, we'll have to group them so there are
2106 * multiple queues per vector.
2108 /* Re-adjusting *qpv takes care of the remainder. */
2109 for (i
= v_start
; i
< vectors
; i
++) {
2110 rqpv
= DIV_ROUND_UP(rxr_remaining
, vectors
- i
);
2111 for (j
= 0; j
< rqpv
; j
++) {
2112 map_vector_to_rxq(adapter
, i
, rxr_idx
);
2117 for (i
= v_start
; i
< vectors
; i
++) {
2118 tqpv
= DIV_ROUND_UP(txr_remaining
, vectors
- i
);
2119 for (j
= 0; j
< tqpv
; j
++) {
2120 map_vector_to_txq(adapter
, i
, txr_idx
);
2131 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2132 * @adapter: board private structure
2134 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2135 * interrupts from the kernel.
2137 static int ixgbe_request_msix_irqs(struct ixgbe_adapter
*adapter
)
2139 struct net_device
*netdev
= adapter
->netdev
;
2140 irqreturn_t (*handler
)(int, void *);
2141 int i
, vector
, q_vectors
, err
;
2144 /* Decrement for Other and TCP Timer vectors */
2145 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2147 /* Map the Tx/Rx rings to the vectors we were allotted. */
2148 err
= ixgbe_map_rings_to_vectors(adapter
, q_vectors
);
2152 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2153 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2154 &ixgbe_msix_clean_many)
2155 for (vector
= 0; vector
< q_vectors
; vector
++) {
2156 handler
= SET_HANDLER(adapter
->q_vector
[vector
]);
2158 if (handler
== &ixgbe_msix_clean_rx
) {
2159 sprintf(adapter
->name
[vector
], "%s-%s-%d",
2160 netdev
->name
, "rx", ri
++);
2161 } else if (handler
== &ixgbe_msix_clean_tx
) {
2162 sprintf(adapter
->name
[vector
], "%s-%s-%d",
2163 netdev
->name
, "tx", ti
++);
2165 sprintf(adapter
->name
[vector
], "%s-%s-%d",
2166 netdev
->name
, "TxRx", vector
);
2168 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
2169 handler
, 0, adapter
->name
[vector
],
2170 adapter
->q_vector
[vector
]);
2172 e_err(probe
, "request_irq failed for MSIX interrupt "
2173 "Error: %d\n", err
);
2174 goto free_queue_irqs
;
2178 sprintf(adapter
->name
[vector
], "%s:lsc", netdev
->name
);
2179 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
2180 ixgbe_msix_lsc
, 0, adapter
->name
[vector
], netdev
);
2182 e_err(probe
, "request_irq for msix_lsc failed: %d\n", err
);
2183 goto free_queue_irqs
;
2189 for (i
= vector
- 1; i
>= 0; i
--)
2190 free_irq(adapter
->msix_entries
[--vector
].vector
,
2191 adapter
->q_vector
[i
]);
2192 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
2193 pci_disable_msix(adapter
->pdev
);
2194 kfree(adapter
->msix_entries
);
2195 adapter
->msix_entries
= NULL
;
2200 static void ixgbe_set_itr(struct ixgbe_adapter
*adapter
)
2202 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
2204 u32 new_itr
= q_vector
->eitr
;
2205 struct ixgbe_ring
*rx_ring
= adapter
->rx_ring
[0];
2206 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[0];
2208 q_vector
->tx_itr
= ixgbe_update_itr(adapter
, new_itr
,
2210 tx_ring
->total_packets
,
2211 tx_ring
->total_bytes
);
2212 q_vector
->rx_itr
= ixgbe_update_itr(adapter
, new_itr
,
2214 rx_ring
->total_packets
,
2215 rx_ring
->total_bytes
);
2217 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
2219 switch (current_itr
) {
2220 /* counts and packets in update_itr are dependent on these numbers */
2221 case lowest_latency
:
2225 new_itr
= 20000; /* aka hwitr = ~200 */
2234 if (new_itr
!= q_vector
->eitr
) {
2235 /* do an exponential smoothing */
2236 new_itr
= ((q_vector
->eitr
* 90)/100) + ((new_itr
* 10)/100);
2238 /* save the algorithm value here, not the smoothed one */
2239 q_vector
->eitr
= new_itr
;
2241 ixgbe_write_eitr(q_vector
);
2246 * ixgbe_irq_enable - Enable default interrupt generation settings
2247 * @adapter: board private structure
2249 static inline void ixgbe_irq_enable(struct ixgbe_adapter
*adapter
, bool queues
,
2254 mask
= (IXGBE_EIMS_ENABLE_MASK
& ~IXGBE_EIMS_RTX_QUEUE
);
2255 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
)
2256 mask
|= IXGBE_EIMS_GPI_SDP0
;
2257 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
)
2258 mask
|= IXGBE_EIMS_GPI_SDP1
;
2259 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
2260 mask
|= IXGBE_EIMS_ECC
;
2261 mask
|= IXGBE_EIMS_GPI_SDP1
;
2262 mask
|= IXGBE_EIMS_GPI_SDP2
;
2263 if (adapter
->num_vfs
)
2264 mask
|= IXGBE_EIMS_MAILBOX
;
2266 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
2267 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
2268 mask
|= IXGBE_EIMS_FLOW_DIR
;
2270 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
2272 ixgbe_irq_enable_queues(adapter
, ~0);
2274 IXGBE_WRITE_FLUSH(&adapter
->hw
);
2276 if (adapter
->num_vfs
> 32) {
2277 u32 eitrsel
= (1 << (adapter
->num_vfs
- 32)) - 1;
2278 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, eitrsel
);
2283 * ixgbe_intr - legacy mode Interrupt Handler
2284 * @irq: interrupt number
2285 * @data: pointer to a network interface device structure
2287 static irqreturn_t
ixgbe_intr(int irq
, void *data
)
2289 struct net_device
*netdev
= data
;
2290 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2291 struct ixgbe_hw
*hw
= &adapter
->hw
;
2292 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
2296 * Workaround for silicon errata on 82598. Mask the interrupts
2297 * before the read of EICR.
2299 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_IRQ_CLEAR_MASK
);
2301 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2302 * therefore no explict interrupt disable is necessary */
2303 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICR
);
2306 * shared interrupt alert!
2307 * make sure interrupts are enabled because the read will
2308 * have disabled interrupts due to EIAM
2309 * finish the workaround of silicon errata on 82598. Unmask
2310 * the interrupt that we masked before the EICR read.
2312 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2313 ixgbe_irq_enable(adapter
, true, true);
2314 return IRQ_NONE
; /* Not our interrupt */
2317 if (eicr
& IXGBE_EICR_LSC
)
2318 ixgbe_check_lsc(adapter
);
2320 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
2321 ixgbe_check_sfp_event(adapter
, eicr
);
2323 ixgbe_check_fan_failure(adapter
, eicr
);
2324 if ((adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) &&
2325 ((eicr
& IXGBE_EICR_GPI_SDP0
) || (eicr
& IXGBE_EICR_LSC
)))
2326 schedule_work(&adapter
->check_overtemp_task
);
2328 if (napi_schedule_prep(&(q_vector
->napi
))) {
2329 adapter
->tx_ring
[0]->total_packets
= 0;
2330 adapter
->tx_ring
[0]->total_bytes
= 0;
2331 adapter
->rx_ring
[0]->total_packets
= 0;
2332 adapter
->rx_ring
[0]->total_bytes
= 0;
2333 /* would disable interrupts here but EIAM disabled it */
2334 __napi_schedule(&(q_vector
->napi
));
2338 * re-enable link(maybe) and non-queue interrupts, no flush.
2339 * ixgbe_poll will re-enable the queue interrupts
2342 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2343 ixgbe_irq_enable(adapter
, false, false);
2348 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter
*adapter
)
2350 int i
, q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2352 for (i
= 0; i
< q_vectors
; i
++) {
2353 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
2354 bitmap_zero(q_vector
->rxr_idx
, MAX_RX_QUEUES
);
2355 bitmap_zero(q_vector
->txr_idx
, MAX_TX_QUEUES
);
2356 q_vector
->rxr_count
= 0;
2357 q_vector
->txr_count
= 0;
2362 * ixgbe_request_irq - initialize interrupts
2363 * @adapter: board private structure
2365 * Attempts to configure interrupts using the best available
2366 * capabilities of the hardware and kernel.
2368 static int ixgbe_request_irq(struct ixgbe_adapter
*adapter
)
2370 struct net_device
*netdev
= adapter
->netdev
;
2373 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2374 err
= ixgbe_request_msix_irqs(adapter
);
2375 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
2376 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, 0,
2377 netdev
->name
, netdev
);
2379 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, IRQF_SHARED
,
2380 netdev
->name
, netdev
);
2384 e_err(probe
, "request_irq failed, Error %d\n", err
);
2389 static void ixgbe_free_irq(struct ixgbe_adapter
*adapter
)
2391 struct net_device
*netdev
= adapter
->netdev
;
2393 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2396 q_vectors
= adapter
->num_msix_vectors
;
2399 free_irq(adapter
->msix_entries
[i
].vector
, netdev
);
2402 for (; i
>= 0; i
--) {
2403 free_irq(adapter
->msix_entries
[i
].vector
,
2404 adapter
->q_vector
[i
]);
2407 ixgbe_reset_q_vectors(adapter
);
2409 free_irq(adapter
->pdev
->irq
, netdev
);
2414 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2415 * @adapter: board private structure
2417 static inline void ixgbe_irq_disable(struct ixgbe_adapter
*adapter
)
2419 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
2420 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, ~0);
2422 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, 0xFFFF0000);
2423 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), ~0);
2424 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1), ~0);
2425 if (adapter
->num_vfs
> 32)
2426 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, 0);
2428 IXGBE_WRITE_FLUSH(&adapter
->hw
);
2429 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2431 for (i
= 0; i
< adapter
->num_msix_vectors
; i
++)
2432 synchronize_irq(adapter
->msix_entries
[i
].vector
);
2434 synchronize_irq(adapter
->pdev
->irq
);
2439 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2442 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter
*adapter
)
2444 struct ixgbe_hw
*hw
= &adapter
->hw
;
2446 IXGBE_WRITE_REG(hw
, IXGBE_EITR(0),
2447 EITR_INTS_PER_SEC_TO_REG(adapter
->rx_eitr_param
));
2449 ixgbe_set_ivar(adapter
, 0, 0, 0);
2450 ixgbe_set_ivar(adapter
, 1, 0, 0);
2452 map_vector_to_rxq(adapter
, 0, 0);
2453 map_vector_to_txq(adapter
, 0, 0);
2455 e_info(hw
, "Legacy interrupt IVAR setup done\n");
2459 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2460 * @adapter: board private structure
2461 * @ring: structure containing ring specific data
2463 * Configure the Tx descriptor ring after a reset.
2465 void ixgbe_configure_tx_ring(struct ixgbe_adapter
*adapter
,
2466 struct ixgbe_ring
*ring
)
2468 struct ixgbe_hw
*hw
= &adapter
->hw
;
2469 u64 tdba
= ring
->dma
;
2472 u16 reg_idx
= ring
->reg_idx
;
2474 /* disable queue to avoid issues while updating state */
2475 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(reg_idx
));
2476 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(reg_idx
),
2477 txdctl
& ~IXGBE_TXDCTL_ENABLE
);
2478 IXGBE_WRITE_FLUSH(hw
);
2480 IXGBE_WRITE_REG(hw
, IXGBE_TDBAL(reg_idx
),
2481 (tdba
& DMA_BIT_MASK(32)));
2482 IXGBE_WRITE_REG(hw
, IXGBE_TDBAH(reg_idx
), (tdba
>> 32));
2483 IXGBE_WRITE_REG(hw
, IXGBE_TDLEN(reg_idx
),
2484 ring
->count
* sizeof(union ixgbe_adv_tx_desc
));
2485 IXGBE_WRITE_REG(hw
, IXGBE_TDH(reg_idx
), 0);
2486 IXGBE_WRITE_REG(hw
, IXGBE_TDT(reg_idx
), 0);
2487 ring
->head
= IXGBE_TDH(reg_idx
);
2488 ring
->tail
= IXGBE_TDT(reg_idx
);
2490 /* configure fetching thresholds */
2491 if (adapter
->rx_itr_setting
== 0) {
2492 /* cannot set wthresh when itr==0 */
2493 txdctl
&= ~0x007F0000;
2495 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2496 txdctl
|= (8 << 16);
2498 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
2499 /* PThresh workaround for Tx hang with DFP enabled. */
2503 /* reinitialize flowdirector state */
2504 set_bit(__IXGBE_FDIR_INIT_DONE
, &ring
->reinit_state
);
2507 txdctl
|= IXGBE_TXDCTL_ENABLE
;
2508 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(reg_idx
), txdctl
);
2510 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2511 if (hw
->mac
.type
== ixgbe_mac_82598EB
&&
2512 !(IXGBE_READ_REG(hw
, IXGBE_LINKS
) & IXGBE_LINKS_UP
))
2515 /* poll to verify queue is enabled */
2518 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(reg_idx
));
2519 } while (--wait_loop
&& !(txdctl
& IXGBE_TXDCTL_ENABLE
));
2521 e_err(drv
, "Could not enable Tx Queue %d\n", reg_idx
);
2524 static void ixgbe_setup_mtqc(struct ixgbe_adapter
*adapter
)
2526 struct ixgbe_hw
*hw
= &adapter
->hw
;
2530 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2533 /* disable the arbiter while setting MTQC */
2534 rttdcs
= IXGBE_READ_REG(hw
, IXGBE_RTTDCS
);
2535 rttdcs
|= IXGBE_RTTDCS_ARBDIS
;
2536 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2538 /* set transmit pool layout */
2539 mask
= (IXGBE_FLAG_SRIOV_ENABLED
| IXGBE_FLAG_DCB_ENABLED
);
2540 switch (adapter
->flags
& mask
) {
2542 case (IXGBE_FLAG_SRIOV_ENABLED
):
2543 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
,
2544 (IXGBE_MTQC_VT_ENA
| IXGBE_MTQC_64VF
));
2547 case (IXGBE_FLAG_DCB_ENABLED
):
2548 /* We enable 8 traffic classes, DCB only */
2549 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
,
2550 (IXGBE_MTQC_RT_ENA
| IXGBE_MTQC_8TC_8TQ
));
2554 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
, IXGBE_MTQC_64Q_1PB
);
2558 /* re-enable the arbiter */
2559 rttdcs
&= ~IXGBE_RTTDCS_ARBDIS
;
2560 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2564 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2565 * @adapter: board private structure
2567 * Configure the Tx unit of the MAC after a reset.
2569 static void ixgbe_configure_tx(struct ixgbe_adapter
*adapter
)
2571 struct ixgbe_hw
*hw
= &adapter
->hw
;
2575 ixgbe_setup_mtqc(adapter
);
2577 if (hw
->mac
.type
!= ixgbe_mac_82598EB
) {
2578 /* DMATXCTL.EN must be before Tx queues are enabled */
2579 dmatxctl
= IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
);
2580 dmatxctl
|= IXGBE_DMATXCTL_TE
;
2581 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
, dmatxctl
);
2584 /* Setup the HW Tx Head and Tail descriptor pointers */
2585 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
2586 ixgbe_configure_tx_ring(adapter
, adapter
->tx_ring
[i
]);
2589 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2591 static void ixgbe_configure_srrctl(struct ixgbe_adapter
*adapter
,
2592 struct ixgbe_ring
*rx_ring
)
2596 struct ixgbe_ring_feature
*feature
= adapter
->ring_feature
;
2598 index
= rx_ring
->reg_idx
;
2599 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
2601 mask
= (unsigned long) feature
[RING_F_RSS
].mask
;
2602 index
= index
& mask
;
2604 srrctl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_SRRCTL(index
));
2606 srrctl
&= ~IXGBE_SRRCTL_BSIZEHDR_MASK
;
2607 srrctl
&= ~IXGBE_SRRCTL_BSIZEPKT_MASK
;
2608 if (adapter
->num_vfs
)
2609 srrctl
|= IXGBE_SRRCTL_DROP_EN
;
2611 srrctl
|= (IXGBE_RX_HDR_SIZE
<< IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT
) &
2612 IXGBE_SRRCTL_BSIZEHDR_MASK
;
2614 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
2615 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2616 srrctl
|= IXGBE_MAX_RXBUFFER
>> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2618 srrctl
|= (PAGE_SIZE
/ 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2620 srrctl
|= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS
;
2622 srrctl
|= ALIGN(rx_ring
->rx_buf_len
, 1024) >>
2623 IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2624 srrctl
|= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF
;
2627 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_SRRCTL(index
), srrctl
);
2630 static void ixgbe_setup_mrqc(struct ixgbe_adapter
*adapter
)
2632 struct ixgbe_hw
*hw
= &adapter
->hw
;
2633 static const u32 seed
[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2634 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2635 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2636 u32 mrqc
= 0, reta
= 0;
2641 /* Fill out hash function seeds */
2642 for (i
= 0; i
< 10; i
++)
2643 IXGBE_WRITE_REG(hw
, IXGBE_RSSRK(i
), seed
[i
]);
2645 /* Fill out redirection table */
2646 for (i
= 0, j
= 0; i
< 128; i
++, j
++) {
2647 if (j
== adapter
->ring_feature
[RING_F_RSS
].indices
)
2649 /* reta = 4-byte sliding window of
2650 * 0x00..(indices-1)(indices-1)00..etc. */
2651 reta
= (reta
<< 8) | (j
* 0x11);
2653 IXGBE_WRITE_REG(hw
, IXGBE_RETA(i
>> 2), reta
);
2656 /* Disable indicating checksum in descriptor, enables RSS hash */
2657 rxcsum
= IXGBE_READ_REG(hw
, IXGBE_RXCSUM
);
2658 rxcsum
|= IXGBE_RXCSUM_PCSD
;
2659 IXGBE_WRITE_REG(hw
, IXGBE_RXCSUM
, rxcsum
);
2661 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
2662 mask
= adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
;
2664 mask
= adapter
->flags
& (IXGBE_FLAG_RSS_ENABLED
2665 #ifdef CONFIG_IXGBE_DCB
2666 | IXGBE_FLAG_DCB_ENABLED
2668 | IXGBE_FLAG_SRIOV_ENABLED
2672 case (IXGBE_FLAG_RSS_ENABLED
):
2673 mrqc
= IXGBE_MRQC_RSSEN
;
2675 case (IXGBE_FLAG_SRIOV_ENABLED
):
2676 mrqc
= IXGBE_MRQC_VMDQEN
;
2678 #ifdef CONFIG_IXGBE_DCB
2679 case (IXGBE_FLAG_DCB_ENABLED
):
2680 mrqc
= IXGBE_MRQC_RT8TCEN
;
2682 #endif /* CONFIG_IXGBE_DCB */
2687 /* Perform hash on these packet types */
2688 mrqc
|= IXGBE_MRQC_RSS_FIELD_IPV4
2689 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2690 | IXGBE_MRQC_RSS_FIELD_IPV6
2691 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
;
2693 IXGBE_WRITE_REG(hw
, IXGBE_MRQC
, mrqc
);
2697 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2698 * @adapter: address of board private structure
2699 * @index: index of ring to set
2701 static void ixgbe_configure_rscctl(struct ixgbe_adapter
*adapter
,
2702 struct ixgbe_ring
*ring
)
2704 struct ixgbe_hw
*hw
= &adapter
->hw
;
2707 u16 reg_idx
= ring
->reg_idx
;
2709 if (!(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
))
2712 rx_buf_len
= ring
->rx_buf_len
;
2713 rscctrl
= IXGBE_READ_REG(hw
, IXGBE_RSCCTL(reg_idx
));
2714 rscctrl
|= IXGBE_RSCCTL_RSCEN
;
2716 * we must limit the number of descriptors so that the
2717 * total size of max desc * buf_len is not greater
2720 if (ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
2721 #if (MAX_SKB_FRAGS > 16)
2722 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2723 #elif (MAX_SKB_FRAGS > 8)
2724 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2725 #elif (MAX_SKB_FRAGS > 4)
2726 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2728 rscctrl
|= IXGBE_RSCCTL_MAXDESC_1
;
2731 if (rx_buf_len
< IXGBE_RXBUFFER_4096
)
2732 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2733 else if (rx_buf_len
< IXGBE_RXBUFFER_8192
)
2734 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2736 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2738 IXGBE_WRITE_REG(hw
, IXGBE_RSCCTL(reg_idx
), rscctrl
);
2742 * ixgbe_set_uta - Set unicast filter table address
2743 * @adapter: board private structure
2745 * The unicast table address is a register array of 32-bit registers.
2746 * The table is meant to be used in a way similar to how the MTA is used
2747 * however due to certain limitations in the hardware it is necessary to
2748 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2749 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2751 static void ixgbe_set_uta(struct ixgbe_adapter
*adapter
)
2753 struct ixgbe_hw
*hw
= &adapter
->hw
;
2756 /* The UTA table only exists on 82599 hardware and newer */
2757 if (hw
->mac
.type
< ixgbe_mac_82599EB
)
2760 /* we only need to do this if VMDq is enabled */
2761 if (!(adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
))
2764 for (i
= 0; i
< 128; i
++)
2765 IXGBE_WRITE_REG(hw
, IXGBE_UTA(i
), ~0);
2768 #define IXGBE_MAX_RX_DESC_POLL 10
2769 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter
*adapter
,
2770 struct ixgbe_ring
*ring
)
2772 struct ixgbe_hw
*hw
= &adapter
->hw
;
2773 int reg_idx
= ring
->reg_idx
;
2774 int wait_loop
= IXGBE_MAX_RX_DESC_POLL
;
2777 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2778 if (hw
->mac
.type
== ixgbe_mac_82598EB
&&
2779 !(IXGBE_READ_REG(hw
, IXGBE_LINKS
) & IXGBE_LINKS_UP
))
2784 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
2785 } while (--wait_loop
&& !(rxdctl
& IXGBE_RXDCTL_ENABLE
));
2788 e_err(drv
, "RXDCTL.ENABLE on Rx queue %d not set within "
2789 "the polling period\n", reg_idx
);
2793 void ixgbe_configure_rx_ring(struct ixgbe_adapter
*adapter
,
2794 struct ixgbe_ring
*ring
)
2796 struct ixgbe_hw
*hw
= &adapter
->hw
;
2797 u64 rdba
= ring
->dma
;
2799 u16 reg_idx
= ring
->reg_idx
;
2801 /* disable queue to avoid issues while updating state */
2802 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
2803 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(reg_idx
),
2804 rxdctl
& ~IXGBE_RXDCTL_ENABLE
);
2805 IXGBE_WRITE_FLUSH(hw
);
2807 IXGBE_WRITE_REG(hw
, IXGBE_RDBAL(reg_idx
), (rdba
& DMA_BIT_MASK(32)));
2808 IXGBE_WRITE_REG(hw
, IXGBE_RDBAH(reg_idx
), (rdba
>> 32));
2809 IXGBE_WRITE_REG(hw
, IXGBE_RDLEN(reg_idx
),
2810 ring
->count
* sizeof(union ixgbe_adv_rx_desc
));
2811 IXGBE_WRITE_REG(hw
, IXGBE_RDH(reg_idx
), 0);
2812 IXGBE_WRITE_REG(hw
, IXGBE_RDT(reg_idx
), 0);
2813 ring
->head
= IXGBE_RDH(reg_idx
);
2814 ring
->tail
= IXGBE_RDT(reg_idx
);
2816 ixgbe_configure_srrctl(adapter
, ring
);
2817 ixgbe_configure_rscctl(adapter
, ring
);
2819 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
2821 * enable cache line friendly hardware writes:
2822 * PTHRESH=32 descriptors (half the internal cache),
2823 * this also removes ugly rx_no_buffer_count increment
2824 * HTHRESH=4 descriptors (to minimize latency on fetch)
2825 * WTHRESH=8 burst writeback up to two cache lines
2827 rxdctl
&= ~0x3FFFFF;
2831 /* enable receive descriptor ring */
2832 rxdctl
|= IXGBE_RXDCTL_ENABLE
;
2833 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(reg_idx
), rxdctl
);
2835 ixgbe_rx_desc_queue_enable(adapter
, ring
);
2836 ixgbe_alloc_rx_buffers(adapter
, ring
, IXGBE_DESC_UNUSED(ring
));
2839 static void ixgbe_setup_psrtype(struct ixgbe_adapter
*adapter
)
2841 struct ixgbe_hw
*hw
= &adapter
->hw
;
2844 /* PSRTYPE must be initialized in non 82598 adapters */
2845 u32 psrtype
= IXGBE_PSRTYPE_TCPHDR
|
2846 IXGBE_PSRTYPE_UDPHDR
|
2847 IXGBE_PSRTYPE_IPV4HDR
|
2848 IXGBE_PSRTYPE_L2HDR
|
2849 IXGBE_PSRTYPE_IPV6HDR
;
2851 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2854 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
)
2855 psrtype
|= (adapter
->num_rx_queues_per_pool
<< 29);
2857 for (p
= 0; p
< adapter
->num_rx_pools
; p
++)
2858 IXGBE_WRITE_REG(hw
, IXGBE_PSRTYPE(adapter
->num_vfs
+ p
),
2862 static void ixgbe_configure_virtualization(struct ixgbe_adapter
*adapter
)
2864 struct ixgbe_hw
*hw
= &adapter
->hw
;
2867 u32 reg_offset
, vf_shift
;
2870 if (!(adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
))
2873 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
2874 vt_reg_bits
= IXGBE_VMD_CTL_VMDQ_EN
| IXGBE_VT_CTL_REPLEN
;
2875 vt_reg_bits
|= (adapter
->num_vfs
<< IXGBE_VT_CTL_POOL_SHIFT
);
2876 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
| vt_reg_bits
);
2878 vf_shift
= adapter
->num_vfs
% 32;
2879 reg_offset
= (adapter
->num_vfs
> 32) ? 1 : 0;
2881 /* Enable only the PF's pool for Tx/Rx */
2882 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(reg_offset
), (1 << vf_shift
));
2883 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(reg_offset
^ 1), 0);
2884 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(reg_offset
), (1 << vf_shift
));
2885 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(reg_offset
^ 1), 0);
2886 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, IXGBE_PFDTXGSWC_VT_LBEN
);
2888 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2889 hw
->mac
.ops
.set_vmdq(hw
, 0, adapter
->num_vfs
);
2892 * Set up VF register offsets for selected VT Mode,
2893 * i.e. 32 or 64 VFs for SR-IOV
2895 gcr_ext
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
2896 gcr_ext
|= IXGBE_GCR_EXT_MSIX_EN
;
2897 gcr_ext
|= IXGBE_GCR_EXT_VT_MODE_64
;
2898 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, gcr_ext
);
2900 /* enable Tx loopback for VF/PF communication */
2901 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, IXGBE_PFDTXGSWC_VT_LBEN
);
2904 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter
*adapter
)
2906 struct ixgbe_hw
*hw
= &adapter
->hw
;
2907 struct net_device
*netdev
= adapter
->netdev
;
2908 int max_frame
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
2910 struct ixgbe_ring
*rx_ring
;
2914 /* Decide whether to use packet split mode or not */
2915 /* Do not use packet split if we're in SR-IOV Mode */
2916 if (!adapter
->num_vfs
)
2917 adapter
->flags
|= IXGBE_FLAG_RX_PS_ENABLED
;
2919 /* Set the RX buffer length according to the mode */
2920 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
) {
2921 rx_buf_len
= IXGBE_RX_HDR_SIZE
;
2923 if (!(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) &&
2924 (netdev
->mtu
<= ETH_DATA_LEN
))
2925 rx_buf_len
= MAXIMUM_ETHERNET_VLAN_SIZE
;
2927 rx_buf_len
= ALIGN(max_frame
+ VLAN_HLEN
, 1024);
2931 /* adjust max frame to be able to do baby jumbo for FCoE */
2932 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) &&
2933 (max_frame
< IXGBE_FCOE_JUMBO_FRAME_SIZE
))
2934 max_frame
= IXGBE_FCOE_JUMBO_FRAME_SIZE
;
2936 #endif /* IXGBE_FCOE */
2937 mhadd
= IXGBE_READ_REG(hw
, IXGBE_MHADD
);
2938 if (max_frame
!= (mhadd
>> IXGBE_MHADD_MFS_SHIFT
)) {
2939 mhadd
&= ~IXGBE_MHADD_MFS_MASK
;
2940 mhadd
|= max_frame
<< IXGBE_MHADD_MFS_SHIFT
;
2942 IXGBE_WRITE_REG(hw
, IXGBE_MHADD
, mhadd
);
2945 hlreg0
= IXGBE_READ_REG(hw
, IXGBE_HLREG0
);
2946 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2947 hlreg0
|= IXGBE_HLREG0_JUMBOEN
;
2948 IXGBE_WRITE_REG(hw
, IXGBE_HLREG0
, hlreg0
);
2951 * Setup the HW Rx Head and Tail Descriptor Pointers and
2952 * the Base and Length of the Rx Descriptor Ring
2954 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2955 rx_ring
= adapter
->rx_ring
[i
];
2956 rx_ring
->rx_buf_len
= rx_buf_len
;
2958 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
)
2959 rx_ring
->flags
|= IXGBE_RING_RX_PS_ENABLED
;
2961 rx_ring
->flags
&= ~IXGBE_RING_RX_PS_ENABLED
;
2964 if (netdev
->features
& NETIF_F_FCOE_MTU
) {
2965 struct ixgbe_ring_feature
*f
;
2966 f
= &adapter
->ring_feature
[RING_F_FCOE
];
2967 if ((i
>= f
->mask
) && (i
< f
->mask
+ f
->indices
)) {
2968 rx_ring
->flags
&= ~IXGBE_RING_RX_PS_ENABLED
;
2969 if (rx_buf_len
< IXGBE_FCOE_JUMBO_FRAME_SIZE
)
2970 rx_ring
->rx_buf_len
=
2971 IXGBE_FCOE_JUMBO_FRAME_SIZE
;
2974 #endif /* IXGBE_FCOE */
2979 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter
*adapter
)
2981 struct ixgbe_hw
*hw
= &adapter
->hw
;
2982 u32 rdrxctl
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
2984 switch (hw
->mac
.type
) {
2985 case ixgbe_mac_82598EB
:
2987 * For VMDq support of different descriptor types or
2988 * buffer sizes through the use of multiple SRRCTL
2989 * registers, RDRXCTL.MVMEN must be set to 1
2991 * also, the manual doesn't mention it clearly but DCA hints
2992 * will only use queue 0's tags unless this bit is set. Side
2993 * effects of setting this bit are only that SRRCTL must be
2994 * fully programmed [0..15]
2996 rdrxctl
|= IXGBE_RDRXCTL_MVMEN
;
2998 case ixgbe_mac_82599EB
:
2999 /* Disable RSC for ACK packets */
3000 IXGBE_WRITE_REG(hw
, IXGBE_RSCDBU
,
3001 (IXGBE_RSCDBU_RSCACKDIS
| IXGBE_READ_REG(hw
, IXGBE_RSCDBU
)));
3002 rdrxctl
&= ~IXGBE_RDRXCTL_RSCFRSTSIZE
;
3003 /* hardware requires some bits to be set by default */
3004 rdrxctl
|= (IXGBE_RDRXCTL_RSCACKC
| IXGBE_RDRXCTL_FCOE_WRFIX
);
3005 rdrxctl
|= IXGBE_RDRXCTL_CRCSTRIP
;
3008 /* We should do nothing since we don't know this hardware */
3012 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, rdrxctl
);
3016 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3017 * @adapter: board private structure
3019 * Configure the Rx unit of the MAC after a reset.
3021 static void ixgbe_configure_rx(struct ixgbe_adapter
*adapter
)
3023 struct ixgbe_hw
*hw
= &adapter
->hw
;
3027 /* disable receives while setting up the descriptors */
3028 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
3029 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
3031 ixgbe_setup_psrtype(adapter
);
3032 ixgbe_setup_rdrxctl(adapter
);
3034 /* Program registers for the distribution of queues */
3035 ixgbe_setup_mrqc(adapter
);
3037 ixgbe_set_uta(adapter
);
3039 /* set_rx_buffer_len must be called before ring initialization */
3040 ixgbe_set_rx_buffer_len(adapter
);
3043 * Setup the HW Rx Head and Tail Descriptor Pointers and
3044 * the Base and Length of the Rx Descriptor Ring
3046 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3047 ixgbe_configure_rx_ring(adapter
, adapter
->rx_ring
[i
]);
3049 /* disable drop enable for 82598 parts */
3050 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3051 rxctrl
|= IXGBE_RXCTRL_DMBYPS
;
3053 /* enable all receives */
3054 rxctrl
|= IXGBE_RXCTRL_RXEN
;
3055 hw
->mac
.ops
.enable_rx_dma(hw
, rxctrl
);
3058 static void ixgbe_vlan_rx_add_vid(struct net_device
*netdev
, u16 vid
)
3060 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3061 struct ixgbe_hw
*hw
= &adapter
->hw
;
3062 int pool_ndx
= adapter
->num_vfs
;
3064 /* add VID to filter table */
3065 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, true);
3066 set_bit(vid
, adapter
->active_vlans
);
3069 static void ixgbe_vlan_rx_kill_vid(struct net_device
*netdev
, u16 vid
)
3071 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3072 struct ixgbe_hw
*hw
= &adapter
->hw
;
3073 int pool_ndx
= adapter
->num_vfs
;
3075 /* remove VID from filter table */
3076 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, false);
3077 clear_bit(vid
, adapter
->active_vlans
);
3081 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3082 * @adapter: driver data
3084 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter
*adapter
)
3086 struct ixgbe_hw
*hw
= &adapter
->hw
;
3089 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3090 vlnctrl
&= ~(IXGBE_VLNCTRL_VFE
| IXGBE_VLNCTRL_CFIEN
);
3091 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3095 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3096 * @adapter: driver data
3098 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter
*adapter
)
3100 struct ixgbe_hw
*hw
= &adapter
->hw
;
3103 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3104 vlnctrl
|= IXGBE_VLNCTRL_VFE
;
3105 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
3106 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3110 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3111 * @adapter: driver data
3113 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter
*adapter
)
3115 struct ixgbe_hw
*hw
= &adapter
->hw
;
3119 switch (hw
->mac
.type
) {
3120 case ixgbe_mac_82598EB
:
3121 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3122 vlnctrl
&= ~IXGBE_VLNCTRL_VME
;
3123 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3125 case ixgbe_mac_82599EB
:
3126 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3127 j
= adapter
->rx_ring
[i
]->reg_idx
;
3128 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
3129 vlnctrl
&= ~IXGBE_RXDCTL_VME
;
3130 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
3139 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3140 * @adapter: driver data
3142 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter
*adapter
)
3144 struct ixgbe_hw
*hw
= &adapter
->hw
;
3148 switch (hw
->mac
.type
) {
3149 case ixgbe_mac_82598EB
:
3150 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3151 vlnctrl
|= IXGBE_VLNCTRL_VME
;
3152 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3154 case ixgbe_mac_82599EB
:
3155 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3156 j
= adapter
->rx_ring
[i
]->reg_idx
;
3157 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
3158 vlnctrl
|= IXGBE_RXDCTL_VME
;
3159 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
3167 static void ixgbe_restore_vlan(struct ixgbe_adapter
*adapter
)
3171 ixgbe_vlan_rx_add_vid(adapter
->netdev
, 0);
3173 for_each_set_bit(vid
, adapter
->active_vlans
, VLAN_N_VID
)
3174 ixgbe_vlan_rx_add_vid(adapter
->netdev
, vid
);
3178 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3179 * @netdev: network interface device structure
3181 * Writes unicast address list to the RAR table.
3182 * Returns: -ENOMEM on failure/insufficient address space
3183 * 0 on no addresses written
3184 * X on writing X addresses to the RAR table
3186 static int ixgbe_write_uc_addr_list(struct net_device
*netdev
)
3188 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3189 struct ixgbe_hw
*hw
= &adapter
->hw
;
3190 unsigned int vfn
= adapter
->num_vfs
;
3191 unsigned int rar_entries
= hw
->mac
.num_rar_entries
- (vfn
+ 1);
3194 /* return ENOMEM indicating insufficient memory for addresses */
3195 if (netdev_uc_count(netdev
) > rar_entries
)
3198 if (!netdev_uc_empty(netdev
) && rar_entries
) {
3199 struct netdev_hw_addr
*ha
;
3200 /* return error if we do not support writing to RAR table */
3201 if (!hw
->mac
.ops
.set_rar
)
3204 netdev_for_each_uc_addr(ha
, netdev
) {
3207 hw
->mac
.ops
.set_rar(hw
, rar_entries
--, ha
->addr
,
3212 /* write the addresses in reverse order to avoid write combining */
3213 for (; rar_entries
> 0 ; rar_entries
--)
3214 hw
->mac
.ops
.clear_rar(hw
, rar_entries
);
3220 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3221 * @netdev: network interface device structure
3223 * The set_rx_method entry point is called whenever the unicast/multicast
3224 * address list or the network interface flags are updated. This routine is
3225 * responsible for configuring the hardware for proper unicast, multicast and
3228 void ixgbe_set_rx_mode(struct net_device
*netdev
)
3230 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3231 struct ixgbe_hw
*hw
= &adapter
->hw
;
3232 u32 fctrl
, vmolr
= IXGBE_VMOLR_BAM
| IXGBE_VMOLR_AUPE
;
3235 /* Check for Promiscuous and All Multicast modes */
3237 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
3239 /* set all bits that we expect to always be set */
3240 fctrl
|= IXGBE_FCTRL_BAM
;
3241 fctrl
|= IXGBE_FCTRL_DPF
; /* discard pause frames when FC enabled */
3242 fctrl
|= IXGBE_FCTRL_PMCF
;
3244 /* clear the bits we are changing the status of */
3245 fctrl
&= ~(IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
3247 if (netdev
->flags
& IFF_PROMISC
) {
3248 hw
->addr_ctrl
.user_set_promisc
= true;
3249 fctrl
|= (IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
3250 vmolr
|= (IXGBE_VMOLR_ROPE
| IXGBE_VMOLR_MPE
);
3251 /* don't hardware filter vlans in promisc mode */
3252 ixgbe_vlan_filter_disable(adapter
);
3254 if (netdev
->flags
& IFF_ALLMULTI
) {
3255 fctrl
|= IXGBE_FCTRL_MPE
;
3256 vmolr
|= IXGBE_VMOLR_MPE
;
3259 * Write addresses to the MTA, if the attempt fails
3260 * then we should just turn on promiscous mode so
3261 * that we can at least receive multicast traffic
3263 hw
->mac
.ops
.update_mc_addr_list(hw
, netdev
);
3264 vmolr
|= IXGBE_VMOLR_ROMPE
;
3266 ixgbe_vlan_filter_enable(adapter
);
3267 hw
->addr_ctrl
.user_set_promisc
= false;
3269 * Write addresses to available RAR registers, if there is not
3270 * sufficient space to store all the addresses then enable
3271 * unicast promiscous mode
3273 count
= ixgbe_write_uc_addr_list(netdev
);
3275 fctrl
|= IXGBE_FCTRL_UPE
;
3276 vmolr
|= IXGBE_VMOLR_ROPE
;
3280 if (adapter
->num_vfs
) {
3281 ixgbe_restore_vf_multicasts(adapter
);
3282 vmolr
|= IXGBE_READ_REG(hw
, IXGBE_VMOLR(adapter
->num_vfs
)) &
3283 ~(IXGBE_VMOLR_MPE
| IXGBE_VMOLR_ROMPE
|
3285 IXGBE_WRITE_REG(hw
, IXGBE_VMOLR(adapter
->num_vfs
), vmolr
);
3288 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
3290 if (netdev
->features
& NETIF_F_HW_VLAN_RX
)
3291 ixgbe_vlan_strip_enable(adapter
);
3293 ixgbe_vlan_strip_disable(adapter
);
3296 static void ixgbe_napi_enable_all(struct ixgbe_adapter
*adapter
)
3299 struct ixgbe_q_vector
*q_vector
;
3300 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3302 /* legacy and MSI only use one vector */
3303 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
3306 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
3307 struct napi_struct
*napi
;
3308 q_vector
= adapter
->q_vector
[q_idx
];
3309 napi
= &q_vector
->napi
;
3310 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3311 if (!q_vector
->rxr_count
|| !q_vector
->txr_count
) {
3312 if (q_vector
->txr_count
== 1)
3313 napi
->poll
= &ixgbe_clean_txonly
;
3314 else if (q_vector
->rxr_count
== 1)
3315 napi
->poll
= &ixgbe_clean_rxonly
;
3323 static void ixgbe_napi_disable_all(struct ixgbe_adapter
*adapter
)
3326 struct ixgbe_q_vector
*q_vector
;
3327 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3329 /* legacy and MSI only use one vector */
3330 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
3333 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
3334 q_vector
= adapter
->q_vector
[q_idx
];
3335 napi_disable(&q_vector
->napi
);
3339 #ifdef CONFIG_IXGBE_DCB
3341 * ixgbe_configure_dcb - Configure DCB hardware
3342 * @adapter: ixgbe adapter struct
3344 * This is called by the driver on open to configure the DCB hardware.
3345 * This is also called by the gennetlink interface when reconfiguring
3348 static void ixgbe_configure_dcb(struct ixgbe_adapter
*adapter
)
3350 struct ixgbe_hw
*hw
= &adapter
->hw
;
3351 int max_frame
= adapter
->netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
3355 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)) {
3356 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3357 netif_set_gso_max_size(adapter
->netdev
, 65536);
3361 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3362 netif_set_gso_max_size(adapter
->netdev
, 32768);
3365 if (adapter
->netdev
->features
& NETIF_F_FCOE_MTU
)
3366 max_frame
= max(max_frame
, IXGBE_FCOE_JUMBO_FRAME_SIZE
);
3369 ixgbe_dcb_calculate_tc_credits(&adapter
->dcb_cfg
, max_frame
,
3371 ixgbe_dcb_calculate_tc_credits(&adapter
->dcb_cfg
, max_frame
,
3374 /* reconfigure the hardware */
3375 ixgbe_dcb_hw_config(&adapter
->hw
, &adapter
->dcb_cfg
);
3377 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
3378 j
= adapter
->tx_ring
[i
]->reg_idx
;
3379 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
3380 /* PThresh workaround for Tx hang with DFP enabled. */
3382 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
), txdctl
);
3384 /* Enable VLAN tag insert/strip */
3385 adapter
->netdev
->features
|= NETIF_F_HW_VLAN_RX
;
3387 hw
->mac
.ops
.set_vfta(&adapter
->hw
, 0, 0, true);
3391 static void ixgbe_configure(struct ixgbe_adapter
*adapter
)
3393 struct net_device
*netdev
= adapter
->netdev
;
3394 struct ixgbe_hw
*hw
= &adapter
->hw
;
3397 #ifdef CONFIG_IXGBE_DCB
3398 ixgbe_configure_dcb(adapter
);
3401 ixgbe_set_rx_mode(netdev
);
3402 ixgbe_restore_vlan(adapter
);
3405 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
3406 ixgbe_configure_fcoe(adapter
);
3408 #endif /* IXGBE_FCOE */
3409 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
3410 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3411 adapter
->tx_ring
[i
]->atr_sample_rate
=
3412 adapter
->atr_sample_rate
;
3413 ixgbe_init_fdir_signature_82599(hw
, adapter
->fdir_pballoc
);
3414 } else if (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
) {
3415 ixgbe_init_fdir_perfect_82599(hw
, adapter
->fdir_pballoc
);
3417 ixgbe_configure_virtualization(adapter
);
3419 ixgbe_configure_tx(adapter
);
3420 ixgbe_configure_rx(adapter
);
3423 static inline bool ixgbe_is_sfp(struct ixgbe_hw
*hw
)
3425 switch (hw
->phy
.type
) {
3426 case ixgbe_phy_sfp_avago
:
3427 case ixgbe_phy_sfp_ftl
:
3428 case ixgbe_phy_sfp_intel
:
3429 case ixgbe_phy_sfp_unknown
:
3430 case ixgbe_phy_sfp_passive_tyco
:
3431 case ixgbe_phy_sfp_passive_unknown
:
3432 case ixgbe_phy_sfp_active_unknown
:
3433 case ixgbe_phy_sfp_ftl_active
:
3441 * ixgbe_sfp_link_config - set up SFP+ link
3442 * @adapter: pointer to private adapter struct
3444 static void ixgbe_sfp_link_config(struct ixgbe_adapter
*adapter
)
3446 struct ixgbe_hw
*hw
= &adapter
->hw
;
3448 if (hw
->phy
.multispeed_fiber
) {
3450 * In multispeed fiber setups, the device may not have
3451 * had a physical connection when the driver loaded.
3452 * If that's the case, the initial link configuration
3453 * couldn't get the MAC into 10G or 1G mode, so we'll
3454 * never have a link status change interrupt fire.
3455 * We need to try and force an autonegotiation
3456 * session, then bring up link.
3458 hw
->mac
.ops
.setup_sfp(hw
);
3459 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_LINK_TASK
))
3460 schedule_work(&adapter
->multispeed_fiber_task
);
3463 * Direct Attach Cu and non-multispeed fiber modules
3464 * still need to be configured properly prior to
3467 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_MOD_TASK
))
3468 schedule_work(&adapter
->sfp_config_module_task
);
3473 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3474 * @hw: pointer to private hardware struct
3476 * Returns 0 on success, negative on failure
3478 static int ixgbe_non_sfp_link_config(struct ixgbe_hw
*hw
)
3481 bool negotiation
, link_up
= false;
3482 u32 ret
= IXGBE_ERR_LINK_SETUP
;
3484 if (hw
->mac
.ops
.check_link
)
3485 ret
= hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
3490 if (hw
->mac
.ops
.get_link_capabilities
)
3491 ret
= hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
,
3496 if (hw
->mac
.ops
.setup_link
)
3497 ret
= hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, link_up
);
3502 static void ixgbe_setup_gpie(struct ixgbe_adapter
*adapter
)
3504 struct ixgbe_hw
*hw
= &adapter
->hw
;
3507 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3508 gpie
= IXGBE_GPIE_MSIX_MODE
| IXGBE_GPIE_PBA_SUPPORT
|
3510 gpie
|= IXGBE_GPIE_EIAME
;
3512 * use EIAM to auto-mask when MSI-X interrupt is asserted
3513 * this saves a register write for every interrupt
3515 switch (hw
->mac
.type
) {
3516 case ixgbe_mac_82598EB
:
3517 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
3520 case ixgbe_mac_82599EB
:
3521 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3522 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3526 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3527 * specifically only auto mask tx and rx interrupts */
3528 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
3531 /* XXX: to interrupt immediately for EICS writes, enable this */
3532 /* gpie |= IXGBE_GPIE_EIMEN; */
3534 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
3535 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
3536 gpie
|= IXGBE_GPIE_VTMODE_64
;
3539 /* Enable fan failure interrupt */
3540 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
)
3541 gpie
|= IXGBE_SDP1_GPIEN
;
3543 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
3544 gpie
|= IXGBE_SDP1_GPIEN
;
3545 gpie
|= IXGBE_SDP2_GPIEN
;
3547 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
3550 static int ixgbe_up_complete(struct ixgbe_adapter
*adapter
)
3552 struct ixgbe_hw
*hw
= &adapter
->hw
;
3556 ixgbe_get_hw_control(adapter
);
3557 ixgbe_setup_gpie(adapter
);
3559 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
3560 ixgbe_configure_msix(adapter
);
3562 ixgbe_configure_msi_and_legacy(adapter
);
3564 /* enable the optics */
3565 if (hw
->phy
.multispeed_fiber
)
3566 hw
->mac
.ops
.enable_tx_laser(hw
);
3568 clear_bit(__IXGBE_DOWN
, &adapter
->state
);
3569 ixgbe_napi_enable_all(adapter
);
3571 /* clear any pending interrupts, may auto mask */
3572 IXGBE_READ_REG(hw
, IXGBE_EICR
);
3573 ixgbe_irq_enable(adapter
, true, true);
3576 * If this adapter has a fan, check to see if we had a failure
3577 * before we enabled the interrupt.
3579 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
3580 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
3581 if (esdp
& IXGBE_ESDP_SDP1
)
3582 e_crit(drv
, "Fan has stopped, replace the adapter\n");
3586 * For hot-pluggable SFP+ devices, a new SFP+ module may have
3587 * arrived before interrupts were enabled but after probe. Such
3588 * devices wouldn't have their type identified yet. We need to
3589 * kick off the SFP+ module setup first, then try to bring up link.
3590 * If we're not hot-pluggable SFP+, we just need to configure link
3593 if (hw
->phy
.type
== ixgbe_phy_unknown
) {
3594 err
= hw
->phy
.ops
.identify(hw
);
3595 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
3597 * Take the device down and schedule the sfp tasklet
3598 * which will unregister_netdev and log it.
3600 ixgbe_down(adapter
);
3601 schedule_work(&adapter
->sfp_config_module_task
);
3606 if (ixgbe_is_sfp(hw
)) {
3607 ixgbe_sfp_link_config(adapter
);
3609 err
= ixgbe_non_sfp_link_config(hw
);
3611 e_err(probe
, "link_config FAILED %d\n", err
);
3614 /* enable transmits */
3615 netif_tx_start_all_queues(adapter
->netdev
);
3617 /* bring the link up in the watchdog, this could race with our first
3618 * link up interrupt but shouldn't be a problem */
3619 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
3620 adapter
->link_check_timeout
= jiffies
;
3621 mod_timer(&adapter
->watchdog_timer
, jiffies
);
3623 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3624 ctrl_ext
= IXGBE_READ_REG(hw
, IXGBE_CTRL_EXT
);
3625 ctrl_ext
|= IXGBE_CTRL_EXT_PFRSTD
;
3626 IXGBE_WRITE_REG(hw
, IXGBE_CTRL_EXT
, ctrl_ext
);
3631 void ixgbe_reinit_locked(struct ixgbe_adapter
*adapter
)
3633 WARN_ON(in_interrupt());
3634 while (test_and_set_bit(__IXGBE_RESETTING
, &adapter
->state
))
3636 ixgbe_down(adapter
);
3638 * If SR-IOV enabled then wait a bit before bringing the adapter
3639 * back up to give the VFs time to respond to the reset. The
3640 * two second wait is based upon the watchdog timer cycle in
3643 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
3646 clear_bit(__IXGBE_RESETTING
, &adapter
->state
);
3649 int ixgbe_up(struct ixgbe_adapter
*adapter
)
3651 /* hardware has been reset, we need to reload some things */
3652 ixgbe_configure(adapter
);
3654 return ixgbe_up_complete(adapter
);
3657 void ixgbe_reset(struct ixgbe_adapter
*adapter
)
3659 struct ixgbe_hw
*hw
= &adapter
->hw
;
3662 err
= hw
->mac
.ops
.init_hw(hw
);
3665 case IXGBE_ERR_SFP_NOT_PRESENT
:
3667 case IXGBE_ERR_MASTER_REQUESTS_PENDING
:
3668 e_dev_err("master disable timed out\n");
3670 case IXGBE_ERR_EEPROM_VERSION
:
3671 /* We are running on a pre-production device, log a warning */
3672 e_dev_warn("This device is a pre-production adapter/LOM. "
3673 "Please be aware there may be issuesassociated with "
3674 "your hardware. If you are experiencing problems "
3675 "please contact your Intel or hardware "
3676 "representative who provided you with this "
3680 e_dev_err("Hardware Error: %d\n", err
);
3683 /* reprogram the RAR[0] in case user changed it. */
3684 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
3689 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3690 * @adapter: board private structure
3691 * @rx_ring: ring to free buffers from
3693 static void ixgbe_clean_rx_ring(struct ixgbe_adapter
*adapter
,
3694 struct ixgbe_ring
*rx_ring
)
3696 struct pci_dev
*pdev
= adapter
->pdev
;
3700 /* ring already cleared, nothing to do */
3701 if (!rx_ring
->rx_buffer_info
)
3704 /* Free all the Rx ring sk_buffs */
3705 for (i
= 0; i
< rx_ring
->count
; i
++) {
3706 struct ixgbe_rx_buffer
*rx_buffer_info
;
3708 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
3709 if (rx_buffer_info
->dma
) {
3710 dma_unmap_single(&pdev
->dev
, rx_buffer_info
->dma
,
3711 rx_ring
->rx_buf_len
,
3713 rx_buffer_info
->dma
= 0;
3715 if (rx_buffer_info
->skb
) {
3716 struct sk_buff
*skb
= rx_buffer_info
->skb
;
3717 rx_buffer_info
->skb
= NULL
;
3719 struct sk_buff
*this = skb
;
3720 if (IXGBE_RSC_CB(this)->delay_unmap
) {
3721 dma_unmap_single(&pdev
->dev
,
3722 IXGBE_RSC_CB(this)->dma
,
3723 rx_ring
->rx_buf_len
,
3725 IXGBE_RSC_CB(this)->dma
= 0;
3726 IXGBE_RSC_CB(skb
)->delay_unmap
= false;
3729 dev_kfree_skb(this);
3732 if (!rx_buffer_info
->page
)
3734 if (rx_buffer_info
->page_dma
) {
3735 dma_unmap_page(&pdev
->dev
, rx_buffer_info
->page_dma
,
3736 PAGE_SIZE
/ 2, DMA_FROM_DEVICE
);
3737 rx_buffer_info
->page_dma
= 0;
3739 put_page(rx_buffer_info
->page
);
3740 rx_buffer_info
->page
= NULL
;
3741 rx_buffer_info
->page_offset
= 0;
3744 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
3745 memset(rx_ring
->rx_buffer_info
, 0, size
);
3747 /* Zero out the descriptor ring */
3748 memset(rx_ring
->desc
, 0, rx_ring
->size
);
3750 rx_ring
->next_to_clean
= 0;
3751 rx_ring
->next_to_use
= 0;
3754 writel(0, adapter
->hw
.hw_addr
+ rx_ring
->head
);
3756 writel(0, adapter
->hw
.hw_addr
+ rx_ring
->tail
);
3760 * ixgbe_clean_tx_ring - Free Tx Buffers
3761 * @adapter: board private structure
3762 * @tx_ring: ring to be cleaned
3764 static void ixgbe_clean_tx_ring(struct ixgbe_adapter
*adapter
,
3765 struct ixgbe_ring
*tx_ring
)
3767 struct ixgbe_tx_buffer
*tx_buffer_info
;
3771 /* ring already cleared, nothing to do */
3772 if (!tx_ring
->tx_buffer_info
)
3775 /* Free all the Tx ring sk_buffs */
3776 for (i
= 0; i
< tx_ring
->count
; i
++) {
3777 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
3778 ixgbe_unmap_and_free_tx_resource(adapter
, tx_buffer_info
);
3781 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
3782 memset(tx_ring
->tx_buffer_info
, 0, size
);
3784 /* Zero out the descriptor ring */
3785 memset(tx_ring
->desc
, 0, tx_ring
->size
);
3787 tx_ring
->next_to_use
= 0;
3788 tx_ring
->next_to_clean
= 0;
3791 writel(0, adapter
->hw
.hw_addr
+ tx_ring
->head
);
3793 writel(0, adapter
->hw
.hw_addr
+ tx_ring
->tail
);
3797 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3798 * @adapter: board private structure
3800 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter
*adapter
)
3804 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3805 ixgbe_clean_rx_ring(adapter
, adapter
->rx_ring
[i
]);
3809 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3810 * @adapter: board private structure
3812 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter
*adapter
)
3816 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3817 ixgbe_clean_tx_ring(adapter
, adapter
->tx_ring
[i
]);
3820 void ixgbe_down(struct ixgbe_adapter
*adapter
)
3822 struct net_device
*netdev
= adapter
->netdev
;
3823 struct ixgbe_hw
*hw
= &adapter
->hw
;
3827 int num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3829 /* signal that we are down to the interrupt handler */
3830 set_bit(__IXGBE_DOWN
, &adapter
->state
);
3832 /* disable receive for all VFs and wait one second */
3833 if (adapter
->num_vfs
) {
3834 /* ping all the active vfs to let them know we are going down */
3835 ixgbe_ping_all_vfs(adapter
);
3837 /* Disable all VFTE/VFRE TX/RX */
3838 ixgbe_disable_tx_rx(adapter
);
3840 /* Mark all the VFs as inactive */
3841 for (i
= 0 ; i
< adapter
->num_vfs
; i
++)
3842 adapter
->vfinfo
[i
].clear_to_send
= 0;
3845 /* disable receives */
3846 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
3847 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
3849 IXGBE_WRITE_FLUSH(hw
);
3852 netif_tx_stop_all_queues(netdev
);
3854 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
3855 del_timer_sync(&adapter
->sfp_timer
);
3856 del_timer_sync(&adapter
->watchdog_timer
);
3857 cancel_work_sync(&adapter
->watchdog_task
);
3859 netif_carrier_off(netdev
);
3860 netif_tx_disable(netdev
);
3862 ixgbe_irq_disable(adapter
);
3864 ixgbe_napi_disable_all(adapter
);
3866 /* Cleanup the affinity_hint CPU mask memory and callback */
3867 for (i
= 0; i
< num_q_vectors
; i
++) {
3868 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
3869 /* clear the affinity_mask in the IRQ descriptor */
3870 irq_set_affinity_hint(adapter
->msix_entries
[i
]. vector
, NULL
);
3871 /* release the CPU mask memory */
3872 free_cpumask_var(q_vector
->affinity_mask
);
3875 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
3876 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
3877 cancel_work_sync(&adapter
->fdir_reinit_task
);
3879 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
)
3880 cancel_work_sync(&adapter
->check_overtemp_task
);
3882 /* disable transmits in the hardware now that interrupts are off */
3883 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
3884 j
= adapter
->tx_ring
[i
]->reg_idx
;
3885 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
3886 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
),
3887 (txdctl
& ~IXGBE_TXDCTL_ENABLE
));
3889 /* Disable the Tx DMA engine on 82599 */
3890 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
3891 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
,
3892 (IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
) &
3893 ~IXGBE_DMATXCTL_TE
));
3895 /* power down the optics */
3896 if (hw
->phy
.multispeed_fiber
)
3897 hw
->mac
.ops
.disable_tx_laser(hw
);
3899 /* clear n-tuple filters that are cached */
3900 ethtool_ntuple_flush(netdev
);
3902 if (!pci_channel_offline(adapter
->pdev
))
3903 ixgbe_reset(adapter
);
3904 ixgbe_clean_all_tx_rings(adapter
);
3905 ixgbe_clean_all_rx_rings(adapter
);
3907 #ifdef CONFIG_IXGBE_DCA
3908 /* since we reset the hardware DCA settings were cleared */
3909 ixgbe_setup_dca(adapter
);
3914 * ixgbe_poll - NAPI Rx polling callback
3915 * @napi: structure for representing this polling device
3916 * @budget: how many packets driver is allowed to clean
3918 * This function is used for legacy and MSI, NAPI mode
3920 static int ixgbe_poll(struct napi_struct
*napi
, int budget
)
3922 struct ixgbe_q_vector
*q_vector
=
3923 container_of(napi
, struct ixgbe_q_vector
, napi
);
3924 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
3925 int tx_clean_complete
, work_done
= 0;
3927 #ifdef CONFIG_IXGBE_DCA
3928 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
3929 ixgbe_update_tx_dca(adapter
, adapter
->tx_ring
[0]);
3930 ixgbe_update_rx_dca(adapter
, adapter
->rx_ring
[0]);
3934 tx_clean_complete
= ixgbe_clean_tx_irq(q_vector
, adapter
->tx_ring
[0]);
3935 ixgbe_clean_rx_irq(q_vector
, adapter
->rx_ring
[0], &work_done
, budget
);
3937 if (!tx_clean_complete
)
3940 /* If budget not fully consumed, exit the polling mode */
3941 if (work_done
< budget
) {
3942 napi_complete(napi
);
3943 if (adapter
->rx_itr_setting
& 1)
3944 ixgbe_set_itr(adapter
);
3945 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
3946 ixgbe_irq_enable_queues(adapter
, IXGBE_EIMS_RTX_QUEUE
);
3952 * ixgbe_tx_timeout - Respond to a Tx Hang
3953 * @netdev: network interface device structure
3955 static void ixgbe_tx_timeout(struct net_device
*netdev
)
3957 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3959 /* Do the reset outside of interrupt context */
3960 schedule_work(&adapter
->reset_task
);
3963 static void ixgbe_reset_task(struct work_struct
*work
)
3965 struct ixgbe_adapter
*adapter
;
3966 adapter
= container_of(work
, struct ixgbe_adapter
, reset_task
);
3968 /* If we're already down or resetting, just bail */
3969 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
3970 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
3973 adapter
->tx_timeout_count
++;
3975 ixgbe_dump(adapter
);
3976 netdev_err(adapter
->netdev
, "Reset adapter\n");
3977 ixgbe_reinit_locked(adapter
);
3980 #ifdef CONFIG_IXGBE_DCB
3981 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter
*adapter
)
3984 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_DCB
];
3986 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
))
3990 adapter
->num_rx_queues
= f
->indices
;
3991 adapter
->num_tx_queues
= f
->indices
;
3999 * ixgbe_set_rss_queues: Allocate queues for RSS
4000 * @adapter: board private structure to initialize
4002 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4003 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4006 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter
*adapter
)
4009 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_RSS
];
4011 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4013 adapter
->num_rx_queues
= f
->indices
;
4014 adapter
->num_tx_queues
= f
->indices
;
4024 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4025 * @adapter: board private structure to initialize
4027 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4028 * to the original CPU that initiated the Tx session. This runs in addition
4029 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4030 * Rx load across CPUs using RSS.
4033 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter
*adapter
)
4036 struct ixgbe_ring_feature
*f_fdir
= &adapter
->ring_feature
[RING_F_FDIR
];
4038 f_fdir
->indices
= min((int)num_online_cpus(), f_fdir
->indices
);
4041 /* Flow Director must have RSS enabled */
4042 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
&&
4043 ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
4044 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)))) {
4045 adapter
->num_tx_queues
= f_fdir
->indices
;
4046 adapter
->num_rx_queues
= f_fdir
->indices
;
4049 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4050 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
4057 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4058 * @adapter: board private structure to initialize
4060 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4061 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4062 * rx queues out of the max number of rx queues, instead, it is used as the
4063 * index of the first rx queue used by FCoE.
4066 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter
*adapter
)
4069 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
4071 f
->indices
= min((int)num_online_cpus(), f
->indices
);
4072 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
4073 adapter
->num_rx_queues
= 1;
4074 adapter
->num_tx_queues
= 1;
4075 #ifdef CONFIG_IXGBE_DCB
4076 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
4077 e_info(probe
, "FCoE enabled with DCB\n");
4078 ixgbe_set_dcb_queues(adapter
);
4081 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4082 e_info(probe
, "FCoE enabled with RSS\n");
4083 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
4084 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))
4085 ixgbe_set_fdir_queues(adapter
);
4087 ixgbe_set_rss_queues(adapter
);
4089 /* adding FCoE rx rings to the end */
4090 f
->mask
= adapter
->num_rx_queues
;
4091 adapter
->num_rx_queues
+= f
->indices
;
4092 adapter
->num_tx_queues
+= f
->indices
;
4100 #endif /* IXGBE_FCOE */
4102 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4103 * @adapter: board private structure to initialize
4105 * IOV doesn't actually use anything, so just NAK the
4106 * request for now and let the other queue routines
4107 * figure out what to do.
4109 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter
*adapter
)
4115 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4116 * @adapter: board private structure to initialize
4118 * This is the top level queue allocation routine. The order here is very
4119 * important, starting with the "most" number of features turned on at once,
4120 * and ending with the smallest set of features. This way large combinations
4121 * can be allocated if they're turned on, and smaller combinations are the
4122 * fallthrough conditions.
4125 static int ixgbe_set_num_queues(struct ixgbe_adapter
*adapter
)
4127 /* Start with base case */
4128 adapter
->num_rx_queues
= 1;
4129 adapter
->num_tx_queues
= 1;
4130 adapter
->num_rx_pools
= adapter
->num_rx_queues
;
4131 adapter
->num_rx_queues_per_pool
= 1;
4133 if (ixgbe_set_sriov_queues(adapter
))
4137 if (ixgbe_set_fcoe_queues(adapter
))
4140 #endif /* IXGBE_FCOE */
4141 #ifdef CONFIG_IXGBE_DCB
4142 if (ixgbe_set_dcb_queues(adapter
))
4146 if (ixgbe_set_fdir_queues(adapter
))
4149 if (ixgbe_set_rss_queues(adapter
))
4152 /* fallback to base case */
4153 adapter
->num_rx_queues
= 1;
4154 adapter
->num_tx_queues
= 1;
4157 /* Notify the stack of the (possibly) reduced queue counts. */
4158 netif_set_real_num_tx_queues(adapter
->netdev
, adapter
->num_tx_queues
);
4159 return netif_set_real_num_rx_queues(adapter
->netdev
,
4160 adapter
->num_rx_queues
);
4163 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter
*adapter
,
4166 int err
, vector_threshold
;
4168 /* We'll want at least 3 (vector_threshold):
4171 * 3) Other (Link Status Change, etc.)
4172 * 4) TCP Timer (optional)
4174 vector_threshold
= MIN_MSIX_COUNT
;
4176 /* The more we get, the more we will assign to Tx/Rx Cleanup
4177 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4178 * Right now, we simply care about how many we'll get; we'll
4179 * set them up later while requesting irq's.
4181 while (vectors
>= vector_threshold
) {
4182 err
= pci_enable_msix(adapter
->pdev
, adapter
->msix_entries
,
4184 if (!err
) /* Success in acquiring all requested vectors. */
4187 vectors
= 0; /* Nasty failure, quit now */
4188 else /* err == number of vectors we should try again with */
4192 if (vectors
< vector_threshold
) {
4193 /* Can't allocate enough MSI-X interrupts? Oh well.
4194 * This just means we'll go with either a single MSI
4195 * vector or fall back to legacy interrupts.
4197 netif_printk(adapter
, hw
, KERN_DEBUG
, adapter
->netdev
,
4198 "Unable to allocate MSI-X interrupts\n");
4199 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
4200 kfree(adapter
->msix_entries
);
4201 adapter
->msix_entries
= NULL
;
4203 adapter
->flags
|= IXGBE_FLAG_MSIX_ENABLED
; /* Woot! */
4205 * Adjust for only the vectors we'll use, which is minimum
4206 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4207 * vectors we were allocated.
4209 adapter
->num_msix_vectors
= min(vectors
,
4210 adapter
->max_msix_q_vectors
+ NON_Q_VECTORS
);
4215 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4216 * @adapter: board private structure to initialize
4218 * Cache the descriptor ring offsets for RSS to the assigned rings.
4221 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter
*adapter
)
4226 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4227 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4228 adapter
->rx_ring
[i
]->reg_idx
= i
;
4229 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4230 adapter
->tx_ring
[i
]->reg_idx
= i
;
4239 #ifdef CONFIG_IXGBE_DCB
4241 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4242 * @adapter: board private structure to initialize
4244 * Cache the descriptor ring offsets for DCB to the assigned rings.
4247 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter
*adapter
)
4251 int dcb_i
= adapter
->ring_feature
[RING_F_DCB
].indices
;
4253 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
4254 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
4255 /* the number of queues is assumed to be symmetric */
4256 for (i
= 0; i
< dcb_i
; i
++) {
4257 adapter
->rx_ring
[i
]->reg_idx
= i
<< 3;
4258 adapter
->tx_ring
[i
]->reg_idx
= i
<< 2;
4261 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
4264 * Tx TC0 starts at: descriptor queue 0
4265 * Tx TC1 starts at: descriptor queue 32
4266 * Tx TC2 starts at: descriptor queue 64
4267 * Tx TC3 starts at: descriptor queue 80
4268 * Tx TC4 starts at: descriptor queue 96
4269 * Tx TC5 starts at: descriptor queue 104
4270 * Tx TC6 starts at: descriptor queue 112
4271 * Tx TC7 starts at: descriptor queue 120
4273 * Rx TC0-TC7 are offset by 16 queues each
4275 for (i
= 0; i
< 3; i
++) {
4276 adapter
->tx_ring
[i
]->reg_idx
= i
<< 5;
4277 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
4279 for ( ; i
< 5; i
++) {
4280 adapter
->tx_ring
[i
]->reg_idx
=
4282 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
4284 for ( ; i
< dcb_i
; i
++) {
4285 adapter
->tx_ring
[i
]->reg_idx
=
4287 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
4291 } else if (dcb_i
== 4) {
4293 * Tx TC0 starts at: descriptor queue 0
4294 * Tx TC1 starts at: descriptor queue 64
4295 * Tx TC2 starts at: descriptor queue 96
4296 * Tx TC3 starts at: descriptor queue 112
4298 * Rx TC0-TC3 are offset by 32 queues each
4300 adapter
->tx_ring
[0]->reg_idx
= 0;
4301 adapter
->tx_ring
[1]->reg_idx
= 64;
4302 adapter
->tx_ring
[2]->reg_idx
= 96;
4303 adapter
->tx_ring
[3]->reg_idx
= 112;
4304 for (i
= 0 ; i
< dcb_i
; i
++)
4305 adapter
->rx_ring
[i
]->reg_idx
= i
<< 5;
4323 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4324 * @adapter: board private structure to initialize
4326 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4329 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter
*adapter
)
4334 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
&&
4335 ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
4336 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))) {
4337 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4338 adapter
->rx_ring
[i
]->reg_idx
= i
;
4339 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4340 adapter
->tx_ring
[i
]->reg_idx
= i
;
4349 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4350 * @adapter: board private structure to initialize
4352 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4355 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter
*adapter
)
4357 int i
, fcoe_rx_i
= 0, fcoe_tx_i
= 0;
4359 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
4361 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
4362 #ifdef CONFIG_IXGBE_DCB
4363 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
4364 struct ixgbe_fcoe
*fcoe
= &adapter
->fcoe
;
4366 ixgbe_cache_ring_dcb(adapter
);
4367 /* find out queues in TC for FCoE */
4368 fcoe_rx_i
= adapter
->rx_ring
[fcoe
->tc
]->reg_idx
+ 1;
4369 fcoe_tx_i
= adapter
->tx_ring
[fcoe
->tc
]->reg_idx
+ 1;
4371 * In 82599, the number of Tx queues for each traffic
4372 * class for both 8-TC and 4-TC modes are:
4373 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4374 * 8 TCs: 32 32 16 16 8 8 8 8
4375 * 4 TCs: 64 64 32 32
4376 * We have max 8 queues for FCoE, where 8 the is
4377 * FCoE redirection table size. If TC for FCoE is
4378 * less than or equal to TC3, we have enough queues
4379 * to add max of 8 queues for FCoE, so we start FCoE
4380 * tx descriptor from the next one, i.e., reg_idx + 1.
4381 * If TC for FCoE is above TC3, implying 8 TC mode,
4382 * and we need 8 for FCoE, we have to take all queues
4383 * in that traffic class for FCoE.
4385 if ((f
->indices
== IXGBE_FCRETA_SIZE
) && (fcoe
->tc
> 3))
4388 #endif /* CONFIG_IXGBE_DCB */
4389 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4390 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
4391 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))
4392 ixgbe_cache_ring_fdir(adapter
);
4394 ixgbe_cache_ring_rss(adapter
);
4396 fcoe_rx_i
= f
->mask
;
4397 fcoe_tx_i
= f
->mask
;
4399 for (i
= 0; i
< f
->indices
; i
++, fcoe_rx_i
++, fcoe_tx_i
++) {
4400 adapter
->rx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_rx_i
;
4401 adapter
->tx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_tx_i
;
4408 #endif /* IXGBE_FCOE */
4410 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4411 * @adapter: board private structure to initialize
4413 * SR-IOV doesn't use any descriptor rings but changes the default if
4414 * no other mapping is used.
4417 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter
*adapter
)
4419 adapter
->rx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
4420 adapter
->tx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
4421 if (adapter
->num_vfs
)
4428 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4429 * @adapter: board private structure to initialize
4431 * Once we know the feature-set enabled for the device, we'll cache
4432 * the register offset the descriptor ring is assigned to.
4434 * Note, the order the various feature calls is important. It must start with
4435 * the "most" features enabled at the same time, then trickle down to the
4436 * least amount of features turned on at once.
4438 static void ixgbe_cache_ring_register(struct ixgbe_adapter
*adapter
)
4440 /* start with default case */
4441 adapter
->rx_ring
[0]->reg_idx
= 0;
4442 adapter
->tx_ring
[0]->reg_idx
= 0;
4444 if (ixgbe_cache_ring_sriov(adapter
))
4448 if (ixgbe_cache_ring_fcoe(adapter
))
4451 #endif /* IXGBE_FCOE */
4452 #ifdef CONFIG_IXGBE_DCB
4453 if (ixgbe_cache_ring_dcb(adapter
))
4457 if (ixgbe_cache_ring_fdir(adapter
))
4460 if (ixgbe_cache_ring_rss(adapter
))
4465 * ixgbe_alloc_queues - Allocate memory for all rings
4466 * @adapter: board private structure to initialize
4468 * We allocate one ring per queue at run-time since we don't know the
4469 * number of queues at compile-time. The polling_netdev array is
4470 * intended for Multiqueue, but should work fine with a single queue.
4472 static int ixgbe_alloc_queues(struct ixgbe_adapter
*adapter
)
4475 int orig_node
= adapter
->node
;
4477 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4478 struct ixgbe_ring
*ring
= adapter
->tx_ring
[i
];
4479 if (orig_node
== -1) {
4480 int cur_node
= next_online_node(adapter
->node
);
4481 if (cur_node
== MAX_NUMNODES
)
4482 cur_node
= first_online_node
;
4483 adapter
->node
= cur_node
;
4485 ring
= kzalloc_node(sizeof(struct ixgbe_ring
), GFP_KERNEL
,
4488 ring
= kzalloc(sizeof(struct ixgbe_ring
), GFP_KERNEL
);
4490 goto err_tx_ring_allocation
;
4491 ring
->count
= adapter
->tx_ring_count
;
4492 ring
->queue_index
= i
;
4493 ring
->numa_node
= adapter
->node
;
4495 adapter
->tx_ring
[i
] = ring
;
4498 /* Restore the adapter's original node */
4499 adapter
->node
= orig_node
;
4501 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
4502 struct ixgbe_ring
*ring
= adapter
->rx_ring
[i
];
4503 if (orig_node
== -1) {
4504 int cur_node
= next_online_node(adapter
->node
);
4505 if (cur_node
== MAX_NUMNODES
)
4506 cur_node
= first_online_node
;
4507 adapter
->node
= cur_node
;
4509 ring
= kzalloc_node(sizeof(struct ixgbe_ring
), GFP_KERNEL
,
4512 ring
= kzalloc(sizeof(struct ixgbe_ring
), GFP_KERNEL
);
4514 goto err_rx_ring_allocation
;
4515 ring
->count
= adapter
->rx_ring_count
;
4516 ring
->queue_index
= i
;
4517 ring
->numa_node
= adapter
->node
;
4519 adapter
->rx_ring
[i
] = ring
;
4522 /* Restore the adapter's original node */
4523 adapter
->node
= orig_node
;
4525 ixgbe_cache_ring_register(adapter
);
4529 err_rx_ring_allocation
:
4530 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4531 kfree(adapter
->tx_ring
[i
]);
4532 err_tx_ring_allocation
:
4537 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4538 * @adapter: board private structure to initialize
4540 * Attempt to configure the interrupts using the best available
4541 * capabilities of the hardware and the kernel.
4543 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter
*adapter
)
4545 struct ixgbe_hw
*hw
= &adapter
->hw
;
4547 int vector
, v_budget
;
4550 * It's easy to be greedy for MSI-X vectors, but it really
4551 * doesn't do us much good if we have a lot more vectors
4552 * than CPU's. So let's be conservative and only ask for
4553 * (roughly) the same number of vectors as there are CPU's.
4555 v_budget
= min(adapter
->num_rx_queues
+ adapter
->num_tx_queues
,
4556 (int)num_online_cpus()) + NON_Q_VECTORS
;
4559 * At the same time, hardware can only support a maximum of
4560 * hw.mac->max_msix_vectors vectors. With features
4561 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4562 * descriptor queues supported by our device. Thus, we cap it off in
4563 * those rare cases where the cpu count also exceeds our vector limit.
4565 v_budget
= min(v_budget
, (int)hw
->mac
.max_msix_vectors
);
4567 /* A failure in MSI-X entry allocation isn't fatal, but it does
4568 * mean we disable MSI-X capabilities of the adapter. */
4569 adapter
->msix_entries
= kcalloc(v_budget
,
4570 sizeof(struct msix_entry
), GFP_KERNEL
);
4571 if (adapter
->msix_entries
) {
4572 for (vector
= 0; vector
< v_budget
; vector
++)
4573 adapter
->msix_entries
[vector
].entry
= vector
;
4575 ixgbe_acquire_msix_vectors(adapter
, v_budget
);
4577 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
4581 adapter
->flags
&= ~IXGBE_FLAG_DCB_ENABLED
;
4582 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
4583 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4584 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
4585 adapter
->atr_sample_rate
= 0;
4586 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
4587 ixgbe_disable_sriov(adapter
);
4589 err
= ixgbe_set_num_queues(adapter
);
4593 err
= pci_enable_msi(adapter
->pdev
);
4595 adapter
->flags
|= IXGBE_FLAG_MSI_ENABLED
;
4597 netif_printk(adapter
, hw
, KERN_DEBUG
, adapter
->netdev
,
4598 "Unable to allocate MSI interrupt, "
4599 "falling back to legacy. Error: %d\n", err
);
4609 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4610 * @adapter: board private structure to initialize
4612 * We allocate one q_vector per queue interrupt. If allocation fails we
4615 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter
*adapter
)
4617 int q_idx
, num_q_vectors
;
4618 struct ixgbe_q_vector
*q_vector
;
4620 int (*poll
)(struct napi_struct
*, int);
4622 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4623 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4624 napi_vectors
= adapter
->num_rx_queues
;
4625 poll
= &ixgbe_clean_rxtx_many
;
4632 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
4633 q_vector
= kzalloc_node(sizeof(struct ixgbe_q_vector
),
4634 GFP_KERNEL
, adapter
->node
);
4636 q_vector
= kzalloc(sizeof(struct ixgbe_q_vector
),
4640 q_vector
->adapter
= adapter
;
4641 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
4642 q_vector
->eitr
= adapter
->tx_eitr_param
;
4644 q_vector
->eitr
= adapter
->rx_eitr_param
;
4645 q_vector
->v_idx
= q_idx
;
4646 netif_napi_add(adapter
->netdev
, &q_vector
->napi
, (*poll
), 64);
4647 adapter
->q_vector
[q_idx
] = q_vector
;
4655 q_vector
= adapter
->q_vector
[q_idx
];
4656 netif_napi_del(&q_vector
->napi
);
4658 adapter
->q_vector
[q_idx
] = NULL
;
4664 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4665 * @adapter: board private structure to initialize
4667 * This function frees the memory allocated to the q_vectors. In addition if
4668 * NAPI is enabled it will delete any references to the NAPI struct prior
4669 * to freeing the q_vector.
4671 static void ixgbe_free_q_vectors(struct ixgbe_adapter
*adapter
)
4673 int q_idx
, num_q_vectors
;
4675 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
4676 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4680 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
4681 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[q_idx
];
4682 adapter
->q_vector
[q_idx
] = NULL
;
4683 netif_napi_del(&q_vector
->napi
);
4688 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter
*adapter
)
4690 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4691 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
4692 pci_disable_msix(adapter
->pdev
);
4693 kfree(adapter
->msix_entries
);
4694 adapter
->msix_entries
= NULL
;
4695 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
4696 adapter
->flags
&= ~IXGBE_FLAG_MSI_ENABLED
;
4697 pci_disable_msi(adapter
->pdev
);
4702 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4703 * @adapter: board private structure to initialize
4705 * We determine which interrupt scheme to use based on...
4706 * - Kernel support (MSI, MSI-X)
4707 * - which can be user-defined (via MODULE_PARAM)
4708 * - Hardware queue count (num_*_queues)
4709 * - defined by miscellaneous hardware support/features (RSS, etc.)
4711 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter
*adapter
)
4715 /* Number of supported queues */
4716 err
= ixgbe_set_num_queues(adapter
);
4720 err
= ixgbe_set_interrupt_capability(adapter
);
4722 e_dev_err("Unable to setup interrupt capabilities\n");
4723 goto err_set_interrupt
;
4726 err
= ixgbe_alloc_q_vectors(adapter
);
4728 e_dev_err("Unable to allocate memory for queue vectors\n");
4729 goto err_alloc_q_vectors
;
4732 err
= ixgbe_alloc_queues(adapter
);
4734 e_dev_err("Unable to allocate memory for queues\n");
4735 goto err_alloc_queues
;
4738 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4739 (adapter
->num_rx_queues
> 1) ? "Enabled" : "Disabled",
4740 adapter
->num_rx_queues
, adapter
->num_tx_queues
);
4742 set_bit(__IXGBE_DOWN
, &adapter
->state
);
4747 ixgbe_free_q_vectors(adapter
);
4748 err_alloc_q_vectors
:
4749 ixgbe_reset_interrupt_capability(adapter
);
4755 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4756 * @adapter: board private structure to clear interrupt scheme on
4758 * We go through and clear interrupt specific resources and reset the structure
4759 * to pre-load conditions
4761 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter
*adapter
)
4765 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4766 kfree(adapter
->tx_ring
[i
]);
4767 adapter
->tx_ring
[i
] = NULL
;
4769 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
4770 kfree(adapter
->rx_ring
[i
]);
4771 adapter
->rx_ring
[i
] = NULL
;
4774 adapter
->num_tx_queues
= 0;
4775 adapter
->num_rx_queues
= 0;
4777 ixgbe_free_q_vectors(adapter
);
4778 ixgbe_reset_interrupt_capability(adapter
);
4782 * ixgbe_sfp_timer - worker thread to find a missing module
4783 * @data: pointer to our adapter struct
4785 static void ixgbe_sfp_timer(unsigned long data
)
4787 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
4790 * Do the sfp_timer outside of interrupt context due to the
4791 * delays that sfp+ detection requires
4793 schedule_work(&adapter
->sfp_task
);
4797 * ixgbe_sfp_task - worker thread to find a missing module
4798 * @work: pointer to work_struct containing our data
4800 static void ixgbe_sfp_task(struct work_struct
*work
)
4802 struct ixgbe_adapter
*adapter
= container_of(work
,
4803 struct ixgbe_adapter
,
4805 struct ixgbe_hw
*hw
= &adapter
->hw
;
4807 if ((hw
->phy
.type
== ixgbe_phy_nl
) &&
4808 (hw
->phy
.sfp_type
== ixgbe_sfp_type_not_present
)) {
4809 s32 ret
= hw
->phy
.ops
.identify_sfp(hw
);
4810 if (ret
== IXGBE_ERR_SFP_NOT_PRESENT
)
4812 ret
= hw
->phy
.ops
.reset(hw
);
4813 if (ret
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
4814 e_dev_err("failed to initialize because an unsupported "
4815 "SFP+ module type was detected.\n");
4816 e_dev_err("Reload the driver after installing a "
4817 "supported module.\n");
4818 unregister_netdev(adapter
->netdev
);
4820 e_info(probe
, "detected SFP+: %d\n", hw
->phy
.sfp_type
);
4822 /* don't need this routine any more */
4823 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
4827 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
))
4828 mod_timer(&adapter
->sfp_timer
,
4829 round_jiffies(jiffies
+ (2 * HZ
)));
4833 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4834 * @adapter: board private structure to initialize
4836 * ixgbe_sw_init initializes the Adapter private data structure.
4837 * Fields are initialized based on PCI device information and
4838 * OS network device settings (MTU size).
4840 static int __devinit
ixgbe_sw_init(struct ixgbe_adapter
*adapter
)
4842 struct ixgbe_hw
*hw
= &adapter
->hw
;
4843 struct pci_dev
*pdev
= adapter
->pdev
;
4844 struct net_device
*dev
= adapter
->netdev
;
4846 #ifdef CONFIG_IXGBE_DCB
4848 struct tc_configuration
*tc
;
4851 /* PCI config space info */
4853 hw
->vendor_id
= pdev
->vendor
;
4854 hw
->device_id
= pdev
->device
;
4855 hw
->revision_id
= pdev
->revision
;
4856 hw
->subsystem_vendor_id
= pdev
->subsystem_vendor
;
4857 hw
->subsystem_device_id
= pdev
->subsystem_device
;
4859 /* Set capability flags */
4860 rss
= min(IXGBE_MAX_RSS_INDICES
, (int)num_online_cpus());
4861 adapter
->ring_feature
[RING_F_RSS
].indices
= rss
;
4862 adapter
->flags
|= IXGBE_FLAG_RSS_ENABLED
;
4863 adapter
->ring_feature
[RING_F_DCB
].indices
= IXGBE_MAX_DCB_INDICES
;
4864 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
4865 if (hw
->device_id
== IXGBE_DEV_ID_82598AT
)
4866 adapter
->flags
|= IXGBE_FLAG_FAN_FAIL_CAPABLE
;
4867 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82598
;
4868 } else if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
4869 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82599
;
4870 adapter
->flags2
|= IXGBE_FLAG2_RSC_CAPABLE
;
4871 adapter
->flags2
|= IXGBE_FLAG2_RSC_ENABLED
;
4872 if (hw
->device_id
== IXGBE_DEV_ID_82599_T3_LOM
)
4873 adapter
->flags2
|= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
;
4874 if (dev
->features
& NETIF_F_NTUPLE
) {
4875 /* Flow Director perfect filter enabled */
4876 adapter
->flags
|= IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
4877 adapter
->atr_sample_rate
= 0;
4878 spin_lock_init(&adapter
->fdir_perfect_lock
);
4880 /* Flow Director hash filters enabled */
4881 adapter
->flags
|= IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4882 adapter
->atr_sample_rate
= 20;
4884 adapter
->ring_feature
[RING_F_FDIR
].indices
=
4885 IXGBE_MAX_FDIR_INDICES
;
4886 adapter
->fdir_pballoc
= 0;
4888 adapter
->flags
|= IXGBE_FLAG_FCOE_CAPABLE
;
4889 adapter
->flags
&= ~IXGBE_FLAG_FCOE_ENABLED
;
4890 adapter
->ring_feature
[RING_F_FCOE
].indices
= 0;
4891 #ifdef CONFIG_IXGBE_DCB
4892 /* Default traffic class to use for FCoE */
4893 adapter
->fcoe
.tc
= IXGBE_FCOE_DEFTC
;
4894 adapter
->fcoe
.up
= IXGBE_FCOE_DEFTC
;
4896 #endif /* IXGBE_FCOE */
4899 #ifdef CONFIG_IXGBE_DCB
4900 /* Configure DCB traffic classes */
4901 for (j
= 0; j
< MAX_TRAFFIC_CLASS
; j
++) {
4902 tc
= &adapter
->dcb_cfg
.tc_config
[j
];
4903 tc
->path
[DCB_TX_CONFIG
].bwg_id
= 0;
4904 tc
->path
[DCB_TX_CONFIG
].bwg_percent
= 12 + (j
& 1);
4905 tc
->path
[DCB_RX_CONFIG
].bwg_id
= 0;
4906 tc
->path
[DCB_RX_CONFIG
].bwg_percent
= 12 + (j
& 1);
4907 tc
->dcb_pfc
= pfc_disabled
;
4909 adapter
->dcb_cfg
.bw_percentage
[DCB_TX_CONFIG
][0] = 100;
4910 adapter
->dcb_cfg
.bw_percentage
[DCB_RX_CONFIG
][0] = 100;
4911 adapter
->dcb_cfg
.rx_pba_cfg
= pba_equal
;
4912 adapter
->dcb_cfg
.pfc_mode_enable
= false;
4913 adapter
->dcb_cfg
.round_robin_enable
= false;
4914 adapter
->dcb_set_bitmap
= 0x00;
4915 ixgbe_copy_dcb_cfg(&adapter
->dcb_cfg
, &adapter
->temp_dcb_cfg
,
4916 adapter
->ring_feature
[RING_F_DCB
].indices
);
4920 /* default flow control settings */
4921 hw
->fc
.requested_mode
= ixgbe_fc_full
;
4922 hw
->fc
.current_mode
= ixgbe_fc_full
; /* init for ethtool output */
4924 adapter
->last_lfc_mode
= hw
->fc
.current_mode
;
4926 hw
->fc
.high_water
= IXGBE_DEFAULT_FCRTH
;
4927 hw
->fc
.low_water
= IXGBE_DEFAULT_FCRTL
;
4928 hw
->fc
.pause_time
= IXGBE_DEFAULT_FCPAUSE
;
4929 hw
->fc
.send_xon
= true;
4930 hw
->fc
.disable_fc_autoneg
= false;
4932 /* enable itr by default in dynamic mode */
4933 adapter
->rx_itr_setting
= 1;
4934 adapter
->rx_eitr_param
= 20000;
4935 adapter
->tx_itr_setting
= 1;
4936 adapter
->tx_eitr_param
= 10000;
4938 /* set defaults for eitr in MegaBytes */
4939 adapter
->eitr_low
= 10;
4940 adapter
->eitr_high
= 20;
4942 /* set default ring sizes */
4943 adapter
->tx_ring_count
= IXGBE_DEFAULT_TXD
;
4944 adapter
->rx_ring_count
= IXGBE_DEFAULT_RXD
;
4946 /* initialize eeprom parameters */
4947 if (ixgbe_init_eeprom_params_generic(hw
)) {
4948 e_dev_err("EEPROM initialization failed\n");
4952 /* enable rx csum by default */
4953 adapter
->flags
|= IXGBE_FLAG_RX_CSUM_ENABLED
;
4955 /* get assigned NUMA node */
4956 adapter
->node
= dev_to_node(&pdev
->dev
);
4958 set_bit(__IXGBE_DOWN
, &adapter
->state
);
4964 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4965 * @adapter: board private structure
4966 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4968 * Return 0 on success, negative on failure
4970 int ixgbe_setup_tx_resources(struct ixgbe_adapter
*adapter
,
4971 struct ixgbe_ring
*tx_ring
)
4973 struct pci_dev
*pdev
= adapter
->pdev
;
4976 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
4977 tx_ring
->tx_buffer_info
= vmalloc_node(size
, tx_ring
->numa_node
);
4978 if (!tx_ring
->tx_buffer_info
)
4979 tx_ring
->tx_buffer_info
= vmalloc(size
);
4980 if (!tx_ring
->tx_buffer_info
)
4982 memset(tx_ring
->tx_buffer_info
, 0, size
);
4984 /* round up to nearest 4K */
4985 tx_ring
->size
= tx_ring
->count
* sizeof(union ixgbe_adv_tx_desc
);
4986 tx_ring
->size
= ALIGN(tx_ring
->size
, 4096);
4988 tx_ring
->desc
= dma_alloc_coherent(&pdev
->dev
, tx_ring
->size
,
4989 &tx_ring
->dma
, GFP_KERNEL
);
4993 tx_ring
->next_to_use
= 0;
4994 tx_ring
->next_to_clean
= 0;
4995 tx_ring
->work_limit
= tx_ring
->count
;
4999 vfree(tx_ring
->tx_buffer_info
);
5000 tx_ring
->tx_buffer_info
= NULL
;
5001 e_err(probe
, "Unable to allocate memory for the Tx descriptor ring\n");
5006 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5007 * @adapter: board private structure
5009 * If this function returns with an error, then it's possible one or
5010 * more of the rings is populated (while the rest are not). It is the
5011 * callers duty to clean those orphaned rings.
5013 * Return 0 on success, negative on failure
5015 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter
*adapter
)
5019 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5020 err
= ixgbe_setup_tx_resources(adapter
, adapter
->tx_ring
[i
]);
5023 e_err(probe
, "Allocation for Tx Queue %u failed\n", i
);
5031 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5032 * @adapter: board private structure
5033 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5035 * Returns 0 on success, negative on failure
5037 int ixgbe_setup_rx_resources(struct ixgbe_adapter
*adapter
,
5038 struct ixgbe_ring
*rx_ring
)
5040 struct pci_dev
*pdev
= adapter
->pdev
;
5043 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
5044 rx_ring
->rx_buffer_info
= vmalloc_node(size
, adapter
->node
);
5045 if (!rx_ring
->rx_buffer_info
)
5046 rx_ring
->rx_buffer_info
= vmalloc(size
);
5047 if (!rx_ring
->rx_buffer_info
) {
5048 e_err(probe
, "vmalloc allocation failed for the Rx "
5049 "descriptor ring\n");
5052 memset(rx_ring
->rx_buffer_info
, 0, size
);
5054 /* Round up to nearest 4K */
5055 rx_ring
->size
= rx_ring
->count
* sizeof(union ixgbe_adv_rx_desc
);
5056 rx_ring
->size
= ALIGN(rx_ring
->size
, 4096);
5058 rx_ring
->desc
= dma_alloc_coherent(&pdev
->dev
, rx_ring
->size
,
5059 &rx_ring
->dma
, GFP_KERNEL
);
5061 if (!rx_ring
->desc
) {
5062 e_err(probe
, "Memory allocation failed for the Rx "
5063 "descriptor ring\n");
5064 vfree(rx_ring
->rx_buffer_info
);
5068 rx_ring
->next_to_clean
= 0;
5069 rx_ring
->next_to_use
= 0;
5078 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5079 * @adapter: board private structure
5081 * If this function returns with an error, then it's possible one or
5082 * more of the rings is populated (while the rest are not). It is the
5083 * callers duty to clean those orphaned rings.
5085 * Return 0 on success, negative on failure
5088 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter
*adapter
)
5092 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5093 err
= ixgbe_setup_rx_resources(adapter
, adapter
->rx_ring
[i
]);
5096 e_err(probe
, "Allocation for Rx Queue %u failed\n", i
);
5104 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5105 * @adapter: board private structure
5106 * @tx_ring: Tx descriptor ring for a specific queue
5108 * Free all transmit software resources
5110 void ixgbe_free_tx_resources(struct ixgbe_adapter
*adapter
,
5111 struct ixgbe_ring
*tx_ring
)
5113 struct pci_dev
*pdev
= adapter
->pdev
;
5115 ixgbe_clean_tx_ring(adapter
, tx_ring
);
5117 vfree(tx_ring
->tx_buffer_info
);
5118 tx_ring
->tx_buffer_info
= NULL
;
5120 dma_free_coherent(&pdev
->dev
, tx_ring
->size
, tx_ring
->desc
,
5123 tx_ring
->desc
= NULL
;
5127 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5128 * @adapter: board private structure
5130 * Free all transmit software resources
5132 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter
*adapter
)
5136 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5137 if (adapter
->tx_ring
[i
]->desc
)
5138 ixgbe_free_tx_resources(adapter
, adapter
->tx_ring
[i
]);
5142 * ixgbe_free_rx_resources - Free Rx Resources
5143 * @adapter: board private structure
5144 * @rx_ring: ring to clean the resources from
5146 * Free all receive software resources
5148 void ixgbe_free_rx_resources(struct ixgbe_adapter
*adapter
,
5149 struct ixgbe_ring
*rx_ring
)
5151 struct pci_dev
*pdev
= adapter
->pdev
;
5153 ixgbe_clean_rx_ring(adapter
, rx_ring
);
5155 vfree(rx_ring
->rx_buffer_info
);
5156 rx_ring
->rx_buffer_info
= NULL
;
5158 dma_free_coherent(&pdev
->dev
, rx_ring
->size
, rx_ring
->desc
,
5161 rx_ring
->desc
= NULL
;
5165 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5166 * @adapter: board private structure
5168 * Free all receive software resources
5170 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter
*adapter
)
5174 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
5175 if (adapter
->rx_ring
[i
]->desc
)
5176 ixgbe_free_rx_resources(adapter
, adapter
->rx_ring
[i
]);
5180 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5181 * @netdev: network interface device structure
5182 * @new_mtu: new value for maximum frame size
5184 * Returns 0 on success, negative on failure
5186 static int ixgbe_change_mtu(struct net_device
*netdev
, int new_mtu
)
5188 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5189 int max_frame
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
5191 /* MTU < 68 is an error and causes problems on some kernels */
5192 if ((new_mtu
< 68) || (max_frame
> IXGBE_MAX_JUMBO_FRAME_SIZE
))
5195 e_info(probe
, "changing MTU from %d to %d\n", netdev
->mtu
, new_mtu
);
5196 /* must set new MTU before calling down or up */
5197 netdev
->mtu
= new_mtu
;
5199 if (netif_running(netdev
))
5200 ixgbe_reinit_locked(adapter
);
5206 * ixgbe_open - Called when a network interface is made active
5207 * @netdev: network interface device structure
5209 * Returns 0 on success, negative value on failure
5211 * The open entry point is called when a network interface is made
5212 * active by the system (IFF_UP). At this point all resources needed
5213 * for transmit and receive operations are allocated, the interrupt
5214 * handler is registered with the OS, the watchdog timer is started,
5215 * and the stack is notified that the interface is ready.
5217 static int ixgbe_open(struct net_device
*netdev
)
5219 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5222 /* disallow open during test */
5223 if (test_bit(__IXGBE_TESTING
, &adapter
->state
))
5226 netif_carrier_off(netdev
);
5228 /* allocate transmit descriptors */
5229 err
= ixgbe_setup_all_tx_resources(adapter
);
5233 /* allocate receive descriptors */
5234 err
= ixgbe_setup_all_rx_resources(adapter
);
5238 ixgbe_configure(adapter
);
5240 err
= ixgbe_request_irq(adapter
);
5244 err
= ixgbe_up_complete(adapter
);
5248 netif_tx_start_all_queues(netdev
);
5253 ixgbe_release_hw_control(adapter
);
5254 ixgbe_free_irq(adapter
);
5257 ixgbe_free_all_rx_resources(adapter
);
5259 ixgbe_free_all_tx_resources(adapter
);
5260 ixgbe_reset(adapter
);
5266 * ixgbe_close - Disables a network interface
5267 * @netdev: network interface device structure
5269 * Returns 0, this is not allowed to fail
5271 * The close entry point is called when an interface is de-activated
5272 * by the OS. The hardware is still under the drivers control, but
5273 * needs to be disabled. A global MAC reset is issued to stop the
5274 * hardware, and all transmit and receive resources are freed.
5276 static int ixgbe_close(struct net_device
*netdev
)
5278 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5280 ixgbe_down(adapter
);
5281 ixgbe_free_irq(adapter
);
5283 ixgbe_free_all_tx_resources(adapter
);
5284 ixgbe_free_all_rx_resources(adapter
);
5286 ixgbe_release_hw_control(adapter
);
5292 static int ixgbe_resume(struct pci_dev
*pdev
)
5294 struct net_device
*netdev
= pci_get_drvdata(pdev
);
5295 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5298 pci_set_power_state(pdev
, PCI_D0
);
5299 pci_restore_state(pdev
);
5301 * pci_restore_state clears dev->state_saved so call
5302 * pci_save_state to restore it.
5304 pci_save_state(pdev
);
5306 err
= pci_enable_device_mem(pdev
);
5308 e_dev_err("Cannot enable PCI device from suspend\n");
5311 pci_set_master(pdev
);
5313 pci_wake_from_d3(pdev
, false);
5315 err
= ixgbe_init_interrupt_scheme(adapter
);
5317 e_dev_err("Cannot initialize interrupts for device\n");
5321 ixgbe_reset(adapter
);
5323 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
5325 if (netif_running(netdev
)) {
5326 err
= ixgbe_open(adapter
->netdev
);
5331 netif_device_attach(netdev
);
5335 #endif /* CONFIG_PM */
5337 static int __ixgbe_shutdown(struct pci_dev
*pdev
, bool *enable_wake
)
5339 struct net_device
*netdev
= pci_get_drvdata(pdev
);
5340 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5341 struct ixgbe_hw
*hw
= &adapter
->hw
;
5343 u32 wufc
= adapter
->wol
;
5348 netif_device_detach(netdev
);
5350 if (netif_running(netdev
)) {
5351 ixgbe_down(adapter
);
5352 ixgbe_free_irq(adapter
);
5353 ixgbe_free_all_tx_resources(adapter
);
5354 ixgbe_free_all_rx_resources(adapter
);
5358 retval
= pci_save_state(pdev
);
5364 ixgbe_set_rx_mode(netdev
);
5366 /* turn on all-multi mode if wake on multicast is enabled */
5367 if (wufc
& IXGBE_WUFC_MC
) {
5368 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
5369 fctrl
|= IXGBE_FCTRL_MPE
;
5370 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
5373 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
5374 ctrl
|= IXGBE_CTRL_GIO_DIS
;
5375 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, ctrl
);
5377 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, wufc
);
5379 IXGBE_WRITE_REG(hw
, IXGBE_WUC
, 0);
5380 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, 0);
5383 if (wufc
&& hw
->mac
.type
== ixgbe_mac_82599EB
)
5384 pci_wake_from_d3(pdev
, true);
5386 pci_wake_from_d3(pdev
, false);
5388 *enable_wake
= !!wufc
;
5390 ixgbe_clear_interrupt_scheme(adapter
);
5392 ixgbe_release_hw_control(adapter
);
5394 pci_disable_device(pdev
);
5400 static int ixgbe_suspend(struct pci_dev
*pdev
, pm_message_t state
)
5405 retval
= __ixgbe_shutdown(pdev
, &wake
);
5410 pci_prepare_to_sleep(pdev
);
5412 pci_wake_from_d3(pdev
, false);
5413 pci_set_power_state(pdev
, PCI_D3hot
);
5418 #endif /* CONFIG_PM */
5420 static void ixgbe_shutdown(struct pci_dev
*pdev
)
5424 __ixgbe_shutdown(pdev
, &wake
);
5426 if (system_state
== SYSTEM_POWER_OFF
) {
5427 pci_wake_from_d3(pdev
, wake
);
5428 pci_set_power_state(pdev
, PCI_D3hot
);
5433 * ixgbe_update_stats - Update the board statistics counters.
5434 * @adapter: board private structure
5436 void ixgbe_update_stats(struct ixgbe_adapter
*adapter
)
5438 struct net_device
*netdev
= adapter
->netdev
;
5439 struct ixgbe_hw
*hw
= &adapter
->hw
;
5441 u32 i
, missed_rx
= 0, mpc
, bprc
, lxon
, lxoff
, xon_off_tot
;
5442 u64 non_eop_descs
= 0, restart_queue
= 0;
5443 struct ixgbe_hw_stats
*hwstats
= &adapter
->stats
;
5445 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
5446 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
5449 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
5452 for (i
= 0; i
< 16; i
++)
5453 adapter
->hw_rx_no_dma_resources
+=
5454 IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
5455 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5456 rsc_count
+= adapter
->rx_ring
[i
]->rsc_count
;
5457 rsc_flush
+= adapter
->rx_ring
[i
]->rsc_flush
;
5459 adapter
->rsc_total_count
= rsc_count
;
5460 adapter
->rsc_total_flush
= rsc_flush
;
5463 /* gather some stats to the adapter struct that are per queue */
5464 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5465 restart_queue
+= adapter
->tx_ring
[i
]->restart_queue
;
5466 adapter
->restart_queue
= restart_queue
;
5468 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
5469 non_eop_descs
+= adapter
->rx_ring
[i
]->non_eop_descs
;
5470 adapter
->non_eop_descs
= non_eop_descs
;
5472 hwstats
->crcerrs
+= IXGBE_READ_REG(hw
, IXGBE_CRCERRS
);
5473 for (i
= 0; i
< 8; i
++) {
5474 /* for packet buffers not used, the register should read 0 */
5475 mpc
= IXGBE_READ_REG(hw
, IXGBE_MPC(i
));
5477 hwstats
->mpc
[i
] += mpc
;
5478 total_mpc
+= hwstats
->mpc
[i
];
5479 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
5480 hwstats
->rnbc
[i
] += IXGBE_READ_REG(hw
, IXGBE_RNBC(i
));
5481 hwstats
->qptc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPTC(i
));
5482 hwstats
->qbtc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBTC(i
));
5483 hwstats
->qprc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRC(i
));
5484 hwstats
->qbrc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBRC(i
));
5485 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
5486 hwstats
->pxonrxc
[i
] +=
5487 IXGBE_READ_REG(hw
, IXGBE_PXONRXCNT(i
));
5488 hwstats
->pxoffrxc
[i
] +=
5489 IXGBE_READ_REG(hw
, IXGBE_PXOFFRXCNT(i
));
5490 hwstats
->qprdc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
5492 hwstats
->pxonrxc
[i
] +=
5493 IXGBE_READ_REG(hw
, IXGBE_PXONRXC(i
));
5494 hwstats
->pxoffrxc
[i
] +=
5495 IXGBE_READ_REG(hw
, IXGBE_PXOFFRXC(i
));
5497 hwstats
->pxontxc
[i
] += IXGBE_READ_REG(hw
, IXGBE_PXONTXC(i
));
5498 hwstats
->pxofftxc
[i
] += IXGBE_READ_REG(hw
, IXGBE_PXOFFTXC(i
));
5500 hwstats
->gprc
+= IXGBE_READ_REG(hw
, IXGBE_GPRC
);
5501 /* work around hardware counting issue */
5502 hwstats
->gprc
-= missed_rx
;
5504 /* 82598 hardware only has a 32 bit counter in the high register */
5505 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
5507 hwstats
->gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCL
);
5508 tmp
= IXGBE_READ_REG(hw
, IXGBE_GORCH
) & 0xF;
5509 /* 4 high bits of GORC */
5510 hwstats
->gorc
+= (tmp
<< 32);
5511 hwstats
->gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCL
);
5512 tmp
= IXGBE_READ_REG(hw
, IXGBE_GOTCH
) & 0xF;
5513 /* 4 high bits of GOTC */
5514 hwstats
->gotc
+= (tmp
<< 32);
5515 hwstats
->tor
+= IXGBE_READ_REG(hw
, IXGBE_TORL
);
5516 IXGBE_READ_REG(hw
, IXGBE_TORH
); /* to clear */
5517 hwstats
->lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXCNT
);
5518 hwstats
->lxoffrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXCNT
);
5519 hwstats
->fdirmatch
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMATCH
);
5520 hwstats
->fdirmiss
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMISS
);
5522 hwstats
->fccrc
+= IXGBE_READ_REG(hw
, IXGBE_FCCRC
);
5523 hwstats
->fcoerpdc
+= IXGBE_READ_REG(hw
, IXGBE_FCOERPDC
);
5524 hwstats
->fcoeprc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPRC
);
5525 hwstats
->fcoeptc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPTC
);
5526 hwstats
->fcoedwrc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWRC
);
5527 hwstats
->fcoedwtc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWTC
);
5528 #endif /* IXGBE_FCOE */
5530 hwstats
->lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXC
);
5531 hwstats
->lxoffrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXC
);
5532 hwstats
->gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCH
);
5533 hwstats
->gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCH
);
5534 hwstats
->tor
+= IXGBE_READ_REG(hw
, IXGBE_TORH
);
5536 bprc
= IXGBE_READ_REG(hw
, IXGBE_BPRC
);
5537 hwstats
->bprc
+= bprc
;
5538 hwstats
->mprc
+= IXGBE_READ_REG(hw
, IXGBE_MPRC
);
5539 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
5540 hwstats
->mprc
-= bprc
;
5541 hwstats
->roc
+= IXGBE_READ_REG(hw
, IXGBE_ROC
);
5542 hwstats
->prc64
+= IXGBE_READ_REG(hw
, IXGBE_PRC64
);
5543 hwstats
->prc127
+= IXGBE_READ_REG(hw
, IXGBE_PRC127
);
5544 hwstats
->prc255
+= IXGBE_READ_REG(hw
, IXGBE_PRC255
);
5545 hwstats
->prc511
+= IXGBE_READ_REG(hw
, IXGBE_PRC511
);
5546 hwstats
->prc1023
+= IXGBE_READ_REG(hw
, IXGBE_PRC1023
);
5547 hwstats
->prc1522
+= IXGBE_READ_REG(hw
, IXGBE_PRC1522
);
5548 hwstats
->rlec
+= IXGBE_READ_REG(hw
, IXGBE_RLEC
);
5549 lxon
= IXGBE_READ_REG(hw
, IXGBE_LXONTXC
);
5550 hwstats
->lxontxc
+= lxon
;
5551 lxoff
= IXGBE_READ_REG(hw
, IXGBE_LXOFFTXC
);
5552 hwstats
->lxofftxc
+= lxoff
;
5553 hwstats
->ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
5554 hwstats
->gptc
+= IXGBE_READ_REG(hw
, IXGBE_GPTC
);
5555 hwstats
->mptc
+= IXGBE_READ_REG(hw
, IXGBE_MPTC
);
5557 * 82598 errata - tx of flow control packets is included in tx counters
5559 xon_off_tot
= lxon
+ lxoff
;
5560 hwstats
->gptc
-= xon_off_tot
;
5561 hwstats
->mptc
-= xon_off_tot
;
5562 hwstats
->gotc
-= (xon_off_tot
* (ETH_ZLEN
+ ETH_FCS_LEN
));
5563 hwstats
->ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
5564 hwstats
->rfc
+= IXGBE_READ_REG(hw
, IXGBE_RFC
);
5565 hwstats
->rjc
+= IXGBE_READ_REG(hw
, IXGBE_RJC
);
5566 hwstats
->tpr
+= IXGBE_READ_REG(hw
, IXGBE_TPR
);
5567 hwstats
->ptc64
+= IXGBE_READ_REG(hw
, IXGBE_PTC64
);
5568 hwstats
->ptc64
-= xon_off_tot
;
5569 hwstats
->ptc127
+= IXGBE_READ_REG(hw
, IXGBE_PTC127
);
5570 hwstats
->ptc255
+= IXGBE_READ_REG(hw
, IXGBE_PTC255
);
5571 hwstats
->ptc511
+= IXGBE_READ_REG(hw
, IXGBE_PTC511
);
5572 hwstats
->ptc1023
+= IXGBE_READ_REG(hw
, IXGBE_PTC1023
);
5573 hwstats
->ptc1522
+= IXGBE_READ_REG(hw
, IXGBE_PTC1522
);
5574 hwstats
->bptc
+= IXGBE_READ_REG(hw
, IXGBE_BPTC
);
5576 /* Fill out the OS statistics structure */
5577 netdev
->stats
.multicast
= hwstats
->mprc
;
5580 netdev
->stats
.rx_errors
= hwstats
->crcerrs
+ hwstats
->rlec
;
5581 netdev
->stats
.rx_dropped
= 0;
5582 netdev
->stats
.rx_length_errors
= hwstats
->rlec
;
5583 netdev
->stats
.rx_crc_errors
= hwstats
->crcerrs
;
5584 netdev
->stats
.rx_missed_errors
= total_mpc
;
5588 * ixgbe_watchdog - Timer Call-back
5589 * @data: pointer to adapter cast into an unsigned long
5591 static void ixgbe_watchdog(unsigned long data
)
5593 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
5594 struct ixgbe_hw
*hw
= &adapter
->hw
;
5599 * Do the watchdog outside of interrupt context due to the lovely
5600 * delays that some of the newer hardware requires
5603 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
5604 goto watchdog_short_circuit
;
5606 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)) {
5608 * for legacy and MSI interrupts don't set any bits
5609 * that are enabled for EIAM, because this operation
5610 * would set *both* EIMS and EICS for any bit in EIAM
5612 IXGBE_WRITE_REG(hw
, IXGBE_EICS
,
5613 (IXGBE_EICS_TCP_TIMER
| IXGBE_EICS_OTHER
));
5614 goto watchdog_reschedule
;
5617 /* get one bit for every active tx/rx interrupt vector */
5618 for (i
= 0; i
< adapter
->num_msix_vectors
- NON_Q_VECTORS
; i
++) {
5619 struct ixgbe_q_vector
*qv
= adapter
->q_vector
[i
];
5620 if (qv
->rxr_count
|| qv
->txr_count
)
5621 eics
|= ((u64
)1 << i
);
5624 /* Cause software interrupt to ensure rx rings are cleaned */
5625 ixgbe_irq_rearm_queues(adapter
, eics
);
5627 watchdog_reschedule
:
5628 /* Reset the timer */
5629 mod_timer(&adapter
->watchdog_timer
, round_jiffies(jiffies
+ 2 * HZ
));
5631 watchdog_short_circuit
:
5632 schedule_work(&adapter
->watchdog_task
);
5636 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5637 * @work: pointer to work_struct containing our data
5639 static void ixgbe_multispeed_fiber_task(struct work_struct
*work
)
5641 struct ixgbe_adapter
*adapter
= container_of(work
,
5642 struct ixgbe_adapter
,
5643 multispeed_fiber_task
);
5644 struct ixgbe_hw
*hw
= &adapter
->hw
;
5648 adapter
->flags
|= IXGBE_FLAG_IN_SFP_LINK_TASK
;
5649 autoneg
= hw
->phy
.autoneg_advertised
;
5650 if ((!autoneg
) && (hw
->mac
.ops
.get_link_capabilities
))
5651 hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
, &negotiation
);
5652 hw
->mac
.autotry_restart
= false;
5653 if (hw
->mac
.ops
.setup_link
)
5654 hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, true);
5655 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
5656 adapter
->flags
&= ~IXGBE_FLAG_IN_SFP_LINK_TASK
;
5660 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5661 * @work: pointer to work_struct containing our data
5663 static void ixgbe_sfp_config_module_task(struct work_struct
*work
)
5665 struct ixgbe_adapter
*adapter
= container_of(work
,
5666 struct ixgbe_adapter
,
5667 sfp_config_module_task
);
5668 struct ixgbe_hw
*hw
= &adapter
->hw
;
5671 adapter
->flags
|= IXGBE_FLAG_IN_SFP_MOD_TASK
;
5673 /* Time for electrical oscillations to settle down */
5675 err
= hw
->phy
.ops
.identify_sfp(hw
);
5677 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
5678 e_dev_err("failed to initialize because an unsupported SFP+ "
5679 "module type was detected.\n");
5680 e_dev_err("Reload the driver after installing a supported "
5682 unregister_netdev(adapter
->netdev
);
5685 hw
->mac
.ops
.setup_sfp(hw
);
5687 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_LINK_TASK
))
5688 /* This will also work for DA Twinax connections */
5689 schedule_work(&adapter
->multispeed_fiber_task
);
5690 adapter
->flags
&= ~IXGBE_FLAG_IN_SFP_MOD_TASK
;
5694 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5695 * @work: pointer to work_struct containing our data
5697 static void ixgbe_fdir_reinit_task(struct work_struct
*work
)
5699 struct ixgbe_adapter
*adapter
= container_of(work
,
5700 struct ixgbe_adapter
,
5702 struct ixgbe_hw
*hw
= &adapter
->hw
;
5705 if (ixgbe_reinit_fdir_tables_82599(hw
) == 0) {
5706 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5707 set_bit(__IXGBE_FDIR_INIT_DONE
,
5708 &(adapter
->tx_ring
[i
]->reinit_state
));
5710 e_err(probe
, "failed to finish FDIR re-initialization, "
5711 "ignored adding FDIR ATR filters\n");
5713 /* Done FDIR Re-initialization, enable transmits */
5714 netif_tx_start_all_queues(adapter
->netdev
);
5717 static DEFINE_MUTEX(ixgbe_watchdog_lock
);
5720 * ixgbe_watchdog_task - worker thread to bring link up
5721 * @work: pointer to work_struct containing our data
5723 static void ixgbe_watchdog_task(struct work_struct
*work
)
5725 struct ixgbe_adapter
*adapter
= container_of(work
,
5726 struct ixgbe_adapter
,
5728 struct net_device
*netdev
= adapter
->netdev
;
5729 struct ixgbe_hw
*hw
= &adapter
->hw
;
5733 struct ixgbe_ring
*tx_ring
;
5734 int some_tx_pending
= 0;
5736 mutex_lock(&ixgbe_watchdog_lock
);
5738 link_up
= adapter
->link_up
;
5739 link_speed
= adapter
->link_speed
;
5741 if (adapter
->flags
& IXGBE_FLAG_NEED_LINK_UPDATE
) {
5742 hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
, false);
5745 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
5746 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++)
5747 hw
->mac
.ops
.fc_enable(hw
, i
);
5749 hw
->mac
.ops
.fc_enable(hw
, 0);
5752 hw
->mac
.ops
.fc_enable(hw
, 0);
5757 time_after(jiffies
, (adapter
->link_check_timeout
+
5758 IXGBE_TRY_LINK_TIMEOUT
))) {
5759 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_UPDATE
;
5760 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMC_LSC
);
5762 adapter
->link_up
= link_up
;
5763 adapter
->link_speed
= link_speed
;
5767 if (!netif_carrier_ok(netdev
)) {
5768 bool flow_rx
, flow_tx
;
5770 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
5771 u32 mflcn
= IXGBE_READ_REG(hw
, IXGBE_MFLCN
);
5772 u32 fccfg
= IXGBE_READ_REG(hw
, IXGBE_FCCFG
);
5773 flow_rx
= !!(mflcn
& IXGBE_MFLCN_RFCE
);
5774 flow_tx
= !!(fccfg
& IXGBE_FCCFG_TFCE_802_3X
);
5776 u32 frctl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
5777 u32 rmcs
= IXGBE_READ_REG(hw
, IXGBE_RMCS
);
5778 flow_rx
= !!(frctl
& IXGBE_FCTRL_RFCE
);
5779 flow_tx
= !!(rmcs
& IXGBE_RMCS_TFCE_802_3X
);
5782 e_info(drv
, "NIC Link is Up %s, Flow Control: %s\n",
5783 (link_speed
== IXGBE_LINK_SPEED_10GB_FULL
?
5785 (link_speed
== IXGBE_LINK_SPEED_1GB_FULL
?
5786 "1 Gbps" : "unknown speed")),
5787 ((flow_rx
&& flow_tx
) ? "RX/TX" :
5789 (flow_tx
? "TX" : "None"))));
5791 netif_carrier_on(netdev
);
5793 /* Force detection of hung controller */
5794 adapter
->detect_tx_hung
= true;
5797 adapter
->link_up
= false;
5798 adapter
->link_speed
= 0;
5799 if (netif_carrier_ok(netdev
)) {
5800 e_info(drv
, "NIC Link is Down\n");
5801 netif_carrier_off(netdev
);
5805 if (!netif_carrier_ok(netdev
)) {
5806 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5807 tx_ring
= adapter
->tx_ring
[i
];
5808 if (tx_ring
->next_to_use
!= tx_ring
->next_to_clean
) {
5809 some_tx_pending
= 1;
5814 if (some_tx_pending
) {
5815 /* We've lost link, so the controller stops DMA,
5816 * but we've got queued Tx work that's never going
5817 * to get done, so reset controller to flush Tx.
5818 * (Do the reset outside of interrupt context).
5820 schedule_work(&adapter
->reset_task
);
5824 ixgbe_update_stats(adapter
);
5825 mutex_unlock(&ixgbe_watchdog_lock
);
5828 static int ixgbe_tso(struct ixgbe_adapter
*adapter
,
5829 struct ixgbe_ring
*tx_ring
, struct sk_buff
*skb
,
5830 u32 tx_flags
, u8
*hdr_len
, __be16 protocol
)
5832 struct ixgbe_adv_tx_context_desc
*context_desc
;
5835 struct ixgbe_tx_buffer
*tx_buffer_info
;
5836 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
;
5837 u32 mss_l4len_idx
, l4len
;
5839 if (skb_is_gso(skb
)) {
5840 if (skb_header_cloned(skb
)) {
5841 err
= pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
);
5845 l4len
= tcp_hdrlen(skb
);
5848 if (protocol
== htons(ETH_P_IP
)) {
5849 struct iphdr
*iph
= ip_hdr(skb
);
5852 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
5856 } else if (skb_is_gso_v6(skb
)) {
5857 ipv6_hdr(skb
)->payload_len
= 0;
5858 tcp_hdr(skb
)->check
=
5859 ~csum_ipv6_magic(&ipv6_hdr(skb
)->saddr
,
5860 &ipv6_hdr(skb
)->daddr
,
5864 i
= tx_ring
->next_to_use
;
5866 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5867 context_desc
= IXGBE_TX_CTXTDESC_ADV(tx_ring
, i
);
5869 /* VLAN MACLEN IPLEN */
5870 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
5872 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
5873 vlan_macip_lens
|= ((skb_network_offset(skb
)) <<
5874 IXGBE_ADVTXD_MACLEN_SHIFT
);
5875 *hdr_len
+= skb_network_offset(skb
);
5877 (skb_transport_header(skb
) - skb_network_header(skb
));
5879 (skb_transport_header(skb
) - skb_network_header(skb
));
5880 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
5881 context_desc
->seqnum_seed
= 0;
5883 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5884 type_tucmd_mlhl
= (IXGBE_TXD_CMD_DEXT
|
5885 IXGBE_ADVTXD_DTYP_CTXT
);
5887 if (protocol
== htons(ETH_P_IP
))
5888 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_IPV4
;
5889 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
5890 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
5894 (skb_shinfo(skb
)->gso_size
<< IXGBE_ADVTXD_MSS_SHIFT
);
5895 mss_l4len_idx
|= (l4len
<< IXGBE_ADVTXD_L4LEN_SHIFT
);
5896 /* use index 1 for TSO */
5897 mss_l4len_idx
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
5898 context_desc
->mss_l4len_idx
= cpu_to_le32(mss_l4len_idx
);
5900 tx_buffer_info
->time_stamp
= jiffies
;
5901 tx_buffer_info
->next_to_watch
= i
;
5904 if (i
== tx_ring
->count
)
5906 tx_ring
->next_to_use
= i
;
5913 static u32
ixgbe_psum(struct ixgbe_adapter
*adapter
, struct sk_buff
*skb
,
5919 case cpu_to_be16(ETH_P_IP
):
5920 rtn
|= IXGBE_ADVTXD_TUCMD_IPV4
;
5921 switch (ip_hdr(skb
)->protocol
) {
5923 rtn
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
5926 rtn
|= IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
5930 case cpu_to_be16(ETH_P_IPV6
):
5931 /* XXX what about other V6 headers?? */
5932 switch (ipv6_hdr(skb
)->nexthdr
) {
5934 rtn
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
5937 rtn
|= IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
5942 if (unlikely(net_ratelimit()))
5943 e_warn(probe
, "partial checksum but proto=%x!\n",
5951 static bool ixgbe_tx_csum(struct ixgbe_adapter
*adapter
,
5952 struct ixgbe_ring
*tx_ring
,
5953 struct sk_buff
*skb
, u32 tx_flags
,
5956 struct ixgbe_adv_tx_context_desc
*context_desc
;
5958 struct ixgbe_tx_buffer
*tx_buffer_info
;
5959 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
= 0;
5961 if (skb
->ip_summed
== CHECKSUM_PARTIAL
||
5962 (tx_flags
& IXGBE_TX_FLAGS_VLAN
)) {
5963 i
= tx_ring
->next_to_use
;
5964 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5965 context_desc
= IXGBE_TX_CTXTDESC_ADV(tx_ring
, i
);
5967 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
5969 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
5970 vlan_macip_lens
|= (skb_network_offset(skb
) <<
5971 IXGBE_ADVTXD_MACLEN_SHIFT
);
5972 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
5973 vlan_macip_lens
|= (skb_transport_header(skb
) -
5974 skb_network_header(skb
));
5976 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
5977 context_desc
->seqnum_seed
= 0;
5979 type_tucmd_mlhl
|= (IXGBE_TXD_CMD_DEXT
|
5980 IXGBE_ADVTXD_DTYP_CTXT
);
5982 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
5983 type_tucmd_mlhl
|= ixgbe_psum(adapter
, skb
, protocol
);
5985 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
5986 /* use index zero for tx checksum offload */
5987 context_desc
->mss_l4len_idx
= 0;
5989 tx_buffer_info
->time_stamp
= jiffies
;
5990 tx_buffer_info
->next_to_watch
= i
;
5993 if (i
== tx_ring
->count
)
5995 tx_ring
->next_to_use
= i
;
6003 static int ixgbe_tx_map(struct ixgbe_adapter
*adapter
,
6004 struct ixgbe_ring
*tx_ring
,
6005 struct sk_buff
*skb
, u32 tx_flags
,
6008 struct pci_dev
*pdev
= adapter
->pdev
;
6009 struct ixgbe_tx_buffer
*tx_buffer_info
;
6011 unsigned int total
= skb
->len
;
6012 unsigned int offset
= 0, size
, count
= 0, i
;
6013 unsigned int nr_frags
= skb_shinfo(skb
)->nr_frags
;
6016 i
= tx_ring
->next_to_use
;
6018 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
)
6019 /* excluding fcoe_crc_eof for FCoE */
6020 total
-= sizeof(struct fcoe_crc_eof
);
6022 len
= min(skb_headlen(skb
), total
);
6024 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6025 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
6027 tx_buffer_info
->length
= size
;
6028 tx_buffer_info
->mapped_as_page
= false;
6029 tx_buffer_info
->dma
= dma_map_single(&pdev
->dev
,
6031 size
, DMA_TO_DEVICE
);
6032 if (dma_mapping_error(&pdev
->dev
, tx_buffer_info
->dma
))
6034 tx_buffer_info
->time_stamp
= jiffies
;
6035 tx_buffer_info
->next_to_watch
= i
;
6044 if (i
== tx_ring
->count
)
6049 for (f
= 0; f
< nr_frags
; f
++) {
6050 struct skb_frag_struct
*frag
;
6052 frag
= &skb_shinfo(skb
)->frags
[f
];
6053 len
= min((unsigned int)frag
->size
, total
);
6054 offset
= frag
->page_offset
;
6058 if (i
== tx_ring
->count
)
6061 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6062 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
6064 tx_buffer_info
->length
= size
;
6065 tx_buffer_info
->dma
= dma_map_page(&adapter
->pdev
->dev
,
6069 tx_buffer_info
->mapped_as_page
= true;
6070 if (dma_mapping_error(&pdev
->dev
, tx_buffer_info
->dma
))
6072 tx_buffer_info
->time_stamp
= jiffies
;
6073 tx_buffer_info
->next_to_watch
= i
;
6084 tx_ring
->tx_buffer_info
[i
].skb
= skb
;
6085 tx_ring
->tx_buffer_info
[first
].next_to_watch
= i
;
6090 e_dev_err("TX DMA map failed\n");
6092 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6093 tx_buffer_info
->dma
= 0;
6094 tx_buffer_info
->time_stamp
= 0;
6095 tx_buffer_info
->next_to_watch
= 0;
6099 /* clear timestamp and dma mappings for remaining portion of packet */
6102 i
+= tx_ring
->count
;
6104 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6105 ixgbe_unmap_and_free_tx_resource(adapter
, tx_buffer_info
);
6111 static void ixgbe_tx_queue(struct ixgbe_adapter
*adapter
,
6112 struct ixgbe_ring
*tx_ring
,
6113 int tx_flags
, int count
, u32 paylen
, u8 hdr_len
)
6115 union ixgbe_adv_tx_desc
*tx_desc
= NULL
;
6116 struct ixgbe_tx_buffer
*tx_buffer_info
;
6117 u32 olinfo_status
= 0, cmd_type_len
= 0;
6119 u32 txd_cmd
= IXGBE_TXD_CMD_EOP
| IXGBE_TXD_CMD_RS
| IXGBE_TXD_CMD_IFCS
;
6121 cmd_type_len
|= IXGBE_ADVTXD_DTYP_DATA
;
6123 cmd_type_len
|= IXGBE_ADVTXD_DCMD_IFCS
| IXGBE_ADVTXD_DCMD_DEXT
;
6125 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
6126 cmd_type_len
|= IXGBE_ADVTXD_DCMD_VLE
;
6128 if (tx_flags
& IXGBE_TX_FLAGS_TSO
) {
6129 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
6131 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
6132 IXGBE_ADVTXD_POPTS_SHIFT
;
6134 /* use index 1 context for tso */
6135 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
6136 if (tx_flags
& IXGBE_TX_FLAGS_IPV4
)
6137 olinfo_status
|= IXGBE_TXD_POPTS_IXSM
<<
6138 IXGBE_ADVTXD_POPTS_SHIFT
;
6140 } else if (tx_flags
& IXGBE_TX_FLAGS_CSUM
)
6141 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
6142 IXGBE_ADVTXD_POPTS_SHIFT
;
6144 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
6145 olinfo_status
|= IXGBE_ADVTXD_CC
;
6146 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
6147 if (tx_flags
& IXGBE_TX_FLAGS_FSO
)
6148 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
6151 olinfo_status
|= ((paylen
- hdr_len
) << IXGBE_ADVTXD_PAYLEN_SHIFT
);
6153 i
= tx_ring
->next_to_use
;
6155 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6156 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, i
);
6157 tx_desc
->read
.buffer_addr
= cpu_to_le64(tx_buffer_info
->dma
);
6158 tx_desc
->read
.cmd_type_len
=
6159 cpu_to_le32(cmd_type_len
| tx_buffer_info
->length
);
6160 tx_desc
->read
.olinfo_status
= cpu_to_le32(olinfo_status
);
6162 if (i
== tx_ring
->count
)
6166 tx_desc
->read
.cmd_type_len
|= cpu_to_le32(txd_cmd
);
6169 * Force memory writes to complete before letting h/w
6170 * know there are new descriptors to fetch. (Only
6171 * applicable for weak-ordered memory model archs,
6176 tx_ring
->next_to_use
= i
;
6177 writel(i
, adapter
->hw
.hw_addr
+ tx_ring
->tail
);
6180 static void ixgbe_atr(struct ixgbe_adapter
*adapter
, struct sk_buff
*skb
,
6181 int queue
, u32 tx_flags
, __be16 protocol
)
6183 struct ixgbe_atr_input atr_input
;
6185 struct iphdr
*iph
= ip_hdr(skb
);
6186 struct ethhdr
*eth
= (struct ethhdr
*)skb
->data
;
6187 u16 vlan_id
, src_port
, dst_port
, flex_bytes
;
6188 u32 src_ipv4_addr
, dst_ipv4_addr
;
6191 /* Right now, we support IPv4 only */
6192 if (protocol
!= htons(ETH_P_IP
))
6194 /* check if we're UDP or TCP */
6195 if (iph
->protocol
== IPPROTO_TCP
) {
6197 src_port
= th
->source
;
6198 dst_port
= th
->dest
;
6199 l4type
|= IXGBE_ATR_L4TYPE_TCP
;
6200 /* l4type IPv4 type is 0, no need to assign */
6202 /* Unsupported L4 header, just bail here */
6206 memset(&atr_input
, 0, sizeof(struct ixgbe_atr_input
));
6208 vlan_id
= (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
) >>
6209 IXGBE_TX_FLAGS_VLAN_SHIFT
;
6210 src_ipv4_addr
= iph
->saddr
;
6211 dst_ipv4_addr
= iph
->daddr
;
6212 flex_bytes
= eth
->h_proto
;
6214 ixgbe_atr_set_vlan_id_82599(&atr_input
, vlan_id
);
6215 ixgbe_atr_set_src_port_82599(&atr_input
, dst_port
);
6216 ixgbe_atr_set_dst_port_82599(&atr_input
, src_port
);
6217 ixgbe_atr_set_flex_byte_82599(&atr_input
, flex_bytes
);
6218 ixgbe_atr_set_l4type_82599(&atr_input
, l4type
);
6219 /* src and dst are inverted, think how the receiver sees them */
6220 ixgbe_atr_set_src_ipv4_82599(&atr_input
, dst_ipv4_addr
);
6221 ixgbe_atr_set_dst_ipv4_82599(&atr_input
, src_ipv4_addr
);
6223 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6224 ixgbe_fdir_add_signature_filter_82599(&adapter
->hw
, &atr_input
, queue
);
6227 static int __ixgbe_maybe_stop_tx(struct net_device
*netdev
,
6228 struct ixgbe_ring
*tx_ring
, int size
)
6230 netif_stop_subqueue(netdev
, tx_ring
->queue_index
);
6231 /* Herbert's original patch had:
6232 * smp_mb__after_netif_stop_queue();
6233 * but since that doesn't exist yet, just open code it. */
6236 /* We need to check again in a case another CPU has just
6237 * made room available. */
6238 if (likely(IXGBE_DESC_UNUSED(tx_ring
) < size
))
6241 /* A reprieve! - use start_queue because it doesn't call schedule */
6242 netif_start_subqueue(netdev
, tx_ring
->queue_index
);
6243 ++tx_ring
->restart_queue
;
6247 static int ixgbe_maybe_stop_tx(struct net_device
*netdev
,
6248 struct ixgbe_ring
*tx_ring
, int size
)
6250 if (likely(IXGBE_DESC_UNUSED(tx_ring
) >= size
))
6252 return __ixgbe_maybe_stop_tx(netdev
, tx_ring
, size
);
6255 static u16
ixgbe_select_queue(struct net_device
*dev
, struct sk_buff
*skb
)
6257 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6258 int txq
= smp_processor_id();
6262 protocol
= vlan_get_protocol(skb
);
6264 if ((protocol
== htons(ETH_P_FCOE
)) ||
6265 (protocol
== htons(ETH_P_FIP
))) {
6266 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
6267 txq
&= (adapter
->ring_feature
[RING_F_FCOE
].indices
- 1);
6268 txq
+= adapter
->ring_feature
[RING_F_FCOE
].mask
;
6270 #ifdef CONFIG_IXGBE_DCB
6271 } else if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6272 txq
= adapter
->fcoe
.up
;
6279 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
6280 while (unlikely(txq
>= dev
->real_num_tx_queues
))
6281 txq
-= dev
->real_num_tx_queues
;
6285 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6286 if (skb
->priority
== TC_PRIO_CONTROL
)
6287 txq
= adapter
->ring_feature
[RING_F_DCB
].indices
-1;
6289 txq
= (skb
->vlan_tci
& IXGBE_TX_FLAGS_VLAN_PRIO_MASK
)
6294 return skb_tx_hash(dev
, skb
);
6297 netdev_tx_t
ixgbe_xmit_frame_ring(struct sk_buff
*skb
, struct net_device
*netdev
,
6298 struct ixgbe_adapter
*adapter
,
6299 struct ixgbe_ring
*tx_ring
)
6301 struct netdev_queue
*txq
;
6303 unsigned int tx_flags
= 0;
6310 protocol
= vlan_get_protocol(skb
);
6312 if (vlan_tx_tag_present(skb
)) {
6313 tx_flags
|= vlan_tx_tag_get(skb
);
6314 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6315 tx_flags
&= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK
;
6316 tx_flags
|= ((skb
->queue_mapping
& 0x7) << 13);
6318 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
6319 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
6320 } else if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
&&
6321 skb
->priority
!= TC_PRIO_CONTROL
) {
6322 tx_flags
|= ((skb
->queue_mapping
& 0x7) << 13);
6323 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
6324 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
6328 /* for FCoE with DCB, we force the priority to what
6329 * was specified by the switch */
6330 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
&&
6331 (protocol
== htons(ETH_P_FCOE
) ||
6332 protocol
== htons(ETH_P_FIP
))) {
6333 #ifdef CONFIG_IXGBE_DCB
6334 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6335 tx_flags
&= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6336 << IXGBE_TX_FLAGS_VLAN_SHIFT
);
6337 tx_flags
|= ((adapter
->fcoe
.up
<< 13)
6338 << IXGBE_TX_FLAGS_VLAN_SHIFT
);
6341 /* flag for FCoE offloads */
6342 if (protocol
== htons(ETH_P_FCOE
))
6343 tx_flags
|= IXGBE_TX_FLAGS_FCOE
;
6347 /* four things can cause us to need a context descriptor */
6348 if (skb_is_gso(skb
) ||
6349 (skb
->ip_summed
== CHECKSUM_PARTIAL
) ||
6350 (tx_flags
& IXGBE_TX_FLAGS_VLAN
) ||
6351 (tx_flags
& IXGBE_TX_FLAGS_FCOE
))
6354 count
+= TXD_USE_COUNT(skb_headlen(skb
));
6355 for (f
= 0; f
< skb_shinfo(skb
)->nr_frags
; f
++)
6356 count
+= TXD_USE_COUNT(skb_shinfo(skb
)->frags
[f
].size
);
6358 if (ixgbe_maybe_stop_tx(netdev
, tx_ring
, count
)) {
6360 return NETDEV_TX_BUSY
;
6363 first
= tx_ring
->next_to_use
;
6364 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
6366 /* setup tx offload for FCoE */
6367 tso
= ixgbe_fso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
);
6369 dev_kfree_skb_any(skb
);
6370 return NETDEV_TX_OK
;
6373 tx_flags
|= IXGBE_TX_FLAGS_FSO
;
6374 #endif /* IXGBE_FCOE */
6376 if (protocol
== htons(ETH_P_IP
))
6377 tx_flags
|= IXGBE_TX_FLAGS_IPV4
;
6378 tso
= ixgbe_tso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
,
6381 dev_kfree_skb_any(skb
);
6382 return NETDEV_TX_OK
;
6386 tx_flags
|= IXGBE_TX_FLAGS_TSO
;
6387 else if (ixgbe_tx_csum(adapter
, tx_ring
, skb
, tx_flags
,
6389 (skb
->ip_summed
== CHECKSUM_PARTIAL
))
6390 tx_flags
|= IXGBE_TX_FLAGS_CSUM
;
6393 count
= ixgbe_tx_map(adapter
, tx_ring
, skb
, tx_flags
, first
);
6395 /* add the ATR filter if ATR is on */
6396 if (tx_ring
->atr_sample_rate
) {
6397 ++tx_ring
->atr_count
;
6398 if ((tx_ring
->atr_count
>= tx_ring
->atr_sample_rate
) &&
6399 test_bit(__IXGBE_FDIR_INIT_DONE
,
6400 &tx_ring
->reinit_state
)) {
6401 ixgbe_atr(adapter
, skb
, tx_ring
->queue_index
,
6402 tx_flags
, protocol
);
6403 tx_ring
->atr_count
= 0;
6406 txq
= netdev_get_tx_queue(netdev
, tx_ring
->queue_index
);
6407 txq
->tx_bytes
+= skb
->len
;
6409 ixgbe_tx_queue(adapter
, tx_ring
, tx_flags
, count
, skb
->len
,
6411 ixgbe_maybe_stop_tx(netdev
, tx_ring
, DESC_NEEDED
);
6414 dev_kfree_skb_any(skb
);
6415 tx_ring
->tx_buffer_info
[first
].time_stamp
= 0;
6416 tx_ring
->next_to_use
= first
;
6419 return NETDEV_TX_OK
;
6422 static netdev_tx_t
ixgbe_xmit_frame(struct sk_buff
*skb
, struct net_device
*netdev
)
6424 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6425 struct ixgbe_ring
*tx_ring
;
6427 tx_ring
= adapter
->tx_ring
[skb
->queue_mapping
];
6428 return ixgbe_xmit_frame_ring(skb
, netdev
, adapter
, tx_ring
);
6432 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6433 * @netdev: network interface device structure
6434 * @p: pointer to an address structure
6436 * Returns 0 on success, negative on failure
6438 static int ixgbe_set_mac(struct net_device
*netdev
, void *p
)
6440 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6441 struct ixgbe_hw
*hw
= &adapter
->hw
;
6442 struct sockaddr
*addr
= p
;
6444 if (!is_valid_ether_addr(addr
->sa_data
))
6445 return -EADDRNOTAVAIL
;
6447 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
6448 memcpy(hw
->mac
.addr
, addr
->sa_data
, netdev
->addr_len
);
6450 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
6457 ixgbe_mdio_read(struct net_device
*netdev
, int prtad
, int devad
, u16 addr
)
6459 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6460 struct ixgbe_hw
*hw
= &adapter
->hw
;
6464 if (prtad
!= hw
->phy
.mdio
.prtad
)
6466 rc
= hw
->phy
.ops
.read_reg(hw
, addr
, devad
, &value
);
6472 static int ixgbe_mdio_write(struct net_device
*netdev
, int prtad
, int devad
,
6473 u16 addr
, u16 value
)
6475 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6476 struct ixgbe_hw
*hw
= &adapter
->hw
;
6478 if (prtad
!= hw
->phy
.mdio
.prtad
)
6480 return hw
->phy
.ops
.write_reg(hw
, addr
, devad
, value
);
6483 static int ixgbe_ioctl(struct net_device
*netdev
, struct ifreq
*req
, int cmd
)
6485 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6487 return mdio_mii_ioctl(&adapter
->hw
.phy
.mdio
, if_mii(req
), cmd
);
6491 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6493 * @netdev: network interface device structure
6495 * Returns non-zero on failure
6497 static int ixgbe_add_sanmac_netdev(struct net_device
*dev
)
6500 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6501 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
6503 if (is_valid_ether_addr(mac
->san_addr
)) {
6505 err
= dev_addr_add(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
6512 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6514 * @netdev: network interface device structure
6516 * Returns non-zero on failure
6518 static int ixgbe_del_sanmac_netdev(struct net_device
*dev
)
6521 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6522 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
6524 if (is_valid_ether_addr(mac
->san_addr
)) {
6526 err
= dev_addr_del(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
6532 #ifdef CONFIG_NET_POLL_CONTROLLER
6534 * Polling 'interrupt' - used by things like netconsole to send skbs
6535 * without having to re-enable interrupts. It's not called while
6536 * the interrupt routine is executing.
6538 static void ixgbe_netpoll(struct net_device
*netdev
)
6540 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6543 /* if interface is down do nothing */
6544 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
6547 adapter
->flags
|= IXGBE_FLAG_IN_NETPOLL
;
6548 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
6549 int num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
6550 for (i
= 0; i
< num_q_vectors
; i
++) {
6551 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
6552 ixgbe_msix_clean_many(0, q_vector
);
6555 ixgbe_intr(adapter
->pdev
->irq
, netdev
);
6557 adapter
->flags
&= ~IXGBE_FLAG_IN_NETPOLL
;
6561 static struct rtnl_link_stats64
*ixgbe_get_stats64(struct net_device
*netdev
,
6562 struct rtnl_link_stats64
*stats
)
6564 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6567 /* accurate rx/tx bytes/packets stats */
6568 dev_txq_stats_fold(netdev
, stats
);
6569 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
6570 struct ixgbe_ring
*ring
= adapter
->rx_ring
[i
];
6575 start
= u64_stats_fetch_begin_bh(&ring
->syncp
);
6576 packets
= ring
->stats
.packets
;
6577 bytes
= ring
->stats
.bytes
;
6578 } while (u64_stats_fetch_retry_bh(&ring
->syncp
, start
));
6579 stats
->rx_packets
+= packets
;
6580 stats
->rx_bytes
+= bytes
;
6583 /* following stats updated by ixgbe_watchdog_task() */
6584 stats
->multicast
= netdev
->stats
.multicast
;
6585 stats
->rx_errors
= netdev
->stats
.rx_errors
;
6586 stats
->rx_length_errors
= netdev
->stats
.rx_length_errors
;
6587 stats
->rx_crc_errors
= netdev
->stats
.rx_crc_errors
;
6588 stats
->rx_missed_errors
= netdev
->stats
.rx_missed_errors
;
6593 static const struct net_device_ops ixgbe_netdev_ops
= {
6594 .ndo_open
= ixgbe_open
,
6595 .ndo_stop
= ixgbe_close
,
6596 .ndo_start_xmit
= ixgbe_xmit_frame
,
6597 .ndo_select_queue
= ixgbe_select_queue
,
6598 .ndo_set_rx_mode
= ixgbe_set_rx_mode
,
6599 .ndo_set_multicast_list
= ixgbe_set_rx_mode
,
6600 .ndo_validate_addr
= eth_validate_addr
,
6601 .ndo_set_mac_address
= ixgbe_set_mac
,
6602 .ndo_change_mtu
= ixgbe_change_mtu
,
6603 .ndo_tx_timeout
= ixgbe_tx_timeout
,
6604 .ndo_vlan_rx_add_vid
= ixgbe_vlan_rx_add_vid
,
6605 .ndo_vlan_rx_kill_vid
= ixgbe_vlan_rx_kill_vid
,
6606 .ndo_do_ioctl
= ixgbe_ioctl
,
6607 .ndo_set_vf_mac
= ixgbe_ndo_set_vf_mac
,
6608 .ndo_set_vf_vlan
= ixgbe_ndo_set_vf_vlan
,
6609 .ndo_set_vf_tx_rate
= ixgbe_ndo_set_vf_bw
,
6610 .ndo_get_vf_config
= ixgbe_ndo_get_vf_config
,
6611 .ndo_get_stats64
= ixgbe_get_stats64
,
6612 #ifdef CONFIG_NET_POLL_CONTROLLER
6613 .ndo_poll_controller
= ixgbe_netpoll
,
6616 .ndo_fcoe_ddp_setup
= ixgbe_fcoe_ddp_get
,
6617 .ndo_fcoe_ddp_done
= ixgbe_fcoe_ddp_put
,
6618 .ndo_fcoe_enable
= ixgbe_fcoe_enable
,
6619 .ndo_fcoe_disable
= ixgbe_fcoe_disable
,
6620 .ndo_fcoe_get_wwn
= ixgbe_fcoe_get_wwn
,
6621 #endif /* IXGBE_FCOE */
6624 static void __devinit
ixgbe_probe_vf(struct ixgbe_adapter
*adapter
,
6625 const struct ixgbe_info
*ii
)
6627 #ifdef CONFIG_PCI_IOV
6628 struct ixgbe_hw
*hw
= &adapter
->hw
;
6631 if (hw
->mac
.type
!= ixgbe_mac_82599EB
|| !max_vfs
)
6634 /* The 82599 supports up to 64 VFs per physical function
6635 * but this implementation limits allocation to 63 so that
6636 * basic networking resources are still available to the
6639 adapter
->num_vfs
= (max_vfs
> 63) ? 63 : max_vfs
;
6640 adapter
->flags
|= IXGBE_FLAG_SRIOV_ENABLED
;
6641 err
= pci_enable_sriov(adapter
->pdev
, adapter
->num_vfs
);
6643 e_err(probe
, "Failed to enable PCI sriov: %d\n", err
);
6646 /* If call to enable VFs succeeded then allocate memory
6647 * for per VF control structures.
6650 kcalloc(adapter
->num_vfs
,
6651 sizeof(struct vf_data_storage
), GFP_KERNEL
);
6652 if (adapter
->vfinfo
) {
6653 /* Now that we're sure SR-IOV is enabled
6654 * and memory allocated set up the mailbox parameters
6656 ixgbe_init_mbx_params_pf(hw
);
6657 memcpy(&hw
->mbx
.ops
, ii
->mbx_ops
,
6658 sizeof(hw
->mbx
.ops
));
6660 /* Disable RSC when in SR-IOV mode */
6661 adapter
->flags2
&= ~(IXGBE_FLAG2_RSC_CAPABLE
|
6662 IXGBE_FLAG2_RSC_ENABLED
);
6667 e_err(probe
, "Unable to allocate memory for VF Data Storage - "
6668 "SRIOV disabled\n");
6669 pci_disable_sriov(adapter
->pdev
);
6672 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
6673 adapter
->num_vfs
= 0;
6674 #endif /* CONFIG_PCI_IOV */
6678 * ixgbe_probe - Device Initialization Routine
6679 * @pdev: PCI device information struct
6680 * @ent: entry in ixgbe_pci_tbl
6682 * Returns 0 on success, negative on failure
6684 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6685 * The OS initialization, configuring of the adapter private structure,
6686 * and a hardware reset occur.
6688 static int __devinit
ixgbe_probe(struct pci_dev
*pdev
,
6689 const struct pci_device_id
*ent
)
6691 struct net_device
*netdev
;
6692 struct ixgbe_adapter
*adapter
= NULL
;
6693 struct ixgbe_hw
*hw
;
6694 const struct ixgbe_info
*ii
= ixgbe_info_tbl
[ent
->driver_data
];
6695 static int cards_found
;
6696 int i
, err
, pci_using_dac
;
6697 unsigned int indices
= num_possible_cpus();
6703 /* Catch broken hardware that put the wrong VF device ID in
6704 * the PCIe SR-IOV capability.
6706 if (pdev
->is_virtfn
) {
6707 WARN(1, KERN_ERR
"%s (%hx:%hx) should not be a VF!\n",
6708 pci_name(pdev
), pdev
->vendor
, pdev
->device
);
6712 err
= pci_enable_device_mem(pdev
);
6716 if (!dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(64)) &&
6717 !dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(64))) {
6720 err
= dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(32));
6722 err
= dma_set_coherent_mask(&pdev
->dev
,
6726 "No usable DMA configuration, aborting\n");
6733 err
= pci_request_selected_regions(pdev
, pci_select_bars(pdev
,
6734 IORESOURCE_MEM
), ixgbe_driver_name
);
6737 "pci_request_selected_regions failed 0x%x\n", err
);
6741 pci_enable_pcie_error_reporting(pdev
);
6743 pci_set_master(pdev
);
6744 pci_save_state(pdev
);
6746 if (ii
->mac
== ixgbe_mac_82598EB
)
6747 indices
= min_t(unsigned int, indices
, IXGBE_MAX_RSS_INDICES
);
6749 indices
= min_t(unsigned int, indices
, IXGBE_MAX_FDIR_INDICES
);
6751 indices
= max_t(unsigned int, indices
, IXGBE_MAX_DCB_INDICES
);
6753 indices
+= min_t(unsigned int, num_possible_cpus(),
6754 IXGBE_MAX_FCOE_INDICES
);
6756 netdev
= alloc_etherdev_mq(sizeof(struct ixgbe_adapter
), indices
);
6759 goto err_alloc_etherdev
;
6762 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
6764 pci_set_drvdata(pdev
, netdev
);
6765 adapter
= netdev_priv(netdev
);
6767 adapter
->netdev
= netdev
;
6768 adapter
->pdev
= pdev
;
6771 adapter
->msg_enable
= (1 << DEFAULT_DEBUG_LEVEL_SHIFT
) - 1;
6773 hw
->hw_addr
= ioremap(pci_resource_start(pdev
, 0),
6774 pci_resource_len(pdev
, 0));
6780 for (i
= 1; i
<= 5; i
++) {
6781 if (pci_resource_len(pdev
, i
) == 0)
6785 netdev
->netdev_ops
= &ixgbe_netdev_ops
;
6786 ixgbe_set_ethtool_ops(netdev
);
6787 netdev
->watchdog_timeo
= 5 * HZ
;
6788 strcpy(netdev
->name
, pci_name(pdev
));
6790 adapter
->bd_number
= cards_found
;
6793 memcpy(&hw
->mac
.ops
, ii
->mac_ops
, sizeof(hw
->mac
.ops
));
6794 hw
->mac
.type
= ii
->mac
;
6797 memcpy(&hw
->eeprom
.ops
, ii
->eeprom_ops
, sizeof(hw
->eeprom
.ops
));
6798 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
6799 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6800 if (!(eec
& (1 << 8)))
6801 hw
->eeprom
.ops
.read
= &ixgbe_read_eeprom_bit_bang_generic
;
6804 memcpy(&hw
->phy
.ops
, ii
->phy_ops
, sizeof(hw
->phy
.ops
));
6805 hw
->phy
.sfp_type
= ixgbe_sfp_type_unknown
;
6806 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6807 hw
->phy
.mdio
.prtad
= MDIO_PRTAD_NONE
;
6808 hw
->phy
.mdio
.mmds
= 0;
6809 hw
->phy
.mdio
.mode_support
= MDIO_SUPPORTS_C45
| MDIO_EMULATE_C22
;
6810 hw
->phy
.mdio
.dev
= netdev
;
6811 hw
->phy
.mdio
.mdio_read
= ixgbe_mdio_read
;
6812 hw
->phy
.mdio
.mdio_write
= ixgbe_mdio_write
;
6814 /* set up this timer and work struct before calling get_invariants
6815 * which might start the timer
6817 init_timer(&adapter
->sfp_timer
);
6818 adapter
->sfp_timer
.function
= ixgbe_sfp_timer
;
6819 adapter
->sfp_timer
.data
= (unsigned long) adapter
;
6821 INIT_WORK(&adapter
->sfp_task
, ixgbe_sfp_task
);
6823 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6824 INIT_WORK(&adapter
->multispeed_fiber_task
, ixgbe_multispeed_fiber_task
);
6826 /* a new SFP+ module arrival, called from GPI SDP2 context */
6827 INIT_WORK(&adapter
->sfp_config_module_task
,
6828 ixgbe_sfp_config_module_task
);
6830 ii
->get_invariants(hw
);
6832 /* setup the private structure */
6833 err
= ixgbe_sw_init(adapter
);
6837 /* Make it possible the adapter to be woken up via WOL */
6838 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
6839 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
6842 * If there is a fan on this device and it has failed log the
6845 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
6846 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
6847 if (esdp
& IXGBE_ESDP_SDP1
)
6848 e_crit(probe
, "Fan has stopped, replace the adapter\n");
6851 /* reset_hw fills in the perm_addr as well */
6852 hw
->phy
.reset_if_overtemp
= true;
6853 err
= hw
->mac
.ops
.reset_hw(hw
);
6854 hw
->phy
.reset_if_overtemp
= false;
6855 if (err
== IXGBE_ERR_SFP_NOT_PRESENT
&&
6856 hw
->mac
.type
== ixgbe_mac_82598EB
) {
6858 * Start a kernel thread to watch for a module to arrive.
6859 * Only do this for 82598, since 82599 will generate
6860 * interrupts on module arrival.
6862 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
6863 mod_timer(&adapter
->sfp_timer
,
6864 round_jiffies(jiffies
+ (2 * HZ
)));
6866 } else if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
6867 e_dev_err("failed to initialize because an unsupported SFP+ "
6868 "module type was detected.\n");
6869 e_dev_err("Reload the driver after installing a supported "
6873 e_dev_err("HW Init failed: %d\n", err
);
6877 ixgbe_probe_vf(adapter
, ii
);
6879 netdev
->features
= NETIF_F_SG
|
6881 NETIF_F_HW_VLAN_TX
|
6882 NETIF_F_HW_VLAN_RX
|
6883 NETIF_F_HW_VLAN_FILTER
;
6885 netdev
->features
|= NETIF_F_IPV6_CSUM
;
6886 netdev
->features
|= NETIF_F_TSO
;
6887 netdev
->features
|= NETIF_F_TSO6
;
6888 netdev
->features
|= NETIF_F_GRO
;
6890 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
6891 netdev
->features
|= NETIF_F_SCTP_CSUM
;
6893 netdev
->vlan_features
|= NETIF_F_TSO
;
6894 netdev
->vlan_features
|= NETIF_F_TSO6
;
6895 netdev
->vlan_features
|= NETIF_F_IP_CSUM
;
6896 netdev
->vlan_features
|= NETIF_F_IPV6_CSUM
;
6897 netdev
->vlan_features
|= NETIF_F_SG
;
6899 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
6900 adapter
->flags
&= ~(IXGBE_FLAG_RSS_ENABLED
|
6901 IXGBE_FLAG_DCB_ENABLED
);
6902 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)
6903 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
6905 #ifdef CONFIG_IXGBE_DCB
6906 netdev
->dcbnl_ops
= &dcbnl_ops
;
6910 if (adapter
->flags
& IXGBE_FLAG_FCOE_CAPABLE
) {
6911 if (hw
->mac
.ops
.get_device_caps
) {
6912 hw
->mac
.ops
.get_device_caps(hw
, &device_caps
);
6913 if (device_caps
& IXGBE_DEVICE_CAPS_FCOE_OFFLOADS
)
6914 adapter
->flags
&= ~IXGBE_FLAG_FCOE_CAPABLE
;
6917 if (adapter
->flags
& IXGBE_FLAG_FCOE_CAPABLE
) {
6918 netdev
->vlan_features
|= NETIF_F_FCOE_CRC
;
6919 netdev
->vlan_features
|= NETIF_F_FSO
;
6920 netdev
->vlan_features
|= NETIF_F_FCOE_MTU
;
6922 #endif /* IXGBE_FCOE */
6923 if (pci_using_dac
) {
6924 netdev
->features
|= NETIF_F_HIGHDMA
;
6925 netdev
->vlan_features
|= NETIF_F_HIGHDMA
;
6928 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
)
6929 netdev
->features
|= NETIF_F_LRO
;
6931 /* make sure the EEPROM is good */
6932 if (hw
->eeprom
.ops
.validate_checksum(hw
, NULL
) < 0) {
6933 e_dev_err("The EEPROM Checksum Is Not Valid\n");
6938 memcpy(netdev
->dev_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
6939 memcpy(netdev
->perm_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
6941 if (ixgbe_validate_mac_addr(netdev
->perm_addr
)) {
6942 e_dev_err("invalid MAC address\n");
6947 /* power down the optics */
6948 if (hw
->phy
.multispeed_fiber
)
6949 hw
->mac
.ops
.disable_tx_laser(hw
);
6951 init_timer(&adapter
->watchdog_timer
);
6952 adapter
->watchdog_timer
.function
= ixgbe_watchdog
;
6953 adapter
->watchdog_timer
.data
= (unsigned long)adapter
;
6955 INIT_WORK(&adapter
->reset_task
, ixgbe_reset_task
);
6956 INIT_WORK(&adapter
->watchdog_task
, ixgbe_watchdog_task
);
6958 err
= ixgbe_init_interrupt_scheme(adapter
);
6962 switch (pdev
->device
) {
6963 case IXGBE_DEV_ID_82599_KX4
:
6964 adapter
->wol
= (IXGBE_WUFC_MAG
| IXGBE_WUFC_EX
|
6965 IXGBE_WUFC_MC
| IXGBE_WUFC_BC
);
6971 device_set_wakeup_enable(&adapter
->pdev
->dev
, adapter
->wol
);
6973 /* pick up the PCI bus settings for reporting later */
6974 hw
->mac
.ops
.get_bus_info(hw
);
6976 /* print bus type/speed/width info */
6977 e_dev_info("(PCI Express:%s:%s) %pM\n",
6978 (hw
->bus
.speed
== ixgbe_bus_speed_5000
? "5.0Gb/s" :
6979 hw
->bus
.speed
== ixgbe_bus_speed_2500
? "2.5Gb/s" :
6981 (hw
->bus
.width
== ixgbe_bus_width_pcie_x8
? "Width x8" :
6982 hw
->bus
.width
== ixgbe_bus_width_pcie_x4
? "Width x4" :
6983 hw
->bus
.width
== ixgbe_bus_width_pcie_x1
? "Width x1" :
6986 ixgbe_read_pba_num_generic(hw
, &part_num
);
6987 if (ixgbe_is_sfp(hw
) && hw
->phy
.sfp_type
!= ixgbe_sfp_type_not_present
)
6988 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
6989 "PBA No: %06x-%03x\n",
6990 hw
->mac
.type
, hw
->phy
.type
, hw
->phy
.sfp_type
,
6991 (part_num
>> 8), (part_num
& 0xff));
6993 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6994 hw
->mac
.type
, hw
->phy
.type
,
6995 (part_num
>> 8), (part_num
& 0xff));
6997 if (hw
->bus
.width
<= ixgbe_bus_width_pcie_x4
) {
6998 e_dev_warn("PCI-Express bandwidth available for this card is "
6999 "not sufficient for optimal performance.\n");
7000 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7004 /* save off EEPROM version number */
7005 hw
->eeprom
.ops
.read(hw
, 0x29, &adapter
->eeprom_version
);
7007 /* reset the hardware with the new settings */
7008 err
= hw
->mac
.ops
.start_hw(hw
);
7010 if (err
== IXGBE_ERR_EEPROM_VERSION
) {
7011 /* We are running on a pre-production device, log a warning */
7012 e_dev_warn("This device is a pre-production adapter/LOM. "
7013 "Please be aware there may be issues associated "
7014 "with your hardware. If you are experiencing "
7015 "problems please contact your Intel or hardware "
7016 "representative who provided you with this "
7019 strcpy(netdev
->name
, "eth%d");
7020 err
= register_netdev(netdev
);
7024 /* carrier off reporting is important to ethtool even BEFORE open */
7025 netif_carrier_off(netdev
);
7027 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
7028 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
7029 INIT_WORK(&adapter
->fdir_reinit_task
, ixgbe_fdir_reinit_task
);
7031 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
)
7032 INIT_WORK(&adapter
->check_overtemp_task
,
7033 ixgbe_check_overtemp_task
);
7034 #ifdef CONFIG_IXGBE_DCA
7035 if (dca_add_requester(&pdev
->dev
) == 0) {
7036 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
7037 ixgbe_setup_dca(adapter
);
7040 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
7041 e_info(probe
, "IOV is enabled with %d VFs\n", adapter
->num_vfs
);
7042 for (i
= 0; i
< adapter
->num_vfs
; i
++)
7043 ixgbe_vf_configuration(pdev
, (i
| 0x10000000));
7046 /* add san mac addr to netdev */
7047 ixgbe_add_sanmac_netdev(netdev
);
7049 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7054 ixgbe_release_hw_control(adapter
);
7055 ixgbe_clear_interrupt_scheme(adapter
);
7058 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
7059 ixgbe_disable_sriov(adapter
);
7060 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
7061 del_timer_sync(&adapter
->sfp_timer
);
7062 cancel_work_sync(&adapter
->sfp_task
);
7063 cancel_work_sync(&adapter
->multispeed_fiber_task
);
7064 cancel_work_sync(&adapter
->sfp_config_module_task
);
7065 iounmap(hw
->hw_addr
);
7067 free_netdev(netdev
);
7069 pci_release_selected_regions(pdev
,
7070 pci_select_bars(pdev
, IORESOURCE_MEM
));
7073 pci_disable_device(pdev
);
7078 * ixgbe_remove - Device Removal Routine
7079 * @pdev: PCI device information struct
7081 * ixgbe_remove is called by the PCI subsystem to alert the driver
7082 * that it should release a PCI device. The could be caused by a
7083 * Hot-Plug event, or because the driver is going to be removed from
7086 static void __devexit
ixgbe_remove(struct pci_dev
*pdev
)
7088 struct net_device
*netdev
= pci_get_drvdata(pdev
);
7089 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
7091 set_bit(__IXGBE_DOWN
, &adapter
->state
);
7092 /* clear the module not found bit to make sure the worker won't
7095 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
7096 del_timer_sync(&adapter
->watchdog_timer
);
7098 del_timer_sync(&adapter
->sfp_timer
);
7099 cancel_work_sync(&adapter
->watchdog_task
);
7100 cancel_work_sync(&adapter
->sfp_task
);
7101 cancel_work_sync(&adapter
->multispeed_fiber_task
);
7102 cancel_work_sync(&adapter
->sfp_config_module_task
);
7103 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
7104 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
7105 cancel_work_sync(&adapter
->fdir_reinit_task
);
7106 flush_scheduled_work();
7108 #ifdef CONFIG_IXGBE_DCA
7109 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
7110 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
7111 dca_remove_requester(&pdev
->dev
);
7112 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
7117 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
7118 ixgbe_cleanup_fcoe(adapter
);
7120 #endif /* IXGBE_FCOE */
7122 /* remove the added san mac */
7123 ixgbe_del_sanmac_netdev(netdev
);
7125 if (netdev
->reg_state
== NETREG_REGISTERED
)
7126 unregister_netdev(netdev
);
7128 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
7129 ixgbe_disable_sriov(adapter
);
7131 ixgbe_clear_interrupt_scheme(adapter
);
7133 ixgbe_release_hw_control(adapter
);
7135 iounmap(adapter
->hw
.hw_addr
);
7136 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
7139 e_dev_info("complete\n");
7141 free_netdev(netdev
);
7143 pci_disable_pcie_error_reporting(pdev
);
7145 pci_disable_device(pdev
);
7149 * ixgbe_io_error_detected - called when PCI error is detected
7150 * @pdev: Pointer to PCI device
7151 * @state: The current pci connection state
7153 * This function is called after a PCI bus error affecting
7154 * this device has been detected.
7156 static pci_ers_result_t
ixgbe_io_error_detected(struct pci_dev
*pdev
,
7157 pci_channel_state_t state
)
7159 struct net_device
*netdev
= pci_get_drvdata(pdev
);
7160 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
7162 netif_device_detach(netdev
);
7164 if (state
== pci_channel_io_perm_failure
)
7165 return PCI_ERS_RESULT_DISCONNECT
;
7167 if (netif_running(netdev
))
7168 ixgbe_down(adapter
);
7169 pci_disable_device(pdev
);
7171 /* Request a slot reset. */
7172 return PCI_ERS_RESULT_NEED_RESET
;
7176 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7177 * @pdev: Pointer to PCI device
7179 * Restart the card from scratch, as if from a cold-boot.
7181 static pci_ers_result_t
ixgbe_io_slot_reset(struct pci_dev
*pdev
)
7183 struct net_device
*netdev
= pci_get_drvdata(pdev
);
7184 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
7185 pci_ers_result_t result
;
7188 if (pci_enable_device_mem(pdev
)) {
7189 e_err(probe
, "Cannot re-enable PCI device after reset.\n");
7190 result
= PCI_ERS_RESULT_DISCONNECT
;
7192 pci_set_master(pdev
);
7193 pci_restore_state(pdev
);
7194 pci_save_state(pdev
);
7196 pci_wake_from_d3(pdev
, false);
7198 ixgbe_reset(adapter
);
7199 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
7200 result
= PCI_ERS_RESULT_RECOVERED
;
7203 err
= pci_cleanup_aer_uncorrect_error_status(pdev
);
7205 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7206 "failed 0x%0x\n", err
);
7207 /* non-fatal, continue */
7214 * ixgbe_io_resume - called when traffic can start flowing again.
7215 * @pdev: Pointer to PCI device
7217 * This callback is called when the error recovery driver tells us that
7218 * its OK to resume normal operation.
7220 static void ixgbe_io_resume(struct pci_dev
*pdev
)
7222 struct net_device
*netdev
= pci_get_drvdata(pdev
);
7223 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
7225 if (netif_running(netdev
)) {
7226 if (ixgbe_up(adapter
)) {
7227 e_info(probe
, "ixgbe_up failed after reset\n");
7232 netif_device_attach(netdev
);
7235 static struct pci_error_handlers ixgbe_err_handler
= {
7236 .error_detected
= ixgbe_io_error_detected
,
7237 .slot_reset
= ixgbe_io_slot_reset
,
7238 .resume
= ixgbe_io_resume
,
7241 static struct pci_driver ixgbe_driver
= {
7242 .name
= ixgbe_driver_name
,
7243 .id_table
= ixgbe_pci_tbl
,
7244 .probe
= ixgbe_probe
,
7245 .remove
= __devexit_p(ixgbe_remove
),
7247 .suspend
= ixgbe_suspend
,
7248 .resume
= ixgbe_resume
,
7250 .shutdown
= ixgbe_shutdown
,
7251 .err_handler
= &ixgbe_err_handler
7255 * ixgbe_init_module - Driver Registration Routine
7257 * ixgbe_init_module is the first routine called when the driver is
7258 * loaded. All it does is register with the PCI subsystem.
7260 static int __init
ixgbe_init_module(void)
7263 pr_info("%s - version %s\n", ixgbe_driver_string
, ixgbe_driver_version
);
7264 pr_info("%s\n", ixgbe_copyright
);
7266 #ifdef CONFIG_IXGBE_DCA
7267 dca_register_notify(&dca_notifier
);
7270 ret
= pci_register_driver(&ixgbe_driver
);
7274 module_init(ixgbe_init_module
);
7277 * ixgbe_exit_module - Driver Exit Cleanup Routine
7279 * ixgbe_exit_module is called just before the driver is removed
7282 static void __exit
ixgbe_exit_module(void)
7284 #ifdef CONFIG_IXGBE_DCA
7285 dca_unregister_notify(&dca_notifier
);
7287 pci_unregister_driver(&ixgbe_driver
);
7290 #ifdef CONFIG_IXGBE_DCA
7291 static int ixgbe_notify_dca(struct notifier_block
*nb
, unsigned long event
,
7296 ret_val
= driver_for_each_device(&ixgbe_driver
.driver
, NULL
, &event
,
7297 __ixgbe_notify_dca
);
7299 return ret_val
? NOTIFY_BAD
: NOTIFY_DONE
;
7302 #endif /* CONFIG_IXGBE_DCA */
7305 * ixgbe_get_hw_dev return device
7306 * used by hardware layer to print debugging information
7308 struct net_device
*ixgbe_get_hw_dev(struct ixgbe_hw
*hw
)
7310 struct ixgbe_adapter
*adapter
= hw
->back
;
7311 return adapter
->netdev
;
7314 module_exit(ixgbe_exit_module
);