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[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <linux/slab.h>
40 #include <net/checksum.h>
41 #include <net/ip6_checksum.h>
42 #include <linux/ethtool.h>
43 #include <linux/if_vlan.h>
44 #include <scsi/fc/fc_fcoe.h>
45
46 #include "ixgbe.h"
47 #include "ixgbe_common.h"
48 #include "ixgbe_dcb_82599.h"
49 #include "ixgbe_sriov.h"
50
51 char ixgbe_driver_name[] = "ixgbe";
52 static const char ixgbe_driver_string[] =
53 "Intel(R) 10 Gigabit PCI Express Network Driver";
54
55 #define DRV_VERSION "3.2.9-k2"
56 const char ixgbe_driver_version[] = DRV_VERSION;
57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
58
59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
60 [board_82598] = &ixgbe_82598_info,
61 [board_82599] = &ixgbe_82599_info,
62 [board_X540] = &ixgbe_X540_info,
63 };
64
65 /* ixgbe_pci_tbl - PCI Device ID Table
66 *
67 * Wildcard entries (PCI_ANY_ID) should come last
68 * Last entry must be all 0s
69 *
70 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
71 * Class, Class Mask, private data (not used) }
72 */
73 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
75 board_82598 },
76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
77 board_82598 },
78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
79 board_82598 },
80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
81 board_82598 },
82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
83 board_82598 },
84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
85 board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
87 board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
89 board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
91 board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
93 board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
95 board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
97 board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
99 board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
101 board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
103 board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
105 board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
107 board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
109 board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
111 board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
113 board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
115 board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
117 board_82599 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
119 board_82599 },
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
121 board_X540 },
122
123 /* required last entry */
124 {0, }
125 };
126 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
127
128 #ifdef CONFIG_IXGBE_DCA
129 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
130 void *p);
131 static struct notifier_block dca_notifier = {
132 .notifier_call = ixgbe_notify_dca,
133 .next = NULL,
134 .priority = 0
135 };
136 #endif
137
138 #ifdef CONFIG_PCI_IOV
139 static unsigned int max_vfs;
140 module_param(max_vfs, uint, 0);
141 MODULE_PARM_DESC(max_vfs,
142 "Maximum number of virtual functions to allocate per physical function");
143 #endif /* CONFIG_PCI_IOV */
144
145 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
146 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
147 MODULE_LICENSE("GPL");
148 MODULE_VERSION(DRV_VERSION);
149
150 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
151
152 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
153 {
154 struct ixgbe_hw *hw = &adapter->hw;
155 u32 gcr;
156 u32 gpie;
157 u32 vmdctl;
158
159 #ifdef CONFIG_PCI_IOV
160 /* disable iov and allow time for transactions to clear */
161 pci_disable_sriov(adapter->pdev);
162 #endif
163
164 /* turn off device IOV mode */
165 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
166 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
167 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
168 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
169 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
170 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
171
172 /* set default pool back to 0 */
173 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
174 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
175 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
176
177 /* take a breather then clean up driver data */
178 msleep(100);
179
180 kfree(adapter->vfinfo);
181 adapter->vfinfo = NULL;
182
183 adapter->num_vfs = 0;
184 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
185 }
186
187 struct ixgbe_reg_info {
188 u32 ofs;
189 char *name;
190 };
191
192 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
193
194 /* General Registers */
195 {IXGBE_CTRL, "CTRL"},
196 {IXGBE_STATUS, "STATUS"},
197 {IXGBE_CTRL_EXT, "CTRL_EXT"},
198
199 /* Interrupt Registers */
200 {IXGBE_EICR, "EICR"},
201
202 /* RX Registers */
203 {IXGBE_SRRCTL(0), "SRRCTL"},
204 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
205 {IXGBE_RDLEN(0), "RDLEN"},
206 {IXGBE_RDH(0), "RDH"},
207 {IXGBE_RDT(0), "RDT"},
208 {IXGBE_RXDCTL(0), "RXDCTL"},
209 {IXGBE_RDBAL(0), "RDBAL"},
210 {IXGBE_RDBAH(0), "RDBAH"},
211
212 /* TX Registers */
213 {IXGBE_TDBAL(0), "TDBAL"},
214 {IXGBE_TDBAH(0), "TDBAH"},
215 {IXGBE_TDLEN(0), "TDLEN"},
216 {IXGBE_TDH(0), "TDH"},
217 {IXGBE_TDT(0), "TDT"},
218 {IXGBE_TXDCTL(0), "TXDCTL"},
219
220 /* List Terminator */
221 {}
222 };
223
224
225 /*
226 * ixgbe_regdump - register printout routine
227 */
228 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
229 {
230 int i = 0, j = 0;
231 char rname[16];
232 u32 regs[64];
233
234 switch (reginfo->ofs) {
235 case IXGBE_SRRCTL(0):
236 for (i = 0; i < 64; i++)
237 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
238 break;
239 case IXGBE_DCA_RXCTRL(0):
240 for (i = 0; i < 64; i++)
241 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
242 break;
243 case IXGBE_RDLEN(0):
244 for (i = 0; i < 64; i++)
245 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
246 break;
247 case IXGBE_RDH(0):
248 for (i = 0; i < 64; i++)
249 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
250 break;
251 case IXGBE_RDT(0):
252 for (i = 0; i < 64; i++)
253 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
254 break;
255 case IXGBE_RXDCTL(0):
256 for (i = 0; i < 64; i++)
257 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
258 break;
259 case IXGBE_RDBAL(0):
260 for (i = 0; i < 64; i++)
261 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
262 break;
263 case IXGBE_RDBAH(0):
264 for (i = 0; i < 64; i++)
265 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
266 break;
267 case IXGBE_TDBAL(0):
268 for (i = 0; i < 64; i++)
269 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
270 break;
271 case IXGBE_TDBAH(0):
272 for (i = 0; i < 64; i++)
273 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
274 break;
275 case IXGBE_TDLEN(0):
276 for (i = 0; i < 64; i++)
277 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
278 break;
279 case IXGBE_TDH(0):
280 for (i = 0; i < 64; i++)
281 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
282 break;
283 case IXGBE_TDT(0):
284 for (i = 0; i < 64; i++)
285 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
286 break;
287 case IXGBE_TXDCTL(0):
288 for (i = 0; i < 64; i++)
289 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
290 break;
291 default:
292 pr_info("%-15s %08x\n", reginfo->name,
293 IXGBE_READ_REG(hw, reginfo->ofs));
294 return;
295 }
296
297 for (i = 0; i < 8; i++) {
298 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
299 pr_err("%-15s", rname);
300 for (j = 0; j < 8; j++)
301 pr_cont(" %08x", regs[i*8+j]);
302 pr_cont("\n");
303 }
304
305 }
306
307 /*
308 * ixgbe_dump - Print registers, tx-rings and rx-rings
309 */
310 static void ixgbe_dump(struct ixgbe_adapter *adapter)
311 {
312 struct net_device *netdev = adapter->netdev;
313 struct ixgbe_hw *hw = &adapter->hw;
314 struct ixgbe_reg_info *reginfo;
315 int n = 0;
316 struct ixgbe_ring *tx_ring;
317 struct ixgbe_tx_buffer *tx_buffer_info;
318 union ixgbe_adv_tx_desc *tx_desc;
319 struct my_u0 { u64 a; u64 b; } *u0;
320 struct ixgbe_ring *rx_ring;
321 union ixgbe_adv_rx_desc *rx_desc;
322 struct ixgbe_rx_buffer *rx_buffer_info;
323 u32 staterr;
324 int i = 0;
325
326 if (!netif_msg_hw(adapter))
327 return;
328
329 /* Print netdevice Info */
330 if (netdev) {
331 dev_info(&adapter->pdev->dev, "Net device Info\n");
332 pr_info("Device Name state "
333 "trans_start last_rx\n");
334 pr_info("%-15s %016lX %016lX %016lX\n",
335 netdev->name,
336 netdev->state,
337 netdev->trans_start,
338 netdev->last_rx);
339 }
340
341 /* Print Registers */
342 dev_info(&adapter->pdev->dev, "Register Dump\n");
343 pr_info(" Register Name Value\n");
344 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
345 reginfo->name; reginfo++) {
346 ixgbe_regdump(hw, reginfo);
347 }
348
349 /* Print TX Ring Summary */
350 if (!netdev || !netif_running(netdev))
351 goto exit;
352
353 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
354 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
355 for (n = 0; n < adapter->num_tx_queues; n++) {
356 tx_ring = adapter->tx_ring[n];
357 tx_buffer_info =
358 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
359 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
360 n, tx_ring->next_to_use, tx_ring->next_to_clean,
361 (u64)tx_buffer_info->dma,
362 tx_buffer_info->length,
363 tx_buffer_info->next_to_watch,
364 (u64)tx_buffer_info->time_stamp);
365 }
366
367 /* Print TX Rings */
368 if (!netif_msg_tx_done(adapter))
369 goto rx_ring_summary;
370
371 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
372
373 /* Transmit Descriptor Formats
374 *
375 * Advanced Transmit Descriptor
376 * +--------------------------------------------------------------+
377 * 0 | Buffer Address [63:0] |
378 * +--------------------------------------------------------------+
379 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
380 * +--------------------------------------------------------------+
381 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
382 */
383
384 for (n = 0; n < adapter->num_tx_queues; n++) {
385 tx_ring = adapter->tx_ring[n];
386 pr_info("------------------------------------\n");
387 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
388 pr_info("------------------------------------\n");
389 pr_info("T [desc] [address 63:0 ] "
390 "[PlPOIdStDDt Ln] [bi->dma ] "
391 "leng ntw timestamp bi->skb\n");
392
393 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
394 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
395 tx_buffer_info = &tx_ring->tx_buffer_info[i];
396 u0 = (struct my_u0 *)tx_desc;
397 pr_info("T [0x%03X] %016llX %016llX %016llX"
398 " %04X %3X %016llX %p", i,
399 le64_to_cpu(u0->a),
400 le64_to_cpu(u0->b),
401 (u64)tx_buffer_info->dma,
402 tx_buffer_info->length,
403 tx_buffer_info->next_to_watch,
404 (u64)tx_buffer_info->time_stamp,
405 tx_buffer_info->skb);
406 if (i == tx_ring->next_to_use &&
407 i == tx_ring->next_to_clean)
408 pr_cont(" NTC/U\n");
409 else if (i == tx_ring->next_to_use)
410 pr_cont(" NTU\n");
411 else if (i == tx_ring->next_to_clean)
412 pr_cont(" NTC\n");
413 else
414 pr_cont("\n");
415
416 if (netif_msg_pktdata(adapter) &&
417 tx_buffer_info->dma != 0)
418 print_hex_dump(KERN_INFO, "",
419 DUMP_PREFIX_ADDRESS, 16, 1,
420 phys_to_virt(tx_buffer_info->dma),
421 tx_buffer_info->length, true);
422 }
423 }
424
425 /* Print RX Rings Summary */
426 rx_ring_summary:
427 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
428 pr_info("Queue [NTU] [NTC]\n");
429 for (n = 0; n < adapter->num_rx_queues; n++) {
430 rx_ring = adapter->rx_ring[n];
431 pr_info("%5d %5X %5X\n",
432 n, rx_ring->next_to_use, rx_ring->next_to_clean);
433 }
434
435 /* Print RX Rings */
436 if (!netif_msg_rx_status(adapter))
437 goto exit;
438
439 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
440
441 /* Advanced Receive Descriptor (Read) Format
442 * 63 1 0
443 * +-----------------------------------------------------+
444 * 0 | Packet Buffer Address [63:1] |A0/NSE|
445 * +----------------------------------------------+------+
446 * 8 | Header Buffer Address [63:1] | DD |
447 * +-----------------------------------------------------+
448 *
449 *
450 * Advanced Receive Descriptor (Write-Back) Format
451 *
452 * 63 48 47 32 31 30 21 20 16 15 4 3 0
453 * +------------------------------------------------------+
454 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
455 * | Checksum Ident | | | | Type | Type |
456 * +------------------------------------------------------+
457 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
458 * +------------------------------------------------------+
459 * 63 48 47 32 31 20 19 0
460 */
461 for (n = 0; n < adapter->num_rx_queues; n++) {
462 rx_ring = adapter->rx_ring[n];
463 pr_info("------------------------------------\n");
464 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
465 pr_info("------------------------------------\n");
466 pr_info("R [desc] [ PktBuf A0] "
467 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
468 "<-- Adv Rx Read format\n");
469 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
470 "[vl er S cks ln] ---------------- [bi->skb] "
471 "<-- Adv Rx Write-Back format\n");
472
473 for (i = 0; i < rx_ring->count; i++) {
474 rx_buffer_info = &rx_ring->rx_buffer_info[i];
475 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
476 u0 = (struct my_u0 *)rx_desc;
477 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
478 if (staterr & IXGBE_RXD_STAT_DD) {
479 /* Descriptor Done */
480 pr_info("RWB[0x%03X] %016llX "
481 "%016llX ---------------- %p", i,
482 le64_to_cpu(u0->a),
483 le64_to_cpu(u0->b),
484 rx_buffer_info->skb);
485 } else {
486 pr_info("R [0x%03X] %016llX "
487 "%016llX %016llX %p", i,
488 le64_to_cpu(u0->a),
489 le64_to_cpu(u0->b),
490 (u64)rx_buffer_info->dma,
491 rx_buffer_info->skb);
492
493 if (netif_msg_pktdata(adapter)) {
494 print_hex_dump(KERN_INFO, "",
495 DUMP_PREFIX_ADDRESS, 16, 1,
496 phys_to_virt(rx_buffer_info->dma),
497 rx_ring->rx_buf_len, true);
498
499 if (rx_ring->rx_buf_len
500 < IXGBE_RXBUFFER_2048)
501 print_hex_dump(KERN_INFO, "",
502 DUMP_PREFIX_ADDRESS, 16, 1,
503 phys_to_virt(
504 rx_buffer_info->page_dma +
505 rx_buffer_info->page_offset
506 ),
507 PAGE_SIZE/2, true);
508 }
509 }
510
511 if (i == rx_ring->next_to_use)
512 pr_cont(" NTU\n");
513 else if (i == rx_ring->next_to_clean)
514 pr_cont(" NTC\n");
515 else
516 pr_cont("\n");
517
518 }
519 }
520
521 exit:
522 return;
523 }
524
525 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
526 {
527 u32 ctrl_ext;
528
529 /* Let firmware take over control of h/w */
530 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
531 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
532 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
533 }
534
535 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
536 {
537 u32 ctrl_ext;
538
539 /* Let firmware know the driver has taken over */
540 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
541 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
542 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
543 }
544
545 /*
546 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
547 * @adapter: pointer to adapter struct
548 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
549 * @queue: queue to map the corresponding interrupt to
550 * @msix_vector: the vector to map to the corresponding queue
551 *
552 */
553 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
554 u8 queue, u8 msix_vector)
555 {
556 u32 ivar, index;
557 struct ixgbe_hw *hw = &adapter->hw;
558 switch (hw->mac.type) {
559 case ixgbe_mac_82598EB:
560 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
561 if (direction == -1)
562 direction = 0;
563 index = (((direction * 64) + queue) >> 2) & 0x1F;
564 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
565 ivar &= ~(0xFF << (8 * (queue & 0x3)));
566 ivar |= (msix_vector << (8 * (queue & 0x3)));
567 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
568 break;
569 case ixgbe_mac_82599EB:
570 case ixgbe_mac_X540:
571 if (direction == -1) {
572 /* other causes */
573 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
574 index = ((queue & 1) * 8);
575 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
576 ivar &= ~(0xFF << index);
577 ivar |= (msix_vector << index);
578 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
579 break;
580 } else {
581 /* tx or rx causes */
582 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
583 index = ((16 * (queue & 1)) + (8 * direction));
584 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
585 ivar &= ~(0xFF << index);
586 ivar |= (msix_vector << index);
587 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
588 break;
589 }
590 default:
591 break;
592 }
593 }
594
595 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
596 u64 qmask)
597 {
598 u32 mask;
599
600 switch (adapter->hw.mac.type) {
601 case ixgbe_mac_82598EB:
602 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
603 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
604 break;
605 case ixgbe_mac_82599EB:
606 case ixgbe_mac_X540:
607 mask = (qmask & 0xFFFFFFFF);
608 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
609 mask = (qmask >> 32);
610 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
611 break;
612 default:
613 break;
614 }
615 }
616
617 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
618 struct ixgbe_tx_buffer *tx_buffer_info)
619 {
620 if (tx_buffer_info->dma) {
621 if (tx_buffer_info->mapped_as_page)
622 dma_unmap_page(tx_ring->dev,
623 tx_buffer_info->dma,
624 tx_buffer_info->length,
625 DMA_TO_DEVICE);
626 else
627 dma_unmap_single(tx_ring->dev,
628 tx_buffer_info->dma,
629 tx_buffer_info->length,
630 DMA_TO_DEVICE);
631 tx_buffer_info->dma = 0;
632 }
633 if (tx_buffer_info->skb) {
634 dev_kfree_skb_any(tx_buffer_info->skb);
635 tx_buffer_info->skb = NULL;
636 }
637 tx_buffer_info->time_stamp = 0;
638 /* tx_buffer_info must be completely set up in the transmit path */
639 }
640
641 /**
642 * ixgbe_dcb_txq_to_tc - convert a reg index to a traffic class
643 * @adapter: driver private struct
644 * @index: reg idx of queue to query (0-127)
645 *
646 * Helper function to determine the traffic index for a paticular
647 * register index.
648 *
649 * Returns : a tc index for use in range 0-7, or 0-3
650 */
651 static u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx)
652 {
653 int tc = -1;
654 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
655
656 /* if DCB is not enabled the queues have no TC */
657 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
658 return tc;
659
660 /* check valid range */
661 if (reg_idx >= adapter->hw.mac.max_tx_queues)
662 return tc;
663
664 switch (adapter->hw.mac.type) {
665 case ixgbe_mac_82598EB:
666 tc = reg_idx >> 2;
667 break;
668 default:
669 if (dcb_i != 4 && dcb_i != 8)
670 break;
671
672 /* if VMDq is enabled the lowest order bits determine TC */
673 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
674 IXGBE_FLAG_VMDQ_ENABLED)) {
675 tc = reg_idx & (dcb_i - 1);
676 break;
677 }
678
679 /*
680 * Convert the reg_idx into the correct TC. This bitmask
681 * targets the last full 32 ring traffic class and assigns
682 * it a value of 1. From there the rest of the rings are
683 * based on shifting the mask further up to include the
684 * reg_idx / 16 and then reg_idx / 8. It assumes dcB_i
685 * will only ever be 8 or 4 and that reg_idx will never
686 * be greater then 128. The code without the power of 2
687 * optimizations would be:
688 * (((reg_idx % 32) + 32) * dcb_i) >> (9 - reg_idx / 32)
689 */
690 tc = ((reg_idx & 0X1F) + 0x20) * dcb_i;
691 tc >>= 9 - (reg_idx >> 5);
692 }
693
694 return tc;
695 }
696
697 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
698 {
699 struct ixgbe_hw *hw = &adapter->hw;
700 struct ixgbe_hw_stats *hwstats = &adapter->stats;
701 u32 data = 0;
702 u32 xoff[8] = {0};
703 int i;
704
705 if ((hw->fc.current_mode == ixgbe_fc_full) ||
706 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
707 switch (hw->mac.type) {
708 case ixgbe_mac_82598EB:
709 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
710 break;
711 default:
712 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
713 }
714 hwstats->lxoffrxc += data;
715
716 /* refill credits (no tx hang) if we received xoff */
717 if (!data)
718 return;
719
720 for (i = 0; i < adapter->num_tx_queues; i++)
721 clear_bit(__IXGBE_HANG_CHECK_ARMED,
722 &adapter->tx_ring[i]->state);
723 return;
724 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
725 return;
726
727 /* update stats for each tc, only valid with PFC enabled */
728 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
729 switch (hw->mac.type) {
730 case ixgbe_mac_82598EB:
731 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
732 break;
733 default:
734 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
735 }
736 hwstats->pxoffrxc[i] += xoff[i];
737 }
738
739 /* disarm tx queues that have received xoff frames */
740 for (i = 0; i < adapter->num_tx_queues; i++) {
741 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
742 u32 tc = ixgbe_dcb_txq_to_tc(adapter, tx_ring->reg_idx);
743
744 if (xoff[tc])
745 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
746 }
747 }
748
749 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
750 {
751 return ring->tx_stats.completed;
752 }
753
754 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
755 {
756 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
757 struct ixgbe_hw *hw = &adapter->hw;
758
759 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
760 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
761
762 if (head != tail)
763 return (head < tail) ?
764 tail - head : (tail + ring->count - head);
765
766 return 0;
767 }
768
769 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
770 {
771 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
772 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
773 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
774 bool ret = false;
775
776 clear_check_for_tx_hang(tx_ring);
777
778 /*
779 * Check for a hung queue, but be thorough. This verifies
780 * that a transmit has been completed since the previous
781 * check AND there is at least one packet pending. The
782 * ARMED bit is set to indicate a potential hang. The
783 * bit is cleared if a pause frame is received to remove
784 * false hang detection due to PFC or 802.3x frames. By
785 * requiring this to fail twice we avoid races with
786 * pfc clearing the ARMED bit and conditions where we
787 * run the check_tx_hang logic with a transmit completion
788 * pending but without time to complete it yet.
789 */
790 if ((tx_done_old == tx_done) && tx_pending) {
791 /* make sure it is true for two checks in a row */
792 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
793 &tx_ring->state);
794 } else {
795 /* update completed stats and continue */
796 tx_ring->tx_stats.tx_done_old = tx_done;
797 /* reset the countdown */
798 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
799 }
800
801 return ret;
802 }
803
804 #define IXGBE_MAX_TXD_PWR 14
805 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
806
807 /* Tx Descriptors needed, worst case */
808 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
809 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
810 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
811 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
812
813 static void ixgbe_tx_timeout(struct net_device *netdev);
814
815 /**
816 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
817 * @q_vector: structure containing interrupt and ring information
818 * @tx_ring: tx ring to clean
819 **/
820 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
821 struct ixgbe_ring *tx_ring)
822 {
823 struct ixgbe_adapter *adapter = q_vector->adapter;
824 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
825 struct ixgbe_tx_buffer *tx_buffer_info;
826 unsigned int total_bytes = 0, total_packets = 0;
827 u16 i, eop, count = 0;
828
829 i = tx_ring->next_to_clean;
830 eop = tx_ring->tx_buffer_info[i].next_to_watch;
831 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
832
833 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
834 (count < tx_ring->work_limit)) {
835 bool cleaned = false;
836 rmb(); /* read buffer_info after eop_desc */
837 for ( ; !cleaned; count++) {
838 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
839 tx_buffer_info = &tx_ring->tx_buffer_info[i];
840
841 tx_desc->wb.status = 0;
842 cleaned = (i == eop);
843
844 i++;
845 if (i == tx_ring->count)
846 i = 0;
847
848 if (cleaned && tx_buffer_info->skb) {
849 total_bytes += tx_buffer_info->bytecount;
850 total_packets += tx_buffer_info->gso_segs;
851 }
852
853 ixgbe_unmap_and_free_tx_resource(tx_ring,
854 tx_buffer_info);
855 }
856
857 tx_ring->tx_stats.completed++;
858 eop = tx_ring->tx_buffer_info[i].next_to_watch;
859 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
860 }
861
862 tx_ring->next_to_clean = i;
863 tx_ring->total_bytes += total_bytes;
864 tx_ring->total_packets += total_packets;
865 u64_stats_update_begin(&tx_ring->syncp);
866 tx_ring->stats.packets += total_packets;
867 tx_ring->stats.bytes += total_bytes;
868 u64_stats_update_end(&tx_ring->syncp);
869
870 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
871 /* schedule immediate reset if we believe we hung */
872 struct ixgbe_hw *hw = &adapter->hw;
873 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
874 e_err(drv, "Detected Tx Unit Hang\n"
875 " Tx Queue <%d>\n"
876 " TDH, TDT <%x>, <%x>\n"
877 " next_to_use <%x>\n"
878 " next_to_clean <%x>\n"
879 "tx_buffer_info[next_to_clean]\n"
880 " time_stamp <%lx>\n"
881 " jiffies <%lx>\n",
882 tx_ring->queue_index,
883 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
884 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
885 tx_ring->next_to_use, eop,
886 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
887
888 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
889
890 e_info(probe,
891 "tx hang %d detected on queue %d, resetting adapter\n",
892 adapter->tx_timeout_count + 1, tx_ring->queue_index);
893
894 /* schedule immediate reset if we believe we hung */
895 ixgbe_tx_timeout(adapter->netdev);
896
897 /* the adapter is about to reset, no point in enabling stuff */
898 return true;
899 }
900
901 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
902 if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
903 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
904 /* Make sure that anybody stopping the queue after this
905 * sees the new next_to_clean.
906 */
907 smp_mb();
908 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
909 !test_bit(__IXGBE_DOWN, &adapter->state)) {
910 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
911 ++tx_ring->tx_stats.restart_queue;
912 }
913 }
914
915 return count < tx_ring->work_limit;
916 }
917
918 #ifdef CONFIG_IXGBE_DCA
919 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
920 struct ixgbe_ring *rx_ring,
921 int cpu)
922 {
923 struct ixgbe_hw *hw = &adapter->hw;
924 u32 rxctrl;
925 u8 reg_idx = rx_ring->reg_idx;
926
927 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
928 switch (hw->mac.type) {
929 case ixgbe_mac_82598EB:
930 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
931 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
932 break;
933 case ixgbe_mac_82599EB:
934 case ixgbe_mac_X540:
935 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
936 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
937 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
938 break;
939 default:
940 break;
941 }
942 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
943 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
944 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
945 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
946 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
947 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
948 }
949
950 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
951 struct ixgbe_ring *tx_ring,
952 int cpu)
953 {
954 struct ixgbe_hw *hw = &adapter->hw;
955 u32 txctrl;
956 u8 reg_idx = tx_ring->reg_idx;
957
958 switch (hw->mac.type) {
959 case ixgbe_mac_82598EB:
960 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
961 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
962 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
963 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
964 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
965 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
966 break;
967 case ixgbe_mac_82599EB:
968 case ixgbe_mac_X540:
969 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
970 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
971 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
972 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
973 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
974 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
975 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
976 break;
977 default:
978 break;
979 }
980 }
981
982 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
983 {
984 struct ixgbe_adapter *adapter = q_vector->adapter;
985 int cpu = get_cpu();
986 long r_idx;
987 int i;
988
989 if (q_vector->cpu == cpu)
990 goto out_no_update;
991
992 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
993 for (i = 0; i < q_vector->txr_count; i++) {
994 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
995 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
996 r_idx + 1);
997 }
998
999 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1000 for (i = 0; i < q_vector->rxr_count; i++) {
1001 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
1002 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1003 r_idx + 1);
1004 }
1005
1006 q_vector->cpu = cpu;
1007 out_no_update:
1008 put_cpu();
1009 }
1010
1011 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1012 {
1013 int num_q_vectors;
1014 int i;
1015
1016 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1017 return;
1018
1019 /* always use CB2 mode, difference is masked in the CB driver */
1020 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1021
1022 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1023 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1024 else
1025 num_q_vectors = 1;
1026
1027 for (i = 0; i < num_q_vectors; i++) {
1028 adapter->q_vector[i]->cpu = -1;
1029 ixgbe_update_dca(adapter->q_vector[i]);
1030 }
1031 }
1032
1033 static int __ixgbe_notify_dca(struct device *dev, void *data)
1034 {
1035 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1036 unsigned long event = *(unsigned long *)data;
1037
1038 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1039 return 0;
1040
1041 switch (event) {
1042 case DCA_PROVIDER_ADD:
1043 /* if we're already enabled, don't do it again */
1044 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1045 break;
1046 if (dca_add_requester(dev) == 0) {
1047 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1048 ixgbe_setup_dca(adapter);
1049 break;
1050 }
1051 /* Fall Through since DCA is disabled. */
1052 case DCA_PROVIDER_REMOVE:
1053 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1054 dca_remove_requester(dev);
1055 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1056 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1057 }
1058 break;
1059 }
1060
1061 return 0;
1062 }
1063
1064 #endif /* CONFIG_IXGBE_DCA */
1065 /**
1066 * ixgbe_receive_skb - Send a completed packet up the stack
1067 * @adapter: board private structure
1068 * @skb: packet to send up
1069 * @status: hardware indication of status of receive
1070 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1071 * @rx_desc: rx descriptor
1072 **/
1073 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1074 struct sk_buff *skb, u8 status,
1075 struct ixgbe_ring *ring,
1076 union ixgbe_adv_rx_desc *rx_desc)
1077 {
1078 struct ixgbe_adapter *adapter = q_vector->adapter;
1079 struct napi_struct *napi = &q_vector->napi;
1080 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1081 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1082
1083 if (is_vlan && (tag & VLAN_VID_MASK))
1084 __vlan_hwaccel_put_tag(skb, tag);
1085
1086 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1087 napi_gro_receive(napi, skb);
1088 else
1089 netif_rx(skb);
1090 }
1091
1092 /**
1093 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1094 * @adapter: address of board private structure
1095 * @status_err: hardware indication of status of receive
1096 * @skb: skb currently being received and modified
1097 **/
1098 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1099 union ixgbe_adv_rx_desc *rx_desc,
1100 struct sk_buff *skb)
1101 {
1102 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
1103
1104 skb_checksum_none_assert(skb);
1105
1106 /* Rx csum disabled */
1107 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1108 return;
1109
1110 /* if IP and error */
1111 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1112 (status_err & IXGBE_RXDADV_ERR_IPE)) {
1113 adapter->hw_csum_rx_error++;
1114 return;
1115 }
1116
1117 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1118 return;
1119
1120 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1121 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1122
1123 /*
1124 * 82599 errata, UDP frames with a 0 checksum can be marked as
1125 * checksum errors.
1126 */
1127 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1128 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1129 return;
1130
1131 adapter->hw_csum_rx_error++;
1132 return;
1133 }
1134
1135 /* It must be a TCP or UDP packet with a valid checksum */
1136 skb->ip_summed = CHECKSUM_UNNECESSARY;
1137 }
1138
1139 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1140 {
1141 /*
1142 * Force memory writes to complete before letting h/w
1143 * know there are new descriptors to fetch. (Only
1144 * applicable for weak-ordered memory model archs,
1145 * such as IA-64).
1146 */
1147 wmb();
1148 writel(val, rx_ring->tail);
1149 }
1150
1151 /**
1152 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1153 * @rx_ring: ring to place buffers on
1154 * @cleaned_count: number of buffers to replace
1155 **/
1156 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1157 {
1158 union ixgbe_adv_rx_desc *rx_desc;
1159 struct ixgbe_rx_buffer *bi;
1160 struct sk_buff *skb;
1161 u16 i = rx_ring->next_to_use;
1162
1163 /* do nothing if no valid netdev defined */
1164 if (!rx_ring->netdev)
1165 return;
1166
1167 while (cleaned_count--) {
1168 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1169 bi = &rx_ring->rx_buffer_info[i];
1170 skb = bi->skb;
1171
1172 if (!skb) {
1173 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1174 rx_ring->rx_buf_len);
1175 if (!skb) {
1176 rx_ring->rx_stats.alloc_rx_buff_failed++;
1177 goto no_buffers;
1178 }
1179 /* initialize queue mapping */
1180 skb_record_rx_queue(skb, rx_ring->queue_index);
1181 bi->skb = skb;
1182 }
1183
1184 if (!bi->dma) {
1185 bi->dma = dma_map_single(rx_ring->dev,
1186 skb->data,
1187 rx_ring->rx_buf_len,
1188 DMA_FROM_DEVICE);
1189 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1190 rx_ring->rx_stats.alloc_rx_buff_failed++;
1191 bi->dma = 0;
1192 goto no_buffers;
1193 }
1194 }
1195
1196 if (ring_is_ps_enabled(rx_ring)) {
1197 if (!bi->page) {
1198 bi->page = netdev_alloc_page(rx_ring->netdev);
1199 if (!bi->page) {
1200 rx_ring->rx_stats.alloc_rx_page_failed++;
1201 goto no_buffers;
1202 }
1203 }
1204
1205 if (!bi->page_dma) {
1206 /* use a half page if we're re-using */
1207 bi->page_offset ^= PAGE_SIZE / 2;
1208 bi->page_dma = dma_map_page(rx_ring->dev,
1209 bi->page,
1210 bi->page_offset,
1211 PAGE_SIZE / 2,
1212 DMA_FROM_DEVICE);
1213 if (dma_mapping_error(rx_ring->dev,
1214 bi->page_dma)) {
1215 rx_ring->rx_stats.alloc_rx_page_failed++;
1216 bi->page_dma = 0;
1217 goto no_buffers;
1218 }
1219 }
1220
1221 /* Refresh the desc even if buffer_addrs didn't change
1222 * because each write-back erases this info. */
1223 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1224 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1225 } else {
1226 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1227 rx_desc->read.hdr_addr = 0;
1228 }
1229
1230 i++;
1231 if (i == rx_ring->count)
1232 i = 0;
1233 }
1234
1235 no_buffers:
1236 if (rx_ring->next_to_use != i) {
1237 rx_ring->next_to_use = i;
1238 ixgbe_release_rx_desc(rx_ring, i);
1239 }
1240 }
1241
1242 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1243 {
1244 /* HW will not DMA in data larger than the given buffer, even if it
1245 * parses the (NFS, of course) header to be larger. In that case, it
1246 * fills the header buffer and spills the rest into the page.
1247 */
1248 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1249 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1250 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1251 if (hlen > IXGBE_RX_HDR_SIZE)
1252 hlen = IXGBE_RX_HDR_SIZE;
1253 return hlen;
1254 }
1255
1256 /**
1257 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1258 * @skb: pointer to the last skb in the rsc queue
1259 *
1260 * This function changes a queue full of hw rsc buffers into a completed
1261 * packet. It uses the ->prev pointers to find the first packet and then
1262 * turns it into the frag list owner.
1263 **/
1264 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1265 {
1266 unsigned int frag_list_size = 0;
1267 unsigned int skb_cnt = 1;
1268
1269 while (skb->prev) {
1270 struct sk_buff *prev = skb->prev;
1271 frag_list_size += skb->len;
1272 skb->prev = NULL;
1273 skb = prev;
1274 skb_cnt++;
1275 }
1276
1277 skb_shinfo(skb)->frag_list = skb->next;
1278 skb->next = NULL;
1279 skb->len += frag_list_size;
1280 skb->data_len += frag_list_size;
1281 skb->truesize += frag_list_size;
1282 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1283
1284 return skb;
1285 }
1286
1287 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1288 {
1289 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1290 IXGBE_RXDADV_RSCCNT_MASK);
1291 }
1292
1293 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1294 struct ixgbe_ring *rx_ring,
1295 int *work_done, int work_to_do)
1296 {
1297 struct ixgbe_adapter *adapter = q_vector->adapter;
1298 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1299 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1300 struct sk_buff *skb;
1301 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1302 const int current_node = numa_node_id();
1303 #ifdef IXGBE_FCOE
1304 int ddp_bytes = 0;
1305 #endif /* IXGBE_FCOE */
1306 u32 staterr;
1307 u16 i;
1308 u16 cleaned_count = 0;
1309 bool pkt_is_rsc = false;
1310
1311 i = rx_ring->next_to_clean;
1312 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1313 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1314
1315 while (staterr & IXGBE_RXD_STAT_DD) {
1316 u32 upper_len = 0;
1317
1318 rmb(); /* read descriptor and rx_buffer_info after status DD */
1319
1320 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1321
1322 skb = rx_buffer_info->skb;
1323 rx_buffer_info->skb = NULL;
1324 prefetch(skb->data);
1325
1326 if (ring_is_rsc_enabled(rx_ring))
1327 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1328
1329 /* if this is a skb from previous receive DMA will be 0 */
1330 if (rx_buffer_info->dma) {
1331 u16 hlen;
1332 if (pkt_is_rsc &&
1333 !(staterr & IXGBE_RXD_STAT_EOP) &&
1334 !skb->prev) {
1335 /*
1336 * When HWRSC is enabled, delay unmapping
1337 * of the first packet. It carries the
1338 * header information, HW may still
1339 * access the header after the writeback.
1340 * Only unmap it when EOP is reached
1341 */
1342 IXGBE_RSC_CB(skb)->delay_unmap = true;
1343 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1344 } else {
1345 dma_unmap_single(rx_ring->dev,
1346 rx_buffer_info->dma,
1347 rx_ring->rx_buf_len,
1348 DMA_FROM_DEVICE);
1349 }
1350 rx_buffer_info->dma = 0;
1351
1352 if (ring_is_ps_enabled(rx_ring)) {
1353 hlen = ixgbe_get_hlen(rx_desc);
1354 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1355 } else {
1356 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1357 }
1358
1359 skb_put(skb, hlen);
1360 } else {
1361 /* assume packet split since header is unmapped */
1362 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1363 }
1364
1365 if (upper_len) {
1366 dma_unmap_page(rx_ring->dev,
1367 rx_buffer_info->page_dma,
1368 PAGE_SIZE / 2,
1369 DMA_FROM_DEVICE);
1370 rx_buffer_info->page_dma = 0;
1371 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1372 rx_buffer_info->page,
1373 rx_buffer_info->page_offset,
1374 upper_len);
1375
1376 if ((page_count(rx_buffer_info->page) == 1) &&
1377 (page_to_nid(rx_buffer_info->page) == current_node))
1378 get_page(rx_buffer_info->page);
1379 else
1380 rx_buffer_info->page = NULL;
1381
1382 skb->len += upper_len;
1383 skb->data_len += upper_len;
1384 skb->truesize += upper_len;
1385 }
1386
1387 i++;
1388 if (i == rx_ring->count)
1389 i = 0;
1390
1391 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1392 prefetch(next_rxd);
1393 cleaned_count++;
1394
1395 if (pkt_is_rsc) {
1396 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1397 IXGBE_RXDADV_NEXTP_SHIFT;
1398 next_buffer = &rx_ring->rx_buffer_info[nextp];
1399 } else {
1400 next_buffer = &rx_ring->rx_buffer_info[i];
1401 }
1402
1403 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1404 if (ring_is_ps_enabled(rx_ring)) {
1405 rx_buffer_info->skb = next_buffer->skb;
1406 rx_buffer_info->dma = next_buffer->dma;
1407 next_buffer->skb = skb;
1408 next_buffer->dma = 0;
1409 } else {
1410 skb->next = next_buffer->skb;
1411 skb->next->prev = skb;
1412 }
1413 rx_ring->rx_stats.non_eop_descs++;
1414 goto next_desc;
1415 }
1416
1417 if (skb->prev) {
1418 skb = ixgbe_transform_rsc_queue(skb);
1419 /* if we got here without RSC the packet is invalid */
1420 if (!pkt_is_rsc) {
1421 __pskb_trim(skb, 0);
1422 rx_buffer_info->skb = skb;
1423 goto next_desc;
1424 }
1425 }
1426
1427 if (ring_is_rsc_enabled(rx_ring)) {
1428 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1429 dma_unmap_single(rx_ring->dev,
1430 IXGBE_RSC_CB(skb)->dma,
1431 rx_ring->rx_buf_len,
1432 DMA_FROM_DEVICE);
1433 IXGBE_RSC_CB(skb)->dma = 0;
1434 IXGBE_RSC_CB(skb)->delay_unmap = false;
1435 }
1436 }
1437 if (pkt_is_rsc) {
1438 if (ring_is_ps_enabled(rx_ring))
1439 rx_ring->rx_stats.rsc_count +=
1440 skb_shinfo(skb)->nr_frags;
1441 else
1442 rx_ring->rx_stats.rsc_count +=
1443 IXGBE_RSC_CB(skb)->skb_cnt;
1444 rx_ring->rx_stats.rsc_flush++;
1445 }
1446
1447 /* ERR_MASK will only have valid bits if EOP set */
1448 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1449 /* trim packet back to size 0 and recycle it */
1450 __pskb_trim(skb, 0);
1451 rx_buffer_info->skb = skb;
1452 goto next_desc;
1453 }
1454
1455 ixgbe_rx_checksum(adapter, rx_desc, skb);
1456
1457 /* probably a little skewed due to removing CRC */
1458 total_rx_bytes += skb->len;
1459 total_rx_packets++;
1460
1461 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1462 #ifdef IXGBE_FCOE
1463 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1464 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1465 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1466 if (!ddp_bytes)
1467 goto next_desc;
1468 }
1469 #endif /* IXGBE_FCOE */
1470 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1471
1472 next_desc:
1473 rx_desc->wb.upper.status_error = 0;
1474
1475 (*work_done)++;
1476 if (*work_done >= work_to_do)
1477 break;
1478
1479 /* return some buffers to hardware, one at a time is too slow */
1480 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1481 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1482 cleaned_count = 0;
1483 }
1484
1485 /* use prefetched values */
1486 rx_desc = next_rxd;
1487 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1488 }
1489
1490 rx_ring->next_to_clean = i;
1491 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1492
1493 if (cleaned_count)
1494 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1495
1496 #ifdef IXGBE_FCOE
1497 /* include DDPed FCoE data */
1498 if (ddp_bytes > 0) {
1499 unsigned int mss;
1500
1501 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1502 sizeof(struct fc_frame_header) -
1503 sizeof(struct fcoe_crc_eof);
1504 if (mss > 512)
1505 mss &= ~511;
1506 total_rx_bytes += ddp_bytes;
1507 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1508 }
1509 #endif /* IXGBE_FCOE */
1510
1511 rx_ring->total_packets += total_rx_packets;
1512 rx_ring->total_bytes += total_rx_bytes;
1513 u64_stats_update_begin(&rx_ring->syncp);
1514 rx_ring->stats.packets += total_rx_packets;
1515 rx_ring->stats.bytes += total_rx_bytes;
1516 u64_stats_update_end(&rx_ring->syncp);
1517 }
1518
1519 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1520 /**
1521 * ixgbe_configure_msix - Configure MSI-X hardware
1522 * @adapter: board private structure
1523 *
1524 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1525 * interrupts.
1526 **/
1527 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1528 {
1529 struct ixgbe_q_vector *q_vector;
1530 int i, q_vectors, v_idx, r_idx;
1531 u32 mask;
1532
1533 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1534
1535 /*
1536 * Populate the IVAR table and set the ITR values to the
1537 * corresponding register.
1538 */
1539 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1540 q_vector = adapter->q_vector[v_idx];
1541 /* XXX for_each_set_bit(...) */
1542 r_idx = find_first_bit(q_vector->rxr_idx,
1543 adapter->num_rx_queues);
1544
1545 for (i = 0; i < q_vector->rxr_count; i++) {
1546 u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1547 ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
1548 r_idx = find_next_bit(q_vector->rxr_idx,
1549 adapter->num_rx_queues,
1550 r_idx + 1);
1551 }
1552 r_idx = find_first_bit(q_vector->txr_idx,
1553 adapter->num_tx_queues);
1554
1555 for (i = 0; i < q_vector->txr_count; i++) {
1556 u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1557 ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
1558 r_idx = find_next_bit(q_vector->txr_idx,
1559 adapter->num_tx_queues,
1560 r_idx + 1);
1561 }
1562
1563 if (q_vector->txr_count && !q_vector->rxr_count)
1564 /* tx only */
1565 q_vector->eitr = adapter->tx_eitr_param;
1566 else if (q_vector->rxr_count)
1567 /* rx or mixed */
1568 q_vector->eitr = adapter->rx_eitr_param;
1569
1570 ixgbe_write_eitr(q_vector);
1571 /* If Flow Director is enabled, set interrupt affinity */
1572 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1573 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1574 /*
1575 * Allocate the affinity_hint cpumask, assign the mask
1576 * for this vector, and set our affinity_hint for
1577 * this irq.
1578 */
1579 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1580 GFP_KERNEL))
1581 return;
1582 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1583 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1584 q_vector->affinity_mask);
1585 }
1586 }
1587
1588 switch (adapter->hw.mac.type) {
1589 case ixgbe_mac_82598EB:
1590 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1591 v_idx);
1592 break;
1593 case ixgbe_mac_82599EB:
1594 case ixgbe_mac_X540:
1595 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1596 break;
1597
1598 default:
1599 break;
1600 }
1601 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1602
1603 /* set up to autoclear timer, and the vectors */
1604 mask = IXGBE_EIMS_ENABLE_MASK;
1605 if (adapter->num_vfs)
1606 mask &= ~(IXGBE_EIMS_OTHER |
1607 IXGBE_EIMS_MAILBOX |
1608 IXGBE_EIMS_LSC);
1609 else
1610 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1611 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1612 }
1613
1614 enum latency_range {
1615 lowest_latency = 0,
1616 low_latency = 1,
1617 bulk_latency = 2,
1618 latency_invalid = 255
1619 };
1620
1621 /**
1622 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1623 * @adapter: pointer to adapter
1624 * @eitr: eitr setting (ints per sec) to give last timeslice
1625 * @itr_setting: current throttle rate in ints/second
1626 * @packets: the number of packets during this measurement interval
1627 * @bytes: the number of bytes during this measurement interval
1628 *
1629 * Stores a new ITR value based on packets and byte
1630 * counts during the last interrupt. The advantage of per interrupt
1631 * computation is faster updates and more accurate ITR for the current
1632 * traffic pattern. Constants in this function were computed
1633 * based on theoretical maximum wire speed and thresholds were set based
1634 * on testing data as well as attempting to minimize response time
1635 * while increasing bulk throughput.
1636 * this functionality is controlled by the InterruptThrottleRate module
1637 * parameter (see ixgbe_param.c)
1638 **/
1639 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1640 u32 eitr, u8 itr_setting,
1641 int packets, int bytes)
1642 {
1643 unsigned int retval = itr_setting;
1644 u32 timepassed_us;
1645 u64 bytes_perint;
1646
1647 if (packets == 0)
1648 goto update_itr_done;
1649
1650
1651 /* simple throttlerate management
1652 * 0-20MB/s lowest (100000 ints/s)
1653 * 20-100MB/s low (20000 ints/s)
1654 * 100-1249MB/s bulk (8000 ints/s)
1655 */
1656 /* what was last interrupt timeslice? */
1657 timepassed_us = 1000000/eitr;
1658 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1659
1660 switch (itr_setting) {
1661 case lowest_latency:
1662 if (bytes_perint > adapter->eitr_low)
1663 retval = low_latency;
1664 break;
1665 case low_latency:
1666 if (bytes_perint > adapter->eitr_high)
1667 retval = bulk_latency;
1668 else if (bytes_perint <= adapter->eitr_low)
1669 retval = lowest_latency;
1670 break;
1671 case bulk_latency:
1672 if (bytes_perint <= adapter->eitr_high)
1673 retval = low_latency;
1674 break;
1675 }
1676
1677 update_itr_done:
1678 return retval;
1679 }
1680
1681 /**
1682 * ixgbe_write_eitr - write EITR register in hardware specific way
1683 * @q_vector: structure containing interrupt and ring information
1684 *
1685 * This function is made to be called by ethtool and by the driver
1686 * when it needs to update EITR registers at runtime. Hardware
1687 * specific quirks/differences are taken care of here.
1688 */
1689 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1690 {
1691 struct ixgbe_adapter *adapter = q_vector->adapter;
1692 struct ixgbe_hw *hw = &adapter->hw;
1693 int v_idx = q_vector->v_idx;
1694 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1695
1696 switch (adapter->hw.mac.type) {
1697 case ixgbe_mac_82598EB:
1698 /* must write high and low 16 bits to reset counter */
1699 itr_reg |= (itr_reg << 16);
1700 break;
1701 case ixgbe_mac_82599EB:
1702 case ixgbe_mac_X540:
1703 /*
1704 * 82599 and X540 can support a value of zero, so allow it for
1705 * max interrupt rate, but there is an errata where it can
1706 * not be zero with RSC
1707 */
1708 if (itr_reg == 8 &&
1709 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1710 itr_reg = 0;
1711
1712 /*
1713 * set the WDIS bit to not clear the timer bits and cause an
1714 * immediate assertion of the interrupt
1715 */
1716 itr_reg |= IXGBE_EITR_CNT_WDIS;
1717 break;
1718 default:
1719 break;
1720 }
1721 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1722 }
1723
1724 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1725 {
1726 struct ixgbe_adapter *adapter = q_vector->adapter;
1727 int i, r_idx;
1728 u32 new_itr;
1729 u8 current_itr, ret_itr;
1730
1731 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1732 for (i = 0; i < q_vector->txr_count; i++) {
1733 struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
1734 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1735 q_vector->tx_itr,
1736 tx_ring->total_packets,
1737 tx_ring->total_bytes);
1738 /* if the result for this queue would decrease interrupt
1739 * rate for this vector then use that result */
1740 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1741 q_vector->tx_itr - 1 : ret_itr);
1742 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1743 r_idx + 1);
1744 }
1745
1746 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1747 for (i = 0; i < q_vector->rxr_count; i++) {
1748 struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
1749 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1750 q_vector->rx_itr,
1751 rx_ring->total_packets,
1752 rx_ring->total_bytes);
1753 /* if the result for this queue would decrease interrupt
1754 * rate for this vector then use that result */
1755 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1756 q_vector->rx_itr - 1 : ret_itr);
1757 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1758 r_idx + 1);
1759 }
1760
1761 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1762
1763 switch (current_itr) {
1764 /* counts and packets in update_itr are dependent on these numbers */
1765 case lowest_latency:
1766 new_itr = 100000;
1767 break;
1768 case low_latency:
1769 new_itr = 20000; /* aka hwitr = ~200 */
1770 break;
1771 case bulk_latency:
1772 default:
1773 new_itr = 8000;
1774 break;
1775 }
1776
1777 if (new_itr != q_vector->eitr) {
1778 /* do an exponential smoothing */
1779 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1780
1781 /* save the algorithm value here, not the smoothed one */
1782 q_vector->eitr = new_itr;
1783
1784 ixgbe_write_eitr(q_vector);
1785 }
1786 }
1787
1788 /**
1789 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1790 * @work: pointer to work_struct containing our data
1791 **/
1792 static void ixgbe_check_overtemp_task(struct work_struct *work)
1793 {
1794 struct ixgbe_adapter *adapter = container_of(work,
1795 struct ixgbe_adapter,
1796 check_overtemp_task);
1797 struct ixgbe_hw *hw = &adapter->hw;
1798 u32 eicr = adapter->interrupt_event;
1799
1800 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1801 return;
1802
1803 switch (hw->device_id) {
1804 case IXGBE_DEV_ID_82599_T3_LOM: {
1805 u32 autoneg;
1806 bool link_up = false;
1807
1808 if (hw->mac.ops.check_link)
1809 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1810
1811 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1812 (eicr & IXGBE_EICR_LSC))
1813 /* Check if this is due to overtemp */
1814 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1815 break;
1816 return;
1817 }
1818 default:
1819 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1820 return;
1821 break;
1822 }
1823 e_crit(drv,
1824 "Network adapter has been stopped because it has over heated. "
1825 "Restart the computer. If the problem persists, "
1826 "power off the system and replace the adapter\n");
1827 /* write to clear the interrupt */
1828 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1829 }
1830
1831 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1832 {
1833 struct ixgbe_hw *hw = &adapter->hw;
1834
1835 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1836 (eicr & IXGBE_EICR_GPI_SDP1)) {
1837 e_crit(probe, "Fan has stopped, replace the adapter\n");
1838 /* write to clear the interrupt */
1839 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1840 }
1841 }
1842
1843 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1844 {
1845 struct ixgbe_hw *hw = &adapter->hw;
1846
1847 if (eicr & IXGBE_EICR_GPI_SDP2) {
1848 /* Clear the interrupt */
1849 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1850 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1851 schedule_work(&adapter->sfp_config_module_task);
1852 }
1853
1854 if (eicr & IXGBE_EICR_GPI_SDP1) {
1855 /* Clear the interrupt */
1856 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1857 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1858 schedule_work(&adapter->multispeed_fiber_task);
1859 }
1860 }
1861
1862 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1863 {
1864 struct ixgbe_hw *hw = &adapter->hw;
1865
1866 adapter->lsc_int++;
1867 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1868 adapter->link_check_timeout = jiffies;
1869 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1870 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1871 IXGBE_WRITE_FLUSH(hw);
1872 schedule_work(&adapter->watchdog_task);
1873 }
1874 }
1875
1876 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1877 {
1878 struct net_device *netdev = data;
1879 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1880 struct ixgbe_hw *hw = &adapter->hw;
1881 u32 eicr;
1882
1883 /*
1884 * Workaround for Silicon errata. Use clear-by-write instead
1885 * of clear-by-read. Reading with EICS will return the
1886 * interrupt causes without clearing, which later be done
1887 * with the write to EICR.
1888 */
1889 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1890 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1891
1892 if (eicr & IXGBE_EICR_LSC)
1893 ixgbe_check_lsc(adapter);
1894
1895 if (eicr & IXGBE_EICR_MAILBOX)
1896 ixgbe_msg_task(adapter);
1897
1898 switch (hw->mac.type) {
1899 case ixgbe_mac_82599EB:
1900 ixgbe_check_sfp_event(adapter, eicr);
1901 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1902 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1903 adapter->interrupt_event = eicr;
1904 schedule_work(&adapter->check_overtemp_task);
1905 }
1906 /* now fallthrough to handle Flow Director */
1907 case ixgbe_mac_X540:
1908 /* Handle Flow Director Full threshold interrupt */
1909 if (eicr & IXGBE_EICR_FLOW_DIR) {
1910 int i;
1911 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1912 /* Disable transmits before FDIR Re-initialization */
1913 netif_tx_stop_all_queues(netdev);
1914 for (i = 0; i < adapter->num_tx_queues; i++) {
1915 struct ixgbe_ring *tx_ring =
1916 adapter->tx_ring[i];
1917 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1918 &tx_ring->state))
1919 schedule_work(&adapter->fdir_reinit_task);
1920 }
1921 }
1922 break;
1923 default:
1924 break;
1925 }
1926
1927 ixgbe_check_fan_failure(adapter, eicr);
1928
1929 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1930 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1931
1932 return IRQ_HANDLED;
1933 }
1934
1935 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1936 u64 qmask)
1937 {
1938 u32 mask;
1939 struct ixgbe_hw *hw = &adapter->hw;
1940
1941 switch (hw->mac.type) {
1942 case ixgbe_mac_82598EB:
1943 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1944 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1945 break;
1946 case ixgbe_mac_82599EB:
1947 case ixgbe_mac_X540:
1948 mask = (qmask & 0xFFFFFFFF);
1949 if (mask)
1950 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1951 mask = (qmask >> 32);
1952 if (mask)
1953 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1954 break;
1955 default:
1956 break;
1957 }
1958 /* skip the flush */
1959 }
1960
1961 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1962 u64 qmask)
1963 {
1964 u32 mask;
1965 struct ixgbe_hw *hw = &adapter->hw;
1966
1967 switch (hw->mac.type) {
1968 case ixgbe_mac_82598EB:
1969 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1970 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1971 break;
1972 case ixgbe_mac_82599EB:
1973 case ixgbe_mac_X540:
1974 mask = (qmask & 0xFFFFFFFF);
1975 if (mask)
1976 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1977 mask = (qmask >> 32);
1978 if (mask)
1979 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1980 break;
1981 default:
1982 break;
1983 }
1984 /* skip the flush */
1985 }
1986
1987 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1988 {
1989 struct ixgbe_q_vector *q_vector = data;
1990 struct ixgbe_adapter *adapter = q_vector->adapter;
1991 struct ixgbe_ring *tx_ring;
1992 int i, r_idx;
1993
1994 if (!q_vector->txr_count)
1995 return IRQ_HANDLED;
1996
1997 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1998 for (i = 0; i < q_vector->txr_count; i++) {
1999 tx_ring = adapter->tx_ring[r_idx];
2000 tx_ring->total_bytes = 0;
2001 tx_ring->total_packets = 0;
2002 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2003 r_idx + 1);
2004 }
2005
2006 /* EIAM disabled interrupts (on this vector) for us */
2007 napi_schedule(&q_vector->napi);
2008
2009 return IRQ_HANDLED;
2010 }
2011
2012 /**
2013 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2014 * @irq: unused
2015 * @data: pointer to our q_vector struct for this interrupt vector
2016 **/
2017 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2018 {
2019 struct ixgbe_q_vector *q_vector = data;
2020 struct ixgbe_adapter *adapter = q_vector->adapter;
2021 struct ixgbe_ring *rx_ring;
2022 int r_idx;
2023 int i;
2024
2025 #ifdef CONFIG_IXGBE_DCA
2026 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2027 ixgbe_update_dca(q_vector);
2028 #endif
2029
2030 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2031 for (i = 0; i < q_vector->rxr_count; i++) {
2032 rx_ring = adapter->rx_ring[r_idx];
2033 rx_ring->total_bytes = 0;
2034 rx_ring->total_packets = 0;
2035 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2036 r_idx + 1);
2037 }
2038
2039 if (!q_vector->rxr_count)
2040 return IRQ_HANDLED;
2041
2042 /* EIAM disabled interrupts (on this vector) for us */
2043 napi_schedule(&q_vector->napi);
2044
2045 return IRQ_HANDLED;
2046 }
2047
2048 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2049 {
2050 struct ixgbe_q_vector *q_vector = data;
2051 struct ixgbe_adapter *adapter = q_vector->adapter;
2052 struct ixgbe_ring *ring;
2053 int r_idx;
2054 int i;
2055
2056 if (!q_vector->txr_count && !q_vector->rxr_count)
2057 return IRQ_HANDLED;
2058
2059 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2060 for (i = 0; i < q_vector->txr_count; i++) {
2061 ring = adapter->tx_ring[r_idx];
2062 ring->total_bytes = 0;
2063 ring->total_packets = 0;
2064 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2065 r_idx + 1);
2066 }
2067
2068 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2069 for (i = 0; i < q_vector->rxr_count; i++) {
2070 ring = adapter->rx_ring[r_idx];
2071 ring->total_bytes = 0;
2072 ring->total_packets = 0;
2073 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2074 r_idx + 1);
2075 }
2076
2077 /* EIAM disabled interrupts (on this vector) for us */
2078 napi_schedule(&q_vector->napi);
2079
2080 return IRQ_HANDLED;
2081 }
2082
2083 /**
2084 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2085 * @napi: napi struct with our devices info in it
2086 * @budget: amount of work driver is allowed to do this pass, in packets
2087 *
2088 * This function is optimized for cleaning one queue only on a single
2089 * q_vector!!!
2090 **/
2091 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2092 {
2093 struct ixgbe_q_vector *q_vector =
2094 container_of(napi, struct ixgbe_q_vector, napi);
2095 struct ixgbe_adapter *adapter = q_vector->adapter;
2096 struct ixgbe_ring *rx_ring = NULL;
2097 int work_done = 0;
2098 long r_idx;
2099
2100 #ifdef CONFIG_IXGBE_DCA
2101 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2102 ixgbe_update_dca(q_vector);
2103 #endif
2104
2105 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2106 rx_ring = adapter->rx_ring[r_idx];
2107
2108 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
2109
2110 /* If all Rx work done, exit the polling mode */
2111 if (work_done < budget) {
2112 napi_complete(napi);
2113 if (adapter->rx_itr_setting & 1)
2114 ixgbe_set_itr_msix(q_vector);
2115 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2116 ixgbe_irq_enable_queues(adapter,
2117 ((u64)1 << q_vector->v_idx));
2118 }
2119
2120 return work_done;
2121 }
2122
2123 /**
2124 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2125 * @napi: napi struct with our devices info in it
2126 * @budget: amount of work driver is allowed to do this pass, in packets
2127 *
2128 * This function will clean more than one rx queue associated with a
2129 * q_vector.
2130 **/
2131 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
2132 {
2133 struct ixgbe_q_vector *q_vector =
2134 container_of(napi, struct ixgbe_q_vector, napi);
2135 struct ixgbe_adapter *adapter = q_vector->adapter;
2136 struct ixgbe_ring *ring = NULL;
2137 int work_done = 0, i;
2138 long r_idx;
2139 bool tx_clean_complete = true;
2140
2141 #ifdef CONFIG_IXGBE_DCA
2142 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2143 ixgbe_update_dca(q_vector);
2144 #endif
2145
2146 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2147 for (i = 0; i < q_vector->txr_count; i++) {
2148 ring = adapter->tx_ring[r_idx];
2149 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2150 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2151 r_idx + 1);
2152 }
2153
2154 /* attempt to distribute budget to each queue fairly, but don't allow
2155 * the budget to go below 1 because we'll exit polling */
2156 budget /= (q_vector->rxr_count ?: 1);
2157 budget = max(budget, 1);
2158 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2159 for (i = 0; i < q_vector->rxr_count; i++) {
2160 ring = adapter->rx_ring[r_idx];
2161 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2162 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2163 r_idx + 1);
2164 }
2165
2166 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2167 ring = adapter->rx_ring[r_idx];
2168 /* If all Rx work done, exit the polling mode */
2169 if (work_done < budget) {
2170 napi_complete(napi);
2171 if (adapter->rx_itr_setting & 1)
2172 ixgbe_set_itr_msix(q_vector);
2173 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2174 ixgbe_irq_enable_queues(adapter,
2175 ((u64)1 << q_vector->v_idx));
2176 return 0;
2177 }
2178
2179 return work_done;
2180 }
2181
2182 /**
2183 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2184 * @napi: napi struct with our devices info in it
2185 * @budget: amount of work driver is allowed to do this pass, in packets
2186 *
2187 * This function is optimized for cleaning one queue only on a single
2188 * q_vector!!!
2189 **/
2190 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2191 {
2192 struct ixgbe_q_vector *q_vector =
2193 container_of(napi, struct ixgbe_q_vector, napi);
2194 struct ixgbe_adapter *adapter = q_vector->adapter;
2195 struct ixgbe_ring *tx_ring = NULL;
2196 int work_done = 0;
2197 long r_idx;
2198
2199 #ifdef CONFIG_IXGBE_DCA
2200 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2201 ixgbe_update_dca(q_vector);
2202 #endif
2203
2204 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2205 tx_ring = adapter->tx_ring[r_idx];
2206
2207 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2208 work_done = budget;
2209
2210 /* If all Tx work done, exit the polling mode */
2211 if (work_done < budget) {
2212 napi_complete(napi);
2213 if (adapter->tx_itr_setting & 1)
2214 ixgbe_set_itr_msix(q_vector);
2215 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2216 ixgbe_irq_enable_queues(adapter,
2217 ((u64)1 << q_vector->v_idx));
2218 }
2219
2220 return work_done;
2221 }
2222
2223 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2224 int r_idx)
2225 {
2226 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2227 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2228
2229 set_bit(r_idx, q_vector->rxr_idx);
2230 q_vector->rxr_count++;
2231 rx_ring->q_vector = q_vector;
2232 }
2233
2234 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2235 int t_idx)
2236 {
2237 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2238 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2239
2240 set_bit(t_idx, q_vector->txr_idx);
2241 q_vector->txr_count++;
2242 tx_ring->q_vector = q_vector;
2243 }
2244
2245 /**
2246 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2247 * @adapter: board private structure to initialize
2248 *
2249 * This function maps descriptor rings to the queue-specific vectors
2250 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2251 * one vector per ring/queue, but on a constrained vector budget, we
2252 * group the rings as "efficiently" as possible. You would add new
2253 * mapping configurations in here.
2254 **/
2255 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2256 {
2257 int q_vectors;
2258 int v_start = 0;
2259 int rxr_idx = 0, txr_idx = 0;
2260 int rxr_remaining = adapter->num_rx_queues;
2261 int txr_remaining = adapter->num_tx_queues;
2262 int i, j;
2263 int rqpv, tqpv;
2264 int err = 0;
2265
2266 /* No mapping required if MSI-X is disabled. */
2267 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2268 goto out;
2269
2270 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2271
2272 /*
2273 * The ideal configuration...
2274 * We have enough vectors to map one per queue.
2275 */
2276 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2277 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2278 map_vector_to_rxq(adapter, v_start, rxr_idx);
2279
2280 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2281 map_vector_to_txq(adapter, v_start, txr_idx);
2282
2283 goto out;
2284 }
2285
2286 /*
2287 * If we don't have enough vectors for a 1-to-1
2288 * mapping, we'll have to group them so there are
2289 * multiple queues per vector.
2290 */
2291 /* Re-adjusting *qpv takes care of the remainder. */
2292 for (i = v_start; i < q_vectors; i++) {
2293 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
2294 for (j = 0; j < rqpv; j++) {
2295 map_vector_to_rxq(adapter, i, rxr_idx);
2296 rxr_idx++;
2297 rxr_remaining--;
2298 }
2299 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
2300 for (j = 0; j < tqpv; j++) {
2301 map_vector_to_txq(adapter, i, txr_idx);
2302 txr_idx++;
2303 txr_remaining--;
2304 }
2305 }
2306 out:
2307 return err;
2308 }
2309
2310 /**
2311 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2312 * @adapter: board private structure
2313 *
2314 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2315 * interrupts from the kernel.
2316 **/
2317 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2318 {
2319 struct net_device *netdev = adapter->netdev;
2320 irqreturn_t (*handler)(int, void *);
2321 int i, vector, q_vectors, err;
2322 int ri = 0, ti = 0;
2323
2324 /* Decrement for Other and TCP Timer vectors */
2325 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2326
2327 err = ixgbe_map_rings_to_vectors(adapter);
2328 if (err)
2329 return err;
2330
2331 #define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \
2332 ? &ixgbe_msix_clean_many : \
2333 (_v)->rxr_count ? &ixgbe_msix_clean_rx : \
2334 (_v)->txr_count ? &ixgbe_msix_clean_tx : \
2335 NULL)
2336 for (vector = 0; vector < q_vectors; vector++) {
2337 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2338 handler = SET_HANDLER(q_vector);
2339
2340 if (handler == &ixgbe_msix_clean_rx) {
2341 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2342 "%s-%s-%d", netdev->name, "rx", ri++);
2343 } else if (handler == &ixgbe_msix_clean_tx) {
2344 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2345 "%s-%s-%d", netdev->name, "tx", ti++);
2346 } else if (handler == &ixgbe_msix_clean_many) {
2347 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2348 "%s-%s-%d", netdev->name, "TxRx", ri++);
2349 ti++;
2350 } else {
2351 /* skip this unused q_vector */
2352 continue;
2353 }
2354 err = request_irq(adapter->msix_entries[vector].vector,
2355 handler, 0, q_vector->name,
2356 q_vector);
2357 if (err) {
2358 e_err(probe, "request_irq failed for MSIX interrupt "
2359 "Error: %d\n", err);
2360 goto free_queue_irqs;
2361 }
2362 }
2363
2364 sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
2365 err = request_irq(adapter->msix_entries[vector].vector,
2366 ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev);
2367 if (err) {
2368 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2369 goto free_queue_irqs;
2370 }
2371
2372 return 0;
2373
2374 free_queue_irqs:
2375 for (i = vector - 1; i >= 0; i--)
2376 free_irq(adapter->msix_entries[--vector].vector,
2377 adapter->q_vector[i]);
2378 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2379 pci_disable_msix(adapter->pdev);
2380 kfree(adapter->msix_entries);
2381 adapter->msix_entries = NULL;
2382 return err;
2383 }
2384
2385 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2386 {
2387 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2388 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2389 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2390 u32 new_itr = q_vector->eitr;
2391 u8 current_itr;
2392
2393 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2394 q_vector->tx_itr,
2395 tx_ring->total_packets,
2396 tx_ring->total_bytes);
2397 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2398 q_vector->rx_itr,
2399 rx_ring->total_packets,
2400 rx_ring->total_bytes);
2401
2402 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2403
2404 switch (current_itr) {
2405 /* counts and packets in update_itr are dependent on these numbers */
2406 case lowest_latency:
2407 new_itr = 100000;
2408 break;
2409 case low_latency:
2410 new_itr = 20000; /* aka hwitr = ~200 */
2411 break;
2412 case bulk_latency:
2413 new_itr = 8000;
2414 break;
2415 default:
2416 break;
2417 }
2418
2419 if (new_itr != q_vector->eitr) {
2420 /* do an exponential smoothing */
2421 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
2422
2423 /* save the algorithm value here */
2424 q_vector->eitr = new_itr;
2425
2426 ixgbe_write_eitr(q_vector);
2427 }
2428 }
2429
2430 /**
2431 * ixgbe_irq_enable - Enable default interrupt generation settings
2432 * @adapter: board private structure
2433 **/
2434 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2435 bool flush)
2436 {
2437 u32 mask;
2438
2439 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2440 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2441 mask |= IXGBE_EIMS_GPI_SDP0;
2442 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2443 mask |= IXGBE_EIMS_GPI_SDP1;
2444 switch (adapter->hw.mac.type) {
2445 case ixgbe_mac_82599EB:
2446 case ixgbe_mac_X540:
2447 mask |= IXGBE_EIMS_ECC;
2448 mask |= IXGBE_EIMS_GPI_SDP1;
2449 mask |= IXGBE_EIMS_GPI_SDP2;
2450 if (adapter->num_vfs)
2451 mask |= IXGBE_EIMS_MAILBOX;
2452 break;
2453 default:
2454 break;
2455 }
2456 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2457 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2458 mask |= IXGBE_EIMS_FLOW_DIR;
2459
2460 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2461 if (queues)
2462 ixgbe_irq_enable_queues(adapter, ~0);
2463 if (flush)
2464 IXGBE_WRITE_FLUSH(&adapter->hw);
2465
2466 if (adapter->num_vfs > 32) {
2467 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2468 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2469 }
2470 }
2471
2472 /**
2473 * ixgbe_intr - legacy mode Interrupt Handler
2474 * @irq: interrupt number
2475 * @data: pointer to a network interface device structure
2476 **/
2477 static irqreturn_t ixgbe_intr(int irq, void *data)
2478 {
2479 struct net_device *netdev = data;
2480 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2481 struct ixgbe_hw *hw = &adapter->hw;
2482 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2483 u32 eicr;
2484
2485 /*
2486 * Workaround for silicon errata on 82598. Mask the interrupts
2487 * before the read of EICR.
2488 */
2489 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2490
2491 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2492 * therefore no explict interrupt disable is necessary */
2493 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2494 if (!eicr) {
2495 /*
2496 * shared interrupt alert!
2497 * make sure interrupts are enabled because the read will
2498 * have disabled interrupts due to EIAM
2499 * finish the workaround of silicon errata on 82598. Unmask
2500 * the interrupt that we masked before the EICR read.
2501 */
2502 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2503 ixgbe_irq_enable(adapter, true, true);
2504 return IRQ_NONE; /* Not our interrupt */
2505 }
2506
2507 if (eicr & IXGBE_EICR_LSC)
2508 ixgbe_check_lsc(adapter);
2509
2510 switch (hw->mac.type) {
2511 case ixgbe_mac_82599EB:
2512 ixgbe_check_sfp_event(adapter, eicr);
2513 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2514 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2515 adapter->interrupt_event = eicr;
2516 schedule_work(&adapter->check_overtemp_task);
2517 }
2518 break;
2519 default:
2520 break;
2521 }
2522
2523 ixgbe_check_fan_failure(adapter, eicr);
2524
2525 if (napi_schedule_prep(&(q_vector->napi))) {
2526 adapter->tx_ring[0]->total_packets = 0;
2527 adapter->tx_ring[0]->total_bytes = 0;
2528 adapter->rx_ring[0]->total_packets = 0;
2529 adapter->rx_ring[0]->total_bytes = 0;
2530 /* would disable interrupts here but EIAM disabled it */
2531 __napi_schedule(&(q_vector->napi));
2532 }
2533
2534 /*
2535 * re-enable link(maybe) and non-queue interrupts, no flush.
2536 * ixgbe_poll will re-enable the queue interrupts
2537 */
2538
2539 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2540 ixgbe_irq_enable(adapter, false, false);
2541
2542 return IRQ_HANDLED;
2543 }
2544
2545 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2546 {
2547 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2548
2549 for (i = 0; i < q_vectors; i++) {
2550 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2551 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2552 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2553 q_vector->rxr_count = 0;
2554 q_vector->txr_count = 0;
2555 }
2556 }
2557
2558 /**
2559 * ixgbe_request_irq - initialize interrupts
2560 * @adapter: board private structure
2561 *
2562 * Attempts to configure interrupts using the best available
2563 * capabilities of the hardware and kernel.
2564 **/
2565 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2566 {
2567 struct net_device *netdev = adapter->netdev;
2568 int err;
2569
2570 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2571 err = ixgbe_request_msix_irqs(adapter);
2572 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2573 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2574 netdev->name, netdev);
2575 } else {
2576 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2577 netdev->name, netdev);
2578 }
2579
2580 if (err)
2581 e_err(probe, "request_irq failed, Error %d\n", err);
2582
2583 return err;
2584 }
2585
2586 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2587 {
2588 struct net_device *netdev = adapter->netdev;
2589
2590 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2591 int i, q_vectors;
2592
2593 q_vectors = adapter->num_msix_vectors;
2594
2595 i = q_vectors - 1;
2596 free_irq(adapter->msix_entries[i].vector, netdev);
2597
2598 i--;
2599 for (; i >= 0; i--) {
2600 free_irq(adapter->msix_entries[i].vector,
2601 adapter->q_vector[i]);
2602 }
2603
2604 ixgbe_reset_q_vectors(adapter);
2605 } else {
2606 free_irq(adapter->pdev->irq, netdev);
2607 }
2608 }
2609
2610 /**
2611 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2612 * @adapter: board private structure
2613 **/
2614 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2615 {
2616 switch (adapter->hw.mac.type) {
2617 case ixgbe_mac_82598EB:
2618 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2619 break;
2620 case ixgbe_mac_82599EB:
2621 case ixgbe_mac_X540:
2622 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2623 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2624 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2625 if (adapter->num_vfs > 32)
2626 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2627 break;
2628 default:
2629 break;
2630 }
2631 IXGBE_WRITE_FLUSH(&adapter->hw);
2632 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2633 int i;
2634 for (i = 0; i < adapter->num_msix_vectors; i++)
2635 synchronize_irq(adapter->msix_entries[i].vector);
2636 } else {
2637 synchronize_irq(adapter->pdev->irq);
2638 }
2639 }
2640
2641 /**
2642 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2643 *
2644 **/
2645 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2646 {
2647 struct ixgbe_hw *hw = &adapter->hw;
2648
2649 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2650 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2651
2652 ixgbe_set_ivar(adapter, 0, 0, 0);
2653 ixgbe_set_ivar(adapter, 1, 0, 0);
2654
2655 map_vector_to_rxq(adapter, 0, 0);
2656 map_vector_to_txq(adapter, 0, 0);
2657
2658 e_info(hw, "Legacy interrupt IVAR setup done\n");
2659 }
2660
2661 /**
2662 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2663 * @adapter: board private structure
2664 * @ring: structure containing ring specific data
2665 *
2666 * Configure the Tx descriptor ring after a reset.
2667 **/
2668 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2669 struct ixgbe_ring *ring)
2670 {
2671 struct ixgbe_hw *hw = &adapter->hw;
2672 u64 tdba = ring->dma;
2673 int wait_loop = 10;
2674 u32 txdctl;
2675 u8 reg_idx = ring->reg_idx;
2676
2677 /* disable queue to avoid issues while updating state */
2678 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2679 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2680 txdctl & ~IXGBE_TXDCTL_ENABLE);
2681 IXGBE_WRITE_FLUSH(hw);
2682
2683 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2684 (tdba & DMA_BIT_MASK(32)));
2685 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2686 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2687 ring->count * sizeof(union ixgbe_adv_tx_desc));
2688 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2689 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2690 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2691
2692 /* configure fetching thresholds */
2693 if (adapter->rx_itr_setting == 0) {
2694 /* cannot set wthresh when itr==0 */
2695 txdctl &= ~0x007F0000;
2696 } else {
2697 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2698 txdctl |= (8 << 16);
2699 }
2700 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2701 /* PThresh workaround for Tx hang with DFP enabled. */
2702 txdctl |= 32;
2703 }
2704
2705 /* reinitialize flowdirector state */
2706 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2707 adapter->atr_sample_rate) {
2708 ring->atr_sample_rate = adapter->atr_sample_rate;
2709 ring->atr_count = 0;
2710 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2711 } else {
2712 ring->atr_sample_rate = 0;
2713 }
2714
2715 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2716
2717 /* enable queue */
2718 txdctl |= IXGBE_TXDCTL_ENABLE;
2719 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2720
2721 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2722 if (hw->mac.type == ixgbe_mac_82598EB &&
2723 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2724 return;
2725
2726 /* poll to verify queue is enabled */
2727 do {
2728 msleep(1);
2729 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2730 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2731 if (!wait_loop)
2732 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2733 }
2734
2735 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2736 {
2737 struct ixgbe_hw *hw = &adapter->hw;
2738 u32 rttdcs;
2739 u32 mask;
2740
2741 if (hw->mac.type == ixgbe_mac_82598EB)
2742 return;
2743
2744 /* disable the arbiter while setting MTQC */
2745 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2746 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2747 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2748
2749 /* set transmit pool layout */
2750 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2751 switch (adapter->flags & mask) {
2752
2753 case (IXGBE_FLAG_SRIOV_ENABLED):
2754 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2755 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2756 break;
2757
2758 case (IXGBE_FLAG_DCB_ENABLED):
2759 /* We enable 8 traffic classes, DCB only */
2760 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2761 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2762 break;
2763
2764 default:
2765 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2766 break;
2767 }
2768
2769 /* re-enable the arbiter */
2770 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2771 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2772 }
2773
2774 /**
2775 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2776 * @adapter: board private structure
2777 *
2778 * Configure the Tx unit of the MAC after a reset.
2779 **/
2780 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2781 {
2782 struct ixgbe_hw *hw = &adapter->hw;
2783 u32 dmatxctl;
2784 u32 i;
2785
2786 ixgbe_setup_mtqc(adapter);
2787
2788 if (hw->mac.type != ixgbe_mac_82598EB) {
2789 /* DMATXCTL.EN must be before Tx queues are enabled */
2790 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2791 dmatxctl |= IXGBE_DMATXCTL_TE;
2792 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2793 }
2794
2795 /* Setup the HW Tx Head and Tail descriptor pointers */
2796 for (i = 0; i < adapter->num_tx_queues; i++)
2797 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2798 }
2799
2800 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2801
2802 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2803 struct ixgbe_ring *rx_ring)
2804 {
2805 u32 srrctl;
2806 u8 reg_idx = rx_ring->reg_idx;
2807
2808 switch (adapter->hw.mac.type) {
2809 case ixgbe_mac_82598EB: {
2810 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2811 const int mask = feature[RING_F_RSS].mask;
2812 reg_idx = reg_idx & mask;
2813 }
2814 break;
2815 case ixgbe_mac_82599EB:
2816 case ixgbe_mac_X540:
2817 default:
2818 break;
2819 }
2820
2821 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2822
2823 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2824 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2825 if (adapter->num_vfs)
2826 srrctl |= IXGBE_SRRCTL_DROP_EN;
2827
2828 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2829 IXGBE_SRRCTL_BSIZEHDR_MASK;
2830
2831 if (ring_is_ps_enabled(rx_ring)) {
2832 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2833 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2834 #else
2835 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2836 #endif
2837 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2838 } else {
2839 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2840 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2841 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2842 }
2843
2844 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2845 }
2846
2847 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2848 {
2849 struct ixgbe_hw *hw = &adapter->hw;
2850 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2851 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2852 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2853 u32 mrqc = 0, reta = 0;
2854 u32 rxcsum;
2855 int i, j;
2856 int mask;
2857
2858 /* Fill out hash function seeds */
2859 for (i = 0; i < 10; i++)
2860 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2861
2862 /* Fill out redirection table */
2863 for (i = 0, j = 0; i < 128; i++, j++) {
2864 if (j == adapter->ring_feature[RING_F_RSS].indices)
2865 j = 0;
2866 /* reta = 4-byte sliding window of
2867 * 0x00..(indices-1)(indices-1)00..etc. */
2868 reta = (reta << 8) | (j * 0x11);
2869 if ((i & 3) == 3)
2870 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2871 }
2872
2873 /* Disable indicating checksum in descriptor, enables RSS hash */
2874 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2875 rxcsum |= IXGBE_RXCSUM_PCSD;
2876 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2877
2878 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2879 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2880 else
2881 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2882 #ifdef CONFIG_IXGBE_DCB
2883 | IXGBE_FLAG_DCB_ENABLED
2884 #endif
2885 | IXGBE_FLAG_SRIOV_ENABLED
2886 );
2887
2888 switch (mask) {
2889 case (IXGBE_FLAG_RSS_ENABLED):
2890 mrqc = IXGBE_MRQC_RSSEN;
2891 break;
2892 case (IXGBE_FLAG_SRIOV_ENABLED):
2893 mrqc = IXGBE_MRQC_VMDQEN;
2894 break;
2895 #ifdef CONFIG_IXGBE_DCB
2896 case (IXGBE_FLAG_DCB_ENABLED):
2897 mrqc = IXGBE_MRQC_RT8TCEN;
2898 break;
2899 #endif /* CONFIG_IXGBE_DCB */
2900 default:
2901 break;
2902 }
2903
2904 /* Perform hash on these packet types */
2905 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2906 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2907 | IXGBE_MRQC_RSS_FIELD_IPV6
2908 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2909
2910 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2911 }
2912
2913 /**
2914 * ixgbe_clear_rscctl - disable RSC for the indicated ring
2915 * @adapter: address of board private structure
2916 * @ring: structure containing ring specific data
2917 **/
2918 void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
2919 struct ixgbe_ring *ring)
2920 {
2921 struct ixgbe_hw *hw = &adapter->hw;
2922 u32 rscctrl;
2923 u8 reg_idx = ring->reg_idx;
2924
2925 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2926 rscctrl &= ~IXGBE_RSCCTL_RSCEN;
2927 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2928 }
2929
2930 /**
2931 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2932 * @adapter: address of board private structure
2933 * @index: index of ring to set
2934 **/
2935 void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2936 struct ixgbe_ring *ring)
2937 {
2938 struct ixgbe_hw *hw = &adapter->hw;
2939 u32 rscctrl;
2940 int rx_buf_len;
2941 u8 reg_idx = ring->reg_idx;
2942
2943 if (!ring_is_rsc_enabled(ring))
2944 return;
2945
2946 rx_buf_len = ring->rx_buf_len;
2947 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2948 rscctrl |= IXGBE_RSCCTL_RSCEN;
2949 /*
2950 * we must limit the number of descriptors so that the
2951 * total size of max desc * buf_len is not greater
2952 * than 65535
2953 */
2954 if (ring_is_ps_enabled(ring)) {
2955 #if (MAX_SKB_FRAGS > 16)
2956 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2957 #elif (MAX_SKB_FRAGS > 8)
2958 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2959 #elif (MAX_SKB_FRAGS > 4)
2960 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2961 #else
2962 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2963 #endif
2964 } else {
2965 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2966 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2967 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2968 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2969 else
2970 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2971 }
2972 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2973 }
2974
2975 /**
2976 * ixgbe_set_uta - Set unicast filter table address
2977 * @adapter: board private structure
2978 *
2979 * The unicast table address is a register array of 32-bit registers.
2980 * The table is meant to be used in a way similar to how the MTA is used
2981 * however due to certain limitations in the hardware it is necessary to
2982 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2983 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2984 **/
2985 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2986 {
2987 struct ixgbe_hw *hw = &adapter->hw;
2988 int i;
2989
2990 /* The UTA table only exists on 82599 hardware and newer */
2991 if (hw->mac.type < ixgbe_mac_82599EB)
2992 return;
2993
2994 /* we only need to do this if VMDq is enabled */
2995 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2996 return;
2997
2998 for (i = 0; i < 128; i++)
2999 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3000 }
3001
3002 #define IXGBE_MAX_RX_DESC_POLL 10
3003 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3004 struct ixgbe_ring *ring)
3005 {
3006 struct ixgbe_hw *hw = &adapter->hw;
3007 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3008 u32 rxdctl;
3009 u8 reg_idx = ring->reg_idx;
3010
3011 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3012 if (hw->mac.type == ixgbe_mac_82598EB &&
3013 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3014 return;
3015
3016 do {
3017 msleep(1);
3018 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3019 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3020
3021 if (!wait_loop) {
3022 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3023 "the polling period\n", reg_idx);
3024 }
3025 }
3026
3027 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3028 struct ixgbe_ring *ring)
3029 {
3030 struct ixgbe_hw *hw = &adapter->hw;
3031 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3032 u32 rxdctl;
3033 u8 reg_idx = ring->reg_idx;
3034
3035 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3036 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3037
3038 /* write value back with RXDCTL.ENABLE bit cleared */
3039 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3040
3041 if (hw->mac.type == ixgbe_mac_82598EB &&
3042 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3043 return;
3044
3045 /* the hardware may take up to 100us to really disable the rx queue */
3046 do {
3047 udelay(10);
3048 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3049 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3050
3051 if (!wait_loop) {
3052 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3053 "the polling period\n", reg_idx);
3054 }
3055 }
3056
3057 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3058 struct ixgbe_ring *ring)
3059 {
3060 struct ixgbe_hw *hw = &adapter->hw;
3061 u64 rdba = ring->dma;
3062 u32 rxdctl;
3063 u8 reg_idx = ring->reg_idx;
3064
3065 /* disable queue to avoid issues while updating state */
3066 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3067 ixgbe_disable_rx_queue(adapter, ring);
3068
3069 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3070 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3071 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3072 ring->count * sizeof(union ixgbe_adv_rx_desc));
3073 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3074 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3075 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3076
3077 ixgbe_configure_srrctl(adapter, ring);
3078 ixgbe_configure_rscctl(adapter, ring);
3079
3080 /* If operating in IOV mode set RLPML for X540 */
3081 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3082 hw->mac.type == ixgbe_mac_X540) {
3083 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3084 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3085 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3086 }
3087
3088 if (hw->mac.type == ixgbe_mac_82598EB) {
3089 /*
3090 * enable cache line friendly hardware writes:
3091 * PTHRESH=32 descriptors (half the internal cache),
3092 * this also removes ugly rx_no_buffer_count increment
3093 * HTHRESH=4 descriptors (to minimize latency on fetch)
3094 * WTHRESH=8 burst writeback up to two cache lines
3095 */
3096 rxdctl &= ~0x3FFFFF;
3097 rxdctl |= 0x080420;
3098 }
3099
3100 /* enable receive descriptor ring */
3101 rxdctl |= IXGBE_RXDCTL_ENABLE;
3102 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3103
3104 ixgbe_rx_desc_queue_enable(adapter, ring);
3105 ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
3106 }
3107
3108 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3109 {
3110 struct ixgbe_hw *hw = &adapter->hw;
3111 int p;
3112
3113 /* PSRTYPE must be initialized in non 82598 adapters */
3114 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3115 IXGBE_PSRTYPE_UDPHDR |
3116 IXGBE_PSRTYPE_IPV4HDR |
3117 IXGBE_PSRTYPE_L2HDR |
3118 IXGBE_PSRTYPE_IPV6HDR;
3119
3120 if (hw->mac.type == ixgbe_mac_82598EB)
3121 return;
3122
3123 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3124 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3125
3126 for (p = 0; p < adapter->num_rx_pools; p++)
3127 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3128 psrtype);
3129 }
3130
3131 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3132 {
3133 struct ixgbe_hw *hw = &adapter->hw;
3134 u32 gcr_ext;
3135 u32 vt_reg_bits;
3136 u32 reg_offset, vf_shift;
3137 u32 vmdctl;
3138
3139 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3140 return;
3141
3142 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3143 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3144 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3145 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3146
3147 vf_shift = adapter->num_vfs % 32;
3148 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3149
3150 /* Enable only the PF's pool for Tx/Rx */
3151 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3152 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3153 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3154 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3155 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3156
3157 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3158 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3159
3160 /*
3161 * Set up VF register offsets for selected VT Mode,
3162 * i.e. 32 or 64 VFs for SR-IOV
3163 */
3164 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3165 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3166 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3167 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3168
3169 /* enable Tx loopback for VF/PF communication */
3170 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3171 /* Enable MAC Anti-Spoofing */
3172 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3173 adapter->num_vfs);
3174 }
3175
3176 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3177 {
3178 struct ixgbe_hw *hw = &adapter->hw;
3179 struct net_device *netdev = adapter->netdev;
3180 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3181 int rx_buf_len;
3182 struct ixgbe_ring *rx_ring;
3183 int i;
3184 u32 mhadd, hlreg0;
3185
3186 /* Decide whether to use packet split mode or not */
3187 /* On by default */
3188 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3189
3190 /* Do not use packet split if we're in SR-IOV Mode */
3191 if (adapter->num_vfs)
3192 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3193
3194 /* Disable packet split due to 82599 erratum #45 */
3195 if (hw->mac.type == ixgbe_mac_82599EB)
3196 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3197
3198 /* Set the RX buffer length according to the mode */
3199 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3200 rx_buf_len = IXGBE_RX_HDR_SIZE;
3201 } else {
3202 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3203 (netdev->mtu <= ETH_DATA_LEN))
3204 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3205 else
3206 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
3207 }
3208
3209 #ifdef IXGBE_FCOE
3210 /* adjust max frame to be able to do baby jumbo for FCoE */
3211 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3212 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3213 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3214
3215 #endif /* IXGBE_FCOE */
3216 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3217 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3218 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3219 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3220
3221 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3222 }
3223
3224 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3225 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3226 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3227 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3228
3229 /*
3230 * Setup the HW Rx Head and Tail Descriptor Pointers and
3231 * the Base and Length of the Rx Descriptor Ring
3232 */
3233 for (i = 0; i < adapter->num_rx_queues; i++) {
3234 rx_ring = adapter->rx_ring[i];
3235 rx_ring->rx_buf_len = rx_buf_len;
3236
3237 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
3238 set_ring_ps_enabled(rx_ring);
3239 else
3240 clear_ring_ps_enabled(rx_ring);
3241
3242 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3243 set_ring_rsc_enabled(rx_ring);
3244 else
3245 clear_ring_rsc_enabled(rx_ring);
3246
3247 #ifdef IXGBE_FCOE
3248 if (netdev->features & NETIF_F_FCOE_MTU) {
3249 struct ixgbe_ring_feature *f;
3250 f = &adapter->ring_feature[RING_F_FCOE];
3251 if ((i >= f->mask) && (i < f->mask + f->indices)) {
3252 clear_ring_ps_enabled(rx_ring);
3253 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3254 rx_ring->rx_buf_len =
3255 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3256 } else if (!ring_is_rsc_enabled(rx_ring) &&
3257 !ring_is_ps_enabled(rx_ring)) {
3258 rx_ring->rx_buf_len =
3259 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3260 }
3261 }
3262 #endif /* IXGBE_FCOE */
3263 }
3264 }
3265
3266 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3267 {
3268 struct ixgbe_hw *hw = &adapter->hw;
3269 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3270
3271 switch (hw->mac.type) {
3272 case ixgbe_mac_82598EB:
3273 /*
3274 * For VMDq support of different descriptor types or
3275 * buffer sizes through the use of multiple SRRCTL
3276 * registers, RDRXCTL.MVMEN must be set to 1
3277 *
3278 * also, the manual doesn't mention it clearly but DCA hints
3279 * will only use queue 0's tags unless this bit is set. Side
3280 * effects of setting this bit are only that SRRCTL must be
3281 * fully programmed [0..15]
3282 */
3283 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3284 break;
3285 case ixgbe_mac_82599EB:
3286 case ixgbe_mac_X540:
3287 /* Disable RSC for ACK packets */
3288 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3289 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3290 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3291 /* hardware requires some bits to be set by default */
3292 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3293 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3294 break;
3295 default:
3296 /* We should do nothing since we don't know this hardware */
3297 return;
3298 }
3299
3300 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3301 }
3302
3303 /**
3304 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3305 * @adapter: board private structure
3306 *
3307 * Configure the Rx unit of the MAC after a reset.
3308 **/
3309 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3310 {
3311 struct ixgbe_hw *hw = &adapter->hw;
3312 int i;
3313 u32 rxctrl;
3314
3315 /* disable receives while setting up the descriptors */
3316 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3317 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3318
3319 ixgbe_setup_psrtype(adapter);
3320 ixgbe_setup_rdrxctl(adapter);
3321
3322 /* Program registers for the distribution of queues */
3323 ixgbe_setup_mrqc(adapter);
3324
3325 ixgbe_set_uta(adapter);
3326
3327 /* set_rx_buffer_len must be called before ring initialization */
3328 ixgbe_set_rx_buffer_len(adapter);
3329
3330 /*
3331 * Setup the HW Rx Head and Tail Descriptor Pointers and
3332 * the Base and Length of the Rx Descriptor Ring
3333 */
3334 for (i = 0; i < adapter->num_rx_queues; i++)
3335 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3336
3337 /* disable drop enable for 82598 parts */
3338 if (hw->mac.type == ixgbe_mac_82598EB)
3339 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3340
3341 /* enable all receives */
3342 rxctrl |= IXGBE_RXCTRL_RXEN;
3343 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3344 }
3345
3346 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3347 {
3348 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3349 struct ixgbe_hw *hw = &adapter->hw;
3350 int pool_ndx = adapter->num_vfs;
3351
3352 /* add VID to filter table */
3353 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3354 set_bit(vid, adapter->active_vlans);
3355 }
3356
3357 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3358 {
3359 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3360 struct ixgbe_hw *hw = &adapter->hw;
3361 int pool_ndx = adapter->num_vfs;
3362
3363 /* remove VID from filter table */
3364 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3365 clear_bit(vid, adapter->active_vlans);
3366 }
3367
3368 /**
3369 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3370 * @adapter: driver data
3371 */
3372 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3373 {
3374 struct ixgbe_hw *hw = &adapter->hw;
3375 u32 vlnctrl;
3376
3377 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3378 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3379 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3380 }
3381
3382 /**
3383 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3384 * @adapter: driver data
3385 */
3386 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3387 {
3388 struct ixgbe_hw *hw = &adapter->hw;
3389 u32 vlnctrl;
3390
3391 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3392 vlnctrl |= IXGBE_VLNCTRL_VFE;
3393 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3394 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3395 }
3396
3397 /**
3398 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3399 * @adapter: driver data
3400 */
3401 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3402 {
3403 struct ixgbe_hw *hw = &adapter->hw;
3404 u32 vlnctrl;
3405 int i, j;
3406
3407 switch (hw->mac.type) {
3408 case ixgbe_mac_82598EB:
3409 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3410 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3411 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3412 break;
3413 case ixgbe_mac_82599EB:
3414 case ixgbe_mac_X540:
3415 for (i = 0; i < adapter->num_rx_queues; i++) {
3416 j = adapter->rx_ring[i]->reg_idx;
3417 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3418 vlnctrl &= ~IXGBE_RXDCTL_VME;
3419 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3420 }
3421 break;
3422 default:
3423 break;
3424 }
3425 }
3426
3427 /**
3428 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3429 * @adapter: driver data
3430 */
3431 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3432 {
3433 struct ixgbe_hw *hw = &adapter->hw;
3434 u32 vlnctrl;
3435 int i, j;
3436
3437 switch (hw->mac.type) {
3438 case ixgbe_mac_82598EB:
3439 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3440 vlnctrl |= IXGBE_VLNCTRL_VME;
3441 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3442 break;
3443 case ixgbe_mac_82599EB:
3444 case ixgbe_mac_X540:
3445 for (i = 0; i < adapter->num_rx_queues; i++) {
3446 j = adapter->rx_ring[i]->reg_idx;
3447 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3448 vlnctrl |= IXGBE_RXDCTL_VME;
3449 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3450 }
3451 break;
3452 default:
3453 break;
3454 }
3455 }
3456
3457 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3458 {
3459 u16 vid;
3460
3461 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3462
3463 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3464 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3465 }
3466
3467 /**
3468 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3469 * @netdev: network interface device structure
3470 *
3471 * Writes unicast address list to the RAR table.
3472 * Returns: -ENOMEM on failure/insufficient address space
3473 * 0 on no addresses written
3474 * X on writing X addresses to the RAR table
3475 **/
3476 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3477 {
3478 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3479 struct ixgbe_hw *hw = &adapter->hw;
3480 unsigned int vfn = adapter->num_vfs;
3481 unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3482 int count = 0;
3483
3484 /* return ENOMEM indicating insufficient memory for addresses */
3485 if (netdev_uc_count(netdev) > rar_entries)
3486 return -ENOMEM;
3487
3488 if (!netdev_uc_empty(netdev) && rar_entries) {
3489 struct netdev_hw_addr *ha;
3490 /* return error if we do not support writing to RAR table */
3491 if (!hw->mac.ops.set_rar)
3492 return -ENOMEM;
3493
3494 netdev_for_each_uc_addr(ha, netdev) {
3495 if (!rar_entries)
3496 break;
3497 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3498 vfn, IXGBE_RAH_AV);
3499 count++;
3500 }
3501 }
3502 /* write the addresses in reverse order to avoid write combining */
3503 for (; rar_entries > 0 ; rar_entries--)
3504 hw->mac.ops.clear_rar(hw, rar_entries);
3505
3506 return count;
3507 }
3508
3509 /**
3510 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3511 * @netdev: network interface device structure
3512 *
3513 * The set_rx_method entry point is called whenever the unicast/multicast
3514 * address list or the network interface flags are updated. This routine is
3515 * responsible for configuring the hardware for proper unicast, multicast and
3516 * promiscuous mode.
3517 **/
3518 void ixgbe_set_rx_mode(struct net_device *netdev)
3519 {
3520 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3521 struct ixgbe_hw *hw = &adapter->hw;
3522 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3523 int count;
3524
3525 /* Check for Promiscuous and All Multicast modes */
3526
3527 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3528
3529 /* set all bits that we expect to always be set */
3530 fctrl |= IXGBE_FCTRL_BAM;
3531 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3532 fctrl |= IXGBE_FCTRL_PMCF;
3533
3534 /* clear the bits we are changing the status of */
3535 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3536
3537 if (netdev->flags & IFF_PROMISC) {
3538 hw->addr_ctrl.user_set_promisc = true;
3539 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3540 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3541 /* don't hardware filter vlans in promisc mode */
3542 ixgbe_vlan_filter_disable(adapter);
3543 } else {
3544 if (netdev->flags & IFF_ALLMULTI) {
3545 fctrl |= IXGBE_FCTRL_MPE;
3546 vmolr |= IXGBE_VMOLR_MPE;
3547 } else {
3548 /*
3549 * Write addresses to the MTA, if the attempt fails
3550 * then we should just turn on promiscous mode so
3551 * that we can at least receive multicast traffic
3552 */
3553 hw->mac.ops.update_mc_addr_list(hw, netdev);
3554 vmolr |= IXGBE_VMOLR_ROMPE;
3555 }
3556 ixgbe_vlan_filter_enable(adapter);
3557 hw->addr_ctrl.user_set_promisc = false;
3558 /*
3559 * Write addresses to available RAR registers, if there is not
3560 * sufficient space to store all the addresses then enable
3561 * unicast promiscous mode
3562 */
3563 count = ixgbe_write_uc_addr_list(netdev);
3564 if (count < 0) {
3565 fctrl |= IXGBE_FCTRL_UPE;
3566 vmolr |= IXGBE_VMOLR_ROPE;
3567 }
3568 }
3569
3570 if (adapter->num_vfs) {
3571 ixgbe_restore_vf_multicasts(adapter);
3572 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3573 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3574 IXGBE_VMOLR_ROPE);
3575 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3576 }
3577
3578 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3579
3580 if (netdev->features & NETIF_F_HW_VLAN_RX)
3581 ixgbe_vlan_strip_enable(adapter);
3582 else
3583 ixgbe_vlan_strip_disable(adapter);
3584 }
3585
3586 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3587 {
3588 int q_idx;
3589 struct ixgbe_q_vector *q_vector;
3590 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3591
3592 /* legacy and MSI only use one vector */
3593 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3594 q_vectors = 1;
3595
3596 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3597 struct napi_struct *napi;
3598 q_vector = adapter->q_vector[q_idx];
3599 napi = &q_vector->napi;
3600 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3601 if (!q_vector->rxr_count || !q_vector->txr_count) {
3602 if (q_vector->txr_count == 1)
3603 napi->poll = &ixgbe_clean_txonly;
3604 else if (q_vector->rxr_count == 1)
3605 napi->poll = &ixgbe_clean_rxonly;
3606 }
3607 }
3608
3609 napi_enable(napi);
3610 }
3611 }
3612
3613 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3614 {
3615 int q_idx;
3616 struct ixgbe_q_vector *q_vector;
3617 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3618
3619 /* legacy and MSI only use one vector */
3620 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3621 q_vectors = 1;
3622
3623 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3624 q_vector = adapter->q_vector[q_idx];
3625 napi_disable(&q_vector->napi);
3626 }
3627 }
3628
3629 #ifdef CONFIG_IXGBE_DCB
3630 /*
3631 * ixgbe_configure_dcb - Configure DCB hardware
3632 * @adapter: ixgbe adapter struct
3633 *
3634 * This is called by the driver on open to configure the DCB hardware.
3635 * This is also called by the gennetlink interface when reconfiguring
3636 * the DCB state.
3637 */
3638 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3639 {
3640 struct ixgbe_hw *hw = &adapter->hw;
3641 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3642
3643 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3644 if (hw->mac.type == ixgbe_mac_82598EB)
3645 netif_set_gso_max_size(adapter->netdev, 65536);
3646 return;
3647 }
3648
3649 if (hw->mac.type == ixgbe_mac_82598EB)
3650 netif_set_gso_max_size(adapter->netdev, 32768);
3651
3652 #ifdef CONFIG_FCOE
3653 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3654 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3655 #endif
3656
3657 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3658 DCB_TX_CONFIG);
3659 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3660 DCB_RX_CONFIG);
3661
3662 /* Enable VLAN tag insert/strip */
3663 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3664
3665 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3666
3667 /* reconfigure the hardware */
3668 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3669 }
3670
3671 #endif
3672 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3673 {
3674 struct net_device *netdev = adapter->netdev;
3675 struct ixgbe_hw *hw = &adapter->hw;
3676 int i;
3677
3678 #ifdef CONFIG_IXGBE_DCB
3679 ixgbe_configure_dcb(adapter);
3680 #endif
3681
3682 ixgbe_set_rx_mode(netdev);
3683 ixgbe_restore_vlan(adapter);
3684
3685 #ifdef IXGBE_FCOE
3686 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3687 ixgbe_configure_fcoe(adapter);
3688
3689 #endif /* IXGBE_FCOE */
3690 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3691 for (i = 0; i < adapter->num_tx_queues; i++)
3692 adapter->tx_ring[i]->atr_sample_rate =
3693 adapter->atr_sample_rate;
3694 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3695 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3696 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3697 }
3698 ixgbe_configure_virtualization(adapter);
3699
3700 ixgbe_configure_tx(adapter);
3701 ixgbe_configure_rx(adapter);
3702 }
3703
3704 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3705 {
3706 switch (hw->phy.type) {
3707 case ixgbe_phy_sfp_avago:
3708 case ixgbe_phy_sfp_ftl:
3709 case ixgbe_phy_sfp_intel:
3710 case ixgbe_phy_sfp_unknown:
3711 case ixgbe_phy_sfp_passive_tyco:
3712 case ixgbe_phy_sfp_passive_unknown:
3713 case ixgbe_phy_sfp_active_unknown:
3714 case ixgbe_phy_sfp_ftl_active:
3715 return true;
3716 default:
3717 return false;
3718 }
3719 }
3720
3721 /**
3722 * ixgbe_sfp_link_config - set up SFP+ link
3723 * @adapter: pointer to private adapter struct
3724 **/
3725 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3726 {
3727 struct ixgbe_hw *hw = &adapter->hw;
3728
3729 if (hw->phy.multispeed_fiber) {
3730 /*
3731 * In multispeed fiber setups, the device may not have
3732 * had a physical connection when the driver loaded.
3733 * If that's the case, the initial link configuration
3734 * couldn't get the MAC into 10G or 1G mode, so we'll
3735 * never have a link status change interrupt fire.
3736 * We need to try and force an autonegotiation
3737 * session, then bring up link.
3738 */
3739 if (hw->mac.ops.setup_sfp)
3740 hw->mac.ops.setup_sfp(hw);
3741 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3742 schedule_work(&adapter->multispeed_fiber_task);
3743 } else {
3744 /*
3745 * Direct Attach Cu and non-multispeed fiber modules
3746 * still need to be configured properly prior to
3747 * attempting link.
3748 */
3749 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3750 schedule_work(&adapter->sfp_config_module_task);
3751 }
3752 }
3753
3754 /**
3755 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3756 * @hw: pointer to private hardware struct
3757 *
3758 * Returns 0 on success, negative on failure
3759 **/
3760 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3761 {
3762 u32 autoneg;
3763 bool negotiation, link_up = false;
3764 u32 ret = IXGBE_ERR_LINK_SETUP;
3765
3766 if (hw->mac.ops.check_link)
3767 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3768
3769 if (ret)
3770 goto link_cfg_out;
3771
3772 if (hw->mac.ops.get_link_capabilities)
3773 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3774 &negotiation);
3775 if (ret)
3776 goto link_cfg_out;
3777
3778 if (hw->mac.ops.setup_link)
3779 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3780 link_cfg_out:
3781 return ret;
3782 }
3783
3784 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3785 {
3786 struct ixgbe_hw *hw = &adapter->hw;
3787 u32 gpie = 0;
3788
3789 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3790 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3791 IXGBE_GPIE_OCD;
3792 gpie |= IXGBE_GPIE_EIAME;
3793 /*
3794 * use EIAM to auto-mask when MSI-X interrupt is asserted
3795 * this saves a register write for every interrupt
3796 */
3797 switch (hw->mac.type) {
3798 case ixgbe_mac_82598EB:
3799 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3800 break;
3801 case ixgbe_mac_82599EB:
3802 case ixgbe_mac_X540:
3803 default:
3804 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3805 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3806 break;
3807 }
3808 } else {
3809 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3810 * specifically only auto mask tx and rx interrupts */
3811 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3812 }
3813
3814 /* XXX: to interrupt immediately for EICS writes, enable this */
3815 /* gpie |= IXGBE_GPIE_EIMEN; */
3816
3817 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3818 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3819 gpie |= IXGBE_GPIE_VTMODE_64;
3820 }
3821
3822 /* Enable fan failure interrupt */
3823 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3824 gpie |= IXGBE_SDP1_GPIEN;
3825
3826 if (hw->mac.type == ixgbe_mac_82599EB)
3827 gpie |= IXGBE_SDP1_GPIEN;
3828 gpie |= IXGBE_SDP2_GPIEN;
3829
3830 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3831 }
3832
3833 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3834 {
3835 struct ixgbe_hw *hw = &adapter->hw;
3836 int err;
3837 u32 ctrl_ext;
3838
3839 ixgbe_get_hw_control(adapter);
3840 ixgbe_setup_gpie(adapter);
3841
3842 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3843 ixgbe_configure_msix(adapter);
3844 else
3845 ixgbe_configure_msi_and_legacy(adapter);
3846
3847 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3848 if (hw->mac.ops.enable_tx_laser &&
3849 ((hw->phy.multispeed_fiber) ||
3850 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3851 (hw->mac.type == ixgbe_mac_82599EB))))
3852 hw->mac.ops.enable_tx_laser(hw);
3853
3854 clear_bit(__IXGBE_DOWN, &adapter->state);
3855 ixgbe_napi_enable_all(adapter);
3856
3857 if (ixgbe_is_sfp(hw)) {
3858 ixgbe_sfp_link_config(adapter);
3859 } else {
3860 err = ixgbe_non_sfp_link_config(hw);
3861 if (err)
3862 e_err(probe, "link_config FAILED %d\n", err);
3863 }
3864
3865 /* clear any pending interrupts, may auto mask */
3866 IXGBE_READ_REG(hw, IXGBE_EICR);
3867 ixgbe_irq_enable(adapter, true, true);
3868
3869 /*
3870 * If this adapter has a fan, check to see if we had a failure
3871 * before we enabled the interrupt.
3872 */
3873 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3874 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3875 if (esdp & IXGBE_ESDP_SDP1)
3876 e_crit(drv, "Fan has stopped, replace the adapter\n");
3877 }
3878
3879 /*
3880 * For hot-pluggable SFP+ devices, a new SFP+ module may have
3881 * arrived before interrupts were enabled but after probe. Such
3882 * devices wouldn't have their type identified yet. We need to
3883 * kick off the SFP+ module setup first, then try to bring up link.
3884 * If we're not hot-pluggable SFP+, we just need to configure link
3885 * and bring it up.
3886 */
3887 if (hw->phy.type == ixgbe_phy_unknown)
3888 schedule_work(&adapter->sfp_config_module_task);
3889
3890 /* enable transmits */
3891 netif_tx_start_all_queues(adapter->netdev);
3892
3893 /* bring the link up in the watchdog, this could race with our first
3894 * link up interrupt but shouldn't be a problem */
3895 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3896 adapter->link_check_timeout = jiffies;
3897 mod_timer(&adapter->watchdog_timer, jiffies);
3898
3899 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3900 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3901 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3902 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3903
3904 return 0;
3905 }
3906
3907 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3908 {
3909 WARN_ON(in_interrupt());
3910 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3911 msleep(1);
3912 ixgbe_down(adapter);
3913 /*
3914 * If SR-IOV enabled then wait a bit before bringing the adapter
3915 * back up to give the VFs time to respond to the reset. The
3916 * two second wait is based upon the watchdog timer cycle in
3917 * the VF driver.
3918 */
3919 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3920 msleep(2000);
3921 ixgbe_up(adapter);
3922 clear_bit(__IXGBE_RESETTING, &adapter->state);
3923 }
3924
3925 int ixgbe_up(struct ixgbe_adapter *adapter)
3926 {
3927 /* hardware has been reset, we need to reload some things */
3928 ixgbe_configure(adapter);
3929
3930 return ixgbe_up_complete(adapter);
3931 }
3932
3933 void ixgbe_reset(struct ixgbe_adapter *adapter)
3934 {
3935 struct ixgbe_hw *hw = &adapter->hw;
3936 int err;
3937
3938 err = hw->mac.ops.init_hw(hw);
3939 switch (err) {
3940 case 0:
3941 case IXGBE_ERR_SFP_NOT_PRESENT:
3942 break;
3943 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3944 e_dev_err("master disable timed out\n");
3945 break;
3946 case IXGBE_ERR_EEPROM_VERSION:
3947 /* We are running on a pre-production device, log a warning */
3948 e_dev_warn("This device is a pre-production adapter/LOM. "
3949 "Please be aware there may be issuesassociated with "
3950 "your hardware. If you are experiencing problems "
3951 "please contact your Intel or hardware "
3952 "representative who provided you with this "
3953 "hardware.\n");
3954 break;
3955 default:
3956 e_dev_err("Hardware Error: %d\n", err);
3957 }
3958
3959 /* reprogram the RAR[0] in case user changed it. */
3960 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3961 IXGBE_RAH_AV);
3962 }
3963
3964 /**
3965 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3966 * @rx_ring: ring to free buffers from
3967 **/
3968 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3969 {
3970 struct device *dev = rx_ring->dev;
3971 unsigned long size;
3972 u16 i;
3973
3974 /* ring already cleared, nothing to do */
3975 if (!rx_ring->rx_buffer_info)
3976 return;
3977
3978 /* Free all the Rx ring sk_buffs */
3979 for (i = 0; i < rx_ring->count; i++) {
3980 struct ixgbe_rx_buffer *rx_buffer_info;
3981
3982 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3983 if (rx_buffer_info->dma) {
3984 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3985 rx_ring->rx_buf_len,
3986 DMA_FROM_DEVICE);
3987 rx_buffer_info->dma = 0;
3988 }
3989 if (rx_buffer_info->skb) {
3990 struct sk_buff *skb = rx_buffer_info->skb;
3991 rx_buffer_info->skb = NULL;
3992 do {
3993 struct sk_buff *this = skb;
3994 if (IXGBE_RSC_CB(this)->delay_unmap) {
3995 dma_unmap_single(dev,
3996 IXGBE_RSC_CB(this)->dma,
3997 rx_ring->rx_buf_len,
3998 DMA_FROM_DEVICE);
3999 IXGBE_RSC_CB(this)->dma = 0;
4000 IXGBE_RSC_CB(skb)->delay_unmap = false;
4001 }
4002 skb = skb->prev;
4003 dev_kfree_skb(this);
4004 } while (skb);
4005 }
4006 if (!rx_buffer_info->page)
4007 continue;
4008 if (rx_buffer_info->page_dma) {
4009 dma_unmap_page(dev, rx_buffer_info->page_dma,
4010 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4011 rx_buffer_info->page_dma = 0;
4012 }
4013 put_page(rx_buffer_info->page);
4014 rx_buffer_info->page = NULL;
4015 rx_buffer_info->page_offset = 0;
4016 }
4017
4018 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4019 memset(rx_ring->rx_buffer_info, 0, size);
4020
4021 /* Zero out the descriptor ring */
4022 memset(rx_ring->desc, 0, rx_ring->size);
4023
4024 rx_ring->next_to_clean = 0;
4025 rx_ring->next_to_use = 0;
4026 }
4027
4028 /**
4029 * ixgbe_clean_tx_ring - Free Tx Buffers
4030 * @tx_ring: ring to be cleaned
4031 **/
4032 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4033 {
4034 struct ixgbe_tx_buffer *tx_buffer_info;
4035 unsigned long size;
4036 u16 i;
4037
4038 /* ring already cleared, nothing to do */
4039 if (!tx_ring->tx_buffer_info)
4040 return;
4041
4042 /* Free all the Tx ring sk_buffs */
4043 for (i = 0; i < tx_ring->count; i++) {
4044 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4045 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4046 }
4047
4048 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4049 memset(tx_ring->tx_buffer_info, 0, size);
4050
4051 /* Zero out the descriptor ring */
4052 memset(tx_ring->desc, 0, tx_ring->size);
4053
4054 tx_ring->next_to_use = 0;
4055 tx_ring->next_to_clean = 0;
4056 }
4057
4058 /**
4059 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4060 * @adapter: board private structure
4061 **/
4062 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4063 {
4064 int i;
4065
4066 for (i = 0; i < adapter->num_rx_queues; i++)
4067 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4068 }
4069
4070 /**
4071 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4072 * @adapter: board private structure
4073 **/
4074 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4075 {
4076 int i;
4077
4078 for (i = 0; i < adapter->num_tx_queues; i++)
4079 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4080 }
4081
4082 void ixgbe_down(struct ixgbe_adapter *adapter)
4083 {
4084 struct net_device *netdev = adapter->netdev;
4085 struct ixgbe_hw *hw = &adapter->hw;
4086 u32 rxctrl;
4087 u32 txdctl;
4088 int i;
4089 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4090
4091 /* signal that we are down to the interrupt handler */
4092 set_bit(__IXGBE_DOWN, &adapter->state);
4093
4094 /* disable receive for all VFs and wait one second */
4095 if (adapter->num_vfs) {
4096 /* ping all the active vfs to let them know we are going down */
4097 ixgbe_ping_all_vfs(adapter);
4098
4099 /* Disable all VFTE/VFRE TX/RX */
4100 ixgbe_disable_tx_rx(adapter);
4101
4102 /* Mark all the VFs as inactive */
4103 for (i = 0 ; i < adapter->num_vfs; i++)
4104 adapter->vfinfo[i].clear_to_send = 0;
4105 }
4106
4107 /* disable receives */
4108 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4109 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4110
4111 /* disable all enabled rx queues */
4112 for (i = 0; i < adapter->num_rx_queues; i++)
4113 /* this call also flushes the previous write */
4114 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4115
4116 msleep(10);
4117
4118 netif_tx_stop_all_queues(netdev);
4119
4120 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4121 del_timer_sync(&adapter->sfp_timer);
4122 del_timer_sync(&adapter->watchdog_timer);
4123 cancel_work_sync(&adapter->watchdog_task);
4124
4125 netif_carrier_off(netdev);
4126 netif_tx_disable(netdev);
4127
4128 ixgbe_irq_disable(adapter);
4129
4130 ixgbe_napi_disable_all(adapter);
4131
4132 /* Cleanup the affinity_hint CPU mask memory and callback */
4133 for (i = 0; i < num_q_vectors; i++) {
4134 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4135 /* clear the affinity_mask in the IRQ descriptor */
4136 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4137 /* release the CPU mask memory */
4138 free_cpumask_var(q_vector->affinity_mask);
4139 }
4140
4141 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4142 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4143 cancel_work_sync(&adapter->fdir_reinit_task);
4144
4145 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4146 cancel_work_sync(&adapter->check_overtemp_task);
4147
4148 /* disable transmits in the hardware now that interrupts are off */
4149 for (i = 0; i < adapter->num_tx_queues; i++) {
4150 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4151 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
4152 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
4153 (txdctl & ~IXGBE_TXDCTL_ENABLE));
4154 }
4155 /* Disable the Tx DMA engine on 82599 */
4156 switch (hw->mac.type) {
4157 case ixgbe_mac_82599EB:
4158 case ixgbe_mac_X540:
4159 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4160 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4161 ~IXGBE_DMATXCTL_TE));
4162 break;
4163 default:
4164 break;
4165 }
4166
4167 /* clear n-tuple filters that are cached */
4168 ethtool_ntuple_flush(netdev);
4169
4170 if (!pci_channel_offline(adapter->pdev))
4171 ixgbe_reset(adapter);
4172
4173 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4174 if (hw->mac.ops.disable_tx_laser &&
4175 ((hw->phy.multispeed_fiber) ||
4176 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4177 (hw->mac.type == ixgbe_mac_82599EB))))
4178 hw->mac.ops.disable_tx_laser(hw);
4179
4180 ixgbe_clean_all_tx_rings(adapter);
4181 ixgbe_clean_all_rx_rings(adapter);
4182
4183 #ifdef CONFIG_IXGBE_DCA
4184 /* since we reset the hardware DCA settings were cleared */
4185 ixgbe_setup_dca(adapter);
4186 #endif
4187 }
4188
4189 /**
4190 * ixgbe_poll - NAPI Rx polling callback
4191 * @napi: structure for representing this polling device
4192 * @budget: how many packets driver is allowed to clean
4193 *
4194 * This function is used for legacy and MSI, NAPI mode
4195 **/
4196 static int ixgbe_poll(struct napi_struct *napi, int budget)
4197 {
4198 struct ixgbe_q_vector *q_vector =
4199 container_of(napi, struct ixgbe_q_vector, napi);
4200 struct ixgbe_adapter *adapter = q_vector->adapter;
4201 int tx_clean_complete, work_done = 0;
4202
4203 #ifdef CONFIG_IXGBE_DCA
4204 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4205 ixgbe_update_dca(q_vector);
4206 #endif
4207
4208 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4209 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
4210
4211 if (!tx_clean_complete)
4212 work_done = budget;
4213
4214 /* If budget not fully consumed, exit the polling mode */
4215 if (work_done < budget) {
4216 napi_complete(napi);
4217 if (adapter->rx_itr_setting & 1)
4218 ixgbe_set_itr(adapter);
4219 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4220 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
4221 }
4222 return work_done;
4223 }
4224
4225 /**
4226 * ixgbe_tx_timeout - Respond to a Tx Hang
4227 * @netdev: network interface device structure
4228 **/
4229 static void ixgbe_tx_timeout(struct net_device *netdev)
4230 {
4231 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4232
4233 adapter->tx_timeout_count++;
4234
4235 /* Do the reset outside of interrupt context */
4236 schedule_work(&adapter->reset_task);
4237 }
4238
4239 static void ixgbe_reset_task(struct work_struct *work)
4240 {
4241 struct ixgbe_adapter *adapter;
4242 adapter = container_of(work, struct ixgbe_adapter, reset_task);
4243
4244 /* If we're already down or resetting, just bail */
4245 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
4246 test_bit(__IXGBE_RESETTING, &adapter->state))
4247 return;
4248
4249 ixgbe_dump(adapter);
4250 netdev_err(adapter->netdev, "Reset adapter\n");
4251 ixgbe_reinit_locked(adapter);
4252 }
4253
4254 #ifdef CONFIG_IXGBE_DCB
4255 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4256 {
4257 bool ret = false;
4258 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
4259
4260 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4261 return ret;
4262
4263 f->mask = 0x7 << 3;
4264 adapter->num_rx_queues = f->indices;
4265 adapter->num_tx_queues = f->indices;
4266 ret = true;
4267
4268 return ret;
4269 }
4270 #endif
4271
4272 /**
4273 * ixgbe_set_rss_queues: Allocate queues for RSS
4274 * @adapter: board private structure to initialize
4275 *
4276 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4277 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4278 *
4279 **/
4280 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4281 {
4282 bool ret = false;
4283 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4284
4285 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4286 f->mask = 0xF;
4287 adapter->num_rx_queues = f->indices;
4288 adapter->num_tx_queues = f->indices;
4289 ret = true;
4290 } else {
4291 ret = false;
4292 }
4293
4294 return ret;
4295 }
4296
4297 /**
4298 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4299 * @adapter: board private structure to initialize
4300 *
4301 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4302 * to the original CPU that initiated the Tx session. This runs in addition
4303 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4304 * Rx load across CPUs using RSS.
4305 *
4306 **/
4307 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4308 {
4309 bool ret = false;
4310 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4311
4312 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4313 f_fdir->mask = 0;
4314
4315 /* Flow Director must have RSS enabled */
4316 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4317 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4318 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4319 adapter->num_tx_queues = f_fdir->indices;
4320 adapter->num_rx_queues = f_fdir->indices;
4321 ret = true;
4322 } else {
4323 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4324 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4325 }
4326 return ret;
4327 }
4328
4329 #ifdef IXGBE_FCOE
4330 /**
4331 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4332 * @adapter: board private structure to initialize
4333 *
4334 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4335 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4336 * rx queues out of the max number of rx queues, instead, it is used as the
4337 * index of the first rx queue used by FCoE.
4338 *
4339 **/
4340 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4341 {
4342 bool ret = false;
4343 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4344
4345 f->indices = min((int)num_online_cpus(), f->indices);
4346 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4347 adapter->num_rx_queues = 1;
4348 adapter->num_tx_queues = 1;
4349 #ifdef CONFIG_IXGBE_DCB
4350 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4351 e_info(probe, "FCoE enabled with DCB\n");
4352 ixgbe_set_dcb_queues(adapter);
4353 }
4354 #endif
4355 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4356 e_info(probe, "FCoE enabled with RSS\n");
4357 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4358 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4359 ixgbe_set_fdir_queues(adapter);
4360 else
4361 ixgbe_set_rss_queues(adapter);
4362 }
4363 /* adding FCoE rx rings to the end */
4364 f->mask = adapter->num_rx_queues;
4365 adapter->num_rx_queues += f->indices;
4366 adapter->num_tx_queues += f->indices;
4367
4368 ret = true;
4369 }
4370
4371 return ret;
4372 }
4373
4374 #endif /* IXGBE_FCOE */
4375 /**
4376 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4377 * @adapter: board private structure to initialize
4378 *
4379 * IOV doesn't actually use anything, so just NAK the
4380 * request for now and let the other queue routines
4381 * figure out what to do.
4382 */
4383 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4384 {
4385 return false;
4386 }
4387
4388 /*
4389 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4390 * @adapter: board private structure to initialize
4391 *
4392 * This is the top level queue allocation routine. The order here is very
4393 * important, starting with the "most" number of features turned on at once,
4394 * and ending with the smallest set of features. This way large combinations
4395 * can be allocated if they're turned on, and smaller combinations are the
4396 * fallthrough conditions.
4397 *
4398 **/
4399 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4400 {
4401 /* Start with base case */
4402 adapter->num_rx_queues = 1;
4403 adapter->num_tx_queues = 1;
4404 adapter->num_rx_pools = adapter->num_rx_queues;
4405 adapter->num_rx_queues_per_pool = 1;
4406
4407 if (ixgbe_set_sriov_queues(adapter))
4408 goto done;
4409
4410 #ifdef IXGBE_FCOE
4411 if (ixgbe_set_fcoe_queues(adapter))
4412 goto done;
4413
4414 #endif /* IXGBE_FCOE */
4415 #ifdef CONFIG_IXGBE_DCB
4416 if (ixgbe_set_dcb_queues(adapter))
4417 goto done;
4418
4419 #endif
4420 if (ixgbe_set_fdir_queues(adapter))
4421 goto done;
4422
4423 if (ixgbe_set_rss_queues(adapter))
4424 goto done;
4425
4426 /* fallback to base case */
4427 adapter->num_rx_queues = 1;
4428 adapter->num_tx_queues = 1;
4429
4430 done:
4431 /* Notify the stack of the (possibly) reduced queue counts. */
4432 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4433 return netif_set_real_num_rx_queues(adapter->netdev,
4434 adapter->num_rx_queues);
4435 }
4436
4437 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4438 int vectors)
4439 {
4440 int err, vector_threshold;
4441
4442 /* We'll want at least 3 (vector_threshold):
4443 * 1) TxQ[0] Cleanup
4444 * 2) RxQ[0] Cleanup
4445 * 3) Other (Link Status Change, etc.)
4446 * 4) TCP Timer (optional)
4447 */
4448 vector_threshold = MIN_MSIX_COUNT;
4449
4450 /* The more we get, the more we will assign to Tx/Rx Cleanup
4451 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4452 * Right now, we simply care about how many we'll get; we'll
4453 * set them up later while requesting irq's.
4454 */
4455 while (vectors >= vector_threshold) {
4456 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4457 vectors);
4458 if (!err) /* Success in acquiring all requested vectors. */
4459 break;
4460 else if (err < 0)
4461 vectors = 0; /* Nasty failure, quit now */
4462 else /* err == number of vectors we should try again with */
4463 vectors = err;
4464 }
4465
4466 if (vectors < vector_threshold) {
4467 /* Can't allocate enough MSI-X interrupts? Oh well.
4468 * This just means we'll go with either a single MSI
4469 * vector or fall back to legacy interrupts.
4470 */
4471 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4472 "Unable to allocate MSI-X interrupts\n");
4473 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4474 kfree(adapter->msix_entries);
4475 adapter->msix_entries = NULL;
4476 } else {
4477 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4478 /*
4479 * Adjust for only the vectors we'll use, which is minimum
4480 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4481 * vectors we were allocated.
4482 */
4483 adapter->num_msix_vectors = min(vectors,
4484 adapter->max_msix_q_vectors + NON_Q_VECTORS);
4485 }
4486 }
4487
4488 /**
4489 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4490 * @adapter: board private structure to initialize
4491 *
4492 * Cache the descriptor ring offsets for RSS to the assigned rings.
4493 *
4494 **/
4495 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4496 {
4497 int i;
4498
4499 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4500 return false;
4501
4502 for (i = 0; i < adapter->num_rx_queues; i++)
4503 adapter->rx_ring[i]->reg_idx = i;
4504 for (i = 0; i < adapter->num_tx_queues; i++)
4505 adapter->tx_ring[i]->reg_idx = i;
4506
4507 return true;
4508 }
4509
4510 #ifdef CONFIG_IXGBE_DCB
4511 /**
4512 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4513 * @adapter: board private structure to initialize
4514 *
4515 * Cache the descriptor ring offsets for DCB to the assigned rings.
4516 *
4517 **/
4518 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4519 {
4520 int i;
4521 bool ret = false;
4522 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4523
4524 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4525 return false;
4526
4527 /* the number of queues is assumed to be symmetric */
4528 switch (adapter->hw.mac.type) {
4529 case ixgbe_mac_82598EB:
4530 for (i = 0; i < dcb_i; i++) {
4531 adapter->rx_ring[i]->reg_idx = i << 3;
4532 adapter->tx_ring[i]->reg_idx = i << 2;
4533 }
4534 ret = true;
4535 break;
4536 case ixgbe_mac_82599EB:
4537 case ixgbe_mac_X540:
4538 if (dcb_i == 8) {
4539 /*
4540 * Tx TC0 starts at: descriptor queue 0
4541 * Tx TC1 starts at: descriptor queue 32
4542 * Tx TC2 starts at: descriptor queue 64
4543 * Tx TC3 starts at: descriptor queue 80
4544 * Tx TC4 starts at: descriptor queue 96
4545 * Tx TC5 starts at: descriptor queue 104
4546 * Tx TC6 starts at: descriptor queue 112
4547 * Tx TC7 starts at: descriptor queue 120
4548 *
4549 * Rx TC0-TC7 are offset by 16 queues each
4550 */
4551 for (i = 0; i < 3; i++) {
4552 adapter->tx_ring[i]->reg_idx = i << 5;
4553 adapter->rx_ring[i]->reg_idx = i << 4;
4554 }
4555 for ( ; i < 5; i++) {
4556 adapter->tx_ring[i]->reg_idx = ((i + 2) << 4);
4557 adapter->rx_ring[i]->reg_idx = i << 4;
4558 }
4559 for ( ; i < dcb_i; i++) {
4560 adapter->tx_ring[i]->reg_idx = ((i + 8) << 3);
4561 adapter->rx_ring[i]->reg_idx = i << 4;
4562 }
4563 ret = true;
4564 } else if (dcb_i == 4) {
4565 /*
4566 * Tx TC0 starts at: descriptor queue 0
4567 * Tx TC1 starts at: descriptor queue 64
4568 * Tx TC2 starts at: descriptor queue 96
4569 * Tx TC3 starts at: descriptor queue 112
4570 *
4571 * Rx TC0-TC3 are offset by 32 queues each
4572 */
4573 adapter->tx_ring[0]->reg_idx = 0;
4574 adapter->tx_ring[1]->reg_idx = 64;
4575 adapter->tx_ring[2]->reg_idx = 96;
4576 adapter->tx_ring[3]->reg_idx = 112;
4577 for (i = 0 ; i < dcb_i; i++)
4578 adapter->rx_ring[i]->reg_idx = i << 5;
4579 ret = true;
4580 }
4581 break;
4582 default:
4583 break;
4584 }
4585 return ret;
4586 }
4587 #endif
4588
4589 /**
4590 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4591 * @adapter: board private structure to initialize
4592 *
4593 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4594 *
4595 **/
4596 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4597 {
4598 int i;
4599 bool ret = false;
4600
4601 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4602 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4603 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4604 for (i = 0; i < adapter->num_rx_queues; i++)
4605 adapter->rx_ring[i]->reg_idx = i;
4606 for (i = 0; i < adapter->num_tx_queues; i++)
4607 adapter->tx_ring[i]->reg_idx = i;
4608 ret = true;
4609 }
4610
4611 return ret;
4612 }
4613
4614 #ifdef IXGBE_FCOE
4615 /**
4616 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4617 * @adapter: board private structure to initialize
4618 *
4619 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4620 *
4621 */
4622 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4623 {
4624 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4625 int i;
4626 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4627
4628 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4629 return false;
4630
4631 #ifdef CONFIG_IXGBE_DCB
4632 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4633 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4634
4635 ixgbe_cache_ring_dcb(adapter);
4636 /* find out queues in TC for FCoE */
4637 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4638 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4639 /*
4640 * In 82599, the number of Tx queues for each traffic
4641 * class for both 8-TC and 4-TC modes are:
4642 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4643 * 8 TCs: 32 32 16 16 8 8 8 8
4644 * 4 TCs: 64 64 32 32
4645 * We have max 8 queues for FCoE, where 8 the is
4646 * FCoE redirection table size. If TC for FCoE is
4647 * less than or equal to TC3, we have enough queues
4648 * to add max of 8 queues for FCoE, so we start FCoE
4649 * Tx queue from the next one, i.e., reg_idx + 1.
4650 * If TC for FCoE is above TC3, implying 8 TC mode,
4651 * and we need 8 for FCoE, we have to take all queues
4652 * in that traffic class for FCoE.
4653 */
4654 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4655 fcoe_tx_i--;
4656 }
4657 #endif /* CONFIG_IXGBE_DCB */
4658 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4659 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4660 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4661 ixgbe_cache_ring_fdir(adapter);
4662 else
4663 ixgbe_cache_ring_rss(adapter);
4664
4665 fcoe_rx_i = f->mask;
4666 fcoe_tx_i = f->mask;
4667 }
4668 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4669 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4670 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4671 }
4672 return true;
4673 }
4674
4675 #endif /* IXGBE_FCOE */
4676 /**
4677 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4678 * @adapter: board private structure to initialize
4679 *
4680 * SR-IOV doesn't use any descriptor rings but changes the default if
4681 * no other mapping is used.
4682 *
4683 */
4684 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4685 {
4686 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4687 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4688 if (adapter->num_vfs)
4689 return true;
4690 else
4691 return false;
4692 }
4693
4694 /**
4695 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4696 * @adapter: board private structure to initialize
4697 *
4698 * Once we know the feature-set enabled for the device, we'll cache
4699 * the register offset the descriptor ring is assigned to.
4700 *
4701 * Note, the order the various feature calls is important. It must start with
4702 * the "most" features enabled at the same time, then trickle down to the
4703 * least amount of features turned on at once.
4704 **/
4705 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4706 {
4707 /* start with default case */
4708 adapter->rx_ring[0]->reg_idx = 0;
4709 adapter->tx_ring[0]->reg_idx = 0;
4710
4711 if (ixgbe_cache_ring_sriov(adapter))
4712 return;
4713
4714 #ifdef IXGBE_FCOE
4715 if (ixgbe_cache_ring_fcoe(adapter))
4716 return;
4717
4718 #endif /* IXGBE_FCOE */
4719 #ifdef CONFIG_IXGBE_DCB
4720 if (ixgbe_cache_ring_dcb(adapter))
4721 return;
4722
4723 #endif
4724 if (ixgbe_cache_ring_fdir(adapter))
4725 return;
4726
4727 if (ixgbe_cache_ring_rss(adapter))
4728 return;
4729 }
4730
4731 /**
4732 * ixgbe_alloc_queues - Allocate memory for all rings
4733 * @adapter: board private structure to initialize
4734 *
4735 * We allocate one ring per queue at run-time since we don't know the
4736 * number of queues at compile-time. The polling_netdev array is
4737 * intended for Multiqueue, but should work fine with a single queue.
4738 **/
4739 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4740 {
4741 int rx = 0, tx = 0, nid = adapter->node;
4742
4743 if (nid < 0 || !node_online(nid))
4744 nid = first_online_node;
4745
4746 for (; tx < adapter->num_tx_queues; tx++) {
4747 struct ixgbe_ring *ring;
4748
4749 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4750 if (!ring)
4751 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4752 if (!ring)
4753 goto err_allocation;
4754 ring->count = adapter->tx_ring_count;
4755 ring->queue_index = tx;
4756 ring->numa_node = nid;
4757 ring->dev = &adapter->pdev->dev;
4758 ring->netdev = adapter->netdev;
4759
4760 adapter->tx_ring[tx] = ring;
4761 }
4762
4763 for (; rx < adapter->num_rx_queues; rx++) {
4764 struct ixgbe_ring *ring;
4765
4766 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4767 if (!ring)
4768 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4769 if (!ring)
4770 goto err_allocation;
4771 ring->count = adapter->rx_ring_count;
4772 ring->queue_index = rx;
4773 ring->numa_node = nid;
4774 ring->dev = &adapter->pdev->dev;
4775 ring->netdev = adapter->netdev;
4776
4777 adapter->rx_ring[rx] = ring;
4778 }
4779
4780 ixgbe_cache_ring_register(adapter);
4781
4782 return 0;
4783
4784 err_allocation:
4785 while (tx)
4786 kfree(adapter->tx_ring[--tx]);
4787
4788 while (rx)
4789 kfree(adapter->rx_ring[--rx]);
4790 return -ENOMEM;
4791 }
4792
4793 /**
4794 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4795 * @adapter: board private structure to initialize
4796 *
4797 * Attempt to configure the interrupts using the best available
4798 * capabilities of the hardware and the kernel.
4799 **/
4800 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4801 {
4802 struct ixgbe_hw *hw = &adapter->hw;
4803 int err = 0;
4804 int vector, v_budget;
4805
4806 /*
4807 * It's easy to be greedy for MSI-X vectors, but it really
4808 * doesn't do us much good if we have a lot more vectors
4809 * than CPU's. So let's be conservative and only ask for
4810 * (roughly) the same number of vectors as there are CPU's.
4811 */
4812 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4813 (int)num_online_cpus()) + NON_Q_VECTORS;
4814
4815 /*
4816 * At the same time, hardware can only support a maximum of
4817 * hw.mac->max_msix_vectors vectors. With features
4818 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4819 * descriptor queues supported by our device. Thus, we cap it off in
4820 * those rare cases where the cpu count also exceeds our vector limit.
4821 */
4822 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4823
4824 /* A failure in MSI-X entry allocation isn't fatal, but it does
4825 * mean we disable MSI-X capabilities of the adapter. */
4826 adapter->msix_entries = kcalloc(v_budget,
4827 sizeof(struct msix_entry), GFP_KERNEL);
4828 if (adapter->msix_entries) {
4829 for (vector = 0; vector < v_budget; vector++)
4830 adapter->msix_entries[vector].entry = vector;
4831
4832 ixgbe_acquire_msix_vectors(adapter, v_budget);
4833
4834 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4835 goto out;
4836 }
4837
4838 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4839 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4840 if (adapter->flags & (IXGBE_FLAG_FDIR_HASH_CAPABLE |
4841 IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
4842 e_err(probe,
4843 "Flow Director is not supported while multiple "
4844 "queues are disabled. Disabling Flow Director\n");
4845 }
4846 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4847 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4848 adapter->atr_sample_rate = 0;
4849 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4850 ixgbe_disable_sriov(adapter);
4851
4852 err = ixgbe_set_num_queues(adapter);
4853 if (err)
4854 return err;
4855
4856 err = pci_enable_msi(adapter->pdev);
4857 if (!err) {
4858 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4859 } else {
4860 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4861 "Unable to allocate MSI interrupt, "
4862 "falling back to legacy. Error: %d\n", err);
4863 /* reset err */
4864 err = 0;
4865 }
4866
4867 out:
4868 return err;
4869 }
4870
4871 /**
4872 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4873 * @adapter: board private structure to initialize
4874 *
4875 * We allocate one q_vector per queue interrupt. If allocation fails we
4876 * return -ENOMEM.
4877 **/
4878 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4879 {
4880 int q_idx, num_q_vectors;
4881 struct ixgbe_q_vector *q_vector;
4882 int (*poll)(struct napi_struct *, int);
4883
4884 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4885 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4886 poll = &ixgbe_clean_rxtx_many;
4887 } else {
4888 num_q_vectors = 1;
4889 poll = &ixgbe_poll;
4890 }
4891
4892 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4893 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4894 GFP_KERNEL, adapter->node);
4895 if (!q_vector)
4896 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4897 GFP_KERNEL);
4898 if (!q_vector)
4899 goto err_out;
4900 q_vector->adapter = adapter;
4901 if (q_vector->txr_count && !q_vector->rxr_count)
4902 q_vector->eitr = adapter->tx_eitr_param;
4903 else
4904 q_vector->eitr = adapter->rx_eitr_param;
4905 q_vector->v_idx = q_idx;
4906 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4907 adapter->q_vector[q_idx] = q_vector;
4908 }
4909
4910 return 0;
4911
4912 err_out:
4913 while (q_idx) {
4914 q_idx--;
4915 q_vector = adapter->q_vector[q_idx];
4916 netif_napi_del(&q_vector->napi);
4917 kfree(q_vector);
4918 adapter->q_vector[q_idx] = NULL;
4919 }
4920 return -ENOMEM;
4921 }
4922
4923 /**
4924 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4925 * @adapter: board private structure to initialize
4926 *
4927 * This function frees the memory allocated to the q_vectors. In addition if
4928 * NAPI is enabled it will delete any references to the NAPI struct prior
4929 * to freeing the q_vector.
4930 **/
4931 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4932 {
4933 int q_idx, num_q_vectors;
4934
4935 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4936 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4937 else
4938 num_q_vectors = 1;
4939
4940 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4941 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4942 adapter->q_vector[q_idx] = NULL;
4943 netif_napi_del(&q_vector->napi);
4944 kfree(q_vector);
4945 }
4946 }
4947
4948 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4949 {
4950 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4951 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4952 pci_disable_msix(adapter->pdev);
4953 kfree(adapter->msix_entries);
4954 adapter->msix_entries = NULL;
4955 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4956 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4957 pci_disable_msi(adapter->pdev);
4958 }
4959 }
4960
4961 /**
4962 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4963 * @adapter: board private structure to initialize
4964 *
4965 * We determine which interrupt scheme to use based on...
4966 * - Kernel support (MSI, MSI-X)
4967 * - which can be user-defined (via MODULE_PARAM)
4968 * - Hardware queue count (num_*_queues)
4969 * - defined by miscellaneous hardware support/features (RSS, etc.)
4970 **/
4971 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4972 {
4973 int err;
4974
4975 /* Number of supported queues */
4976 err = ixgbe_set_num_queues(adapter);
4977 if (err)
4978 return err;
4979
4980 err = ixgbe_set_interrupt_capability(adapter);
4981 if (err) {
4982 e_dev_err("Unable to setup interrupt capabilities\n");
4983 goto err_set_interrupt;
4984 }
4985
4986 err = ixgbe_alloc_q_vectors(adapter);
4987 if (err) {
4988 e_dev_err("Unable to allocate memory for queue vectors\n");
4989 goto err_alloc_q_vectors;
4990 }
4991
4992 err = ixgbe_alloc_queues(adapter);
4993 if (err) {
4994 e_dev_err("Unable to allocate memory for queues\n");
4995 goto err_alloc_queues;
4996 }
4997
4998 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4999 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5000 adapter->num_rx_queues, adapter->num_tx_queues);
5001
5002 set_bit(__IXGBE_DOWN, &adapter->state);
5003
5004 return 0;
5005
5006 err_alloc_queues:
5007 ixgbe_free_q_vectors(adapter);
5008 err_alloc_q_vectors:
5009 ixgbe_reset_interrupt_capability(adapter);
5010 err_set_interrupt:
5011 return err;
5012 }
5013
5014 static void ring_free_rcu(struct rcu_head *head)
5015 {
5016 kfree(container_of(head, struct ixgbe_ring, rcu));
5017 }
5018
5019 /**
5020 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5021 * @adapter: board private structure to clear interrupt scheme on
5022 *
5023 * We go through and clear interrupt specific resources and reset the structure
5024 * to pre-load conditions
5025 **/
5026 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5027 {
5028 int i;
5029
5030 for (i = 0; i < adapter->num_tx_queues; i++) {
5031 kfree(adapter->tx_ring[i]);
5032 adapter->tx_ring[i] = NULL;
5033 }
5034 for (i = 0; i < adapter->num_rx_queues; i++) {
5035 struct ixgbe_ring *ring = adapter->rx_ring[i];
5036
5037 /* ixgbe_get_stats64() might access this ring, we must wait
5038 * a grace period before freeing it.
5039 */
5040 call_rcu(&ring->rcu, ring_free_rcu);
5041 adapter->rx_ring[i] = NULL;
5042 }
5043
5044 adapter->num_tx_queues = 0;
5045 adapter->num_rx_queues = 0;
5046
5047 ixgbe_free_q_vectors(adapter);
5048 ixgbe_reset_interrupt_capability(adapter);
5049 }
5050
5051 /**
5052 * ixgbe_sfp_timer - worker thread to find a missing module
5053 * @data: pointer to our adapter struct
5054 **/
5055 static void ixgbe_sfp_timer(unsigned long data)
5056 {
5057 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5058
5059 /*
5060 * Do the sfp_timer outside of interrupt context due to the
5061 * delays that sfp+ detection requires
5062 */
5063 schedule_work(&adapter->sfp_task);
5064 }
5065
5066 /**
5067 * ixgbe_sfp_task - worker thread to find a missing module
5068 * @work: pointer to work_struct containing our data
5069 **/
5070 static void ixgbe_sfp_task(struct work_struct *work)
5071 {
5072 struct ixgbe_adapter *adapter = container_of(work,
5073 struct ixgbe_adapter,
5074 sfp_task);
5075 struct ixgbe_hw *hw = &adapter->hw;
5076
5077 if ((hw->phy.type == ixgbe_phy_nl) &&
5078 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
5079 s32 ret = hw->phy.ops.identify_sfp(hw);
5080 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
5081 goto reschedule;
5082 ret = hw->phy.ops.reset(hw);
5083 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5084 e_dev_err("failed to initialize because an unsupported "
5085 "SFP+ module type was detected.\n");
5086 e_dev_err("Reload the driver after installing a "
5087 "supported module.\n");
5088 unregister_netdev(adapter->netdev);
5089 } else {
5090 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5091 }
5092 /* don't need this routine any more */
5093 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5094 }
5095 return;
5096 reschedule:
5097 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
5098 mod_timer(&adapter->sfp_timer,
5099 round_jiffies(jiffies + (2 * HZ)));
5100 }
5101
5102 /**
5103 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5104 * @adapter: board private structure to initialize
5105 *
5106 * ixgbe_sw_init initializes the Adapter private data structure.
5107 * Fields are initialized based on PCI device information and
5108 * OS network device settings (MTU size).
5109 **/
5110 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5111 {
5112 struct ixgbe_hw *hw = &adapter->hw;
5113 struct pci_dev *pdev = adapter->pdev;
5114 struct net_device *dev = adapter->netdev;
5115 unsigned int rss;
5116 #ifdef CONFIG_IXGBE_DCB
5117 int j;
5118 struct tc_configuration *tc;
5119 #endif
5120 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5121
5122 /* PCI config space info */
5123
5124 hw->vendor_id = pdev->vendor;
5125 hw->device_id = pdev->device;
5126 hw->revision_id = pdev->revision;
5127 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5128 hw->subsystem_device_id = pdev->subsystem_device;
5129
5130 /* Set capability flags */
5131 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5132 adapter->ring_feature[RING_F_RSS].indices = rss;
5133 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
5134 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
5135 switch (hw->mac.type) {
5136 case ixgbe_mac_82598EB:
5137 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5138 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5139 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
5140 break;
5141 case ixgbe_mac_82599EB:
5142 case ixgbe_mac_X540:
5143 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
5144 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5145 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5146 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5147 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5148 /* n-tuple support exists, always init our spinlock */
5149 spin_lock_init(&adapter->fdir_perfect_lock);
5150 /* Flow Director hash filters enabled */
5151 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5152 adapter->atr_sample_rate = 20;
5153 adapter->ring_feature[RING_F_FDIR].indices =
5154 IXGBE_MAX_FDIR_INDICES;
5155 adapter->fdir_pballoc = 0;
5156 #ifdef IXGBE_FCOE
5157 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5158 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5159 adapter->ring_feature[RING_F_FCOE].indices = 0;
5160 #ifdef CONFIG_IXGBE_DCB
5161 /* Default traffic class to use for FCoE */
5162 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
5163 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5164 #endif
5165 #endif /* IXGBE_FCOE */
5166 break;
5167 default:
5168 break;
5169 }
5170
5171 #ifdef CONFIG_IXGBE_DCB
5172 /* Configure DCB traffic classes */
5173 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5174 tc = &adapter->dcb_cfg.tc_config[j];
5175 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5176 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5177 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5178 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5179 tc->dcb_pfc = pfc_disabled;
5180 }
5181 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5182 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5183 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
5184 adapter->dcb_cfg.pfc_mode_enable = false;
5185 adapter->dcb_set_bitmap = 0x00;
5186 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5187 adapter->ring_feature[RING_F_DCB].indices);
5188
5189 #endif
5190
5191 /* default flow control settings */
5192 hw->fc.requested_mode = ixgbe_fc_full;
5193 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
5194 #ifdef CONFIG_DCB
5195 adapter->last_lfc_mode = hw->fc.current_mode;
5196 #endif
5197 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5198 hw->fc.low_water = FC_LOW_WATER(max_frame);
5199 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5200 hw->fc.send_xon = true;
5201 hw->fc.disable_fc_autoneg = false;
5202
5203 /* enable itr by default in dynamic mode */
5204 adapter->rx_itr_setting = 1;
5205 adapter->rx_eitr_param = 20000;
5206 adapter->tx_itr_setting = 1;
5207 adapter->tx_eitr_param = 10000;
5208
5209 /* set defaults for eitr in MegaBytes */
5210 adapter->eitr_low = 10;
5211 adapter->eitr_high = 20;
5212
5213 /* set default ring sizes */
5214 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5215 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5216
5217 /* initialize eeprom parameters */
5218 if (ixgbe_init_eeprom_params_generic(hw)) {
5219 e_dev_err("EEPROM initialization failed\n");
5220 return -EIO;
5221 }
5222
5223 /* enable rx csum by default */
5224 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5225
5226 /* get assigned NUMA node */
5227 adapter->node = dev_to_node(&pdev->dev);
5228
5229 set_bit(__IXGBE_DOWN, &adapter->state);
5230
5231 return 0;
5232 }
5233
5234 /**
5235 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5236 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5237 *
5238 * Return 0 on success, negative on failure
5239 **/
5240 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5241 {
5242 struct device *dev = tx_ring->dev;
5243 int size;
5244
5245 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5246 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
5247 if (!tx_ring->tx_buffer_info)
5248 tx_ring->tx_buffer_info = vzalloc(size);
5249 if (!tx_ring->tx_buffer_info)
5250 goto err;
5251
5252 /* round up to nearest 4K */
5253 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5254 tx_ring->size = ALIGN(tx_ring->size, 4096);
5255
5256 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5257 &tx_ring->dma, GFP_KERNEL);
5258 if (!tx_ring->desc)
5259 goto err;
5260
5261 tx_ring->next_to_use = 0;
5262 tx_ring->next_to_clean = 0;
5263 tx_ring->work_limit = tx_ring->count;
5264 return 0;
5265
5266 err:
5267 vfree(tx_ring->tx_buffer_info);
5268 tx_ring->tx_buffer_info = NULL;
5269 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5270 return -ENOMEM;
5271 }
5272
5273 /**
5274 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5275 * @adapter: board private structure
5276 *
5277 * If this function returns with an error, then it's possible one or
5278 * more of the rings is populated (while the rest are not). It is the
5279 * callers duty to clean those orphaned rings.
5280 *
5281 * Return 0 on success, negative on failure
5282 **/
5283 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5284 {
5285 int i, err = 0;
5286
5287 for (i = 0; i < adapter->num_tx_queues; i++) {
5288 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5289 if (!err)
5290 continue;
5291 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5292 break;
5293 }
5294
5295 return err;
5296 }
5297
5298 /**
5299 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5300 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5301 *
5302 * Returns 0 on success, negative on failure
5303 **/
5304 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5305 {
5306 struct device *dev = rx_ring->dev;
5307 int size;
5308
5309 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5310 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5311 if (!rx_ring->rx_buffer_info)
5312 rx_ring->rx_buffer_info = vzalloc(size);
5313 if (!rx_ring->rx_buffer_info)
5314 goto err;
5315
5316 /* Round up to nearest 4K */
5317 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5318 rx_ring->size = ALIGN(rx_ring->size, 4096);
5319
5320 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5321 &rx_ring->dma, GFP_KERNEL);
5322
5323 if (!rx_ring->desc)
5324 goto err;
5325
5326 rx_ring->next_to_clean = 0;
5327 rx_ring->next_to_use = 0;
5328
5329 return 0;
5330 err:
5331 vfree(rx_ring->rx_buffer_info);
5332 rx_ring->rx_buffer_info = NULL;
5333 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5334 return -ENOMEM;
5335 }
5336
5337 /**
5338 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5339 * @adapter: board private structure
5340 *
5341 * If this function returns with an error, then it's possible one or
5342 * more of the rings is populated (while the rest are not). It is the
5343 * callers duty to clean those orphaned rings.
5344 *
5345 * Return 0 on success, negative on failure
5346 **/
5347 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5348 {
5349 int i, err = 0;
5350
5351 for (i = 0; i < adapter->num_rx_queues; i++) {
5352 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5353 if (!err)
5354 continue;
5355 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5356 break;
5357 }
5358
5359 return err;
5360 }
5361
5362 /**
5363 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5364 * @tx_ring: Tx descriptor ring for a specific queue
5365 *
5366 * Free all transmit software resources
5367 **/
5368 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5369 {
5370 ixgbe_clean_tx_ring(tx_ring);
5371
5372 vfree(tx_ring->tx_buffer_info);
5373 tx_ring->tx_buffer_info = NULL;
5374
5375 /* if not set, then don't free */
5376 if (!tx_ring->desc)
5377 return;
5378
5379 dma_free_coherent(tx_ring->dev, tx_ring->size,
5380 tx_ring->desc, tx_ring->dma);
5381
5382 tx_ring->desc = NULL;
5383 }
5384
5385 /**
5386 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5387 * @adapter: board private structure
5388 *
5389 * Free all transmit software resources
5390 **/
5391 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5392 {
5393 int i;
5394
5395 for (i = 0; i < adapter->num_tx_queues; i++)
5396 if (adapter->tx_ring[i]->desc)
5397 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5398 }
5399
5400 /**
5401 * ixgbe_free_rx_resources - Free Rx Resources
5402 * @rx_ring: ring to clean the resources from
5403 *
5404 * Free all receive software resources
5405 **/
5406 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5407 {
5408 ixgbe_clean_rx_ring(rx_ring);
5409
5410 vfree(rx_ring->rx_buffer_info);
5411 rx_ring->rx_buffer_info = NULL;
5412
5413 /* if not set, then don't free */
5414 if (!rx_ring->desc)
5415 return;
5416
5417 dma_free_coherent(rx_ring->dev, rx_ring->size,
5418 rx_ring->desc, rx_ring->dma);
5419
5420 rx_ring->desc = NULL;
5421 }
5422
5423 /**
5424 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5425 * @adapter: board private structure
5426 *
5427 * Free all receive software resources
5428 **/
5429 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5430 {
5431 int i;
5432
5433 for (i = 0; i < adapter->num_rx_queues; i++)
5434 if (adapter->rx_ring[i]->desc)
5435 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5436 }
5437
5438 /**
5439 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5440 * @netdev: network interface device structure
5441 * @new_mtu: new value for maximum frame size
5442 *
5443 * Returns 0 on success, negative on failure
5444 **/
5445 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5446 {
5447 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5448 struct ixgbe_hw *hw = &adapter->hw;
5449 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5450
5451 /* MTU < 68 is an error and causes problems on some kernels */
5452 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5453 hw->mac.type != ixgbe_mac_X540) {
5454 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5455 return -EINVAL;
5456 } else {
5457 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5458 return -EINVAL;
5459 }
5460
5461 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5462 /* must set new MTU before calling down or up */
5463 netdev->mtu = new_mtu;
5464
5465 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5466 hw->fc.low_water = FC_LOW_WATER(max_frame);
5467
5468 if (netif_running(netdev))
5469 ixgbe_reinit_locked(adapter);
5470
5471 return 0;
5472 }
5473
5474 /**
5475 * ixgbe_open - Called when a network interface is made active
5476 * @netdev: network interface device structure
5477 *
5478 * Returns 0 on success, negative value on failure
5479 *
5480 * The open entry point is called when a network interface is made
5481 * active by the system (IFF_UP). At this point all resources needed
5482 * for transmit and receive operations are allocated, the interrupt
5483 * handler is registered with the OS, the watchdog timer is started,
5484 * and the stack is notified that the interface is ready.
5485 **/
5486 static int ixgbe_open(struct net_device *netdev)
5487 {
5488 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5489 int err;
5490
5491 /* disallow open during test */
5492 if (test_bit(__IXGBE_TESTING, &adapter->state))
5493 return -EBUSY;
5494
5495 netif_carrier_off(netdev);
5496
5497 /* allocate transmit descriptors */
5498 err = ixgbe_setup_all_tx_resources(adapter);
5499 if (err)
5500 goto err_setup_tx;
5501
5502 /* allocate receive descriptors */
5503 err = ixgbe_setup_all_rx_resources(adapter);
5504 if (err)
5505 goto err_setup_rx;
5506
5507 ixgbe_configure(adapter);
5508
5509 err = ixgbe_request_irq(adapter);
5510 if (err)
5511 goto err_req_irq;
5512
5513 err = ixgbe_up_complete(adapter);
5514 if (err)
5515 goto err_up;
5516
5517 netif_tx_start_all_queues(netdev);
5518
5519 return 0;
5520
5521 err_up:
5522 ixgbe_release_hw_control(adapter);
5523 ixgbe_free_irq(adapter);
5524 err_req_irq:
5525 err_setup_rx:
5526 ixgbe_free_all_rx_resources(adapter);
5527 err_setup_tx:
5528 ixgbe_free_all_tx_resources(adapter);
5529 ixgbe_reset(adapter);
5530
5531 return err;
5532 }
5533
5534 /**
5535 * ixgbe_close - Disables a network interface
5536 * @netdev: network interface device structure
5537 *
5538 * Returns 0, this is not allowed to fail
5539 *
5540 * The close entry point is called when an interface is de-activated
5541 * by the OS. The hardware is still under the drivers control, but
5542 * needs to be disabled. A global MAC reset is issued to stop the
5543 * hardware, and all transmit and receive resources are freed.
5544 **/
5545 static int ixgbe_close(struct net_device *netdev)
5546 {
5547 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5548
5549 ixgbe_down(adapter);
5550 ixgbe_free_irq(adapter);
5551
5552 ixgbe_free_all_tx_resources(adapter);
5553 ixgbe_free_all_rx_resources(adapter);
5554
5555 ixgbe_release_hw_control(adapter);
5556
5557 return 0;
5558 }
5559
5560 #ifdef CONFIG_PM
5561 static int ixgbe_resume(struct pci_dev *pdev)
5562 {
5563 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5564 struct net_device *netdev = adapter->netdev;
5565 u32 err;
5566
5567 pci_set_power_state(pdev, PCI_D0);
5568 pci_restore_state(pdev);
5569 /*
5570 * pci_restore_state clears dev->state_saved so call
5571 * pci_save_state to restore it.
5572 */
5573 pci_save_state(pdev);
5574
5575 err = pci_enable_device_mem(pdev);
5576 if (err) {
5577 e_dev_err("Cannot enable PCI device from suspend\n");
5578 return err;
5579 }
5580 pci_set_master(pdev);
5581
5582 pci_wake_from_d3(pdev, false);
5583
5584 err = ixgbe_init_interrupt_scheme(adapter);
5585 if (err) {
5586 e_dev_err("Cannot initialize interrupts for device\n");
5587 return err;
5588 }
5589
5590 ixgbe_reset(adapter);
5591
5592 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5593
5594 if (netif_running(netdev)) {
5595 err = ixgbe_open(netdev);
5596 if (err)
5597 return err;
5598 }
5599
5600 netif_device_attach(netdev);
5601
5602 return 0;
5603 }
5604 #endif /* CONFIG_PM */
5605
5606 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5607 {
5608 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5609 struct net_device *netdev = adapter->netdev;
5610 struct ixgbe_hw *hw = &adapter->hw;
5611 u32 ctrl, fctrl;
5612 u32 wufc = adapter->wol;
5613 #ifdef CONFIG_PM
5614 int retval = 0;
5615 #endif
5616
5617 netif_device_detach(netdev);
5618
5619 if (netif_running(netdev)) {
5620 ixgbe_down(adapter);
5621 ixgbe_free_irq(adapter);
5622 ixgbe_free_all_tx_resources(adapter);
5623 ixgbe_free_all_rx_resources(adapter);
5624 }
5625
5626 ixgbe_clear_interrupt_scheme(adapter);
5627 #ifdef CONFIG_DCB
5628 kfree(adapter->ixgbe_ieee_pfc);
5629 kfree(adapter->ixgbe_ieee_ets);
5630 #endif
5631
5632 #ifdef CONFIG_PM
5633 retval = pci_save_state(pdev);
5634 if (retval)
5635 return retval;
5636
5637 #endif
5638 if (wufc) {
5639 ixgbe_set_rx_mode(netdev);
5640
5641 /* turn on all-multi mode if wake on multicast is enabled */
5642 if (wufc & IXGBE_WUFC_MC) {
5643 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5644 fctrl |= IXGBE_FCTRL_MPE;
5645 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5646 }
5647
5648 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5649 ctrl |= IXGBE_CTRL_GIO_DIS;
5650 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5651
5652 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5653 } else {
5654 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5655 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5656 }
5657
5658 switch (hw->mac.type) {
5659 case ixgbe_mac_82598EB:
5660 pci_wake_from_d3(pdev, false);
5661 break;
5662 case ixgbe_mac_82599EB:
5663 case ixgbe_mac_X540:
5664 pci_wake_from_d3(pdev, !!wufc);
5665 break;
5666 default:
5667 break;
5668 }
5669
5670 *enable_wake = !!wufc;
5671
5672 ixgbe_release_hw_control(adapter);
5673
5674 pci_disable_device(pdev);
5675
5676 return 0;
5677 }
5678
5679 #ifdef CONFIG_PM
5680 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5681 {
5682 int retval;
5683 bool wake;
5684
5685 retval = __ixgbe_shutdown(pdev, &wake);
5686 if (retval)
5687 return retval;
5688
5689 if (wake) {
5690 pci_prepare_to_sleep(pdev);
5691 } else {
5692 pci_wake_from_d3(pdev, false);
5693 pci_set_power_state(pdev, PCI_D3hot);
5694 }
5695
5696 return 0;
5697 }
5698 #endif /* CONFIG_PM */
5699
5700 static void ixgbe_shutdown(struct pci_dev *pdev)
5701 {
5702 bool wake;
5703
5704 __ixgbe_shutdown(pdev, &wake);
5705
5706 if (system_state == SYSTEM_POWER_OFF) {
5707 pci_wake_from_d3(pdev, wake);
5708 pci_set_power_state(pdev, PCI_D3hot);
5709 }
5710 }
5711
5712 /**
5713 * ixgbe_update_stats - Update the board statistics counters.
5714 * @adapter: board private structure
5715 **/
5716 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5717 {
5718 struct net_device *netdev = adapter->netdev;
5719 struct ixgbe_hw *hw = &adapter->hw;
5720 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5721 u64 total_mpc = 0;
5722 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5723 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5724 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5725 u64 bytes = 0, packets = 0;
5726
5727 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5728 test_bit(__IXGBE_RESETTING, &adapter->state))
5729 return;
5730
5731 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5732 u64 rsc_count = 0;
5733 u64 rsc_flush = 0;
5734 for (i = 0; i < 16; i++)
5735 adapter->hw_rx_no_dma_resources +=
5736 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5737 for (i = 0; i < adapter->num_rx_queues; i++) {
5738 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5739 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5740 }
5741 adapter->rsc_total_count = rsc_count;
5742 adapter->rsc_total_flush = rsc_flush;
5743 }
5744
5745 for (i = 0; i < adapter->num_rx_queues; i++) {
5746 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5747 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5748 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5749 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5750 bytes += rx_ring->stats.bytes;
5751 packets += rx_ring->stats.packets;
5752 }
5753 adapter->non_eop_descs = non_eop_descs;
5754 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5755 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5756 netdev->stats.rx_bytes = bytes;
5757 netdev->stats.rx_packets = packets;
5758
5759 bytes = 0;
5760 packets = 0;
5761 /* gather some stats to the adapter struct that are per queue */
5762 for (i = 0; i < adapter->num_tx_queues; i++) {
5763 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5764 restart_queue += tx_ring->tx_stats.restart_queue;
5765 tx_busy += tx_ring->tx_stats.tx_busy;
5766 bytes += tx_ring->stats.bytes;
5767 packets += tx_ring->stats.packets;
5768 }
5769 adapter->restart_queue = restart_queue;
5770 adapter->tx_busy = tx_busy;
5771 netdev->stats.tx_bytes = bytes;
5772 netdev->stats.tx_packets = packets;
5773
5774 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5775 for (i = 0; i < 8; i++) {
5776 /* for packet buffers not used, the register should read 0 */
5777 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5778 missed_rx += mpc;
5779 hwstats->mpc[i] += mpc;
5780 total_mpc += hwstats->mpc[i];
5781 if (hw->mac.type == ixgbe_mac_82598EB)
5782 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5783 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5784 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5785 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5786 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5787 switch (hw->mac.type) {
5788 case ixgbe_mac_82598EB:
5789 hwstats->pxonrxc[i] +=
5790 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5791 break;
5792 case ixgbe_mac_82599EB:
5793 case ixgbe_mac_X540:
5794 hwstats->pxonrxc[i] +=
5795 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5796 break;
5797 default:
5798 break;
5799 }
5800 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5801 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5802 }
5803 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5804 /* work around hardware counting issue */
5805 hwstats->gprc -= missed_rx;
5806
5807 ixgbe_update_xoff_received(adapter);
5808
5809 /* 82598 hardware only has a 32 bit counter in the high register */
5810 switch (hw->mac.type) {
5811 case ixgbe_mac_82598EB:
5812 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5813 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5814 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5815 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5816 break;
5817 case ixgbe_mac_82599EB:
5818 case ixgbe_mac_X540:
5819 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5820 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5821 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5822 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5823 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5824 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5825 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5826 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5827 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5828 #ifdef IXGBE_FCOE
5829 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5830 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5831 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5832 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5833 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5834 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5835 #endif /* IXGBE_FCOE */
5836 break;
5837 default:
5838 break;
5839 }
5840 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5841 hwstats->bprc += bprc;
5842 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5843 if (hw->mac.type == ixgbe_mac_82598EB)
5844 hwstats->mprc -= bprc;
5845 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5846 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5847 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5848 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5849 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5850 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5851 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5852 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5853 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5854 hwstats->lxontxc += lxon;
5855 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5856 hwstats->lxofftxc += lxoff;
5857 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5858 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5859 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5860 /*
5861 * 82598 errata - tx of flow control packets is included in tx counters
5862 */
5863 xon_off_tot = lxon + lxoff;
5864 hwstats->gptc -= xon_off_tot;
5865 hwstats->mptc -= xon_off_tot;
5866 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5867 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5868 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5869 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5870 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5871 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5872 hwstats->ptc64 -= xon_off_tot;
5873 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5874 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5875 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5876 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5877 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5878 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5879
5880 /* Fill out the OS statistics structure */
5881 netdev->stats.multicast = hwstats->mprc;
5882
5883 /* Rx Errors */
5884 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5885 netdev->stats.rx_dropped = 0;
5886 netdev->stats.rx_length_errors = hwstats->rlec;
5887 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5888 netdev->stats.rx_missed_errors = total_mpc;
5889 }
5890
5891 /**
5892 * ixgbe_watchdog - Timer Call-back
5893 * @data: pointer to adapter cast into an unsigned long
5894 **/
5895 static void ixgbe_watchdog(unsigned long data)
5896 {
5897 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5898 struct ixgbe_hw *hw = &adapter->hw;
5899 u64 eics = 0;
5900 int i;
5901
5902 /*
5903 * Do the watchdog outside of interrupt context due to the lovely
5904 * delays that some of the newer hardware requires
5905 */
5906
5907 if (test_bit(__IXGBE_DOWN, &adapter->state))
5908 goto watchdog_short_circuit;
5909
5910 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5911 /*
5912 * for legacy and MSI interrupts don't set any bits
5913 * that are enabled for EIAM, because this operation
5914 * would set *both* EIMS and EICS for any bit in EIAM
5915 */
5916 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5917 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5918 goto watchdog_reschedule;
5919 }
5920
5921 /* get one bit for every active tx/rx interrupt vector */
5922 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5923 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5924 if (qv->rxr_count || qv->txr_count)
5925 eics |= ((u64)1 << i);
5926 }
5927
5928 /* Cause software interrupt to ensure rx rings are cleaned */
5929 ixgbe_irq_rearm_queues(adapter, eics);
5930
5931 watchdog_reschedule:
5932 /* Reset the timer */
5933 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5934
5935 watchdog_short_circuit:
5936 schedule_work(&adapter->watchdog_task);
5937 }
5938
5939 /**
5940 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5941 * @work: pointer to work_struct containing our data
5942 **/
5943 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5944 {
5945 struct ixgbe_adapter *adapter = container_of(work,
5946 struct ixgbe_adapter,
5947 multispeed_fiber_task);
5948 struct ixgbe_hw *hw = &adapter->hw;
5949 u32 autoneg;
5950 bool negotiation;
5951
5952 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5953 autoneg = hw->phy.autoneg_advertised;
5954 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5955 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5956 hw->mac.autotry_restart = false;
5957 if (hw->mac.ops.setup_link)
5958 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5959 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5960 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5961 }
5962
5963 /**
5964 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5965 * @work: pointer to work_struct containing our data
5966 **/
5967 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5968 {
5969 struct ixgbe_adapter *adapter = container_of(work,
5970 struct ixgbe_adapter,
5971 sfp_config_module_task);
5972 struct ixgbe_hw *hw = &adapter->hw;
5973 u32 err;
5974
5975 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5976
5977 /* Time for electrical oscillations to settle down */
5978 msleep(100);
5979 err = hw->phy.ops.identify_sfp(hw);
5980
5981 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5982 e_dev_err("failed to initialize because an unsupported SFP+ "
5983 "module type was detected.\n");
5984 e_dev_err("Reload the driver after installing a supported "
5985 "module.\n");
5986 unregister_netdev(adapter->netdev);
5987 return;
5988 }
5989 if (hw->mac.ops.setup_sfp)
5990 hw->mac.ops.setup_sfp(hw);
5991
5992 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5993 /* This will also work for DA Twinax connections */
5994 schedule_work(&adapter->multispeed_fiber_task);
5995 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5996 }
5997
5998 /**
5999 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
6000 * @work: pointer to work_struct containing our data
6001 **/
6002 static void ixgbe_fdir_reinit_task(struct work_struct *work)
6003 {
6004 struct ixgbe_adapter *adapter = container_of(work,
6005 struct ixgbe_adapter,
6006 fdir_reinit_task);
6007 struct ixgbe_hw *hw = &adapter->hw;
6008 int i;
6009
6010 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6011 for (i = 0; i < adapter->num_tx_queues; i++)
6012 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
6013 &(adapter->tx_ring[i]->state));
6014 } else {
6015 e_err(probe, "failed to finish FDIR re-initialization, "
6016 "ignored adding FDIR ATR filters\n");
6017 }
6018 /* Done FDIR Re-initialization, enable transmits */
6019 netif_tx_start_all_queues(adapter->netdev);
6020 }
6021
6022 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6023 {
6024 u32 ssvpc;
6025
6026 /* Do not perform spoof check for 82598 */
6027 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6028 return;
6029
6030 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6031
6032 /*
6033 * ssvpc register is cleared on read, if zero then no
6034 * spoofed packets in the last interval.
6035 */
6036 if (!ssvpc)
6037 return;
6038
6039 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6040 }
6041
6042 static DEFINE_MUTEX(ixgbe_watchdog_lock);
6043
6044 /**
6045 * ixgbe_watchdog_task - worker thread to bring link up
6046 * @work: pointer to work_struct containing our data
6047 **/
6048 static void ixgbe_watchdog_task(struct work_struct *work)
6049 {
6050 struct ixgbe_adapter *adapter = container_of(work,
6051 struct ixgbe_adapter,
6052 watchdog_task);
6053 struct net_device *netdev = adapter->netdev;
6054 struct ixgbe_hw *hw = &adapter->hw;
6055 u32 link_speed;
6056 bool link_up;
6057 int i;
6058 struct ixgbe_ring *tx_ring;
6059 int some_tx_pending = 0;
6060
6061 mutex_lock(&ixgbe_watchdog_lock);
6062
6063 link_up = adapter->link_up;
6064 link_speed = adapter->link_speed;
6065
6066 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
6067 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
6068 if (link_up) {
6069 #ifdef CONFIG_DCB
6070 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6071 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
6072 hw->mac.ops.fc_enable(hw, i);
6073 } else {
6074 hw->mac.ops.fc_enable(hw, 0);
6075 }
6076 #else
6077 hw->mac.ops.fc_enable(hw, 0);
6078 #endif
6079 }
6080
6081 if (link_up ||
6082 time_after(jiffies, (adapter->link_check_timeout +
6083 IXGBE_TRY_LINK_TIMEOUT))) {
6084 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6085 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6086 }
6087 adapter->link_up = link_up;
6088 adapter->link_speed = link_speed;
6089 }
6090
6091 if (link_up) {
6092 if (!netif_carrier_ok(netdev)) {
6093 bool flow_rx, flow_tx;
6094
6095 switch (hw->mac.type) {
6096 case ixgbe_mac_82598EB: {
6097 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6098 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6099 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6100 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6101 }
6102 break;
6103 case ixgbe_mac_82599EB:
6104 case ixgbe_mac_X540: {
6105 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6106 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6107 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6108 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6109 }
6110 break;
6111 default:
6112 flow_tx = false;
6113 flow_rx = false;
6114 break;
6115 }
6116
6117 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6118 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6119 "10 Gbps" :
6120 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6121 "1 Gbps" :
6122 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6123 "100 Mbps" :
6124 "unknown speed"))),
6125 ((flow_rx && flow_tx) ? "RX/TX" :
6126 (flow_rx ? "RX" :
6127 (flow_tx ? "TX" : "None"))));
6128
6129 netif_carrier_on(netdev);
6130 } else {
6131 /* Force detection of hung controller */
6132 for (i = 0; i < adapter->num_tx_queues; i++) {
6133 tx_ring = adapter->tx_ring[i];
6134 set_check_for_tx_hang(tx_ring);
6135 }
6136 }
6137 } else {
6138 adapter->link_up = false;
6139 adapter->link_speed = 0;
6140 if (netif_carrier_ok(netdev)) {
6141 e_info(drv, "NIC Link is Down\n");
6142 netif_carrier_off(netdev);
6143 }
6144 }
6145
6146 if (!netif_carrier_ok(netdev)) {
6147 for (i = 0; i < adapter->num_tx_queues; i++) {
6148 tx_ring = adapter->tx_ring[i];
6149 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6150 some_tx_pending = 1;
6151 break;
6152 }
6153 }
6154
6155 if (some_tx_pending) {
6156 /* We've lost link, so the controller stops DMA,
6157 * but we've got queued Tx work that's never going
6158 * to get done, so reset controller to flush Tx.
6159 * (Do the reset outside of interrupt context).
6160 */
6161 schedule_work(&adapter->reset_task);
6162 }
6163 }
6164
6165 ixgbe_spoof_check(adapter);
6166 ixgbe_update_stats(adapter);
6167 mutex_unlock(&ixgbe_watchdog_lock);
6168 }
6169
6170 static int ixgbe_tso(struct ixgbe_adapter *adapter,
6171 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6172 u32 tx_flags, u8 *hdr_len, __be16 protocol)
6173 {
6174 struct ixgbe_adv_tx_context_desc *context_desc;
6175 unsigned int i;
6176 int err;
6177 struct ixgbe_tx_buffer *tx_buffer_info;
6178 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
6179 u32 mss_l4len_idx, l4len;
6180
6181 if (skb_is_gso(skb)) {
6182 if (skb_header_cloned(skb)) {
6183 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6184 if (err)
6185 return err;
6186 }
6187 l4len = tcp_hdrlen(skb);
6188 *hdr_len += l4len;
6189
6190 if (protocol == htons(ETH_P_IP)) {
6191 struct iphdr *iph = ip_hdr(skb);
6192 iph->tot_len = 0;
6193 iph->check = 0;
6194 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6195 iph->daddr, 0,
6196 IPPROTO_TCP,
6197 0);
6198 } else if (skb_is_gso_v6(skb)) {
6199 ipv6_hdr(skb)->payload_len = 0;
6200 tcp_hdr(skb)->check =
6201 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6202 &ipv6_hdr(skb)->daddr,
6203 0, IPPROTO_TCP, 0);
6204 }
6205
6206 i = tx_ring->next_to_use;
6207
6208 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6209 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6210
6211 /* VLAN MACLEN IPLEN */
6212 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6213 vlan_macip_lens |=
6214 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6215 vlan_macip_lens |= ((skb_network_offset(skb)) <<
6216 IXGBE_ADVTXD_MACLEN_SHIFT);
6217 *hdr_len += skb_network_offset(skb);
6218 vlan_macip_lens |=
6219 (skb_transport_header(skb) - skb_network_header(skb));
6220 *hdr_len +=
6221 (skb_transport_header(skb) - skb_network_header(skb));
6222 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6223 context_desc->seqnum_seed = 0;
6224
6225 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6226 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
6227 IXGBE_ADVTXD_DTYP_CTXT);
6228
6229 if (protocol == htons(ETH_P_IP))
6230 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
6231 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6232 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6233
6234 /* MSS L4LEN IDX */
6235 mss_l4len_idx =
6236 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
6237 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
6238 /* use index 1 for TSO */
6239 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6240 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6241
6242 tx_buffer_info->time_stamp = jiffies;
6243 tx_buffer_info->next_to_watch = i;
6244
6245 i++;
6246 if (i == tx_ring->count)
6247 i = 0;
6248 tx_ring->next_to_use = i;
6249
6250 return true;
6251 }
6252 return false;
6253 }
6254
6255 static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6256 __be16 protocol)
6257 {
6258 u32 rtn = 0;
6259
6260 switch (protocol) {
6261 case cpu_to_be16(ETH_P_IP):
6262 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
6263 switch (ip_hdr(skb)->protocol) {
6264 case IPPROTO_TCP:
6265 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6266 break;
6267 case IPPROTO_SCTP:
6268 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6269 break;
6270 }
6271 break;
6272 case cpu_to_be16(ETH_P_IPV6):
6273 /* XXX what about other V6 headers?? */
6274 switch (ipv6_hdr(skb)->nexthdr) {
6275 case IPPROTO_TCP:
6276 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6277 break;
6278 case IPPROTO_SCTP:
6279 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6280 break;
6281 }
6282 break;
6283 default:
6284 if (unlikely(net_ratelimit()))
6285 e_warn(probe, "partial checksum but proto=%x!\n",
6286 protocol);
6287 break;
6288 }
6289
6290 return rtn;
6291 }
6292
6293 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
6294 struct ixgbe_ring *tx_ring,
6295 struct sk_buff *skb, u32 tx_flags,
6296 __be16 protocol)
6297 {
6298 struct ixgbe_adv_tx_context_desc *context_desc;
6299 unsigned int i;
6300 struct ixgbe_tx_buffer *tx_buffer_info;
6301 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6302
6303 if (skb->ip_summed == CHECKSUM_PARTIAL ||
6304 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6305 i = tx_ring->next_to_use;
6306 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6307 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6308
6309 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6310 vlan_macip_lens |=
6311 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6312 vlan_macip_lens |= (skb_network_offset(skb) <<
6313 IXGBE_ADVTXD_MACLEN_SHIFT);
6314 if (skb->ip_summed == CHECKSUM_PARTIAL)
6315 vlan_macip_lens |= (skb_transport_header(skb) -
6316 skb_network_header(skb));
6317
6318 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6319 context_desc->seqnum_seed = 0;
6320
6321 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
6322 IXGBE_ADVTXD_DTYP_CTXT);
6323
6324 if (skb->ip_summed == CHECKSUM_PARTIAL)
6325 type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
6326
6327 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6328 /* use index zero for tx checksum offload */
6329 context_desc->mss_l4len_idx = 0;
6330
6331 tx_buffer_info->time_stamp = jiffies;
6332 tx_buffer_info->next_to_watch = i;
6333
6334 i++;
6335 if (i == tx_ring->count)
6336 i = 0;
6337 tx_ring->next_to_use = i;
6338
6339 return true;
6340 }
6341
6342 return false;
6343 }
6344
6345 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6346 struct ixgbe_ring *tx_ring,
6347 struct sk_buff *skb, u32 tx_flags,
6348 unsigned int first, const u8 hdr_len)
6349 {
6350 struct device *dev = tx_ring->dev;
6351 struct ixgbe_tx_buffer *tx_buffer_info;
6352 unsigned int len;
6353 unsigned int total = skb->len;
6354 unsigned int offset = 0, size, count = 0, i;
6355 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6356 unsigned int f;
6357 unsigned int bytecount = skb->len;
6358 u16 gso_segs = 1;
6359
6360 i = tx_ring->next_to_use;
6361
6362 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6363 /* excluding fcoe_crc_eof for FCoE */
6364 total -= sizeof(struct fcoe_crc_eof);
6365
6366 len = min(skb_headlen(skb), total);
6367 while (len) {
6368 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6369 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6370
6371 tx_buffer_info->length = size;
6372 tx_buffer_info->mapped_as_page = false;
6373 tx_buffer_info->dma = dma_map_single(dev,
6374 skb->data + offset,
6375 size, DMA_TO_DEVICE);
6376 if (dma_mapping_error(dev, tx_buffer_info->dma))
6377 goto dma_error;
6378 tx_buffer_info->time_stamp = jiffies;
6379 tx_buffer_info->next_to_watch = i;
6380
6381 len -= size;
6382 total -= size;
6383 offset += size;
6384 count++;
6385
6386 if (len) {
6387 i++;
6388 if (i == tx_ring->count)
6389 i = 0;
6390 }
6391 }
6392
6393 for (f = 0; f < nr_frags; f++) {
6394 struct skb_frag_struct *frag;
6395
6396 frag = &skb_shinfo(skb)->frags[f];
6397 len = min((unsigned int)frag->size, total);
6398 offset = frag->page_offset;
6399
6400 while (len) {
6401 i++;
6402 if (i == tx_ring->count)
6403 i = 0;
6404
6405 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6406 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6407
6408 tx_buffer_info->length = size;
6409 tx_buffer_info->dma = dma_map_page(dev,
6410 frag->page,
6411 offset, size,
6412 DMA_TO_DEVICE);
6413 tx_buffer_info->mapped_as_page = true;
6414 if (dma_mapping_error(dev, tx_buffer_info->dma))
6415 goto dma_error;
6416 tx_buffer_info->time_stamp = jiffies;
6417 tx_buffer_info->next_to_watch = i;
6418
6419 len -= size;
6420 total -= size;
6421 offset += size;
6422 count++;
6423 }
6424 if (total == 0)
6425 break;
6426 }
6427
6428 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6429 gso_segs = skb_shinfo(skb)->gso_segs;
6430 #ifdef IXGBE_FCOE
6431 /* adjust for FCoE Sequence Offload */
6432 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6433 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6434 skb_shinfo(skb)->gso_size);
6435 #endif /* IXGBE_FCOE */
6436 bytecount += (gso_segs - 1) * hdr_len;
6437
6438 /* multiply data chunks by size of headers */
6439 tx_ring->tx_buffer_info[i].bytecount = bytecount;
6440 tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6441 tx_ring->tx_buffer_info[i].skb = skb;
6442 tx_ring->tx_buffer_info[first].next_to_watch = i;
6443
6444 return count;
6445
6446 dma_error:
6447 e_dev_err("TX DMA map failed\n");
6448
6449 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6450 tx_buffer_info->dma = 0;
6451 tx_buffer_info->time_stamp = 0;
6452 tx_buffer_info->next_to_watch = 0;
6453 if (count)
6454 count--;
6455
6456 /* clear timestamp and dma mappings for remaining portion of packet */
6457 while (count--) {
6458 if (i == 0)
6459 i += tx_ring->count;
6460 i--;
6461 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6462 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6463 }
6464
6465 return 0;
6466 }
6467
6468 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6469 int tx_flags, int count, u32 paylen, u8 hdr_len)
6470 {
6471 union ixgbe_adv_tx_desc *tx_desc = NULL;
6472 struct ixgbe_tx_buffer *tx_buffer_info;
6473 u32 olinfo_status = 0, cmd_type_len = 0;
6474 unsigned int i;
6475 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6476
6477 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6478
6479 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6480
6481 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6482 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6483
6484 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6485 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6486
6487 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6488 IXGBE_ADVTXD_POPTS_SHIFT;
6489
6490 /* use index 1 context for tso */
6491 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6492 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6493 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6494 IXGBE_ADVTXD_POPTS_SHIFT;
6495
6496 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6497 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6498 IXGBE_ADVTXD_POPTS_SHIFT;
6499
6500 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6501 olinfo_status |= IXGBE_ADVTXD_CC;
6502 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6503 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6504 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6505 }
6506
6507 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6508
6509 i = tx_ring->next_to_use;
6510 while (count--) {
6511 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6512 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6513 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6514 tx_desc->read.cmd_type_len =
6515 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6516 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6517 i++;
6518 if (i == tx_ring->count)
6519 i = 0;
6520 }
6521
6522 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6523
6524 /*
6525 * Force memory writes to complete before letting h/w
6526 * know there are new descriptors to fetch. (Only
6527 * applicable for weak-ordered memory model archs,
6528 * such as IA-64).
6529 */
6530 wmb();
6531
6532 tx_ring->next_to_use = i;
6533 writel(i, tx_ring->tail);
6534 }
6535
6536 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6537 u32 tx_flags, __be16 protocol)
6538 {
6539 struct ixgbe_q_vector *q_vector = ring->q_vector;
6540 union ixgbe_atr_hash_dword input = { .dword = 0 };
6541 union ixgbe_atr_hash_dword common = { .dword = 0 };
6542 union {
6543 unsigned char *network;
6544 struct iphdr *ipv4;
6545 struct ipv6hdr *ipv6;
6546 } hdr;
6547 struct tcphdr *th;
6548 __be16 vlan_id;
6549
6550 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6551 if (!q_vector)
6552 return;
6553
6554 /* do nothing if sampling is disabled */
6555 if (!ring->atr_sample_rate)
6556 return;
6557
6558 ring->atr_count++;
6559
6560 /* snag network header to get L4 type and address */
6561 hdr.network = skb_network_header(skb);
6562
6563 /* Currently only IPv4/IPv6 with TCP is supported */
6564 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6565 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6566 (protocol != __constant_htons(ETH_P_IP) ||
6567 hdr.ipv4->protocol != IPPROTO_TCP))
6568 return;
6569
6570 th = tcp_hdr(skb);
6571
6572 /* skip this packet since the socket is closing */
6573 if (th->fin)
6574 return;
6575
6576 /* sample on all syn packets or once every atr sample count */
6577 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6578 return;
6579
6580 /* reset sample count */
6581 ring->atr_count = 0;
6582
6583 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6584
6585 /*
6586 * src and dst are inverted, think how the receiver sees them
6587 *
6588 * The input is broken into two sections, a non-compressed section
6589 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6590 * is XORed together and stored in the compressed dword.
6591 */
6592 input.formatted.vlan_id = vlan_id;
6593
6594 /*
6595 * since src port and flex bytes occupy the same word XOR them together
6596 * and write the value to source port portion of compressed dword
6597 */
6598 if (vlan_id)
6599 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6600 else
6601 common.port.src ^= th->dest ^ protocol;
6602 common.port.dst ^= th->source;
6603
6604 if (protocol == __constant_htons(ETH_P_IP)) {
6605 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6606 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6607 } else {
6608 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6609 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6610 hdr.ipv6->saddr.s6_addr32[1] ^
6611 hdr.ipv6->saddr.s6_addr32[2] ^
6612 hdr.ipv6->saddr.s6_addr32[3] ^
6613 hdr.ipv6->daddr.s6_addr32[0] ^
6614 hdr.ipv6->daddr.s6_addr32[1] ^
6615 hdr.ipv6->daddr.s6_addr32[2] ^
6616 hdr.ipv6->daddr.s6_addr32[3];
6617 }
6618
6619 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6620 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6621 input, common, ring->queue_index);
6622 }
6623
6624 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6625 {
6626 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6627 /* Herbert's original patch had:
6628 * smp_mb__after_netif_stop_queue();
6629 * but since that doesn't exist yet, just open code it. */
6630 smp_mb();
6631
6632 /* We need to check again in a case another CPU has just
6633 * made room available. */
6634 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6635 return -EBUSY;
6636
6637 /* A reprieve! - use start_queue because it doesn't call schedule */
6638 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6639 ++tx_ring->tx_stats.restart_queue;
6640 return 0;
6641 }
6642
6643 static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6644 {
6645 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6646 return 0;
6647 return __ixgbe_maybe_stop_tx(tx_ring, size);
6648 }
6649
6650 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6651 {
6652 struct ixgbe_adapter *adapter = netdev_priv(dev);
6653 int txq = smp_processor_id();
6654 #ifdef IXGBE_FCOE
6655 __be16 protocol;
6656
6657 protocol = vlan_get_protocol(skb);
6658
6659 if ((protocol == htons(ETH_P_FCOE)) ||
6660 (protocol == htons(ETH_P_FIP))) {
6661 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6662 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6663 txq += adapter->ring_feature[RING_F_FCOE].mask;
6664 return txq;
6665 #ifdef CONFIG_IXGBE_DCB
6666 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6667 txq = adapter->fcoe.up;
6668 return txq;
6669 #endif
6670 }
6671 }
6672 #endif
6673
6674 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6675 while (unlikely(txq >= dev->real_num_tx_queues))
6676 txq -= dev->real_num_tx_queues;
6677 return txq;
6678 }
6679
6680 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6681 if (skb->priority == TC_PRIO_CONTROL)
6682 txq = adapter->ring_feature[RING_F_DCB].indices-1;
6683 else
6684 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6685 >> 13;
6686 return txq;
6687 }
6688
6689 return skb_tx_hash(dev, skb);
6690 }
6691
6692 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6693 struct ixgbe_adapter *adapter,
6694 struct ixgbe_ring *tx_ring)
6695 {
6696 unsigned int first;
6697 unsigned int tx_flags = 0;
6698 u8 hdr_len = 0;
6699 int tso;
6700 int count = 0;
6701 unsigned int f;
6702 __be16 protocol;
6703
6704 protocol = vlan_get_protocol(skb);
6705
6706 if (vlan_tx_tag_present(skb)) {
6707 tx_flags |= vlan_tx_tag_get(skb);
6708 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6709 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6710 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6711 }
6712 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6713 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6714 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6715 skb->priority != TC_PRIO_CONTROL) {
6716 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6717 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6718 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6719 }
6720
6721 #ifdef IXGBE_FCOE
6722 /* for FCoE with DCB, we force the priority to what
6723 * was specified by the switch */
6724 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6725 (protocol == htons(ETH_P_FCOE) ||
6726 protocol == htons(ETH_P_FIP))) {
6727 #ifdef CONFIG_IXGBE_DCB
6728 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6729 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6730 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6731 tx_flags |= ((adapter->fcoe.up << 13)
6732 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6733 }
6734 #endif
6735 /* flag for FCoE offloads */
6736 if (protocol == htons(ETH_P_FCOE))
6737 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6738 }
6739 #endif
6740
6741 /* four things can cause us to need a context descriptor */
6742 if (skb_is_gso(skb) ||
6743 (skb->ip_summed == CHECKSUM_PARTIAL) ||
6744 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6745 (tx_flags & IXGBE_TX_FLAGS_FCOE))
6746 count++;
6747
6748 count += TXD_USE_COUNT(skb_headlen(skb));
6749 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6750 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6751
6752 if (ixgbe_maybe_stop_tx(tx_ring, count)) {
6753 tx_ring->tx_stats.tx_busy++;
6754 return NETDEV_TX_BUSY;
6755 }
6756
6757 first = tx_ring->next_to_use;
6758 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6759 #ifdef IXGBE_FCOE
6760 /* setup tx offload for FCoE */
6761 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6762 if (tso < 0) {
6763 dev_kfree_skb_any(skb);
6764 return NETDEV_TX_OK;
6765 }
6766 if (tso)
6767 tx_flags |= IXGBE_TX_FLAGS_FSO;
6768 #endif /* IXGBE_FCOE */
6769 } else {
6770 if (protocol == htons(ETH_P_IP))
6771 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6772 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6773 protocol);
6774 if (tso < 0) {
6775 dev_kfree_skb_any(skb);
6776 return NETDEV_TX_OK;
6777 }
6778
6779 if (tso)
6780 tx_flags |= IXGBE_TX_FLAGS_TSO;
6781 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6782 protocol) &&
6783 (skb->ip_summed == CHECKSUM_PARTIAL))
6784 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6785 }
6786
6787 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6788 if (count) {
6789 /* add the ATR filter if ATR is on */
6790 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6791 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6792 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
6793 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6794
6795 } else {
6796 dev_kfree_skb_any(skb);
6797 tx_ring->tx_buffer_info[first].time_stamp = 0;
6798 tx_ring->next_to_use = first;
6799 }
6800
6801 return NETDEV_TX_OK;
6802 }
6803
6804 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6805 {
6806 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6807 struct ixgbe_ring *tx_ring;
6808
6809 tx_ring = adapter->tx_ring[skb->queue_mapping];
6810 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6811 }
6812
6813 /**
6814 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6815 * @netdev: network interface device structure
6816 * @p: pointer to an address structure
6817 *
6818 * Returns 0 on success, negative on failure
6819 **/
6820 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6821 {
6822 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6823 struct ixgbe_hw *hw = &adapter->hw;
6824 struct sockaddr *addr = p;
6825
6826 if (!is_valid_ether_addr(addr->sa_data))
6827 return -EADDRNOTAVAIL;
6828
6829 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6830 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6831
6832 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6833 IXGBE_RAH_AV);
6834
6835 return 0;
6836 }
6837
6838 static int
6839 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6840 {
6841 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6842 struct ixgbe_hw *hw = &adapter->hw;
6843 u16 value;
6844 int rc;
6845
6846 if (prtad != hw->phy.mdio.prtad)
6847 return -EINVAL;
6848 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6849 if (!rc)
6850 rc = value;
6851 return rc;
6852 }
6853
6854 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6855 u16 addr, u16 value)
6856 {
6857 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6858 struct ixgbe_hw *hw = &adapter->hw;
6859
6860 if (prtad != hw->phy.mdio.prtad)
6861 return -EINVAL;
6862 return hw->phy.ops.write_reg(hw, addr, devad, value);
6863 }
6864
6865 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6866 {
6867 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6868
6869 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6870 }
6871
6872 /**
6873 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6874 * netdev->dev_addrs
6875 * @netdev: network interface device structure
6876 *
6877 * Returns non-zero on failure
6878 **/
6879 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6880 {
6881 int err = 0;
6882 struct ixgbe_adapter *adapter = netdev_priv(dev);
6883 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6884
6885 if (is_valid_ether_addr(mac->san_addr)) {
6886 rtnl_lock();
6887 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6888 rtnl_unlock();
6889 }
6890 return err;
6891 }
6892
6893 /**
6894 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6895 * netdev->dev_addrs
6896 * @netdev: network interface device structure
6897 *
6898 * Returns non-zero on failure
6899 **/
6900 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6901 {
6902 int err = 0;
6903 struct ixgbe_adapter *adapter = netdev_priv(dev);
6904 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6905
6906 if (is_valid_ether_addr(mac->san_addr)) {
6907 rtnl_lock();
6908 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6909 rtnl_unlock();
6910 }
6911 return err;
6912 }
6913
6914 #ifdef CONFIG_NET_POLL_CONTROLLER
6915 /*
6916 * Polling 'interrupt' - used by things like netconsole to send skbs
6917 * without having to re-enable interrupts. It's not called while
6918 * the interrupt routine is executing.
6919 */
6920 static void ixgbe_netpoll(struct net_device *netdev)
6921 {
6922 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6923 int i;
6924
6925 /* if interface is down do nothing */
6926 if (test_bit(__IXGBE_DOWN, &adapter->state))
6927 return;
6928
6929 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6930 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6931 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6932 for (i = 0; i < num_q_vectors; i++) {
6933 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6934 ixgbe_msix_clean_many(0, q_vector);
6935 }
6936 } else {
6937 ixgbe_intr(adapter->pdev->irq, netdev);
6938 }
6939 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6940 }
6941 #endif
6942
6943 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6944 struct rtnl_link_stats64 *stats)
6945 {
6946 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6947 int i;
6948
6949 rcu_read_lock();
6950 for (i = 0; i < adapter->num_rx_queues; i++) {
6951 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6952 u64 bytes, packets;
6953 unsigned int start;
6954
6955 if (ring) {
6956 do {
6957 start = u64_stats_fetch_begin_bh(&ring->syncp);
6958 packets = ring->stats.packets;
6959 bytes = ring->stats.bytes;
6960 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6961 stats->rx_packets += packets;
6962 stats->rx_bytes += bytes;
6963 }
6964 }
6965
6966 for (i = 0; i < adapter->num_tx_queues; i++) {
6967 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6968 u64 bytes, packets;
6969 unsigned int start;
6970
6971 if (ring) {
6972 do {
6973 start = u64_stats_fetch_begin_bh(&ring->syncp);
6974 packets = ring->stats.packets;
6975 bytes = ring->stats.bytes;
6976 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6977 stats->tx_packets += packets;
6978 stats->tx_bytes += bytes;
6979 }
6980 }
6981 rcu_read_unlock();
6982 /* following stats updated by ixgbe_watchdog_task() */
6983 stats->multicast = netdev->stats.multicast;
6984 stats->rx_errors = netdev->stats.rx_errors;
6985 stats->rx_length_errors = netdev->stats.rx_length_errors;
6986 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6987 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6988 return stats;
6989 }
6990
6991
6992 static const struct net_device_ops ixgbe_netdev_ops = {
6993 .ndo_open = ixgbe_open,
6994 .ndo_stop = ixgbe_close,
6995 .ndo_start_xmit = ixgbe_xmit_frame,
6996 .ndo_select_queue = ixgbe_select_queue,
6997 .ndo_set_rx_mode = ixgbe_set_rx_mode,
6998 .ndo_set_multicast_list = ixgbe_set_rx_mode,
6999 .ndo_validate_addr = eth_validate_addr,
7000 .ndo_set_mac_address = ixgbe_set_mac,
7001 .ndo_change_mtu = ixgbe_change_mtu,
7002 .ndo_tx_timeout = ixgbe_tx_timeout,
7003 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7004 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7005 .ndo_do_ioctl = ixgbe_ioctl,
7006 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7007 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7008 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7009 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7010 .ndo_get_stats64 = ixgbe_get_stats64,
7011 #ifdef CONFIG_NET_POLL_CONTROLLER
7012 .ndo_poll_controller = ixgbe_netpoll,
7013 #endif
7014 #ifdef IXGBE_FCOE
7015 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7016 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7017 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7018 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7019 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7020 #endif /* IXGBE_FCOE */
7021 };
7022
7023 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7024 const struct ixgbe_info *ii)
7025 {
7026 #ifdef CONFIG_PCI_IOV
7027 struct ixgbe_hw *hw = &adapter->hw;
7028 int err;
7029
7030 if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
7031 return;
7032
7033 /* The 82599 supports up to 64 VFs per physical function
7034 * but this implementation limits allocation to 63 so that
7035 * basic networking resources are still available to the
7036 * physical function
7037 */
7038 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7039 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7040 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7041 if (err) {
7042 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
7043 goto err_novfs;
7044 }
7045 /* If call to enable VFs succeeded then allocate memory
7046 * for per VF control structures.
7047 */
7048 adapter->vfinfo =
7049 kcalloc(adapter->num_vfs,
7050 sizeof(struct vf_data_storage), GFP_KERNEL);
7051 if (adapter->vfinfo) {
7052 /* Now that we're sure SR-IOV is enabled
7053 * and memory allocated set up the mailbox parameters
7054 */
7055 ixgbe_init_mbx_params_pf(hw);
7056 memcpy(&hw->mbx.ops, ii->mbx_ops,
7057 sizeof(hw->mbx.ops));
7058
7059 /* Disable RSC when in SR-IOV mode */
7060 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7061 IXGBE_FLAG2_RSC_ENABLED);
7062 return;
7063 }
7064
7065 /* Oh oh */
7066 e_err(probe, "Unable to allocate memory for VF Data Storage - "
7067 "SRIOV disabled\n");
7068 pci_disable_sriov(adapter->pdev);
7069
7070 err_novfs:
7071 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7072 adapter->num_vfs = 0;
7073 #endif /* CONFIG_PCI_IOV */
7074 }
7075
7076 /**
7077 * ixgbe_probe - Device Initialization Routine
7078 * @pdev: PCI device information struct
7079 * @ent: entry in ixgbe_pci_tbl
7080 *
7081 * Returns 0 on success, negative on failure
7082 *
7083 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7084 * The OS initialization, configuring of the adapter private structure,
7085 * and a hardware reset occur.
7086 **/
7087 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7088 const struct pci_device_id *ent)
7089 {
7090 struct net_device *netdev;
7091 struct ixgbe_adapter *adapter = NULL;
7092 struct ixgbe_hw *hw;
7093 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7094 static int cards_found;
7095 int i, err, pci_using_dac;
7096 u8 part_str[IXGBE_PBANUM_LENGTH];
7097 unsigned int indices = num_possible_cpus();
7098 #ifdef IXGBE_FCOE
7099 u16 device_caps;
7100 #endif
7101 u32 eec;
7102
7103 /* Catch broken hardware that put the wrong VF device ID in
7104 * the PCIe SR-IOV capability.
7105 */
7106 if (pdev->is_virtfn) {
7107 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7108 pci_name(pdev), pdev->vendor, pdev->device);
7109 return -EINVAL;
7110 }
7111
7112 err = pci_enable_device_mem(pdev);
7113 if (err)
7114 return err;
7115
7116 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7117 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7118 pci_using_dac = 1;
7119 } else {
7120 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7121 if (err) {
7122 err = dma_set_coherent_mask(&pdev->dev,
7123 DMA_BIT_MASK(32));
7124 if (err) {
7125 dev_err(&pdev->dev,
7126 "No usable DMA configuration, aborting\n");
7127 goto err_dma;
7128 }
7129 }
7130 pci_using_dac = 0;
7131 }
7132
7133 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7134 IORESOURCE_MEM), ixgbe_driver_name);
7135 if (err) {
7136 dev_err(&pdev->dev,
7137 "pci_request_selected_regions failed 0x%x\n", err);
7138 goto err_pci_reg;
7139 }
7140
7141 pci_enable_pcie_error_reporting(pdev);
7142
7143 pci_set_master(pdev);
7144 pci_save_state(pdev);
7145
7146 if (ii->mac == ixgbe_mac_82598EB)
7147 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7148 else
7149 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7150
7151 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
7152 #ifdef IXGBE_FCOE
7153 indices += min_t(unsigned int, num_possible_cpus(),
7154 IXGBE_MAX_FCOE_INDICES);
7155 #endif
7156 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7157 if (!netdev) {
7158 err = -ENOMEM;
7159 goto err_alloc_etherdev;
7160 }
7161
7162 SET_NETDEV_DEV(netdev, &pdev->dev);
7163
7164 adapter = netdev_priv(netdev);
7165 pci_set_drvdata(pdev, adapter);
7166
7167 adapter->netdev = netdev;
7168 adapter->pdev = pdev;
7169 hw = &adapter->hw;
7170 hw->back = adapter;
7171 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7172
7173 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7174 pci_resource_len(pdev, 0));
7175 if (!hw->hw_addr) {
7176 err = -EIO;
7177 goto err_ioremap;
7178 }
7179
7180 for (i = 1; i <= 5; i++) {
7181 if (pci_resource_len(pdev, i) == 0)
7182 continue;
7183 }
7184
7185 netdev->netdev_ops = &ixgbe_netdev_ops;
7186 ixgbe_set_ethtool_ops(netdev);
7187 netdev->watchdog_timeo = 5 * HZ;
7188 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7189
7190 adapter->bd_number = cards_found;
7191
7192 /* Setup hw api */
7193 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7194 hw->mac.type = ii->mac;
7195
7196 /* EEPROM */
7197 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7198 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7199 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7200 if (!(eec & (1 << 8)))
7201 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7202
7203 /* PHY */
7204 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7205 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7206 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7207 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7208 hw->phy.mdio.mmds = 0;
7209 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7210 hw->phy.mdio.dev = netdev;
7211 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7212 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7213
7214 /* set up this timer and work struct before calling get_invariants
7215 * which might start the timer
7216 */
7217 init_timer(&adapter->sfp_timer);
7218 adapter->sfp_timer.function = ixgbe_sfp_timer;
7219 adapter->sfp_timer.data = (unsigned long) adapter;
7220
7221 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
7222
7223 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
7224 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
7225
7226 /* a new SFP+ module arrival, called from GPI SDP2 context */
7227 INIT_WORK(&adapter->sfp_config_module_task,
7228 ixgbe_sfp_config_module_task);
7229
7230 ii->get_invariants(hw);
7231
7232 /* setup the private structure */
7233 err = ixgbe_sw_init(adapter);
7234 if (err)
7235 goto err_sw_init;
7236
7237 /* Make it possible the adapter to be woken up via WOL */
7238 switch (adapter->hw.mac.type) {
7239 case ixgbe_mac_82599EB:
7240 case ixgbe_mac_X540:
7241 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7242 break;
7243 default:
7244 break;
7245 }
7246
7247 /*
7248 * If there is a fan on this device and it has failed log the
7249 * failure.
7250 */
7251 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7252 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7253 if (esdp & IXGBE_ESDP_SDP1)
7254 e_crit(probe, "Fan has stopped, replace the adapter\n");
7255 }
7256
7257 /* reset_hw fills in the perm_addr as well */
7258 hw->phy.reset_if_overtemp = true;
7259 err = hw->mac.ops.reset_hw(hw);
7260 hw->phy.reset_if_overtemp = false;
7261 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7262 hw->mac.type == ixgbe_mac_82598EB) {
7263 /*
7264 * Start a kernel thread to watch for a module to arrive.
7265 * Only do this for 82598, since 82599 will generate
7266 * interrupts on module arrival.
7267 */
7268 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7269 mod_timer(&adapter->sfp_timer,
7270 round_jiffies(jiffies + (2 * HZ)));
7271 err = 0;
7272 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7273 e_dev_err("failed to initialize because an unsupported SFP+ "
7274 "module type was detected.\n");
7275 e_dev_err("Reload the driver after installing a supported "
7276 "module.\n");
7277 goto err_sw_init;
7278 } else if (err) {
7279 e_dev_err("HW Init failed: %d\n", err);
7280 goto err_sw_init;
7281 }
7282
7283 ixgbe_probe_vf(adapter, ii);
7284
7285 netdev->features = NETIF_F_SG |
7286 NETIF_F_IP_CSUM |
7287 NETIF_F_HW_VLAN_TX |
7288 NETIF_F_HW_VLAN_RX |
7289 NETIF_F_HW_VLAN_FILTER;
7290
7291 netdev->features |= NETIF_F_IPV6_CSUM;
7292 netdev->features |= NETIF_F_TSO;
7293 netdev->features |= NETIF_F_TSO6;
7294 netdev->features |= NETIF_F_GRO;
7295
7296 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
7297 netdev->features |= NETIF_F_SCTP_CSUM;
7298
7299 netdev->vlan_features |= NETIF_F_TSO;
7300 netdev->vlan_features |= NETIF_F_TSO6;
7301 netdev->vlan_features |= NETIF_F_IP_CSUM;
7302 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7303 netdev->vlan_features |= NETIF_F_SG;
7304
7305 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7306 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7307 IXGBE_FLAG_DCB_ENABLED);
7308 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7309 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
7310
7311 #ifdef CONFIG_IXGBE_DCB
7312 netdev->dcbnl_ops = &dcbnl_ops;
7313 #endif
7314
7315 #ifdef IXGBE_FCOE
7316 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7317 if (hw->mac.ops.get_device_caps) {
7318 hw->mac.ops.get_device_caps(hw, &device_caps);
7319 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7320 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7321 }
7322 }
7323 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7324 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7325 netdev->vlan_features |= NETIF_F_FSO;
7326 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7327 }
7328 #endif /* IXGBE_FCOE */
7329 if (pci_using_dac) {
7330 netdev->features |= NETIF_F_HIGHDMA;
7331 netdev->vlan_features |= NETIF_F_HIGHDMA;
7332 }
7333
7334 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7335 netdev->features |= NETIF_F_LRO;
7336
7337 /* make sure the EEPROM is good */
7338 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7339 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7340 err = -EIO;
7341 goto err_eeprom;
7342 }
7343
7344 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7345 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7346
7347 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7348 e_dev_err("invalid MAC address\n");
7349 err = -EIO;
7350 goto err_eeprom;
7351 }
7352
7353 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7354 if (hw->mac.ops.disable_tx_laser &&
7355 ((hw->phy.multispeed_fiber) ||
7356 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7357 (hw->mac.type == ixgbe_mac_82599EB))))
7358 hw->mac.ops.disable_tx_laser(hw);
7359
7360 init_timer(&adapter->watchdog_timer);
7361 adapter->watchdog_timer.function = ixgbe_watchdog;
7362 adapter->watchdog_timer.data = (unsigned long)adapter;
7363
7364 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
7365 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
7366
7367 err = ixgbe_init_interrupt_scheme(adapter);
7368 if (err)
7369 goto err_sw_init;
7370
7371 switch (pdev->device) {
7372 case IXGBE_DEV_ID_82599_SFP:
7373 /* Only this subdevice supports WOL */
7374 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7375 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7376 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7377 break;
7378 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7379 /* All except this subdevice support WOL */
7380 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7381 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7382 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7383 break;
7384 case IXGBE_DEV_ID_82599_KX4:
7385 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7386 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7387 break;
7388 default:
7389 adapter->wol = 0;
7390 break;
7391 }
7392 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7393
7394 /* pick up the PCI bus settings for reporting later */
7395 hw->mac.ops.get_bus_info(hw);
7396
7397 /* print bus type/speed/width info */
7398 e_dev_info("(PCI Express:%s:%s) %pM\n",
7399 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
7400 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
7401 "Unknown"),
7402 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7403 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7404 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7405 "Unknown"),
7406 netdev->dev_addr);
7407
7408 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7409 if (err)
7410 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7411 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7412 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7413 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7414 part_str);
7415 else
7416 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7417 hw->mac.type, hw->phy.type, part_str);
7418
7419 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7420 e_dev_warn("PCI-Express bandwidth available for this card is "
7421 "not sufficient for optimal performance.\n");
7422 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7423 "is required.\n");
7424 }
7425
7426 /* save off EEPROM version number */
7427 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7428
7429 /* reset the hardware with the new settings */
7430 err = hw->mac.ops.start_hw(hw);
7431
7432 if (err == IXGBE_ERR_EEPROM_VERSION) {
7433 /* We are running on a pre-production device, log a warning */
7434 e_dev_warn("This device is a pre-production adapter/LOM. "
7435 "Please be aware there may be issues associated "
7436 "with your hardware. If you are experiencing "
7437 "problems please contact your Intel or hardware "
7438 "representative who provided you with this "
7439 "hardware.\n");
7440 }
7441 strcpy(netdev->name, "eth%d");
7442 err = register_netdev(netdev);
7443 if (err)
7444 goto err_register;
7445
7446 /* carrier off reporting is important to ethtool even BEFORE open */
7447 netif_carrier_off(netdev);
7448
7449 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7450 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7451 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7452
7453 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7454 INIT_WORK(&adapter->check_overtemp_task,
7455 ixgbe_check_overtemp_task);
7456 #ifdef CONFIG_IXGBE_DCA
7457 if (dca_add_requester(&pdev->dev) == 0) {
7458 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7459 ixgbe_setup_dca(adapter);
7460 }
7461 #endif
7462 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7463 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7464 for (i = 0; i < adapter->num_vfs; i++)
7465 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7466 }
7467
7468 /* add san mac addr to netdev */
7469 ixgbe_add_sanmac_netdev(netdev);
7470
7471 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7472 cards_found++;
7473 return 0;
7474
7475 err_register:
7476 ixgbe_release_hw_control(adapter);
7477 ixgbe_clear_interrupt_scheme(adapter);
7478 err_sw_init:
7479 err_eeprom:
7480 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7481 ixgbe_disable_sriov(adapter);
7482 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7483 del_timer_sync(&adapter->sfp_timer);
7484 cancel_work_sync(&adapter->sfp_task);
7485 cancel_work_sync(&adapter->multispeed_fiber_task);
7486 cancel_work_sync(&adapter->sfp_config_module_task);
7487 iounmap(hw->hw_addr);
7488 err_ioremap:
7489 free_netdev(netdev);
7490 err_alloc_etherdev:
7491 pci_release_selected_regions(pdev,
7492 pci_select_bars(pdev, IORESOURCE_MEM));
7493 err_pci_reg:
7494 err_dma:
7495 pci_disable_device(pdev);
7496 return err;
7497 }
7498
7499 /**
7500 * ixgbe_remove - Device Removal Routine
7501 * @pdev: PCI device information struct
7502 *
7503 * ixgbe_remove is called by the PCI subsystem to alert the driver
7504 * that it should release a PCI device. The could be caused by a
7505 * Hot-Plug event, or because the driver is going to be removed from
7506 * memory.
7507 **/
7508 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7509 {
7510 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7511 struct net_device *netdev = adapter->netdev;
7512
7513 set_bit(__IXGBE_DOWN, &adapter->state);
7514
7515 /*
7516 * The timers may be rescheduled, so explicitly disable them
7517 * from being rescheduled.
7518 */
7519 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7520 del_timer_sync(&adapter->watchdog_timer);
7521 del_timer_sync(&adapter->sfp_timer);
7522
7523 cancel_work_sync(&adapter->watchdog_task);
7524 cancel_work_sync(&adapter->sfp_task);
7525 cancel_work_sync(&adapter->multispeed_fiber_task);
7526 cancel_work_sync(&adapter->sfp_config_module_task);
7527 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7528 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7529 cancel_work_sync(&adapter->fdir_reinit_task);
7530 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7531 cancel_work_sync(&adapter->check_overtemp_task);
7532
7533 #ifdef CONFIG_IXGBE_DCA
7534 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7535 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7536 dca_remove_requester(&pdev->dev);
7537 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7538 }
7539
7540 #endif
7541 #ifdef IXGBE_FCOE
7542 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7543 ixgbe_cleanup_fcoe(adapter);
7544
7545 #endif /* IXGBE_FCOE */
7546
7547 /* remove the added san mac */
7548 ixgbe_del_sanmac_netdev(netdev);
7549
7550 if (netdev->reg_state == NETREG_REGISTERED)
7551 unregister_netdev(netdev);
7552
7553 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7554 ixgbe_disable_sriov(adapter);
7555
7556 ixgbe_clear_interrupt_scheme(adapter);
7557
7558 ixgbe_release_hw_control(adapter);
7559
7560 iounmap(adapter->hw.hw_addr);
7561 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7562 IORESOURCE_MEM));
7563
7564 e_dev_info("complete\n");
7565
7566 free_netdev(netdev);
7567
7568 pci_disable_pcie_error_reporting(pdev);
7569
7570 pci_disable_device(pdev);
7571 }
7572
7573 /**
7574 * ixgbe_io_error_detected - called when PCI error is detected
7575 * @pdev: Pointer to PCI device
7576 * @state: The current pci connection state
7577 *
7578 * This function is called after a PCI bus error affecting
7579 * this device has been detected.
7580 */
7581 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7582 pci_channel_state_t state)
7583 {
7584 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7585 struct net_device *netdev = adapter->netdev;
7586
7587 netif_device_detach(netdev);
7588
7589 if (state == pci_channel_io_perm_failure)
7590 return PCI_ERS_RESULT_DISCONNECT;
7591
7592 if (netif_running(netdev))
7593 ixgbe_down(adapter);
7594 pci_disable_device(pdev);
7595
7596 /* Request a slot reset. */
7597 return PCI_ERS_RESULT_NEED_RESET;
7598 }
7599
7600 /**
7601 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7602 * @pdev: Pointer to PCI device
7603 *
7604 * Restart the card from scratch, as if from a cold-boot.
7605 */
7606 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7607 {
7608 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7609 pci_ers_result_t result;
7610 int err;
7611
7612 if (pci_enable_device_mem(pdev)) {
7613 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7614 result = PCI_ERS_RESULT_DISCONNECT;
7615 } else {
7616 pci_set_master(pdev);
7617 pci_restore_state(pdev);
7618 pci_save_state(pdev);
7619
7620 pci_wake_from_d3(pdev, false);
7621
7622 ixgbe_reset(adapter);
7623 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7624 result = PCI_ERS_RESULT_RECOVERED;
7625 }
7626
7627 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7628 if (err) {
7629 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7630 "failed 0x%0x\n", err);
7631 /* non-fatal, continue */
7632 }
7633
7634 return result;
7635 }
7636
7637 /**
7638 * ixgbe_io_resume - called when traffic can start flowing again.
7639 * @pdev: Pointer to PCI device
7640 *
7641 * This callback is called when the error recovery driver tells us that
7642 * its OK to resume normal operation.
7643 */
7644 static void ixgbe_io_resume(struct pci_dev *pdev)
7645 {
7646 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7647 struct net_device *netdev = adapter->netdev;
7648
7649 if (netif_running(netdev)) {
7650 if (ixgbe_up(adapter)) {
7651 e_info(probe, "ixgbe_up failed after reset\n");
7652 return;
7653 }
7654 }
7655
7656 netif_device_attach(netdev);
7657 }
7658
7659 static struct pci_error_handlers ixgbe_err_handler = {
7660 .error_detected = ixgbe_io_error_detected,
7661 .slot_reset = ixgbe_io_slot_reset,
7662 .resume = ixgbe_io_resume,
7663 };
7664
7665 static struct pci_driver ixgbe_driver = {
7666 .name = ixgbe_driver_name,
7667 .id_table = ixgbe_pci_tbl,
7668 .probe = ixgbe_probe,
7669 .remove = __devexit_p(ixgbe_remove),
7670 #ifdef CONFIG_PM
7671 .suspend = ixgbe_suspend,
7672 .resume = ixgbe_resume,
7673 #endif
7674 .shutdown = ixgbe_shutdown,
7675 .err_handler = &ixgbe_err_handler
7676 };
7677
7678 /**
7679 * ixgbe_init_module - Driver Registration Routine
7680 *
7681 * ixgbe_init_module is the first routine called when the driver is
7682 * loaded. All it does is register with the PCI subsystem.
7683 **/
7684 static int __init ixgbe_init_module(void)
7685 {
7686 int ret;
7687 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7688 pr_info("%s\n", ixgbe_copyright);
7689
7690 #ifdef CONFIG_IXGBE_DCA
7691 dca_register_notify(&dca_notifier);
7692 #endif
7693
7694 ret = pci_register_driver(&ixgbe_driver);
7695 return ret;
7696 }
7697
7698 module_init(ixgbe_init_module);
7699
7700 /**
7701 * ixgbe_exit_module - Driver Exit Cleanup Routine
7702 *
7703 * ixgbe_exit_module is called just before the driver is removed
7704 * from memory.
7705 **/
7706 static void __exit ixgbe_exit_module(void)
7707 {
7708 #ifdef CONFIG_IXGBE_DCA
7709 dca_unregister_notify(&dca_notifier);
7710 #endif
7711 pci_unregister_driver(&ixgbe_driver);
7712 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7713 }
7714
7715 #ifdef CONFIG_IXGBE_DCA
7716 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7717 void *p)
7718 {
7719 int ret_val;
7720
7721 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7722 __ixgbe_notify_dca);
7723
7724 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7725 }
7726
7727 #endif /* CONFIG_IXGBE_DCA */
7728
7729 module_exit(ixgbe_exit_module);
7730
7731 /* ixgbe_main.c */
Linux kernel - Deliverables
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