1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <linux/slab.h>
40 #include <net/checksum.h>
41 #include <net/ip6_checksum.h>
42 #include <linux/ethtool.h>
43 #include <linux/if_vlan.h>
44 #include <scsi/fc/fc_fcoe.h>
47 #include "ixgbe_common.h"
48 #include "ixgbe_dcb_82599.h"
49 #include "ixgbe_sriov.h"
51 char ixgbe_driver_name
[] = "ixgbe";
52 static const char ixgbe_driver_string
[] =
53 "Intel(R) 10 Gigabit PCI Express Network Driver";
55 #define DRV_VERSION "3.2.9-k2"
56 const char ixgbe_driver_version
[] = DRV_VERSION
;
57 static const char ixgbe_copyright
[] =
58 "Copyright (c) 1999-2011 Intel Corporation.";
60 static const struct ixgbe_info
*ixgbe_info_tbl
[] = {
61 [board_82598
] = &ixgbe_82598_info
,
62 [board_82599
] = &ixgbe_82599_info
,
63 [board_X540
] = &ixgbe_X540_info
,
66 /* ixgbe_pci_tbl - PCI Device ID Table
68 * Wildcard entries (PCI_ANY_ID) should come last
69 * Last entry must be all 0s
71 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
72 * Class, Class Mask, private data (not used) }
74 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl
) = {
75 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598
),
77 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_DUAL_PORT
),
79 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_SINGLE_PORT
),
81 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT
),
83 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT2
),
85 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_CX4
),
87 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_CX4_DUAL_PORT
),
89 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_DA_DUAL_PORT
),
91 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM
),
93 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_XF_LR
),
95 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_SFP_LOM
),
97 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_BX
),
99 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4
),
101 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_XAUI_LOM
),
103 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KR
),
105 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP
),
107 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP_EM
),
109 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4_MEZZ
),
111 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_CX4
),
113 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_BACKPLANE_FCOE
),
115 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP_FCOE
),
117 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_T3_LOM
),
119 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_COMBO_BACKPLANE
),
121 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_X540T
),
124 /* required last entry */
127 MODULE_DEVICE_TABLE(pci
, ixgbe_pci_tbl
);
129 #ifdef CONFIG_IXGBE_DCA
130 static int ixgbe_notify_dca(struct notifier_block
*, unsigned long event
,
132 static struct notifier_block dca_notifier
= {
133 .notifier_call
= ixgbe_notify_dca
,
139 #ifdef CONFIG_PCI_IOV
140 static unsigned int max_vfs
;
141 module_param(max_vfs
, uint
, 0);
142 MODULE_PARM_DESC(max_vfs
,
143 "Maximum number of virtual functions to allocate per physical function");
144 #endif /* CONFIG_PCI_IOV */
146 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
147 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
148 MODULE_LICENSE("GPL");
149 MODULE_VERSION(DRV_VERSION
);
151 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
153 static inline void ixgbe_disable_sriov(struct ixgbe_adapter
*adapter
)
155 struct ixgbe_hw
*hw
= &adapter
->hw
;
160 #ifdef CONFIG_PCI_IOV
161 /* disable iov and allow time for transactions to clear */
162 pci_disable_sriov(adapter
->pdev
);
165 /* turn off device IOV mode */
166 gcr
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
167 gcr
&= ~(IXGBE_GCR_EXT_SRIOV
);
168 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, gcr
);
169 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
170 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
171 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
173 /* set default pool back to 0 */
174 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
175 vmdctl
&= ~IXGBE_VT_CTL_POOL_MASK
;
176 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
);
178 /* take a breather then clean up driver data */
181 kfree(adapter
->vfinfo
);
182 adapter
->vfinfo
= NULL
;
184 adapter
->num_vfs
= 0;
185 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
188 struct ixgbe_reg_info
{
193 static const struct ixgbe_reg_info ixgbe_reg_info_tbl
[] = {
195 /* General Registers */
196 {IXGBE_CTRL
, "CTRL"},
197 {IXGBE_STATUS
, "STATUS"},
198 {IXGBE_CTRL_EXT
, "CTRL_EXT"},
200 /* Interrupt Registers */
201 {IXGBE_EICR
, "EICR"},
204 {IXGBE_SRRCTL(0), "SRRCTL"},
205 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
206 {IXGBE_RDLEN(0), "RDLEN"},
207 {IXGBE_RDH(0), "RDH"},
208 {IXGBE_RDT(0), "RDT"},
209 {IXGBE_RXDCTL(0), "RXDCTL"},
210 {IXGBE_RDBAL(0), "RDBAL"},
211 {IXGBE_RDBAH(0), "RDBAH"},
214 {IXGBE_TDBAL(0), "TDBAL"},
215 {IXGBE_TDBAH(0), "TDBAH"},
216 {IXGBE_TDLEN(0), "TDLEN"},
217 {IXGBE_TDH(0), "TDH"},
218 {IXGBE_TDT(0), "TDT"},
219 {IXGBE_TXDCTL(0), "TXDCTL"},
221 /* List Terminator */
227 * ixgbe_regdump - register printout routine
229 static void ixgbe_regdump(struct ixgbe_hw
*hw
, struct ixgbe_reg_info
*reginfo
)
235 switch (reginfo
->ofs
) {
236 case IXGBE_SRRCTL(0):
237 for (i
= 0; i
< 64; i
++)
238 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_SRRCTL(i
));
240 case IXGBE_DCA_RXCTRL(0):
241 for (i
= 0; i
< 64; i
++)
242 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_DCA_RXCTRL(i
));
245 for (i
= 0; i
< 64; i
++)
246 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDLEN(i
));
249 for (i
= 0; i
< 64; i
++)
250 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDH(i
));
253 for (i
= 0; i
< 64; i
++)
254 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDT(i
));
256 case IXGBE_RXDCTL(0):
257 for (i
= 0; i
< 64; i
++)
258 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RXDCTL(i
));
261 for (i
= 0; i
< 64; i
++)
262 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDBAL(i
));
265 for (i
= 0; i
< 64; i
++)
266 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDBAH(i
));
269 for (i
= 0; i
< 64; i
++)
270 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDBAL(i
));
273 for (i
= 0; i
< 64; i
++)
274 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDBAH(i
));
277 for (i
= 0; i
< 64; i
++)
278 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDLEN(i
));
281 for (i
= 0; i
< 64; i
++)
282 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDH(i
));
285 for (i
= 0; i
< 64; i
++)
286 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDT(i
));
288 case IXGBE_TXDCTL(0):
289 for (i
= 0; i
< 64; i
++)
290 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TXDCTL(i
));
293 pr_info("%-15s %08x\n", reginfo
->name
,
294 IXGBE_READ_REG(hw
, reginfo
->ofs
));
298 for (i
= 0; i
< 8; i
++) {
299 snprintf(rname
, 16, "%s[%d-%d]", reginfo
->name
, i
*8, i
*8+7);
300 pr_err("%-15s", rname
);
301 for (j
= 0; j
< 8; j
++)
302 pr_cont(" %08x", regs
[i
*8+j
]);
309 * ixgbe_dump - Print registers, tx-rings and rx-rings
311 static void ixgbe_dump(struct ixgbe_adapter
*adapter
)
313 struct net_device
*netdev
= adapter
->netdev
;
314 struct ixgbe_hw
*hw
= &adapter
->hw
;
315 struct ixgbe_reg_info
*reginfo
;
317 struct ixgbe_ring
*tx_ring
;
318 struct ixgbe_tx_buffer
*tx_buffer_info
;
319 union ixgbe_adv_tx_desc
*tx_desc
;
320 struct my_u0
{ u64 a
; u64 b
; } *u0
;
321 struct ixgbe_ring
*rx_ring
;
322 union ixgbe_adv_rx_desc
*rx_desc
;
323 struct ixgbe_rx_buffer
*rx_buffer_info
;
327 if (!netif_msg_hw(adapter
))
330 /* Print netdevice Info */
332 dev_info(&adapter
->pdev
->dev
, "Net device Info\n");
333 pr_info("Device Name state "
334 "trans_start last_rx\n");
335 pr_info("%-15s %016lX %016lX %016lX\n",
342 /* Print Registers */
343 dev_info(&adapter
->pdev
->dev
, "Register Dump\n");
344 pr_info(" Register Name Value\n");
345 for (reginfo
= (struct ixgbe_reg_info
*)ixgbe_reg_info_tbl
;
346 reginfo
->name
; reginfo
++) {
347 ixgbe_regdump(hw
, reginfo
);
350 /* Print TX Ring Summary */
351 if (!netdev
|| !netif_running(netdev
))
354 dev_info(&adapter
->pdev
->dev
, "TX Rings Summary\n");
355 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
356 for (n
= 0; n
< adapter
->num_tx_queues
; n
++) {
357 tx_ring
= adapter
->tx_ring
[n
];
359 &tx_ring
->tx_buffer_info
[tx_ring
->next_to_clean
];
360 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
361 n
, tx_ring
->next_to_use
, tx_ring
->next_to_clean
,
362 (u64
)tx_buffer_info
->dma
,
363 tx_buffer_info
->length
,
364 tx_buffer_info
->next_to_watch
,
365 (u64
)tx_buffer_info
->time_stamp
);
369 if (!netif_msg_tx_done(adapter
))
370 goto rx_ring_summary
;
372 dev_info(&adapter
->pdev
->dev
, "TX Rings Dump\n");
374 /* Transmit Descriptor Formats
376 * Advanced Transmit Descriptor
377 * +--------------------------------------------------------------+
378 * 0 | Buffer Address [63:0] |
379 * +--------------------------------------------------------------+
380 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
381 * +--------------------------------------------------------------+
382 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
385 for (n
= 0; n
< adapter
->num_tx_queues
; n
++) {
386 tx_ring
= adapter
->tx_ring
[n
];
387 pr_info("------------------------------------\n");
388 pr_info("TX QUEUE INDEX = %d\n", tx_ring
->queue_index
);
389 pr_info("------------------------------------\n");
390 pr_info("T [desc] [address 63:0 ] "
391 "[PlPOIdStDDt Ln] [bi->dma ] "
392 "leng ntw timestamp bi->skb\n");
394 for (i
= 0; tx_ring
->desc
&& (i
< tx_ring
->count
); i
++) {
395 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, i
);
396 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
397 u0
= (struct my_u0
*)tx_desc
;
398 pr_info("T [0x%03X] %016llX %016llX %016llX"
399 " %04X %3X %016llX %p", i
,
402 (u64
)tx_buffer_info
->dma
,
403 tx_buffer_info
->length
,
404 tx_buffer_info
->next_to_watch
,
405 (u64
)tx_buffer_info
->time_stamp
,
406 tx_buffer_info
->skb
);
407 if (i
== tx_ring
->next_to_use
&&
408 i
== tx_ring
->next_to_clean
)
410 else if (i
== tx_ring
->next_to_use
)
412 else if (i
== tx_ring
->next_to_clean
)
417 if (netif_msg_pktdata(adapter
) &&
418 tx_buffer_info
->dma
!= 0)
419 print_hex_dump(KERN_INFO
, "",
420 DUMP_PREFIX_ADDRESS
, 16, 1,
421 phys_to_virt(tx_buffer_info
->dma
),
422 tx_buffer_info
->length
, true);
426 /* Print RX Rings Summary */
428 dev_info(&adapter
->pdev
->dev
, "RX Rings Summary\n");
429 pr_info("Queue [NTU] [NTC]\n");
430 for (n
= 0; n
< adapter
->num_rx_queues
; n
++) {
431 rx_ring
= adapter
->rx_ring
[n
];
432 pr_info("%5d %5X %5X\n",
433 n
, rx_ring
->next_to_use
, rx_ring
->next_to_clean
);
437 if (!netif_msg_rx_status(adapter
))
440 dev_info(&adapter
->pdev
->dev
, "RX Rings Dump\n");
442 /* Advanced Receive Descriptor (Read) Format
444 * +-----------------------------------------------------+
445 * 0 | Packet Buffer Address [63:1] |A0/NSE|
446 * +----------------------------------------------+------+
447 * 8 | Header Buffer Address [63:1] | DD |
448 * +-----------------------------------------------------+
451 * Advanced Receive Descriptor (Write-Back) Format
453 * 63 48 47 32 31 30 21 20 16 15 4 3 0
454 * +------------------------------------------------------+
455 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
456 * | Checksum Ident | | | | Type | Type |
457 * +------------------------------------------------------+
458 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
459 * +------------------------------------------------------+
460 * 63 48 47 32 31 20 19 0
462 for (n
= 0; n
< adapter
->num_rx_queues
; n
++) {
463 rx_ring
= adapter
->rx_ring
[n
];
464 pr_info("------------------------------------\n");
465 pr_info("RX QUEUE INDEX = %d\n", rx_ring
->queue_index
);
466 pr_info("------------------------------------\n");
467 pr_info("R [desc] [ PktBuf A0] "
468 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
469 "<-- Adv Rx Read format\n");
470 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
471 "[vl er S cks ln] ---------------- [bi->skb] "
472 "<-- Adv Rx Write-Back format\n");
474 for (i
= 0; i
< rx_ring
->count
; i
++) {
475 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
476 rx_desc
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
477 u0
= (struct my_u0
*)rx_desc
;
478 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
479 if (staterr
& IXGBE_RXD_STAT_DD
) {
480 /* Descriptor Done */
481 pr_info("RWB[0x%03X] %016llX "
482 "%016llX ---------------- %p", i
,
485 rx_buffer_info
->skb
);
487 pr_info("R [0x%03X] %016llX "
488 "%016llX %016llX %p", i
,
491 (u64
)rx_buffer_info
->dma
,
492 rx_buffer_info
->skb
);
494 if (netif_msg_pktdata(adapter
)) {
495 print_hex_dump(KERN_INFO
, "",
496 DUMP_PREFIX_ADDRESS
, 16, 1,
497 phys_to_virt(rx_buffer_info
->dma
),
498 rx_ring
->rx_buf_len
, true);
500 if (rx_ring
->rx_buf_len
501 < IXGBE_RXBUFFER_2048
)
502 print_hex_dump(KERN_INFO
, "",
503 DUMP_PREFIX_ADDRESS
, 16, 1,
505 rx_buffer_info
->page_dma
+
506 rx_buffer_info
->page_offset
512 if (i
== rx_ring
->next_to_use
)
514 else if (i
== rx_ring
->next_to_clean
)
526 static void ixgbe_release_hw_control(struct ixgbe_adapter
*adapter
)
530 /* Let firmware take over control of h/w */
531 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
532 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
533 ctrl_ext
& ~IXGBE_CTRL_EXT_DRV_LOAD
);
536 static void ixgbe_get_hw_control(struct ixgbe_adapter
*adapter
)
540 /* Let firmware know the driver has taken over */
541 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
542 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
543 ctrl_ext
| IXGBE_CTRL_EXT_DRV_LOAD
);
547 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
548 * @adapter: pointer to adapter struct
549 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
550 * @queue: queue to map the corresponding interrupt to
551 * @msix_vector: the vector to map to the corresponding queue
554 static void ixgbe_set_ivar(struct ixgbe_adapter
*adapter
, s8 direction
,
555 u8 queue
, u8 msix_vector
)
558 struct ixgbe_hw
*hw
= &adapter
->hw
;
559 switch (hw
->mac
.type
) {
560 case ixgbe_mac_82598EB
:
561 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
564 index
= (((direction
* 64) + queue
) >> 2) & 0x1F;
565 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(index
));
566 ivar
&= ~(0xFF << (8 * (queue
& 0x3)));
567 ivar
|= (msix_vector
<< (8 * (queue
& 0x3)));
568 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(index
), ivar
);
570 case ixgbe_mac_82599EB
:
572 if (direction
== -1) {
574 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
575 index
= ((queue
& 1) * 8);
576 ivar
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_IVAR_MISC
);
577 ivar
&= ~(0xFF << index
);
578 ivar
|= (msix_vector
<< index
);
579 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_IVAR_MISC
, ivar
);
582 /* tx or rx causes */
583 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
584 index
= ((16 * (queue
& 1)) + (8 * direction
));
585 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(queue
>> 1));
586 ivar
&= ~(0xFF << index
);
587 ivar
|= (msix_vector
<< index
);
588 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(queue
>> 1), ivar
);
596 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter
*adapter
,
601 switch (adapter
->hw
.mac
.type
) {
602 case ixgbe_mac_82598EB
:
603 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
604 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS
, mask
);
606 case ixgbe_mac_82599EB
:
608 mask
= (qmask
& 0xFFFFFFFF);
609 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(0), mask
);
610 mask
= (qmask
>> 32);
611 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(1), mask
);
618 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring
*tx_ring
,
619 struct ixgbe_tx_buffer
*tx_buffer_info
)
621 if (tx_buffer_info
->dma
) {
622 if (tx_buffer_info
->mapped_as_page
)
623 dma_unmap_page(tx_ring
->dev
,
625 tx_buffer_info
->length
,
628 dma_unmap_single(tx_ring
->dev
,
630 tx_buffer_info
->length
,
632 tx_buffer_info
->dma
= 0;
634 if (tx_buffer_info
->skb
) {
635 dev_kfree_skb_any(tx_buffer_info
->skb
);
636 tx_buffer_info
->skb
= NULL
;
638 tx_buffer_info
->time_stamp
= 0;
639 /* tx_buffer_info must be completely set up in the transmit path */
643 * ixgbe_dcb_txq_to_tc - convert a reg index to a traffic class
644 * @adapter: driver private struct
645 * @index: reg idx of queue to query (0-127)
647 * Helper function to determine the traffic index for a paticular
650 * Returns : a tc index for use in range 0-7, or 0-3
652 static u8
ixgbe_dcb_txq_to_tc(struct ixgbe_adapter
*adapter
, u8 reg_idx
)
655 int dcb_i
= adapter
->ring_feature
[RING_F_DCB
].indices
;
657 /* if DCB is not enabled the queues have no TC */
658 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
))
661 /* check valid range */
662 if (reg_idx
>= adapter
->hw
.mac
.max_tx_queues
)
665 switch (adapter
->hw
.mac
.type
) {
666 case ixgbe_mac_82598EB
:
670 if (dcb_i
!= 4 && dcb_i
!= 8)
673 /* if VMDq is enabled the lowest order bits determine TC */
674 if (adapter
->flags
& (IXGBE_FLAG_SRIOV_ENABLED
|
675 IXGBE_FLAG_VMDQ_ENABLED
)) {
676 tc
= reg_idx
& (dcb_i
- 1);
681 * Convert the reg_idx into the correct TC. This bitmask
682 * targets the last full 32 ring traffic class and assigns
683 * it a value of 1. From there the rest of the rings are
684 * based on shifting the mask further up to include the
685 * reg_idx / 16 and then reg_idx / 8. It assumes dcB_i
686 * will only ever be 8 or 4 and that reg_idx will never
687 * be greater then 128. The code without the power of 2
688 * optimizations would be:
689 * (((reg_idx % 32) + 32) * dcb_i) >> (9 - reg_idx / 32)
691 tc
= ((reg_idx
& 0X1F) + 0x20) * dcb_i
;
692 tc
>>= 9 - (reg_idx
>> 5);
698 static void ixgbe_update_xoff_received(struct ixgbe_adapter
*adapter
)
700 struct ixgbe_hw
*hw
= &adapter
->hw
;
701 struct ixgbe_hw_stats
*hwstats
= &adapter
->stats
;
706 if ((hw
->fc
.current_mode
== ixgbe_fc_full
) ||
707 (hw
->fc
.current_mode
== ixgbe_fc_rx_pause
)) {
708 switch (hw
->mac
.type
) {
709 case ixgbe_mac_82598EB
:
710 data
= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXC
);
713 data
= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXCNT
);
715 hwstats
->lxoffrxc
+= data
;
717 /* refill credits (no tx hang) if we received xoff */
721 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
722 clear_bit(__IXGBE_HANG_CHECK_ARMED
,
723 &adapter
->tx_ring
[i
]->state
);
725 } else if (!(adapter
->dcb_cfg
.pfc_mode_enable
))
728 /* update stats for each tc, only valid with PFC enabled */
729 for (i
= 0; i
< MAX_TX_PACKET_BUFFERS
; i
++) {
730 switch (hw
->mac
.type
) {
731 case ixgbe_mac_82598EB
:
732 xoff
[i
] = IXGBE_READ_REG(hw
, IXGBE_PXOFFRXC(i
));
735 xoff
[i
] = IXGBE_READ_REG(hw
, IXGBE_PXOFFRXCNT(i
));
737 hwstats
->pxoffrxc
[i
] += xoff
[i
];
740 /* disarm tx queues that have received xoff frames */
741 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
742 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[i
];
743 u32 tc
= ixgbe_dcb_txq_to_tc(adapter
, tx_ring
->reg_idx
);
746 clear_bit(__IXGBE_HANG_CHECK_ARMED
, &tx_ring
->state
);
750 static u64
ixgbe_get_tx_completed(struct ixgbe_ring
*ring
)
752 return ring
->tx_stats
.completed
;
755 static u64
ixgbe_get_tx_pending(struct ixgbe_ring
*ring
)
757 struct ixgbe_adapter
*adapter
= netdev_priv(ring
->netdev
);
758 struct ixgbe_hw
*hw
= &adapter
->hw
;
760 u32 head
= IXGBE_READ_REG(hw
, IXGBE_TDH(ring
->reg_idx
));
761 u32 tail
= IXGBE_READ_REG(hw
, IXGBE_TDT(ring
->reg_idx
));
764 return (head
< tail
) ?
765 tail
- head
: (tail
+ ring
->count
- head
);
770 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring
*tx_ring
)
772 u32 tx_done
= ixgbe_get_tx_completed(tx_ring
);
773 u32 tx_done_old
= tx_ring
->tx_stats
.tx_done_old
;
774 u32 tx_pending
= ixgbe_get_tx_pending(tx_ring
);
777 clear_check_for_tx_hang(tx_ring
);
780 * Check for a hung queue, but be thorough. This verifies
781 * that a transmit has been completed since the previous
782 * check AND there is at least one packet pending. The
783 * ARMED bit is set to indicate a potential hang. The
784 * bit is cleared if a pause frame is received to remove
785 * false hang detection due to PFC or 802.3x frames. By
786 * requiring this to fail twice we avoid races with
787 * pfc clearing the ARMED bit and conditions where we
788 * run the check_tx_hang logic with a transmit completion
789 * pending but without time to complete it yet.
791 if ((tx_done_old
== tx_done
) && tx_pending
) {
792 /* make sure it is true for two checks in a row */
793 ret
= test_and_set_bit(__IXGBE_HANG_CHECK_ARMED
,
796 /* update completed stats and continue */
797 tx_ring
->tx_stats
.tx_done_old
= tx_done
;
798 /* reset the countdown */
799 clear_bit(__IXGBE_HANG_CHECK_ARMED
, &tx_ring
->state
);
805 #define IXGBE_MAX_TXD_PWR 14
806 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
808 /* Tx Descriptors needed, worst case */
809 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
810 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
811 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
812 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
814 static void ixgbe_tx_timeout(struct net_device
*netdev
);
817 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
818 * @q_vector: structure containing interrupt and ring information
819 * @tx_ring: tx ring to clean
821 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector
*q_vector
,
822 struct ixgbe_ring
*tx_ring
)
824 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
825 union ixgbe_adv_tx_desc
*tx_desc
, *eop_desc
;
826 struct ixgbe_tx_buffer
*tx_buffer_info
;
827 unsigned int total_bytes
= 0, total_packets
= 0;
828 u16 i
, eop
, count
= 0;
830 i
= tx_ring
->next_to_clean
;
831 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
832 eop_desc
= IXGBE_TX_DESC_ADV(tx_ring
, eop
);
834 while ((eop_desc
->wb
.status
& cpu_to_le32(IXGBE_TXD_STAT_DD
)) &&
835 (count
< tx_ring
->work_limit
)) {
836 bool cleaned
= false;
837 rmb(); /* read buffer_info after eop_desc */
838 for ( ; !cleaned
; count
++) {
839 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, i
);
840 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
842 tx_desc
->wb
.status
= 0;
843 cleaned
= (i
== eop
);
846 if (i
== tx_ring
->count
)
849 if (cleaned
&& tx_buffer_info
->skb
) {
850 total_bytes
+= tx_buffer_info
->bytecount
;
851 total_packets
+= tx_buffer_info
->gso_segs
;
854 ixgbe_unmap_and_free_tx_resource(tx_ring
,
858 tx_ring
->tx_stats
.completed
++;
859 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
860 eop_desc
= IXGBE_TX_DESC_ADV(tx_ring
, eop
);
863 tx_ring
->next_to_clean
= i
;
864 tx_ring
->total_bytes
+= total_bytes
;
865 tx_ring
->total_packets
+= total_packets
;
866 u64_stats_update_begin(&tx_ring
->syncp
);
867 tx_ring
->stats
.packets
+= total_packets
;
868 tx_ring
->stats
.bytes
+= total_bytes
;
869 u64_stats_update_end(&tx_ring
->syncp
);
871 if (check_for_tx_hang(tx_ring
) && ixgbe_check_tx_hang(tx_ring
)) {
872 /* schedule immediate reset if we believe we hung */
873 struct ixgbe_hw
*hw
= &adapter
->hw
;
874 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, eop
);
875 e_err(drv
, "Detected Tx Unit Hang\n"
877 " TDH, TDT <%x>, <%x>\n"
878 " next_to_use <%x>\n"
879 " next_to_clean <%x>\n"
880 "tx_buffer_info[next_to_clean]\n"
881 " time_stamp <%lx>\n"
883 tx_ring
->queue_index
,
884 IXGBE_READ_REG(hw
, IXGBE_TDH(tx_ring
->reg_idx
)),
885 IXGBE_READ_REG(hw
, IXGBE_TDT(tx_ring
->reg_idx
)),
886 tx_ring
->next_to_use
, eop
,
887 tx_ring
->tx_buffer_info
[eop
].time_stamp
, jiffies
);
889 netif_stop_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
892 "tx hang %d detected on queue %d, resetting adapter\n",
893 adapter
->tx_timeout_count
+ 1, tx_ring
->queue_index
);
895 /* schedule immediate reset if we believe we hung */
896 ixgbe_tx_timeout(adapter
->netdev
);
898 /* the adapter is about to reset, no point in enabling stuff */
902 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
903 if (unlikely(count
&& netif_carrier_ok(tx_ring
->netdev
) &&
904 (IXGBE_DESC_UNUSED(tx_ring
) >= TX_WAKE_THRESHOLD
))) {
905 /* Make sure that anybody stopping the queue after this
906 * sees the new next_to_clean.
909 if (__netif_subqueue_stopped(tx_ring
->netdev
, tx_ring
->queue_index
) &&
910 !test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
911 netif_wake_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
912 ++tx_ring
->tx_stats
.restart_queue
;
916 return count
< tx_ring
->work_limit
;
919 #ifdef CONFIG_IXGBE_DCA
920 static void ixgbe_update_rx_dca(struct ixgbe_adapter
*adapter
,
921 struct ixgbe_ring
*rx_ring
,
924 struct ixgbe_hw
*hw
= &adapter
->hw
;
926 u8 reg_idx
= rx_ring
->reg_idx
;
928 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_RXCTRL(reg_idx
));
929 switch (hw
->mac
.type
) {
930 case ixgbe_mac_82598EB
:
931 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK
;
932 rxctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
934 case ixgbe_mac_82599EB
:
936 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599
;
937 rxctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
938 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599
);
943 rxctrl
|= IXGBE_DCA_RXCTRL_DESC_DCA_EN
;
944 rxctrl
|= IXGBE_DCA_RXCTRL_HEAD_DCA_EN
;
945 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN
);
946 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN
|
947 IXGBE_DCA_RXCTRL_DESC_HSRO_EN
);
948 IXGBE_WRITE_REG(hw
, IXGBE_DCA_RXCTRL(reg_idx
), rxctrl
);
951 static void ixgbe_update_tx_dca(struct ixgbe_adapter
*adapter
,
952 struct ixgbe_ring
*tx_ring
,
955 struct ixgbe_hw
*hw
= &adapter
->hw
;
957 u8 reg_idx
= tx_ring
->reg_idx
;
959 switch (hw
->mac
.type
) {
960 case ixgbe_mac_82598EB
:
961 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL(reg_idx
));
962 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK
;
963 txctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
964 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
965 txctrl
&= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN
;
966 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL(reg_idx
), txctrl
);
968 case ixgbe_mac_82599EB
:
970 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL_82599(reg_idx
));
971 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599
;
972 txctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
973 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599
);
974 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
975 txctrl
&= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN
;
976 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL_82599(reg_idx
), txctrl
);
983 static void ixgbe_update_dca(struct ixgbe_q_vector
*q_vector
)
985 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
990 if (q_vector
->cpu
== cpu
)
993 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
994 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
995 ixgbe_update_tx_dca(adapter
, adapter
->tx_ring
[r_idx
], cpu
);
996 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1000 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1001 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1002 ixgbe_update_rx_dca(adapter
, adapter
->rx_ring
[r_idx
], cpu
);
1003 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1007 q_vector
->cpu
= cpu
;
1012 static void ixgbe_setup_dca(struct ixgbe_adapter
*adapter
)
1017 if (!(adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
))
1020 /* always use CB2 mode, difference is masked in the CB driver */
1021 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 2);
1023 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
1024 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1028 for (i
= 0; i
< num_q_vectors
; i
++) {
1029 adapter
->q_vector
[i
]->cpu
= -1;
1030 ixgbe_update_dca(adapter
->q_vector
[i
]);
1034 static int __ixgbe_notify_dca(struct device
*dev
, void *data
)
1036 struct ixgbe_adapter
*adapter
= dev_get_drvdata(dev
);
1037 unsigned long event
= *(unsigned long *)data
;
1039 if (!(adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
))
1043 case DCA_PROVIDER_ADD
:
1044 /* if we're already enabled, don't do it again */
1045 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1047 if (dca_add_requester(dev
) == 0) {
1048 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
1049 ixgbe_setup_dca(adapter
);
1052 /* Fall Through since DCA is disabled. */
1053 case DCA_PROVIDER_REMOVE
:
1054 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
1055 dca_remove_requester(dev
);
1056 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
1057 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
1065 #endif /* CONFIG_IXGBE_DCA */
1067 * ixgbe_receive_skb - Send a completed packet up the stack
1068 * @adapter: board private structure
1069 * @skb: packet to send up
1070 * @status: hardware indication of status of receive
1071 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1072 * @rx_desc: rx descriptor
1074 static void ixgbe_receive_skb(struct ixgbe_q_vector
*q_vector
,
1075 struct sk_buff
*skb
, u8 status
,
1076 struct ixgbe_ring
*ring
,
1077 union ixgbe_adv_rx_desc
*rx_desc
)
1079 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1080 struct napi_struct
*napi
= &q_vector
->napi
;
1081 bool is_vlan
= (status
& IXGBE_RXD_STAT_VP
);
1082 u16 tag
= le16_to_cpu(rx_desc
->wb
.upper
.vlan
);
1084 if (is_vlan
&& (tag
& VLAN_VID_MASK
))
1085 __vlan_hwaccel_put_tag(skb
, tag
);
1087 if (!(adapter
->flags
& IXGBE_FLAG_IN_NETPOLL
))
1088 napi_gro_receive(napi
, skb
);
1094 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1095 * @adapter: address of board private structure
1096 * @status_err: hardware indication of status of receive
1097 * @skb: skb currently being received and modified
1099 static inline void ixgbe_rx_checksum(struct ixgbe_adapter
*adapter
,
1100 union ixgbe_adv_rx_desc
*rx_desc
,
1101 struct sk_buff
*skb
)
1103 u32 status_err
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1105 skb_checksum_none_assert(skb
);
1107 /* Rx csum disabled */
1108 if (!(adapter
->flags
& IXGBE_FLAG_RX_CSUM_ENABLED
))
1111 /* if IP and error */
1112 if ((status_err
& IXGBE_RXD_STAT_IPCS
) &&
1113 (status_err
& IXGBE_RXDADV_ERR_IPE
)) {
1114 adapter
->hw_csum_rx_error
++;
1118 if (!(status_err
& IXGBE_RXD_STAT_L4CS
))
1121 if (status_err
& IXGBE_RXDADV_ERR_TCPE
) {
1122 u16 pkt_info
= rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
1125 * 82599 errata, UDP frames with a 0 checksum can be marked as
1128 if ((pkt_info
& IXGBE_RXDADV_PKTTYPE_UDP
) &&
1129 (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
))
1132 adapter
->hw_csum_rx_error
++;
1136 /* It must be a TCP or UDP packet with a valid checksum */
1137 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1140 static inline void ixgbe_release_rx_desc(struct ixgbe_ring
*rx_ring
, u32 val
)
1143 * Force memory writes to complete before letting h/w
1144 * know there are new descriptors to fetch. (Only
1145 * applicable for weak-ordered memory model archs,
1149 writel(val
, rx_ring
->tail
);
1153 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1154 * @rx_ring: ring to place buffers on
1155 * @cleaned_count: number of buffers to replace
1157 void ixgbe_alloc_rx_buffers(struct ixgbe_ring
*rx_ring
, u16 cleaned_count
)
1159 union ixgbe_adv_rx_desc
*rx_desc
;
1160 struct ixgbe_rx_buffer
*bi
;
1161 struct sk_buff
*skb
;
1162 u16 i
= rx_ring
->next_to_use
;
1164 /* do nothing if no valid netdev defined */
1165 if (!rx_ring
->netdev
)
1168 while (cleaned_count
--) {
1169 rx_desc
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
1170 bi
= &rx_ring
->rx_buffer_info
[i
];
1174 skb
= netdev_alloc_skb_ip_align(rx_ring
->netdev
,
1175 rx_ring
->rx_buf_len
);
1177 rx_ring
->rx_stats
.alloc_rx_buff_failed
++;
1180 /* initialize queue mapping */
1181 skb_record_rx_queue(skb
, rx_ring
->queue_index
);
1186 bi
->dma
= dma_map_single(rx_ring
->dev
,
1188 rx_ring
->rx_buf_len
,
1190 if (dma_mapping_error(rx_ring
->dev
, bi
->dma
)) {
1191 rx_ring
->rx_stats
.alloc_rx_buff_failed
++;
1197 if (ring_is_ps_enabled(rx_ring
)) {
1199 bi
->page
= netdev_alloc_page(rx_ring
->netdev
);
1201 rx_ring
->rx_stats
.alloc_rx_page_failed
++;
1206 if (!bi
->page_dma
) {
1207 /* use a half page if we're re-using */
1208 bi
->page_offset
^= PAGE_SIZE
/ 2;
1209 bi
->page_dma
= dma_map_page(rx_ring
->dev
,
1214 if (dma_mapping_error(rx_ring
->dev
,
1216 rx_ring
->rx_stats
.alloc_rx_page_failed
++;
1222 /* Refresh the desc even if buffer_addrs didn't change
1223 * because each write-back erases this info. */
1224 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->page_dma
);
1225 rx_desc
->read
.hdr_addr
= cpu_to_le64(bi
->dma
);
1227 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->dma
);
1228 rx_desc
->read
.hdr_addr
= 0;
1232 if (i
== rx_ring
->count
)
1237 if (rx_ring
->next_to_use
!= i
) {
1238 rx_ring
->next_to_use
= i
;
1239 ixgbe_release_rx_desc(rx_ring
, i
);
1243 static inline u16
ixgbe_get_hlen(union ixgbe_adv_rx_desc
*rx_desc
)
1245 /* HW will not DMA in data larger than the given buffer, even if it
1246 * parses the (NFS, of course) header to be larger. In that case, it
1247 * fills the header buffer and spills the rest into the page.
1249 u16 hdr_info
= le16_to_cpu(rx_desc
->wb
.lower
.lo_dword
.hs_rss
.hdr_info
);
1250 u16 hlen
= (hdr_info
& IXGBE_RXDADV_HDRBUFLEN_MASK
) >>
1251 IXGBE_RXDADV_HDRBUFLEN_SHIFT
;
1252 if (hlen
> IXGBE_RX_HDR_SIZE
)
1253 hlen
= IXGBE_RX_HDR_SIZE
;
1258 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1259 * @skb: pointer to the last skb in the rsc queue
1261 * This function changes a queue full of hw rsc buffers into a completed
1262 * packet. It uses the ->prev pointers to find the first packet and then
1263 * turns it into the frag list owner.
1265 static inline struct sk_buff
*ixgbe_transform_rsc_queue(struct sk_buff
*skb
)
1267 unsigned int frag_list_size
= 0;
1268 unsigned int skb_cnt
= 1;
1271 struct sk_buff
*prev
= skb
->prev
;
1272 frag_list_size
+= skb
->len
;
1278 skb_shinfo(skb
)->frag_list
= skb
->next
;
1280 skb
->len
+= frag_list_size
;
1281 skb
->data_len
+= frag_list_size
;
1282 skb
->truesize
+= frag_list_size
;
1283 IXGBE_RSC_CB(skb
)->skb_cnt
= skb_cnt
;
1288 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc
*rx_desc
)
1290 return !!(le32_to_cpu(rx_desc
->wb
.lower
.lo_dword
.data
) &
1291 IXGBE_RXDADV_RSCCNT_MASK
);
1294 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector
*q_vector
,
1295 struct ixgbe_ring
*rx_ring
,
1296 int *work_done
, int work_to_do
)
1298 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1299 union ixgbe_adv_rx_desc
*rx_desc
, *next_rxd
;
1300 struct ixgbe_rx_buffer
*rx_buffer_info
, *next_buffer
;
1301 struct sk_buff
*skb
;
1302 unsigned int total_rx_bytes
= 0, total_rx_packets
= 0;
1303 const int current_node
= numa_node_id();
1306 #endif /* IXGBE_FCOE */
1309 u16 cleaned_count
= 0;
1310 bool pkt_is_rsc
= false;
1312 i
= rx_ring
->next_to_clean
;
1313 rx_desc
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
1314 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1316 while (staterr
& IXGBE_RXD_STAT_DD
) {
1319 rmb(); /* read descriptor and rx_buffer_info after status DD */
1321 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
1323 skb
= rx_buffer_info
->skb
;
1324 rx_buffer_info
->skb
= NULL
;
1325 prefetch(skb
->data
);
1327 if (ring_is_rsc_enabled(rx_ring
))
1328 pkt_is_rsc
= ixgbe_get_rsc_state(rx_desc
);
1330 /* if this is a skb from previous receive DMA will be 0 */
1331 if (rx_buffer_info
->dma
) {
1334 !(staterr
& IXGBE_RXD_STAT_EOP
) &&
1337 * When HWRSC is enabled, delay unmapping
1338 * of the first packet. It carries the
1339 * header information, HW may still
1340 * access the header after the writeback.
1341 * Only unmap it when EOP is reached
1343 IXGBE_RSC_CB(skb
)->delay_unmap
= true;
1344 IXGBE_RSC_CB(skb
)->dma
= rx_buffer_info
->dma
;
1346 dma_unmap_single(rx_ring
->dev
,
1347 rx_buffer_info
->dma
,
1348 rx_ring
->rx_buf_len
,
1351 rx_buffer_info
->dma
= 0;
1353 if (ring_is_ps_enabled(rx_ring
)) {
1354 hlen
= ixgbe_get_hlen(rx_desc
);
1355 upper_len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1357 hlen
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1362 /* assume packet split since header is unmapped */
1363 upper_len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1367 dma_unmap_page(rx_ring
->dev
,
1368 rx_buffer_info
->page_dma
,
1371 rx_buffer_info
->page_dma
= 0;
1372 skb_fill_page_desc(skb
, skb_shinfo(skb
)->nr_frags
,
1373 rx_buffer_info
->page
,
1374 rx_buffer_info
->page_offset
,
1377 if ((page_count(rx_buffer_info
->page
) == 1) &&
1378 (page_to_nid(rx_buffer_info
->page
) == current_node
))
1379 get_page(rx_buffer_info
->page
);
1381 rx_buffer_info
->page
= NULL
;
1383 skb
->len
+= upper_len
;
1384 skb
->data_len
+= upper_len
;
1385 skb
->truesize
+= upper_len
;
1389 if (i
== rx_ring
->count
)
1392 next_rxd
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
1397 u32 nextp
= (staterr
& IXGBE_RXDADV_NEXTP_MASK
) >>
1398 IXGBE_RXDADV_NEXTP_SHIFT
;
1399 next_buffer
= &rx_ring
->rx_buffer_info
[nextp
];
1401 next_buffer
= &rx_ring
->rx_buffer_info
[i
];
1404 if (!(staterr
& IXGBE_RXD_STAT_EOP
)) {
1405 if (ring_is_ps_enabled(rx_ring
)) {
1406 rx_buffer_info
->skb
= next_buffer
->skb
;
1407 rx_buffer_info
->dma
= next_buffer
->dma
;
1408 next_buffer
->skb
= skb
;
1409 next_buffer
->dma
= 0;
1411 skb
->next
= next_buffer
->skb
;
1412 skb
->next
->prev
= skb
;
1414 rx_ring
->rx_stats
.non_eop_descs
++;
1419 skb
= ixgbe_transform_rsc_queue(skb
);
1420 /* if we got here without RSC the packet is invalid */
1422 __pskb_trim(skb
, 0);
1423 rx_buffer_info
->skb
= skb
;
1428 if (ring_is_rsc_enabled(rx_ring
)) {
1429 if (IXGBE_RSC_CB(skb
)->delay_unmap
) {
1430 dma_unmap_single(rx_ring
->dev
,
1431 IXGBE_RSC_CB(skb
)->dma
,
1432 rx_ring
->rx_buf_len
,
1434 IXGBE_RSC_CB(skb
)->dma
= 0;
1435 IXGBE_RSC_CB(skb
)->delay_unmap
= false;
1439 if (ring_is_ps_enabled(rx_ring
))
1440 rx_ring
->rx_stats
.rsc_count
+=
1441 skb_shinfo(skb
)->nr_frags
;
1443 rx_ring
->rx_stats
.rsc_count
+=
1444 IXGBE_RSC_CB(skb
)->skb_cnt
;
1445 rx_ring
->rx_stats
.rsc_flush
++;
1448 /* ERR_MASK will only have valid bits if EOP set */
1449 if (staterr
& IXGBE_RXDADV_ERR_FRAME_ERR_MASK
) {
1450 /* trim packet back to size 0 and recycle it */
1451 __pskb_trim(skb
, 0);
1452 rx_buffer_info
->skb
= skb
;
1456 ixgbe_rx_checksum(adapter
, rx_desc
, skb
);
1458 /* probably a little skewed due to removing CRC */
1459 total_rx_bytes
+= skb
->len
;
1462 skb
->protocol
= eth_type_trans(skb
, rx_ring
->netdev
);
1464 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1465 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
1466 ddp_bytes
= ixgbe_fcoe_ddp(adapter
, rx_desc
, skb
);
1470 #endif /* IXGBE_FCOE */
1471 ixgbe_receive_skb(q_vector
, skb
, staterr
, rx_ring
, rx_desc
);
1474 rx_desc
->wb
.upper
.status_error
= 0;
1477 if (*work_done
>= work_to_do
)
1480 /* return some buffers to hardware, one at a time is too slow */
1481 if (cleaned_count
>= IXGBE_RX_BUFFER_WRITE
) {
1482 ixgbe_alloc_rx_buffers(rx_ring
, cleaned_count
);
1486 /* use prefetched values */
1488 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1491 rx_ring
->next_to_clean
= i
;
1492 cleaned_count
= IXGBE_DESC_UNUSED(rx_ring
);
1495 ixgbe_alloc_rx_buffers(rx_ring
, cleaned_count
);
1498 /* include DDPed FCoE data */
1499 if (ddp_bytes
> 0) {
1502 mss
= rx_ring
->netdev
->mtu
- sizeof(struct fcoe_hdr
) -
1503 sizeof(struct fc_frame_header
) -
1504 sizeof(struct fcoe_crc_eof
);
1507 total_rx_bytes
+= ddp_bytes
;
1508 total_rx_packets
+= DIV_ROUND_UP(ddp_bytes
, mss
);
1510 #endif /* IXGBE_FCOE */
1512 rx_ring
->total_packets
+= total_rx_packets
;
1513 rx_ring
->total_bytes
+= total_rx_bytes
;
1514 u64_stats_update_begin(&rx_ring
->syncp
);
1515 rx_ring
->stats
.packets
+= total_rx_packets
;
1516 rx_ring
->stats
.bytes
+= total_rx_bytes
;
1517 u64_stats_update_end(&rx_ring
->syncp
);
1520 static int ixgbe_clean_rxonly(struct napi_struct
*, int);
1522 * ixgbe_configure_msix - Configure MSI-X hardware
1523 * @adapter: board private structure
1525 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1528 static void ixgbe_configure_msix(struct ixgbe_adapter
*adapter
)
1530 struct ixgbe_q_vector
*q_vector
;
1531 int i
, q_vectors
, v_idx
, r_idx
;
1534 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1537 * Populate the IVAR table and set the ITR values to the
1538 * corresponding register.
1540 for (v_idx
= 0; v_idx
< q_vectors
; v_idx
++) {
1541 q_vector
= adapter
->q_vector
[v_idx
];
1542 /* XXX for_each_set_bit(...) */
1543 r_idx
= find_first_bit(q_vector
->rxr_idx
,
1544 adapter
->num_rx_queues
);
1546 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1547 u8 reg_idx
= adapter
->rx_ring
[r_idx
]->reg_idx
;
1548 ixgbe_set_ivar(adapter
, 0, reg_idx
, v_idx
);
1549 r_idx
= find_next_bit(q_vector
->rxr_idx
,
1550 adapter
->num_rx_queues
,
1553 r_idx
= find_first_bit(q_vector
->txr_idx
,
1554 adapter
->num_tx_queues
);
1556 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1557 u8 reg_idx
= adapter
->tx_ring
[r_idx
]->reg_idx
;
1558 ixgbe_set_ivar(adapter
, 1, reg_idx
, v_idx
);
1559 r_idx
= find_next_bit(q_vector
->txr_idx
,
1560 adapter
->num_tx_queues
,
1564 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
1566 q_vector
->eitr
= adapter
->tx_eitr_param
;
1567 else if (q_vector
->rxr_count
)
1569 q_vector
->eitr
= adapter
->rx_eitr_param
;
1571 ixgbe_write_eitr(q_vector
);
1572 /* If Flow Director is enabled, set interrupt affinity */
1573 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
1574 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)) {
1576 * Allocate the affinity_hint cpumask, assign the mask
1577 * for this vector, and set our affinity_hint for
1580 if (!alloc_cpumask_var(&q_vector
->affinity_mask
,
1583 cpumask_set_cpu(v_idx
, q_vector
->affinity_mask
);
1584 irq_set_affinity_hint(adapter
->msix_entries
[v_idx
].vector
,
1585 q_vector
->affinity_mask
);
1589 switch (adapter
->hw
.mac
.type
) {
1590 case ixgbe_mac_82598EB
:
1591 ixgbe_set_ivar(adapter
, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX
,
1594 case ixgbe_mac_82599EB
:
1595 case ixgbe_mac_X540
:
1596 ixgbe_set_ivar(adapter
, -1, 1, v_idx
);
1602 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITR(v_idx
), 1950);
1604 /* set up to autoclear timer, and the vectors */
1605 mask
= IXGBE_EIMS_ENABLE_MASK
;
1606 if (adapter
->num_vfs
)
1607 mask
&= ~(IXGBE_EIMS_OTHER
|
1608 IXGBE_EIMS_MAILBOX
|
1611 mask
&= ~(IXGBE_EIMS_OTHER
| IXGBE_EIMS_LSC
);
1612 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIAC
, mask
);
1615 enum latency_range
{
1619 latency_invalid
= 255
1623 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1624 * @adapter: pointer to adapter
1625 * @eitr: eitr setting (ints per sec) to give last timeslice
1626 * @itr_setting: current throttle rate in ints/second
1627 * @packets: the number of packets during this measurement interval
1628 * @bytes: the number of bytes during this measurement interval
1630 * Stores a new ITR value based on packets and byte
1631 * counts during the last interrupt. The advantage of per interrupt
1632 * computation is faster updates and more accurate ITR for the current
1633 * traffic pattern. Constants in this function were computed
1634 * based on theoretical maximum wire speed and thresholds were set based
1635 * on testing data as well as attempting to minimize response time
1636 * while increasing bulk throughput.
1637 * this functionality is controlled by the InterruptThrottleRate module
1638 * parameter (see ixgbe_param.c)
1640 static u8
ixgbe_update_itr(struct ixgbe_adapter
*adapter
,
1641 u32 eitr
, u8 itr_setting
,
1642 int packets
, int bytes
)
1644 unsigned int retval
= itr_setting
;
1649 goto update_itr_done
;
1652 /* simple throttlerate management
1653 * 0-20MB/s lowest (100000 ints/s)
1654 * 20-100MB/s low (20000 ints/s)
1655 * 100-1249MB/s bulk (8000 ints/s)
1657 /* what was last interrupt timeslice? */
1658 timepassed_us
= 1000000/eitr
;
1659 bytes_perint
= bytes
/ timepassed_us
; /* bytes/usec */
1661 switch (itr_setting
) {
1662 case lowest_latency
:
1663 if (bytes_perint
> adapter
->eitr_low
)
1664 retval
= low_latency
;
1667 if (bytes_perint
> adapter
->eitr_high
)
1668 retval
= bulk_latency
;
1669 else if (bytes_perint
<= adapter
->eitr_low
)
1670 retval
= lowest_latency
;
1673 if (bytes_perint
<= adapter
->eitr_high
)
1674 retval
= low_latency
;
1683 * ixgbe_write_eitr - write EITR register in hardware specific way
1684 * @q_vector: structure containing interrupt and ring information
1686 * This function is made to be called by ethtool and by the driver
1687 * when it needs to update EITR registers at runtime. Hardware
1688 * specific quirks/differences are taken care of here.
1690 void ixgbe_write_eitr(struct ixgbe_q_vector
*q_vector
)
1692 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1693 struct ixgbe_hw
*hw
= &adapter
->hw
;
1694 int v_idx
= q_vector
->v_idx
;
1695 u32 itr_reg
= EITR_INTS_PER_SEC_TO_REG(q_vector
->eitr
);
1697 switch (adapter
->hw
.mac
.type
) {
1698 case ixgbe_mac_82598EB
:
1699 /* must write high and low 16 bits to reset counter */
1700 itr_reg
|= (itr_reg
<< 16);
1702 case ixgbe_mac_82599EB
:
1703 case ixgbe_mac_X540
:
1705 * 82599 and X540 can support a value of zero, so allow it for
1706 * max interrupt rate, but there is an errata where it can
1707 * not be zero with RSC
1710 !(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
))
1714 * set the WDIS bit to not clear the timer bits and cause an
1715 * immediate assertion of the interrupt
1717 itr_reg
|= IXGBE_EITR_CNT_WDIS
;
1722 IXGBE_WRITE_REG(hw
, IXGBE_EITR(v_idx
), itr_reg
);
1725 static void ixgbe_set_itr_msix(struct ixgbe_q_vector
*q_vector
)
1727 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1730 u8 current_itr
, ret_itr
;
1732 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1733 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1734 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[r_idx
];
1735 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1737 tx_ring
->total_packets
,
1738 tx_ring
->total_bytes
);
1739 /* if the result for this queue would decrease interrupt
1740 * rate for this vector then use that result */
1741 q_vector
->tx_itr
= ((q_vector
->tx_itr
> ret_itr
) ?
1742 q_vector
->tx_itr
- 1 : ret_itr
);
1743 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1747 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1748 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1749 struct ixgbe_ring
*rx_ring
= adapter
->rx_ring
[r_idx
];
1750 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1752 rx_ring
->total_packets
,
1753 rx_ring
->total_bytes
);
1754 /* if the result for this queue would decrease interrupt
1755 * rate for this vector then use that result */
1756 q_vector
->rx_itr
= ((q_vector
->rx_itr
> ret_itr
) ?
1757 q_vector
->rx_itr
- 1 : ret_itr
);
1758 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1762 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
1764 switch (current_itr
) {
1765 /* counts and packets in update_itr are dependent on these numbers */
1766 case lowest_latency
:
1770 new_itr
= 20000; /* aka hwitr = ~200 */
1778 if (new_itr
!= q_vector
->eitr
) {
1779 /* do an exponential smoothing */
1780 new_itr
= ((q_vector
->eitr
* 9) + new_itr
)/10;
1782 /* save the algorithm value here, not the smoothed one */
1783 q_vector
->eitr
= new_itr
;
1785 ixgbe_write_eitr(q_vector
);
1790 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1791 * @work: pointer to work_struct containing our data
1793 static void ixgbe_check_overtemp_task(struct work_struct
*work
)
1795 struct ixgbe_adapter
*adapter
= container_of(work
,
1796 struct ixgbe_adapter
,
1797 check_overtemp_task
);
1798 struct ixgbe_hw
*hw
= &adapter
->hw
;
1799 u32 eicr
= adapter
->interrupt_event
;
1801 if (!(adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
))
1804 switch (hw
->device_id
) {
1805 case IXGBE_DEV_ID_82599_T3_LOM
: {
1807 bool link_up
= false;
1809 if (hw
->mac
.ops
.check_link
)
1810 hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
1812 if (((eicr
& IXGBE_EICR_GPI_SDP0
) && (!link_up
)) ||
1813 (eicr
& IXGBE_EICR_LSC
))
1814 /* Check if this is due to overtemp */
1815 if (hw
->phy
.ops
.check_overtemp(hw
) == IXGBE_ERR_OVERTEMP
)
1820 if (!(eicr
& IXGBE_EICR_GPI_SDP0
))
1825 "Network adapter has been stopped because it has over heated. "
1826 "Restart the computer. If the problem persists, "
1827 "power off the system and replace the adapter\n");
1828 /* write to clear the interrupt */
1829 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP0
);
1832 static void ixgbe_check_fan_failure(struct ixgbe_adapter
*adapter
, u32 eicr
)
1834 struct ixgbe_hw
*hw
= &adapter
->hw
;
1836 if ((adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) &&
1837 (eicr
& IXGBE_EICR_GPI_SDP1
)) {
1838 e_crit(probe
, "Fan has stopped, replace the adapter\n");
1839 /* write to clear the interrupt */
1840 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1844 static void ixgbe_check_sfp_event(struct ixgbe_adapter
*adapter
, u32 eicr
)
1846 struct ixgbe_hw
*hw
= &adapter
->hw
;
1848 if (eicr
& IXGBE_EICR_GPI_SDP2
) {
1849 /* Clear the interrupt */
1850 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP2
);
1851 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1852 schedule_work(&adapter
->sfp_config_module_task
);
1855 if (eicr
& IXGBE_EICR_GPI_SDP1
) {
1856 /* Clear the interrupt */
1857 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1858 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1859 schedule_work(&adapter
->multispeed_fiber_task
);
1863 static void ixgbe_check_lsc(struct ixgbe_adapter
*adapter
)
1865 struct ixgbe_hw
*hw
= &adapter
->hw
;
1868 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
1869 adapter
->link_check_timeout
= jiffies
;
1870 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1871 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_EIMC_LSC
);
1872 IXGBE_WRITE_FLUSH(hw
);
1873 schedule_work(&adapter
->watchdog_task
);
1877 static irqreturn_t
ixgbe_msix_lsc(int irq
, void *data
)
1879 struct net_device
*netdev
= data
;
1880 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
1881 struct ixgbe_hw
*hw
= &adapter
->hw
;
1885 * Workaround for Silicon errata. Use clear-by-write instead
1886 * of clear-by-read. Reading with EICS will return the
1887 * interrupt causes without clearing, which later be done
1888 * with the write to EICR.
1890 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICS
);
1891 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, eicr
);
1893 if (eicr
& IXGBE_EICR_LSC
)
1894 ixgbe_check_lsc(adapter
);
1896 if (eicr
& IXGBE_EICR_MAILBOX
)
1897 ixgbe_msg_task(adapter
);
1899 switch (hw
->mac
.type
) {
1900 case ixgbe_mac_82599EB
:
1901 ixgbe_check_sfp_event(adapter
, eicr
);
1902 if ((adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) &&
1903 ((eicr
& IXGBE_EICR_GPI_SDP0
) || (eicr
& IXGBE_EICR_LSC
))) {
1904 adapter
->interrupt_event
= eicr
;
1905 schedule_work(&adapter
->check_overtemp_task
);
1907 /* now fallthrough to handle Flow Director */
1908 case ixgbe_mac_X540
:
1909 /* Handle Flow Director Full threshold interrupt */
1910 if (eicr
& IXGBE_EICR_FLOW_DIR
) {
1912 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_FLOW_DIR
);
1913 /* Disable transmits before FDIR Re-initialization */
1914 netif_tx_stop_all_queues(netdev
);
1915 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
1916 struct ixgbe_ring
*tx_ring
=
1917 adapter
->tx_ring
[i
];
1918 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE
,
1920 schedule_work(&adapter
->fdir_reinit_task
);
1928 ixgbe_check_fan_failure(adapter
, eicr
);
1930 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1931 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMS_OTHER
);
1936 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter
*adapter
,
1940 struct ixgbe_hw
*hw
= &adapter
->hw
;
1942 switch (hw
->mac
.type
) {
1943 case ixgbe_mac_82598EB
:
1944 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1945 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, mask
);
1947 case ixgbe_mac_82599EB
:
1948 case ixgbe_mac_X540
:
1949 mask
= (qmask
& 0xFFFFFFFF);
1951 IXGBE_WRITE_REG(hw
, IXGBE_EIMS_EX(0), mask
);
1952 mask
= (qmask
>> 32);
1954 IXGBE_WRITE_REG(hw
, IXGBE_EIMS_EX(1), mask
);
1959 /* skip the flush */
1962 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter
*adapter
,
1966 struct ixgbe_hw
*hw
= &adapter
->hw
;
1968 switch (hw
->mac
.type
) {
1969 case ixgbe_mac_82598EB
:
1970 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1971 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, mask
);
1973 case ixgbe_mac_82599EB
:
1974 case ixgbe_mac_X540
:
1975 mask
= (qmask
& 0xFFFFFFFF);
1977 IXGBE_WRITE_REG(hw
, IXGBE_EIMC_EX(0), mask
);
1978 mask
= (qmask
>> 32);
1980 IXGBE_WRITE_REG(hw
, IXGBE_EIMC_EX(1), mask
);
1985 /* skip the flush */
1988 static irqreturn_t
ixgbe_msix_clean_tx(int irq
, void *data
)
1990 struct ixgbe_q_vector
*q_vector
= data
;
1991 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1992 struct ixgbe_ring
*tx_ring
;
1995 if (!q_vector
->txr_count
)
1998 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1999 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
2000 tx_ring
= adapter
->tx_ring
[r_idx
];
2001 tx_ring
->total_bytes
= 0;
2002 tx_ring
->total_packets
= 0;
2003 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
2007 /* EIAM disabled interrupts (on this vector) for us */
2008 napi_schedule(&q_vector
->napi
);
2014 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2016 * @data: pointer to our q_vector struct for this interrupt vector
2018 static irqreturn_t
ixgbe_msix_clean_rx(int irq
, void *data
)
2020 struct ixgbe_q_vector
*q_vector
= data
;
2021 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2022 struct ixgbe_ring
*rx_ring
;
2026 #ifdef CONFIG_IXGBE_DCA
2027 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
2028 ixgbe_update_dca(q_vector
);
2031 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
2032 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
2033 rx_ring
= adapter
->rx_ring
[r_idx
];
2034 rx_ring
->total_bytes
= 0;
2035 rx_ring
->total_packets
= 0;
2036 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
2040 if (!q_vector
->rxr_count
)
2043 /* EIAM disabled interrupts (on this vector) for us */
2044 napi_schedule(&q_vector
->napi
);
2049 static irqreturn_t
ixgbe_msix_clean_many(int irq
, void *data
)
2051 struct ixgbe_q_vector
*q_vector
= data
;
2052 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2053 struct ixgbe_ring
*ring
;
2057 if (!q_vector
->txr_count
&& !q_vector
->rxr_count
)
2060 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
2061 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
2062 ring
= adapter
->tx_ring
[r_idx
];
2063 ring
->total_bytes
= 0;
2064 ring
->total_packets
= 0;
2065 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
2069 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
2070 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
2071 ring
= adapter
->rx_ring
[r_idx
];
2072 ring
->total_bytes
= 0;
2073 ring
->total_packets
= 0;
2074 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
2078 /* EIAM disabled interrupts (on this vector) for us */
2079 napi_schedule(&q_vector
->napi
);
2085 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2086 * @napi: napi struct with our devices info in it
2087 * @budget: amount of work driver is allowed to do this pass, in packets
2089 * This function is optimized for cleaning one queue only on a single
2092 static int ixgbe_clean_rxonly(struct napi_struct
*napi
, int budget
)
2094 struct ixgbe_q_vector
*q_vector
=
2095 container_of(napi
, struct ixgbe_q_vector
, napi
);
2096 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2097 struct ixgbe_ring
*rx_ring
= NULL
;
2101 #ifdef CONFIG_IXGBE_DCA
2102 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
2103 ixgbe_update_dca(q_vector
);
2106 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
2107 rx_ring
= adapter
->rx_ring
[r_idx
];
2109 ixgbe_clean_rx_irq(q_vector
, rx_ring
, &work_done
, budget
);
2111 /* If all Rx work done, exit the polling mode */
2112 if (work_done
< budget
) {
2113 napi_complete(napi
);
2114 if (adapter
->rx_itr_setting
& 1)
2115 ixgbe_set_itr_msix(q_vector
);
2116 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2117 ixgbe_irq_enable_queues(adapter
,
2118 ((u64
)1 << q_vector
->v_idx
));
2125 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2126 * @napi: napi struct with our devices info in it
2127 * @budget: amount of work driver is allowed to do this pass, in packets
2129 * This function will clean more than one rx queue associated with a
2132 static int ixgbe_clean_rxtx_many(struct napi_struct
*napi
, int budget
)
2134 struct ixgbe_q_vector
*q_vector
=
2135 container_of(napi
, struct ixgbe_q_vector
, napi
);
2136 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2137 struct ixgbe_ring
*ring
= NULL
;
2138 int work_done
= 0, i
;
2140 bool tx_clean_complete
= true;
2142 #ifdef CONFIG_IXGBE_DCA
2143 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
2144 ixgbe_update_dca(q_vector
);
2147 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
2148 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
2149 ring
= adapter
->tx_ring
[r_idx
];
2150 tx_clean_complete
&= ixgbe_clean_tx_irq(q_vector
, ring
);
2151 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
2155 /* attempt to distribute budget to each queue fairly, but don't allow
2156 * the budget to go below 1 because we'll exit polling */
2157 budget
/= (q_vector
->rxr_count
?: 1);
2158 budget
= max(budget
, 1);
2159 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
2160 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
2161 ring
= adapter
->rx_ring
[r_idx
];
2162 ixgbe_clean_rx_irq(q_vector
, ring
, &work_done
, budget
);
2163 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
2167 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
2168 ring
= adapter
->rx_ring
[r_idx
];
2169 /* If all Rx work done, exit the polling mode */
2170 if (work_done
< budget
) {
2171 napi_complete(napi
);
2172 if (adapter
->rx_itr_setting
& 1)
2173 ixgbe_set_itr_msix(q_vector
);
2174 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2175 ixgbe_irq_enable_queues(adapter
,
2176 ((u64
)1 << q_vector
->v_idx
));
2184 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2185 * @napi: napi struct with our devices info in it
2186 * @budget: amount of work driver is allowed to do this pass, in packets
2188 * This function is optimized for cleaning one queue only on a single
2191 static int ixgbe_clean_txonly(struct napi_struct
*napi
, int budget
)
2193 struct ixgbe_q_vector
*q_vector
=
2194 container_of(napi
, struct ixgbe_q_vector
, napi
);
2195 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2196 struct ixgbe_ring
*tx_ring
= NULL
;
2200 #ifdef CONFIG_IXGBE_DCA
2201 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
2202 ixgbe_update_dca(q_vector
);
2205 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
2206 tx_ring
= adapter
->tx_ring
[r_idx
];
2208 if (!ixgbe_clean_tx_irq(q_vector
, tx_ring
))
2211 /* If all Tx work done, exit the polling mode */
2212 if (work_done
< budget
) {
2213 napi_complete(napi
);
2214 if (adapter
->tx_itr_setting
& 1)
2215 ixgbe_set_itr_msix(q_vector
);
2216 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2217 ixgbe_irq_enable_queues(adapter
,
2218 ((u64
)1 << q_vector
->v_idx
));
2224 static inline void map_vector_to_rxq(struct ixgbe_adapter
*a
, int v_idx
,
2227 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
2228 struct ixgbe_ring
*rx_ring
= a
->rx_ring
[r_idx
];
2230 set_bit(r_idx
, q_vector
->rxr_idx
);
2231 q_vector
->rxr_count
++;
2232 rx_ring
->q_vector
= q_vector
;
2235 static inline void map_vector_to_txq(struct ixgbe_adapter
*a
, int v_idx
,
2238 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
2239 struct ixgbe_ring
*tx_ring
= a
->tx_ring
[t_idx
];
2241 set_bit(t_idx
, q_vector
->txr_idx
);
2242 q_vector
->txr_count
++;
2243 tx_ring
->q_vector
= q_vector
;
2247 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2248 * @adapter: board private structure to initialize
2250 * This function maps descriptor rings to the queue-specific vectors
2251 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2252 * one vector per ring/queue, but on a constrained vector budget, we
2253 * group the rings as "efficiently" as possible. You would add new
2254 * mapping configurations in here.
2256 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter
*adapter
)
2260 int rxr_idx
= 0, txr_idx
= 0;
2261 int rxr_remaining
= adapter
->num_rx_queues
;
2262 int txr_remaining
= adapter
->num_tx_queues
;
2267 /* No mapping required if MSI-X is disabled. */
2268 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
2271 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2274 * The ideal configuration...
2275 * We have enough vectors to map one per queue.
2277 if (q_vectors
== adapter
->num_rx_queues
+ adapter
->num_tx_queues
) {
2278 for (; rxr_idx
< rxr_remaining
; v_start
++, rxr_idx
++)
2279 map_vector_to_rxq(adapter
, v_start
, rxr_idx
);
2281 for (; txr_idx
< txr_remaining
; v_start
++, txr_idx
++)
2282 map_vector_to_txq(adapter
, v_start
, txr_idx
);
2288 * If we don't have enough vectors for a 1-to-1
2289 * mapping, we'll have to group them so there are
2290 * multiple queues per vector.
2292 /* Re-adjusting *qpv takes care of the remainder. */
2293 for (i
= v_start
; i
< q_vectors
; i
++) {
2294 rqpv
= DIV_ROUND_UP(rxr_remaining
, q_vectors
- i
);
2295 for (j
= 0; j
< rqpv
; j
++) {
2296 map_vector_to_rxq(adapter
, i
, rxr_idx
);
2300 tqpv
= DIV_ROUND_UP(txr_remaining
, q_vectors
- i
);
2301 for (j
= 0; j
< tqpv
; j
++) {
2302 map_vector_to_txq(adapter
, i
, txr_idx
);
2312 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2313 * @adapter: board private structure
2315 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2316 * interrupts from the kernel.
2318 static int ixgbe_request_msix_irqs(struct ixgbe_adapter
*adapter
)
2320 struct net_device
*netdev
= adapter
->netdev
;
2321 irqreturn_t (*handler
)(int, void *);
2322 int i
, vector
, q_vectors
, err
;
2325 /* Decrement for Other and TCP Timer vectors */
2326 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2328 err
= ixgbe_map_rings_to_vectors(adapter
);
2332 #define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \
2333 ? &ixgbe_msix_clean_many : \
2334 (_v)->rxr_count ? &ixgbe_msix_clean_rx : \
2335 (_v)->txr_count ? &ixgbe_msix_clean_tx : \
2337 for (vector
= 0; vector
< q_vectors
; vector
++) {
2338 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[vector
];
2339 handler
= SET_HANDLER(q_vector
);
2341 if (handler
== &ixgbe_msix_clean_rx
) {
2342 snprintf(q_vector
->name
, sizeof(q_vector
->name
) - 1,
2343 "%s-%s-%d", netdev
->name
, "rx", ri
++);
2344 } else if (handler
== &ixgbe_msix_clean_tx
) {
2345 snprintf(q_vector
->name
, sizeof(q_vector
->name
) - 1,
2346 "%s-%s-%d", netdev
->name
, "tx", ti
++);
2347 } else if (handler
== &ixgbe_msix_clean_many
) {
2348 snprintf(q_vector
->name
, sizeof(q_vector
->name
) - 1,
2349 "%s-%s-%d", netdev
->name
, "TxRx", ri
++);
2352 /* skip this unused q_vector */
2355 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
2356 handler
, 0, q_vector
->name
,
2359 e_err(probe
, "request_irq failed for MSIX interrupt "
2360 "Error: %d\n", err
);
2361 goto free_queue_irqs
;
2365 sprintf(adapter
->lsc_int_name
, "%s:lsc", netdev
->name
);
2366 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
2367 ixgbe_msix_lsc
, 0, adapter
->lsc_int_name
, netdev
);
2369 e_err(probe
, "request_irq for msix_lsc failed: %d\n", err
);
2370 goto free_queue_irqs
;
2376 for (i
= vector
- 1; i
>= 0; i
--)
2377 free_irq(adapter
->msix_entries
[--vector
].vector
,
2378 adapter
->q_vector
[i
]);
2379 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
2380 pci_disable_msix(adapter
->pdev
);
2381 kfree(adapter
->msix_entries
);
2382 adapter
->msix_entries
= NULL
;
2386 static void ixgbe_set_itr(struct ixgbe_adapter
*adapter
)
2388 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
2389 struct ixgbe_ring
*rx_ring
= adapter
->rx_ring
[0];
2390 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[0];
2391 u32 new_itr
= q_vector
->eitr
;
2394 q_vector
->tx_itr
= ixgbe_update_itr(adapter
, new_itr
,
2396 tx_ring
->total_packets
,
2397 tx_ring
->total_bytes
);
2398 q_vector
->rx_itr
= ixgbe_update_itr(adapter
, new_itr
,
2400 rx_ring
->total_packets
,
2401 rx_ring
->total_bytes
);
2403 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
2405 switch (current_itr
) {
2406 /* counts and packets in update_itr are dependent on these numbers */
2407 case lowest_latency
:
2411 new_itr
= 20000; /* aka hwitr = ~200 */
2420 if (new_itr
!= q_vector
->eitr
) {
2421 /* do an exponential smoothing */
2422 new_itr
= ((q_vector
->eitr
* 9) + new_itr
)/10;
2424 /* save the algorithm value here */
2425 q_vector
->eitr
= new_itr
;
2427 ixgbe_write_eitr(q_vector
);
2432 * ixgbe_irq_enable - Enable default interrupt generation settings
2433 * @adapter: board private structure
2435 static inline void ixgbe_irq_enable(struct ixgbe_adapter
*adapter
, bool queues
,
2440 mask
= (IXGBE_EIMS_ENABLE_MASK
& ~IXGBE_EIMS_RTX_QUEUE
);
2441 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
)
2442 mask
|= IXGBE_EIMS_GPI_SDP0
;
2443 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
)
2444 mask
|= IXGBE_EIMS_GPI_SDP1
;
2445 switch (adapter
->hw
.mac
.type
) {
2446 case ixgbe_mac_82599EB
:
2447 case ixgbe_mac_X540
:
2448 mask
|= IXGBE_EIMS_ECC
;
2449 mask
|= IXGBE_EIMS_GPI_SDP1
;
2450 mask
|= IXGBE_EIMS_GPI_SDP2
;
2451 if (adapter
->num_vfs
)
2452 mask
|= IXGBE_EIMS_MAILBOX
;
2457 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
2458 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
2459 mask
|= IXGBE_EIMS_FLOW_DIR
;
2461 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
2463 ixgbe_irq_enable_queues(adapter
, ~0);
2465 IXGBE_WRITE_FLUSH(&adapter
->hw
);
2467 if (adapter
->num_vfs
> 32) {
2468 u32 eitrsel
= (1 << (adapter
->num_vfs
- 32)) - 1;
2469 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, eitrsel
);
2474 * ixgbe_intr - legacy mode Interrupt Handler
2475 * @irq: interrupt number
2476 * @data: pointer to a network interface device structure
2478 static irqreturn_t
ixgbe_intr(int irq
, void *data
)
2480 struct net_device
*netdev
= data
;
2481 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2482 struct ixgbe_hw
*hw
= &adapter
->hw
;
2483 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
2487 * Workaround for silicon errata on 82598. Mask the interrupts
2488 * before the read of EICR.
2490 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_IRQ_CLEAR_MASK
);
2492 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2493 * therefore no explict interrupt disable is necessary */
2494 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICR
);
2497 * shared interrupt alert!
2498 * make sure interrupts are enabled because the read will
2499 * have disabled interrupts due to EIAM
2500 * finish the workaround of silicon errata on 82598. Unmask
2501 * the interrupt that we masked before the EICR read.
2503 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2504 ixgbe_irq_enable(adapter
, true, true);
2505 return IRQ_NONE
; /* Not our interrupt */
2508 if (eicr
& IXGBE_EICR_LSC
)
2509 ixgbe_check_lsc(adapter
);
2511 switch (hw
->mac
.type
) {
2512 case ixgbe_mac_82599EB
:
2513 ixgbe_check_sfp_event(adapter
, eicr
);
2514 if ((adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) &&
2515 ((eicr
& IXGBE_EICR_GPI_SDP0
) || (eicr
& IXGBE_EICR_LSC
))) {
2516 adapter
->interrupt_event
= eicr
;
2517 schedule_work(&adapter
->check_overtemp_task
);
2524 ixgbe_check_fan_failure(adapter
, eicr
);
2526 if (napi_schedule_prep(&(q_vector
->napi
))) {
2527 adapter
->tx_ring
[0]->total_packets
= 0;
2528 adapter
->tx_ring
[0]->total_bytes
= 0;
2529 adapter
->rx_ring
[0]->total_packets
= 0;
2530 adapter
->rx_ring
[0]->total_bytes
= 0;
2531 /* would disable interrupts here but EIAM disabled it */
2532 __napi_schedule(&(q_vector
->napi
));
2536 * re-enable link(maybe) and non-queue interrupts, no flush.
2537 * ixgbe_poll will re-enable the queue interrupts
2540 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2541 ixgbe_irq_enable(adapter
, false, false);
2546 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter
*adapter
)
2548 int i
, q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2550 for (i
= 0; i
< q_vectors
; i
++) {
2551 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
2552 bitmap_zero(q_vector
->rxr_idx
, MAX_RX_QUEUES
);
2553 bitmap_zero(q_vector
->txr_idx
, MAX_TX_QUEUES
);
2554 q_vector
->rxr_count
= 0;
2555 q_vector
->txr_count
= 0;
2560 * ixgbe_request_irq - initialize interrupts
2561 * @adapter: board private structure
2563 * Attempts to configure interrupts using the best available
2564 * capabilities of the hardware and kernel.
2566 static int ixgbe_request_irq(struct ixgbe_adapter
*adapter
)
2568 struct net_device
*netdev
= adapter
->netdev
;
2571 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2572 err
= ixgbe_request_msix_irqs(adapter
);
2573 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
2574 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, 0,
2575 netdev
->name
, netdev
);
2577 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, IRQF_SHARED
,
2578 netdev
->name
, netdev
);
2582 e_err(probe
, "request_irq failed, Error %d\n", err
);
2587 static void ixgbe_free_irq(struct ixgbe_adapter
*adapter
)
2589 struct net_device
*netdev
= adapter
->netdev
;
2591 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2594 q_vectors
= adapter
->num_msix_vectors
;
2597 free_irq(adapter
->msix_entries
[i
].vector
, netdev
);
2600 for (; i
>= 0; i
--) {
2601 /* free only the irqs that were actually requested */
2602 if (!adapter
->q_vector
[i
]->rxr_count
&&
2603 !adapter
->q_vector
[i
]->txr_count
)
2606 free_irq(adapter
->msix_entries
[i
].vector
,
2607 adapter
->q_vector
[i
]);
2610 ixgbe_reset_q_vectors(adapter
);
2612 free_irq(adapter
->pdev
->irq
, netdev
);
2617 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2618 * @adapter: board private structure
2620 static inline void ixgbe_irq_disable(struct ixgbe_adapter
*adapter
)
2622 switch (adapter
->hw
.mac
.type
) {
2623 case ixgbe_mac_82598EB
:
2624 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, ~0);
2626 case ixgbe_mac_82599EB
:
2627 case ixgbe_mac_X540
:
2628 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, 0xFFFF0000);
2629 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), ~0);
2630 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1), ~0);
2631 if (adapter
->num_vfs
> 32)
2632 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, 0);
2637 IXGBE_WRITE_FLUSH(&adapter
->hw
);
2638 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2640 for (i
= 0; i
< adapter
->num_msix_vectors
; i
++)
2641 synchronize_irq(adapter
->msix_entries
[i
].vector
);
2643 synchronize_irq(adapter
->pdev
->irq
);
2648 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2651 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter
*adapter
)
2653 struct ixgbe_hw
*hw
= &adapter
->hw
;
2655 IXGBE_WRITE_REG(hw
, IXGBE_EITR(0),
2656 EITR_INTS_PER_SEC_TO_REG(adapter
->rx_eitr_param
));
2658 ixgbe_set_ivar(adapter
, 0, 0, 0);
2659 ixgbe_set_ivar(adapter
, 1, 0, 0);
2661 map_vector_to_rxq(adapter
, 0, 0);
2662 map_vector_to_txq(adapter
, 0, 0);
2664 e_info(hw
, "Legacy interrupt IVAR setup done\n");
2668 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2669 * @adapter: board private structure
2670 * @ring: structure containing ring specific data
2672 * Configure the Tx descriptor ring after a reset.
2674 void ixgbe_configure_tx_ring(struct ixgbe_adapter
*adapter
,
2675 struct ixgbe_ring
*ring
)
2677 struct ixgbe_hw
*hw
= &adapter
->hw
;
2678 u64 tdba
= ring
->dma
;
2681 u8 reg_idx
= ring
->reg_idx
;
2683 /* disable queue to avoid issues while updating state */
2684 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(reg_idx
));
2685 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(reg_idx
),
2686 txdctl
& ~IXGBE_TXDCTL_ENABLE
);
2687 IXGBE_WRITE_FLUSH(hw
);
2689 IXGBE_WRITE_REG(hw
, IXGBE_TDBAL(reg_idx
),
2690 (tdba
& DMA_BIT_MASK(32)));
2691 IXGBE_WRITE_REG(hw
, IXGBE_TDBAH(reg_idx
), (tdba
>> 32));
2692 IXGBE_WRITE_REG(hw
, IXGBE_TDLEN(reg_idx
),
2693 ring
->count
* sizeof(union ixgbe_adv_tx_desc
));
2694 IXGBE_WRITE_REG(hw
, IXGBE_TDH(reg_idx
), 0);
2695 IXGBE_WRITE_REG(hw
, IXGBE_TDT(reg_idx
), 0);
2696 ring
->tail
= hw
->hw_addr
+ IXGBE_TDT(reg_idx
);
2698 /* configure fetching thresholds */
2699 if (adapter
->rx_itr_setting
== 0) {
2700 /* cannot set wthresh when itr==0 */
2701 txdctl
&= ~0x007F0000;
2703 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2704 txdctl
|= (8 << 16);
2706 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
2707 /* PThresh workaround for Tx hang with DFP enabled. */
2711 /* reinitialize flowdirector state */
2712 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) &&
2713 adapter
->atr_sample_rate
) {
2714 ring
->atr_sample_rate
= adapter
->atr_sample_rate
;
2715 ring
->atr_count
= 0;
2716 set_bit(__IXGBE_TX_FDIR_INIT_DONE
, &ring
->state
);
2718 ring
->atr_sample_rate
= 0;
2721 clear_bit(__IXGBE_HANG_CHECK_ARMED
, &ring
->state
);
2724 txdctl
|= IXGBE_TXDCTL_ENABLE
;
2725 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(reg_idx
), txdctl
);
2727 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2728 if (hw
->mac
.type
== ixgbe_mac_82598EB
&&
2729 !(IXGBE_READ_REG(hw
, IXGBE_LINKS
) & IXGBE_LINKS_UP
))
2732 /* poll to verify queue is enabled */
2735 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(reg_idx
));
2736 } while (--wait_loop
&& !(txdctl
& IXGBE_TXDCTL_ENABLE
));
2738 e_err(drv
, "Could not enable Tx Queue %d\n", reg_idx
);
2741 static void ixgbe_setup_mtqc(struct ixgbe_adapter
*adapter
)
2743 struct ixgbe_hw
*hw
= &adapter
->hw
;
2747 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2750 /* disable the arbiter while setting MTQC */
2751 rttdcs
= IXGBE_READ_REG(hw
, IXGBE_RTTDCS
);
2752 rttdcs
|= IXGBE_RTTDCS_ARBDIS
;
2753 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2755 /* set transmit pool layout */
2756 mask
= (IXGBE_FLAG_SRIOV_ENABLED
| IXGBE_FLAG_DCB_ENABLED
);
2757 switch (adapter
->flags
& mask
) {
2759 case (IXGBE_FLAG_SRIOV_ENABLED
):
2760 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
,
2761 (IXGBE_MTQC_VT_ENA
| IXGBE_MTQC_64VF
));
2764 case (IXGBE_FLAG_DCB_ENABLED
):
2765 /* We enable 8 traffic classes, DCB only */
2766 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
,
2767 (IXGBE_MTQC_RT_ENA
| IXGBE_MTQC_8TC_8TQ
));
2771 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
, IXGBE_MTQC_64Q_1PB
);
2775 /* re-enable the arbiter */
2776 rttdcs
&= ~IXGBE_RTTDCS_ARBDIS
;
2777 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2781 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2782 * @adapter: board private structure
2784 * Configure the Tx unit of the MAC after a reset.
2786 static void ixgbe_configure_tx(struct ixgbe_adapter
*adapter
)
2788 struct ixgbe_hw
*hw
= &adapter
->hw
;
2792 ixgbe_setup_mtqc(adapter
);
2794 if (hw
->mac
.type
!= ixgbe_mac_82598EB
) {
2795 /* DMATXCTL.EN must be before Tx queues are enabled */
2796 dmatxctl
= IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
);
2797 dmatxctl
|= IXGBE_DMATXCTL_TE
;
2798 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
, dmatxctl
);
2801 /* Setup the HW Tx Head and Tail descriptor pointers */
2802 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
2803 ixgbe_configure_tx_ring(adapter
, adapter
->tx_ring
[i
]);
2806 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2808 static void ixgbe_configure_srrctl(struct ixgbe_adapter
*adapter
,
2809 struct ixgbe_ring
*rx_ring
)
2812 u8 reg_idx
= rx_ring
->reg_idx
;
2814 switch (adapter
->hw
.mac
.type
) {
2815 case ixgbe_mac_82598EB
: {
2816 struct ixgbe_ring_feature
*feature
= adapter
->ring_feature
;
2817 const int mask
= feature
[RING_F_RSS
].mask
;
2818 reg_idx
= reg_idx
& mask
;
2821 case ixgbe_mac_82599EB
:
2822 case ixgbe_mac_X540
:
2827 srrctl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_SRRCTL(reg_idx
));
2829 srrctl
&= ~IXGBE_SRRCTL_BSIZEHDR_MASK
;
2830 srrctl
&= ~IXGBE_SRRCTL_BSIZEPKT_MASK
;
2831 if (adapter
->num_vfs
)
2832 srrctl
|= IXGBE_SRRCTL_DROP_EN
;
2834 srrctl
|= (IXGBE_RX_HDR_SIZE
<< IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT
) &
2835 IXGBE_SRRCTL_BSIZEHDR_MASK
;
2837 if (ring_is_ps_enabled(rx_ring
)) {
2838 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2839 srrctl
|= IXGBE_MAX_RXBUFFER
>> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2841 srrctl
|= (PAGE_SIZE
/ 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2843 srrctl
|= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS
;
2845 srrctl
|= ALIGN(rx_ring
->rx_buf_len
, 1024) >>
2846 IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2847 srrctl
|= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF
;
2850 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_SRRCTL(reg_idx
), srrctl
);
2853 static void ixgbe_setup_mrqc(struct ixgbe_adapter
*adapter
)
2855 struct ixgbe_hw
*hw
= &adapter
->hw
;
2856 static const u32 seed
[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2857 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2858 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2859 u32 mrqc
= 0, reta
= 0;
2864 /* Fill out hash function seeds */
2865 for (i
= 0; i
< 10; i
++)
2866 IXGBE_WRITE_REG(hw
, IXGBE_RSSRK(i
), seed
[i
]);
2868 /* Fill out redirection table */
2869 for (i
= 0, j
= 0; i
< 128; i
++, j
++) {
2870 if (j
== adapter
->ring_feature
[RING_F_RSS
].indices
)
2872 /* reta = 4-byte sliding window of
2873 * 0x00..(indices-1)(indices-1)00..etc. */
2874 reta
= (reta
<< 8) | (j
* 0x11);
2876 IXGBE_WRITE_REG(hw
, IXGBE_RETA(i
>> 2), reta
);
2879 /* Disable indicating checksum in descriptor, enables RSS hash */
2880 rxcsum
= IXGBE_READ_REG(hw
, IXGBE_RXCSUM
);
2881 rxcsum
|= IXGBE_RXCSUM_PCSD
;
2882 IXGBE_WRITE_REG(hw
, IXGBE_RXCSUM
, rxcsum
);
2884 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
2885 mask
= adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
;
2887 mask
= adapter
->flags
& (IXGBE_FLAG_RSS_ENABLED
2888 #ifdef CONFIG_IXGBE_DCB
2889 | IXGBE_FLAG_DCB_ENABLED
2891 | IXGBE_FLAG_SRIOV_ENABLED
2895 case (IXGBE_FLAG_RSS_ENABLED
):
2896 mrqc
= IXGBE_MRQC_RSSEN
;
2898 case (IXGBE_FLAG_SRIOV_ENABLED
):
2899 mrqc
= IXGBE_MRQC_VMDQEN
;
2901 #ifdef CONFIG_IXGBE_DCB
2902 case (IXGBE_FLAG_DCB_ENABLED
):
2903 mrqc
= IXGBE_MRQC_RT8TCEN
;
2905 #endif /* CONFIG_IXGBE_DCB */
2910 /* Perform hash on these packet types */
2911 mrqc
|= IXGBE_MRQC_RSS_FIELD_IPV4
2912 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2913 | IXGBE_MRQC_RSS_FIELD_IPV6
2914 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
;
2916 IXGBE_WRITE_REG(hw
, IXGBE_MRQC
, mrqc
);
2920 * ixgbe_clear_rscctl - disable RSC for the indicated ring
2921 * @adapter: address of board private structure
2922 * @ring: structure containing ring specific data
2924 void ixgbe_clear_rscctl(struct ixgbe_adapter
*adapter
,
2925 struct ixgbe_ring
*ring
)
2927 struct ixgbe_hw
*hw
= &adapter
->hw
;
2929 u8 reg_idx
= ring
->reg_idx
;
2931 rscctrl
= IXGBE_READ_REG(hw
, IXGBE_RSCCTL(reg_idx
));
2932 rscctrl
&= ~IXGBE_RSCCTL_RSCEN
;
2933 IXGBE_WRITE_REG(hw
, IXGBE_RSCCTL(reg_idx
), rscctrl
);
2937 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2938 * @adapter: address of board private structure
2939 * @index: index of ring to set
2941 void ixgbe_configure_rscctl(struct ixgbe_adapter
*adapter
,
2942 struct ixgbe_ring
*ring
)
2944 struct ixgbe_hw
*hw
= &adapter
->hw
;
2947 u8 reg_idx
= ring
->reg_idx
;
2949 if (!ring_is_rsc_enabled(ring
))
2952 rx_buf_len
= ring
->rx_buf_len
;
2953 rscctrl
= IXGBE_READ_REG(hw
, IXGBE_RSCCTL(reg_idx
));
2954 rscctrl
|= IXGBE_RSCCTL_RSCEN
;
2956 * we must limit the number of descriptors so that the
2957 * total size of max desc * buf_len is not greater
2960 if (ring_is_ps_enabled(ring
)) {
2961 #if (MAX_SKB_FRAGS > 16)
2962 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2963 #elif (MAX_SKB_FRAGS > 8)
2964 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2965 #elif (MAX_SKB_FRAGS > 4)
2966 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2968 rscctrl
|= IXGBE_RSCCTL_MAXDESC_1
;
2971 if (rx_buf_len
< IXGBE_RXBUFFER_4096
)
2972 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2973 else if (rx_buf_len
< IXGBE_RXBUFFER_8192
)
2974 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2976 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2978 IXGBE_WRITE_REG(hw
, IXGBE_RSCCTL(reg_idx
), rscctrl
);
2982 * ixgbe_set_uta - Set unicast filter table address
2983 * @adapter: board private structure
2985 * The unicast table address is a register array of 32-bit registers.
2986 * The table is meant to be used in a way similar to how the MTA is used
2987 * however due to certain limitations in the hardware it is necessary to
2988 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2989 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2991 static void ixgbe_set_uta(struct ixgbe_adapter
*adapter
)
2993 struct ixgbe_hw
*hw
= &adapter
->hw
;
2996 /* The UTA table only exists on 82599 hardware and newer */
2997 if (hw
->mac
.type
< ixgbe_mac_82599EB
)
3000 /* we only need to do this if VMDq is enabled */
3001 if (!(adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
))
3004 for (i
= 0; i
< 128; i
++)
3005 IXGBE_WRITE_REG(hw
, IXGBE_UTA(i
), ~0);
3008 #define IXGBE_MAX_RX_DESC_POLL 10
3009 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter
*adapter
,
3010 struct ixgbe_ring
*ring
)
3012 struct ixgbe_hw
*hw
= &adapter
->hw
;
3013 int wait_loop
= IXGBE_MAX_RX_DESC_POLL
;
3015 u8 reg_idx
= ring
->reg_idx
;
3017 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3018 if (hw
->mac
.type
== ixgbe_mac_82598EB
&&
3019 !(IXGBE_READ_REG(hw
, IXGBE_LINKS
) & IXGBE_LINKS_UP
))
3024 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
3025 } while (--wait_loop
&& !(rxdctl
& IXGBE_RXDCTL_ENABLE
));
3028 e_err(drv
, "RXDCTL.ENABLE on Rx queue %d not set within "
3029 "the polling period\n", reg_idx
);
3033 void ixgbe_disable_rx_queue(struct ixgbe_adapter
*adapter
,
3034 struct ixgbe_ring
*ring
)
3036 struct ixgbe_hw
*hw
= &adapter
->hw
;
3037 int wait_loop
= IXGBE_MAX_RX_DESC_POLL
;
3039 u8 reg_idx
= ring
->reg_idx
;
3041 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
3042 rxdctl
&= ~IXGBE_RXDCTL_ENABLE
;
3044 /* write value back with RXDCTL.ENABLE bit cleared */
3045 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(reg_idx
), rxdctl
);
3047 if (hw
->mac
.type
== ixgbe_mac_82598EB
&&
3048 !(IXGBE_READ_REG(hw
, IXGBE_LINKS
) & IXGBE_LINKS_UP
))
3051 /* the hardware may take up to 100us to really disable the rx queue */
3054 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
3055 } while (--wait_loop
&& (rxdctl
& IXGBE_RXDCTL_ENABLE
));
3058 e_err(drv
, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3059 "the polling period\n", reg_idx
);
3063 void ixgbe_configure_rx_ring(struct ixgbe_adapter
*adapter
,
3064 struct ixgbe_ring
*ring
)
3066 struct ixgbe_hw
*hw
= &adapter
->hw
;
3067 u64 rdba
= ring
->dma
;
3069 u8 reg_idx
= ring
->reg_idx
;
3071 /* disable queue to avoid issues while updating state */
3072 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
3073 ixgbe_disable_rx_queue(adapter
, ring
);
3075 IXGBE_WRITE_REG(hw
, IXGBE_RDBAL(reg_idx
), (rdba
& DMA_BIT_MASK(32)));
3076 IXGBE_WRITE_REG(hw
, IXGBE_RDBAH(reg_idx
), (rdba
>> 32));
3077 IXGBE_WRITE_REG(hw
, IXGBE_RDLEN(reg_idx
),
3078 ring
->count
* sizeof(union ixgbe_adv_rx_desc
));
3079 IXGBE_WRITE_REG(hw
, IXGBE_RDH(reg_idx
), 0);
3080 IXGBE_WRITE_REG(hw
, IXGBE_RDT(reg_idx
), 0);
3081 ring
->tail
= hw
->hw_addr
+ IXGBE_RDT(reg_idx
);
3083 ixgbe_configure_srrctl(adapter
, ring
);
3084 ixgbe_configure_rscctl(adapter
, ring
);
3086 /* If operating in IOV mode set RLPML for X540 */
3087 if ((adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) &&
3088 hw
->mac
.type
== ixgbe_mac_X540
) {
3089 rxdctl
&= ~IXGBE_RXDCTL_RLPMLMASK
;
3090 rxdctl
|= ((ring
->netdev
->mtu
+ ETH_HLEN
+
3091 ETH_FCS_LEN
+ VLAN_HLEN
) | IXGBE_RXDCTL_RLPML_EN
);
3094 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
3096 * enable cache line friendly hardware writes:
3097 * PTHRESH=32 descriptors (half the internal cache),
3098 * this also removes ugly rx_no_buffer_count increment
3099 * HTHRESH=4 descriptors (to minimize latency on fetch)
3100 * WTHRESH=8 burst writeback up to two cache lines
3102 rxdctl
&= ~0x3FFFFF;
3106 /* enable receive descriptor ring */
3107 rxdctl
|= IXGBE_RXDCTL_ENABLE
;
3108 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(reg_idx
), rxdctl
);
3110 ixgbe_rx_desc_queue_enable(adapter
, ring
);
3111 ixgbe_alloc_rx_buffers(ring
, IXGBE_DESC_UNUSED(ring
));
3114 static void ixgbe_setup_psrtype(struct ixgbe_adapter
*adapter
)
3116 struct ixgbe_hw
*hw
= &adapter
->hw
;
3119 /* PSRTYPE must be initialized in non 82598 adapters */
3120 u32 psrtype
= IXGBE_PSRTYPE_TCPHDR
|
3121 IXGBE_PSRTYPE_UDPHDR
|
3122 IXGBE_PSRTYPE_IPV4HDR
|
3123 IXGBE_PSRTYPE_L2HDR
|
3124 IXGBE_PSRTYPE_IPV6HDR
;
3126 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3129 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
)
3130 psrtype
|= (adapter
->num_rx_queues_per_pool
<< 29);
3132 for (p
= 0; p
< adapter
->num_rx_pools
; p
++)
3133 IXGBE_WRITE_REG(hw
, IXGBE_PSRTYPE(adapter
->num_vfs
+ p
),
3137 static void ixgbe_configure_virtualization(struct ixgbe_adapter
*adapter
)
3139 struct ixgbe_hw
*hw
= &adapter
->hw
;
3142 u32 reg_offset
, vf_shift
;
3145 if (!(adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
))
3148 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
3149 vt_reg_bits
= IXGBE_VMD_CTL_VMDQ_EN
| IXGBE_VT_CTL_REPLEN
;
3150 vt_reg_bits
|= (adapter
->num_vfs
<< IXGBE_VT_CTL_POOL_SHIFT
);
3151 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
| vt_reg_bits
);
3153 vf_shift
= adapter
->num_vfs
% 32;
3154 reg_offset
= (adapter
->num_vfs
> 32) ? 1 : 0;
3156 /* Enable only the PF's pool for Tx/Rx */
3157 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(reg_offset
), (1 << vf_shift
));
3158 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(reg_offset
^ 1), 0);
3159 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(reg_offset
), (1 << vf_shift
));
3160 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(reg_offset
^ 1), 0);
3161 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, IXGBE_PFDTXGSWC_VT_LBEN
);
3163 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3164 hw
->mac
.ops
.set_vmdq(hw
, 0, adapter
->num_vfs
);
3167 * Set up VF register offsets for selected VT Mode,
3168 * i.e. 32 or 64 VFs for SR-IOV
3170 gcr_ext
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
3171 gcr_ext
|= IXGBE_GCR_EXT_MSIX_EN
;
3172 gcr_ext
|= IXGBE_GCR_EXT_VT_MODE_64
;
3173 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, gcr_ext
);
3175 /* enable Tx loopback for VF/PF communication */
3176 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, IXGBE_PFDTXGSWC_VT_LBEN
);
3177 /* Enable MAC Anti-Spoofing */
3178 hw
->mac
.ops
.set_mac_anti_spoofing(hw
, (adapter
->num_vfs
!= 0),
3182 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter
*adapter
)
3184 struct ixgbe_hw
*hw
= &adapter
->hw
;
3185 struct net_device
*netdev
= adapter
->netdev
;
3186 int max_frame
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
3188 struct ixgbe_ring
*rx_ring
;
3192 /* Decide whether to use packet split mode or not */
3194 adapter
->flags
|= IXGBE_FLAG_RX_PS_ENABLED
;
3196 /* Do not use packet split if we're in SR-IOV Mode */
3197 if (adapter
->num_vfs
)
3198 adapter
->flags
&= ~IXGBE_FLAG_RX_PS_ENABLED
;
3200 /* Disable packet split due to 82599 erratum #45 */
3201 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
3202 adapter
->flags
&= ~IXGBE_FLAG_RX_PS_ENABLED
;
3204 /* Set the RX buffer length according to the mode */
3205 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
) {
3206 rx_buf_len
= IXGBE_RX_HDR_SIZE
;
3208 if (!(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) &&
3209 (netdev
->mtu
<= ETH_DATA_LEN
))
3210 rx_buf_len
= MAXIMUM_ETHERNET_VLAN_SIZE
;
3212 rx_buf_len
= ALIGN(max_frame
+ VLAN_HLEN
, 1024);
3216 /* adjust max frame to be able to do baby jumbo for FCoE */
3217 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) &&
3218 (max_frame
< IXGBE_FCOE_JUMBO_FRAME_SIZE
))
3219 max_frame
= IXGBE_FCOE_JUMBO_FRAME_SIZE
;
3221 #endif /* IXGBE_FCOE */
3222 mhadd
= IXGBE_READ_REG(hw
, IXGBE_MHADD
);
3223 if (max_frame
!= (mhadd
>> IXGBE_MHADD_MFS_SHIFT
)) {
3224 mhadd
&= ~IXGBE_MHADD_MFS_MASK
;
3225 mhadd
|= max_frame
<< IXGBE_MHADD_MFS_SHIFT
;
3227 IXGBE_WRITE_REG(hw
, IXGBE_MHADD
, mhadd
);
3230 hlreg0
= IXGBE_READ_REG(hw
, IXGBE_HLREG0
);
3231 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3232 hlreg0
|= IXGBE_HLREG0_JUMBOEN
;
3233 IXGBE_WRITE_REG(hw
, IXGBE_HLREG0
, hlreg0
);
3236 * Setup the HW Rx Head and Tail Descriptor Pointers and
3237 * the Base and Length of the Rx Descriptor Ring
3239 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3240 rx_ring
= adapter
->rx_ring
[i
];
3241 rx_ring
->rx_buf_len
= rx_buf_len
;
3243 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
)
3244 set_ring_ps_enabled(rx_ring
);
3246 clear_ring_ps_enabled(rx_ring
);
3248 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
)
3249 set_ring_rsc_enabled(rx_ring
);
3251 clear_ring_rsc_enabled(rx_ring
);
3254 if (netdev
->features
& NETIF_F_FCOE_MTU
) {
3255 struct ixgbe_ring_feature
*f
;
3256 f
= &adapter
->ring_feature
[RING_F_FCOE
];
3257 if ((i
>= f
->mask
) && (i
< f
->mask
+ f
->indices
)) {
3258 clear_ring_ps_enabled(rx_ring
);
3259 if (rx_buf_len
< IXGBE_FCOE_JUMBO_FRAME_SIZE
)
3260 rx_ring
->rx_buf_len
=
3261 IXGBE_FCOE_JUMBO_FRAME_SIZE
;
3262 } else if (!ring_is_rsc_enabled(rx_ring
) &&
3263 !ring_is_ps_enabled(rx_ring
)) {
3264 rx_ring
->rx_buf_len
=
3265 IXGBE_FCOE_JUMBO_FRAME_SIZE
;
3268 #endif /* IXGBE_FCOE */
3272 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter
*adapter
)
3274 struct ixgbe_hw
*hw
= &adapter
->hw
;
3275 u32 rdrxctl
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
3277 switch (hw
->mac
.type
) {
3278 case ixgbe_mac_82598EB
:
3280 * For VMDq support of different descriptor types or
3281 * buffer sizes through the use of multiple SRRCTL
3282 * registers, RDRXCTL.MVMEN must be set to 1
3284 * also, the manual doesn't mention it clearly but DCA hints
3285 * will only use queue 0's tags unless this bit is set. Side
3286 * effects of setting this bit are only that SRRCTL must be
3287 * fully programmed [0..15]
3289 rdrxctl
|= IXGBE_RDRXCTL_MVMEN
;
3291 case ixgbe_mac_82599EB
:
3292 case ixgbe_mac_X540
:
3293 /* Disable RSC for ACK packets */
3294 IXGBE_WRITE_REG(hw
, IXGBE_RSCDBU
,
3295 (IXGBE_RSCDBU_RSCACKDIS
| IXGBE_READ_REG(hw
, IXGBE_RSCDBU
)));
3296 rdrxctl
&= ~IXGBE_RDRXCTL_RSCFRSTSIZE
;
3297 /* hardware requires some bits to be set by default */
3298 rdrxctl
|= (IXGBE_RDRXCTL_RSCACKC
| IXGBE_RDRXCTL_FCOE_WRFIX
);
3299 rdrxctl
|= IXGBE_RDRXCTL_CRCSTRIP
;
3302 /* We should do nothing since we don't know this hardware */
3306 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, rdrxctl
);
3310 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3311 * @adapter: board private structure
3313 * Configure the Rx unit of the MAC after a reset.
3315 static void ixgbe_configure_rx(struct ixgbe_adapter
*adapter
)
3317 struct ixgbe_hw
*hw
= &adapter
->hw
;
3321 /* disable receives while setting up the descriptors */
3322 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
3323 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
3325 ixgbe_setup_psrtype(adapter
);
3326 ixgbe_setup_rdrxctl(adapter
);
3328 /* Program registers for the distribution of queues */
3329 ixgbe_setup_mrqc(adapter
);
3331 ixgbe_set_uta(adapter
);
3333 /* set_rx_buffer_len must be called before ring initialization */
3334 ixgbe_set_rx_buffer_len(adapter
);
3337 * Setup the HW Rx Head and Tail Descriptor Pointers and
3338 * the Base and Length of the Rx Descriptor Ring
3340 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3341 ixgbe_configure_rx_ring(adapter
, adapter
->rx_ring
[i
]);
3343 /* disable drop enable for 82598 parts */
3344 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3345 rxctrl
|= IXGBE_RXCTRL_DMBYPS
;
3347 /* enable all receives */
3348 rxctrl
|= IXGBE_RXCTRL_RXEN
;
3349 hw
->mac
.ops
.enable_rx_dma(hw
, rxctrl
);
3352 static void ixgbe_vlan_rx_add_vid(struct net_device
*netdev
, u16 vid
)
3354 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3355 struct ixgbe_hw
*hw
= &adapter
->hw
;
3356 int pool_ndx
= adapter
->num_vfs
;
3358 /* add VID to filter table */
3359 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, true);
3360 set_bit(vid
, adapter
->active_vlans
);
3363 static void ixgbe_vlan_rx_kill_vid(struct net_device
*netdev
, u16 vid
)
3365 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3366 struct ixgbe_hw
*hw
= &adapter
->hw
;
3367 int pool_ndx
= adapter
->num_vfs
;
3369 /* remove VID from filter table */
3370 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, false);
3371 clear_bit(vid
, adapter
->active_vlans
);
3375 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3376 * @adapter: driver data
3378 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter
*adapter
)
3380 struct ixgbe_hw
*hw
= &adapter
->hw
;
3383 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3384 vlnctrl
&= ~(IXGBE_VLNCTRL_VFE
| IXGBE_VLNCTRL_CFIEN
);
3385 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3389 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3390 * @adapter: driver data
3392 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter
*adapter
)
3394 struct ixgbe_hw
*hw
= &adapter
->hw
;
3397 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3398 vlnctrl
|= IXGBE_VLNCTRL_VFE
;
3399 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
3400 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3404 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3405 * @adapter: driver data
3407 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter
*adapter
)
3409 struct ixgbe_hw
*hw
= &adapter
->hw
;
3413 switch (hw
->mac
.type
) {
3414 case ixgbe_mac_82598EB
:
3415 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3416 vlnctrl
&= ~IXGBE_VLNCTRL_VME
;
3417 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3419 case ixgbe_mac_82599EB
:
3420 case ixgbe_mac_X540
:
3421 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3422 j
= adapter
->rx_ring
[i
]->reg_idx
;
3423 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
3424 vlnctrl
&= ~IXGBE_RXDCTL_VME
;
3425 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
3434 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3435 * @adapter: driver data
3437 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter
*adapter
)
3439 struct ixgbe_hw
*hw
= &adapter
->hw
;
3443 switch (hw
->mac
.type
) {
3444 case ixgbe_mac_82598EB
:
3445 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3446 vlnctrl
|= IXGBE_VLNCTRL_VME
;
3447 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3449 case ixgbe_mac_82599EB
:
3450 case ixgbe_mac_X540
:
3451 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3452 j
= adapter
->rx_ring
[i
]->reg_idx
;
3453 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
3454 vlnctrl
|= IXGBE_RXDCTL_VME
;
3455 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
3463 static void ixgbe_restore_vlan(struct ixgbe_adapter
*adapter
)
3467 ixgbe_vlan_rx_add_vid(adapter
->netdev
, 0);
3469 for_each_set_bit(vid
, adapter
->active_vlans
, VLAN_N_VID
)
3470 ixgbe_vlan_rx_add_vid(adapter
->netdev
, vid
);
3474 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3475 * @netdev: network interface device structure
3477 * Writes unicast address list to the RAR table.
3478 * Returns: -ENOMEM on failure/insufficient address space
3479 * 0 on no addresses written
3480 * X on writing X addresses to the RAR table
3482 static int ixgbe_write_uc_addr_list(struct net_device
*netdev
)
3484 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3485 struct ixgbe_hw
*hw
= &adapter
->hw
;
3486 unsigned int vfn
= adapter
->num_vfs
;
3487 unsigned int rar_entries
= hw
->mac
.num_rar_entries
- (vfn
+ 1);
3490 /* return ENOMEM indicating insufficient memory for addresses */
3491 if (netdev_uc_count(netdev
) > rar_entries
)
3494 if (!netdev_uc_empty(netdev
) && rar_entries
) {
3495 struct netdev_hw_addr
*ha
;
3496 /* return error if we do not support writing to RAR table */
3497 if (!hw
->mac
.ops
.set_rar
)
3500 netdev_for_each_uc_addr(ha
, netdev
) {
3503 hw
->mac
.ops
.set_rar(hw
, rar_entries
--, ha
->addr
,
3508 /* write the addresses in reverse order to avoid write combining */
3509 for (; rar_entries
> 0 ; rar_entries
--)
3510 hw
->mac
.ops
.clear_rar(hw
, rar_entries
);
3516 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3517 * @netdev: network interface device structure
3519 * The set_rx_method entry point is called whenever the unicast/multicast
3520 * address list or the network interface flags are updated. This routine is
3521 * responsible for configuring the hardware for proper unicast, multicast and
3524 void ixgbe_set_rx_mode(struct net_device
*netdev
)
3526 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3527 struct ixgbe_hw
*hw
= &adapter
->hw
;
3528 u32 fctrl
, vmolr
= IXGBE_VMOLR_BAM
| IXGBE_VMOLR_AUPE
;
3531 /* Check for Promiscuous and All Multicast modes */
3533 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
3535 /* set all bits that we expect to always be set */
3536 fctrl
|= IXGBE_FCTRL_BAM
;
3537 fctrl
|= IXGBE_FCTRL_DPF
; /* discard pause frames when FC enabled */
3538 fctrl
|= IXGBE_FCTRL_PMCF
;
3540 /* clear the bits we are changing the status of */
3541 fctrl
&= ~(IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
3543 if (netdev
->flags
& IFF_PROMISC
) {
3544 hw
->addr_ctrl
.user_set_promisc
= true;
3545 fctrl
|= (IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
3546 vmolr
|= (IXGBE_VMOLR_ROPE
| IXGBE_VMOLR_MPE
);
3547 /* don't hardware filter vlans in promisc mode */
3548 ixgbe_vlan_filter_disable(adapter
);
3550 if (netdev
->flags
& IFF_ALLMULTI
) {
3551 fctrl
|= IXGBE_FCTRL_MPE
;
3552 vmolr
|= IXGBE_VMOLR_MPE
;
3555 * Write addresses to the MTA, if the attempt fails
3556 * then we should just turn on promiscous mode so
3557 * that we can at least receive multicast traffic
3559 hw
->mac
.ops
.update_mc_addr_list(hw
, netdev
);
3560 vmolr
|= IXGBE_VMOLR_ROMPE
;
3562 ixgbe_vlan_filter_enable(adapter
);
3563 hw
->addr_ctrl
.user_set_promisc
= false;
3565 * Write addresses to available RAR registers, if there is not
3566 * sufficient space to store all the addresses then enable
3567 * unicast promiscous mode
3569 count
= ixgbe_write_uc_addr_list(netdev
);
3571 fctrl
|= IXGBE_FCTRL_UPE
;
3572 vmolr
|= IXGBE_VMOLR_ROPE
;
3576 if (adapter
->num_vfs
) {
3577 ixgbe_restore_vf_multicasts(adapter
);
3578 vmolr
|= IXGBE_READ_REG(hw
, IXGBE_VMOLR(adapter
->num_vfs
)) &
3579 ~(IXGBE_VMOLR_MPE
| IXGBE_VMOLR_ROMPE
|
3581 IXGBE_WRITE_REG(hw
, IXGBE_VMOLR(adapter
->num_vfs
), vmolr
);
3584 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
3586 if (netdev
->features
& NETIF_F_HW_VLAN_RX
)
3587 ixgbe_vlan_strip_enable(adapter
);
3589 ixgbe_vlan_strip_disable(adapter
);
3592 static void ixgbe_napi_enable_all(struct ixgbe_adapter
*adapter
)
3595 struct ixgbe_q_vector
*q_vector
;
3596 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3598 /* legacy and MSI only use one vector */
3599 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
3602 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
3603 struct napi_struct
*napi
;
3604 q_vector
= adapter
->q_vector
[q_idx
];
3605 napi
= &q_vector
->napi
;
3606 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3607 if (!q_vector
->rxr_count
|| !q_vector
->txr_count
) {
3608 if (q_vector
->txr_count
== 1)
3609 napi
->poll
= &ixgbe_clean_txonly
;
3610 else if (q_vector
->rxr_count
== 1)
3611 napi
->poll
= &ixgbe_clean_rxonly
;
3619 static void ixgbe_napi_disable_all(struct ixgbe_adapter
*adapter
)
3622 struct ixgbe_q_vector
*q_vector
;
3623 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3625 /* legacy and MSI only use one vector */
3626 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
3629 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
3630 q_vector
= adapter
->q_vector
[q_idx
];
3631 napi_disable(&q_vector
->napi
);
3635 #ifdef CONFIG_IXGBE_DCB
3637 * ixgbe_configure_dcb - Configure DCB hardware
3638 * @adapter: ixgbe adapter struct
3640 * This is called by the driver on open to configure the DCB hardware.
3641 * This is also called by the gennetlink interface when reconfiguring
3644 static void ixgbe_configure_dcb(struct ixgbe_adapter
*adapter
)
3646 struct ixgbe_hw
*hw
= &adapter
->hw
;
3647 int max_frame
= adapter
->netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
3649 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)) {
3650 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3651 netif_set_gso_max_size(adapter
->netdev
, 65536);
3655 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3656 netif_set_gso_max_size(adapter
->netdev
, 32768);
3659 if (adapter
->netdev
->features
& NETIF_F_FCOE_MTU
)
3660 max_frame
= max(max_frame
, IXGBE_FCOE_JUMBO_FRAME_SIZE
);
3663 ixgbe_dcb_calculate_tc_credits(hw
, &adapter
->dcb_cfg
, max_frame
,
3665 ixgbe_dcb_calculate_tc_credits(hw
, &adapter
->dcb_cfg
, max_frame
,
3668 /* Enable VLAN tag insert/strip */
3669 adapter
->netdev
->features
|= NETIF_F_HW_VLAN_RX
;
3671 hw
->mac
.ops
.set_vfta(&adapter
->hw
, 0, 0, true);
3673 /* reconfigure the hardware */
3674 ixgbe_dcb_hw_config(hw
, &adapter
->dcb_cfg
);
3678 static void ixgbe_configure(struct ixgbe_adapter
*adapter
)
3680 struct net_device
*netdev
= adapter
->netdev
;
3681 struct ixgbe_hw
*hw
= &adapter
->hw
;
3684 #ifdef CONFIG_IXGBE_DCB
3685 ixgbe_configure_dcb(adapter
);
3688 ixgbe_set_rx_mode(netdev
);
3689 ixgbe_restore_vlan(adapter
);
3692 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
3693 ixgbe_configure_fcoe(adapter
);
3695 #endif /* IXGBE_FCOE */
3696 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
3697 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3698 adapter
->tx_ring
[i
]->atr_sample_rate
=
3699 adapter
->atr_sample_rate
;
3700 ixgbe_init_fdir_signature_82599(hw
, adapter
->fdir_pballoc
);
3701 } else if (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
) {
3702 ixgbe_init_fdir_perfect_82599(hw
, adapter
->fdir_pballoc
);
3704 ixgbe_configure_virtualization(adapter
);
3706 ixgbe_configure_tx(adapter
);
3707 ixgbe_configure_rx(adapter
);
3710 static inline bool ixgbe_is_sfp(struct ixgbe_hw
*hw
)
3712 switch (hw
->phy
.type
) {
3713 case ixgbe_phy_sfp_avago
:
3714 case ixgbe_phy_sfp_ftl
:
3715 case ixgbe_phy_sfp_intel
:
3716 case ixgbe_phy_sfp_unknown
:
3717 case ixgbe_phy_sfp_passive_tyco
:
3718 case ixgbe_phy_sfp_passive_unknown
:
3719 case ixgbe_phy_sfp_active_unknown
:
3720 case ixgbe_phy_sfp_ftl_active
:
3728 * ixgbe_sfp_link_config - set up SFP+ link
3729 * @adapter: pointer to private adapter struct
3731 static void ixgbe_sfp_link_config(struct ixgbe_adapter
*adapter
)
3733 struct ixgbe_hw
*hw
= &adapter
->hw
;
3735 if (hw
->phy
.multispeed_fiber
) {
3737 * In multispeed fiber setups, the device may not have
3738 * had a physical connection when the driver loaded.
3739 * If that's the case, the initial link configuration
3740 * couldn't get the MAC into 10G or 1G mode, so we'll
3741 * never have a link status change interrupt fire.
3742 * We need to try and force an autonegotiation
3743 * session, then bring up link.
3745 if (hw
->mac
.ops
.setup_sfp
)
3746 hw
->mac
.ops
.setup_sfp(hw
);
3747 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_LINK_TASK
))
3748 schedule_work(&adapter
->multispeed_fiber_task
);
3751 * Direct Attach Cu and non-multispeed fiber modules
3752 * still need to be configured properly prior to
3755 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_MOD_TASK
))
3756 schedule_work(&adapter
->sfp_config_module_task
);
3761 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3762 * @hw: pointer to private hardware struct
3764 * Returns 0 on success, negative on failure
3766 static int ixgbe_non_sfp_link_config(struct ixgbe_hw
*hw
)
3769 bool negotiation
, link_up
= false;
3770 u32 ret
= IXGBE_ERR_LINK_SETUP
;
3772 if (hw
->mac
.ops
.check_link
)
3773 ret
= hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
3778 autoneg
= hw
->phy
.autoneg_advertised
;
3779 if ((!autoneg
) && (hw
->mac
.ops
.get_link_capabilities
))
3780 ret
= hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
,
3785 if (hw
->mac
.ops
.setup_link
)
3786 ret
= hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, link_up
);
3791 static void ixgbe_setup_gpie(struct ixgbe_adapter
*adapter
)
3793 struct ixgbe_hw
*hw
= &adapter
->hw
;
3796 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3797 gpie
= IXGBE_GPIE_MSIX_MODE
| IXGBE_GPIE_PBA_SUPPORT
|
3799 gpie
|= IXGBE_GPIE_EIAME
;
3801 * use EIAM to auto-mask when MSI-X interrupt is asserted
3802 * this saves a register write for every interrupt
3804 switch (hw
->mac
.type
) {
3805 case ixgbe_mac_82598EB
:
3806 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
3808 case ixgbe_mac_82599EB
:
3809 case ixgbe_mac_X540
:
3811 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3812 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3816 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3817 * specifically only auto mask tx and rx interrupts */
3818 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
3821 /* XXX: to interrupt immediately for EICS writes, enable this */
3822 /* gpie |= IXGBE_GPIE_EIMEN; */
3824 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
3825 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
3826 gpie
|= IXGBE_GPIE_VTMODE_64
;
3829 /* Enable fan failure interrupt */
3830 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
)
3831 gpie
|= IXGBE_SDP1_GPIEN
;
3833 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
3834 gpie
|= IXGBE_SDP1_GPIEN
;
3835 gpie
|= IXGBE_SDP2_GPIEN
;
3837 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
3840 static int ixgbe_up_complete(struct ixgbe_adapter
*adapter
)
3842 struct ixgbe_hw
*hw
= &adapter
->hw
;
3846 ixgbe_get_hw_control(adapter
);
3847 ixgbe_setup_gpie(adapter
);
3849 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
3850 ixgbe_configure_msix(adapter
);
3852 ixgbe_configure_msi_and_legacy(adapter
);
3854 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3855 if (hw
->mac
.ops
.enable_tx_laser
&&
3856 ((hw
->phy
.multispeed_fiber
) ||
3857 ((hw
->mac
.ops
.get_media_type(hw
) == ixgbe_media_type_fiber
) &&
3858 (hw
->mac
.type
== ixgbe_mac_82599EB
))))
3859 hw
->mac
.ops
.enable_tx_laser(hw
);
3861 clear_bit(__IXGBE_DOWN
, &adapter
->state
);
3862 ixgbe_napi_enable_all(adapter
);
3864 if (ixgbe_is_sfp(hw
)) {
3865 ixgbe_sfp_link_config(adapter
);
3867 err
= ixgbe_non_sfp_link_config(hw
);
3869 e_err(probe
, "link_config FAILED %d\n", err
);
3872 /* clear any pending interrupts, may auto mask */
3873 IXGBE_READ_REG(hw
, IXGBE_EICR
);
3874 ixgbe_irq_enable(adapter
, true, true);
3877 * If this adapter has a fan, check to see if we had a failure
3878 * before we enabled the interrupt.
3880 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
3881 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
3882 if (esdp
& IXGBE_ESDP_SDP1
)
3883 e_crit(drv
, "Fan has stopped, replace the adapter\n");
3887 * For hot-pluggable SFP+ devices, a new SFP+ module may have
3888 * arrived before interrupts were enabled but after probe. Such
3889 * devices wouldn't have their type identified yet. We need to
3890 * kick off the SFP+ module setup first, then try to bring up link.
3891 * If we're not hot-pluggable SFP+, we just need to configure link
3894 if (hw
->phy
.type
== ixgbe_phy_none
)
3895 schedule_work(&adapter
->sfp_config_module_task
);
3897 /* enable transmits */
3898 netif_tx_start_all_queues(adapter
->netdev
);
3900 /* bring the link up in the watchdog, this could race with our first
3901 * link up interrupt but shouldn't be a problem */
3902 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
3903 adapter
->link_check_timeout
= jiffies
;
3904 mod_timer(&adapter
->watchdog_timer
, jiffies
);
3906 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3907 ctrl_ext
= IXGBE_READ_REG(hw
, IXGBE_CTRL_EXT
);
3908 ctrl_ext
|= IXGBE_CTRL_EXT_PFRSTD
;
3909 IXGBE_WRITE_REG(hw
, IXGBE_CTRL_EXT
, ctrl_ext
);
3914 void ixgbe_reinit_locked(struct ixgbe_adapter
*adapter
)
3916 WARN_ON(in_interrupt());
3917 while (test_and_set_bit(__IXGBE_RESETTING
, &adapter
->state
))
3919 ixgbe_down(adapter
);
3921 * If SR-IOV enabled then wait a bit before bringing the adapter
3922 * back up to give the VFs time to respond to the reset. The
3923 * two second wait is based upon the watchdog timer cycle in
3926 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
3929 clear_bit(__IXGBE_RESETTING
, &adapter
->state
);
3932 int ixgbe_up(struct ixgbe_adapter
*adapter
)
3934 /* hardware has been reset, we need to reload some things */
3935 ixgbe_configure(adapter
);
3937 return ixgbe_up_complete(adapter
);
3940 void ixgbe_reset(struct ixgbe_adapter
*adapter
)
3942 struct ixgbe_hw
*hw
= &adapter
->hw
;
3945 err
= hw
->mac
.ops
.init_hw(hw
);
3948 case IXGBE_ERR_SFP_NOT_PRESENT
:
3950 case IXGBE_ERR_MASTER_REQUESTS_PENDING
:
3951 e_dev_err("master disable timed out\n");
3953 case IXGBE_ERR_EEPROM_VERSION
:
3954 /* We are running on a pre-production device, log a warning */
3955 e_dev_warn("This device is a pre-production adapter/LOM. "
3956 "Please be aware there may be issuesassociated with "
3957 "your hardware. If you are experiencing problems "
3958 "please contact your Intel or hardware "
3959 "representative who provided you with this "
3963 e_dev_err("Hardware Error: %d\n", err
);
3966 /* reprogram the RAR[0] in case user changed it. */
3967 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
3972 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3973 * @rx_ring: ring to free buffers from
3975 static void ixgbe_clean_rx_ring(struct ixgbe_ring
*rx_ring
)
3977 struct device
*dev
= rx_ring
->dev
;
3981 /* ring already cleared, nothing to do */
3982 if (!rx_ring
->rx_buffer_info
)
3985 /* Free all the Rx ring sk_buffs */
3986 for (i
= 0; i
< rx_ring
->count
; i
++) {
3987 struct ixgbe_rx_buffer
*rx_buffer_info
;
3989 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
3990 if (rx_buffer_info
->dma
) {
3991 dma_unmap_single(rx_ring
->dev
, rx_buffer_info
->dma
,
3992 rx_ring
->rx_buf_len
,
3994 rx_buffer_info
->dma
= 0;
3996 if (rx_buffer_info
->skb
) {
3997 struct sk_buff
*skb
= rx_buffer_info
->skb
;
3998 rx_buffer_info
->skb
= NULL
;
4000 struct sk_buff
*this = skb
;
4001 if (IXGBE_RSC_CB(this)->delay_unmap
) {
4002 dma_unmap_single(dev
,
4003 IXGBE_RSC_CB(this)->dma
,
4004 rx_ring
->rx_buf_len
,
4006 IXGBE_RSC_CB(this)->dma
= 0;
4007 IXGBE_RSC_CB(skb
)->delay_unmap
= false;
4010 dev_kfree_skb(this);
4013 if (!rx_buffer_info
->page
)
4015 if (rx_buffer_info
->page_dma
) {
4016 dma_unmap_page(dev
, rx_buffer_info
->page_dma
,
4017 PAGE_SIZE
/ 2, DMA_FROM_DEVICE
);
4018 rx_buffer_info
->page_dma
= 0;
4020 put_page(rx_buffer_info
->page
);
4021 rx_buffer_info
->page
= NULL
;
4022 rx_buffer_info
->page_offset
= 0;
4025 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
4026 memset(rx_ring
->rx_buffer_info
, 0, size
);
4028 /* Zero out the descriptor ring */
4029 memset(rx_ring
->desc
, 0, rx_ring
->size
);
4031 rx_ring
->next_to_clean
= 0;
4032 rx_ring
->next_to_use
= 0;
4036 * ixgbe_clean_tx_ring - Free Tx Buffers
4037 * @tx_ring: ring to be cleaned
4039 static void ixgbe_clean_tx_ring(struct ixgbe_ring
*tx_ring
)
4041 struct ixgbe_tx_buffer
*tx_buffer_info
;
4045 /* ring already cleared, nothing to do */
4046 if (!tx_ring
->tx_buffer_info
)
4049 /* Free all the Tx ring sk_buffs */
4050 for (i
= 0; i
< tx_ring
->count
; i
++) {
4051 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
4052 ixgbe_unmap_and_free_tx_resource(tx_ring
, tx_buffer_info
);
4055 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
4056 memset(tx_ring
->tx_buffer_info
, 0, size
);
4058 /* Zero out the descriptor ring */
4059 memset(tx_ring
->desc
, 0, tx_ring
->size
);
4061 tx_ring
->next_to_use
= 0;
4062 tx_ring
->next_to_clean
= 0;
4066 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4067 * @adapter: board private structure
4069 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter
*adapter
)
4073 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4074 ixgbe_clean_rx_ring(adapter
->rx_ring
[i
]);
4078 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4079 * @adapter: board private structure
4081 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter
*adapter
)
4085 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4086 ixgbe_clean_tx_ring(adapter
->tx_ring
[i
]);
4089 void ixgbe_down(struct ixgbe_adapter
*adapter
)
4091 struct net_device
*netdev
= adapter
->netdev
;
4092 struct ixgbe_hw
*hw
= &adapter
->hw
;
4096 int num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4098 /* signal that we are down to the interrupt handler */
4099 set_bit(__IXGBE_DOWN
, &adapter
->state
);
4101 /* disable receive for all VFs and wait one second */
4102 if (adapter
->num_vfs
) {
4103 /* ping all the active vfs to let them know we are going down */
4104 ixgbe_ping_all_vfs(adapter
);
4106 /* Disable all VFTE/VFRE TX/RX */
4107 ixgbe_disable_tx_rx(adapter
);
4109 /* Mark all the VFs as inactive */
4110 for (i
= 0 ; i
< adapter
->num_vfs
; i
++)
4111 adapter
->vfinfo
[i
].clear_to_send
= 0;
4114 /* disable receives */
4115 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
4116 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
4118 /* disable all enabled rx queues */
4119 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4120 /* this call also flushes the previous write */
4121 ixgbe_disable_rx_queue(adapter
, adapter
->rx_ring
[i
]);
4125 netif_tx_stop_all_queues(netdev
);
4127 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
4128 del_timer_sync(&adapter
->sfp_timer
);
4129 del_timer_sync(&adapter
->watchdog_timer
);
4130 cancel_work_sync(&adapter
->watchdog_task
);
4132 netif_carrier_off(netdev
);
4133 netif_tx_disable(netdev
);
4135 ixgbe_irq_disable(adapter
);
4137 ixgbe_napi_disable_all(adapter
);
4139 /* Cleanup the affinity_hint CPU mask memory and callback */
4140 for (i
= 0; i
< num_q_vectors
; i
++) {
4141 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
4142 /* clear the affinity_mask in the IRQ descriptor */
4143 irq_set_affinity_hint(adapter
->msix_entries
[i
]. vector
, NULL
);
4144 /* release the CPU mask memory */
4145 free_cpumask_var(q_vector
->affinity_mask
);
4148 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
4149 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
4150 cancel_work_sync(&adapter
->fdir_reinit_task
);
4152 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
)
4153 cancel_work_sync(&adapter
->check_overtemp_task
);
4155 /* disable transmits in the hardware now that interrupts are off */
4156 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4157 u8 reg_idx
= adapter
->tx_ring
[i
]->reg_idx
;
4158 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(reg_idx
));
4159 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(reg_idx
),
4160 (txdctl
& ~IXGBE_TXDCTL_ENABLE
));
4162 /* Disable the Tx DMA engine on 82599 */
4163 switch (hw
->mac
.type
) {
4164 case ixgbe_mac_82599EB
:
4165 case ixgbe_mac_X540
:
4166 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
,
4167 (IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
) &
4168 ~IXGBE_DMATXCTL_TE
));
4174 /* clear n-tuple filters that are cached */
4175 ethtool_ntuple_flush(netdev
);
4177 if (!pci_channel_offline(adapter
->pdev
))
4178 ixgbe_reset(adapter
);
4180 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4181 if (hw
->mac
.ops
.disable_tx_laser
&&
4182 ((hw
->phy
.multispeed_fiber
) ||
4183 ((hw
->mac
.ops
.get_media_type(hw
) == ixgbe_media_type_fiber
) &&
4184 (hw
->mac
.type
== ixgbe_mac_82599EB
))))
4185 hw
->mac
.ops
.disable_tx_laser(hw
);
4187 ixgbe_clean_all_tx_rings(adapter
);
4188 ixgbe_clean_all_rx_rings(adapter
);
4190 #ifdef CONFIG_IXGBE_DCA
4191 /* since we reset the hardware DCA settings were cleared */
4192 ixgbe_setup_dca(adapter
);
4197 * ixgbe_poll - NAPI Rx polling callback
4198 * @napi: structure for representing this polling device
4199 * @budget: how many packets driver is allowed to clean
4201 * This function is used for legacy and MSI, NAPI mode
4203 static int ixgbe_poll(struct napi_struct
*napi
, int budget
)
4205 struct ixgbe_q_vector
*q_vector
=
4206 container_of(napi
, struct ixgbe_q_vector
, napi
);
4207 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
4208 int tx_clean_complete
, work_done
= 0;
4210 #ifdef CONFIG_IXGBE_DCA
4211 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
4212 ixgbe_update_dca(q_vector
);
4215 tx_clean_complete
= ixgbe_clean_tx_irq(q_vector
, adapter
->tx_ring
[0]);
4216 ixgbe_clean_rx_irq(q_vector
, adapter
->rx_ring
[0], &work_done
, budget
);
4218 if (!tx_clean_complete
)
4221 /* If budget not fully consumed, exit the polling mode */
4222 if (work_done
< budget
) {
4223 napi_complete(napi
);
4224 if (adapter
->rx_itr_setting
& 1)
4225 ixgbe_set_itr(adapter
);
4226 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
4227 ixgbe_irq_enable_queues(adapter
, IXGBE_EIMS_RTX_QUEUE
);
4233 * ixgbe_tx_timeout - Respond to a Tx Hang
4234 * @netdev: network interface device structure
4236 static void ixgbe_tx_timeout(struct net_device
*netdev
)
4238 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4240 adapter
->tx_timeout_count
++;
4242 /* Do the reset outside of interrupt context */
4243 schedule_work(&adapter
->reset_task
);
4246 static void ixgbe_reset_task(struct work_struct
*work
)
4248 struct ixgbe_adapter
*adapter
;
4249 adapter
= container_of(work
, struct ixgbe_adapter
, reset_task
);
4251 /* If we're already down or resetting, just bail */
4252 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
4253 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
4256 ixgbe_dump(adapter
);
4257 netdev_err(adapter
->netdev
, "Reset adapter\n");
4258 ixgbe_reinit_locked(adapter
);
4261 #ifdef CONFIG_IXGBE_DCB
4262 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter
*adapter
)
4265 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_DCB
];
4267 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
))
4271 adapter
->num_rx_queues
= f
->indices
;
4272 adapter
->num_tx_queues
= f
->indices
;
4280 * ixgbe_set_rss_queues: Allocate queues for RSS
4281 * @adapter: board private structure to initialize
4283 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4284 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4287 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter
*adapter
)
4290 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_RSS
];
4292 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4294 adapter
->num_rx_queues
= f
->indices
;
4295 adapter
->num_tx_queues
= f
->indices
;
4305 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4306 * @adapter: board private structure to initialize
4308 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4309 * to the original CPU that initiated the Tx session. This runs in addition
4310 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4311 * Rx load across CPUs using RSS.
4314 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter
*adapter
)
4317 struct ixgbe_ring_feature
*f_fdir
= &adapter
->ring_feature
[RING_F_FDIR
];
4319 f_fdir
->indices
= min((int)num_online_cpus(), f_fdir
->indices
);
4322 /* Flow Director must have RSS enabled */
4323 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
&&
4324 ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
4325 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)))) {
4326 adapter
->num_tx_queues
= f_fdir
->indices
;
4327 adapter
->num_rx_queues
= f_fdir
->indices
;
4330 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4331 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
4338 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4339 * @adapter: board private structure to initialize
4341 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4342 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4343 * rx queues out of the max number of rx queues, instead, it is used as the
4344 * index of the first rx queue used by FCoE.
4347 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter
*adapter
)
4350 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
4352 f
->indices
= min((int)num_online_cpus(), f
->indices
);
4353 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
4354 adapter
->num_rx_queues
= 1;
4355 adapter
->num_tx_queues
= 1;
4356 #ifdef CONFIG_IXGBE_DCB
4357 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
4358 e_info(probe
, "FCoE enabled with DCB\n");
4359 ixgbe_set_dcb_queues(adapter
);
4362 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4363 e_info(probe
, "FCoE enabled with RSS\n");
4364 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
4365 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))
4366 ixgbe_set_fdir_queues(adapter
);
4368 ixgbe_set_rss_queues(adapter
);
4370 /* adding FCoE rx rings to the end */
4371 f
->mask
= adapter
->num_rx_queues
;
4372 adapter
->num_rx_queues
+= f
->indices
;
4373 adapter
->num_tx_queues
+= f
->indices
;
4381 #endif /* IXGBE_FCOE */
4383 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4384 * @adapter: board private structure to initialize
4386 * IOV doesn't actually use anything, so just NAK the
4387 * request for now and let the other queue routines
4388 * figure out what to do.
4390 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter
*adapter
)
4396 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4397 * @adapter: board private structure to initialize
4399 * This is the top level queue allocation routine. The order here is very
4400 * important, starting with the "most" number of features turned on at once,
4401 * and ending with the smallest set of features. This way large combinations
4402 * can be allocated if they're turned on, and smaller combinations are the
4403 * fallthrough conditions.
4406 static int ixgbe_set_num_queues(struct ixgbe_adapter
*adapter
)
4408 /* Start with base case */
4409 adapter
->num_rx_queues
= 1;
4410 adapter
->num_tx_queues
= 1;
4411 adapter
->num_rx_pools
= adapter
->num_rx_queues
;
4412 adapter
->num_rx_queues_per_pool
= 1;
4414 if (ixgbe_set_sriov_queues(adapter
))
4418 if (ixgbe_set_fcoe_queues(adapter
))
4421 #endif /* IXGBE_FCOE */
4422 #ifdef CONFIG_IXGBE_DCB
4423 if (ixgbe_set_dcb_queues(adapter
))
4427 if (ixgbe_set_fdir_queues(adapter
))
4430 if (ixgbe_set_rss_queues(adapter
))
4433 /* fallback to base case */
4434 adapter
->num_rx_queues
= 1;
4435 adapter
->num_tx_queues
= 1;
4438 /* Notify the stack of the (possibly) reduced queue counts. */
4439 netif_set_real_num_tx_queues(adapter
->netdev
, adapter
->num_tx_queues
);
4440 return netif_set_real_num_rx_queues(adapter
->netdev
,
4441 adapter
->num_rx_queues
);
4444 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter
*adapter
,
4447 int err
, vector_threshold
;
4449 /* We'll want at least 3 (vector_threshold):
4452 * 3) Other (Link Status Change, etc.)
4453 * 4) TCP Timer (optional)
4455 vector_threshold
= MIN_MSIX_COUNT
;
4457 /* The more we get, the more we will assign to Tx/Rx Cleanup
4458 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4459 * Right now, we simply care about how many we'll get; we'll
4460 * set them up later while requesting irq's.
4462 while (vectors
>= vector_threshold
) {
4463 err
= pci_enable_msix(adapter
->pdev
, adapter
->msix_entries
,
4465 if (!err
) /* Success in acquiring all requested vectors. */
4468 vectors
= 0; /* Nasty failure, quit now */
4469 else /* err == number of vectors we should try again with */
4473 if (vectors
< vector_threshold
) {
4474 /* Can't allocate enough MSI-X interrupts? Oh well.
4475 * This just means we'll go with either a single MSI
4476 * vector or fall back to legacy interrupts.
4478 netif_printk(adapter
, hw
, KERN_DEBUG
, adapter
->netdev
,
4479 "Unable to allocate MSI-X interrupts\n");
4480 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
4481 kfree(adapter
->msix_entries
);
4482 adapter
->msix_entries
= NULL
;
4484 adapter
->flags
|= IXGBE_FLAG_MSIX_ENABLED
; /* Woot! */
4486 * Adjust for only the vectors we'll use, which is minimum
4487 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4488 * vectors we were allocated.
4490 adapter
->num_msix_vectors
= min(vectors
,
4491 adapter
->max_msix_q_vectors
+ NON_Q_VECTORS
);
4496 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4497 * @adapter: board private structure to initialize
4499 * Cache the descriptor ring offsets for RSS to the assigned rings.
4502 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter
*adapter
)
4506 if (!(adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
))
4509 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4510 adapter
->rx_ring
[i
]->reg_idx
= i
;
4511 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4512 adapter
->tx_ring
[i
]->reg_idx
= i
;
4517 #ifdef CONFIG_IXGBE_DCB
4519 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4520 * @adapter: board private structure to initialize
4522 * Cache the descriptor ring offsets for DCB to the assigned rings.
4525 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter
*adapter
)
4529 int dcb_i
= adapter
->ring_feature
[RING_F_DCB
].indices
;
4531 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
))
4534 /* the number of queues is assumed to be symmetric */
4535 switch (adapter
->hw
.mac
.type
) {
4536 case ixgbe_mac_82598EB
:
4537 for (i
= 0; i
< dcb_i
; i
++) {
4538 adapter
->rx_ring
[i
]->reg_idx
= i
<< 3;
4539 adapter
->tx_ring
[i
]->reg_idx
= i
<< 2;
4543 case ixgbe_mac_82599EB
:
4544 case ixgbe_mac_X540
:
4547 * Tx TC0 starts at: descriptor queue 0
4548 * Tx TC1 starts at: descriptor queue 32
4549 * Tx TC2 starts at: descriptor queue 64
4550 * Tx TC3 starts at: descriptor queue 80
4551 * Tx TC4 starts at: descriptor queue 96
4552 * Tx TC5 starts at: descriptor queue 104
4553 * Tx TC6 starts at: descriptor queue 112
4554 * Tx TC7 starts at: descriptor queue 120
4556 * Rx TC0-TC7 are offset by 16 queues each
4558 for (i
= 0; i
< 3; i
++) {
4559 adapter
->tx_ring
[i
]->reg_idx
= i
<< 5;
4560 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
4562 for ( ; i
< 5; i
++) {
4563 adapter
->tx_ring
[i
]->reg_idx
= ((i
+ 2) << 4);
4564 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
4566 for ( ; i
< dcb_i
; i
++) {
4567 adapter
->tx_ring
[i
]->reg_idx
= ((i
+ 8) << 3);
4568 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
4571 } else if (dcb_i
== 4) {
4573 * Tx TC0 starts at: descriptor queue 0
4574 * Tx TC1 starts at: descriptor queue 64
4575 * Tx TC2 starts at: descriptor queue 96
4576 * Tx TC3 starts at: descriptor queue 112
4578 * Rx TC0-TC3 are offset by 32 queues each
4580 adapter
->tx_ring
[0]->reg_idx
= 0;
4581 adapter
->tx_ring
[1]->reg_idx
= 64;
4582 adapter
->tx_ring
[2]->reg_idx
= 96;
4583 adapter
->tx_ring
[3]->reg_idx
= 112;
4584 for (i
= 0 ; i
< dcb_i
; i
++)
4585 adapter
->rx_ring
[i
]->reg_idx
= i
<< 5;
4597 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4598 * @adapter: board private structure to initialize
4600 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4603 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter
*adapter
)
4608 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
&&
4609 ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
4610 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))) {
4611 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4612 adapter
->rx_ring
[i
]->reg_idx
= i
;
4613 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4614 adapter
->tx_ring
[i
]->reg_idx
= i
;
4623 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4624 * @adapter: board private structure to initialize
4626 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4629 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter
*adapter
)
4631 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
4633 u8 fcoe_rx_i
= 0, fcoe_tx_i
= 0;
4635 if (!(adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
))
4638 #ifdef CONFIG_IXGBE_DCB
4639 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
4640 struct ixgbe_fcoe
*fcoe
= &adapter
->fcoe
;
4642 ixgbe_cache_ring_dcb(adapter
);
4643 /* find out queues in TC for FCoE */
4644 fcoe_rx_i
= adapter
->rx_ring
[fcoe
->tc
]->reg_idx
+ 1;
4645 fcoe_tx_i
= adapter
->tx_ring
[fcoe
->tc
]->reg_idx
+ 1;
4647 * In 82599, the number of Tx queues for each traffic
4648 * class for both 8-TC and 4-TC modes are:
4649 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4650 * 8 TCs: 32 32 16 16 8 8 8 8
4651 * 4 TCs: 64 64 32 32
4652 * We have max 8 queues for FCoE, where 8 the is
4653 * FCoE redirection table size. If TC for FCoE is
4654 * less than or equal to TC3, we have enough queues
4655 * to add max of 8 queues for FCoE, so we start FCoE
4656 * Tx queue from the next one, i.e., reg_idx + 1.
4657 * If TC for FCoE is above TC3, implying 8 TC mode,
4658 * and we need 8 for FCoE, we have to take all queues
4659 * in that traffic class for FCoE.
4661 if ((f
->indices
== IXGBE_FCRETA_SIZE
) && (fcoe
->tc
> 3))
4664 #endif /* CONFIG_IXGBE_DCB */
4665 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4666 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
4667 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))
4668 ixgbe_cache_ring_fdir(adapter
);
4670 ixgbe_cache_ring_rss(adapter
);
4672 fcoe_rx_i
= f
->mask
;
4673 fcoe_tx_i
= f
->mask
;
4675 for (i
= 0; i
< f
->indices
; i
++, fcoe_rx_i
++, fcoe_tx_i
++) {
4676 adapter
->rx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_rx_i
;
4677 adapter
->tx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_tx_i
;
4682 #endif /* IXGBE_FCOE */
4684 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4685 * @adapter: board private structure to initialize
4687 * SR-IOV doesn't use any descriptor rings but changes the default if
4688 * no other mapping is used.
4691 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter
*adapter
)
4693 adapter
->rx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
4694 adapter
->tx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
4695 if (adapter
->num_vfs
)
4702 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4703 * @adapter: board private structure to initialize
4705 * Once we know the feature-set enabled for the device, we'll cache
4706 * the register offset the descriptor ring is assigned to.
4708 * Note, the order the various feature calls is important. It must start with
4709 * the "most" features enabled at the same time, then trickle down to the
4710 * least amount of features turned on at once.
4712 static void ixgbe_cache_ring_register(struct ixgbe_adapter
*adapter
)
4714 /* start with default case */
4715 adapter
->rx_ring
[0]->reg_idx
= 0;
4716 adapter
->tx_ring
[0]->reg_idx
= 0;
4718 if (ixgbe_cache_ring_sriov(adapter
))
4722 if (ixgbe_cache_ring_fcoe(adapter
))
4725 #endif /* IXGBE_FCOE */
4726 #ifdef CONFIG_IXGBE_DCB
4727 if (ixgbe_cache_ring_dcb(adapter
))
4731 if (ixgbe_cache_ring_fdir(adapter
))
4734 if (ixgbe_cache_ring_rss(adapter
))
4739 * ixgbe_alloc_queues - Allocate memory for all rings
4740 * @adapter: board private structure to initialize
4742 * We allocate one ring per queue at run-time since we don't know the
4743 * number of queues at compile-time. The polling_netdev array is
4744 * intended for Multiqueue, but should work fine with a single queue.
4746 static int ixgbe_alloc_queues(struct ixgbe_adapter
*adapter
)
4748 int rx
= 0, tx
= 0, nid
= adapter
->node
;
4750 if (nid
< 0 || !node_online(nid
))
4751 nid
= first_online_node
;
4753 for (; tx
< adapter
->num_tx_queues
; tx
++) {
4754 struct ixgbe_ring
*ring
;
4756 ring
= kzalloc_node(sizeof(*ring
), GFP_KERNEL
, nid
);
4758 ring
= kzalloc(sizeof(*ring
), GFP_KERNEL
);
4760 goto err_allocation
;
4761 ring
->count
= adapter
->tx_ring_count
;
4762 ring
->queue_index
= tx
;
4763 ring
->numa_node
= nid
;
4764 ring
->dev
= &adapter
->pdev
->dev
;
4765 ring
->netdev
= adapter
->netdev
;
4767 adapter
->tx_ring
[tx
] = ring
;
4770 for (; rx
< adapter
->num_rx_queues
; rx
++) {
4771 struct ixgbe_ring
*ring
;
4773 ring
= kzalloc_node(sizeof(*ring
), GFP_KERNEL
, nid
);
4775 ring
= kzalloc(sizeof(*ring
), GFP_KERNEL
);
4777 goto err_allocation
;
4778 ring
->count
= adapter
->rx_ring_count
;
4779 ring
->queue_index
= rx
;
4780 ring
->numa_node
= nid
;
4781 ring
->dev
= &adapter
->pdev
->dev
;
4782 ring
->netdev
= adapter
->netdev
;
4784 adapter
->rx_ring
[rx
] = ring
;
4787 ixgbe_cache_ring_register(adapter
);
4793 kfree(adapter
->tx_ring
[--tx
]);
4796 kfree(adapter
->rx_ring
[--rx
]);
4801 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4802 * @adapter: board private structure to initialize
4804 * Attempt to configure the interrupts using the best available
4805 * capabilities of the hardware and the kernel.
4807 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter
*adapter
)
4809 struct ixgbe_hw
*hw
= &adapter
->hw
;
4811 int vector
, v_budget
;
4814 * It's easy to be greedy for MSI-X vectors, but it really
4815 * doesn't do us much good if we have a lot more vectors
4816 * than CPU's. So let's be conservative and only ask for
4817 * (roughly) the same number of vectors as there are CPU's.
4819 v_budget
= min(adapter
->num_rx_queues
+ adapter
->num_tx_queues
,
4820 (int)num_online_cpus()) + NON_Q_VECTORS
;
4823 * At the same time, hardware can only support a maximum of
4824 * hw.mac->max_msix_vectors vectors. With features
4825 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4826 * descriptor queues supported by our device. Thus, we cap it off in
4827 * those rare cases where the cpu count also exceeds our vector limit.
4829 v_budget
= min(v_budget
, (int)hw
->mac
.max_msix_vectors
);
4831 /* A failure in MSI-X entry allocation isn't fatal, but it does
4832 * mean we disable MSI-X capabilities of the adapter. */
4833 adapter
->msix_entries
= kcalloc(v_budget
,
4834 sizeof(struct msix_entry
), GFP_KERNEL
);
4835 if (adapter
->msix_entries
) {
4836 for (vector
= 0; vector
< v_budget
; vector
++)
4837 adapter
->msix_entries
[vector
].entry
= vector
;
4839 ixgbe_acquire_msix_vectors(adapter
, v_budget
);
4841 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
4845 adapter
->flags
&= ~IXGBE_FLAG_DCB_ENABLED
;
4846 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
4847 if (adapter
->flags
& (IXGBE_FLAG_FDIR_HASH_CAPABLE
|
4848 IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)) {
4850 "Flow Director is not supported while multiple "
4851 "queues are disabled. Disabling Flow Director\n");
4853 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4854 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
4855 adapter
->atr_sample_rate
= 0;
4856 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
4857 ixgbe_disable_sriov(adapter
);
4859 err
= ixgbe_set_num_queues(adapter
);
4863 err
= pci_enable_msi(adapter
->pdev
);
4865 adapter
->flags
|= IXGBE_FLAG_MSI_ENABLED
;
4867 netif_printk(adapter
, hw
, KERN_DEBUG
, adapter
->netdev
,
4868 "Unable to allocate MSI interrupt, "
4869 "falling back to legacy. Error: %d\n", err
);
4879 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4880 * @adapter: board private structure to initialize
4882 * We allocate one q_vector per queue interrupt. If allocation fails we
4885 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter
*adapter
)
4887 int q_idx
, num_q_vectors
;
4888 struct ixgbe_q_vector
*q_vector
;
4889 int (*poll
)(struct napi_struct
*, int);
4891 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4892 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4893 poll
= &ixgbe_clean_rxtx_many
;
4899 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
4900 q_vector
= kzalloc_node(sizeof(struct ixgbe_q_vector
),
4901 GFP_KERNEL
, adapter
->node
);
4903 q_vector
= kzalloc(sizeof(struct ixgbe_q_vector
),
4907 q_vector
->adapter
= adapter
;
4908 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
4909 q_vector
->eitr
= adapter
->tx_eitr_param
;
4911 q_vector
->eitr
= adapter
->rx_eitr_param
;
4912 q_vector
->v_idx
= q_idx
;
4913 netif_napi_add(adapter
->netdev
, &q_vector
->napi
, (*poll
), 64);
4914 adapter
->q_vector
[q_idx
] = q_vector
;
4922 q_vector
= adapter
->q_vector
[q_idx
];
4923 netif_napi_del(&q_vector
->napi
);
4925 adapter
->q_vector
[q_idx
] = NULL
;
4931 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4932 * @adapter: board private structure to initialize
4934 * This function frees the memory allocated to the q_vectors. In addition if
4935 * NAPI is enabled it will delete any references to the NAPI struct prior
4936 * to freeing the q_vector.
4938 static void ixgbe_free_q_vectors(struct ixgbe_adapter
*adapter
)
4940 int q_idx
, num_q_vectors
;
4942 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
4943 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4947 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
4948 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[q_idx
];
4949 adapter
->q_vector
[q_idx
] = NULL
;
4950 netif_napi_del(&q_vector
->napi
);
4955 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter
*adapter
)
4957 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4958 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
4959 pci_disable_msix(adapter
->pdev
);
4960 kfree(adapter
->msix_entries
);
4961 adapter
->msix_entries
= NULL
;
4962 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
4963 adapter
->flags
&= ~IXGBE_FLAG_MSI_ENABLED
;
4964 pci_disable_msi(adapter
->pdev
);
4969 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4970 * @adapter: board private structure to initialize
4972 * We determine which interrupt scheme to use based on...
4973 * - Kernel support (MSI, MSI-X)
4974 * - which can be user-defined (via MODULE_PARAM)
4975 * - Hardware queue count (num_*_queues)
4976 * - defined by miscellaneous hardware support/features (RSS, etc.)
4978 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter
*adapter
)
4982 /* Number of supported queues */
4983 err
= ixgbe_set_num_queues(adapter
);
4987 err
= ixgbe_set_interrupt_capability(adapter
);
4989 e_dev_err("Unable to setup interrupt capabilities\n");
4990 goto err_set_interrupt
;
4993 err
= ixgbe_alloc_q_vectors(adapter
);
4995 e_dev_err("Unable to allocate memory for queue vectors\n");
4996 goto err_alloc_q_vectors
;
4999 err
= ixgbe_alloc_queues(adapter
);
5001 e_dev_err("Unable to allocate memory for queues\n");
5002 goto err_alloc_queues
;
5005 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
5006 (adapter
->num_rx_queues
> 1) ? "Enabled" : "Disabled",
5007 adapter
->num_rx_queues
, adapter
->num_tx_queues
);
5009 set_bit(__IXGBE_DOWN
, &adapter
->state
);
5014 ixgbe_free_q_vectors(adapter
);
5015 err_alloc_q_vectors
:
5016 ixgbe_reset_interrupt_capability(adapter
);
5021 static void ring_free_rcu(struct rcu_head
*head
)
5023 kfree(container_of(head
, struct ixgbe_ring
, rcu
));
5027 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5028 * @adapter: board private structure to clear interrupt scheme on
5030 * We go through and clear interrupt specific resources and reset the structure
5031 * to pre-load conditions
5033 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter
*adapter
)
5037 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5038 kfree(adapter
->tx_ring
[i
]);
5039 adapter
->tx_ring
[i
] = NULL
;
5041 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5042 struct ixgbe_ring
*ring
= adapter
->rx_ring
[i
];
5044 /* ixgbe_get_stats64() might access this ring, we must wait
5045 * a grace period before freeing it.
5047 call_rcu(&ring
->rcu
, ring_free_rcu
);
5048 adapter
->rx_ring
[i
] = NULL
;
5051 adapter
->num_tx_queues
= 0;
5052 adapter
->num_rx_queues
= 0;
5054 ixgbe_free_q_vectors(adapter
);
5055 ixgbe_reset_interrupt_capability(adapter
);
5059 * ixgbe_sfp_timer - worker thread to find a missing module
5060 * @data: pointer to our adapter struct
5062 static void ixgbe_sfp_timer(unsigned long data
)
5064 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
5067 * Do the sfp_timer outside of interrupt context due to the
5068 * delays that sfp+ detection requires
5070 schedule_work(&adapter
->sfp_task
);
5074 * ixgbe_sfp_task - worker thread to find a missing module
5075 * @work: pointer to work_struct containing our data
5077 static void ixgbe_sfp_task(struct work_struct
*work
)
5079 struct ixgbe_adapter
*adapter
= container_of(work
,
5080 struct ixgbe_adapter
,
5082 struct ixgbe_hw
*hw
= &adapter
->hw
;
5084 if ((hw
->phy
.type
== ixgbe_phy_nl
) &&
5085 (hw
->phy
.sfp_type
== ixgbe_sfp_type_not_present
)) {
5086 s32 ret
= hw
->phy
.ops
.identify_sfp(hw
);
5087 if (ret
== IXGBE_ERR_SFP_NOT_PRESENT
)
5089 ret
= hw
->phy
.ops
.reset(hw
);
5090 if (ret
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
5091 e_dev_err("failed to initialize because an unsupported "
5092 "SFP+ module type was detected.\n");
5093 e_dev_err("Reload the driver after installing a "
5094 "supported module.\n");
5095 unregister_netdev(adapter
->netdev
);
5097 e_info(probe
, "detected SFP+: %d\n", hw
->phy
.sfp_type
);
5099 /* don't need this routine any more */
5100 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
5104 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
))
5105 mod_timer(&adapter
->sfp_timer
,
5106 round_jiffies(jiffies
+ (2 * HZ
)));
5110 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5111 * @adapter: board private structure to initialize
5113 * ixgbe_sw_init initializes the Adapter private data structure.
5114 * Fields are initialized based on PCI device information and
5115 * OS network device settings (MTU size).
5117 static int __devinit
ixgbe_sw_init(struct ixgbe_adapter
*adapter
)
5119 struct ixgbe_hw
*hw
= &adapter
->hw
;
5120 struct pci_dev
*pdev
= adapter
->pdev
;
5121 struct net_device
*dev
= adapter
->netdev
;
5123 #ifdef CONFIG_IXGBE_DCB
5125 struct tc_configuration
*tc
;
5127 int max_frame
= dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
5129 /* PCI config space info */
5131 hw
->vendor_id
= pdev
->vendor
;
5132 hw
->device_id
= pdev
->device
;
5133 hw
->revision_id
= pdev
->revision
;
5134 hw
->subsystem_vendor_id
= pdev
->subsystem_vendor
;
5135 hw
->subsystem_device_id
= pdev
->subsystem_device
;
5137 /* Set capability flags */
5138 rss
= min(IXGBE_MAX_RSS_INDICES
, (int)num_online_cpus());
5139 adapter
->ring_feature
[RING_F_RSS
].indices
= rss
;
5140 adapter
->flags
|= IXGBE_FLAG_RSS_ENABLED
;
5141 adapter
->ring_feature
[RING_F_DCB
].indices
= IXGBE_MAX_DCB_INDICES
;
5142 switch (hw
->mac
.type
) {
5143 case ixgbe_mac_82598EB
:
5144 if (hw
->device_id
== IXGBE_DEV_ID_82598AT
)
5145 adapter
->flags
|= IXGBE_FLAG_FAN_FAIL_CAPABLE
;
5146 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82598
;
5148 case ixgbe_mac_82599EB
:
5149 case ixgbe_mac_X540
:
5150 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82599
;
5151 adapter
->flags2
|= IXGBE_FLAG2_RSC_CAPABLE
;
5152 adapter
->flags2
|= IXGBE_FLAG2_RSC_ENABLED
;
5153 if (hw
->device_id
== IXGBE_DEV_ID_82599_T3_LOM
)
5154 adapter
->flags2
|= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
;
5155 /* n-tuple support exists, always init our spinlock */
5156 spin_lock_init(&adapter
->fdir_perfect_lock
);
5157 /* Flow Director hash filters enabled */
5158 adapter
->flags
|= IXGBE_FLAG_FDIR_HASH_CAPABLE
;
5159 adapter
->atr_sample_rate
= 20;
5160 adapter
->ring_feature
[RING_F_FDIR
].indices
=
5161 IXGBE_MAX_FDIR_INDICES
;
5162 adapter
->fdir_pballoc
= 0;
5164 adapter
->flags
|= IXGBE_FLAG_FCOE_CAPABLE
;
5165 adapter
->flags
&= ~IXGBE_FLAG_FCOE_ENABLED
;
5166 adapter
->ring_feature
[RING_F_FCOE
].indices
= 0;
5167 #ifdef CONFIG_IXGBE_DCB
5168 /* Default traffic class to use for FCoE */
5169 adapter
->fcoe
.tc
= IXGBE_FCOE_DEFTC
;
5170 adapter
->fcoe
.up
= IXGBE_FCOE_DEFTC
;
5172 #endif /* IXGBE_FCOE */
5178 #ifdef CONFIG_IXGBE_DCB
5179 /* Configure DCB traffic classes */
5180 for (j
= 0; j
< MAX_TRAFFIC_CLASS
; j
++) {
5181 tc
= &adapter
->dcb_cfg
.tc_config
[j
];
5182 tc
->path
[DCB_TX_CONFIG
].bwg_id
= 0;
5183 tc
->path
[DCB_TX_CONFIG
].bwg_percent
= 12 + (j
& 1);
5184 tc
->path
[DCB_RX_CONFIG
].bwg_id
= 0;
5185 tc
->path
[DCB_RX_CONFIG
].bwg_percent
= 12 + (j
& 1);
5186 tc
->dcb_pfc
= pfc_disabled
;
5188 adapter
->dcb_cfg
.bw_percentage
[DCB_TX_CONFIG
][0] = 100;
5189 adapter
->dcb_cfg
.bw_percentage
[DCB_RX_CONFIG
][0] = 100;
5190 adapter
->dcb_cfg
.rx_pba_cfg
= pba_equal
;
5191 adapter
->dcb_cfg
.pfc_mode_enable
= false;
5192 adapter
->dcb_set_bitmap
= 0x00;
5193 ixgbe_copy_dcb_cfg(&adapter
->dcb_cfg
, &adapter
->temp_dcb_cfg
,
5194 adapter
->ring_feature
[RING_F_DCB
].indices
);
5198 /* default flow control settings */
5199 hw
->fc
.requested_mode
= ixgbe_fc_full
;
5200 hw
->fc
.current_mode
= ixgbe_fc_full
; /* init for ethtool output */
5202 adapter
->last_lfc_mode
= hw
->fc
.current_mode
;
5204 hw
->fc
.high_water
= FC_HIGH_WATER(max_frame
);
5205 hw
->fc
.low_water
= FC_LOW_WATER(max_frame
);
5206 hw
->fc
.pause_time
= IXGBE_DEFAULT_FCPAUSE
;
5207 hw
->fc
.send_xon
= true;
5208 hw
->fc
.disable_fc_autoneg
= false;
5210 /* enable itr by default in dynamic mode */
5211 adapter
->rx_itr_setting
= 1;
5212 adapter
->rx_eitr_param
= 20000;
5213 adapter
->tx_itr_setting
= 1;
5214 adapter
->tx_eitr_param
= 10000;
5216 /* set defaults for eitr in MegaBytes */
5217 adapter
->eitr_low
= 10;
5218 adapter
->eitr_high
= 20;
5220 /* set default ring sizes */
5221 adapter
->tx_ring_count
= IXGBE_DEFAULT_TXD
;
5222 adapter
->rx_ring_count
= IXGBE_DEFAULT_RXD
;
5224 /* initialize eeprom parameters */
5225 if (ixgbe_init_eeprom_params_generic(hw
)) {
5226 e_dev_err("EEPROM initialization failed\n");
5230 /* enable rx csum by default */
5231 adapter
->flags
|= IXGBE_FLAG_RX_CSUM_ENABLED
;
5233 /* get assigned NUMA node */
5234 adapter
->node
= dev_to_node(&pdev
->dev
);
5236 set_bit(__IXGBE_DOWN
, &adapter
->state
);
5242 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5243 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5245 * Return 0 on success, negative on failure
5247 int ixgbe_setup_tx_resources(struct ixgbe_ring
*tx_ring
)
5249 struct device
*dev
= tx_ring
->dev
;
5252 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
5253 tx_ring
->tx_buffer_info
= vzalloc_node(size
, tx_ring
->numa_node
);
5254 if (!tx_ring
->tx_buffer_info
)
5255 tx_ring
->tx_buffer_info
= vzalloc(size
);
5256 if (!tx_ring
->tx_buffer_info
)
5259 /* round up to nearest 4K */
5260 tx_ring
->size
= tx_ring
->count
* sizeof(union ixgbe_adv_tx_desc
);
5261 tx_ring
->size
= ALIGN(tx_ring
->size
, 4096);
5263 tx_ring
->desc
= dma_alloc_coherent(dev
, tx_ring
->size
,
5264 &tx_ring
->dma
, GFP_KERNEL
);
5268 tx_ring
->next_to_use
= 0;
5269 tx_ring
->next_to_clean
= 0;
5270 tx_ring
->work_limit
= tx_ring
->count
;
5274 vfree(tx_ring
->tx_buffer_info
);
5275 tx_ring
->tx_buffer_info
= NULL
;
5276 dev_err(dev
, "Unable to allocate memory for the Tx descriptor ring\n");
5281 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5282 * @adapter: board private structure
5284 * If this function returns with an error, then it's possible one or
5285 * more of the rings is populated (while the rest are not). It is the
5286 * callers duty to clean those orphaned rings.
5288 * Return 0 on success, negative on failure
5290 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter
*adapter
)
5294 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5295 err
= ixgbe_setup_tx_resources(adapter
->tx_ring
[i
]);
5298 e_err(probe
, "Allocation for Tx Queue %u failed\n", i
);
5306 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5307 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5309 * Returns 0 on success, negative on failure
5311 int ixgbe_setup_rx_resources(struct ixgbe_ring
*rx_ring
)
5313 struct device
*dev
= rx_ring
->dev
;
5316 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
5317 rx_ring
->rx_buffer_info
= vzalloc_node(size
, rx_ring
->numa_node
);
5318 if (!rx_ring
->rx_buffer_info
)
5319 rx_ring
->rx_buffer_info
= vzalloc(size
);
5320 if (!rx_ring
->rx_buffer_info
)
5323 /* Round up to nearest 4K */
5324 rx_ring
->size
= rx_ring
->count
* sizeof(union ixgbe_adv_rx_desc
);
5325 rx_ring
->size
= ALIGN(rx_ring
->size
, 4096);
5327 rx_ring
->desc
= dma_alloc_coherent(dev
, rx_ring
->size
,
5328 &rx_ring
->dma
, GFP_KERNEL
);
5333 rx_ring
->next_to_clean
= 0;
5334 rx_ring
->next_to_use
= 0;
5338 vfree(rx_ring
->rx_buffer_info
);
5339 rx_ring
->rx_buffer_info
= NULL
;
5340 dev_err(dev
, "Unable to allocate memory for the Rx descriptor ring\n");
5345 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5346 * @adapter: board private structure
5348 * If this function returns with an error, then it's possible one or
5349 * more of the rings is populated (while the rest are not). It is the
5350 * callers duty to clean those orphaned rings.
5352 * Return 0 on success, negative on failure
5354 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter
*adapter
)
5358 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5359 err
= ixgbe_setup_rx_resources(adapter
->rx_ring
[i
]);
5362 e_err(probe
, "Allocation for Rx Queue %u failed\n", i
);
5370 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5371 * @tx_ring: Tx descriptor ring for a specific queue
5373 * Free all transmit software resources
5375 void ixgbe_free_tx_resources(struct ixgbe_ring
*tx_ring
)
5377 ixgbe_clean_tx_ring(tx_ring
);
5379 vfree(tx_ring
->tx_buffer_info
);
5380 tx_ring
->tx_buffer_info
= NULL
;
5382 /* if not set, then don't free */
5386 dma_free_coherent(tx_ring
->dev
, tx_ring
->size
,
5387 tx_ring
->desc
, tx_ring
->dma
);
5389 tx_ring
->desc
= NULL
;
5393 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5394 * @adapter: board private structure
5396 * Free all transmit software resources
5398 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter
*adapter
)
5402 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5403 if (adapter
->tx_ring
[i
]->desc
)
5404 ixgbe_free_tx_resources(adapter
->tx_ring
[i
]);
5408 * ixgbe_free_rx_resources - Free Rx Resources
5409 * @rx_ring: ring to clean the resources from
5411 * Free all receive software resources
5413 void ixgbe_free_rx_resources(struct ixgbe_ring
*rx_ring
)
5415 ixgbe_clean_rx_ring(rx_ring
);
5417 vfree(rx_ring
->rx_buffer_info
);
5418 rx_ring
->rx_buffer_info
= NULL
;
5420 /* if not set, then don't free */
5424 dma_free_coherent(rx_ring
->dev
, rx_ring
->size
,
5425 rx_ring
->desc
, rx_ring
->dma
);
5427 rx_ring
->desc
= NULL
;
5431 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5432 * @adapter: board private structure
5434 * Free all receive software resources
5436 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter
*adapter
)
5440 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
5441 if (adapter
->rx_ring
[i
]->desc
)
5442 ixgbe_free_rx_resources(adapter
->rx_ring
[i
]);
5446 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5447 * @netdev: network interface device structure
5448 * @new_mtu: new value for maximum frame size
5450 * Returns 0 on success, negative on failure
5452 static int ixgbe_change_mtu(struct net_device
*netdev
, int new_mtu
)
5454 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5455 struct ixgbe_hw
*hw
= &adapter
->hw
;
5456 int max_frame
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
5458 /* MTU < 68 is an error and causes problems on some kernels */
5459 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
&&
5460 hw
->mac
.type
!= ixgbe_mac_X540
) {
5461 if ((new_mtu
< 68) || (max_frame
> MAXIMUM_ETHERNET_VLAN_SIZE
))
5464 if ((new_mtu
< 68) || (max_frame
> IXGBE_MAX_JUMBO_FRAME_SIZE
))
5468 e_info(probe
, "changing MTU from %d to %d\n", netdev
->mtu
, new_mtu
);
5469 /* must set new MTU before calling down or up */
5470 netdev
->mtu
= new_mtu
;
5472 hw
->fc
.high_water
= FC_HIGH_WATER(max_frame
);
5473 hw
->fc
.low_water
= FC_LOW_WATER(max_frame
);
5475 if (netif_running(netdev
))
5476 ixgbe_reinit_locked(adapter
);
5482 * ixgbe_open - Called when a network interface is made active
5483 * @netdev: network interface device structure
5485 * Returns 0 on success, negative value on failure
5487 * The open entry point is called when a network interface is made
5488 * active by the system (IFF_UP). At this point all resources needed
5489 * for transmit and receive operations are allocated, the interrupt
5490 * handler is registered with the OS, the watchdog timer is started,
5491 * and the stack is notified that the interface is ready.
5493 static int ixgbe_open(struct net_device
*netdev
)
5495 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5498 /* disallow open during test */
5499 if (test_bit(__IXGBE_TESTING
, &adapter
->state
))
5502 netif_carrier_off(netdev
);
5504 /* allocate transmit descriptors */
5505 err
= ixgbe_setup_all_tx_resources(adapter
);
5509 /* allocate receive descriptors */
5510 err
= ixgbe_setup_all_rx_resources(adapter
);
5514 ixgbe_configure(adapter
);
5516 err
= ixgbe_request_irq(adapter
);
5520 err
= ixgbe_up_complete(adapter
);
5524 netif_tx_start_all_queues(netdev
);
5529 ixgbe_release_hw_control(adapter
);
5530 ixgbe_free_irq(adapter
);
5533 ixgbe_free_all_rx_resources(adapter
);
5535 ixgbe_free_all_tx_resources(adapter
);
5536 ixgbe_reset(adapter
);
5542 * ixgbe_close - Disables a network interface
5543 * @netdev: network interface device structure
5545 * Returns 0, this is not allowed to fail
5547 * The close entry point is called when an interface is de-activated
5548 * by the OS. The hardware is still under the drivers control, but
5549 * needs to be disabled. A global MAC reset is issued to stop the
5550 * hardware, and all transmit and receive resources are freed.
5552 static int ixgbe_close(struct net_device
*netdev
)
5554 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5556 ixgbe_down(adapter
);
5557 ixgbe_free_irq(adapter
);
5559 ixgbe_free_all_tx_resources(adapter
);
5560 ixgbe_free_all_rx_resources(adapter
);
5562 ixgbe_release_hw_control(adapter
);
5568 static int ixgbe_resume(struct pci_dev
*pdev
)
5570 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
5571 struct net_device
*netdev
= adapter
->netdev
;
5574 pci_set_power_state(pdev
, PCI_D0
);
5575 pci_restore_state(pdev
);
5577 * pci_restore_state clears dev->state_saved so call
5578 * pci_save_state to restore it.
5580 pci_save_state(pdev
);
5582 err
= pci_enable_device_mem(pdev
);
5584 e_dev_err("Cannot enable PCI device from suspend\n");
5587 pci_set_master(pdev
);
5589 pci_wake_from_d3(pdev
, false);
5591 err
= ixgbe_init_interrupt_scheme(adapter
);
5593 e_dev_err("Cannot initialize interrupts for device\n");
5597 ixgbe_reset(adapter
);
5599 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
5601 if (netif_running(netdev
)) {
5602 err
= ixgbe_open(netdev
);
5607 netif_device_attach(netdev
);
5611 #endif /* CONFIG_PM */
5613 static int __ixgbe_shutdown(struct pci_dev
*pdev
, bool *enable_wake
)
5615 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
5616 struct net_device
*netdev
= adapter
->netdev
;
5617 struct ixgbe_hw
*hw
= &adapter
->hw
;
5619 u32 wufc
= adapter
->wol
;
5624 netif_device_detach(netdev
);
5626 if (netif_running(netdev
)) {
5627 ixgbe_down(adapter
);
5628 ixgbe_free_irq(adapter
);
5629 ixgbe_free_all_tx_resources(adapter
);
5630 ixgbe_free_all_rx_resources(adapter
);
5633 ixgbe_clear_interrupt_scheme(adapter
);
5635 kfree(adapter
->ixgbe_ieee_pfc
);
5636 kfree(adapter
->ixgbe_ieee_ets
);
5640 retval
= pci_save_state(pdev
);
5646 ixgbe_set_rx_mode(netdev
);
5648 /* turn on all-multi mode if wake on multicast is enabled */
5649 if (wufc
& IXGBE_WUFC_MC
) {
5650 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
5651 fctrl
|= IXGBE_FCTRL_MPE
;
5652 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
5655 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
5656 ctrl
|= IXGBE_CTRL_GIO_DIS
;
5657 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, ctrl
);
5659 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, wufc
);
5661 IXGBE_WRITE_REG(hw
, IXGBE_WUC
, 0);
5662 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, 0);
5665 switch (hw
->mac
.type
) {
5666 case ixgbe_mac_82598EB
:
5667 pci_wake_from_d3(pdev
, false);
5669 case ixgbe_mac_82599EB
:
5670 case ixgbe_mac_X540
:
5671 pci_wake_from_d3(pdev
, !!wufc
);
5677 *enable_wake
= !!wufc
;
5679 ixgbe_release_hw_control(adapter
);
5681 pci_disable_device(pdev
);
5687 static int ixgbe_suspend(struct pci_dev
*pdev
, pm_message_t state
)
5692 retval
= __ixgbe_shutdown(pdev
, &wake
);
5697 pci_prepare_to_sleep(pdev
);
5699 pci_wake_from_d3(pdev
, false);
5700 pci_set_power_state(pdev
, PCI_D3hot
);
5705 #endif /* CONFIG_PM */
5707 static void ixgbe_shutdown(struct pci_dev
*pdev
)
5711 __ixgbe_shutdown(pdev
, &wake
);
5713 if (system_state
== SYSTEM_POWER_OFF
) {
5714 pci_wake_from_d3(pdev
, wake
);
5715 pci_set_power_state(pdev
, PCI_D3hot
);
5720 * ixgbe_update_stats - Update the board statistics counters.
5721 * @adapter: board private structure
5723 void ixgbe_update_stats(struct ixgbe_adapter
*adapter
)
5725 struct net_device
*netdev
= adapter
->netdev
;
5726 struct ixgbe_hw
*hw
= &adapter
->hw
;
5727 struct ixgbe_hw_stats
*hwstats
= &adapter
->stats
;
5729 u32 i
, missed_rx
= 0, mpc
, bprc
, lxon
, lxoff
, xon_off_tot
;
5730 u64 non_eop_descs
= 0, restart_queue
= 0, tx_busy
= 0;
5731 u64 alloc_rx_page_failed
= 0, alloc_rx_buff_failed
= 0;
5732 u64 bytes
= 0, packets
= 0;
5734 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
5735 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
5738 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
5741 for (i
= 0; i
< 16; i
++)
5742 adapter
->hw_rx_no_dma_resources
+=
5743 IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
5744 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5745 rsc_count
+= adapter
->rx_ring
[i
]->rx_stats
.rsc_count
;
5746 rsc_flush
+= adapter
->rx_ring
[i
]->rx_stats
.rsc_flush
;
5748 adapter
->rsc_total_count
= rsc_count
;
5749 adapter
->rsc_total_flush
= rsc_flush
;
5752 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5753 struct ixgbe_ring
*rx_ring
= adapter
->rx_ring
[i
];
5754 non_eop_descs
+= rx_ring
->rx_stats
.non_eop_descs
;
5755 alloc_rx_page_failed
+= rx_ring
->rx_stats
.alloc_rx_page_failed
;
5756 alloc_rx_buff_failed
+= rx_ring
->rx_stats
.alloc_rx_buff_failed
;
5757 bytes
+= rx_ring
->stats
.bytes
;
5758 packets
+= rx_ring
->stats
.packets
;
5760 adapter
->non_eop_descs
= non_eop_descs
;
5761 adapter
->alloc_rx_page_failed
= alloc_rx_page_failed
;
5762 adapter
->alloc_rx_buff_failed
= alloc_rx_buff_failed
;
5763 netdev
->stats
.rx_bytes
= bytes
;
5764 netdev
->stats
.rx_packets
= packets
;
5768 /* gather some stats to the adapter struct that are per queue */
5769 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5770 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[i
];
5771 restart_queue
+= tx_ring
->tx_stats
.restart_queue
;
5772 tx_busy
+= tx_ring
->tx_stats
.tx_busy
;
5773 bytes
+= tx_ring
->stats
.bytes
;
5774 packets
+= tx_ring
->stats
.packets
;
5776 adapter
->restart_queue
= restart_queue
;
5777 adapter
->tx_busy
= tx_busy
;
5778 netdev
->stats
.tx_bytes
= bytes
;
5779 netdev
->stats
.tx_packets
= packets
;
5781 hwstats
->crcerrs
+= IXGBE_READ_REG(hw
, IXGBE_CRCERRS
);
5782 for (i
= 0; i
< 8; i
++) {
5783 /* for packet buffers not used, the register should read 0 */
5784 mpc
= IXGBE_READ_REG(hw
, IXGBE_MPC(i
));
5786 hwstats
->mpc
[i
] += mpc
;
5787 total_mpc
+= hwstats
->mpc
[i
];
5788 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
5789 hwstats
->rnbc
[i
] += IXGBE_READ_REG(hw
, IXGBE_RNBC(i
));
5790 hwstats
->qptc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPTC(i
));
5791 hwstats
->qbtc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBTC(i
));
5792 hwstats
->qprc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRC(i
));
5793 hwstats
->qbrc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBRC(i
));
5794 switch (hw
->mac
.type
) {
5795 case ixgbe_mac_82598EB
:
5796 hwstats
->pxonrxc
[i
] +=
5797 IXGBE_READ_REG(hw
, IXGBE_PXONRXC(i
));
5799 case ixgbe_mac_82599EB
:
5800 case ixgbe_mac_X540
:
5801 hwstats
->pxonrxc
[i
] +=
5802 IXGBE_READ_REG(hw
, IXGBE_PXONRXCNT(i
));
5807 hwstats
->pxontxc
[i
] += IXGBE_READ_REG(hw
, IXGBE_PXONTXC(i
));
5808 hwstats
->pxofftxc
[i
] += IXGBE_READ_REG(hw
, IXGBE_PXOFFTXC(i
));
5810 hwstats
->gprc
+= IXGBE_READ_REG(hw
, IXGBE_GPRC
);
5811 /* work around hardware counting issue */
5812 hwstats
->gprc
-= missed_rx
;
5814 ixgbe_update_xoff_received(adapter
);
5816 /* 82598 hardware only has a 32 bit counter in the high register */
5817 switch (hw
->mac
.type
) {
5818 case ixgbe_mac_82598EB
:
5819 hwstats
->lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXC
);
5820 hwstats
->gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCH
);
5821 hwstats
->gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCH
);
5822 hwstats
->tor
+= IXGBE_READ_REG(hw
, IXGBE_TORH
);
5824 case ixgbe_mac_82599EB
:
5825 case ixgbe_mac_X540
:
5826 hwstats
->gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCL
);
5827 IXGBE_READ_REG(hw
, IXGBE_GORCH
); /* to clear */
5828 hwstats
->gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCL
);
5829 IXGBE_READ_REG(hw
, IXGBE_GOTCH
); /* to clear */
5830 hwstats
->tor
+= IXGBE_READ_REG(hw
, IXGBE_TORL
);
5831 IXGBE_READ_REG(hw
, IXGBE_TORH
); /* to clear */
5832 hwstats
->lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXCNT
);
5833 hwstats
->fdirmatch
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMATCH
);
5834 hwstats
->fdirmiss
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMISS
);
5836 hwstats
->fccrc
+= IXGBE_READ_REG(hw
, IXGBE_FCCRC
);
5837 hwstats
->fcoerpdc
+= IXGBE_READ_REG(hw
, IXGBE_FCOERPDC
);
5838 hwstats
->fcoeprc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPRC
);
5839 hwstats
->fcoeptc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPTC
);
5840 hwstats
->fcoedwrc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWRC
);
5841 hwstats
->fcoedwtc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWTC
);
5842 #endif /* IXGBE_FCOE */
5847 bprc
= IXGBE_READ_REG(hw
, IXGBE_BPRC
);
5848 hwstats
->bprc
+= bprc
;
5849 hwstats
->mprc
+= IXGBE_READ_REG(hw
, IXGBE_MPRC
);
5850 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
5851 hwstats
->mprc
-= bprc
;
5852 hwstats
->roc
+= IXGBE_READ_REG(hw
, IXGBE_ROC
);
5853 hwstats
->prc64
+= IXGBE_READ_REG(hw
, IXGBE_PRC64
);
5854 hwstats
->prc127
+= IXGBE_READ_REG(hw
, IXGBE_PRC127
);
5855 hwstats
->prc255
+= IXGBE_READ_REG(hw
, IXGBE_PRC255
);
5856 hwstats
->prc511
+= IXGBE_READ_REG(hw
, IXGBE_PRC511
);
5857 hwstats
->prc1023
+= IXGBE_READ_REG(hw
, IXGBE_PRC1023
);
5858 hwstats
->prc1522
+= IXGBE_READ_REG(hw
, IXGBE_PRC1522
);
5859 hwstats
->rlec
+= IXGBE_READ_REG(hw
, IXGBE_RLEC
);
5860 lxon
= IXGBE_READ_REG(hw
, IXGBE_LXONTXC
);
5861 hwstats
->lxontxc
+= lxon
;
5862 lxoff
= IXGBE_READ_REG(hw
, IXGBE_LXOFFTXC
);
5863 hwstats
->lxofftxc
+= lxoff
;
5864 hwstats
->ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
5865 hwstats
->gptc
+= IXGBE_READ_REG(hw
, IXGBE_GPTC
);
5866 hwstats
->mptc
+= IXGBE_READ_REG(hw
, IXGBE_MPTC
);
5868 * 82598 errata - tx of flow control packets is included in tx counters
5870 xon_off_tot
= lxon
+ lxoff
;
5871 hwstats
->gptc
-= xon_off_tot
;
5872 hwstats
->mptc
-= xon_off_tot
;
5873 hwstats
->gotc
-= (xon_off_tot
* (ETH_ZLEN
+ ETH_FCS_LEN
));
5874 hwstats
->ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
5875 hwstats
->rfc
+= IXGBE_READ_REG(hw
, IXGBE_RFC
);
5876 hwstats
->rjc
+= IXGBE_READ_REG(hw
, IXGBE_RJC
);
5877 hwstats
->tpr
+= IXGBE_READ_REG(hw
, IXGBE_TPR
);
5878 hwstats
->ptc64
+= IXGBE_READ_REG(hw
, IXGBE_PTC64
);
5879 hwstats
->ptc64
-= xon_off_tot
;
5880 hwstats
->ptc127
+= IXGBE_READ_REG(hw
, IXGBE_PTC127
);
5881 hwstats
->ptc255
+= IXGBE_READ_REG(hw
, IXGBE_PTC255
);
5882 hwstats
->ptc511
+= IXGBE_READ_REG(hw
, IXGBE_PTC511
);
5883 hwstats
->ptc1023
+= IXGBE_READ_REG(hw
, IXGBE_PTC1023
);
5884 hwstats
->ptc1522
+= IXGBE_READ_REG(hw
, IXGBE_PTC1522
);
5885 hwstats
->bptc
+= IXGBE_READ_REG(hw
, IXGBE_BPTC
);
5887 /* Fill out the OS statistics structure */
5888 netdev
->stats
.multicast
= hwstats
->mprc
;
5891 netdev
->stats
.rx_errors
= hwstats
->crcerrs
+ hwstats
->rlec
;
5892 netdev
->stats
.rx_dropped
= 0;
5893 netdev
->stats
.rx_length_errors
= hwstats
->rlec
;
5894 netdev
->stats
.rx_crc_errors
= hwstats
->crcerrs
;
5895 netdev
->stats
.rx_missed_errors
= total_mpc
;
5899 * ixgbe_watchdog - Timer Call-back
5900 * @data: pointer to adapter cast into an unsigned long
5902 static void ixgbe_watchdog(unsigned long data
)
5904 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
5905 struct ixgbe_hw
*hw
= &adapter
->hw
;
5910 * Do the watchdog outside of interrupt context due to the lovely
5911 * delays that some of the newer hardware requires
5914 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
5915 goto watchdog_short_circuit
;
5917 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)) {
5919 * for legacy and MSI interrupts don't set any bits
5920 * that are enabled for EIAM, because this operation
5921 * would set *both* EIMS and EICS for any bit in EIAM
5923 IXGBE_WRITE_REG(hw
, IXGBE_EICS
,
5924 (IXGBE_EICS_TCP_TIMER
| IXGBE_EICS_OTHER
));
5925 goto watchdog_reschedule
;
5928 /* get one bit for every active tx/rx interrupt vector */
5929 for (i
= 0; i
< adapter
->num_msix_vectors
- NON_Q_VECTORS
; i
++) {
5930 struct ixgbe_q_vector
*qv
= adapter
->q_vector
[i
];
5931 if (qv
->rxr_count
|| qv
->txr_count
)
5932 eics
|= ((u64
)1 << i
);
5935 /* Cause software interrupt to ensure rx rings are cleaned */
5936 ixgbe_irq_rearm_queues(adapter
, eics
);
5938 watchdog_reschedule
:
5939 /* Reset the timer */
5940 mod_timer(&adapter
->watchdog_timer
, round_jiffies(jiffies
+ 2 * HZ
));
5942 watchdog_short_circuit
:
5943 schedule_work(&adapter
->watchdog_task
);
5947 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5948 * @work: pointer to work_struct containing our data
5950 static void ixgbe_multispeed_fiber_task(struct work_struct
*work
)
5952 struct ixgbe_adapter
*adapter
= container_of(work
,
5953 struct ixgbe_adapter
,
5954 multispeed_fiber_task
);
5955 struct ixgbe_hw
*hw
= &adapter
->hw
;
5959 adapter
->flags
|= IXGBE_FLAG_IN_SFP_LINK_TASK
;
5960 autoneg
= hw
->phy
.autoneg_advertised
;
5961 if ((!autoneg
) && (hw
->mac
.ops
.get_link_capabilities
))
5962 hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
, &negotiation
);
5963 hw
->mac
.autotry_restart
= false;
5964 if (hw
->mac
.ops
.setup_link
)
5965 hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, true);
5966 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
5967 adapter
->flags
&= ~IXGBE_FLAG_IN_SFP_LINK_TASK
;
5971 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5972 * @work: pointer to work_struct containing our data
5974 static void ixgbe_sfp_config_module_task(struct work_struct
*work
)
5976 struct ixgbe_adapter
*adapter
= container_of(work
,
5977 struct ixgbe_adapter
,
5978 sfp_config_module_task
);
5979 struct ixgbe_hw
*hw
= &adapter
->hw
;
5982 adapter
->flags
|= IXGBE_FLAG_IN_SFP_MOD_TASK
;
5984 /* Time for electrical oscillations to settle down */
5986 err
= hw
->phy
.ops
.identify_sfp(hw
);
5988 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
5989 e_dev_err("failed to initialize because an unsupported SFP+ "
5990 "module type was detected.\n");
5991 e_dev_err("Reload the driver after installing a supported "
5993 unregister_netdev(adapter
->netdev
);
5996 if (hw
->mac
.ops
.setup_sfp
)
5997 hw
->mac
.ops
.setup_sfp(hw
);
5999 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_LINK_TASK
))
6000 /* This will also work for DA Twinax connections */
6001 schedule_work(&adapter
->multispeed_fiber_task
);
6002 adapter
->flags
&= ~IXGBE_FLAG_IN_SFP_MOD_TASK
;
6006 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
6007 * @work: pointer to work_struct containing our data
6009 static void ixgbe_fdir_reinit_task(struct work_struct
*work
)
6011 struct ixgbe_adapter
*adapter
= container_of(work
,
6012 struct ixgbe_adapter
,
6014 struct ixgbe_hw
*hw
= &adapter
->hw
;
6017 if (ixgbe_reinit_fdir_tables_82599(hw
) == 0) {
6018 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
6019 set_bit(__IXGBE_TX_FDIR_INIT_DONE
,
6020 &(adapter
->tx_ring
[i
]->state
));
6022 e_err(probe
, "failed to finish FDIR re-initialization, "
6023 "ignored adding FDIR ATR filters\n");
6025 /* Done FDIR Re-initialization, enable transmits */
6026 netif_tx_start_all_queues(adapter
->netdev
);
6029 static void ixgbe_spoof_check(struct ixgbe_adapter
*adapter
)
6033 /* Do not perform spoof check for 82598 */
6034 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
6037 ssvpc
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_SSVPC
);
6040 * ssvpc register is cleared on read, if zero then no
6041 * spoofed packets in the last interval.
6046 e_warn(drv
, "%d Spoofed packets detected\n", ssvpc
);
6049 static DEFINE_MUTEX(ixgbe_watchdog_lock
);
6052 * ixgbe_watchdog_task - worker thread to bring link up
6053 * @work: pointer to work_struct containing our data
6055 static void ixgbe_watchdog_task(struct work_struct
*work
)
6057 struct ixgbe_adapter
*adapter
= container_of(work
,
6058 struct ixgbe_adapter
,
6060 struct net_device
*netdev
= adapter
->netdev
;
6061 struct ixgbe_hw
*hw
= &adapter
->hw
;
6065 struct ixgbe_ring
*tx_ring
;
6066 int some_tx_pending
= 0;
6068 mutex_lock(&ixgbe_watchdog_lock
);
6070 link_up
= adapter
->link_up
;
6071 link_speed
= adapter
->link_speed
;
6073 if (adapter
->flags
& IXGBE_FLAG_NEED_LINK_UPDATE
) {
6074 hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
, false);
6077 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6078 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++)
6079 hw
->mac
.ops
.fc_enable(hw
, i
);
6081 hw
->mac
.ops
.fc_enable(hw
, 0);
6084 hw
->mac
.ops
.fc_enable(hw
, 0);
6089 time_after(jiffies
, (adapter
->link_check_timeout
+
6090 IXGBE_TRY_LINK_TIMEOUT
))) {
6091 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_UPDATE
;
6092 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMC_LSC
);
6094 adapter
->link_up
= link_up
;
6095 adapter
->link_speed
= link_speed
;
6099 if (!netif_carrier_ok(netdev
)) {
6100 bool flow_rx
, flow_tx
;
6102 switch (hw
->mac
.type
) {
6103 case ixgbe_mac_82598EB
: {
6104 u32 frctl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
6105 u32 rmcs
= IXGBE_READ_REG(hw
, IXGBE_RMCS
);
6106 flow_rx
= !!(frctl
& IXGBE_FCTRL_RFCE
);
6107 flow_tx
= !!(rmcs
& IXGBE_RMCS_TFCE_802_3X
);
6110 case ixgbe_mac_82599EB
:
6111 case ixgbe_mac_X540
: {
6112 u32 mflcn
= IXGBE_READ_REG(hw
, IXGBE_MFLCN
);
6113 u32 fccfg
= IXGBE_READ_REG(hw
, IXGBE_FCCFG
);
6114 flow_rx
= !!(mflcn
& IXGBE_MFLCN_RFCE
);
6115 flow_tx
= !!(fccfg
& IXGBE_FCCFG_TFCE_802_3X
);
6124 e_info(drv
, "NIC Link is Up %s, Flow Control: %s\n",
6125 (link_speed
== IXGBE_LINK_SPEED_10GB_FULL
?
6127 (link_speed
== IXGBE_LINK_SPEED_1GB_FULL
?
6129 (link_speed
== IXGBE_LINK_SPEED_100_FULL
?
6132 ((flow_rx
&& flow_tx
) ? "RX/TX" :
6134 (flow_tx
? "TX" : "None"))));
6136 netif_carrier_on(netdev
);
6138 /* Force detection of hung controller */
6139 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
6140 tx_ring
= adapter
->tx_ring
[i
];
6141 set_check_for_tx_hang(tx_ring
);
6145 adapter
->link_up
= false;
6146 adapter
->link_speed
= 0;
6147 if (netif_carrier_ok(netdev
)) {
6148 e_info(drv
, "NIC Link is Down\n");
6149 netif_carrier_off(netdev
);
6153 if (!netif_carrier_ok(netdev
)) {
6154 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
6155 tx_ring
= adapter
->tx_ring
[i
];
6156 if (tx_ring
->next_to_use
!= tx_ring
->next_to_clean
) {
6157 some_tx_pending
= 1;
6162 if (some_tx_pending
) {
6163 /* We've lost link, so the controller stops DMA,
6164 * but we've got queued Tx work that's never going
6165 * to get done, so reset controller to flush Tx.
6166 * (Do the reset outside of interrupt context).
6168 schedule_work(&adapter
->reset_task
);
6172 ixgbe_spoof_check(adapter
);
6173 ixgbe_update_stats(adapter
);
6174 mutex_unlock(&ixgbe_watchdog_lock
);
6177 static int ixgbe_tso(struct ixgbe_adapter
*adapter
,
6178 struct ixgbe_ring
*tx_ring
, struct sk_buff
*skb
,
6179 u32 tx_flags
, u8
*hdr_len
, __be16 protocol
)
6181 struct ixgbe_adv_tx_context_desc
*context_desc
;
6184 struct ixgbe_tx_buffer
*tx_buffer_info
;
6185 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
;
6186 u32 mss_l4len_idx
, l4len
;
6188 if (skb_is_gso(skb
)) {
6189 if (skb_header_cloned(skb
)) {
6190 err
= pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
);
6194 l4len
= tcp_hdrlen(skb
);
6197 if (protocol
== htons(ETH_P_IP
)) {
6198 struct iphdr
*iph
= ip_hdr(skb
);
6201 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
6205 } else if (skb_is_gso_v6(skb
)) {
6206 ipv6_hdr(skb
)->payload_len
= 0;
6207 tcp_hdr(skb
)->check
=
6208 ~csum_ipv6_magic(&ipv6_hdr(skb
)->saddr
,
6209 &ipv6_hdr(skb
)->daddr
,
6213 i
= tx_ring
->next_to_use
;
6215 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6216 context_desc
= IXGBE_TX_CTXTDESC_ADV(tx_ring
, i
);
6218 /* VLAN MACLEN IPLEN */
6219 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
6221 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
6222 vlan_macip_lens
|= ((skb_network_offset(skb
)) <<
6223 IXGBE_ADVTXD_MACLEN_SHIFT
);
6224 *hdr_len
+= skb_network_offset(skb
);
6226 (skb_transport_header(skb
) - skb_network_header(skb
));
6228 (skb_transport_header(skb
) - skb_network_header(skb
));
6229 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
6230 context_desc
->seqnum_seed
= 0;
6232 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6233 type_tucmd_mlhl
= (IXGBE_TXD_CMD_DEXT
|
6234 IXGBE_ADVTXD_DTYP_CTXT
);
6236 if (protocol
== htons(ETH_P_IP
))
6237 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_IPV4
;
6238 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
6239 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
6243 (skb_shinfo(skb
)->gso_size
<< IXGBE_ADVTXD_MSS_SHIFT
);
6244 mss_l4len_idx
|= (l4len
<< IXGBE_ADVTXD_L4LEN_SHIFT
);
6245 /* use index 1 for TSO */
6246 mss_l4len_idx
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
6247 context_desc
->mss_l4len_idx
= cpu_to_le32(mss_l4len_idx
);
6249 tx_buffer_info
->time_stamp
= jiffies
;
6250 tx_buffer_info
->next_to_watch
= i
;
6253 if (i
== tx_ring
->count
)
6255 tx_ring
->next_to_use
= i
;
6262 static u32
ixgbe_psum(struct ixgbe_adapter
*adapter
, struct sk_buff
*skb
,
6268 case cpu_to_be16(ETH_P_IP
):
6269 rtn
|= IXGBE_ADVTXD_TUCMD_IPV4
;
6270 switch (ip_hdr(skb
)->protocol
) {
6272 rtn
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
6275 rtn
|= IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
6279 case cpu_to_be16(ETH_P_IPV6
):
6280 /* XXX what about other V6 headers?? */
6281 switch (ipv6_hdr(skb
)->nexthdr
) {
6283 rtn
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
6286 rtn
|= IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
6291 if (unlikely(net_ratelimit()))
6292 e_warn(probe
, "partial checksum but proto=%x!\n",
6300 static bool ixgbe_tx_csum(struct ixgbe_adapter
*adapter
,
6301 struct ixgbe_ring
*tx_ring
,
6302 struct sk_buff
*skb
, u32 tx_flags
,
6305 struct ixgbe_adv_tx_context_desc
*context_desc
;
6307 struct ixgbe_tx_buffer
*tx_buffer_info
;
6308 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
= 0;
6310 if (skb
->ip_summed
== CHECKSUM_PARTIAL
||
6311 (tx_flags
& IXGBE_TX_FLAGS_VLAN
)) {
6312 i
= tx_ring
->next_to_use
;
6313 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6314 context_desc
= IXGBE_TX_CTXTDESC_ADV(tx_ring
, i
);
6316 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
6318 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
6319 vlan_macip_lens
|= (skb_network_offset(skb
) <<
6320 IXGBE_ADVTXD_MACLEN_SHIFT
);
6321 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
6322 vlan_macip_lens
|= (skb_transport_header(skb
) -
6323 skb_network_header(skb
));
6325 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
6326 context_desc
->seqnum_seed
= 0;
6328 type_tucmd_mlhl
|= (IXGBE_TXD_CMD_DEXT
|
6329 IXGBE_ADVTXD_DTYP_CTXT
);
6331 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
6332 type_tucmd_mlhl
|= ixgbe_psum(adapter
, skb
, protocol
);
6334 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
6335 /* use index zero for tx checksum offload */
6336 context_desc
->mss_l4len_idx
= 0;
6338 tx_buffer_info
->time_stamp
= jiffies
;
6339 tx_buffer_info
->next_to_watch
= i
;
6342 if (i
== tx_ring
->count
)
6344 tx_ring
->next_to_use
= i
;
6352 static int ixgbe_tx_map(struct ixgbe_adapter
*adapter
,
6353 struct ixgbe_ring
*tx_ring
,
6354 struct sk_buff
*skb
, u32 tx_flags
,
6355 unsigned int first
, const u8 hdr_len
)
6357 struct device
*dev
= tx_ring
->dev
;
6358 struct ixgbe_tx_buffer
*tx_buffer_info
;
6360 unsigned int total
= skb
->len
;
6361 unsigned int offset
= 0, size
, count
= 0, i
;
6362 unsigned int nr_frags
= skb_shinfo(skb
)->nr_frags
;
6364 unsigned int bytecount
= skb
->len
;
6367 i
= tx_ring
->next_to_use
;
6369 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
)
6370 /* excluding fcoe_crc_eof for FCoE */
6371 total
-= sizeof(struct fcoe_crc_eof
);
6373 len
= min(skb_headlen(skb
), total
);
6375 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6376 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
6378 tx_buffer_info
->length
= size
;
6379 tx_buffer_info
->mapped_as_page
= false;
6380 tx_buffer_info
->dma
= dma_map_single(dev
,
6382 size
, DMA_TO_DEVICE
);
6383 if (dma_mapping_error(dev
, tx_buffer_info
->dma
))
6385 tx_buffer_info
->time_stamp
= jiffies
;
6386 tx_buffer_info
->next_to_watch
= i
;
6395 if (i
== tx_ring
->count
)
6400 for (f
= 0; f
< nr_frags
; f
++) {
6401 struct skb_frag_struct
*frag
;
6403 frag
= &skb_shinfo(skb
)->frags
[f
];
6404 len
= min((unsigned int)frag
->size
, total
);
6405 offset
= frag
->page_offset
;
6409 if (i
== tx_ring
->count
)
6412 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6413 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
6415 tx_buffer_info
->length
= size
;
6416 tx_buffer_info
->dma
= dma_map_page(dev
,
6420 tx_buffer_info
->mapped_as_page
= true;
6421 if (dma_mapping_error(dev
, tx_buffer_info
->dma
))
6423 tx_buffer_info
->time_stamp
= jiffies
;
6424 tx_buffer_info
->next_to_watch
= i
;
6435 if (tx_flags
& IXGBE_TX_FLAGS_TSO
)
6436 gso_segs
= skb_shinfo(skb
)->gso_segs
;
6438 /* adjust for FCoE Sequence Offload */
6439 else if (tx_flags
& IXGBE_TX_FLAGS_FSO
)
6440 gso_segs
= DIV_ROUND_UP(skb
->len
- hdr_len
,
6441 skb_shinfo(skb
)->gso_size
);
6442 #endif /* IXGBE_FCOE */
6443 bytecount
+= (gso_segs
- 1) * hdr_len
;
6445 /* multiply data chunks by size of headers */
6446 tx_ring
->tx_buffer_info
[i
].bytecount
= bytecount
;
6447 tx_ring
->tx_buffer_info
[i
].gso_segs
= gso_segs
;
6448 tx_ring
->tx_buffer_info
[i
].skb
= skb
;
6449 tx_ring
->tx_buffer_info
[first
].next_to_watch
= i
;
6454 e_dev_err("TX DMA map failed\n");
6456 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6457 tx_buffer_info
->dma
= 0;
6458 tx_buffer_info
->time_stamp
= 0;
6459 tx_buffer_info
->next_to_watch
= 0;
6463 /* clear timestamp and dma mappings for remaining portion of packet */
6466 i
+= tx_ring
->count
;
6468 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6469 ixgbe_unmap_and_free_tx_resource(tx_ring
, tx_buffer_info
);
6475 static void ixgbe_tx_queue(struct ixgbe_ring
*tx_ring
,
6476 int tx_flags
, int count
, u32 paylen
, u8 hdr_len
)
6478 union ixgbe_adv_tx_desc
*tx_desc
= NULL
;
6479 struct ixgbe_tx_buffer
*tx_buffer_info
;
6480 u32 olinfo_status
= 0, cmd_type_len
= 0;
6482 u32 txd_cmd
= IXGBE_TXD_CMD_EOP
| IXGBE_TXD_CMD_RS
| IXGBE_TXD_CMD_IFCS
;
6484 cmd_type_len
|= IXGBE_ADVTXD_DTYP_DATA
;
6486 cmd_type_len
|= IXGBE_ADVTXD_DCMD_IFCS
| IXGBE_ADVTXD_DCMD_DEXT
;
6488 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
6489 cmd_type_len
|= IXGBE_ADVTXD_DCMD_VLE
;
6491 if (tx_flags
& IXGBE_TX_FLAGS_TSO
) {
6492 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
6494 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
6495 IXGBE_ADVTXD_POPTS_SHIFT
;
6497 /* use index 1 context for tso */
6498 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
6499 if (tx_flags
& IXGBE_TX_FLAGS_IPV4
)
6500 olinfo_status
|= IXGBE_TXD_POPTS_IXSM
<<
6501 IXGBE_ADVTXD_POPTS_SHIFT
;
6503 } else if (tx_flags
& IXGBE_TX_FLAGS_CSUM
)
6504 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
6505 IXGBE_ADVTXD_POPTS_SHIFT
;
6507 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
6508 olinfo_status
|= IXGBE_ADVTXD_CC
;
6509 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
6510 if (tx_flags
& IXGBE_TX_FLAGS_FSO
)
6511 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
6514 olinfo_status
|= ((paylen
- hdr_len
) << IXGBE_ADVTXD_PAYLEN_SHIFT
);
6516 i
= tx_ring
->next_to_use
;
6518 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6519 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, i
);
6520 tx_desc
->read
.buffer_addr
= cpu_to_le64(tx_buffer_info
->dma
);
6521 tx_desc
->read
.cmd_type_len
=
6522 cpu_to_le32(cmd_type_len
| tx_buffer_info
->length
);
6523 tx_desc
->read
.olinfo_status
= cpu_to_le32(olinfo_status
);
6525 if (i
== tx_ring
->count
)
6529 tx_desc
->read
.cmd_type_len
|= cpu_to_le32(txd_cmd
);
6532 * Force memory writes to complete before letting h/w
6533 * know there are new descriptors to fetch. (Only
6534 * applicable for weak-ordered memory model archs,
6539 tx_ring
->next_to_use
= i
;
6540 writel(i
, tx_ring
->tail
);
6543 static void ixgbe_atr(struct ixgbe_ring
*ring
, struct sk_buff
*skb
,
6544 u32 tx_flags
, __be16 protocol
)
6546 struct ixgbe_q_vector
*q_vector
= ring
->q_vector
;
6547 union ixgbe_atr_hash_dword input
= { .dword
= 0 };
6548 union ixgbe_atr_hash_dword common
= { .dword
= 0 };
6550 unsigned char *network
;
6552 struct ipv6hdr
*ipv6
;
6557 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6561 /* do nothing if sampling is disabled */
6562 if (!ring
->atr_sample_rate
)
6567 /* snag network header to get L4 type and address */
6568 hdr
.network
= skb_network_header(skb
);
6570 /* Currently only IPv4/IPv6 with TCP is supported */
6571 if ((protocol
!= __constant_htons(ETH_P_IPV6
) ||
6572 hdr
.ipv6
->nexthdr
!= IPPROTO_TCP
) &&
6573 (protocol
!= __constant_htons(ETH_P_IP
) ||
6574 hdr
.ipv4
->protocol
!= IPPROTO_TCP
))
6579 /* skip this packet since the socket is closing */
6583 /* sample on all syn packets or once every atr sample count */
6584 if (!th
->syn
&& (ring
->atr_count
< ring
->atr_sample_rate
))
6587 /* reset sample count */
6588 ring
->atr_count
= 0;
6590 vlan_id
= htons(tx_flags
>> IXGBE_TX_FLAGS_VLAN_SHIFT
);
6593 * src and dst are inverted, think how the receiver sees them
6595 * The input is broken into two sections, a non-compressed section
6596 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6597 * is XORed together and stored in the compressed dword.
6599 input
.formatted
.vlan_id
= vlan_id
;
6602 * since src port and flex bytes occupy the same word XOR them together
6603 * and write the value to source port portion of compressed dword
6606 common
.port
.src
^= th
->dest
^ __constant_htons(ETH_P_8021Q
);
6608 common
.port
.src
^= th
->dest
^ protocol
;
6609 common
.port
.dst
^= th
->source
;
6611 if (protocol
== __constant_htons(ETH_P_IP
)) {
6612 input
.formatted
.flow_type
= IXGBE_ATR_FLOW_TYPE_TCPV4
;
6613 common
.ip
^= hdr
.ipv4
->saddr
^ hdr
.ipv4
->daddr
;
6615 input
.formatted
.flow_type
= IXGBE_ATR_FLOW_TYPE_TCPV6
;
6616 common
.ip
^= hdr
.ipv6
->saddr
.s6_addr32
[0] ^
6617 hdr
.ipv6
->saddr
.s6_addr32
[1] ^
6618 hdr
.ipv6
->saddr
.s6_addr32
[2] ^
6619 hdr
.ipv6
->saddr
.s6_addr32
[3] ^
6620 hdr
.ipv6
->daddr
.s6_addr32
[0] ^
6621 hdr
.ipv6
->daddr
.s6_addr32
[1] ^
6622 hdr
.ipv6
->daddr
.s6_addr32
[2] ^
6623 hdr
.ipv6
->daddr
.s6_addr32
[3];
6626 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6627 ixgbe_fdir_add_signature_filter_82599(&q_vector
->adapter
->hw
,
6628 input
, common
, ring
->queue_index
);
6631 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring
*tx_ring
, int size
)
6633 netif_stop_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
6634 /* Herbert's original patch had:
6635 * smp_mb__after_netif_stop_queue();
6636 * but since that doesn't exist yet, just open code it. */
6639 /* We need to check again in a case another CPU has just
6640 * made room available. */
6641 if (likely(IXGBE_DESC_UNUSED(tx_ring
) < size
))
6644 /* A reprieve! - use start_queue because it doesn't call schedule */
6645 netif_start_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
6646 ++tx_ring
->tx_stats
.restart_queue
;
6650 static int ixgbe_maybe_stop_tx(struct ixgbe_ring
*tx_ring
, int size
)
6652 if (likely(IXGBE_DESC_UNUSED(tx_ring
) >= size
))
6654 return __ixgbe_maybe_stop_tx(tx_ring
, size
);
6657 static u16
ixgbe_select_queue(struct net_device
*dev
, struct sk_buff
*skb
)
6659 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6660 int txq
= smp_processor_id();
6664 protocol
= vlan_get_protocol(skb
);
6666 if ((protocol
== htons(ETH_P_FCOE
)) ||
6667 (protocol
== htons(ETH_P_FIP
))) {
6668 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
6669 txq
&= (adapter
->ring_feature
[RING_F_FCOE
].indices
- 1);
6670 txq
+= adapter
->ring_feature
[RING_F_FCOE
].mask
;
6672 #ifdef CONFIG_IXGBE_DCB
6673 } else if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6674 txq
= adapter
->fcoe
.up
;
6681 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
6682 while (unlikely(txq
>= dev
->real_num_tx_queues
))
6683 txq
-= dev
->real_num_tx_queues
;
6687 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6688 if (skb
->priority
== TC_PRIO_CONTROL
)
6689 txq
= adapter
->ring_feature
[RING_F_DCB
].indices
-1;
6691 txq
= (skb
->vlan_tci
& IXGBE_TX_FLAGS_VLAN_PRIO_MASK
)
6696 return skb_tx_hash(dev
, skb
);
6699 netdev_tx_t
ixgbe_xmit_frame_ring(struct sk_buff
*skb
,
6700 struct ixgbe_adapter
*adapter
,
6701 struct ixgbe_ring
*tx_ring
)
6704 unsigned int tx_flags
= 0;
6711 protocol
= vlan_get_protocol(skb
);
6713 if (vlan_tx_tag_present(skb
)) {
6714 tx_flags
|= vlan_tx_tag_get(skb
);
6715 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6716 tx_flags
&= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK
;
6717 tx_flags
|= ((skb
->queue_mapping
& 0x7) << 13);
6719 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
6720 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
6721 } else if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
&&
6722 skb
->priority
!= TC_PRIO_CONTROL
) {
6723 tx_flags
|= ((skb
->queue_mapping
& 0x7) << 13);
6724 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
6725 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
6729 /* for FCoE with DCB, we force the priority to what
6730 * was specified by the switch */
6731 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
&&
6732 (protocol
== htons(ETH_P_FCOE
) ||
6733 protocol
== htons(ETH_P_FIP
))) {
6734 #ifdef CONFIG_IXGBE_DCB
6735 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6736 tx_flags
&= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6737 << IXGBE_TX_FLAGS_VLAN_SHIFT
);
6738 tx_flags
|= ((adapter
->fcoe
.up
<< 13)
6739 << IXGBE_TX_FLAGS_VLAN_SHIFT
);
6742 /* flag for FCoE offloads */
6743 if (protocol
== htons(ETH_P_FCOE
))
6744 tx_flags
|= IXGBE_TX_FLAGS_FCOE
;
6748 /* four things can cause us to need a context descriptor */
6749 if (skb_is_gso(skb
) ||
6750 (skb
->ip_summed
== CHECKSUM_PARTIAL
) ||
6751 (tx_flags
& IXGBE_TX_FLAGS_VLAN
) ||
6752 (tx_flags
& IXGBE_TX_FLAGS_FCOE
))
6755 count
+= TXD_USE_COUNT(skb_headlen(skb
));
6756 for (f
= 0; f
< skb_shinfo(skb
)->nr_frags
; f
++)
6757 count
+= TXD_USE_COUNT(skb_shinfo(skb
)->frags
[f
].size
);
6759 if (ixgbe_maybe_stop_tx(tx_ring
, count
)) {
6760 tx_ring
->tx_stats
.tx_busy
++;
6761 return NETDEV_TX_BUSY
;
6764 first
= tx_ring
->next_to_use
;
6765 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
6767 /* setup tx offload for FCoE */
6768 tso
= ixgbe_fso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
);
6770 dev_kfree_skb_any(skb
);
6771 return NETDEV_TX_OK
;
6774 tx_flags
|= IXGBE_TX_FLAGS_FSO
;
6775 #endif /* IXGBE_FCOE */
6777 if (protocol
== htons(ETH_P_IP
))
6778 tx_flags
|= IXGBE_TX_FLAGS_IPV4
;
6779 tso
= ixgbe_tso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
,
6782 dev_kfree_skb_any(skb
);
6783 return NETDEV_TX_OK
;
6787 tx_flags
|= IXGBE_TX_FLAGS_TSO
;
6788 else if (ixgbe_tx_csum(adapter
, tx_ring
, skb
, tx_flags
,
6790 (skb
->ip_summed
== CHECKSUM_PARTIAL
))
6791 tx_flags
|= IXGBE_TX_FLAGS_CSUM
;
6794 count
= ixgbe_tx_map(adapter
, tx_ring
, skb
, tx_flags
, first
, hdr_len
);
6796 /* add the ATR filter if ATR is on */
6797 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE
, &tx_ring
->state
))
6798 ixgbe_atr(tx_ring
, skb
, tx_flags
, protocol
);
6799 ixgbe_tx_queue(tx_ring
, tx_flags
, count
, skb
->len
, hdr_len
);
6800 ixgbe_maybe_stop_tx(tx_ring
, DESC_NEEDED
);
6803 dev_kfree_skb_any(skb
);
6804 tx_ring
->tx_buffer_info
[first
].time_stamp
= 0;
6805 tx_ring
->next_to_use
= first
;
6808 return NETDEV_TX_OK
;
6811 static netdev_tx_t
ixgbe_xmit_frame(struct sk_buff
*skb
, struct net_device
*netdev
)
6813 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6814 struct ixgbe_ring
*tx_ring
;
6816 tx_ring
= adapter
->tx_ring
[skb
->queue_mapping
];
6817 return ixgbe_xmit_frame_ring(skb
, adapter
, tx_ring
);
6821 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6822 * @netdev: network interface device structure
6823 * @p: pointer to an address structure
6825 * Returns 0 on success, negative on failure
6827 static int ixgbe_set_mac(struct net_device
*netdev
, void *p
)
6829 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6830 struct ixgbe_hw
*hw
= &adapter
->hw
;
6831 struct sockaddr
*addr
= p
;
6833 if (!is_valid_ether_addr(addr
->sa_data
))
6834 return -EADDRNOTAVAIL
;
6836 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
6837 memcpy(hw
->mac
.addr
, addr
->sa_data
, netdev
->addr_len
);
6839 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
6846 ixgbe_mdio_read(struct net_device
*netdev
, int prtad
, int devad
, u16 addr
)
6848 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6849 struct ixgbe_hw
*hw
= &adapter
->hw
;
6853 if (prtad
!= hw
->phy
.mdio
.prtad
)
6855 rc
= hw
->phy
.ops
.read_reg(hw
, addr
, devad
, &value
);
6861 static int ixgbe_mdio_write(struct net_device
*netdev
, int prtad
, int devad
,
6862 u16 addr
, u16 value
)
6864 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6865 struct ixgbe_hw
*hw
= &adapter
->hw
;
6867 if (prtad
!= hw
->phy
.mdio
.prtad
)
6869 return hw
->phy
.ops
.write_reg(hw
, addr
, devad
, value
);
6872 static int ixgbe_ioctl(struct net_device
*netdev
, struct ifreq
*req
, int cmd
)
6874 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6876 return mdio_mii_ioctl(&adapter
->hw
.phy
.mdio
, if_mii(req
), cmd
);
6880 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6882 * @netdev: network interface device structure
6884 * Returns non-zero on failure
6886 static int ixgbe_add_sanmac_netdev(struct net_device
*dev
)
6889 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6890 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
6892 if (is_valid_ether_addr(mac
->san_addr
)) {
6894 err
= dev_addr_add(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
6901 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6903 * @netdev: network interface device structure
6905 * Returns non-zero on failure
6907 static int ixgbe_del_sanmac_netdev(struct net_device
*dev
)
6910 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6911 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
6913 if (is_valid_ether_addr(mac
->san_addr
)) {
6915 err
= dev_addr_del(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
6921 #ifdef CONFIG_NET_POLL_CONTROLLER
6923 * Polling 'interrupt' - used by things like netconsole to send skbs
6924 * without having to re-enable interrupts. It's not called while
6925 * the interrupt routine is executing.
6927 static void ixgbe_netpoll(struct net_device
*netdev
)
6929 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6932 /* if interface is down do nothing */
6933 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
6936 adapter
->flags
|= IXGBE_FLAG_IN_NETPOLL
;
6937 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
6938 int num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
6939 for (i
= 0; i
< num_q_vectors
; i
++) {
6940 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
6941 ixgbe_msix_clean_many(0, q_vector
);
6944 ixgbe_intr(adapter
->pdev
->irq
, netdev
);
6946 adapter
->flags
&= ~IXGBE_FLAG_IN_NETPOLL
;
6950 static struct rtnl_link_stats64
*ixgbe_get_stats64(struct net_device
*netdev
,
6951 struct rtnl_link_stats64
*stats
)
6953 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6957 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
6958 struct ixgbe_ring
*ring
= ACCESS_ONCE(adapter
->rx_ring
[i
]);
6964 start
= u64_stats_fetch_begin_bh(&ring
->syncp
);
6965 packets
= ring
->stats
.packets
;
6966 bytes
= ring
->stats
.bytes
;
6967 } while (u64_stats_fetch_retry_bh(&ring
->syncp
, start
));
6968 stats
->rx_packets
+= packets
;
6969 stats
->rx_bytes
+= bytes
;
6973 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
6974 struct ixgbe_ring
*ring
= ACCESS_ONCE(adapter
->tx_ring
[i
]);
6980 start
= u64_stats_fetch_begin_bh(&ring
->syncp
);
6981 packets
= ring
->stats
.packets
;
6982 bytes
= ring
->stats
.bytes
;
6983 } while (u64_stats_fetch_retry_bh(&ring
->syncp
, start
));
6984 stats
->tx_packets
+= packets
;
6985 stats
->tx_bytes
+= bytes
;
6989 /* following stats updated by ixgbe_watchdog_task() */
6990 stats
->multicast
= netdev
->stats
.multicast
;
6991 stats
->rx_errors
= netdev
->stats
.rx_errors
;
6992 stats
->rx_length_errors
= netdev
->stats
.rx_length_errors
;
6993 stats
->rx_crc_errors
= netdev
->stats
.rx_crc_errors
;
6994 stats
->rx_missed_errors
= netdev
->stats
.rx_missed_errors
;
6999 static const struct net_device_ops ixgbe_netdev_ops
= {
7000 .ndo_open
= ixgbe_open
,
7001 .ndo_stop
= ixgbe_close
,
7002 .ndo_start_xmit
= ixgbe_xmit_frame
,
7003 .ndo_select_queue
= ixgbe_select_queue
,
7004 .ndo_set_rx_mode
= ixgbe_set_rx_mode
,
7005 .ndo_set_multicast_list
= ixgbe_set_rx_mode
,
7006 .ndo_validate_addr
= eth_validate_addr
,
7007 .ndo_set_mac_address
= ixgbe_set_mac
,
7008 .ndo_change_mtu
= ixgbe_change_mtu
,
7009 .ndo_tx_timeout
= ixgbe_tx_timeout
,
7010 .ndo_vlan_rx_add_vid
= ixgbe_vlan_rx_add_vid
,
7011 .ndo_vlan_rx_kill_vid
= ixgbe_vlan_rx_kill_vid
,
7012 .ndo_do_ioctl
= ixgbe_ioctl
,
7013 .ndo_set_vf_mac
= ixgbe_ndo_set_vf_mac
,
7014 .ndo_set_vf_vlan
= ixgbe_ndo_set_vf_vlan
,
7015 .ndo_set_vf_tx_rate
= ixgbe_ndo_set_vf_bw
,
7016 .ndo_get_vf_config
= ixgbe_ndo_get_vf_config
,
7017 .ndo_get_stats64
= ixgbe_get_stats64
,
7018 #ifdef CONFIG_NET_POLL_CONTROLLER
7019 .ndo_poll_controller
= ixgbe_netpoll
,
7022 .ndo_fcoe_ddp_setup
= ixgbe_fcoe_ddp_get
,
7023 .ndo_fcoe_ddp_target
= ixgbe_fcoe_ddp_target
,
7024 .ndo_fcoe_ddp_done
= ixgbe_fcoe_ddp_put
,
7025 .ndo_fcoe_enable
= ixgbe_fcoe_enable
,
7026 .ndo_fcoe_disable
= ixgbe_fcoe_disable
,
7027 .ndo_fcoe_get_wwn
= ixgbe_fcoe_get_wwn
,
7028 #endif /* IXGBE_FCOE */
7031 static void __devinit
ixgbe_probe_vf(struct ixgbe_adapter
*adapter
,
7032 const struct ixgbe_info
*ii
)
7034 #ifdef CONFIG_PCI_IOV
7035 struct ixgbe_hw
*hw
= &adapter
->hw
;
7038 if (hw
->mac
.type
== ixgbe_mac_82598EB
|| !max_vfs
)
7041 /* The 82599 supports up to 64 VFs per physical function
7042 * but this implementation limits allocation to 63 so that
7043 * basic networking resources are still available to the
7046 adapter
->num_vfs
= (max_vfs
> 63) ? 63 : max_vfs
;
7047 adapter
->flags
|= IXGBE_FLAG_SRIOV_ENABLED
;
7048 err
= pci_enable_sriov(adapter
->pdev
, adapter
->num_vfs
);
7050 e_err(probe
, "Failed to enable PCI sriov: %d\n", err
);
7053 /* If call to enable VFs succeeded then allocate memory
7054 * for per VF control structures.
7057 kcalloc(adapter
->num_vfs
,
7058 sizeof(struct vf_data_storage
), GFP_KERNEL
);
7059 if (adapter
->vfinfo
) {
7060 /* Now that we're sure SR-IOV is enabled
7061 * and memory allocated set up the mailbox parameters
7063 ixgbe_init_mbx_params_pf(hw
);
7064 memcpy(&hw
->mbx
.ops
, ii
->mbx_ops
,
7065 sizeof(hw
->mbx
.ops
));
7067 /* Disable RSC when in SR-IOV mode */
7068 adapter
->flags2
&= ~(IXGBE_FLAG2_RSC_CAPABLE
|
7069 IXGBE_FLAG2_RSC_ENABLED
);
7074 e_err(probe
, "Unable to allocate memory for VF Data Storage - "
7075 "SRIOV disabled\n");
7076 pci_disable_sriov(adapter
->pdev
);
7079 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
7080 adapter
->num_vfs
= 0;
7081 #endif /* CONFIG_PCI_IOV */
7085 * ixgbe_probe - Device Initialization Routine
7086 * @pdev: PCI device information struct
7087 * @ent: entry in ixgbe_pci_tbl
7089 * Returns 0 on success, negative on failure
7091 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7092 * The OS initialization, configuring of the adapter private structure,
7093 * and a hardware reset occur.
7095 static int __devinit
ixgbe_probe(struct pci_dev
*pdev
,
7096 const struct pci_device_id
*ent
)
7098 struct net_device
*netdev
;
7099 struct ixgbe_adapter
*adapter
= NULL
;
7100 struct ixgbe_hw
*hw
;
7101 const struct ixgbe_info
*ii
= ixgbe_info_tbl
[ent
->driver_data
];
7102 static int cards_found
;
7103 int i
, err
, pci_using_dac
;
7104 u8 part_str
[IXGBE_PBANUM_LENGTH
];
7105 unsigned int indices
= num_possible_cpus();
7111 /* Catch broken hardware that put the wrong VF device ID in
7112 * the PCIe SR-IOV capability.
7114 if (pdev
->is_virtfn
) {
7115 WARN(1, KERN_ERR
"%s (%hx:%hx) should not be a VF!\n",
7116 pci_name(pdev
), pdev
->vendor
, pdev
->device
);
7120 err
= pci_enable_device_mem(pdev
);
7124 if (!dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(64)) &&
7125 !dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(64))) {
7128 err
= dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(32));
7130 err
= dma_set_coherent_mask(&pdev
->dev
,
7134 "No usable DMA configuration, aborting\n");
7141 err
= pci_request_selected_regions(pdev
, pci_select_bars(pdev
,
7142 IORESOURCE_MEM
), ixgbe_driver_name
);
7145 "pci_request_selected_regions failed 0x%x\n", err
);
7149 pci_enable_pcie_error_reporting(pdev
);
7151 pci_set_master(pdev
);
7152 pci_save_state(pdev
);
7154 if (ii
->mac
== ixgbe_mac_82598EB
)
7155 indices
= min_t(unsigned int, indices
, IXGBE_MAX_RSS_INDICES
);
7157 indices
= min_t(unsigned int, indices
, IXGBE_MAX_FDIR_INDICES
);
7159 indices
= max_t(unsigned int, indices
, IXGBE_MAX_DCB_INDICES
);
7161 indices
+= min_t(unsigned int, num_possible_cpus(),
7162 IXGBE_MAX_FCOE_INDICES
);
7164 netdev
= alloc_etherdev_mq(sizeof(struct ixgbe_adapter
), indices
);
7167 goto err_alloc_etherdev
;
7170 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
7172 adapter
= netdev_priv(netdev
);
7173 pci_set_drvdata(pdev
, adapter
);
7175 adapter
->netdev
= netdev
;
7176 adapter
->pdev
= pdev
;
7179 adapter
->msg_enable
= (1 << DEFAULT_DEBUG_LEVEL_SHIFT
) - 1;
7181 hw
->hw_addr
= ioremap(pci_resource_start(pdev
, 0),
7182 pci_resource_len(pdev
, 0));
7188 for (i
= 1; i
<= 5; i
++) {
7189 if (pci_resource_len(pdev
, i
) == 0)
7193 netdev
->netdev_ops
= &ixgbe_netdev_ops
;
7194 ixgbe_set_ethtool_ops(netdev
);
7195 netdev
->watchdog_timeo
= 5 * HZ
;
7196 strncpy(netdev
->name
, pci_name(pdev
), sizeof(netdev
->name
) - 1);
7198 adapter
->bd_number
= cards_found
;
7201 memcpy(&hw
->mac
.ops
, ii
->mac_ops
, sizeof(hw
->mac
.ops
));
7202 hw
->mac
.type
= ii
->mac
;
7205 memcpy(&hw
->eeprom
.ops
, ii
->eeprom_ops
, sizeof(hw
->eeprom
.ops
));
7206 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
7207 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7208 if (!(eec
& (1 << 8)))
7209 hw
->eeprom
.ops
.read
= &ixgbe_read_eeprom_bit_bang_generic
;
7212 memcpy(&hw
->phy
.ops
, ii
->phy_ops
, sizeof(hw
->phy
.ops
));
7213 hw
->phy
.sfp_type
= ixgbe_sfp_type_unknown
;
7214 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7215 hw
->phy
.mdio
.prtad
= MDIO_PRTAD_NONE
;
7216 hw
->phy
.mdio
.mmds
= 0;
7217 hw
->phy
.mdio
.mode_support
= MDIO_SUPPORTS_C45
| MDIO_EMULATE_C22
;
7218 hw
->phy
.mdio
.dev
= netdev
;
7219 hw
->phy
.mdio
.mdio_read
= ixgbe_mdio_read
;
7220 hw
->phy
.mdio
.mdio_write
= ixgbe_mdio_write
;
7222 /* set up this timer and work struct before calling get_invariants
7223 * which might start the timer
7225 init_timer(&adapter
->sfp_timer
);
7226 adapter
->sfp_timer
.function
= ixgbe_sfp_timer
;
7227 adapter
->sfp_timer
.data
= (unsigned long) adapter
;
7229 INIT_WORK(&adapter
->sfp_task
, ixgbe_sfp_task
);
7231 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
7232 INIT_WORK(&adapter
->multispeed_fiber_task
, ixgbe_multispeed_fiber_task
);
7234 /* a new SFP+ module arrival, called from GPI SDP2 context */
7235 INIT_WORK(&adapter
->sfp_config_module_task
,
7236 ixgbe_sfp_config_module_task
);
7238 ii
->get_invariants(hw
);
7240 /* setup the private structure */
7241 err
= ixgbe_sw_init(adapter
);
7245 /* Make it possible the adapter to be woken up via WOL */
7246 switch (adapter
->hw
.mac
.type
) {
7247 case ixgbe_mac_82599EB
:
7248 case ixgbe_mac_X540
:
7249 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
7256 * If there is a fan on this device and it has failed log the
7259 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
7260 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
7261 if (esdp
& IXGBE_ESDP_SDP1
)
7262 e_crit(probe
, "Fan has stopped, replace the adapter\n");
7265 /* reset_hw fills in the perm_addr as well */
7266 hw
->phy
.reset_if_overtemp
= true;
7267 err
= hw
->mac
.ops
.reset_hw(hw
);
7268 hw
->phy
.reset_if_overtemp
= false;
7269 if (err
== IXGBE_ERR_SFP_NOT_PRESENT
&&
7270 hw
->mac
.type
== ixgbe_mac_82598EB
) {
7272 * Start a kernel thread to watch for a module to arrive.
7273 * Only do this for 82598, since 82599 will generate
7274 * interrupts on module arrival.
7276 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
7277 mod_timer(&adapter
->sfp_timer
,
7278 round_jiffies(jiffies
+ (2 * HZ
)));
7280 } else if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
7281 e_dev_err("failed to initialize because an unsupported SFP+ "
7282 "module type was detected.\n");
7283 e_dev_err("Reload the driver after installing a supported "
7287 e_dev_err("HW Init failed: %d\n", err
);
7291 ixgbe_probe_vf(adapter
, ii
);
7293 netdev
->features
= NETIF_F_SG
|
7295 NETIF_F_HW_VLAN_TX
|
7296 NETIF_F_HW_VLAN_RX
|
7297 NETIF_F_HW_VLAN_FILTER
;
7299 netdev
->features
|= NETIF_F_IPV6_CSUM
;
7300 netdev
->features
|= NETIF_F_TSO
;
7301 netdev
->features
|= NETIF_F_TSO6
;
7302 netdev
->features
|= NETIF_F_GRO
;
7304 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
7305 netdev
->features
|= NETIF_F_SCTP_CSUM
;
7307 netdev
->vlan_features
|= NETIF_F_TSO
;
7308 netdev
->vlan_features
|= NETIF_F_TSO6
;
7309 netdev
->vlan_features
|= NETIF_F_IP_CSUM
;
7310 netdev
->vlan_features
|= NETIF_F_IPV6_CSUM
;
7311 netdev
->vlan_features
|= NETIF_F_SG
;
7313 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
7314 adapter
->flags
&= ~(IXGBE_FLAG_RSS_ENABLED
|
7315 IXGBE_FLAG_DCB_ENABLED
);
7316 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)
7317 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
7319 #ifdef CONFIG_IXGBE_DCB
7320 netdev
->dcbnl_ops
= &dcbnl_ops
;
7324 if (adapter
->flags
& IXGBE_FLAG_FCOE_CAPABLE
) {
7325 if (hw
->mac
.ops
.get_device_caps
) {
7326 hw
->mac
.ops
.get_device_caps(hw
, &device_caps
);
7327 if (device_caps
& IXGBE_DEVICE_CAPS_FCOE_OFFLOADS
)
7328 adapter
->flags
&= ~IXGBE_FLAG_FCOE_CAPABLE
;
7331 if (adapter
->flags
& IXGBE_FLAG_FCOE_CAPABLE
) {
7332 netdev
->vlan_features
|= NETIF_F_FCOE_CRC
;
7333 netdev
->vlan_features
|= NETIF_F_FSO
;
7334 netdev
->vlan_features
|= NETIF_F_FCOE_MTU
;
7336 #endif /* IXGBE_FCOE */
7337 if (pci_using_dac
) {
7338 netdev
->features
|= NETIF_F_HIGHDMA
;
7339 netdev
->vlan_features
|= NETIF_F_HIGHDMA
;
7342 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
)
7343 netdev
->features
|= NETIF_F_LRO
;
7345 /* make sure the EEPROM is good */
7346 if (hw
->eeprom
.ops
.validate_checksum(hw
, NULL
) < 0) {
7347 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7352 memcpy(netdev
->dev_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
7353 memcpy(netdev
->perm_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
7355 if (ixgbe_validate_mac_addr(netdev
->perm_addr
)) {
7356 e_dev_err("invalid MAC address\n");
7361 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7362 if (hw
->mac
.ops
.disable_tx_laser
&&
7363 ((hw
->phy
.multispeed_fiber
) ||
7364 ((hw
->mac
.ops
.get_media_type(hw
) == ixgbe_media_type_fiber
) &&
7365 (hw
->mac
.type
== ixgbe_mac_82599EB
))))
7366 hw
->mac
.ops
.disable_tx_laser(hw
);
7368 init_timer(&adapter
->watchdog_timer
);
7369 adapter
->watchdog_timer
.function
= ixgbe_watchdog
;
7370 adapter
->watchdog_timer
.data
= (unsigned long)adapter
;
7372 INIT_WORK(&adapter
->reset_task
, ixgbe_reset_task
);
7373 INIT_WORK(&adapter
->watchdog_task
, ixgbe_watchdog_task
);
7375 err
= ixgbe_init_interrupt_scheme(adapter
);
7379 switch (pdev
->device
) {
7380 case IXGBE_DEV_ID_82599_SFP
:
7381 /* Only this subdevice supports WOL */
7382 if (pdev
->subsystem_device
== IXGBE_SUBDEV_ID_82599_SFP
)
7383 adapter
->wol
= (IXGBE_WUFC_MAG
| IXGBE_WUFC_EX
|
7384 IXGBE_WUFC_MC
| IXGBE_WUFC_BC
);
7386 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE
:
7387 /* All except this subdevice support WOL */
7388 if (pdev
->subsystem_device
!= IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ
)
7389 adapter
->wol
= (IXGBE_WUFC_MAG
| IXGBE_WUFC_EX
|
7390 IXGBE_WUFC_MC
| IXGBE_WUFC_BC
);
7392 case IXGBE_DEV_ID_82599_KX4
:
7393 adapter
->wol
= (IXGBE_WUFC_MAG
| IXGBE_WUFC_EX
|
7394 IXGBE_WUFC_MC
| IXGBE_WUFC_BC
);
7400 device_set_wakeup_enable(&adapter
->pdev
->dev
, adapter
->wol
);
7402 /* pick up the PCI bus settings for reporting later */
7403 hw
->mac
.ops
.get_bus_info(hw
);
7405 /* print bus type/speed/width info */
7406 e_dev_info("(PCI Express:%s:%s) %pM\n",
7407 (hw
->bus
.speed
== ixgbe_bus_speed_5000
? "5.0Gb/s" :
7408 hw
->bus
.speed
== ixgbe_bus_speed_2500
? "2.5Gb/s" :
7410 (hw
->bus
.width
== ixgbe_bus_width_pcie_x8
? "Width x8" :
7411 hw
->bus
.width
== ixgbe_bus_width_pcie_x4
? "Width x4" :
7412 hw
->bus
.width
== ixgbe_bus_width_pcie_x1
? "Width x1" :
7416 err
= ixgbe_read_pba_string_generic(hw
, part_str
, IXGBE_PBANUM_LENGTH
);
7418 strncpy(part_str
, "Unknown", IXGBE_PBANUM_LENGTH
);
7419 if (ixgbe_is_sfp(hw
) && hw
->phy
.sfp_type
!= ixgbe_sfp_type_not_present
)
7420 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7421 hw
->mac
.type
, hw
->phy
.type
, hw
->phy
.sfp_type
,
7424 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7425 hw
->mac
.type
, hw
->phy
.type
, part_str
);
7427 if (hw
->bus
.width
<= ixgbe_bus_width_pcie_x4
) {
7428 e_dev_warn("PCI-Express bandwidth available for this card is "
7429 "not sufficient for optimal performance.\n");
7430 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7434 /* save off EEPROM version number */
7435 hw
->eeprom
.ops
.read(hw
, 0x29, &adapter
->eeprom_version
);
7437 /* reset the hardware with the new settings */
7438 err
= hw
->mac
.ops
.start_hw(hw
);
7440 if (err
== IXGBE_ERR_EEPROM_VERSION
) {
7441 /* We are running on a pre-production device, log a warning */
7442 e_dev_warn("This device is a pre-production adapter/LOM. "
7443 "Please be aware there may be issues associated "
7444 "with your hardware. If you are experiencing "
7445 "problems please contact your Intel or hardware "
7446 "representative who provided you with this "
7449 strcpy(netdev
->name
, "eth%d");
7450 err
= register_netdev(netdev
);
7454 /* carrier off reporting is important to ethtool even BEFORE open */
7455 netif_carrier_off(netdev
);
7457 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
7458 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
7459 INIT_WORK(&adapter
->fdir_reinit_task
, ixgbe_fdir_reinit_task
);
7461 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
)
7462 INIT_WORK(&adapter
->check_overtemp_task
,
7463 ixgbe_check_overtemp_task
);
7464 #ifdef CONFIG_IXGBE_DCA
7465 if (dca_add_requester(&pdev
->dev
) == 0) {
7466 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
7467 ixgbe_setup_dca(adapter
);
7470 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
7471 e_info(probe
, "IOV is enabled with %d VFs\n", adapter
->num_vfs
);
7472 for (i
= 0; i
< adapter
->num_vfs
; i
++)
7473 ixgbe_vf_configuration(pdev
, (i
| 0x10000000));
7476 /* add san mac addr to netdev */
7477 ixgbe_add_sanmac_netdev(netdev
);
7479 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7484 ixgbe_release_hw_control(adapter
);
7485 ixgbe_clear_interrupt_scheme(adapter
);
7488 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
7489 ixgbe_disable_sriov(adapter
);
7490 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
7491 del_timer_sync(&adapter
->sfp_timer
);
7492 cancel_work_sync(&adapter
->sfp_task
);
7493 cancel_work_sync(&adapter
->multispeed_fiber_task
);
7494 cancel_work_sync(&adapter
->sfp_config_module_task
);
7495 iounmap(hw
->hw_addr
);
7497 free_netdev(netdev
);
7499 pci_release_selected_regions(pdev
,
7500 pci_select_bars(pdev
, IORESOURCE_MEM
));
7503 pci_disable_device(pdev
);
7508 * ixgbe_remove - Device Removal Routine
7509 * @pdev: PCI device information struct
7511 * ixgbe_remove is called by the PCI subsystem to alert the driver
7512 * that it should release a PCI device. The could be caused by a
7513 * Hot-Plug event, or because the driver is going to be removed from
7516 static void __devexit
ixgbe_remove(struct pci_dev
*pdev
)
7518 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7519 struct net_device
*netdev
= adapter
->netdev
;
7521 set_bit(__IXGBE_DOWN
, &adapter
->state
);
7524 * The timers may be rescheduled, so explicitly disable them
7525 * from being rescheduled.
7527 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
7528 del_timer_sync(&adapter
->watchdog_timer
);
7529 del_timer_sync(&adapter
->sfp_timer
);
7531 cancel_work_sync(&adapter
->watchdog_task
);
7532 cancel_work_sync(&adapter
->sfp_task
);
7533 cancel_work_sync(&adapter
->multispeed_fiber_task
);
7534 cancel_work_sync(&adapter
->sfp_config_module_task
);
7535 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
7536 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
7537 cancel_work_sync(&adapter
->fdir_reinit_task
);
7538 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
)
7539 cancel_work_sync(&adapter
->check_overtemp_task
);
7541 #ifdef CONFIG_IXGBE_DCA
7542 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
7543 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
7544 dca_remove_requester(&pdev
->dev
);
7545 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
7550 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
7551 ixgbe_cleanup_fcoe(adapter
);
7553 #endif /* IXGBE_FCOE */
7555 /* remove the added san mac */
7556 ixgbe_del_sanmac_netdev(netdev
);
7558 if (netdev
->reg_state
== NETREG_REGISTERED
)
7559 unregister_netdev(netdev
);
7561 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
7562 ixgbe_disable_sriov(adapter
);
7564 ixgbe_clear_interrupt_scheme(adapter
);
7566 ixgbe_release_hw_control(adapter
);
7568 iounmap(adapter
->hw
.hw_addr
);
7569 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
7572 e_dev_info("complete\n");
7574 free_netdev(netdev
);
7576 pci_disable_pcie_error_reporting(pdev
);
7578 pci_disable_device(pdev
);
7582 * ixgbe_io_error_detected - called when PCI error is detected
7583 * @pdev: Pointer to PCI device
7584 * @state: The current pci connection state
7586 * This function is called after a PCI bus error affecting
7587 * this device has been detected.
7589 static pci_ers_result_t
ixgbe_io_error_detected(struct pci_dev
*pdev
,
7590 pci_channel_state_t state
)
7592 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7593 struct net_device
*netdev
= adapter
->netdev
;
7595 netif_device_detach(netdev
);
7597 if (state
== pci_channel_io_perm_failure
)
7598 return PCI_ERS_RESULT_DISCONNECT
;
7600 if (netif_running(netdev
))
7601 ixgbe_down(adapter
);
7602 pci_disable_device(pdev
);
7604 /* Request a slot reset. */
7605 return PCI_ERS_RESULT_NEED_RESET
;
7609 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7610 * @pdev: Pointer to PCI device
7612 * Restart the card from scratch, as if from a cold-boot.
7614 static pci_ers_result_t
ixgbe_io_slot_reset(struct pci_dev
*pdev
)
7616 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7617 pci_ers_result_t result
;
7620 if (pci_enable_device_mem(pdev
)) {
7621 e_err(probe
, "Cannot re-enable PCI device after reset.\n");
7622 result
= PCI_ERS_RESULT_DISCONNECT
;
7624 pci_set_master(pdev
);
7625 pci_restore_state(pdev
);
7626 pci_save_state(pdev
);
7628 pci_wake_from_d3(pdev
, false);
7630 ixgbe_reset(adapter
);
7631 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
7632 result
= PCI_ERS_RESULT_RECOVERED
;
7635 err
= pci_cleanup_aer_uncorrect_error_status(pdev
);
7637 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7638 "failed 0x%0x\n", err
);
7639 /* non-fatal, continue */
7646 * ixgbe_io_resume - called when traffic can start flowing again.
7647 * @pdev: Pointer to PCI device
7649 * This callback is called when the error recovery driver tells us that
7650 * its OK to resume normal operation.
7652 static void ixgbe_io_resume(struct pci_dev
*pdev
)
7654 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7655 struct net_device
*netdev
= adapter
->netdev
;
7657 if (netif_running(netdev
)) {
7658 if (ixgbe_up(adapter
)) {
7659 e_info(probe
, "ixgbe_up failed after reset\n");
7664 netif_device_attach(netdev
);
7667 static struct pci_error_handlers ixgbe_err_handler
= {
7668 .error_detected
= ixgbe_io_error_detected
,
7669 .slot_reset
= ixgbe_io_slot_reset
,
7670 .resume
= ixgbe_io_resume
,
7673 static struct pci_driver ixgbe_driver
= {
7674 .name
= ixgbe_driver_name
,
7675 .id_table
= ixgbe_pci_tbl
,
7676 .probe
= ixgbe_probe
,
7677 .remove
= __devexit_p(ixgbe_remove
),
7679 .suspend
= ixgbe_suspend
,
7680 .resume
= ixgbe_resume
,
7682 .shutdown
= ixgbe_shutdown
,
7683 .err_handler
= &ixgbe_err_handler
7687 * ixgbe_init_module - Driver Registration Routine
7689 * ixgbe_init_module is the first routine called when the driver is
7690 * loaded. All it does is register with the PCI subsystem.
7692 static int __init
ixgbe_init_module(void)
7695 pr_info("%s - version %s\n", ixgbe_driver_string
, ixgbe_driver_version
);
7696 pr_info("%s\n", ixgbe_copyright
);
7698 #ifdef CONFIG_IXGBE_DCA
7699 dca_register_notify(&dca_notifier
);
7702 ret
= pci_register_driver(&ixgbe_driver
);
7706 module_init(ixgbe_init_module
);
7709 * ixgbe_exit_module - Driver Exit Cleanup Routine
7711 * ixgbe_exit_module is called just before the driver is removed
7714 static void __exit
ixgbe_exit_module(void)
7716 #ifdef CONFIG_IXGBE_DCA
7717 dca_unregister_notify(&dca_notifier
);
7719 pci_unregister_driver(&ixgbe_driver
);
7720 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7723 #ifdef CONFIG_IXGBE_DCA
7724 static int ixgbe_notify_dca(struct notifier_block
*nb
, unsigned long event
,
7729 ret_val
= driver_for_each_device(&ixgbe_driver
.driver
, NULL
, &event
,
7730 __ixgbe_notify_dca
);
7732 return ret_val
? NOTIFY_BAD
: NOTIFY_DONE
;
7735 #endif /* CONFIG_IXGBE_DCA */
7737 module_exit(ixgbe_exit_module
);