1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <linux/slab.h>
40 #include <net/checksum.h>
41 #include <net/ip6_checksum.h>
42 #include <linux/ethtool.h>
43 #include <linux/if_vlan.h>
44 #include <scsi/fc/fc_fcoe.h>
47 #include "ixgbe_common.h"
48 #include "ixgbe_dcb_82599.h"
49 #include "ixgbe_sriov.h"
51 char ixgbe_driver_name
[] = "ixgbe";
52 static const char ixgbe_driver_string
[] =
53 "Intel(R) 10 Gigabit PCI Express Network Driver";
55 #define DRV_VERSION "2.0.62-k2"
56 const char ixgbe_driver_version
[] = DRV_VERSION
;
57 static char ixgbe_copyright
[] = "Copyright (c) 1999-2010 Intel Corporation.";
59 static const struct ixgbe_info
*ixgbe_info_tbl
[] = {
60 [board_82598
] = &ixgbe_82598_info
,
61 [board_82599
] = &ixgbe_82599_info
,
64 /* ixgbe_pci_tbl - PCI Device ID Table
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl
) = {
73 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598
),
75 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_DUAL_PORT
),
77 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_SINGLE_PORT
),
79 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT
),
81 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT2
),
83 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_CX4
),
85 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_CX4_DUAL_PORT
),
87 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_DA_DUAL_PORT
),
89 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM
),
91 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_XF_LR
),
93 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_SFP_LOM
),
95 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_BX
),
97 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4
),
99 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_XAUI_LOM
),
101 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KR
),
103 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP
),
105 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP_EM
),
107 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4_MEZZ
),
109 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_CX4
),
111 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_COMBO_BACKPLANE
),
114 /* required last entry */
117 MODULE_DEVICE_TABLE(pci
, ixgbe_pci_tbl
);
119 #ifdef CONFIG_IXGBE_DCA
120 static int ixgbe_notify_dca(struct notifier_block
*, unsigned long event
,
122 static struct notifier_block dca_notifier
= {
123 .notifier_call
= ixgbe_notify_dca
,
129 #ifdef CONFIG_PCI_IOV
130 static unsigned int max_vfs
;
131 module_param(max_vfs
, uint
, 0);
132 MODULE_PARM_DESC(max_vfs
, "Maximum number of virtual functions to allocate "
133 "per physical function");
134 #endif /* CONFIG_PCI_IOV */
136 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
137 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
138 MODULE_LICENSE("GPL");
139 MODULE_VERSION(DRV_VERSION
);
141 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
143 static inline void ixgbe_disable_sriov(struct ixgbe_adapter
*adapter
)
145 struct ixgbe_hw
*hw
= &adapter
->hw
;
150 #ifdef CONFIG_PCI_IOV
151 /* disable iov and allow time for transactions to clear */
152 pci_disable_sriov(adapter
->pdev
);
155 /* turn off device IOV mode */
156 gcr
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
157 gcr
&= ~(IXGBE_GCR_EXT_SRIOV
);
158 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, gcr
);
159 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
160 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
161 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
163 /* set default pool back to 0 */
164 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
165 vmdctl
&= ~IXGBE_VT_CTL_POOL_MASK
;
166 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
);
168 /* take a breather then clean up driver data */
171 kfree(adapter
->vfinfo
);
172 adapter
->vfinfo
= NULL
;
174 adapter
->num_vfs
= 0;
175 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
178 struct ixgbe_reg_info
{
183 static const struct ixgbe_reg_info ixgbe_reg_info_tbl
[] = {
185 /* General Registers */
186 {IXGBE_CTRL
, "CTRL"},
187 {IXGBE_STATUS
, "STATUS"},
188 {IXGBE_CTRL_EXT
, "CTRL_EXT"},
190 /* Interrupt Registers */
191 {IXGBE_EICR
, "EICR"},
194 {IXGBE_SRRCTL(0), "SRRCTL"},
195 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
196 {IXGBE_RDLEN(0), "RDLEN"},
197 {IXGBE_RDH(0), "RDH"},
198 {IXGBE_RDT(0), "RDT"},
199 {IXGBE_RXDCTL(0), "RXDCTL"},
200 {IXGBE_RDBAL(0), "RDBAL"},
201 {IXGBE_RDBAH(0), "RDBAH"},
204 {IXGBE_TDBAL(0), "TDBAL"},
205 {IXGBE_TDBAH(0), "TDBAH"},
206 {IXGBE_TDLEN(0), "TDLEN"},
207 {IXGBE_TDH(0), "TDH"},
208 {IXGBE_TDT(0), "TDT"},
209 {IXGBE_TXDCTL(0), "TXDCTL"},
211 /* List Terminator */
217 * ixgbe_regdump - register printout routine
219 static void ixgbe_regdump(struct ixgbe_hw
*hw
, struct ixgbe_reg_info
*reginfo
)
225 switch (reginfo
->ofs
) {
226 case IXGBE_SRRCTL(0):
227 for (i
= 0; i
< 64; i
++)
228 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_SRRCTL(i
));
230 case IXGBE_DCA_RXCTRL(0):
231 for (i
= 0; i
< 64; i
++)
232 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_DCA_RXCTRL(i
));
235 for (i
= 0; i
< 64; i
++)
236 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDLEN(i
));
239 for (i
= 0; i
< 64; i
++)
240 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDH(i
));
243 for (i
= 0; i
< 64; i
++)
244 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDT(i
));
246 case IXGBE_RXDCTL(0):
247 for (i
= 0; i
< 64; i
++)
248 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RXDCTL(i
));
251 for (i
= 0; i
< 64; i
++)
252 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDBAL(i
));
255 for (i
= 0; i
< 64; i
++)
256 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDBAH(i
));
259 for (i
= 0; i
< 64; i
++)
260 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDBAL(i
));
263 for (i
= 0; i
< 64; i
++)
264 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDBAH(i
));
267 for (i
= 0; i
< 64; i
++)
268 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDLEN(i
));
271 for (i
= 0; i
< 64; i
++)
272 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDH(i
));
275 for (i
= 0; i
< 64; i
++)
276 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDT(i
));
278 case IXGBE_TXDCTL(0):
279 for (i
= 0; i
< 64; i
++)
280 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TXDCTL(i
));
283 printk(KERN_INFO
"%-15s %08x\n", reginfo
->name
,
284 IXGBE_READ_REG(hw
, reginfo
->ofs
));
288 for (i
= 0; i
< 8; i
++) {
289 snprintf(rname
, 16, "%s[%d-%d]", reginfo
->name
, i
*8, i
*8+7);
290 printk(KERN_ERR
"%-15s ", rname
);
291 for (j
= 0; j
< 8; j
++)
292 printk(KERN_CONT
"%08x ", regs
[i
*8+j
]);
293 printk(KERN_CONT
"\n");
299 * ixgbe_dump - Print registers, tx-rings and rx-rings
301 static void ixgbe_dump(struct ixgbe_adapter
*adapter
)
303 struct net_device
*netdev
= adapter
->netdev
;
304 struct ixgbe_hw
*hw
= &adapter
->hw
;
305 struct ixgbe_reg_info
*reginfo
;
307 struct ixgbe_ring
*tx_ring
;
308 struct ixgbe_tx_buffer
*tx_buffer_info
;
309 union ixgbe_adv_tx_desc
*tx_desc
;
310 struct my_u0
{ u64 a
; u64 b
; } *u0
;
311 struct ixgbe_ring
*rx_ring
;
312 union ixgbe_adv_rx_desc
*rx_desc
;
313 struct ixgbe_rx_buffer
*rx_buffer_info
;
317 if (!netif_msg_hw(adapter
))
320 /* Print netdevice Info */
322 dev_info(&adapter
->pdev
->dev
, "Net device Info\n");
323 printk(KERN_INFO
"Device Name state "
324 "trans_start last_rx\n");
325 printk(KERN_INFO
"%-15s %016lX %016lX %016lX\n",
332 /* Print Registers */
333 dev_info(&adapter
->pdev
->dev
, "Register Dump\n");
334 printk(KERN_INFO
" Register Name Value\n");
335 for (reginfo
= (struct ixgbe_reg_info
*)ixgbe_reg_info_tbl
;
336 reginfo
->name
; reginfo
++) {
337 ixgbe_regdump(hw
, reginfo
);
340 /* Print TX Ring Summary */
341 if (!netdev
|| !netif_running(netdev
))
344 dev_info(&adapter
->pdev
->dev
, "TX Rings Summary\n");
345 printk(KERN_INFO
"Queue [NTU] [NTC] [bi(ntc)->dma ] "
346 "leng ntw timestamp\n");
347 for (n
= 0; n
< adapter
->num_tx_queues
; n
++) {
348 tx_ring
= adapter
->tx_ring
[n
];
350 &tx_ring
->tx_buffer_info
[tx_ring
->next_to_clean
];
351 printk(KERN_INFO
" %5d %5X %5X %016llX %04X %3X %016llX\n",
352 n
, tx_ring
->next_to_use
, tx_ring
->next_to_clean
,
353 (u64
)tx_buffer_info
->dma
,
354 tx_buffer_info
->length
,
355 tx_buffer_info
->next_to_watch
,
356 (u64
)tx_buffer_info
->time_stamp
);
360 if (!netif_msg_tx_done(adapter
))
361 goto rx_ring_summary
;
363 dev_info(&adapter
->pdev
->dev
, "TX Rings Dump\n");
365 /* Transmit Descriptor Formats
367 * Advanced Transmit Descriptor
368 * +--------------------------------------------------------------+
369 * 0 | Buffer Address [63:0] |
370 * +--------------------------------------------------------------+
371 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
372 * +--------------------------------------------------------------+
373 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
376 for (n
= 0; n
< adapter
->num_tx_queues
; n
++) {
377 tx_ring
= adapter
->tx_ring
[n
];
378 printk(KERN_INFO
"------------------------------------\n");
379 printk(KERN_INFO
"TX QUEUE INDEX = %d\n", tx_ring
->queue_index
);
380 printk(KERN_INFO
"------------------------------------\n");
381 printk(KERN_INFO
"T [desc] [address 63:0 ] "
382 "[PlPOIdStDDt Ln] [bi->dma ] "
383 "leng ntw timestamp bi->skb\n");
385 for (i
= 0; tx_ring
->desc
&& (i
< tx_ring
->count
); i
++) {
386 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, i
);
387 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
388 u0
= (struct my_u0
*)tx_desc
;
389 printk(KERN_INFO
"T [0x%03X] %016llX %016llX %016llX"
390 " %04X %3X %016llX %p", i
,
393 (u64
)tx_buffer_info
->dma
,
394 tx_buffer_info
->length
,
395 tx_buffer_info
->next_to_watch
,
396 (u64
)tx_buffer_info
->time_stamp
,
397 tx_buffer_info
->skb
);
398 if (i
== tx_ring
->next_to_use
&&
399 i
== tx_ring
->next_to_clean
)
400 printk(KERN_CONT
" NTC/U\n");
401 else if (i
== tx_ring
->next_to_use
)
402 printk(KERN_CONT
" NTU\n");
403 else if (i
== tx_ring
->next_to_clean
)
404 printk(KERN_CONT
" NTC\n");
406 printk(KERN_CONT
"\n");
408 if (netif_msg_pktdata(adapter
) &&
409 tx_buffer_info
->dma
!= 0)
410 print_hex_dump(KERN_INFO
, "",
411 DUMP_PREFIX_ADDRESS
, 16, 1,
412 phys_to_virt(tx_buffer_info
->dma
),
413 tx_buffer_info
->length
, true);
417 /* Print RX Rings Summary */
419 dev_info(&adapter
->pdev
->dev
, "RX Rings Summary\n");
420 printk(KERN_INFO
"Queue [NTU] [NTC]\n");
421 for (n
= 0; n
< adapter
->num_rx_queues
; n
++) {
422 rx_ring
= adapter
->rx_ring
[n
];
423 printk(KERN_INFO
"%5d %5X %5X\n", n
,
424 rx_ring
->next_to_use
, rx_ring
->next_to_clean
);
428 if (!netif_msg_rx_status(adapter
))
431 dev_info(&adapter
->pdev
->dev
, "RX Rings Dump\n");
433 /* Advanced Receive Descriptor (Read) Format
435 * +-----------------------------------------------------+
436 * 0 | Packet Buffer Address [63:1] |A0/NSE|
437 * +----------------------------------------------+------+
438 * 8 | Header Buffer Address [63:1] | DD |
439 * +-----------------------------------------------------+
442 * Advanced Receive Descriptor (Write-Back) Format
444 * 63 48 47 32 31 30 21 20 16 15 4 3 0
445 * +------------------------------------------------------+
446 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
447 * | Checksum Ident | | | | Type | Type |
448 * +------------------------------------------------------+
449 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
450 * +------------------------------------------------------+
451 * 63 48 47 32 31 20 19 0
453 for (n
= 0; n
< adapter
->num_rx_queues
; n
++) {
454 rx_ring
= adapter
->rx_ring
[n
];
455 printk(KERN_INFO
"------------------------------------\n");
456 printk(KERN_INFO
"RX QUEUE INDEX = %d\n", rx_ring
->queue_index
);
457 printk(KERN_INFO
"------------------------------------\n");
458 printk(KERN_INFO
"R [desc] [ PktBuf A0] "
459 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
460 "<-- Adv Rx Read format\n");
461 printk(KERN_INFO
"RWB[desc] [PcsmIpSHl PtRs] "
462 "[vl er S cks ln] ---------------- [bi->skb] "
463 "<-- Adv Rx Write-Back format\n");
465 for (i
= 0; i
< rx_ring
->count
; i
++) {
466 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
467 rx_desc
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
468 u0
= (struct my_u0
*)rx_desc
;
469 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
470 if (staterr
& IXGBE_RXD_STAT_DD
) {
471 /* Descriptor Done */
472 printk(KERN_INFO
"RWB[0x%03X] %016llX "
473 "%016llX ---------------- %p", i
,
476 rx_buffer_info
->skb
);
478 printk(KERN_INFO
"R [0x%03X] %016llX "
479 "%016llX %016llX %p", i
,
482 (u64
)rx_buffer_info
->dma
,
483 rx_buffer_info
->skb
);
485 if (netif_msg_pktdata(adapter
)) {
486 print_hex_dump(KERN_INFO
, "",
487 DUMP_PREFIX_ADDRESS
, 16, 1,
488 phys_to_virt(rx_buffer_info
->dma
),
489 rx_ring
->rx_buf_len
, true);
491 if (rx_ring
->rx_buf_len
492 < IXGBE_RXBUFFER_2048
)
493 print_hex_dump(KERN_INFO
, "",
494 DUMP_PREFIX_ADDRESS
, 16, 1,
496 rx_buffer_info
->page_dma
+
497 rx_buffer_info
->page_offset
503 if (i
== rx_ring
->next_to_use
)
504 printk(KERN_CONT
" NTU\n");
505 else if (i
== rx_ring
->next_to_clean
)
506 printk(KERN_CONT
" NTC\n");
508 printk(KERN_CONT
"\n");
517 static void ixgbe_release_hw_control(struct ixgbe_adapter
*adapter
)
521 /* Let firmware take over control of h/w */
522 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
523 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
524 ctrl_ext
& ~IXGBE_CTRL_EXT_DRV_LOAD
);
527 static void ixgbe_get_hw_control(struct ixgbe_adapter
*adapter
)
531 /* Let firmware know the driver has taken over */
532 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
533 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
534 ctrl_ext
| IXGBE_CTRL_EXT_DRV_LOAD
);
538 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
539 * @adapter: pointer to adapter struct
540 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
541 * @queue: queue to map the corresponding interrupt to
542 * @msix_vector: the vector to map to the corresponding queue
545 static void ixgbe_set_ivar(struct ixgbe_adapter
*adapter
, s8 direction
,
546 u8 queue
, u8 msix_vector
)
549 struct ixgbe_hw
*hw
= &adapter
->hw
;
550 switch (hw
->mac
.type
) {
551 case ixgbe_mac_82598EB
:
552 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
555 index
= (((direction
* 64) + queue
) >> 2) & 0x1F;
556 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(index
));
557 ivar
&= ~(0xFF << (8 * (queue
& 0x3)));
558 ivar
|= (msix_vector
<< (8 * (queue
& 0x3)));
559 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(index
), ivar
);
561 case ixgbe_mac_82599EB
:
562 if (direction
== -1) {
564 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
565 index
= ((queue
& 1) * 8);
566 ivar
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_IVAR_MISC
);
567 ivar
&= ~(0xFF << index
);
568 ivar
|= (msix_vector
<< index
);
569 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_IVAR_MISC
, ivar
);
572 /* tx or rx causes */
573 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
574 index
= ((16 * (queue
& 1)) + (8 * direction
));
575 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(queue
>> 1));
576 ivar
&= ~(0xFF << index
);
577 ivar
|= (msix_vector
<< index
);
578 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(queue
>> 1), ivar
);
586 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter
*adapter
,
591 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
592 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
593 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS
, mask
);
595 mask
= (qmask
& 0xFFFFFFFF);
596 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(0), mask
);
597 mask
= (qmask
>> 32);
598 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(1), mask
);
602 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter
*adapter
,
603 struct ixgbe_tx_buffer
606 if (tx_buffer_info
->dma
) {
607 if (tx_buffer_info
->mapped_as_page
)
608 dma_unmap_page(&adapter
->pdev
->dev
,
610 tx_buffer_info
->length
,
613 dma_unmap_single(&adapter
->pdev
->dev
,
615 tx_buffer_info
->length
,
617 tx_buffer_info
->dma
= 0;
619 if (tx_buffer_info
->skb
) {
620 dev_kfree_skb_any(tx_buffer_info
->skb
);
621 tx_buffer_info
->skb
= NULL
;
623 tx_buffer_info
->time_stamp
= 0;
624 /* tx_buffer_info must be completely set up in the transmit path */
628 * ixgbe_tx_is_paused - check if the tx ring is paused
629 * @adapter: the ixgbe adapter
630 * @tx_ring: the corresponding tx_ring
632 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
633 * corresponding TC of this tx_ring when checking TFCS.
635 * Returns : true if paused
637 static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter
*adapter
,
638 struct ixgbe_ring
*tx_ring
)
640 u32 txoff
= IXGBE_TFCS_TXOFF
;
642 #ifdef CONFIG_IXGBE_DCB
643 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
645 int reg_idx
= tx_ring
->reg_idx
;
646 int dcb_i
= adapter
->ring_feature
[RING_F_DCB
].indices
;
648 switch (adapter
->hw
.mac
.type
) {
649 case ixgbe_mac_82598EB
:
651 txoff
= IXGBE_TFCS_TXOFF0
;
653 case ixgbe_mac_82599EB
:
655 txoff
= IXGBE_TFCS_TXOFF
;
659 if (tc
== 2) /* TC2, TC3 */
660 tc
+= (reg_idx
- 64) >> 4;
661 else if (tc
== 3) /* TC4, TC5, TC6, TC7 */
662 tc
+= 1 + ((reg_idx
- 96) >> 3);
663 } else if (dcb_i
== 4) {
667 tc
+= (reg_idx
- 64) >> 5;
668 if (tc
== 2) /* TC2, TC3 */
669 tc
+= (reg_idx
- 96) >> 4;
679 return IXGBE_READ_REG(&adapter
->hw
, IXGBE_TFCS
) & txoff
;
682 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter
*adapter
,
683 struct ixgbe_ring
*tx_ring
,
686 struct ixgbe_hw
*hw
= &adapter
->hw
;
688 /* Detect a transmit hang in hardware, this serializes the
689 * check with the clearing of time_stamp and movement of eop */
690 adapter
->detect_tx_hung
= false;
691 if (tx_ring
->tx_buffer_info
[eop
].time_stamp
&&
692 time_after(jiffies
, tx_ring
->tx_buffer_info
[eop
].time_stamp
+ HZ
) &&
693 !ixgbe_tx_is_paused(adapter
, tx_ring
)) {
694 /* detected Tx unit hang */
695 union ixgbe_adv_tx_desc
*tx_desc
;
696 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, eop
);
697 DPRINTK(DRV
, ERR
, "Detected Tx Unit Hang\n"
699 " TDH, TDT <%x>, <%x>\n"
700 " next_to_use <%x>\n"
701 " next_to_clean <%x>\n"
702 "tx_buffer_info[next_to_clean]\n"
703 " time_stamp <%lx>\n"
705 tx_ring
->queue_index
,
706 IXGBE_READ_REG(hw
, tx_ring
->head
),
707 IXGBE_READ_REG(hw
, tx_ring
->tail
),
708 tx_ring
->next_to_use
, eop
,
709 tx_ring
->tx_buffer_info
[eop
].time_stamp
, jiffies
);
716 #define IXGBE_MAX_TXD_PWR 14
717 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
719 /* Tx Descriptors needed, worst case */
720 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
721 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
722 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
723 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
725 static void ixgbe_tx_timeout(struct net_device
*netdev
);
728 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
729 * @q_vector: structure containing interrupt and ring information
730 * @tx_ring: tx ring to clean
732 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector
*q_vector
,
733 struct ixgbe_ring
*tx_ring
)
735 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
736 struct net_device
*netdev
= adapter
->netdev
;
737 union ixgbe_adv_tx_desc
*tx_desc
, *eop_desc
;
738 struct ixgbe_tx_buffer
*tx_buffer_info
;
739 unsigned int i
, eop
, count
= 0;
740 unsigned int total_bytes
= 0, total_packets
= 0;
742 i
= tx_ring
->next_to_clean
;
743 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
744 eop_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, eop
);
746 while ((eop_desc
->wb
.status
& cpu_to_le32(IXGBE_TXD_STAT_DD
)) &&
747 (count
< tx_ring
->work_limit
)) {
748 bool cleaned
= false;
749 for ( ; !cleaned
; count
++) {
751 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, i
);
752 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
753 cleaned
= (i
== eop
);
754 skb
= tx_buffer_info
->skb
;
756 if (cleaned
&& skb
) {
757 unsigned int segs
, bytecount
;
758 unsigned int hlen
= skb_headlen(skb
);
760 /* gso_segs is currently only valid for tcp */
761 segs
= skb_shinfo(skb
)->gso_segs
?: 1;
763 /* adjust for FCoE Sequence Offload */
764 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
765 && (skb
->protocol
== htons(ETH_P_FCOE
)) &&
767 hlen
= skb_transport_offset(skb
) +
768 sizeof(struct fc_frame_header
) +
769 sizeof(struct fcoe_crc_eof
);
770 segs
= DIV_ROUND_UP(skb
->len
- hlen
,
771 skb_shinfo(skb
)->gso_size
);
773 #endif /* IXGBE_FCOE */
774 /* multiply data chunks by size of headers */
775 bytecount
= ((segs
- 1) * hlen
) + skb
->len
;
776 total_packets
+= segs
;
777 total_bytes
+= bytecount
;
780 ixgbe_unmap_and_free_tx_resource(adapter
,
783 tx_desc
->wb
.status
= 0;
786 if (i
== tx_ring
->count
)
790 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
791 eop_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, eop
);
794 tx_ring
->next_to_clean
= i
;
796 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
797 if (unlikely(count
&& netif_carrier_ok(netdev
) &&
798 (IXGBE_DESC_UNUSED(tx_ring
) >= TX_WAKE_THRESHOLD
))) {
799 /* Make sure that anybody stopping the queue after this
800 * sees the new next_to_clean.
803 if (__netif_subqueue_stopped(netdev
, tx_ring
->queue_index
) &&
804 !test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
805 netif_wake_subqueue(netdev
, tx_ring
->queue_index
);
806 ++tx_ring
->restart_queue
;
810 if (adapter
->detect_tx_hung
) {
811 if (ixgbe_check_tx_hang(adapter
, tx_ring
, i
)) {
812 /* schedule immediate reset if we believe we hung */
814 "tx hang %d detected, resetting adapter\n",
815 adapter
->tx_timeout_count
+ 1);
816 ixgbe_tx_timeout(adapter
->netdev
);
820 /* re-arm the interrupt */
821 if (count
>= tx_ring
->work_limit
)
822 ixgbe_irq_rearm_queues(adapter
, ((u64
)1 << q_vector
->v_idx
));
824 tx_ring
->total_bytes
+= total_bytes
;
825 tx_ring
->total_packets
+= total_packets
;
826 tx_ring
->stats
.packets
+= total_packets
;
827 tx_ring
->stats
.bytes
+= total_bytes
;
828 return (count
< tx_ring
->work_limit
);
831 #ifdef CONFIG_IXGBE_DCA
832 static void ixgbe_update_rx_dca(struct ixgbe_adapter
*adapter
,
833 struct ixgbe_ring
*rx_ring
)
837 int q
= rx_ring
->reg_idx
;
839 if (rx_ring
->cpu
!= cpu
) {
840 rxctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_DCA_RXCTRL(q
));
841 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
842 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK
;
843 rxctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
844 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
845 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599
;
846 rxctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
847 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599
);
849 rxctrl
|= IXGBE_DCA_RXCTRL_DESC_DCA_EN
;
850 rxctrl
|= IXGBE_DCA_RXCTRL_HEAD_DCA_EN
;
851 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN
);
852 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN
|
853 IXGBE_DCA_RXCTRL_DESC_HSRO_EN
);
854 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_RXCTRL(q
), rxctrl
);
860 static void ixgbe_update_tx_dca(struct ixgbe_adapter
*adapter
,
861 struct ixgbe_ring
*tx_ring
)
865 int q
= tx_ring
->reg_idx
;
866 struct ixgbe_hw
*hw
= &adapter
->hw
;
868 if (tx_ring
->cpu
!= cpu
) {
869 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
870 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL(q
));
871 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK
;
872 txctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
873 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
874 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL(q
), txctrl
);
875 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
876 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL_82599(q
));
877 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599
;
878 txctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
879 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599
);
880 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
881 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL_82599(q
), txctrl
);
888 static void ixgbe_setup_dca(struct ixgbe_adapter
*adapter
)
892 if (!(adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
))
895 /* always use CB2 mode, difference is masked in the CB driver */
896 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 2);
898 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
899 adapter
->tx_ring
[i
]->cpu
= -1;
900 ixgbe_update_tx_dca(adapter
, adapter
->tx_ring
[i
]);
902 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
903 adapter
->rx_ring
[i
]->cpu
= -1;
904 ixgbe_update_rx_dca(adapter
, adapter
->rx_ring
[i
]);
908 static int __ixgbe_notify_dca(struct device
*dev
, void *data
)
910 struct net_device
*netdev
= dev_get_drvdata(dev
);
911 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
912 unsigned long event
= *(unsigned long *)data
;
915 case DCA_PROVIDER_ADD
:
916 /* if we're already enabled, don't do it again */
917 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
919 if (dca_add_requester(dev
) == 0) {
920 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
921 ixgbe_setup_dca(adapter
);
924 /* Fall Through since DCA is disabled. */
925 case DCA_PROVIDER_REMOVE
:
926 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
927 dca_remove_requester(dev
);
928 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
929 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
937 #endif /* CONFIG_IXGBE_DCA */
939 * ixgbe_receive_skb - Send a completed packet up the stack
940 * @adapter: board private structure
941 * @skb: packet to send up
942 * @status: hardware indication of status of receive
943 * @rx_ring: rx descriptor ring (for a specific queue) to setup
944 * @rx_desc: rx descriptor
946 static void ixgbe_receive_skb(struct ixgbe_q_vector
*q_vector
,
947 struct sk_buff
*skb
, u8 status
,
948 struct ixgbe_ring
*ring
,
949 union ixgbe_adv_rx_desc
*rx_desc
)
951 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
952 struct napi_struct
*napi
= &q_vector
->napi
;
953 bool is_vlan
= (status
& IXGBE_RXD_STAT_VP
);
954 u16 tag
= le16_to_cpu(rx_desc
->wb
.upper
.vlan
);
956 skb_record_rx_queue(skb
, ring
->queue_index
);
957 if (!(adapter
->flags
& IXGBE_FLAG_IN_NETPOLL
)) {
958 if (adapter
->vlgrp
&& is_vlan
&& (tag
& VLAN_VID_MASK
))
959 vlan_gro_receive(napi
, adapter
->vlgrp
, tag
, skb
);
961 napi_gro_receive(napi
, skb
);
963 if (adapter
->vlgrp
&& is_vlan
&& (tag
& VLAN_VID_MASK
))
964 vlan_hwaccel_rx(skb
, adapter
->vlgrp
, tag
);
971 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
972 * @adapter: address of board private structure
973 * @status_err: hardware indication of status of receive
974 * @skb: skb currently being received and modified
976 static inline void ixgbe_rx_checksum(struct ixgbe_adapter
*adapter
,
977 union ixgbe_adv_rx_desc
*rx_desc
,
980 u32 status_err
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
982 skb
->ip_summed
= CHECKSUM_NONE
;
984 /* Rx csum disabled */
985 if (!(adapter
->flags
& IXGBE_FLAG_RX_CSUM_ENABLED
))
988 /* if IP and error */
989 if ((status_err
& IXGBE_RXD_STAT_IPCS
) &&
990 (status_err
& IXGBE_RXDADV_ERR_IPE
)) {
991 adapter
->hw_csum_rx_error
++;
995 if (!(status_err
& IXGBE_RXD_STAT_L4CS
))
998 if (status_err
& IXGBE_RXDADV_ERR_TCPE
) {
999 u16 pkt_info
= rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
1002 * 82599 errata, UDP frames with a 0 checksum can be marked as
1005 if ((pkt_info
& IXGBE_RXDADV_PKTTYPE_UDP
) &&
1006 (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
))
1009 adapter
->hw_csum_rx_error
++;
1013 /* It must be a TCP or UDP packet with a valid checksum */
1014 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1017 static inline void ixgbe_release_rx_desc(struct ixgbe_hw
*hw
,
1018 struct ixgbe_ring
*rx_ring
, u32 val
)
1021 * Force memory writes to complete before letting h/w
1022 * know there are new descriptors to fetch. (Only
1023 * applicable for weak-ordered memory model archs,
1027 IXGBE_WRITE_REG(hw
, IXGBE_RDT(rx_ring
->reg_idx
), val
);
1031 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1032 * @adapter: address of board private structure
1034 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter
*adapter
,
1035 struct ixgbe_ring
*rx_ring
,
1038 struct pci_dev
*pdev
= adapter
->pdev
;
1039 union ixgbe_adv_rx_desc
*rx_desc
;
1040 struct ixgbe_rx_buffer
*bi
;
1043 i
= rx_ring
->next_to_use
;
1044 bi
= &rx_ring
->rx_buffer_info
[i
];
1046 while (cleaned_count
--) {
1047 rx_desc
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
1049 if (!bi
->page_dma
&&
1050 (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
)) {
1052 bi
->page
= alloc_page(GFP_ATOMIC
);
1054 adapter
->alloc_rx_page_failed
++;
1057 bi
->page_offset
= 0;
1059 /* use a half page if we're re-using */
1060 bi
->page_offset
^= (PAGE_SIZE
/ 2);
1063 bi
->page_dma
= dma_map_page(&pdev
->dev
, bi
->page
,
1070 struct sk_buff
*skb
;
1071 /* netdev_alloc_skb reserves 32 bytes up front!! */
1072 uint bufsz
= rx_ring
->rx_buf_len
+ SMP_CACHE_BYTES
;
1073 skb
= netdev_alloc_skb(adapter
->netdev
, bufsz
);
1076 adapter
->alloc_rx_buff_failed
++;
1080 /* advance the data pointer to the next cache line */
1081 skb_reserve(skb
, (PTR_ALIGN(skb
->data
, SMP_CACHE_BYTES
)
1085 bi
->dma
= dma_map_single(&pdev
->dev
, skb
->data
,
1086 rx_ring
->rx_buf_len
,
1089 /* Refresh the desc even if buffer_addrs didn't change because
1090 * each write-back erases this info. */
1091 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
1092 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->page_dma
);
1093 rx_desc
->read
.hdr_addr
= cpu_to_le64(bi
->dma
);
1095 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->dma
);
1099 if (i
== rx_ring
->count
)
1101 bi
= &rx_ring
->rx_buffer_info
[i
];
1105 if (rx_ring
->next_to_use
!= i
) {
1106 rx_ring
->next_to_use
= i
;
1108 i
= (rx_ring
->count
- 1);
1110 ixgbe_release_rx_desc(&adapter
->hw
, rx_ring
, i
);
1114 static inline u16
ixgbe_get_hdr_info(union ixgbe_adv_rx_desc
*rx_desc
)
1116 return rx_desc
->wb
.lower
.lo_dword
.hs_rss
.hdr_info
;
1119 static inline u16
ixgbe_get_pkt_info(union ixgbe_adv_rx_desc
*rx_desc
)
1121 return rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
1124 static inline u32
ixgbe_get_rsc_count(union ixgbe_adv_rx_desc
*rx_desc
)
1126 return (le32_to_cpu(rx_desc
->wb
.lower
.lo_dword
.data
) &
1127 IXGBE_RXDADV_RSCCNT_MASK
) >>
1128 IXGBE_RXDADV_RSCCNT_SHIFT
;
1132 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1133 * @skb: pointer to the last skb in the rsc queue
1134 * @count: pointer to number of packets coalesced in this context
1136 * This function changes a queue full of hw rsc buffers into a completed
1137 * packet. It uses the ->prev pointers to find the first packet and then
1138 * turns it into the frag list owner.
1140 static inline struct sk_buff
*ixgbe_transform_rsc_queue(struct sk_buff
*skb
,
1143 unsigned int frag_list_size
= 0;
1146 struct sk_buff
*prev
= skb
->prev
;
1147 frag_list_size
+= skb
->len
;
1153 skb_shinfo(skb
)->frag_list
= skb
->next
;
1155 skb
->len
+= frag_list_size
;
1156 skb
->data_len
+= frag_list_size
;
1157 skb
->truesize
+= frag_list_size
;
1161 struct ixgbe_rsc_cb
{
1166 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1168 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector
*q_vector
,
1169 struct ixgbe_ring
*rx_ring
,
1170 int *work_done
, int work_to_do
)
1172 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1173 struct net_device
*netdev
= adapter
->netdev
;
1174 struct pci_dev
*pdev
= adapter
->pdev
;
1175 union ixgbe_adv_rx_desc
*rx_desc
, *next_rxd
;
1176 struct ixgbe_rx_buffer
*rx_buffer_info
, *next_buffer
;
1177 struct sk_buff
*skb
;
1178 unsigned int i
, rsc_count
= 0;
1181 bool cleaned
= false;
1182 int cleaned_count
= 0;
1183 unsigned int total_rx_bytes
= 0, total_rx_packets
= 0;
1186 #endif /* IXGBE_FCOE */
1188 i
= rx_ring
->next_to_clean
;
1189 rx_desc
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
1190 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1191 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
1193 while (staterr
& IXGBE_RXD_STAT_DD
) {
1195 if (*work_done
>= work_to_do
)
1199 rmb(); /* read descriptor and rx_buffer_info after status DD */
1200 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
1201 hdr_info
= le16_to_cpu(ixgbe_get_hdr_info(rx_desc
));
1202 len
= (hdr_info
& IXGBE_RXDADV_HDRBUFLEN_MASK
) >>
1203 IXGBE_RXDADV_HDRBUFLEN_SHIFT
;
1204 upper_len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1205 if ((len
> IXGBE_RX_HDR_SIZE
) ||
1206 (upper_len
&& !(hdr_info
& IXGBE_RXDADV_SPH
)))
1207 len
= IXGBE_RX_HDR_SIZE
;
1209 len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1213 skb
= rx_buffer_info
->skb
;
1214 prefetch(skb
->data
);
1215 rx_buffer_info
->skb
= NULL
;
1217 if (rx_buffer_info
->dma
) {
1218 if ((adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) &&
1219 (!(staterr
& IXGBE_RXD_STAT_EOP
)) &&
1222 * When HWRSC is enabled, delay unmapping
1223 * of the first packet. It carries the
1224 * header information, HW may still
1225 * access the header after the writeback.
1226 * Only unmap it when EOP is reached
1228 IXGBE_RSC_CB(skb
)->delay_unmap
= true;
1229 IXGBE_RSC_CB(skb
)->dma
= rx_buffer_info
->dma
;
1231 dma_unmap_single(&pdev
->dev
,
1232 rx_buffer_info
->dma
,
1233 rx_ring
->rx_buf_len
,
1236 rx_buffer_info
->dma
= 0;
1241 dma_unmap_page(&pdev
->dev
, rx_buffer_info
->page_dma
,
1242 PAGE_SIZE
/ 2, DMA_FROM_DEVICE
);
1243 rx_buffer_info
->page_dma
= 0;
1244 skb_fill_page_desc(skb
, skb_shinfo(skb
)->nr_frags
,
1245 rx_buffer_info
->page
,
1246 rx_buffer_info
->page_offset
,
1249 if ((rx_ring
->rx_buf_len
> (PAGE_SIZE
/ 2)) ||
1250 (page_count(rx_buffer_info
->page
) != 1))
1251 rx_buffer_info
->page
= NULL
;
1253 get_page(rx_buffer_info
->page
);
1255 skb
->len
+= upper_len
;
1256 skb
->data_len
+= upper_len
;
1257 skb
->truesize
+= upper_len
;
1261 if (i
== rx_ring
->count
)
1264 next_rxd
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
1268 if (adapter
->flags2
& IXGBE_FLAG2_RSC_CAPABLE
)
1269 rsc_count
= ixgbe_get_rsc_count(rx_desc
);
1272 u32 nextp
= (staterr
& IXGBE_RXDADV_NEXTP_MASK
) >>
1273 IXGBE_RXDADV_NEXTP_SHIFT
;
1274 next_buffer
= &rx_ring
->rx_buffer_info
[nextp
];
1276 next_buffer
= &rx_ring
->rx_buffer_info
[i
];
1279 if (staterr
& IXGBE_RXD_STAT_EOP
) {
1281 skb
= ixgbe_transform_rsc_queue(skb
, &(rx_ring
->rsc_count
));
1282 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
1283 if (IXGBE_RSC_CB(skb
)->delay_unmap
) {
1284 dma_unmap_single(&pdev
->dev
,
1285 IXGBE_RSC_CB(skb
)->dma
,
1286 rx_ring
->rx_buf_len
,
1288 IXGBE_RSC_CB(skb
)->dma
= 0;
1289 IXGBE_RSC_CB(skb
)->delay_unmap
= false;
1291 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
)
1292 rx_ring
->rsc_count
+= skb_shinfo(skb
)->nr_frags
;
1294 rx_ring
->rsc_count
++;
1295 rx_ring
->rsc_flush
++;
1297 rx_ring
->stats
.packets
++;
1298 rx_ring
->stats
.bytes
+= skb
->len
;
1300 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
1301 rx_buffer_info
->skb
= next_buffer
->skb
;
1302 rx_buffer_info
->dma
= next_buffer
->dma
;
1303 next_buffer
->skb
= skb
;
1304 next_buffer
->dma
= 0;
1306 skb
->next
= next_buffer
->skb
;
1307 skb
->next
->prev
= skb
;
1309 rx_ring
->non_eop_descs
++;
1313 if (staterr
& IXGBE_RXDADV_ERR_FRAME_ERR_MASK
) {
1314 dev_kfree_skb_irq(skb
);
1318 ixgbe_rx_checksum(adapter
, rx_desc
, skb
);
1320 /* probably a little skewed due to removing CRC */
1321 total_rx_bytes
+= skb
->len
;
1324 skb
->protocol
= eth_type_trans(skb
, adapter
->netdev
);
1326 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1327 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
1328 ddp_bytes
= ixgbe_fcoe_ddp(adapter
, rx_desc
, skb
);
1332 #endif /* IXGBE_FCOE */
1333 ixgbe_receive_skb(q_vector
, skb
, staterr
, rx_ring
, rx_desc
);
1336 rx_desc
->wb
.upper
.status_error
= 0;
1338 /* return some buffers to hardware, one at a time is too slow */
1339 if (cleaned_count
>= IXGBE_RX_BUFFER_WRITE
) {
1340 ixgbe_alloc_rx_buffers(adapter
, rx_ring
, cleaned_count
);
1344 /* use prefetched values */
1346 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
1348 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1351 rx_ring
->next_to_clean
= i
;
1352 cleaned_count
= IXGBE_DESC_UNUSED(rx_ring
);
1355 ixgbe_alloc_rx_buffers(adapter
, rx_ring
, cleaned_count
);
1358 /* include DDPed FCoE data */
1359 if (ddp_bytes
> 0) {
1362 mss
= adapter
->netdev
->mtu
- sizeof(struct fcoe_hdr
) -
1363 sizeof(struct fc_frame_header
) -
1364 sizeof(struct fcoe_crc_eof
);
1367 total_rx_bytes
+= ddp_bytes
;
1368 total_rx_packets
+= DIV_ROUND_UP(ddp_bytes
, mss
);
1370 #endif /* IXGBE_FCOE */
1372 rx_ring
->total_packets
+= total_rx_packets
;
1373 rx_ring
->total_bytes
+= total_rx_bytes
;
1374 netdev
->stats
.rx_bytes
+= total_rx_bytes
;
1375 netdev
->stats
.rx_packets
+= total_rx_packets
;
1380 static int ixgbe_clean_rxonly(struct napi_struct
*, int);
1382 * ixgbe_configure_msix - Configure MSI-X hardware
1383 * @adapter: board private structure
1385 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1388 static void ixgbe_configure_msix(struct ixgbe_adapter
*adapter
)
1390 struct ixgbe_q_vector
*q_vector
;
1391 int i
, j
, q_vectors
, v_idx
, r_idx
;
1394 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1397 * Populate the IVAR table and set the ITR values to the
1398 * corresponding register.
1400 for (v_idx
= 0; v_idx
< q_vectors
; v_idx
++) {
1401 q_vector
= adapter
->q_vector
[v_idx
];
1402 /* XXX for_each_set_bit(...) */
1403 r_idx
= find_first_bit(q_vector
->rxr_idx
,
1404 adapter
->num_rx_queues
);
1406 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1407 j
= adapter
->rx_ring
[r_idx
]->reg_idx
;
1408 ixgbe_set_ivar(adapter
, 0, j
, v_idx
);
1409 r_idx
= find_next_bit(q_vector
->rxr_idx
,
1410 adapter
->num_rx_queues
,
1413 r_idx
= find_first_bit(q_vector
->txr_idx
,
1414 adapter
->num_tx_queues
);
1416 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1417 j
= adapter
->tx_ring
[r_idx
]->reg_idx
;
1418 ixgbe_set_ivar(adapter
, 1, j
, v_idx
);
1419 r_idx
= find_next_bit(q_vector
->txr_idx
,
1420 adapter
->num_tx_queues
,
1424 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
1426 q_vector
->eitr
= adapter
->tx_eitr_param
;
1427 else if (q_vector
->rxr_count
)
1429 q_vector
->eitr
= adapter
->rx_eitr_param
;
1431 ixgbe_write_eitr(q_vector
);
1434 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
1435 ixgbe_set_ivar(adapter
, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX
,
1437 else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
1438 ixgbe_set_ivar(adapter
, -1, 1, v_idx
);
1439 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITR(v_idx
), 1950);
1441 /* set up to autoclear timer, and the vectors */
1442 mask
= IXGBE_EIMS_ENABLE_MASK
;
1443 if (adapter
->num_vfs
)
1444 mask
&= ~(IXGBE_EIMS_OTHER
|
1445 IXGBE_EIMS_MAILBOX
|
1448 mask
&= ~(IXGBE_EIMS_OTHER
| IXGBE_EIMS_LSC
);
1449 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIAC
, mask
);
1452 enum latency_range
{
1456 latency_invalid
= 255
1460 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1461 * @adapter: pointer to adapter
1462 * @eitr: eitr setting (ints per sec) to give last timeslice
1463 * @itr_setting: current throttle rate in ints/second
1464 * @packets: the number of packets during this measurement interval
1465 * @bytes: the number of bytes during this measurement interval
1467 * Stores a new ITR value based on packets and byte
1468 * counts during the last interrupt. The advantage of per interrupt
1469 * computation is faster updates and more accurate ITR for the current
1470 * traffic pattern. Constants in this function were computed
1471 * based on theoretical maximum wire speed and thresholds were set based
1472 * on testing data as well as attempting to minimize response time
1473 * while increasing bulk throughput.
1474 * this functionality is controlled by the InterruptThrottleRate module
1475 * parameter (see ixgbe_param.c)
1477 static u8
ixgbe_update_itr(struct ixgbe_adapter
*adapter
,
1478 u32 eitr
, u8 itr_setting
,
1479 int packets
, int bytes
)
1481 unsigned int retval
= itr_setting
;
1486 goto update_itr_done
;
1489 /* simple throttlerate management
1490 * 0-20MB/s lowest (100000 ints/s)
1491 * 20-100MB/s low (20000 ints/s)
1492 * 100-1249MB/s bulk (8000 ints/s)
1494 /* what was last interrupt timeslice? */
1495 timepassed_us
= 1000000/eitr
;
1496 bytes_perint
= bytes
/ timepassed_us
; /* bytes/usec */
1498 switch (itr_setting
) {
1499 case lowest_latency
:
1500 if (bytes_perint
> adapter
->eitr_low
)
1501 retval
= low_latency
;
1504 if (bytes_perint
> adapter
->eitr_high
)
1505 retval
= bulk_latency
;
1506 else if (bytes_perint
<= adapter
->eitr_low
)
1507 retval
= lowest_latency
;
1510 if (bytes_perint
<= adapter
->eitr_high
)
1511 retval
= low_latency
;
1520 * ixgbe_write_eitr - write EITR register in hardware specific way
1521 * @q_vector: structure containing interrupt and ring information
1523 * This function is made to be called by ethtool and by the driver
1524 * when it needs to update EITR registers at runtime. Hardware
1525 * specific quirks/differences are taken care of here.
1527 void ixgbe_write_eitr(struct ixgbe_q_vector
*q_vector
)
1529 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1530 struct ixgbe_hw
*hw
= &adapter
->hw
;
1531 int v_idx
= q_vector
->v_idx
;
1532 u32 itr_reg
= EITR_INTS_PER_SEC_TO_REG(q_vector
->eitr
);
1534 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1535 /* must write high and low 16 bits to reset counter */
1536 itr_reg
|= (itr_reg
<< 16);
1537 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
1539 * 82599 can support a value of zero, so allow it for
1540 * max interrupt rate, but there is an errata where it can
1541 * not be zero with RSC
1544 !(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
))
1548 * set the WDIS bit to not clear the timer bits and cause an
1549 * immediate assertion of the interrupt
1551 itr_reg
|= IXGBE_EITR_CNT_WDIS
;
1553 IXGBE_WRITE_REG(hw
, IXGBE_EITR(v_idx
), itr_reg
);
1556 static void ixgbe_set_itr_msix(struct ixgbe_q_vector
*q_vector
)
1558 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1560 u8 current_itr
, ret_itr
;
1562 struct ixgbe_ring
*rx_ring
, *tx_ring
;
1564 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1565 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1566 tx_ring
= adapter
->tx_ring
[r_idx
];
1567 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1569 tx_ring
->total_packets
,
1570 tx_ring
->total_bytes
);
1571 /* if the result for this queue would decrease interrupt
1572 * rate for this vector then use that result */
1573 q_vector
->tx_itr
= ((q_vector
->tx_itr
> ret_itr
) ?
1574 q_vector
->tx_itr
- 1 : ret_itr
);
1575 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1579 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1580 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1581 rx_ring
= adapter
->rx_ring
[r_idx
];
1582 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1584 rx_ring
->total_packets
,
1585 rx_ring
->total_bytes
);
1586 /* if the result for this queue would decrease interrupt
1587 * rate for this vector then use that result */
1588 q_vector
->rx_itr
= ((q_vector
->rx_itr
> ret_itr
) ?
1589 q_vector
->rx_itr
- 1 : ret_itr
);
1590 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1594 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
1596 switch (current_itr
) {
1597 /* counts and packets in update_itr are dependent on these numbers */
1598 case lowest_latency
:
1602 new_itr
= 20000; /* aka hwitr = ~200 */
1610 if (new_itr
!= q_vector
->eitr
) {
1611 /* do an exponential smoothing */
1612 new_itr
= ((q_vector
->eitr
* 90)/100) + ((new_itr
* 10)/100);
1614 /* save the algorithm value here, not the smoothed one */
1615 q_vector
->eitr
= new_itr
;
1617 ixgbe_write_eitr(q_vector
);
1621 static void ixgbe_check_fan_failure(struct ixgbe_adapter
*adapter
, u32 eicr
)
1623 struct ixgbe_hw
*hw
= &adapter
->hw
;
1625 if ((adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) &&
1626 (eicr
& IXGBE_EICR_GPI_SDP1
)) {
1627 DPRINTK(PROBE
, CRIT
, "Fan has stopped, replace the adapter\n");
1628 /* write to clear the interrupt */
1629 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1633 static void ixgbe_check_sfp_event(struct ixgbe_adapter
*adapter
, u32 eicr
)
1635 struct ixgbe_hw
*hw
= &adapter
->hw
;
1637 if (eicr
& IXGBE_EICR_GPI_SDP1
) {
1638 /* Clear the interrupt */
1639 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1640 schedule_work(&adapter
->multispeed_fiber_task
);
1641 } else if (eicr
& IXGBE_EICR_GPI_SDP2
) {
1642 /* Clear the interrupt */
1643 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP2
);
1644 schedule_work(&adapter
->sfp_config_module_task
);
1646 /* Interrupt isn't for us... */
1651 static void ixgbe_check_lsc(struct ixgbe_adapter
*adapter
)
1653 struct ixgbe_hw
*hw
= &adapter
->hw
;
1656 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
1657 adapter
->link_check_timeout
= jiffies
;
1658 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1659 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_EIMC_LSC
);
1660 IXGBE_WRITE_FLUSH(hw
);
1661 schedule_work(&adapter
->watchdog_task
);
1665 static irqreturn_t
ixgbe_msix_lsc(int irq
, void *data
)
1667 struct net_device
*netdev
= data
;
1668 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
1669 struct ixgbe_hw
*hw
= &adapter
->hw
;
1673 * Workaround for Silicon errata. Use clear-by-write instead
1674 * of clear-by-read. Reading with EICS will return the
1675 * interrupt causes without clearing, which later be done
1676 * with the write to EICR.
1678 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICS
);
1679 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, eicr
);
1681 if (eicr
& IXGBE_EICR_LSC
)
1682 ixgbe_check_lsc(adapter
);
1684 if (eicr
& IXGBE_EICR_MAILBOX
)
1685 ixgbe_msg_task(adapter
);
1687 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
1688 ixgbe_check_fan_failure(adapter
, eicr
);
1690 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
1691 ixgbe_check_sfp_event(adapter
, eicr
);
1693 /* Handle Flow Director Full threshold interrupt */
1694 if (eicr
& IXGBE_EICR_FLOW_DIR
) {
1696 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_FLOW_DIR
);
1697 /* Disable transmits before FDIR Re-initialization */
1698 netif_tx_stop_all_queues(netdev
);
1699 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
1700 struct ixgbe_ring
*tx_ring
=
1701 adapter
->tx_ring
[i
];
1702 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE
,
1703 &tx_ring
->reinit_state
))
1704 schedule_work(&adapter
->fdir_reinit_task
);
1708 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1709 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMS_OTHER
);
1714 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter
*adapter
,
1719 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1720 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1721 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
1723 mask
= (qmask
& 0xFFFFFFFF);
1724 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS_EX(0), mask
);
1725 mask
= (qmask
>> 32);
1726 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS_EX(1), mask
);
1728 /* skip the flush */
1731 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter
*adapter
,
1736 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1737 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1738 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, mask
);
1740 mask
= (qmask
& 0xFFFFFFFF);
1741 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), mask
);
1742 mask
= (qmask
>> 32);
1743 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1), mask
);
1745 /* skip the flush */
1748 static irqreturn_t
ixgbe_msix_clean_tx(int irq
, void *data
)
1750 struct ixgbe_q_vector
*q_vector
= data
;
1751 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1752 struct ixgbe_ring
*tx_ring
;
1755 if (!q_vector
->txr_count
)
1758 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1759 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1760 tx_ring
= adapter
->tx_ring
[r_idx
];
1761 tx_ring
->total_bytes
= 0;
1762 tx_ring
->total_packets
= 0;
1763 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1767 /* EIAM disabled interrupts (on this vector) for us */
1768 napi_schedule(&q_vector
->napi
);
1774 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1776 * @data: pointer to our q_vector struct for this interrupt vector
1778 static irqreturn_t
ixgbe_msix_clean_rx(int irq
, void *data
)
1780 struct ixgbe_q_vector
*q_vector
= data
;
1781 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1782 struct ixgbe_ring
*rx_ring
;
1786 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1787 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1788 rx_ring
= adapter
->rx_ring
[r_idx
];
1789 rx_ring
->total_bytes
= 0;
1790 rx_ring
->total_packets
= 0;
1791 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1795 if (!q_vector
->rxr_count
)
1798 /* disable interrupts on this vector only */
1799 /* EIAM disabled interrupts (on this vector) for us */
1800 napi_schedule(&q_vector
->napi
);
1805 static irqreturn_t
ixgbe_msix_clean_many(int irq
, void *data
)
1807 struct ixgbe_q_vector
*q_vector
= data
;
1808 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1809 struct ixgbe_ring
*ring
;
1813 if (!q_vector
->txr_count
&& !q_vector
->rxr_count
)
1816 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1817 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1818 ring
= adapter
->tx_ring
[r_idx
];
1819 ring
->total_bytes
= 0;
1820 ring
->total_packets
= 0;
1821 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1825 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1826 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1827 ring
= adapter
->rx_ring
[r_idx
];
1828 ring
->total_bytes
= 0;
1829 ring
->total_packets
= 0;
1830 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1834 /* EIAM disabled interrupts (on this vector) for us */
1835 napi_schedule(&q_vector
->napi
);
1841 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1842 * @napi: napi struct with our devices info in it
1843 * @budget: amount of work driver is allowed to do this pass, in packets
1845 * This function is optimized for cleaning one queue only on a single
1848 static int ixgbe_clean_rxonly(struct napi_struct
*napi
, int budget
)
1850 struct ixgbe_q_vector
*q_vector
=
1851 container_of(napi
, struct ixgbe_q_vector
, napi
);
1852 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1853 struct ixgbe_ring
*rx_ring
= NULL
;
1857 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1858 rx_ring
= adapter
->rx_ring
[r_idx
];
1859 #ifdef CONFIG_IXGBE_DCA
1860 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1861 ixgbe_update_rx_dca(adapter
, rx_ring
);
1864 ixgbe_clean_rx_irq(q_vector
, rx_ring
, &work_done
, budget
);
1866 /* If all Rx work done, exit the polling mode */
1867 if (work_done
< budget
) {
1868 napi_complete(napi
);
1869 if (adapter
->rx_itr_setting
& 1)
1870 ixgbe_set_itr_msix(q_vector
);
1871 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1872 ixgbe_irq_enable_queues(adapter
,
1873 ((u64
)1 << q_vector
->v_idx
));
1880 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1881 * @napi: napi struct with our devices info in it
1882 * @budget: amount of work driver is allowed to do this pass, in packets
1884 * This function will clean more than one rx queue associated with a
1887 static int ixgbe_clean_rxtx_many(struct napi_struct
*napi
, int budget
)
1889 struct ixgbe_q_vector
*q_vector
=
1890 container_of(napi
, struct ixgbe_q_vector
, napi
);
1891 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1892 struct ixgbe_ring
*ring
= NULL
;
1893 int work_done
= 0, i
;
1895 bool tx_clean_complete
= true;
1897 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1898 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1899 ring
= adapter
->tx_ring
[r_idx
];
1900 #ifdef CONFIG_IXGBE_DCA
1901 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1902 ixgbe_update_tx_dca(adapter
, ring
);
1904 tx_clean_complete
&= ixgbe_clean_tx_irq(q_vector
, ring
);
1905 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1909 /* attempt to distribute budget to each queue fairly, but don't allow
1910 * the budget to go below 1 because we'll exit polling */
1911 budget
/= (q_vector
->rxr_count
?: 1);
1912 budget
= max(budget
, 1);
1913 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1914 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1915 ring
= adapter
->rx_ring
[r_idx
];
1916 #ifdef CONFIG_IXGBE_DCA
1917 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1918 ixgbe_update_rx_dca(adapter
, ring
);
1920 ixgbe_clean_rx_irq(q_vector
, ring
, &work_done
, budget
);
1921 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1925 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1926 ring
= adapter
->rx_ring
[r_idx
];
1927 /* If all Rx work done, exit the polling mode */
1928 if (work_done
< budget
) {
1929 napi_complete(napi
);
1930 if (adapter
->rx_itr_setting
& 1)
1931 ixgbe_set_itr_msix(q_vector
);
1932 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1933 ixgbe_irq_enable_queues(adapter
,
1934 ((u64
)1 << q_vector
->v_idx
));
1942 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1943 * @napi: napi struct with our devices info in it
1944 * @budget: amount of work driver is allowed to do this pass, in packets
1946 * This function is optimized for cleaning one queue only on a single
1949 static int ixgbe_clean_txonly(struct napi_struct
*napi
, int budget
)
1951 struct ixgbe_q_vector
*q_vector
=
1952 container_of(napi
, struct ixgbe_q_vector
, napi
);
1953 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1954 struct ixgbe_ring
*tx_ring
= NULL
;
1958 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1959 tx_ring
= adapter
->tx_ring
[r_idx
];
1960 #ifdef CONFIG_IXGBE_DCA
1961 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1962 ixgbe_update_tx_dca(adapter
, tx_ring
);
1965 if (!ixgbe_clean_tx_irq(q_vector
, tx_ring
))
1968 /* If all Tx work done, exit the polling mode */
1969 if (work_done
< budget
) {
1970 napi_complete(napi
);
1971 if (adapter
->tx_itr_setting
& 1)
1972 ixgbe_set_itr_msix(q_vector
);
1973 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1974 ixgbe_irq_enable_queues(adapter
, ((u64
)1 << q_vector
->v_idx
));
1980 static inline void map_vector_to_rxq(struct ixgbe_adapter
*a
, int v_idx
,
1983 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
1985 set_bit(r_idx
, q_vector
->rxr_idx
);
1986 q_vector
->rxr_count
++;
1989 static inline void map_vector_to_txq(struct ixgbe_adapter
*a
, int v_idx
,
1992 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
1994 set_bit(t_idx
, q_vector
->txr_idx
);
1995 q_vector
->txr_count
++;
1999 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2000 * @adapter: board private structure to initialize
2001 * @vectors: allotted vector count for descriptor rings
2003 * This function maps descriptor rings to the queue-specific vectors
2004 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2005 * one vector per ring/queue, but on a constrained vector budget, we
2006 * group the rings as "efficiently" as possible. You would add new
2007 * mapping configurations in here.
2009 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter
*adapter
,
2013 int rxr_idx
= 0, txr_idx
= 0;
2014 int rxr_remaining
= adapter
->num_rx_queues
;
2015 int txr_remaining
= adapter
->num_tx_queues
;
2020 /* No mapping required if MSI-X is disabled. */
2021 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
2025 * The ideal configuration...
2026 * We have enough vectors to map one per queue.
2028 if (vectors
== adapter
->num_rx_queues
+ adapter
->num_tx_queues
) {
2029 for (; rxr_idx
< rxr_remaining
; v_start
++, rxr_idx
++)
2030 map_vector_to_rxq(adapter
, v_start
, rxr_idx
);
2032 for (; txr_idx
< txr_remaining
; v_start
++, txr_idx
++)
2033 map_vector_to_txq(adapter
, v_start
, txr_idx
);
2039 * If we don't have enough vectors for a 1-to-1
2040 * mapping, we'll have to group them so there are
2041 * multiple queues per vector.
2043 /* Re-adjusting *qpv takes care of the remainder. */
2044 for (i
= v_start
; i
< vectors
; i
++) {
2045 rqpv
= DIV_ROUND_UP(rxr_remaining
, vectors
- i
);
2046 for (j
= 0; j
< rqpv
; j
++) {
2047 map_vector_to_rxq(adapter
, i
, rxr_idx
);
2052 for (i
= v_start
; i
< vectors
; i
++) {
2053 tqpv
= DIV_ROUND_UP(txr_remaining
, vectors
- i
);
2054 for (j
= 0; j
< tqpv
; j
++) {
2055 map_vector_to_txq(adapter
, i
, txr_idx
);
2066 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2067 * @adapter: board private structure
2069 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2070 * interrupts from the kernel.
2072 static int ixgbe_request_msix_irqs(struct ixgbe_adapter
*adapter
)
2074 struct net_device
*netdev
= adapter
->netdev
;
2075 irqreturn_t (*handler
)(int, void *);
2076 int i
, vector
, q_vectors
, err
;
2079 /* Decrement for Other and TCP Timer vectors */
2080 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2082 /* Map the Tx/Rx rings to the vectors we were allotted. */
2083 err
= ixgbe_map_rings_to_vectors(adapter
, q_vectors
);
2087 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2088 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2089 &ixgbe_msix_clean_many)
2090 for (vector
= 0; vector
< q_vectors
; vector
++) {
2091 handler
= SET_HANDLER(adapter
->q_vector
[vector
]);
2093 if(handler
== &ixgbe_msix_clean_rx
) {
2094 sprintf(adapter
->name
[vector
], "%s-%s-%d",
2095 netdev
->name
, "rx", ri
++);
2097 else if(handler
== &ixgbe_msix_clean_tx
) {
2098 sprintf(adapter
->name
[vector
], "%s-%s-%d",
2099 netdev
->name
, "tx", ti
++);
2102 sprintf(adapter
->name
[vector
], "%s-%s-%d",
2103 netdev
->name
, "TxRx", vector
);
2105 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
2106 handler
, 0, adapter
->name
[vector
],
2107 adapter
->q_vector
[vector
]);
2110 "request_irq failed for MSIX interrupt "
2111 "Error: %d\n", err
);
2112 goto free_queue_irqs
;
2116 sprintf(adapter
->name
[vector
], "%s:lsc", netdev
->name
);
2117 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
2118 ixgbe_msix_lsc
, 0, adapter
->name
[vector
], netdev
);
2121 "request_irq for msix_lsc failed: %d\n", err
);
2122 goto free_queue_irqs
;
2128 for (i
= vector
- 1; i
>= 0; i
--)
2129 free_irq(adapter
->msix_entries
[--vector
].vector
,
2130 adapter
->q_vector
[i
]);
2131 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
2132 pci_disable_msix(adapter
->pdev
);
2133 kfree(adapter
->msix_entries
);
2134 adapter
->msix_entries
= NULL
;
2139 static void ixgbe_set_itr(struct ixgbe_adapter
*adapter
)
2141 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
2143 u32 new_itr
= q_vector
->eitr
;
2144 struct ixgbe_ring
*rx_ring
= adapter
->rx_ring
[0];
2145 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[0];
2147 q_vector
->tx_itr
= ixgbe_update_itr(adapter
, new_itr
,
2149 tx_ring
->total_packets
,
2150 tx_ring
->total_bytes
);
2151 q_vector
->rx_itr
= ixgbe_update_itr(adapter
, new_itr
,
2153 rx_ring
->total_packets
,
2154 rx_ring
->total_bytes
);
2156 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
2158 switch (current_itr
) {
2159 /* counts and packets in update_itr are dependent on these numbers */
2160 case lowest_latency
:
2164 new_itr
= 20000; /* aka hwitr = ~200 */
2173 if (new_itr
!= q_vector
->eitr
) {
2174 /* do an exponential smoothing */
2175 new_itr
= ((q_vector
->eitr
* 90)/100) + ((new_itr
* 10)/100);
2177 /* save the algorithm value here, not the smoothed one */
2178 q_vector
->eitr
= new_itr
;
2180 ixgbe_write_eitr(q_vector
);
2185 * ixgbe_irq_enable - Enable default interrupt generation settings
2186 * @adapter: board private structure
2188 static inline void ixgbe_irq_enable(struct ixgbe_adapter
*adapter
)
2192 mask
= (IXGBE_EIMS_ENABLE_MASK
& ~IXGBE_EIMS_RTX_QUEUE
);
2193 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
)
2194 mask
|= IXGBE_EIMS_GPI_SDP1
;
2195 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
2196 mask
|= IXGBE_EIMS_ECC
;
2197 mask
|= IXGBE_EIMS_GPI_SDP1
;
2198 mask
|= IXGBE_EIMS_GPI_SDP2
;
2199 if (adapter
->num_vfs
)
2200 mask
|= IXGBE_EIMS_MAILBOX
;
2202 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
2203 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
2204 mask
|= IXGBE_EIMS_FLOW_DIR
;
2206 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
2207 ixgbe_irq_enable_queues(adapter
, ~0);
2208 IXGBE_WRITE_FLUSH(&adapter
->hw
);
2210 if (adapter
->num_vfs
> 32) {
2211 u32 eitrsel
= (1 << (adapter
->num_vfs
- 32)) - 1;
2212 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, eitrsel
);
2217 * ixgbe_intr - legacy mode Interrupt Handler
2218 * @irq: interrupt number
2219 * @data: pointer to a network interface device structure
2221 static irqreturn_t
ixgbe_intr(int irq
, void *data
)
2223 struct net_device
*netdev
= data
;
2224 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2225 struct ixgbe_hw
*hw
= &adapter
->hw
;
2226 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
2230 * Workaround for silicon errata. Mask the interrupts
2231 * before the read of EICR.
2233 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_IRQ_CLEAR_MASK
);
2235 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2236 * therefore no explict interrupt disable is necessary */
2237 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICR
);
2239 /* shared interrupt alert!
2240 * make sure interrupts are enabled because the read will
2241 * have disabled interrupts due to EIAM */
2242 ixgbe_irq_enable(adapter
);
2243 return IRQ_NONE
; /* Not our interrupt */
2246 if (eicr
& IXGBE_EICR_LSC
)
2247 ixgbe_check_lsc(adapter
);
2249 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
2250 ixgbe_check_sfp_event(adapter
, eicr
);
2252 ixgbe_check_fan_failure(adapter
, eicr
);
2254 if (napi_schedule_prep(&(q_vector
->napi
))) {
2255 adapter
->tx_ring
[0]->total_packets
= 0;
2256 adapter
->tx_ring
[0]->total_bytes
= 0;
2257 adapter
->rx_ring
[0]->total_packets
= 0;
2258 adapter
->rx_ring
[0]->total_bytes
= 0;
2259 /* would disable interrupts here but EIAM disabled it */
2260 __napi_schedule(&(q_vector
->napi
));
2266 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter
*adapter
)
2268 int i
, q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2270 for (i
= 0; i
< q_vectors
; i
++) {
2271 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
2272 bitmap_zero(q_vector
->rxr_idx
, MAX_RX_QUEUES
);
2273 bitmap_zero(q_vector
->txr_idx
, MAX_TX_QUEUES
);
2274 q_vector
->rxr_count
= 0;
2275 q_vector
->txr_count
= 0;
2280 * ixgbe_request_irq - initialize interrupts
2281 * @adapter: board private structure
2283 * Attempts to configure interrupts using the best available
2284 * capabilities of the hardware and kernel.
2286 static int ixgbe_request_irq(struct ixgbe_adapter
*adapter
)
2288 struct net_device
*netdev
= adapter
->netdev
;
2291 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2292 err
= ixgbe_request_msix_irqs(adapter
);
2293 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
2294 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, 0,
2295 netdev
->name
, netdev
);
2297 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, IRQF_SHARED
,
2298 netdev
->name
, netdev
);
2302 DPRINTK(PROBE
, ERR
, "request_irq failed, Error %d\n", err
);
2307 static void ixgbe_free_irq(struct ixgbe_adapter
*adapter
)
2309 struct net_device
*netdev
= adapter
->netdev
;
2311 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2314 q_vectors
= adapter
->num_msix_vectors
;
2317 free_irq(adapter
->msix_entries
[i
].vector
, netdev
);
2320 for (; i
>= 0; i
--) {
2321 free_irq(adapter
->msix_entries
[i
].vector
,
2322 adapter
->q_vector
[i
]);
2325 ixgbe_reset_q_vectors(adapter
);
2327 free_irq(adapter
->pdev
->irq
, netdev
);
2332 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2333 * @adapter: board private structure
2335 static inline void ixgbe_irq_disable(struct ixgbe_adapter
*adapter
)
2337 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
2338 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, ~0);
2340 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, 0xFFFF0000);
2341 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), ~0);
2342 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1), ~0);
2343 if (adapter
->num_vfs
> 32)
2344 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, 0);
2346 IXGBE_WRITE_FLUSH(&adapter
->hw
);
2347 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2349 for (i
= 0; i
< adapter
->num_msix_vectors
; i
++)
2350 synchronize_irq(adapter
->msix_entries
[i
].vector
);
2352 synchronize_irq(adapter
->pdev
->irq
);
2357 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2360 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter
*adapter
)
2362 struct ixgbe_hw
*hw
= &adapter
->hw
;
2364 IXGBE_WRITE_REG(hw
, IXGBE_EITR(0),
2365 EITR_INTS_PER_SEC_TO_REG(adapter
->rx_eitr_param
));
2367 ixgbe_set_ivar(adapter
, 0, 0, 0);
2368 ixgbe_set_ivar(adapter
, 1, 0, 0);
2370 map_vector_to_rxq(adapter
, 0, 0);
2371 map_vector_to_txq(adapter
, 0, 0);
2373 DPRINTK(HW
, INFO
, "Legacy interrupt IVAR setup done\n");
2377 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2378 * @adapter: board private structure
2380 * Configure the Tx unit of the MAC after a reset.
2382 static void ixgbe_configure_tx(struct ixgbe_adapter
*adapter
)
2385 struct ixgbe_hw
*hw
= &adapter
->hw
;
2386 u32 i
, j
, tdlen
, txctrl
;
2388 /* Setup the HW Tx Head and Tail descriptor pointers */
2389 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2390 struct ixgbe_ring
*ring
= adapter
->tx_ring
[i
];
2393 tdlen
= ring
->count
* sizeof(union ixgbe_adv_tx_desc
);
2394 IXGBE_WRITE_REG(hw
, IXGBE_TDBAL(j
),
2395 (tdba
& DMA_BIT_MASK(32)));
2396 IXGBE_WRITE_REG(hw
, IXGBE_TDBAH(j
), (tdba
>> 32));
2397 IXGBE_WRITE_REG(hw
, IXGBE_TDLEN(j
), tdlen
);
2398 IXGBE_WRITE_REG(hw
, IXGBE_TDH(j
), 0);
2399 IXGBE_WRITE_REG(hw
, IXGBE_TDT(j
), 0);
2400 adapter
->tx_ring
[i
]->head
= IXGBE_TDH(j
);
2401 adapter
->tx_ring
[i
]->tail
= IXGBE_TDT(j
);
2403 * Disable Tx Head Writeback RO bit, since this hoses
2404 * bookkeeping if things aren't delivered in order.
2406 switch (hw
->mac
.type
) {
2407 case ixgbe_mac_82598EB
:
2408 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL(j
));
2410 case ixgbe_mac_82599EB
:
2412 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL_82599(j
));
2415 txctrl
&= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN
;
2416 switch (hw
->mac
.type
) {
2417 case ixgbe_mac_82598EB
:
2418 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL(j
), txctrl
);
2420 case ixgbe_mac_82599EB
:
2422 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL_82599(j
), txctrl
);
2427 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2431 /* disable the arbiter while setting MTQC */
2432 rttdcs
= IXGBE_READ_REG(hw
, IXGBE_RTTDCS
);
2433 rttdcs
|= IXGBE_RTTDCS_ARBDIS
;
2434 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2436 /* set transmit pool layout */
2437 mask
= (IXGBE_FLAG_SRIOV_ENABLED
| IXGBE_FLAG_DCB_ENABLED
);
2438 switch (adapter
->flags
& mask
) {
2440 case (IXGBE_FLAG_SRIOV_ENABLED
):
2441 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
,
2442 (IXGBE_MTQC_VT_ENA
| IXGBE_MTQC_64VF
));
2445 case (IXGBE_FLAG_DCB_ENABLED
):
2446 /* We enable 8 traffic classes, DCB only */
2447 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
,
2448 (IXGBE_MTQC_RT_ENA
| IXGBE_MTQC_8TC_8TQ
));
2452 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
, IXGBE_MTQC_64Q_1PB
);
2456 /* re-eable the arbiter */
2457 rttdcs
&= ~IXGBE_RTTDCS_ARBDIS
;
2458 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2462 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2464 static void ixgbe_configure_srrctl(struct ixgbe_adapter
*adapter
,
2465 struct ixgbe_ring
*rx_ring
)
2469 struct ixgbe_ring_feature
*feature
= adapter
->ring_feature
;
2471 index
= rx_ring
->reg_idx
;
2472 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
2474 mask
= (unsigned long) feature
[RING_F_RSS
].mask
;
2475 index
= index
& mask
;
2477 srrctl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_SRRCTL(index
));
2479 srrctl
&= ~IXGBE_SRRCTL_BSIZEHDR_MASK
;
2480 srrctl
&= ~IXGBE_SRRCTL_BSIZEPKT_MASK
;
2482 srrctl
|= (IXGBE_RX_HDR_SIZE
<< IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT
) &
2483 IXGBE_SRRCTL_BSIZEHDR_MASK
;
2485 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
2486 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2487 srrctl
|= IXGBE_MAX_RXBUFFER
>> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2489 srrctl
|= (PAGE_SIZE
/ 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2491 srrctl
|= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS
;
2493 srrctl
|= ALIGN(rx_ring
->rx_buf_len
, 1024) >>
2494 IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2495 srrctl
|= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF
;
2498 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_SRRCTL(index
), srrctl
);
2501 static u32
ixgbe_setup_mrqc(struct ixgbe_adapter
*adapter
)
2506 if (!(adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
))
2509 mask
= adapter
->flags
& (IXGBE_FLAG_RSS_ENABLED
2510 #ifdef CONFIG_IXGBE_DCB
2511 | IXGBE_FLAG_DCB_ENABLED
2513 | IXGBE_FLAG_SRIOV_ENABLED
2517 case (IXGBE_FLAG_RSS_ENABLED
):
2518 mrqc
= IXGBE_MRQC_RSSEN
;
2520 case (IXGBE_FLAG_SRIOV_ENABLED
):
2521 mrqc
= IXGBE_MRQC_VMDQEN
;
2523 #ifdef CONFIG_IXGBE_DCB
2524 case (IXGBE_FLAG_DCB_ENABLED
):
2525 mrqc
= IXGBE_MRQC_RT8TCEN
;
2527 #endif /* CONFIG_IXGBE_DCB */
2536 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2537 * @adapter: address of board private structure
2538 * @index: index of ring to set
2540 static void ixgbe_configure_rscctl(struct ixgbe_adapter
*adapter
, int index
)
2542 struct ixgbe_ring
*rx_ring
;
2543 struct ixgbe_hw
*hw
= &adapter
->hw
;
2548 rx_ring
= adapter
->rx_ring
[index
];
2549 j
= rx_ring
->reg_idx
;
2550 rx_buf_len
= rx_ring
->rx_buf_len
;
2551 rscctrl
= IXGBE_READ_REG(hw
, IXGBE_RSCCTL(j
));
2552 rscctrl
|= IXGBE_RSCCTL_RSCEN
;
2554 * we must limit the number of descriptors so that the
2555 * total size of max desc * buf_len is not greater
2558 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
2559 #if (MAX_SKB_FRAGS > 16)
2560 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2561 #elif (MAX_SKB_FRAGS > 8)
2562 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2563 #elif (MAX_SKB_FRAGS > 4)
2564 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2566 rscctrl
|= IXGBE_RSCCTL_MAXDESC_1
;
2569 if (rx_buf_len
< IXGBE_RXBUFFER_4096
)
2570 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2571 else if (rx_buf_len
< IXGBE_RXBUFFER_8192
)
2572 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2574 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2576 IXGBE_WRITE_REG(hw
, IXGBE_RSCCTL(j
), rscctrl
);
2580 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2581 * @adapter: board private structure
2583 * Configure the Rx unit of the MAC after a reset.
2585 static void ixgbe_configure_rx(struct ixgbe_adapter
*adapter
)
2588 struct ixgbe_hw
*hw
= &adapter
->hw
;
2589 struct ixgbe_ring
*rx_ring
;
2590 struct net_device
*netdev
= adapter
->netdev
;
2591 int max_frame
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
2593 u32 rdlen
, rxctrl
, rxcsum
;
2594 static const u32 seed
[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2595 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2596 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2598 u32 reta
= 0, mrqc
= 0;
2602 /* Decide whether to use packet split mode or not */
2603 /* Do not use packet split if we're in SR-IOV Mode */
2604 if (!adapter
->num_vfs
)
2605 adapter
->flags
|= IXGBE_FLAG_RX_PS_ENABLED
;
2607 /* Set the RX buffer length according to the mode */
2608 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
) {
2609 rx_buf_len
= IXGBE_RX_HDR_SIZE
;
2610 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2611 /* PSRTYPE must be initialized in 82599 */
2612 u32 psrtype
= IXGBE_PSRTYPE_TCPHDR
|
2613 IXGBE_PSRTYPE_UDPHDR
|
2614 IXGBE_PSRTYPE_IPV4HDR
|
2615 IXGBE_PSRTYPE_IPV6HDR
|
2616 IXGBE_PSRTYPE_L2HDR
;
2618 IXGBE_PSRTYPE(adapter
->num_vfs
),
2622 if (!(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) &&
2623 (netdev
->mtu
<= ETH_DATA_LEN
))
2624 rx_buf_len
= MAXIMUM_ETHERNET_VLAN_SIZE
;
2626 rx_buf_len
= ALIGN(max_frame
, 1024);
2629 fctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_FCTRL
);
2630 fctrl
|= IXGBE_FCTRL_BAM
;
2631 fctrl
|= IXGBE_FCTRL_DPF
; /* discard pause frames when FC enabled */
2632 fctrl
|= IXGBE_FCTRL_PMCF
;
2633 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_FCTRL
, fctrl
);
2635 hlreg0
= IXGBE_READ_REG(hw
, IXGBE_HLREG0
);
2636 if (adapter
->netdev
->mtu
<= ETH_DATA_LEN
)
2637 hlreg0
&= ~IXGBE_HLREG0_JUMBOEN
;
2639 hlreg0
|= IXGBE_HLREG0_JUMBOEN
;
2641 if (netdev
->features
& NETIF_F_FCOE_MTU
)
2642 hlreg0
|= IXGBE_HLREG0_JUMBOEN
;
2644 IXGBE_WRITE_REG(hw
, IXGBE_HLREG0
, hlreg0
);
2646 rdlen
= adapter
->rx_ring
[0]->count
* sizeof(union ixgbe_adv_rx_desc
);
2647 /* disable receives while setting up the descriptors */
2648 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
2649 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
2652 * Setup the HW Rx Head and Tail Descriptor Pointers and
2653 * the Base and Length of the Rx Descriptor Ring
2655 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2656 rx_ring
= adapter
->rx_ring
[i
];
2657 rdba
= rx_ring
->dma
;
2658 j
= rx_ring
->reg_idx
;
2659 IXGBE_WRITE_REG(hw
, IXGBE_RDBAL(j
), (rdba
& DMA_BIT_MASK(32)));
2660 IXGBE_WRITE_REG(hw
, IXGBE_RDBAH(j
), (rdba
>> 32));
2661 IXGBE_WRITE_REG(hw
, IXGBE_RDLEN(j
), rdlen
);
2662 IXGBE_WRITE_REG(hw
, IXGBE_RDH(j
), 0);
2663 IXGBE_WRITE_REG(hw
, IXGBE_RDT(j
), 0);
2664 rx_ring
->head
= IXGBE_RDH(j
);
2665 rx_ring
->tail
= IXGBE_RDT(j
);
2666 rx_ring
->rx_buf_len
= rx_buf_len
;
2668 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
)
2669 rx_ring
->flags
|= IXGBE_RING_RX_PS_ENABLED
;
2671 rx_ring
->flags
&= ~IXGBE_RING_RX_PS_ENABLED
;
2674 if (netdev
->features
& NETIF_F_FCOE_MTU
) {
2675 struct ixgbe_ring_feature
*f
;
2676 f
= &adapter
->ring_feature
[RING_F_FCOE
];
2677 if ((i
>= f
->mask
) && (i
< f
->mask
+ f
->indices
)) {
2678 rx_ring
->flags
&= ~IXGBE_RING_RX_PS_ENABLED
;
2679 if (rx_buf_len
< IXGBE_FCOE_JUMBO_FRAME_SIZE
)
2680 rx_ring
->rx_buf_len
=
2681 IXGBE_FCOE_JUMBO_FRAME_SIZE
;
2685 #endif /* IXGBE_FCOE */
2686 ixgbe_configure_srrctl(adapter
, rx_ring
);
2689 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
2691 * For VMDq support of different descriptor types or
2692 * buffer sizes through the use of multiple SRRCTL
2693 * registers, RDRXCTL.MVMEN must be set to 1
2695 * also, the manual doesn't mention it clearly but DCA hints
2696 * will only use queue 0's tags unless this bit is set. Side
2697 * effects of setting this bit are only that SRRCTL must be
2698 * fully programmed [0..15]
2700 rdrxctl
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
2701 rdrxctl
|= IXGBE_RDRXCTL_MVMEN
;
2702 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, rdrxctl
);
2705 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
2707 u32 reg_offset
, vf_shift
;
2708 u32 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
2709 vt_reg_bits
= IXGBE_VMD_CTL_VMDQ_EN
2710 | IXGBE_VT_CTL_REPLEN
;
2711 vt_reg_bits
|= (adapter
->num_vfs
<<
2712 IXGBE_VT_CTL_POOL_SHIFT
);
2713 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
| vt_reg_bits
);
2714 IXGBE_WRITE_REG(hw
, IXGBE_MRQC
, 0);
2716 vf_shift
= adapter
->num_vfs
% 32;
2717 reg_offset
= adapter
->num_vfs
/ 32;
2718 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(0), 0);
2719 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(1), 0);
2720 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(0), 0);
2721 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(1), 0);
2722 /* Enable only the PF's pool for Tx/Rx */
2723 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(reg_offset
), (1 << vf_shift
));
2724 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(reg_offset
), (1 << vf_shift
));
2725 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, IXGBE_PFDTXGSWC_VT_LBEN
);
2726 ixgbe_set_vmolr(hw
, adapter
->num_vfs
, true);
2729 /* Program MRQC for the distribution of queues */
2730 mrqc
= ixgbe_setup_mrqc(adapter
);
2732 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
2733 /* Fill out redirection table */
2734 for (i
= 0, j
= 0; i
< 128; i
++, j
++) {
2735 if (j
== adapter
->ring_feature
[RING_F_RSS
].indices
)
2737 /* reta = 4-byte sliding window of
2738 * 0x00..(indices-1)(indices-1)00..etc. */
2739 reta
= (reta
<< 8) | (j
* 0x11);
2741 IXGBE_WRITE_REG(hw
, IXGBE_RETA(i
>> 2), reta
);
2744 /* Fill out hash function seeds */
2745 for (i
= 0; i
< 10; i
++)
2746 IXGBE_WRITE_REG(hw
, IXGBE_RSSRK(i
), seed
[i
]);
2748 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2749 mrqc
|= IXGBE_MRQC_RSSEN
;
2750 /* Perform hash on these packet types */
2751 mrqc
|= IXGBE_MRQC_RSS_FIELD_IPV4
2752 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2753 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2754 | IXGBE_MRQC_RSS_FIELD_IPV6
2755 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2756 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP
;
2758 IXGBE_WRITE_REG(hw
, IXGBE_MRQC
, mrqc
);
2760 if (adapter
->num_vfs
) {
2763 /* Map PF MAC address in RAR Entry 0 to first pool
2765 hw
->mac
.ops
.set_vmdq(hw
, 0, adapter
->num_vfs
);
2767 /* Set up VF register offsets for selected VT Mode, i.e.
2768 * 64 VFs for SR-IOV */
2769 reg
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
2770 reg
|= IXGBE_GCR_EXT_SRIOV
;
2771 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, reg
);
2774 rxcsum
= IXGBE_READ_REG(hw
, IXGBE_RXCSUM
);
2776 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
||
2777 adapter
->flags
& IXGBE_FLAG_RX_CSUM_ENABLED
) {
2778 /* Disable indicating checksum in descriptor, enables
2780 rxcsum
|= IXGBE_RXCSUM_PCSD
;
2782 if (!(rxcsum
& IXGBE_RXCSUM_PCSD
)) {
2783 /* Enable IPv4 payload checksum for UDP fragments
2784 * if PCSD is not set */
2785 rxcsum
|= IXGBE_RXCSUM_IPPCSE
;
2788 IXGBE_WRITE_REG(hw
, IXGBE_RXCSUM
, rxcsum
);
2790 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2791 rdrxctl
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
2792 rdrxctl
|= IXGBE_RDRXCTL_CRCSTRIP
;
2793 rdrxctl
&= ~IXGBE_RDRXCTL_RSCFRSTSIZE
;
2794 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, rdrxctl
);
2797 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
2798 /* Enable 82599 HW-RSC */
2799 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
2800 ixgbe_configure_rscctl(adapter
, i
);
2802 /* Disable RSC for ACK packets */
2803 IXGBE_WRITE_REG(hw
, IXGBE_RSCDBU
,
2804 (IXGBE_RSCDBU_RSCACKDIS
| IXGBE_READ_REG(hw
, IXGBE_RSCDBU
)));
2808 static void ixgbe_vlan_rx_add_vid(struct net_device
*netdev
, u16 vid
)
2810 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2811 struct ixgbe_hw
*hw
= &adapter
->hw
;
2812 int pool_ndx
= adapter
->num_vfs
;
2814 /* add VID to filter table */
2815 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, true);
2818 static void ixgbe_vlan_rx_kill_vid(struct net_device
*netdev
, u16 vid
)
2820 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2821 struct ixgbe_hw
*hw
= &adapter
->hw
;
2822 int pool_ndx
= adapter
->num_vfs
;
2824 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2825 ixgbe_irq_disable(adapter
);
2827 vlan_group_set_device(adapter
->vlgrp
, vid
, NULL
);
2829 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2830 ixgbe_irq_enable(adapter
);
2832 /* remove VID from filter table */
2833 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, false);
2837 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
2838 * @adapter: driver data
2840 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter
*adapter
)
2842 struct ixgbe_hw
*hw
= &adapter
->hw
;
2843 u32 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
2846 switch (hw
->mac
.type
) {
2847 case ixgbe_mac_82598EB
:
2848 vlnctrl
&= ~(IXGBE_VLNCTRL_VME
| IXGBE_VLNCTRL_VFE
);
2849 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2850 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2852 case ixgbe_mac_82599EB
:
2853 vlnctrl
&= ~IXGBE_VLNCTRL_VFE
;
2854 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2855 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2856 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2857 j
= adapter
->rx_ring
[i
]->reg_idx
;
2858 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
2859 vlnctrl
&= ~IXGBE_RXDCTL_VME
;
2860 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
2869 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
2870 * @adapter: driver data
2872 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter
*adapter
)
2874 struct ixgbe_hw
*hw
= &adapter
->hw
;
2875 u32 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
2878 switch (hw
->mac
.type
) {
2879 case ixgbe_mac_82598EB
:
2880 vlnctrl
|= IXGBE_VLNCTRL_VME
| IXGBE_VLNCTRL_VFE
;
2881 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2882 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2884 case ixgbe_mac_82599EB
:
2885 vlnctrl
|= IXGBE_VLNCTRL_VFE
;
2886 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2887 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2888 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2889 j
= adapter
->rx_ring
[i
]->reg_idx
;
2890 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
2891 vlnctrl
|= IXGBE_RXDCTL_VME
;
2892 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
2900 static void ixgbe_vlan_rx_register(struct net_device
*netdev
,
2901 struct vlan_group
*grp
)
2903 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2905 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2906 ixgbe_irq_disable(adapter
);
2907 adapter
->vlgrp
= grp
;
2910 * For a DCB driver, always enable VLAN tag stripping so we can
2911 * still receive traffic from a DCB-enabled host even if we're
2914 ixgbe_vlan_filter_enable(adapter
);
2916 ixgbe_vlan_rx_add_vid(netdev
, 0);
2918 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2919 ixgbe_irq_enable(adapter
);
2922 static void ixgbe_restore_vlan(struct ixgbe_adapter
*adapter
)
2924 ixgbe_vlan_rx_register(adapter
->netdev
, adapter
->vlgrp
);
2926 if (adapter
->vlgrp
) {
2928 for (vid
= 0; vid
< VLAN_GROUP_ARRAY_LEN
; vid
++) {
2929 if (!vlan_group_get_device(adapter
->vlgrp
, vid
))
2931 ixgbe_vlan_rx_add_vid(adapter
->netdev
, vid
);
2937 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2938 * @netdev: network interface device structure
2940 * The set_rx_method entry point is called whenever the unicast/multicast
2941 * address list or the network interface flags are updated. This routine is
2942 * responsible for configuring the hardware for proper unicast, multicast and
2945 void ixgbe_set_rx_mode(struct net_device
*netdev
)
2947 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2948 struct ixgbe_hw
*hw
= &adapter
->hw
;
2951 /* Check for Promiscuous and All Multicast modes */
2953 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
2955 if (netdev
->flags
& IFF_PROMISC
) {
2956 hw
->addr_ctrl
.user_set_promisc
= true;
2957 fctrl
|= (IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
2958 /* don't hardware filter vlans in promisc mode */
2959 ixgbe_vlan_filter_disable(adapter
);
2961 if (netdev
->flags
& IFF_ALLMULTI
) {
2962 fctrl
|= IXGBE_FCTRL_MPE
;
2963 fctrl
&= ~IXGBE_FCTRL_UPE
;
2964 } else if (!hw
->addr_ctrl
.uc_set_promisc
) {
2965 fctrl
&= ~(IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
2967 ixgbe_vlan_filter_enable(adapter
);
2968 hw
->addr_ctrl
.user_set_promisc
= false;
2971 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
2973 /* reprogram secondary unicast list */
2974 hw
->mac
.ops
.update_uc_addr_list(hw
, netdev
);
2976 /* reprogram multicast list */
2977 hw
->mac
.ops
.update_mc_addr_list(hw
, netdev
);
2979 if (adapter
->num_vfs
)
2980 ixgbe_restore_vf_multicasts(adapter
);
2983 static void ixgbe_napi_enable_all(struct ixgbe_adapter
*adapter
)
2986 struct ixgbe_q_vector
*q_vector
;
2987 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2989 /* legacy and MSI only use one vector */
2990 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
2993 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
2994 struct napi_struct
*napi
;
2995 q_vector
= adapter
->q_vector
[q_idx
];
2996 napi
= &q_vector
->napi
;
2997 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2998 if (!q_vector
->rxr_count
|| !q_vector
->txr_count
) {
2999 if (q_vector
->txr_count
== 1)
3000 napi
->poll
= &ixgbe_clean_txonly
;
3001 else if (q_vector
->rxr_count
== 1)
3002 napi
->poll
= &ixgbe_clean_rxonly
;
3010 static void ixgbe_napi_disable_all(struct ixgbe_adapter
*adapter
)
3013 struct ixgbe_q_vector
*q_vector
;
3014 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3016 /* legacy and MSI only use one vector */
3017 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
3020 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
3021 q_vector
= adapter
->q_vector
[q_idx
];
3022 napi_disable(&q_vector
->napi
);
3026 #ifdef CONFIG_IXGBE_DCB
3028 * ixgbe_configure_dcb - Configure DCB hardware
3029 * @adapter: ixgbe adapter struct
3031 * This is called by the driver on open to configure the DCB hardware.
3032 * This is also called by the gennetlink interface when reconfiguring
3035 static void ixgbe_configure_dcb(struct ixgbe_adapter
*adapter
)
3037 struct ixgbe_hw
*hw
= &adapter
->hw
;
3041 ixgbe_dcb_check_config(&adapter
->dcb_cfg
);
3042 ixgbe_dcb_calculate_tc_credits(&adapter
->dcb_cfg
, DCB_TX_CONFIG
);
3043 ixgbe_dcb_calculate_tc_credits(&adapter
->dcb_cfg
, DCB_RX_CONFIG
);
3045 /* reconfigure the hardware */
3046 ixgbe_dcb_hw_config(&adapter
->hw
, &adapter
->dcb_cfg
);
3048 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
3049 j
= adapter
->tx_ring
[i
]->reg_idx
;
3050 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
3051 /* PThresh workaround for Tx hang with DFP enabled. */
3053 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
), txdctl
);
3055 /* Enable VLAN tag insert/strip */
3056 ixgbe_vlan_filter_enable(adapter
);
3058 hw
->mac
.ops
.set_vfta(&adapter
->hw
, 0, 0, true);
3062 static void ixgbe_configure(struct ixgbe_adapter
*adapter
)
3064 struct net_device
*netdev
= adapter
->netdev
;
3065 struct ixgbe_hw
*hw
= &adapter
->hw
;
3068 ixgbe_set_rx_mode(netdev
);
3070 ixgbe_restore_vlan(adapter
);
3071 #ifdef CONFIG_IXGBE_DCB
3072 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
3073 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3074 netif_set_gso_max_size(netdev
, 32768);
3076 netif_set_gso_max_size(netdev
, 65536);
3077 ixgbe_configure_dcb(adapter
);
3079 netif_set_gso_max_size(netdev
, 65536);
3082 netif_set_gso_max_size(netdev
, 65536);
3086 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
3087 ixgbe_configure_fcoe(adapter
);
3089 #endif /* IXGBE_FCOE */
3090 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
3091 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3092 adapter
->tx_ring
[i
]->atr_sample_rate
=
3093 adapter
->atr_sample_rate
;
3094 ixgbe_init_fdir_signature_82599(hw
, adapter
->fdir_pballoc
);
3095 } else if (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
) {
3096 ixgbe_init_fdir_perfect_82599(hw
, adapter
->fdir_pballoc
);
3099 ixgbe_configure_tx(adapter
);
3100 ixgbe_configure_rx(adapter
);
3101 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3102 ixgbe_alloc_rx_buffers(adapter
, adapter
->rx_ring
[i
],
3103 (adapter
->rx_ring
[i
]->count
- 1));
3106 static inline bool ixgbe_is_sfp(struct ixgbe_hw
*hw
)
3108 switch (hw
->phy
.type
) {
3109 case ixgbe_phy_sfp_avago
:
3110 case ixgbe_phy_sfp_ftl
:
3111 case ixgbe_phy_sfp_intel
:
3112 case ixgbe_phy_sfp_unknown
:
3113 case ixgbe_phy_tw_tyco
:
3114 case ixgbe_phy_tw_unknown
:
3122 * ixgbe_sfp_link_config - set up SFP+ link
3123 * @adapter: pointer to private adapter struct
3125 static void ixgbe_sfp_link_config(struct ixgbe_adapter
*adapter
)
3127 struct ixgbe_hw
*hw
= &adapter
->hw
;
3129 if (hw
->phy
.multispeed_fiber
) {
3131 * In multispeed fiber setups, the device may not have
3132 * had a physical connection when the driver loaded.
3133 * If that's the case, the initial link configuration
3134 * couldn't get the MAC into 10G or 1G mode, so we'll
3135 * never have a link status change interrupt fire.
3136 * We need to try and force an autonegotiation
3137 * session, then bring up link.
3139 hw
->mac
.ops
.setup_sfp(hw
);
3140 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_LINK_TASK
))
3141 schedule_work(&adapter
->multispeed_fiber_task
);
3144 * Direct Attach Cu and non-multispeed fiber modules
3145 * still need to be configured properly prior to
3148 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_MOD_TASK
))
3149 schedule_work(&adapter
->sfp_config_module_task
);
3154 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3155 * @hw: pointer to private hardware struct
3157 * Returns 0 on success, negative on failure
3159 static int ixgbe_non_sfp_link_config(struct ixgbe_hw
*hw
)
3162 bool negotiation
, link_up
= false;
3163 u32 ret
= IXGBE_ERR_LINK_SETUP
;
3165 if (hw
->mac
.ops
.check_link
)
3166 ret
= hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
3171 if (hw
->mac
.ops
.get_link_capabilities
)
3172 ret
= hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
, &negotiation
);
3176 if (hw
->mac
.ops
.setup_link
)
3177 ret
= hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, link_up
);
3182 #define IXGBE_MAX_RX_DESC_POLL 10
3183 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter
*adapter
,
3186 int j
= adapter
->rx_ring
[rxr
]->reg_idx
;
3189 for (k
= 0; k
< IXGBE_MAX_RX_DESC_POLL
; k
++) {
3190 if (IXGBE_READ_REG(&adapter
->hw
,
3191 IXGBE_RXDCTL(j
)) & IXGBE_RXDCTL_ENABLE
)
3196 if (k
>= IXGBE_MAX_RX_DESC_POLL
) {
3197 DPRINTK(DRV
, ERR
, "RXDCTL.ENABLE on Rx queue %d "
3198 "not set within the polling period\n", rxr
);
3200 ixgbe_release_rx_desc(&adapter
->hw
, adapter
->rx_ring
[rxr
],
3201 (adapter
->rx_ring
[rxr
]->count
- 1));
3204 static int ixgbe_up_complete(struct ixgbe_adapter
*adapter
)
3206 struct net_device
*netdev
= adapter
->netdev
;
3207 struct ixgbe_hw
*hw
= &adapter
->hw
;
3209 int num_rx_rings
= adapter
->num_rx_queues
;
3211 int max_frame
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
3212 u32 txdctl
, rxdctl
, mhadd
;
3217 ixgbe_get_hw_control(adapter
);
3219 if ((adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) ||
3220 (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
)) {
3221 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3222 gpie
= (IXGBE_GPIE_MSIX_MODE
| IXGBE_GPIE_EIAME
|
3223 IXGBE_GPIE_PBA_SUPPORT
| IXGBE_GPIE_OCD
);
3228 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
3229 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
3230 gpie
|= IXGBE_GPIE_VTMODE_64
;
3232 /* XXX: to interrupt immediately for EICS writes, enable this */
3233 /* gpie |= IXGBE_GPIE_EIMEN; */
3234 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
3237 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3239 * use EIAM to auto-mask when MSI-X interrupt is asserted
3240 * this saves a register write for every interrupt
3242 switch (hw
->mac
.type
) {
3243 case ixgbe_mac_82598EB
:
3244 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
3247 case ixgbe_mac_82599EB
:
3248 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3249 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3253 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3254 * specifically only auto mask tx and rx interrupts */
3255 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
3258 /* Enable fan failure interrupt if media type is copper */
3259 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
3260 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
3261 gpie
|= IXGBE_SDP1_GPIEN
;
3262 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
3265 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
3266 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
3267 gpie
|= IXGBE_SDP1_GPIEN
;
3268 gpie
|= IXGBE_SDP2_GPIEN
;
3269 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
3273 /* adjust max frame to be able to do baby jumbo for FCoE */
3274 if ((netdev
->features
& NETIF_F_FCOE_MTU
) &&
3275 (max_frame
< IXGBE_FCOE_JUMBO_FRAME_SIZE
))
3276 max_frame
= IXGBE_FCOE_JUMBO_FRAME_SIZE
;
3278 #endif /* IXGBE_FCOE */
3279 mhadd
= IXGBE_READ_REG(hw
, IXGBE_MHADD
);
3280 if (max_frame
!= (mhadd
>> IXGBE_MHADD_MFS_SHIFT
)) {
3281 mhadd
&= ~IXGBE_MHADD_MFS_MASK
;
3282 mhadd
|= max_frame
<< IXGBE_MHADD_MFS_SHIFT
;
3284 IXGBE_WRITE_REG(hw
, IXGBE_MHADD
, mhadd
);
3287 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
3288 j
= adapter
->tx_ring
[i
]->reg_idx
;
3289 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
3290 if (adapter
->rx_itr_setting
== 0) {
3291 /* cannot set wthresh when itr==0 */
3292 txdctl
&= ~0x007F0000;
3294 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
3295 txdctl
|= (8 << 16);
3297 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
), txdctl
);
3300 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
3301 /* DMATXCTL.EN must be set after all Tx queue config is done */
3302 dmatxctl
= IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
);
3303 dmatxctl
|= IXGBE_DMATXCTL_TE
;
3304 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
, dmatxctl
);
3306 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
3307 j
= adapter
->tx_ring
[i
]->reg_idx
;
3308 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
3309 txdctl
|= IXGBE_TXDCTL_ENABLE
;
3310 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
), txdctl
);
3311 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
3313 /* poll for Tx Enable ready */
3316 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
3317 } while (--wait_loop
&&
3318 !(txdctl
& IXGBE_TXDCTL_ENABLE
));
3320 DPRINTK(DRV
, ERR
, "Could not enable "
3321 "Tx Queue %d\n", j
);
3325 for (i
= 0; i
< num_rx_rings
; i
++) {
3326 j
= adapter
->rx_ring
[i
]->reg_idx
;
3327 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
3328 /* enable PTHRESH=32 descriptors (half the internal cache)
3329 * and HTHRESH=0 descriptors (to minimize latency on fetch),
3330 * this also removes a pesky rx_no_buffer_count increment */
3332 rxdctl
|= IXGBE_RXDCTL_ENABLE
;
3333 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), rxdctl
);
3334 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
3335 ixgbe_rx_desc_queue_enable(adapter
, i
);
3337 /* enable all receives */
3338 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
3339 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3340 rxdctl
|= (IXGBE_RXCTRL_DMBYPS
| IXGBE_RXCTRL_RXEN
);
3342 rxdctl
|= IXGBE_RXCTRL_RXEN
;
3343 hw
->mac
.ops
.enable_rx_dma(hw
, rxdctl
);
3345 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
3346 ixgbe_configure_msix(adapter
);
3348 ixgbe_configure_msi_and_legacy(adapter
);
3350 /* enable the optics */
3351 if (hw
->phy
.multispeed_fiber
)
3352 hw
->mac
.ops
.enable_tx_laser(hw
);
3354 clear_bit(__IXGBE_DOWN
, &adapter
->state
);
3355 ixgbe_napi_enable_all(adapter
);
3357 /* clear any pending interrupts, may auto mask */
3358 IXGBE_READ_REG(hw
, IXGBE_EICR
);
3360 ixgbe_irq_enable(adapter
);
3363 * If this adapter has a fan, check to see if we had a failure
3364 * before we enabled the interrupt.
3366 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
3367 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
3368 if (esdp
& IXGBE_ESDP_SDP1
)
3370 "Fan has stopped, replace the adapter\n");
3374 * For hot-pluggable SFP+ devices, a new SFP+ module may have
3375 * arrived before interrupts were enabled but after probe. Such
3376 * devices wouldn't have their type identified yet. We need to
3377 * kick off the SFP+ module setup first, then try to bring up link.
3378 * If we're not hot-pluggable SFP+, we just need to configure link
3381 if (hw
->phy
.type
== ixgbe_phy_unknown
) {
3382 err
= hw
->phy
.ops
.identify(hw
);
3383 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
3385 * Take the device down and schedule the sfp tasklet
3386 * which will unregister_netdev and log it.
3388 ixgbe_down(adapter
);
3389 schedule_work(&adapter
->sfp_config_module_task
);
3394 if (ixgbe_is_sfp(hw
)) {
3395 ixgbe_sfp_link_config(adapter
);
3397 err
= ixgbe_non_sfp_link_config(hw
);
3399 DPRINTK(PROBE
, ERR
, "link_config FAILED %d\n", err
);
3402 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3403 set_bit(__IXGBE_FDIR_INIT_DONE
,
3404 &(adapter
->tx_ring
[i
]->reinit_state
));
3406 /* enable transmits */
3407 netif_tx_start_all_queues(netdev
);
3409 /* bring the link up in the watchdog, this could race with our first
3410 * link up interrupt but shouldn't be a problem */
3411 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
3412 adapter
->link_check_timeout
= jiffies
;
3413 mod_timer(&adapter
->watchdog_timer
, jiffies
);
3415 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3416 ctrl_ext
= IXGBE_READ_REG(hw
, IXGBE_CTRL_EXT
);
3417 ctrl_ext
|= IXGBE_CTRL_EXT_PFRSTD
;
3418 IXGBE_WRITE_REG(hw
, IXGBE_CTRL_EXT
, ctrl_ext
);
3423 void ixgbe_reinit_locked(struct ixgbe_adapter
*adapter
)
3425 WARN_ON(in_interrupt());
3426 while (test_and_set_bit(__IXGBE_RESETTING
, &adapter
->state
))
3428 ixgbe_down(adapter
);
3430 * If SR-IOV enabled then wait a bit before bringing the adapter
3431 * back up to give the VFs time to respond to the reset. The
3432 * two second wait is based upon the watchdog timer cycle in
3435 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
3438 clear_bit(__IXGBE_RESETTING
, &adapter
->state
);
3441 int ixgbe_up(struct ixgbe_adapter
*adapter
)
3443 /* hardware has been reset, we need to reload some things */
3444 ixgbe_configure(adapter
);
3446 return ixgbe_up_complete(adapter
);
3449 void ixgbe_reset(struct ixgbe_adapter
*adapter
)
3451 struct ixgbe_hw
*hw
= &adapter
->hw
;
3454 err
= hw
->mac
.ops
.init_hw(hw
);
3457 case IXGBE_ERR_SFP_NOT_PRESENT
:
3459 case IXGBE_ERR_MASTER_REQUESTS_PENDING
:
3460 dev_err(&adapter
->pdev
->dev
, "master disable timed out\n");
3462 case IXGBE_ERR_EEPROM_VERSION
:
3463 /* We are running on a pre-production device, log a warning */
3464 dev_warn(&adapter
->pdev
->dev
, "This device is a pre-production "
3465 "adapter/LOM. Please be aware there may be issues "
3466 "associated with your hardware. If you are "
3467 "experiencing problems please contact your Intel or "
3468 "hardware representative who provided you with this "
3472 dev_err(&adapter
->pdev
->dev
, "Hardware Error: %d\n", err
);
3475 /* reprogram the RAR[0] in case user changed it. */
3476 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
3481 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3482 * @adapter: board private structure
3483 * @rx_ring: ring to free buffers from
3485 static void ixgbe_clean_rx_ring(struct ixgbe_adapter
*adapter
,
3486 struct ixgbe_ring
*rx_ring
)
3488 struct pci_dev
*pdev
= adapter
->pdev
;
3492 /* Free all the Rx ring sk_buffs */
3494 for (i
= 0; i
< rx_ring
->count
; i
++) {
3495 struct ixgbe_rx_buffer
*rx_buffer_info
;
3497 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
3498 if (rx_buffer_info
->dma
) {
3499 dma_unmap_single(&pdev
->dev
, rx_buffer_info
->dma
,
3500 rx_ring
->rx_buf_len
,
3502 rx_buffer_info
->dma
= 0;
3504 if (rx_buffer_info
->skb
) {
3505 struct sk_buff
*skb
= rx_buffer_info
->skb
;
3506 rx_buffer_info
->skb
= NULL
;
3508 struct sk_buff
*this = skb
;
3509 if (IXGBE_RSC_CB(this)->delay_unmap
) {
3510 dma_unmap_single(&pdev
->dev
,
3511 IXGBE_RSC_CB(this)->dma
,
3512 rx_ring
->rx_buf_len
,
3514 IXGBE_RSC_CB(this)->dma
= 0;
3515 IXGBE_RSC_CB(skb
)->delay_unmap
= false;
3518 dev_kfree_skb(this);
3521 if (!rx_buffer_info
->page
)
3523 if (rx_buffer_info
->page_dma
) {
3524 dma_unmap_page(&pdev
->dev
, rx_buffer_info
->page_dma
,
3525 PAGE_SIZE
/ 2, DMA_FROM_DEVICE
);
3526 rx_buffer_info
->page_dma
= 0;
3528 put_page(rx_buffer_info
->page
);
3529 rx_buffer_info
->page
= NULL
;
3530 rx_buffer_info
->page_offset
= 0;
3533 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
3534 memset(rx_ring
->rx_buffer_info
, 0, size
);
3536 /* Zero out the descriptor ring */
3537 memset(rx_ring
->desc
, 0, rx_ring
->size
);
3539 rx_ring
->next_to_clean
= 0;
3540 rx_ring
->next_to_use
= 0;
3543 writel(0, adapter
->hw
.hw_addr
+ rx_ring
->head
);
3545 writel(0, adapter
->hw
.hw_addr
+ rx_ring
->tail
);
3549 * ixgbe_clean_tx_ring - Free Tx Buffers
3550 * @adapter: board private structure
3551 * @tx_ring: ring to be cleaned
3553 static void ixgbe_clean_tx_ring(struct ixgbe_adapter
*adapter
,
3554 struct ixgbe_ring
*tx_ring
)
3556 struct ixgbe_tx_buffer
*tx_buffer_info
;
3560 /* Free all the Tx ring sk_buffs */
3562 for (i
= 0; i
< tx_ring
->count
; i
++) {
3563 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
3564 ixgbe_unmap_and_free_tx_resource(adapter
, tx_buffer_info
);
3567 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
3568 memset(tx_ring
->tx_buffer_info
, 0, size
);
3570 /* Zero out the descriptor ring */
3571 memset(tx_ring
->desc
, 0, tx_ring
->size
);
3573 tx_ring
->next_to_use
= 0;
3574 tx_ring
->next_to_clean
= 0;
3577 writel(0, adapter
->hw
.hw_addr
+ tx_ring
->head
);
3579 writel(0, adapter
->hw
.hw_addr
+ tx_ring
->tail
);
3583 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3584 * @adapter: board private structure
3586 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter
*adapter
)
3590 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3591 ixgbe_clean_rx_ring(adapter
, adapter
->rx_ring
[i
]);
3595 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3596 * @adapter: board private structure
3598 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter
*adapter
)
3602 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3603 ixgbe_clean_tx_ring(adapter
, adapter
->tx_ring
[i
]);
3606 void ixgbe_down(struct ixgbe_adapter
*adapter
)
3608 struct net_device
*netdev
= adapter
->netdev
;
3609 struct ixgbe_hw
*hw
= &adapter
->hw
;
3614 /* signal that we are down to the interrupt handler */
3615 set_bit(__IXGBE_DOWN
, &adapter
->state
);
3617 /* power down the optics */
3618 if (hw
->phy
.multispeed_fiber
)
3619 hw
->mac
.ops
.disable_tx_laser(hw
);
3621 /* disable receive for all VFs and wait one second */
3622 if (adapter
->num_vfs
) {
3623 /* ping all the active vfs to let them know we are going down */
3624 ixgbe_ping_all_vfs(adapter
);
3626 /* Disable all VFTE/VFRE TX/RX */
3627 ixgbe_disable_tx_rx(adapter
);
3629 /* Mark all the VFs as inactive */
3630 for (i
= 0 ; i
< adapter
->num_vfs
; i
++)
3631 adapter
->vfinfo
[i
].clear_to_send
= 0;
3634 /* disable receives */
3635 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
3636 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
3638 IXGBE_WRITE_FLUSH(hw
);
3641 netif_tx_stop_all_queues(netdev
);
3643 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
3644 del_timer_sync(&adapter
->sfp_timer
);
3645 del_timer_sync(&adapter
->watchdog_timer
);
3646 cancel_work_sync(&adapter
->watchdog_task
);
3648 netif_carrier_off(netdev
);
3649 netif_tx_disable(netdev
);
3651 ixgbe_irq_disable(adapter
);
3653 ixgbe_napi_disable_all(adapter
);
3655 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
3656 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
3657 cancel_work_sync(&adapter
->fdir_reinit_task
);
3659 /* disable transmits in the hardware now that interrupts are off */
3660 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
3661 j
= adapter
->tx_ring
[i
]->reg_idx
;
3662 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
3663 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
),
3664 (txdctl
& ~IXGBE_TXDCTL_ENABLE
));
3666 /* Disable the Tx DMA engine on 82599 */
3667 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
3668 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
,
3669 (IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
) &
3670 ~IXGBE_DMATXCTL_TE
));
3672 /* clear n-tuple filters that are cached */
3673 ethtool_ntuple_flush(netdev
);
3675 if (!pci_channel_offline(adapter
->pdev
))
3676 ixgbe_reset(adapter
);
3677 ixgbe_clean_all_tx_rings(adapter
);
3678 ixgbe_clean_all_rx_rings(adapter
);
3680 #ifdef CONFIG_IXGBE_DCA
3681 /* since we reset the hardware DCA settings were cleared */
3682 ixgbe_setup_dca(adapter
);
3687 * ixgbe_poll - NAPI Rx polling callback
3688 * @napi: structure for representing this polling device
3689 * @budget: how many packets driver is allowed to clean
3691 * This function is used for legacy and MSI, NAPI mode
3693 static int ixgbe_poll(struct napi_struct
*napi
, int budget
)
3695 struct ixgbe_q_vector
*q_vector
=
3696 container_of(napi
, struct ixgbe_q_vector
, napi
);
3697 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
3698 int tx_clean_complete
, work_done
= 0;
3700 #ifdef CONFIG_IXGBE_DCA
3701 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
3702 ixgbe_update_tx_dca(adapter
, adapter
->tx_ring
[0]);
3703 ixgbe_update_rx_dca(adapter
, adapter
->rx_ring
[0]);
3707 tx_clean_complete
= ixgbe_clean_tx_irq(q_vector
, adapter
->tx_ring
[0]);
3708 ixgbe_clean_rx_irq(q_vector
, adapter
->rx_ring
[0], &work_done
, budget
);
3710 if (!tx_clean_complete
)
3713 /* If budget not fully consumed, exit the polling mode */
3714 if (work_done
< budget
) {
3715 napi_complete(napi
);
3716 if (adapter
->rx_itr_setting
& 1)
3717 ixgbe_set_itr(adapter
);
3718 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
3719 ixgbe_irq_enable_queues(adapter
, IXGBE_EIMS_RTX_QUEUE
);
3725 * ixgbe_tx_timeout - Respond to a Tx Hang
3726 * @netdev: network interface device structure
3728 static void ixgbe_tx_timeout(struct net_device
*netdev
)
3730 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3732 /* Do the reset outside of interrupt context */
3733 schedule_work(&adapter
->reset_task
);
3736 static void ixgbe_reset_task(struct work_struct
*work
)
3738 struct ixgbe_adapter
*adapter
;
3739 adapter
= container_of(work
, struct ixgbe_adapter
, reset_task
);
3741 /* If we're already down or resetting, just bail */
3742 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
3743 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
3746 adapter
->tx_timeout_count
++;
3748 ixgbe_dump(adapter
);
3749 netdev_err(adapter
->netdev
, "Reset adapter\n");
3750 ixgbe_reinit_locked(adapter
);
3753 #ifdef CONFIG_IXGBE_DCB
3754 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter
*adapter
)
3757 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_DCB
];
3759 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
))
3763 adapter
->num_rx_queues
= f
->indices
;
3764 adapter
->num_tx_queues
= f
->indices
;
3772 * ixgbe_set_rss_queues: Allocate queues for RSS
3773 * @adapter: board private structure to initialize
3775 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3776 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3779 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter
*adapter
)
3782 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_RSS
];
3784 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3786 adapter
->num_rx_queues
= f
->indices
;
3787 adapter
->num_tx_queues
= f
->indices
;
3797 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3798 * @adapter: board private structure to initialize
3800 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3801 * to the original CPU that initiated the Tx session. This runs in addition
3802 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3803 * Rx load across CPUs using RSS.
3806 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter
*adapter
)
3809 struct ixgbe_ring_feature
*f_fdir
= &adapter
->ring_feature
[RING_F_FDIR
];
3811 f_fdir
->indices
= min((int)num_online_cpus(), f_fdir
->indices
);
3814 /* Flow Director must have RSS enabled */
3815 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
&&
3816 ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
3817 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)))) {
3818 adapter
->num_tx_queues
= f_fdir
->indices
;
3819 adapter
->num_rx_queues
= f_fdir
->indices
;
3822 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
3823 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
3830 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3831 * @adapter: board private structure to initialize
3833 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3834 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3835 * rx queues out of the max number of rx queues, instead, it is used as the
3836 * index of the first rx queue used by FCoE.
3839 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter
*adapter
)
3842 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
3844 f
->indices
= min((int)num_online_cpus(), f
->indices
);
3845 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
3846 adapter
->num_rx_queues
= 1;
3847 adapter
->num_tx_queues
= 1;
3848 #ifdef CONFIG_IXGBE_DCB
3849 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
3850 DPRINTK(PROBE
, INFO
, "FCoE enabled with DCB\n");
3851 ixgbe_set_dcb_queues(adapter
);
3854 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3855 DPRINTK(PROBE
, INFO
, "FCoE enabled with RSS\n");
3856 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
3857 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))
3858 ixgbe_set_fdir_queues(adapter
);
3860 ixgbe_set_rss_queues(adapter
);
3862 /* adding FCoE rx rings to the end */
3863 f
->mask
= adapter
->num_rx_queues
;
3864 adapter
->num_rx_queues
+= f
->indices
;
3865 adapter
->num_tx_queues
+= f
->indices
;
3873 #endif /* IXGBE_FCOE */
3875 * ixgbe_set_sriov_queues: Allocate queues for IOV use
3876 * @adapter: board private structure to initialize
3878 * IOV doesn't actually use anything, so just NAK the
3879 * request for now and let the other queue routines
3880 * figure out what to do.
3882 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter
*adapter
)
3888 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3889 * @adapter: board private structure to initialize
3891 * This is the top level queue allocation routine. The order here is very
3892 * important, starting with the "most" number of features turned on at once,
3893 * and ending with the smallest set of features. This way large combinations
3894 * can be allocated if they're turned on, and smaller combinations are the
3895 * fallthrough conditions.
3898 static void ixgbe_set_num_queues(struct ixgbe_adapter
*adapter
)
3900 /* Start with base case */
3901 adapter
->num_rx_queues
= 1;
3902 adapter
->num_tx_queues
= 1;
3903 adapter
->num_rx_pools
= adapter
->num_rx_queues
;
3904 adapter
->num_rx_queues_per_pool
= 1;
3906 if (ixgbe_set_sriov_queues(adapter
))
3910 if (ixgbe_set_fcoe_queues(adapter
))
3913 #endif /* IXGBE_FCOE */
3914 #ifdef CONFIG_IXGBE_DCB
3915 if (ixgbe_set_dcb_queues(adapter
))
3919 if (ixgbe_set_fdir_queues(adapter
))
3922 if (ixgbe_set_rss_queues(adapter
))
3925 /* fallback to base case */
3926 adapter
->num_rx_queues
= 1;
3927 adapter
->num_tx_queues
= 1;
3930 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3931 adapter
->netdev
->real_num_tx_queues
= adapter
->num_tx_queues
;
3934 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter
*adapter
,
3937 int err
, vector_threshold
;
3939 /* We'll want at least 3 (vector_threshold):
3942 * 3) Other (Link Status Change, etc.)
3943 * 4) TCP Timer (optional)
3945 vector_threshold
= MIN_MSIX_COUNT
;
3947 /* The more we get, the more we will assign to Tx/Rx Cleanup
3948 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3949 * Right now, we simply care about how many we'll get; we'll
3950 * set them up later while requesting irq's.
3952 while (vectors
>= vector_threshold
) {
3953 err
= pci_enable_msix(adapter
->pdev
, adapter
->msix_entries
,
3955 if (!err
) /* Success in acquiring all requested vectors. */
3958 vectors
= 0; /* Nasty failure, quit now */
3959 else /* err == number of vectors we should try again with */
3963 if (vectors
< vector_threshold
) {
3964 /* Can't allocate enough MSI-X interrupts? Oh well.
3965 * This just means we'll go with either a single MSI
3966 * vector or fall back to legacy interrupts.
3968 DPRINTK(HW
, DEBUG
, "Unable to allocate MSI-X interrupts\n");
3969 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
3970 kfree(adapter
->msix_entries
);
3971 adapter
->msix_entries
= NULL
;
3973 adapter
->flags
|= IXGBE_FLAG_MSIX_ENABLED
; /* Woot! */
3975 * Adjust for only the vectors we'll use, which is minimum
3976 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3977 * vectors we were allocated.
3979 adapter
->num_msix_vectors
= min(vectors
,
3980 adapter
->max_msix_q_vectors
+ NON_Q_VECTORS
);
3985 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3986 * @adapter: board private structure to initialize
3988 * Cache the descriptor ring offsets for RSS to the assigned rings.
3991 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter
*adapter
)
3996 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3997 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3998 adapter
->rx_ring
[i
]->reg_idx
= i
;
3999 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4000 adapter
->tx_ring
[i
]->reg_idx
= i
;
4009 #ifdef CONFIG_IXGBE_DCB
4011 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4012 * @adapter: board private structure to initialize
4014 * Cache the descriptor ring offsets for DCB to the assigned rings.
4017 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter
*adapter
)
4021 int dcb_i
= adapter
->ring_feature
[RING_F_DCB
].indices
;
4023 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
4024 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
4025 /* the number of queues is assumed to be symmetric */
4026 for (i
= 0; i
< dcb_i
; i
++) {
4027 adapter
->rx_ring
[i
]->reg_idx
= i
<< 3;
4028 adapter
->tx_ring
[i
]->reg_idx
= i
<< 2;
4031 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
4034 * Tx TC0 starts at: descriptor queue 0
4035 * Tx TC1 starts at: descriptor queue 32
4036 * Tx TC2 starts at: descriptor queue 64
4037 * Tx TC3 starts at: descriptor queue 80
4038 * Tx TC4 starts at: descriptor queue 96
4039 * Tx TC5 starts at: descriptor queue 104
4040 * Tx TC6 starts at: descriptor queue 112
4041 * Tx TC7 starts at: descriptor queue 120
4043 * Rx TC0-TC7 are offset by 16 queues each
4045 for (i
= 0; i
< 3; i
++) {
4046 adapter
->tx_ring
[i
]->reg_idx
= i
<< 5;
4047 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
4049 for ( ; i
< 5; i
++) {
4050 adapter
->tx_ring
[i
]->reg_idx
=
4052 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
4054 for ( ; i
< dcb_i
; i
++) {
4055 adapter
->tx_ring
[i
]->reg_idx
=
4057 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
4061 } else if (dcb_i
== 4) {
4063 * Tx TC0 starts at: descriptor queue 0
4064 * Tx TC1 starts at: descriptor queue 64
4065 * Tx TC2 starts at: descriptor queue 96
4066 * Tx TC3 starts at: descriptor queue 112
4068 * Rx TC0-TC3 are offset by 32 queues each
4070 adapter
->tx_ring
[0]->reg_idx
= 0;
4071 adapter
->tx_ring
[1]->reg_idx
= 64;
4072 adapter
->tx_ring
[2]->reg_idx
= 96;
4073 adapter
->tx_ring
[3]->reg_idx
= 112;
4074 for (i
= 0 ; i
< dcb_i
; i
++)
4075 adapter
->rx_ring
[i
]->reg_idx
= i
<< 5;
4093 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4094 * @adapter: board private structure to initialize
4096 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4099 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter
*adapter
)
4104 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
&&
4105 ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
4106 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))) {
4107 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4108 adapter
->rx_ring
[i
]->reg_idx
= i
;
4109 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4110 adapter
->tx_ring
[i
]->reg_idx
= i
;
4119 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4120 * @adapter: board private structure to initialize
4122 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4125 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter
*adapter
)
4127 int i
, fcoe_rx_i
= 0, fcoe_tx_i
= 0;
4129 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
4131 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
4132 #ifdef CONFIG_IXGBE_DCB
4133 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
4134 struct ixgbe_fcoe
*fcoe
= &adapter
->fcoe
;
4136 ixgbe_cache_ring_dcb(adapter
);
4137 /* find out queues in TC for FCoE */
4138 fcoe_rx_i
= adapter
->rx_ring
[fcoe
->tc
]->reg_idx
+ 1;
4139 fcoe_tx_i
= adapter
->tx_ring
[fcoe
->tc
]->reg_idx
+ 1;
4141 * In 82599, the number of Tx queues for each traffic
4142 * class for both 8-TC and 4-TC modes are:
4143 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4144 * 8 TCs: 32 32 16 16 8 8 8 8
4145 * 4 TCs: 64 64 32 32
4146 * We have max 8 queues for FCoE, where 8 the is
4147 * FCoE redirection table size. If TC for FCoE is
4148 * less than or equal to TC3, we have enough queues
4149 * to add max of 8 queues for FCoE, so we start FCoE
4150 * tx descriptor from the next one, i.e., reg_idx + 1.
4151 * If TC for FCoE is above TC3, implying 8 TC mode,
4152 * and we need 8 for FCoE, we have to take all queues
4153 * in that traffic class for FCoE.
4155 if ((f
->indices
== IXGBE_FCRETA_SIZE
) && (fcoe
->tc
> 3))
4158 #endif /* CONFIG_IXGBE_DCB */
4159 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4160 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
4161 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))
4162 ixgbe_cache_ring_fdir(adapter
);
4164 ixgbe_cache_ring_rss(adapter
);
4166 fcoe_rx_i
= f
->mask
;
4167 fcoe_tx_i
= f
->mask
;
4169 for (i
= 0; i
< f
->indices
; i
++, fcoe_rx_i
++, fcoe_tx_i
++) {
4170 adapter
->rx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_rx_i
;
4171 adapter
->tx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_tx_i
;
4178 #endif /* IXGBE_FCOE */
4180 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4181 * @adapter: board private structure to initialize
4183 * SR-IOV doesn't use any descriptor rings but changes the default if
4184 * no other mapping is used.
4187 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter
*adapter
)
4189 adapter
->rx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
4190 adapter
->tx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
4191 if (adapter
->num_vfs
)
4198 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4199 * @adapter: board private structure to initialize
4201 * Once we know the feature-set enabled for the device, we'll cache
4202 * the register offset the descriptor ring is assigned to.
4204 * Note, the order the various feature calls is important. It must start with
4205 * the "most" features enabled at the same time, then trickle down to the
4206 * least amount of features turned on at once.
4208 static void ixgbe_cache_ring_register(struct ixgbe_adapter
*adapter
)
4210 /* start with default case */
4211 adapter
->rx_ring
[0]->reg_idx
= 0;
4212 adapter
->tx_ring
[0]->reg_idx
= 0;
4214 if (ixgbe_cache_ring_sriov(adapter
))
4218 if (ixgbe_cache_ring_fcoe(adapter
))
4221 #endif /* IXGBE_FCOE */
4222 #ifdef CONFIG_IXGBE_DCB
4223 if (ixgbe_cache_ring_dcb(adapter
))
4227 if (ixgbe_cache_ring_fdir(adapter
))
4230 if (ixgbe_cache_ring_rss(adapter
))
4235 * ixgbe_alloc_queues - Allocate memory for all rings
4236 * @adapter: board private structure to initialize
4238 * We allocate one ring per queue at run-time since we don't know the
4239 * number of queues at compile-time. The polling_netdev array is
4240 * intended for Multiqueue, but should work fine with a single queue.
4242 static int ixgbe_alloc_queues(struct ixgbe_adapter
*adapter
)
4245 int orig_node
= adapter
->node
;
4247 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4248 struct ixgbe_ring
*ring
= adapter
->tx_ring
[i
];
4249 if (orig_node
== -1) {
4250 int cur_node
= next_online_node(adapter
->node
);
4251 if (cur_node
== MAX_NUMNODES
)
4252 cur_node
= first_online_node
;
4253 adapter
->node
= cur_node
;
4255 ring
= kzalloc_node(sizeof(struct ixgbe_ring
), GFP_KERNEL
,
4258 ring
= kzalloc(sizeof(struct ixgbe_ring
), GFP_KERNEL
);
4260 goto err_tx_ring_allocation
;
4261 ring
->count
= adapter
->tx_ring_count
;
4262 ring
->queue_index
= i
;
4263 ring
->numa_node
= adapter
->node
;
4265 adapter
->tx_ring
[i
] = ring
;
4268 /* Restore the adapter's original node */
4269 adapter
->node
= orig_node
;
4271 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
4272 struct ixgbe_ring
*ring
= adapter
->rx_ring
[i
];
4273 if (orig_node
== -1) {
4274 int cur_node
= next_online_node(adapter
->node
);
4275 if (cur_node
== MAX_NUMNODES
)
4276 cur_node
= first_online_node
;
4277 adapter
->node
= cur_node
;
4279 ring
= kzalloc_node(sizeof(struct ixgbe_ring
), GFP_KERNEL
,
4282 ring
= kzalloc(sizeof(struct ixgbe_ring
), GFP_KERNEL
);
4284 goto err_rx_ring_allocation
;
4285 ring
->count
= adapter
->rx_ring_count
;
4286 ring
->queue_index
= i
;
4287 ring
->numa_node
= adapter
->node
;
4289 adapter
->rx_ring
[i
] = ring
;
4292 /* Restore the adapter's original node */
4293 adapter
->node
= orig_node
;
4295 ixgbe_cache_ring_register(adapter
);
4299 err_rx_ring_allocation
:
4300 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4301 kfree(adapter
->tx_ring
[i
]);
4302 err_tx_ring_allocation
:
4307 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4308 * @adapter: board private structure to initialize
4310 * Attempt to configure the interrupts using the best available
4311 * capabilities of the hardware and the kernel.
4313 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter
*adapter
)
4315 struct ixgbe_hw
*hw
= &adapter
->hw
;
4317 int vector
, v_budget
;
4320 * It's easy to be greedy for MSI-X vectors, but it really
4321 * doesn't do us much good if we have a lot more vectors
4322 * than CPU's. So let's be conservative and only ask for
4323 * (roughly) the same number of vectors as there are CPU's.
4325 v_budget
= min(adapter
->num_rx_queues
+ adapter
->num_tx_queues
,
4326 (int)num_online_cpus()) + NON_Q_VECTORS
;
4329 * At the same time, hardware can only support a maximum of
4330 * hw.mac->max_msix_vectors vectors. With features
4331 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4332 * descriptor queues supported by our device. Thus, we cap it off in
4333 * those rare cases where the cpu count also exceeds our vector limit.
4335 v_budget
= min(v_budget
, (int)hw
->mac
.max_msix_vectors
);
4337 /* A failure in MSI-X entry allocation isn't fatal, but it does
4338 * mean we disable MSI-X capabilities of the adapter. */
4339 adapter
->msix_entries
= kcalloc(v_budget
,
4340 sizeof(struct msix_entry
), GFP_KERNEL
);
4341 if (adapter
->msix_entries
) {
4342 for (vector
= 0; vector
< v_budget
; vector
++)
4343 adapter
->msix_entries
[vector
].entry
= vector
;
4345 ixgbe_acquire_msix_vectors(adapter
, v_budget
);
4347 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
4351 adapter
->flags
&= ~IXGBE_FLAG_DCB_ENABLED
;
4352 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
4353 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4354 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
4355 adapter
->atr_sample_rate
= 0;
4356 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
4357 ixgbe_disable_sriov(adapter
);
4359 ixgbe_set_num_queues(adapter
);
4361 err
= pci_enable_msi(adapter
->pdev
);
4363 adapter
->flags
|= IXGBE_FLAG_MSI_ENABLED
;
4365 DPRINTK(HW
, DEBUG
, "Unable to allocate MSI interrupt, "
4366 "falling back to legacy. Error: %d\n", err
);
4376 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4377 * @adapter: board private structure to initialize
4379 * We allocate one q_vector per queue interrupt. If allocation fails we
4382 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter
*adapter
)
4384 int q_idx
, num_q_vectors
;
4385 struct ixgbe_q_vector
*q_vector
;
4387 int (*poll
)(struct napi_struct
*, int);
4389 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4390 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4391 napi_vectors
= adapter
->num_rx_queues
;
4392 poll
= &ixgbe_clean_rxtx_many
;
4399 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
4400 q_vector
= kzalloc_node(sizeof(struct ixgbe_q_vector
),
4401 GFP_KERNEL
, adapter
->node
);
4403 q_vector
= kzalloc(sizeof(struct ixgbe_q_vector
),
4407 q_vector
->adapter
= adapter
;
4408 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
4409 q_vector
->eitr
= adapter
->tx_eitr_param
;
4411 q_vector
->eitr
= adapter
->rx_eitr_param
;
4412 q_vector
->v_idx
= q_idx
;
4413 netif_napi_add(adapter
->netdev
, &q_vector
->napi
, (*poll
), 64);
4414 adapter
->q_vector
[q_idx
] = q_vector
;
4422 q_vector
= adapter
->q_vector
[q_idx
];
4423 netif_napi_del(&q_vector
->napi
);
4425 adapter
->q_vector
[q_idx
] = NULL
;
4431 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4432 * @adapter: board private structure to initialize
4434 * This function frees the memory allocated to the q_vectors. In addition if
4435 * NAPI is enabled it will delete any references to the NAPI struct prior
4436 * to freeing the q_vector.
4438 static void ixgbe_free_q_vectors(struct ixgbe_adapter
*adapter
)
4440 int q_idx
, num_q_vectors
;
4442 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
4443 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4447 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
4448 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[q_idx
];
4449 adapter
->q_vector
[q_idx
] = NULL
;
4450 netif_napi_del(&q_vector
->napi
);
4455 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter
*adapter
)
4457 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4458 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
4459 pci_disable_msix(adapter
->pdev
);
4460 kfree(adapter
->msix_entries
);
4461 adapter
->msix_entries
= NULL
;
4462 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
4463 adapter
->flags
&= ~IXGBE_FLAG_MSI_ENABLED
;
4464 pci_disable_msi(adapter
->pdev
);
4469 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4470 * @adapter: board private structure to initialize
4472 * We determine which interrupt scheme to use based on...
4473 * - Kernel support (MSI, MSI-X)
4474 * - which can be user-defined (via MODULE_PARAM)
4475 * - Hardware queue count (num_*_queues)
4476 * - defined by miscellaneous hardware support/features (RSS, etc.)
4478 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter
*adapter
)
4482 /* Number of supported queues */
4483 ixgbe_set_num_queues(adapter
);
4485 err
= ixgbe_set_interrupt_capability(adapter
);
4487 DPRINTK(PROBE
, ERR
, "Unable to setup interrupt capabilities\n");
4488 goto err_set_interrupt
;
4491 err
= ixgbe_alloc_q_vectors(adapter
);
4493 DPRINTK(PROBE
, ERR
, "Unable to allocate memory for queue "
4495 goto err_alloc_q_vectors
;
4498 err
= ixgbe_alloc_queues(adapter
);
4500 DPRINTK(PROBE
, ERR
, "Unable to allocate memory for queues\n");
4501 goto err_alloc_queues
;
4504 DPRINTK(DRV
, INFO
, "Multiqueue %s: Rx Queue count = %u, "
4505 "Tx Queue count = %u\n",
4506 (adapter
->num_rx_queues
> 1) ? "Enabled" :
4507 "Disabled", adapter
->num_rx_queues
, adapter
->num_tx_queues
);
4509 set_bit(__IXGBE_DOWN
, &adapter
->state
);
4514 ixgbe_free_q_vectors(adapter
);
4515 err_alloc_q_vectors
:
4516 ixgbe_reset_interrupt_capability(adapter
);
4522 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4523 * @adapter: board private structure to clear interrupt scheme on
4525 * We go through and clear interrupt specific resources and reset the structure
4526 * to pre-load conditions
4528 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter
*adapter
)
4532 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4533 kfree(adapter
->tx_ring
[i
]);
4534 adapter
->tx_ring
[i
] = NULL
;
4536 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
4537 kfree(adapter
->rx_ring
[i
]);
4538 adapter
->rx_ring
[i
] = NULL
;
4541 ixgbe_free_q_vectors(adapter
);
4542 ixgbe_reset_interrupt_capability(adapter
);
4546 * ixgbe_sfp_timer - worker thread to find a missing module
4547 * @data: pointer to our adapter struct
4549 static void ixgbe_sfp_timer(unsigned long data
)
4551 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
4554 * Do the sfp_timer outside of interrupt context due to the
4555 * delays that sfp+ detection requires
4557 schedule_work(&adapter
->sfp_task
);
4561 * ixgbe_sfp_task - worker thread to find a missing module
4562 * @work: pointer to work_struct containing our data
4564 static void ixgbe_sfp_task(struct work_struct
*work
)
4566 struct ixgbe_adapter
*adapter
= container_of(work
,
4567 struct ixgbe_adapter
,
4569 struct ixgbe_hw
*hw
= &adapter
->hw
;
4571 if ((hw
->phy
.type
== ixgbe_phy_nl
) &&
4572 (hw
->phy
.sfp_type
== ixgbe_sfp_type_not_present
)) {
4573 s32 ret
= hw
->phy
.ops
.identify_sfp(hw
);
4574 if (ret
== IXGBE_ERR_SFP_NOT_PRESENT
)
4576 ret
= hw
->phy
.ops
.reset(hw
);
4577 if (ret
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
4578 dev_err(&adapter
->pdev
->dev
, "failed to initialize "
4579 "because an unsupported SFP+ module type "
4581 "Reload the driver after installing a "
4582 "supported module.\n");
4583 unregister_netdev(adapter
->netdev
);
4585 DPRINTK(PROBE
, INFO
, "detected SFP+: %d\n",
4588 /* don't need this routine any more */
4589 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
4593 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
))
4594 mod_timer(&adapter
->sfp_timer
,
4595 round_jiffies(jiffies
+ (2 * HZ
)));
4599 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4600 * @adapter: board private structure to initialize
4602 * ixgbe_sw_init initializes the Adapter private data structure.
4603 * Fields are initialized based on PCI device information and
4604 * OS network device settings (MTU size).
4606 static int __devinit
ixgbe_sw_init(struct ixgbe_adapter
*adapter
)
4608 struct ixgbe_hw
*hw
= &adapter
->hw
;
4609 struct pci_dev
*pdev
= adapter
->pdev
;
4610 struct net_device
*dev
= adapter
->netdev
;
4612 #ifdef CONFIG_IXGBE_DCB
4614 struct tc_configuration
*tc
;
4617 /* PCI config space info */
4619 hw
->vendor_id
= pdev
->vendor
;
4620 hw
->device_id
= pdev
->device
;
4621 hw
->revision_id
= pdev
->revision
;
4622 hw
->subsystem_vendor_id
= pdev
->subsystem_vendor
;
4623 hw
->subsystem_device_id
= pdev
->subsystem_device
;
4625 /* Set capability flags */
4626 rss
= min(IXGBE_MAX_RSS_INDICES
, (int)num_online_cpus());
4627 adapter
->ring_feature
[RING_F_RSS
].indices
= rss
;
4628 adapter
->flags
|= IXGBE_FLAG_RSS_ENABLED
;
4629 adapter
->ring_feature
[RING_F_DCB
].indices
= IXGBE_MAX_DCB_INDICES
;
4630 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
4631 if (hw
->device_id
== IXGBE_DEV_ID_82598AT
)
4632 adapter
->flags
|= IXGBE_FLAG_FAN_FAIL_CAPABLE
;
4633 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82598
;
4634 } else if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
4635 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82599
;
4636 adapter
->flags2
|= IXGBE_FLAG2_RSC_CAPABLE
;
4637 adapter
->flags2
|= IXGBE_FLAG2_RSC_ENABLED
;
4638 if (dev
->features
& NETIF_F_NTUPLE
) {
4639 /* Flow Director perfect filter enabled */
4640 adapter
->flags
|= IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
4641 adapter
->atr_sample_rate
= 0;
4642 spin_lock_init(&adapter
->fdir_perfect_lock
);
4644 /* Flow Director hash filters enabled */
4645 adapter
->flags
|= IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4646 adapter
->atr_sample_rate
= 20;
4648 adapter
->ring_feature
[RING_F_FDIR
].indices
=
4649 IXGBE_MAX_FDIR_INDICES
;
4650 adapter
->fdir_pballoc
= 0;
4652 adapter
->flags
|= IXGBE_FLAG_FCOE_CAPABLE
;
4653 adapter
->flags
&= ~IXGBE_FLAG_FCOE_ENABLED
;
4654 adapter
->ring_feature
[RING_F_FCOE
].indices
= 0;
4655 #ifdef CONFIG_IXGBE_DCB
4656 /* Default traffic class to use for FCoE */
4657 adapter
->fcoe
.tc
= IXGBE_FCOE_DEFTC
;
4659 #endif /* IXGBE_FCOE */
4662 #ifdef CONFIG_IXGBE_DCB
4663 /* Configure DCB traffic classes */
4664 for (j
= 0; j
< MAX_TRAFFIC_CLASS
; j
++) {
4665 tc
= &adapter
->dcb_cfg
.tc_config
[j
];
4666 tc
->path
[DCB_TX_CONFIG
].bwg_id
= 0;
4667 tc
->path
[DCB_TX_CONFIG
].bwg_percent
= 12 + (j
& 1);
4668 tc
->path
[DCB_RX_CONFIG
].bwg_id
= 0;
4669 tc
->path
[DCB_RX_CONFIG
].bwg_percent
= 12 + (j
& 1);
4670 tc
->dcb_pfc
= pfc_disabled
;
4672 adapter
->dcb_cfg
.bw_percentage
[DCB_TX_CONFIG
][0] = 100;
4673 adapter
->dcb_cfg
.bw_percentage
[DCB_RX_CONFIG
][0] = 100;
4674 adapter
->dcb_cfg
.rx_pba_cfg
= pba_equal
;
4675 adapter
->dcb_cfg
.pfc_mode_enable
= false;
4676 adapter
->dcb_cfg
.round_robin_enable
= false;
4677 adapter
->dcb_set_bitmap
= 0x00;
4678 ixgbe_copy_dcb_cfg(&adapter
->dcb_cfg
, &adapter
->temp_dcb_cfg
,
4679 adapter
->ring_feature
[RING_F_DCB
].indices
);
4683 /* default flow control settings */
4684 hw
->fc
.requested_mode
= ixgbe_fc_full
;
4685 hw
->fc
.current_mode
= ixgbe_fc_full
; /* init for ethtool output */
4687 adapter
->last_lfc_mode
= hw
->fc
.current_mode
;
4689 hw
->fc
.high_water
= IXGBE_DEFAULT_FCRTH
;
4690 hw
->fc
.low_water
= IXGBE_DEFAULT_FCRTL
;
4691 hw
->fc
.pause_time
= IXGBE_DEFAULT_FCPAUSE
;
4692 hw
->fc
.send_xon
= true;
4693 hw
->fc
.disable_fc_autoneg
= false;
4695 /* enable itr by default in dynamic mode */
4696 adapter
->rx_itr_setting
= 1;
4697 adapter
->rx_eitr_param
= 20000;
4698 adapter
->tx_itr_setting
= 1;
4699 adapter
->tx_eitr_param
= 10000;
4701 /* set defaults for eitr in MegaBytes */
4702 adapter
->eitr_low
= 10;
4703 adapter
->eitr_high
= 20;
4705 /* set default ring sizes */
4706 adapter
->tx_ring_count
= IXGBE_DEFAULT_TXD
;
4707 adapter
->rx_ring_count
= IXGBE_DEFAULT_RXD
;
4709 /* initialize eeprom parameters */
4710 if (ixgbe_init_eeprom_params_generic(hw
)) {
4711 dev_err(&pdev
->dev
, "EEPROM initialization failed\n");
4715 /* enable rx csum by default */
4716 adapter
->flags
|= IXGBE_FLAG_RX_CSUM_ENABLED
;
4718 /* get assigned NUMA node */
4719 adapter
->node
= dev_to_node(&pdev
->dev
);
4721 set_bit(__IXGBE_DOWN
, &adapter
->state
);
4727 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4728 * @adapter: board private structure
4729 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4731 * Return 0 on success, negative on failure
4733 int ixgbe_setup_tx_resources(struct ixgbe_adapter
*adapter
,
4734 struct ixgbe_ring
*tx_ring
)
4736 struct pci_dev
*pdev
= adapter
->pdev
;
4739 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
4740 tx_ring
->tx_buffer_info
= vmalloc_node(size
, tx_ring
->numa_node
);
4741 if (!tx_ring
->tx_buffer_info
)
4742 tx_ring
->tx_buffer_info
= vmalloc(size
);
4743 if (!tx_ring
->tx_buffer_info
)
4745 memset(tx_ring
->tx_buffer_info
, 0, size
);
4747 /* round up to nearest 4K */
4748 tx_ring
->size
= tx_ring
->count
* sizeof(union ixgbe_adv_tx_desc
);
4749 tx_ring
->size
= ALIGN(tx_ring
->size
, 4096);
4751 tx_ring
->desc
= dma_alloc_coherent(&pdev
->dev
, tx_ring
->size
,
4752 &tx_ring
->dma
, GFP_KERNEL
);
4756 tx_ring
->next_to_use
= 0;
4757 tx_ring
->next_to_clean
= 0;
4758 tx_ring
->work_limit
= tx_ring
->count
;
4762 vfree(tx_ring
->tx_buffer_info
);
4763 tx_ring
->tx_buffer_info
= NULL
;
4764 DPRINTK(PROBE
, ERR
, "Unable to allocate memory for the transmit "
4765 "descriptor ring\n");
4770 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4771 * @adapter: board private structure
4773 * If this function returns with an error, then it's possible one or
4774 * more of the rings is populated (while the rest are not). It is the
4775 * callers duty to clean those orphaned rings.
4777 * Return 0 on success, negative on failure
4779 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter
*adapter
)
4783 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4784 err
= ixgbe_setup_tx_resources(adapter
, adapter
->tx_ring
[i
]);
4787 DPRINTK(PROBE
, ERR
, "Allocation for Tx Queue %u failed\n", i
);
4795 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4796 * @adapter: board private structure
4797 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4799 * Returns 0 on success, negative on failure
4801 int ixgbe_setup_rx_resources(struct ixgbe_adapter
*adapter
,
4802 struct ixgbe_ring
*rx_ring
)
4804 struct pci_dev
*pdev
= adapter
->pdev
;
4807 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
4808 rx_ring
->rx_buffer_info
= vmalloc_node(size
, adapter
->node
);
4809 if (!rx_ring
->rx_buffer_info
)
4810 rx_ring
->rx_buffer_info
= vmalloc(size
);
4811 if (!rx_ring
->rx_buffer_info
) {
4813 "vmalloc allocation failed for the rx desc ring\n");
4816 memset(rx_ring
->rx_buffer_info
, 0, size
);
4818 /* Round up to nearest 4K */
4819 rx_ring
->size
= rx_ring
->count
* sizeof(union ixgbe_adv_rx_desc
);
4820 rx_ring
->size
= ALIGN(rx_ring
->size
, 4096);
4822 rx_ring
->desc
= dma_alloc_coherent(&pdev
->dev
, rx_ring
->size
,
4823 &rx_ring
->dma
, GFP_KERNEL
);
4825 if (!rx_ring
->desc
) {
4827 "Memory allocation failed for the rx desc ring\n");
4828 vfree(rx_ring
->rx_buffer_info
);
4832 rx_ring
->next_to_clean
= 0;
4833 rx_ring
->next_to_use
= 0;
4842 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4843 * @adapter: board private structure
4845 * If this function returns with an error, then it's possible one or
4846 * more of the rings is populated (while the rest are not). It is the
4847 * callers duty to clean those orphaned rings.
4849 * Return 0 on success, negative on failure
4852 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter
*adapter
)
4856 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
4857 err
= ixgbe_setup_rx_resources(adapter
, adapter
->rx_ring
[i
]);
4860 DPRINTK(PROBE
, ERR
, "Allocation for Rx Queue %u failed\n", i
);
4868 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4869 * @adapter: board private structure
4870 * @tx_ring: Tx descriptor ring for a specific queue
4872 * Free all transmit software resources
4874 void ixgbe_free_tx_resources(struct ixgbe_adapter
*adapter
,
4875 struct ixgbe_ring
*tx_ring
)
4877 struct pci_dev
*pdev
= adapter
->pdev
;
4879 ixgbe_clean_tx_ring(adapter
, tx_ring
);
4881 vfree(tx_ring
->tx_buffer_info
);
4882 tx_ring
->tx_buffer_info
= NULL
;
4884 dma_free_coherent(&pdev
->dev
, tx_ring
->size
, tx_ring
->desc
,
4887 tx_ring
->desc
= NULL
;
4891 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4892 * @adapter: board private structure
4894 * Free all transmit software resources
4896 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter
*adapter
)
4900 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4901 if (adapter
->tx_ring
[i
]->desc
)
4902 ixgbe_free_tx_resources(adapter
, adapter
->tx_ring
[i
]);
4906 * ixgbe_free_rx_resources - Free Rx Resources
4907 * @adapter: board private structure
4908 * @rx_ring: ring to clean the resources from
4910 * Free all receive software resources
4912 void ixgbe_free_rx_resources(struct ixgbe_adapter
*adapter
,
4913 struct ixgbe_ring
*rx_ring
)
4915 struct pci_dev
*pdev
= adapter
->pdev
;
4917 ixgbe_clean_rx_ring(adapter
, rx_ring
);
4919 vfree(rx_ring
->rx_buffer_info
);
4920 rx_ring
->rx_buffer_info
= NULL
;
4922 dma_free_coherent(&pdev
->dev
, rx_ring
->size
, rx_ring
->desc
,
4925 rx_ring
->desc
= NULL
;
4929 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4930 * @adapter: board private structure
4932 * Free all receive software resources
4934 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter
*adapter
)
4938 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4939 if (adapter
->rx_ring
[i
]->desc
)
4940 ixgbe_free_rx_resources(adapter
, adapter
->rx_ring
[i
]);
4944 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4945 * @netdev: network interface device structure
4946 * @new_mtu: new value for maximum frame size
4948 * Returns 0 on success, negative on failure
4950 static int ixgbe_change_mtu(struct net_device
*netdev
, int new_mtu
)
4952 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4953 int max_frame
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
4955 /* MTU < 68 is an error and causes problems on some kernels */
4956 if ((new_mtu
< 68) || (max_frame
> IXGBE_MAX_JUMBO_FRAME_SIZE
))
4959 DPRINTK(PROBE
, INFO
, "changing MTU from %d to %d\n",
4960 netdev
->mtu
, new_mtu
);
4961 /* must set new MTU before calling down or up */
4962 netdev
->mtu
= new_mtu
;
4964 if (netif_running(netdev
))
4965 ixgbe_reinit_locked(adapter
);
4971 * ixgbe_open - Called when a network interface is made active
4972 * @netdev: network interface device structure
4974 * Returns 0 on success, negative value on failure
4976 * The open entry point is called when a network interface is made
4977 * active by the system (IFF_UP). At this point all resources needed
4978 * for transmit and receive operations are allocated, the interrupt
4979 * handler is registered with the OS, the watchdog timer is started,
4980 * and the stack is notified that the interface is ready.
4982 static int ixgbe_open(struct net_device
*netdev
)
4984 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4987 /* disallow open during test */
4988 if (test_bit(__IXGBE_TESTING
, &adapter
->state
))
4991 netif_carrier_off(netdev
);
4993 /* allocate transmit descriptors */
4994 err
= ixgbe_setup_all_tx_resources(adapter
);
4998 /* allocate receive descriptors */
4999 err
= ixgbe_setup_all_rx_resources(adapter
);
5003 ixgbe_configure(adapter
);
5005 err
= ixgbe_request_irq(adapter
);
5009 err
= ixgbe_up_complete(adapter
);
5013 netif_tx_start_all_queues(netdev
);
5018 ixgbe_release_hw_control(adapter
);
5019 ixgbe_free_irq(adapter
);
5022 ixgbe_free_all_rx_resources(adapter
);
5024 ixgbe_free_all_tx_resources(adapter
);
5025 ixgbe_reset(adapter
);
5031 * ixgbe_close - Disables a network interface
5032 * @netdev: network interface device structure
5034 * Returns 0, this is not allowed to fail
5036 * The close entry point is called when an interface is de-activated
5037 * by the OS. The hardware is still under the drivers control, but
5038 * needs to be disabled. A global MAC reset is issued to stop the
5039 * hardware, and all transmit and receive resources are freed.
5041 static int ixgbe_close(struct net_device
*netdev
)
5043 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5045 ixgbe_down(adapter
);
5046 ixgbe_free_irq(adapter
);
5048 ixgbe_free_all_tx_resources(adapter
);
5049 ixgbe_free_all_rx_resources(adapter
);
5051 ixgbe_release_hw_control(adapter
);
5057 static int ixgbe_resume(struct pci_dev
*pdev
)
5059 struct net_device
*netdev
= pci_get_drvdata(pdev
);
5060 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5063 pci_set_power_state(pdev
, PCI_D0
);
5064 pci_restore_state(pdev
);
5066 * pci_restore_state clears dev->state_saved so call
5067 * pci_save_state to restore it.
5069 pci_save_state(pdev
);
5071 err
= pci_enable_device_mem(pdev
);
5073 printk(KERN_ERR
"ixgbe: Cannot enable PCI device from "
5077 pci_set_master(pdev
);
5079 pci_wake_from_d3(pdev
, false);
5081 err
= ixgbe_init_interrupt_scheme(adapter
);
5083 printk(KERN_ERR
"ixgbe: Cannot initialize interrupts for "
5088 ixgbe_reset(adapter
);
5090 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
5092 if (netif_running(netdev
)) {
5093 err
= ixgbe_open(adapter
->netdev
);
5098 netif_device_attach(netdev
);
5102 #endif /* CONFIG_PM */
5104 static int __ixgbe_shutdown(struct pci_dev
*pdev
, bool *enable_wake
)
5106 struct net_device
*netdev
= pci_get_drvdata(pdev
);
5107 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5108 struct ixgbe_hw
*hw
= &adapter
->hw
;
5110 u32 wufc
= adapter
->wol
;
5115 netif_device_detach(netdev
);
5117 if (netif_running(netdev
)) {
5118 ixgbe_down(adapter
);
5119 ixgbe_free_irq(adapter
);
5120 ixgbe_free_all_tx_resources(adapter
);
5121 ixgbe_free_all_rx_resources(adapter
);
5123 ixgbe_clear_interrupt_scheme(adapter
);
5126 retval
= pci_save_state(pdev
);
5132 ixgbe_set_rx_mode(netdev
);
5134 /* turn on all-multi mode if wake on multicast is enabled */
5135 if (wufc
& IXGBE_WUFC_MC
) {
5136 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
5137 fctrl
|= IXGBE_FCTRL_MPE
;
5138 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
5141 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
5142 ctrl
|= IXGBE_CTRL_GIO_DIS
;
5143 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, ctrl
);
5145 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, wufc
);
5147 IXGBE_WRITE_REG(hw
, IXGBE_WUC
, 0);
5148 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, 0);
5151 if (wufc
&& hw
->mac
.type
== ixgbe_mac_82599EB
)
5152 pci_wake_from_d3(pdev
, true);
5154 pci_wake_from_d3(pdev
, false);
5156 *enable_wake
= !!wufc
;
5158 ixgbe_release_hw_control(adapter
);
5160 pci_disable_device(pdev
);
5166 static int ixgbe_suspend(struct pci_dev
*pdev
, pm_message_t state
)
5171 retval
= __ixgbe_shutdown(pdev
, &wake
);
5176 pci_prepare_to_sleep(pdev
);
5178 pci_wake_from_d3(pdev
, false);
5179 pci_set_power_state(pdev
, PCI_D3hot
);
5184 #endif /* CONFIG_PM */
5186 static void ixgbe_shutdown(struct pci_dev
*pdev
)
5190 __ixgbe_shutdown(pdev
, &wake
);
5192 if (system_state
== SYSTEM_POWER_OFF
) {
5193 pci_wake_from_d3(pdev
, wake
);
5194 pci_set_power_state(pdev
, PCI_D3hot
);
5199 * ixgbe_update_stats - Update the board statistics counters.
5200 * @adapter: board private structure
5202 void ixgbe_update_stats(struct ixgbe_adapter
*adapter
)
5204 struct net_device
*netdev
= adapter
->netdev
;
5205 struct ixgbe_hw
*hw
= &adapter
->hw
;
5207 u32 i
, missed_rx
= 0, mpc
, bprc
, lxon
, lxoff
, xon_off_tot
;
5208 u64 non_eop_descs
= 0, restart_queue
= 0;
5210 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
5213 for (i
= 0; i
< 16; i
++)
5214 adapter
->hw_rx_no_dma_resources
+=
5215 IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
5216 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5217 rsc_count
+= adapter
->rx_ring
[i
]->rsc_count
;
5218 rsc_flush
+= adapter
->rx_ring
[i
]->rsc_flush
;
5220 adapter
->rsc_total_count
= rsc_count
;
5221 adapter
->rsc_total_flush
= rsc_flush
;
5224 /* gather some stats to the adapter struct that are per queue */
5225 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5226 restart_queue
+= adapter
->tx_ring
[i
]->restart_queue
;
5227 adapter
->restart_queue
= restart_queue
;
5229 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
5230 non_eop_descs
+= adapter
->rx_ring
[i
]->non_eop_descs
;
5231 adapter
->non_eop_descs
= non_eop_descs
;
5233 adapter
->stats
.crcerrs
+= IXGBE_READ_REG(hw
, IXGBE_CRCERRS
);
5234 for (i
= 0; i
< 8; i
++) {
5235 /* for packet buffers not used, the register should read 0 */
5236 mpc
= IXGBE_READ_REG(hw
, IXGBE_MPC(i
));
5238 adapter
->stats
.mpc
[i
] += mpc
;
5239 total_mpc
+= adapter
->stats
.mpc
[i
];
5240 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
5241 adapter
->stats
.rnbc
[i
] += IXGBE_READ_REG(hw
, IXGBE_RNBC(i
));
5242 adapter
->stats
.qptc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPTC(i
));
5243 adapter
->stats
.qbtc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBTC(i
));
5244 adapter
->stats
.qprc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRC(i
));
5245 adapter
->stats
.qbrc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBRC(i
));
5246 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
5247 adapter
->stats
.pxonrxc
[i
] += IXGBE_READ_REG(hw
,
5248 IXGBE_PXONRXCNT(i
));
5249 adapter
->stats
.pxoffrxc
[i
] += IXGBE_READ_REG(hw
,
5250 IXGBE_PXOFFRXCNT(i
));
5251 adapter
->stats
.qprdc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
5253 adapter
->stats
.pxonrxc
[i
] += IXGBE_READ_REG(hw
,
5255 adapter
->stats
.pxoffrxc
[i
] += IXGBE_READ_REG(hw
,
5258 adapter
->stats
.pxontxc
[i
] += IXGBE_READ_REG(hw
,
5260 adapter
->stats
.pxofftxc
[i
] += IXGBE_READ_REG(hw
,
5263 adapter
->stats
.gprc
+= IXGBE_READ_REG(hw
, IXGBE_GPRC
);
5264 /* work around hardware counting issue */
5265 adapter
->stats
.gprc
-= missed_rx
;
5267 /* 82598 hardware only has a 32 bit counter in the high register */
5268 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
5270 adapter
->stats
.gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCL
);
5271 tmp
= IXGBE_READ_REG(hw
, IXGBE_GORCH
) & 0xF; /* 4 high bits of GORC */
5272 adapter
->stats
.gorc
+= (tmp
<< 32);
5273 adapter
->stats
.gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCL
);
5274 tmp
= IXGBE_READ_REG(hw
, IXGBE_GOTCH
) & 0xF; /* 4 high bits of GOTC */
5275 adapter
->stats
.gotc
+= (tmp
<< 32);
5276 adapter
->stats
.tor
+= IXGBE_READ_REG(hw
, IXGBE_TORL
);
5277 IXGBE_READ_REG(hw
, IXGBE_TORH
); /* to clear */
5278 adapter
->stats
.lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXCNT
);
5279 adapter
->stats
.lxoffrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXCNT
);
5280 adapter
->stats
.fdirmatch
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMATCH
);
5281 adapter
->stats
.fdirmiss
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMISS
);
5283 adapter
->stats
.fccrc
+= IXGBE_READ_REG(hw
, IXGBE_FCCRC
);
5284 adapter
->stats
.fcoerpdc
+= IXGBE_READ_REG(hw
, IXGBE_FCOERPDC
);
5285 adapter
->stats
.fcoeprc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPRC
);
5286 adapter
->stats
.fcoeptc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPTC
);
5287 adapter
->stats
.fcoedwrc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWRC
);
5288 adapter
->stats
.fcoedwtc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWTC
);
5289 #endif /* IXGBE_FCOE */
5291 adapter
->stats
.lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXC
);
5292 adapter
->stats
.lxoffrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXC
);
5293 adapter
->stats
.gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCH
);
5294 adapter
->stats
.gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCH
);
5295 adapter
->stats
.tor
+= IXGBE_READ_REG(hw
, IXGBE_TORH
);
5297 bprc
= IXGBE_READ_REG(hw
, IXGBE_BPRC
);
5298 adapter
->stats
.bprc
+= bprc
;
5299 adapter
->stats
.mprc
+= IXGBE_READ_REG(hw
, IXGBE_MPRC
);
5300 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
5301 adapter
->stats
.mprc
-= bprc
;
5302 adapter
->stats
.roc
+= IXGBE_READ_REG(hw
, IXGBE_ROC
);
5303 adapter
->stats
.prc64
+= IXGBE_READ_REG(hw
, IXGBE_PRC64
);
5304 adapter
->stats
.prc127
+= IXGBE_READ_REG(hw
, IXGBE_PRC127
);
5305 adapter
->stats
.prc255
+= IXGBE_READ_REG(hw
, IXGBE_PRC255
);
5306 adapter
->stats
.prc511
+= IXGBE_READ_REG(hw
, IXGBE_PRC511
);
5307 adapter
->stats
.prc1023
+= IXGBE_READ_REG(hw
, IXGBE_PRC1023
);
5308 adapter
->stats
.prc1522
+= IXGBE_READ_REG(hw
, IXGBE_PRC1522
);
5309 adapter
->stats
.rlec
+= IXGBE_READ_REG(hw
, IXGBE_RLEC
);
5310 lxon
= IXGBE_READ_REG(hw
, IXGBE_LXONTXC
);
5311 adapter
->stats
.lxontxc
+= lxon
;
5312 lxoff
= IXGBE_READ_REG(hw
, IXGBE_LXOFFTXC
);
5313 adapter
->stats
.lxofftxc
+= lxoff
;
5314 adapter
->stats
.ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
5315 adapter
->stats
.gptc
+= IXGBE_READ_REG(hw
, IXGBE_GPTC
);
5316 adapter
->stats
.mptc
+= IXGBE_READ_REG(hw
, IXGBE_MPTC
);
5318 * 82598 errata - tx of flow control packets is included in tx counters
5320 xon_off_tot
= lxon
+ lxoff
;
5321 adapter
->stats
.gptc
-= xon_off_tot
;
5322 adapter
->stats
.mptc
-= xon_off_tot
;
5323 adapter
->stats
.gotc
-= (xon_off_tot
* (ETH_ZLEN
+ ETH_FCS_LEN
));
5324 adapter
->stats
.ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
5325 adapter
->stats
.rfc
+= IXGBE_READ_REG(hw
, IXGBE_RFC
);
5326 adapter
->stats
.rjc
+= IXGBE_READ_REG(hw
, IXGBE_RJC
);
5327 adapter
->stats
.tpr
+= IXGBE_READ_REG(hw
, IXGBE_TPR
);
5328 adapter
->stats
.ptc64
+= IXGBE_READ_REG(hw
, IXGBE_PTC64
);
5329 adapter
->stats
.ptc64
-= xon_off_tot
;
5330 adapter
->stats
.ptc127
+= IXGBE_READ_REG(hw
, IXGBE_PTC127
);
5331 adapter
->stats
.ptc255
+= IXGBE_READ_REG(hw
, IXGBE_PTC255
);
5332 adapter
->stats
.ptc511
+= IXGBE_READ_REG(hw
, IXGBE_PTC511
);
5333 adapter
->stats
.ptc1023
+= IXGBE_READ_REG(hw
, IXGBE_PTC1023
);
5334 adapter
->stats
.ptc1522
+= IXGBE_READ_REG(hw
, IXGBE_PTC1522
);
5335 adapter
->stats
.bptc
+= IXGBE_READ_REG(hw
, IXGBE_BPTC
);
5337 /* Fill out the OS statistics structure */
5338 netdev
->stats
.multicast
= adapter
->stats
.mprc
;
5341 netdev
->stats
.rx_errors
= adapter
->stats
.crcerrs
+
5342 adapter
->stats
.rlec
;
5343 netdev
->stats
.rx_dropped
= 0;
5344 netdev
->stats
.rx_length_errors
= adapter
->stats
.rlec
;
5345 netdev
->stats
.rx_crc_errors
= adapter
->stats
.crcerrs
;
5346 netdev
->stats
.rx_missed_errors
= total_mpc
;
5350 * ixgbe_watchdog - Timer Call-back
5351 * @data: pointer to adapter cast into an unsigned long
5353 static void ixgbe_watchdog(unsigned long data
)
5355 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
5356 struct ixgbe_hw
*hw
= &adapter
->hw
;
5361 * Do the watchdog outside of interrupt context due to the lovely
5362 * delays that some of the newer hardware requires
5365 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
5366 goto watchdog_short_circuit
;
5368 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)) {
5370 * for legacy and MSI interrupts don't set any bits
5371 * that are enabled for EIAM, because this operation
5372 * would set *both* EIMS and EICS for any bit in EIAM
5374 IXGBE_WRITE_REG(hw
, IXGBE_EICS
,
5375 (IXGBE_EICS_TCP_TIMER
| IXGBE_EICS_OTHER
));
5376 goto watchdog_reschedule
;
5379 /* get one bit for every active tx/rx interrupt vector */
5380 for (i
= 0; i
< adapter
->num_msix_vectors
- NON_Q_VECTORS
; i
++) {
5381 struct ixgbe_q_vector
*qv
= adapter
->q_vector
[i
];
5382 if (qv
->rxr_count
|| qv
->txr_count
)
5383 eics
|= ((u64
)1 << i
);
5386 /* Cause software interrupt to ensure rx rings are cleaned */
5387 ixgbe_irq_rearm_queues(adapter
, eics
);
5389 watchdog_reschedule
:
5390 /* Reset the timer */
5391 mod_timer(&adapter
->watchdog_timer
, round_jiffies(jiffies
+ 2 * HZ
));
5393 watchdog_short_circuit
:
5394 schedule_work(&adapter
->watchdog_task
);
5398 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5399 * @work: pointer to work_struct containing our data
5401 static void ixgbe_multispeed_fiber_task(struct work_struct
*work
)
5403 struct ixgbe_adapter
*adapter
= container_of(work
,
5404 struct ixgbe_adapter
,
5405 multispeed_fiber_task
);
5406 struct ixgbe_hw
*hw
= &adapter
->hw
;
5410 adapter
->flags
|= IXGBE_FLAG_IN_SFP_LINK_TASK
;
5411 autoneg
= hw
->phy
.autoneg_advertised
;
5412 if ((!autoneg
) && (hw
->mac
.ops
.get_link_capabilities
))
5413 hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
, &negotiation
);
5414 hw
->mac
.autotry_restart
= false;
5415 if (hw
->mac
.ops
.setup_link
)
5416 hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, true);
5417 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
5418 adapter
->flags
&= ~IXGBE_FLAG_IN_SFP_LINK_TASK
;
5422 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5423 * @work: pointer to work_struct containing our data
5425 static void ixgbe_sfp_config_module_task(struct work_struct
*work
)
5427 struct ixgbe_adapter
*adapter
= container_of(work
,
5428 struct ixgbe_adapter
,
5429 sfp_config_module_task
);
5430 struct ixgbe_hw
*hw
= &adapter
->hw
;
5433 adapter
->flags
|= IXGBE_FLAG_IN_SFP_MOD_TASK
;
5435 /* Time for electrical oscillations to settle down */
5437 err
= hw
->phy
.ops
.identify_sfp(hw
);
5439 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
5440 dev_err(&adapter
->pdev
->dev
, "failed to initialize because "
5441 "an unsupported SFP+ module type was detected.\n"
5442 "Reload the driver after installing a supported "
5444 unregister_netdev(adapter
->netdev
);
5447 hw
->mac
.ops
.setup_sfp(hw
);
5449 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_LINK_TASK
))
5450 /* This will also work for DA Twinax connections */
5451 schedule_work(&adapter
->multispeed_fiber_task
);
5452 adapter
->flags
&= ~IXGBE_FLAG_IN_SFP_MOD_TASK
;
5456 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5457 * @work: pointer to work_struct containing our data
5459 static void ixgbe_fdir_reinit_task(struct work_struct
*work
)
5461 struct ixgbe_adapter
*adapter
= container_of(work
,
5462 struct ixgbe_adapter
,
5464 struct ixgbe_hw
*hw
= &adapter
->hw
;
5467 if (ixgbe_reinit_fdir_tables_82599(hw
) == 0) {
5468 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5469 set_bit(__IXGBE_FDIR_INIT_DONE
,
5470 &(adapter
->tx_ring
[i
]->reinit_state
));
5472 DPRINTK(PROBE
, ERR
, "failed to finish FDIR re-initialization, "
5473 "ignored adding FDIR ATR filters\n");
5475 /* Done FDIR Re-initialization, enable transmits */
5476 netif_tx_start_all_queues(adapter
->netdev
);
5479 static DEFINE_MUTEX(ixgbe_watchdog_lock
);
5482 * ixgbe_watchdog_task - worker thread to bring link up
5483 * @work: pointer to work_struct containing our data
5485 static void ixgbe_watchdog_task(struct work_struct
*work
)
5487 struct ixgbe_adapter
*adapter
= container_of(work
,
5488 struct ixgbe_adapter
,
5490 struct net_device
*netdev
= adapter
->netdev
;
5491 struct ixgbe_hw
*hw
= &adapter
->hw
;
5495 struct ixgbe_ring
*tx_ring
;
5496 int some_tx_pending
= 0;
5498 mutex_lock(&ixgbe_watchdog_lock
);
5500 link_up
= adapter
->link_up
;
5501 link_speed
= adapter
->link_speed
;
5503 if (adapter
->flags
& IXGBE_FLAG_NEED_LINK_UPDATE
) {
5504 hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
, false);
5507 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
5508 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++)
5509 hw
->mac
.ops
.fc_enable(hw
, i
);
5511 hw
->mac
.ops
.fc_enable(hw
, 0);
5514 hw
->mac
.ops
.fc_enable(hw
, 0);
5519 time_after(jiffies
, (adapter
->link_check_timeout
+
5520 IXGBE_TRY_LINK_TIMEOUT
))) {
5521 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_UPDATE
;
5522 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMC_LSC
);
5524 adapter
->link_up
= link_up
;
5525 adapter
->link_speed
= link_speed
;
5529 if (!netif_carrier_ok(netdev
)) {
5530 bool flow_rx
, flow_tx
;
5532 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
5533 u32 mflcn
= IXGBE_READ_REG(hw
, IXGBE_MFLCN
);
5534 u32 fccfg
= IXGBE_READ_REG(hw
, IXGBE_FCCFG
);
5535 flow_rx
= !!(mflcn
& IXGBE_MFLCN_RFCE
);
5536 flow_tx
= !!(fccfg
& IXGBE_FCCFG_TFCE_802_3X
);
5538 u32 frctl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
5539 u32 rmcs
= IXGBE_READ_REG(hw
, IXGBE_RMCS
);
5540 flow_rx
= !!(frctl
& IXGBE_FCTRL_RFCE
);
5541 flow_tx
= !!(rmcs
& IXGBE_RMCS_TFCE_802_3X
);
5544 printk(KERN_INFO
"ixgbe: %s NIC Link is Up %s, "
5545 "Flow Control: %s\n",
5547 (link_speed
== IXGBE_LINK_SPEED_10GB_FULL
?
5549 (link_speed
== IXGBE_LINK_SPEED_1GB_FULL
?
5550 "1 Gbps" : "unknown speed")),
5551 ((flow_rx
&& flow_tx
) ? "RX/TX" :
5553 (flow_tx
? "TX" : "None"))));
5555 netif_carrier_on(netdev
);
5557 /* Force detection of hung controller */
5558 adapter
->detect_tx_hung
= true;
5561 adapter
->link_up
= false;
5562 adapter
->link_speed
= 0;
5563 if (netif_carrier_ok(netdev
)) {
5564 printk(KERN_INFO
"ixgbe: %s NIC Link is Down\n",
5566 netif_carrier_off(netdev
);
5570 if (!netif_carrier_ok(netdev
)) {
5571 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5572 tx_ring
= adapter
->tx_ring
[i
];
5573 if (tx_ring
->next_to_use
!= tx_ring
->next_to_clean
) {
5574 some_tx_pending
= 1;
5579 if (some_tx_pending
) {
5580 /* We've lost link, so the controller stops DMA,
5581 * but we've got queued Tx work that's never going
5582 * to get done, so reset controller to flush Tx.
5583 * (Do the reset outside of interrupt context).
5585 schedule_work(&adapter
->reset_task
);
5589 ixgbe_update_stats(adapter
);
5590 mutex_unlock(&ixgbe_watchdog_lock
);
5593 static int ixgbe_tso(struct ixgbe_adapter
*adapter
,
5594 struct ixgbe_ring
*tx_ring
, struct sk_buff
*skb
,
5595 u32 tx_flags
, u8
*hdr_len
)
5597 struct ixgbe_adv_tx_context_desc
*context_desc
;
5600 struct ixgbe_tx_buffer
*tx_buffer_info
;
5601 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
;
5602 u32 mss_l4len_idx
, l4len
;
5604 if (skb_is_gso(skb
)) {
5605 if (skb_header_cloned(skb
)) {
5606 err
= pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
);
5610 l4len
= tcp_hdrlen(skb
);
5613 if (skb
->protocol
== htons(ETH_P_IP
)) {
5614 struct iphdr
*iph
= ip_hdr(skb
);
5617 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
5621 } else if (skb_is_gso_v6(skb
)) {
5622 ipv6_hdr(skb
)->payload_len
= 0;
5623 tcp_hdr(skb
)->check
=
5624 ~csum_ipv6_magic(&ipv6_hdr(skb
)->saddr
,
5625 &ipv6_hdr(skb
)->daddr
,
5629 i
= tx_ring
->next_to_use
;
5631 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5632 context_desc
= IXGBE_TX_CTXTDESC_ADV(*tx_ring
, i
);
5634 /* VLAN MACLEN IPLEN */
5635 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
5637 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
5638 vlan_macip_lens
|= ((skb_network_offset(skb
)) <<
5639 IXGBE_ADVTXD_MACLEN_SHIFT
);
5640 *hdr_len
+= skb_network_offset(skb
);
5642 (skb_transport_header(skb
) - skb_network_header(skb
));
5644 (skb_transport_header(skb
) - skb_network_header(skb
));
5645 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
5646 context_desc
->seqnum_seed
= 0;
5648 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5649 type_tucmd_mlhl
= (IXGBE_TXD_CMD_DEXT
|
5650 IXGBE_ADVTXD_DTYP_CTXT
);
5652 if (skb
->protocol
== htons(ETH_P_IP
))
5653 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_IPV4
;
5654 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
5655 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
5659 (skb_shinfo(skb
)->gso_size
<< IXGBE_ADVTXD_MSS_SHIFT
);
5660 mss_l4len_idx
|= (l4len
<< IXGBE_ADVTXD_L4LEN_SHIFT
);
5661 /* use index 1 for TSO */
5662 mss_l4len_idx
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
5663 context_desc
->mss_l4len_idx
= cpu_to_le32(mss_l4len_idx
);
5665 tx_buffer_info
->time_stamp
= jiffies
;
5666 tx_buffer_info
->next_to_watch
= i
;
5669 if (i
== tx_ring
->count
)
5671 tx_ring
->next_to_use
= i
;
5678 static bool ixgbe_tx_csum(struct ixgbe_adapter
*adapter
,
5679 struct ixgbe_ring
*tx_ring
,
5680 struct sk_buff
*skb
, u32 tx_flags
)
5682 struct ixgbe_adv_tx_context_desc
*context_desc
;
5684 struct ixgbe_tx_buffer
*tx_buffer_info
;
5685 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
= 0;
5687 if (skb
->ip_summed
== CHECKSUM_PARTIAL
||
5688 (tx_flags
& IXGBE_TX_FLAGS_VLAN
)) {
5689 i
= tx_ring
->next_to_use
;
5690 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5691 context_desc
= IXGBE_TX_CTXTDESC_ADV(*tx_ring
, i
);
5693 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
5695 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
5696 vlan_macip_lens
|= (skb_network_offset(skb
) <<
5697 IXGBE_ADVTXD_MACLEN_SHIFT
);
5698 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
5699 vlan_macip_lens
|= (skb_transport_header(skb
) -
5700 skb_network_header(skb
));
5702 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
5703 context_desc
->seqnum_seed
= 0;
5705 type_tucmd_mlhl
|= (IXGBE_TXD_CMD_DEXT
|
5706 IXGBE_ADVTXD_DTYP_CTXT
);
5708 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5711 if (skb
->protocol
== cpu_to_be16(ETH_P_8021Q
)) {
5712 const struct vlan_ethhdr
*vhdr
=
5713 (const struct vlan_ethhdr
*)skb
->data
;
5715 protocol
= vhdr
->h_vlan_encapsulated_proto
;
5717 protocol
= skb
->protocol
;
5721 case cpu_to_be16(ETH_P_IP
):
5722 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_IPV4
;
5723 if (ip_hdr(skb
)->protocol
== IPPROTO_TCP
)
5725 IXGBE_ADVTXD_TUCMD_L4T_TCP
;
5726 else if (ip_hdr(skb
)->protocol
== IPPROTO_SCTP
)
5728 IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
5730 case cpu_to_be16(ETH_P_IPV6
):
5731 /* XXX what about other V6 headers?? */
5732 if (ipv6_hdr(skb
)->nexthdr
== IPPROTO_TCP
)
5734 IXGBE_ADVTXD_TUCMD_L4T_TCP
;
5735 else if (ipv6_hdr(skb
)->nexthdr
== IPPROTO_SCTP
)
5737 IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
5740 if (unlikely(net_ratelimit())) {
5741 DPRINTK(PROBE
, WARNING
,
5742 "partial checksum but proto=%x!\n",
5749 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
5750 /* use index zero for tx checksum offload */
5751 context_desc
->mss_l4len_idx
= 0;
5753 tx_buffer_info
->time_stamp
= jiffies
;
5754 tx_buffer_info
->next_to_watch
= i
;
5757 if (i
== tx_ring
->count
)
5759 tx_ring
->next_to_use
= i
;
5767 static int ixgbe_tx_map(struct ixgbe_adapter
*adapter
,
5768 struct ixgbe_ring
*tx_ring
,
5769 struct sk_buff
*skb
, u32 tx_flags
,
5772 struct pci_dev
*pdev
= adapter
->pdev
;
5773 struct ixgbe_tx_buffer
*tx_buffer_info
;
5775 unsigned int total
= skb
->len
;
5776 unsigned int offset
= 0, size
, count
= 0, i
;
5777 unsigned int nr_frags
= skb_shinfo(skb
)->nr_frags
;
5780 i
= tx_ring
->next_to_use
;
5782 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
)
5783 /* excluding fcoe_crc_eof for FCoE */
5784 total
-= sizeof(struct fcoe_crc_eof
);
5786 len
= min(skb_headlen(skb
), total
);
5788 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5789 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
5791 tx_buffer_info
->length
= size
;
5792 tx_buffer_info
->mapped_as_page
= false;
5793 tx_buffer_info
->dma
= dma_map_single(&pdev
->dev
,
5795 size
, DMA_TO_DEVICE
);
5796 if (dma_mapping_error(&pdev
->dev
, tx_buffer_info
->dma
))
5798 tx_buffer_info
->time_stamp
= jiffies
;
5799 tx_buffer_info
->next_to_watch
= i
;
5808 if (i
== tx_ring
->count
)
5813 for (f
= 0; f
< nr_frags
; f
++) {
5814 struct skb_frag_struct
*frag
;
5816 frag
= &skb_shinfo(skb
)->frags
[f
];
5817 len
= min((unsigned int)frag
->size
, total
);
5818 offset
= frag
->page_offset
;
5822 if (i
== tx_ring
->count
)
5825 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5826 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
5828 tx_buffer_info
->length
= size
;
5829 tx_buffer_info
->dma
= dma_map_page(&adapter
->pdev
->dev
,
5833 tx_buffer_info
->mapped_as_page
= true;
5834 if (dma_mapping_error(&pdev
->dev
, tx_buffer_info
->dma
))
5836 tx_buffer_info
->time_stamp
= jiffies
;
5837 tx_buffer_info
->next_to_watch
= i
;
5848 tx_ring
->tx_buffer_info
[i
].skb
= skb
;
5849 tx_ring
->tx_buffer_info
[first
].next_to_watch
= i
;
5854 dev_err(&pdev
->dev
, "TX DMA map failed\n");
5856 /* clear timestamp and dma mappings for failed tx_buffer_info map */
5857 tx_buffer_info
->dma
= 0;
5858 tx_buffer_info
->time_stamp
= 0;
5859 tx_buffer_info
->next_to_watch
= 0;
5863 /* clear timestamp and dma mappings for remaining portion of packet */
5866 i
+= tx_ring
->count
;
5868 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5869 ixgbe_unmap_and_free_tx_resource(adapter
, tx_buffer_info
);
5875 static void ixgbe_tx_queue(struct ixgbe_adapter
*adapter
,
5876 struct ixgbe_ring
*tx_ring
,
5877 int tx_flags
, int count
, u32 paylen
, u8 hdr_len
)
5879 union ixgbe_adv_tx_desc
*tx_desc
= NULL
;
5880 struct ixgbe_tx_buffer
*tx_buffer_info
;
5881 u32 olinfo_status
= 0, cmd_type_len
= 0;
5883 u32 txd_cmd
= IXGBE_TXD_CMD_EOP
| IXGBE_TXD_CMD_RS
| IXGBE_TXD_CMD_IFCS
;
5885 cmd_type_len
|= IXGBE_ADVTXD_DTYP_DATA
;
5887 cmd_type_len
|= IXGBE_ADVTXD_DCMD_IFCS
| IXGBE_ADVTXD_DCMD_DEXT
;
5889 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
5890 cmd_type_len
|= IXGBE_ADVTXD_DCMD_VLE
;
5892 if (tx_flags
& IXGBE_TX_FLAGS_TSO
) {
5893 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
5895 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
5896 IXGBE_ADVTXD_POPTS_SHIFT
;
5898 /* use index 1 context for tso */
5899 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
5900 if (tx_flags
& IXGBE_TX_FLAGS_IPV4
)
5901 olinfo_status
|= IXGBE_TXD_POPTS_IXSM
<<
5902 IXGBE_ADVTXD_POPTS_SHIFT
;
5904 } else if (tx_flags
& IXGBE_TX_FLAGS_CSUM
)
5905 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
5906 IXGBE_ADVTXD_POPTS_SHIFT
;
5908 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
5909 olinfo_status
|= IXGBE_ADVTXD_CC
;
5910 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
5911 if (tx_flags
& IXGBE_TX_FLAGS_FSO
)
5912 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
5915 olinfo_status
|= ((paylen
- hdr_len
) << IXGBE_ADVTXD_PAYLEN_SHIFT
);
5917 i
= tx_ring
->next_to_use
;
5919 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5920 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, i
);
5921 tx_desc
->read
.buffer_addr
= cpu_to_le64(tx_buffer_info
->dma
);
5922 tx_desc
->read
.cmd_type_len
=
5923 cpu_to_le32(cmd_type_len
| tx_buffer_info
->length
);
5924 tx_desc
->read
.olinfo_status
= cpu_to_le32(olinfo_status
);
5926 if (i
== tx_ring
->count
)
5930 tx_desc
->read
.cmd_type_len
|= cpu_to_le32(txd_cmd
);
5933 * Force memory writes to complete before letting h/w
5934 * know there are new descriptors to fetch. (Only
5935 * applicable for weak-ordered memory model archs,
5940 tx_ring
->next_to_use
= i
;
5941 writel(i
, adapter
->hw
.hw_addr
+ tx_ring
->tail
);
5944 static void ixgbe_atr(struct ixgbe_adapter
*adapter
, struct sk_buff
*skb
,
5945 int queue
, u32 tx_flags
)
5947 /* Right now, we support IPv4 only */
5948 struct ixgbe_atr_input atr_input
;
5950 struct iphdr
*iph
= ip_hdr(skb
);
5951 struct ethhdr
*eth
= (struct ethhdr
*)skb
->data
;
5952 u16 vlan_id
, src_port
, dst_port
, flex_bytes
;
5953 u32 src_ipv4_addr
, dst_ipv4_addr
;
5956 /* check if we're UDP or TCP */
5957 if (iph
->protocol
== IPPROTO_TCP
) {
5959 src_port
= th
->source
;
5960 dst_port
= th
->dest
;
5961 l4type
|= IXGBE_ATR_L4TYPE_TCP
;
5962 /* l4type IPv4 type is 0, no need to assign */
5964 /* Unsupported L4 header, just bail here */
5968 memset(&atr_input
, 0, sizeof(struct ixgbe_atr_input
));
5970 vlan_id
= (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
) >>
5971 IXGBE_TX_FLAGS_VLAN_SHIFT
;
5972 src_ipv4_addr
= iph
->saddr
;
5973 dst_ipv4_addr
= iph
->daddr
;
5974 flex_bytes
= eth
->h_proto
;
5976 ixgbe_atr_set_vlan_id_82599(&atr_input
, vlan_id
);
5977 ixgbe_atr_set_src_port_82599(&atr_input
, dst_port
);
5978 ixgbe_atr_set_dst_port_82599(&atr_input
, src_port
);
5979 ixgbe_atr_set_flex_byte_82599(&atr_input
, flex_bytes
);
5980 ixgbe_atr_set_l4type_82599(&atr_input
, l4type
);
5981 /* src and dst are inverted, think how the receiver sees them */
5982 ixgbe_atr_set_src_ipv4_82599(&atr_input
, dst_ipv4_addr
);
5983 ixgbe_atr_set_dst_ipv4_82599(&atr_input
, src_ipv4_addr
);
5985 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5986 ixgbe_fdir_add_signature_filter_82599(&adapter
->hw
, &atr_input
, queue
);
5989 static int __ixgbe_maybe_stop_tx(struct net_device
*netdev
,
5990 struct ixgbe_ring
*tx_ring
, int size
)
5992 netif_stop_subqueue(netdev
, tx_ring
->queue_index
);
5993 /* Herbert's original patch had:
5994 * smp_mb__after_netif_stop_queue();
5995 * but since that doesn't exist yet, just open code it. */
5998 /* We need to check again in a case another CPU has just
5999 * made room available. */
6000 if (likely(IXGBE_DESC_UNUSED(tx_ring
) < size
))
6003 /* A reprieve! - use start_queue because it doesn't call schedule */
6004 netif_start_subqueue(netdev
, tx_ring
->queue_index
);
6005 ++tx_ring
->restart_queue
;
6009 static int ixgbe_maybe_stop_tx(struct net_device
*netdev
,
6010 struct ixgbe_ring
*tx_ring
, int size
)
6012 if (likely(IXGBE_DESC_UNUSED(tx_ring
) >= size
))
6014 return __ixgbe_maybe_stop_tx(netdev
, tx_ring
, size
);
6017 static u16
ixgbe_select_queue(struct net_device
*dev
, struct sk_buff
*skb
)
6019 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6020 int txq
= smp_processor_id();
6022 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
6023 while (unlikely(txq
>= dev
->real_num_tx_queues
))
6024 txq
-= dev
->real_num_tx_queues
;
6029 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) &&
6030 ((skb
->protocol
== htons(ETH_P_FCOE
)) ||
6031 (skb
->protocol
== htons(ETH_P_FIP
)))) {
6032 txq
&= (adapter
->ring_feature
[RING_F_FCOE
].indices
- 1);
6033 txq
+= adapter
->ring_feature
[RING_F_FCOE
].mask
;
6037 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6038 if (skb
->priority
== TC_PRIO_CONTROL
)
6039 txq
= adapter
->ring_feature
[RING_F_DCB
].indices
-1;
6041 txq
= (skb
->vlan_tci
& IXGBE_TX_FLAGS_VLAN_PRIO_MASK
)
6046 return skb_tx_hash(dev
, skb
);
6049 static netdev_tx_t
ixgbe_xmit_frame(struct sk_buff
*skb
,
6050 struct net_device
*netdev
)
6052 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6053 struct ixgbe_ring
*tx_ring
;
6054 struct netdev_queue
*txq
;
6056 unsigned int tx_flags
= 0;
6062 if (adapter
->vlgrp
&& vlan_tx_tag_present(skb
)) {
6063 tx_flags
|= vlan_tx_tag_get(skb
);
6064 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6065 tx_flags
&= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK
;
6066 tx_flags
|= ((skb
->queue_mapping
& 0x7) << 13);
6068 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
6069 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
6070 } else if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6071 tx_flags
|= ((skb
->queue_mapping
& 0x7) << 13);
6072 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
6073 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
6076 tx_ring
= adapter
->tx_ring
[skb
->queue_mapping
];
6079 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
6080 #ifdef CONFIG_IXGBE_DCB
6081 /* for FCoE with DCB, we force the priority to what
6082 * was specified by the switch */
6083 if ((skb
->protocol
== htons(ETH_P_FCOE
)) ||
6084 (skb
->protocol
== htons(ETH_P_FIP
))) {
6085 tx_flags
&= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6086 << IXGBE_TX_FLAGS_VLAN_SHIFT
);
6087 tx_flags
|= ((adapter
->fcoe
.up
<< 13)
6088 << IXGBE_TX_FLAGS_VLAN_SHIFT
);
6091 /* flag for FCoE offloads */
6092 if (skb
->protocol
== htons(ETH_P_FCOE
))
6093 tx_flags
|= IXGBE_TX_FLAGS_FCOE
;
6097 /* four things can cause us to need a context descriptor */
6098 if (skb_is_gso(skb
) ||
6099 (skb
->ip_summed
== CHECKSUM_PARTIAL
) ||
6100 (tx_flags
& IXGBE_TX_FLAGS_VLAN
) ||
6101 (tx_flags
& IXGBE_TX_FLAGS_FCOE
))
6104 count
+= TXD_USE_COUNT(skb_headlen(skb
));
6105 for (f
= 0; f
< skb_shinfo(skb
)->nr_frags
; f
++)
6106 count
+= TXD_USE_COUNT(skb_shinfo(skb
)->frags
[f
].size
);
6108 if (ixgbe_maybe_stop_tx(netdev
, tx_ring
, count
)) {
6110 return NETDEV_TX_BUSY
;
6113 first
= tx_ring
->next_to_use
;
6114 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
6116 /* setup tx offload for FCoE */
6117 tso
= ixgbe_fso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
);
6119 dev_kfree_skb_any(skb
);
6120 return NETDEV_TX_OK
;
6123 tx_flags
|= IXGBE_TX_FLAGS_FSO
;
6124 #endif /* IXGBE_FCOE */
6126 if (skb
->protocol
== htons(ETH_P_IP
))
6127 tx_flags
|= IXGBE_TX_FLAGS_IPV4
;
6128 tso
= ixgbe_tso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
);
6130 dev_kfree_skb_any(skb
);
6131 return NETDEV_TX_OK
;
6135 tx_flags
|= IXGBE_TX_FLAGS_TSO
;
6136 else if (ixgbe_tx_csum(adapter
, tx_ring
, skb
, tx_flags
) &&
6137 (skb
->ip_summed
== CHECKSUM_PARTIAL
))
6138 tx_flags
|= IXGBE_TX_FLAGS_CSUM
;
6141 count
= ixgbe_tx_map(adapter
, tx_ring
, skb
, tx_flags
, first
);
6143 /* add the ATR filter if ATR is on */
6144 if (tx_ring
->atr_sample_rate
) {
6145 ++tx_ring
->atr_count
;
6146 if ((tx_ring
->atr_count
>= tx_ring
->atr_sample_rate
) &&
6147 test_bit(__IXGBE_FDIR_INIT_DONE
,
6148 &tx_ring
->reinit_state
)) {
6149 ixgbe_atr(adapter
, skb
, tx_ring
->queue_index
,
6151 tx_ring
->atr_count
= 0;
6154 txq
= netdev_get_tx_queue(netdev
, tx_ring
->queue_index
);
6155 txq
->tx_bytes
+= skb
->len
;
6157 ixgbe_tx_queue(adapter
, tx_ring
, tx_flags
, count
, skb
->len
,
6159 ixgbe_maybe_stop_tx(netdev
, tx_ring
, DESC_NEEDED
);
6162 dev_kfree_skb_any(skb
);
6163 tx_ring
->tx_buffer_info
[first
].time_stamp
= 0;
6164 tx_ring
->next_to_use
= first
;
6167 return NETDEV_TX_OK
;
6171 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6172 * @netdev: network interface device structure
6173 * @p: pointer to an address structure
6175 * Returns 0 on success, negative on failure
6177 static int ixgbe_set_mac(struct net_device
*netdev
, void *p
)
6179 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6180 struct ixgbe_hw
*hw
= &adapter
->hw
;
6181 struct sockaddr
*addr
= p
;
6183 if (!is_valid_ether_addr(addr
->sa_data
))
6184 return -EADDRNOTAVAIL
;
6186 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
6187 memcpy(hw
->mac
.addr
, addr
->sa_data
, netdev
->addr_len
);
6189 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
6196 ixgbe_mdio_read(struct net_device
*netdev
, int prtad
, int devad
, u16 addr
)
6198 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6199 struct ixgbe_hw
*hw
= &adapter
->hw
;
6203 if (prtad
!= hw
->phy
.mdio
.prtad
)
6205 rc
= hw
->phy
.ops
.read_reg(hw
, addr
, devad
, &value
);
6211 static int ixgbe_mdio_write(struct net_device
*netdev
, int prtad
, int devad
,
6212 u16 addr
, u16 value
)
6214 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6215 struct ixgbe_hw
*hw
= &adapter
->hw
;
6217 if (prtad
!= hw
->phy
.mdio
.prtad
)
6219 return hw
->phy
.ops
.write_reg(hw
, addr
, devad
, value
);
6222 static int ixgbe_ioctl(struct net_device
*netdev
, struct ifreq
*req
, int cmd
)
6224 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6226 return mdio_mii_ioctl(&adapter
->hw
.phy
.mdio
, if_mii(req
), cmd
);
6230 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6232 * @netdev: network interface device structure
6234 * Returns non-zero on failure
6236 static int ixgbe_add_sanmac_netdev(struct net_device
*dev
)
6239 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6240 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
6242 if (is_valid_ether_addr(mac
->san_addr
)) {
6244 err
= dev_addr_add(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
6251 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6253 * @netdev: network interface device structure
6255 * Returns non-zero on failure
6257 static int ixgbe_del_sanmac_netdev(struct net_device
*dev
)
6260 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6261 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
6263 if (is_valid_ether_addr(mac
->san_addr
)) {
6265 err
= dev_addr_del(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
6271 #ifdef CONFIG_NET_POLL_CONTROLLER
6273 * Polling 'interrupt' - used by things like netconsole to send skbs
6274 * without having to re-enable interrupts. It's not called while
6275 * the interrupt routine is executing.
6277 static void ixgbe_netpoll(struct net_device
*netdev
)
6279 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6282 /* if interface is down do nothing */
6283 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
6286 adapter
->flags
|= IXGBE_FLAG_IN_NETPOLL
;
6287 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
6288 int num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
6289 for (i
= 0; i
< num_q_vectors
; i
++) {
6290 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
6291 ixgbe_msix_clean_many(0, q_vector
);
6294 ixgbe_intr(adapter
->pdev
->irq
, netdev
);
6296 adapter
->flags
&= ~IXGBE_FLAG_IN_NETPOLL
;
6300 static const struct net_device_ops ixgbe_netdev_ops
= {
6301 .ndo_open
= ixgbe_open
,
6302 .ndo_stop
= ixgbe_close
,
6303 .ndo_start_xmit
= ixgbe_xmit_frame
,
6304 .ndo_select_queue
= ixgbe_select_queue
,
6305 .ndo_set_rx_mode
= ixgbe_set_rx_mode
,
6306 .ndo_set_multicast_list
= ixgbe_set_rx_mode
,
6307 .ndo_validate_addr
= eth_validate_addr
,
6308 .ndo_set_mac_address
= ixgbe_set_mac
,
6309 .ndo_change_mtu
= ixgbe_change_mtu
,
6310 .ndo_tx_timeout
= ixgbe_tx_timeout
,
6311 .ndo_vlan_rx_register
= ixgbe_vlan_rx_register
,
6312 .ndo_vlan_rx_add_vid
= ixgbe_vlan_rx_add_vid
,
6313 .ndo_vlan_rx_kill_vid
= ixgbe_vlan_rx_kill_vid
,
6314 .ndo_do_ioctl
= ixgbe_ioctl
,
6315 .ndo_set_vf_mac
= ixgbe_ndo_set_vf_mac
,
6316 .ndo_set_vf_vlan
= ixgbe_ndo_set_vf_vlan
,
6317 .ndo_set_vf_tx_rate
= ixgbe_ndo_set_vf_bw
,
6318 .ndo_get_vf_config
= ixgbe_ndo_get_vf_config
,
6319 #ifdef CONFIG_NET_POLL_CONTROLLER
6320 .ndo_poll_controller
= ixgbe_netpoll
,
6323 .ndo_fcoe_ddp_setup
= ixgbe_fcoe_ddp_get
,
6324 .ndo_fcoe_ddp_done
= ixgbe_fcoe_ddp_put
,
6325 .ndo_fcoe_enable
= ixgbe_fcoe_enable
,
6326 .ndo_fcoe_disable
= ixgbe_fcoe_disable
,
6327 .ndo_fcoe_get_wwn
= ixgbe_fcoe_get_wwn
,
6328 #endif /* IXGBE_FCOE */
6331 static void __devinit
ixgbe_probe_vf(struct ixgbe_adapter
*adapter
,
6332 const struct ixgbe_info
*ii
)
6334 #ifdef CONFIG_PCI_IOV
6335 struct ixgbe_hw
*hw
= &adapter
->hw
;
6338 if (hw
->mac
.type
!= ixgbe_mac_82599EB
|| !max_vfs
)
6341 /* The 82599 supports up to 64 VFs per physical function
6342 * but this implementation limits allocation to 63 so that
6343 * basic networking resources are still available to the
6346 adapter
->num_vfs
= (max_vfs
> 63) ? 63 : max_vfs
;
6347 adapter
->flags
|= IXGBE_FLAG_SRIOV_ENABLED
;
6348 err
= pci_enable_sriov(adapter
->pdev
, adapter
->num_vfs
);
6351 "Failed to enable PCI sriov: %d\n", err
);
6354 /* If call to enable VFs succeeded then allocate memory
6355 * for per VF control structures.
6358 kcalloc(adapter
->num_vfs
,
6359 sizeof(struct vf_data_storage
), GFP_KERNEL
);
6360 if (adapter
->vfinfo
) {
6361 /* Now that we're sure SR-IOV is enabled
6362 * and memory allocated set up the mailbox parameters
6364 ixgbe_init_mbx_params_pf(hw
);
6365 memcpy(&hw
->mbx
.ops
, ii
->mbx_ops
,
6366 sizeof(hw
->mbx
.ops
));
6368 /* Disable RSC when in SR-IOV mode */
6369 adapter
->flags2
&= ~(IXGBE_FLAG2_RSC_CAPABLE
|
6370 IXGBE_FLAG2_RSC_ENABLED
);
6376 "Unable to allocate memory for VF "
6377 "Data Storage - SRIOV disabled\n");
6378 pci_disable_sriov(adapter
->pdev
);
6381 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
6382 adapter
->num_vfs
= 0;
6383 #endif /* CONFIG_PCI_IOV */
6387 * ixgbe_probe - Device Initialization Routine
6388 * @pdev: PCI device information struct
6389 * @ent: entry in ixgbe_pci_tbl
6391 * Returns 0 on success, negative on failure
6393 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6394 * The OS initialization, configuring of the adapter private structure,
6395 * and a hardware reset occur.
6397 static int __devinit
ixgbe_probe(struct pci_dev
*pdev
,
6398 const struct pci_device_id
*ent
)
6400 struct net_device
*netdev
;
6401 struct ixgbe_adapter
*adapter
= NULL
;
6402 struct ixgbe_hw
*hw
;
6403 const struct ixgbe_info
*ii
= ixgbe_info_tbl
[ent
->driver_data
];
6404 static int cards_found
;
6405 int i
, err
, pci_using_dac
;
6406 unsigned int indices
= num_possible_cpus();
6412 err
= pci_enable_device_mem(pdev
);
6416 if (!dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(64)) &&
6417 !dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(64))) {
6420 err
= dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(32));
6422 err
= dma_set_coherent_mask(&pdev
->dev
,
6425 dev_err(&pdev
->dev
, "No usable DMA "
6426 "configuration, aborting\n");
6433 err
= pci_request_selected_regions(pdev
, pci_select_bars(pdev
,
6434 IORESOURCE_MEM
), ixgbe_driver_name
);
6437 "pci_request_selected_regions failed 0x%x\n", err
);
6441 pci_enable_pcie_error_reporting(pdev
);
6443 pci_set_master(pdev
);
6444 pci_save_state(pdev
);
6446 if (ii
->mac
== ixgbe_mac_82598EB
)
6447 indices
= min_t(unsigned int, indices
, IXGBE_MAX_RSS_INDICES
);
6449 indices
= min_t(unsigned int, indices
, IXGBE_MAX_FDIR_INDICES
);
6451 indices
= max_t(unsigned int, indices
, IXGBE_MAX_DCB_INDICES
);
6453 indices
+= min_t(unsigned int, num_possible_cpus(),
6454 IXGBE_MAX_FCOE_INDICES
);
6456 netdev
= alloc_etherdev_mq(sizeof(struct ixgbe_adapter
), indices
);
6459 goto err_alloc_etherdev
;
6462 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
6464 pci_set_drvdata(pdev
, netdev
);
6465 adapter
= netdev_priv(netdev
);
6467 adapter
->netdev
= netdev
;
6468 adapter
->pdev
= pdev
;
6471 adapter
->msg_enable
= (1 << DEFAULT_DEBUG_LEVEL_SHIFT
) - 1;
6473 hw
->hw_addr
= ioremap(pci_resource_start(pdev
, 0),
6474 pci_resource_len(pdev
, 0));
6480 for (i
= 1; i
<= 5; i
++) {
6481 if (pci_resource_len(pdev
, i
) == 0)
6485 netdev
->netdev_ops
= &ixgbe_netdev_ops
;
6486 ixgbe_set_ethtool_ops(netdev
);
6487 netdev
->watchdog_timeo
= 5 * HZ
;
6488 strcpy(netdev
->name
, pci_name(pdev
));
6490 adapter
->bd_number
= cards_found
;
6493 memcpy(&hw
->mac
.ops
, ii
->mac_ops
, sizeof(hw
->mac
.ops
));
6494 hw
->mac
.type
= ii
->mac
;
6497 memcpy(&hw
->eeprom
.ops
, ii
->eeprom_ops
, sizeof(hw
->eeprom
.ops
));
6498 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
6499 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6500 if (!(eec
& (1 << 8)))
6501 hw
->eeprom
.ops
.read
= &ixgbe_read_eeprom_bit_bang_generic
;
6504 memcpy(&hw
->phy
.ops
, ii
->phy_ops
, sizeof(hw
->phy
.ops
));
6505 hw
->phy
.sfp_type
= ixgbe_sfp_type_unknown
;
6506 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6507 hw
->phy
.mdio
.prtad
= MDIO_PRTAD_NONE
;
6508 hw
->phy
.mdio
.mmds
= 0;
6509 hw
->phy
.mdio
.mode_support
= MDIO_SUPPORTS_C45
| MDIO_EMULATE_C22
;
6510 hw
->phy
.mdio
.dev
= netdev
;
6511 hw
->phy
.mdio
.mdio_read
= ixgbe_mdio_read
;
6512 hw
->phy
.mdio
.mdio_write
= ixgbe_mdio_write
;
6514 /* set up this timer and work struct before calling get_invariants
6515 * which might start the timer
6517 init_timer(&adapter
->sfp_timer
);
6518 adapter
->sfp_timer
.function
= &ixgbe_sfp_timer
;
6519 adapter
->sfp_timer
.data
= (unsigned long) adapter
;
6521 INIT_WORK(&adapter
->sfp_task
, ixgbe_sfp_task
);
6523 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6524 INIT_WORK(&adapter
->multispeed_fiber_task
, ixgbe_multispeed_fiber_task
);
6526 /* a new SFP+ module arrival, called from GPI SDP2 context */
6527 INIT_WORK(&adapter
->sfp_config_module_task
,
6528 ixgbe_sfp_config_module_task
);
6530 ii
->get_invariants(hw
);
6532 /* setup the private structure */
6533 err
= ixgbe_sw_init(adapter
);
6537 /* Make it possible the adapter to be woken up via WOL */
6538 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
6539 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
6542 * If there is a fan on this device and it has failed log the
6545 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
6546 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
6547 if (esdp
& IXGBE_ESDP_SDP1
)
6548 DPRINTK(PROBE
, CRIT
,
6549 "Fan has stopped, replace the adapter\n");
6552 /* reset_hw fills in the perm_addr as well */
6553 err
= hw
->mac
.ops
.reset_hw(hw
);
6554 if (err
== IXGBE_ERR_SFP_NOT_PRESENT
&&
6555 hw
->mac
.type
== ixgbe_mac_82598EB
) {
6557 * Start a kernel thread to watch for a module to arrive.
6558 * Only do this for 82598, since 82599 will generate
6559 * interrupts on module arrival.
6561 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
6562 mod_timer(&adapter
->sfp_timer
,
6563 round_jiffies(jiffies
+ (2 * HZ
)));
6565 } else if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
6566 dev_err(&adapter
->pdev
->dev
, "failed to initialize because "
6567 "an unsupported SFP+ module type was detected.\n"
6568 "Reload the driver after installing a supported "
6572 dev_err(&adapter
->pdev
->dev
, "HW Init failed: %d\n", err
);
6576 ixgbe_probe_vf(adapter
, ii
);
6578 netdev
->features
= NETIF_F_SG
|
6580 NETIF_F_HW_VLAN_TX
|
6581 NETIF_F_HW_VLAN_RX
|
6582 NETIF_F_HW_VLAN_FILTER
;
6584 netdev
->features
|= NETIF_F_IPV6_CSUM
;
6585 netdev
->features
|= NETIF_F_TSO
;
6586 netdev
->features
|= NETIF_F_TSO6
;
6587 netdev
->features
|= NETIF_F_GRO
;
6589 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
6590 netdev
->features
|= NETIF_F_SCTP_CSUM
;
6592 netdev
->vlan_features
|= NETIF_F_TSO
;
6593 netdev
->vlan_features
|= NETIF_F_TSO6
;
6594 netdev
->vlan_features
|= NETIF_F_IP_CSUM
;
6595 netdev
->vlan_features
|= NETIF_F_IPV6_CSUM
;
6596 netdev
->vlan_features
|= NETIF_F_SG
;
6598 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
6599 adapter
->flags
&= ~(IXGBE_FLAG_RSS_ENABLED
|
6600 IXGBE_FLAG_DCB_ENABLED
);
6601 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)
6602 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
6604 #ifdef CONFIG_IXGBE_DCB
6605 netdev
->dcbnl_ops
= &dcbnl_ops
;
6609 if (adapter
->flags
& IXGBE_FLAG_FCOE_CAPABLE
) {
6610 if (hw
->mac
.ops
.get_device_caps
) {
6611 hw
->mac
.ops
.get_device_caps(hw
, &device_caps
);
6612 if (device_caps
& IXGBE_DEVICE_CAPS_FCOE_OFFLOADS
)
6613 adapter
->flags
&= ~IXGBE_FLAG_FCOE_CAPABLE
;
6616 #endif /* IXGBE_FCOE */
6618 netdev
->features
|= NETIF_F_HIGHDMA
;
6620 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
)
6621 netdev
->features
|= NETIF_F_LRO
;
6623 /* make sure the EEPROM is good */
6624 if (hw
->eeprom
.ops
.validate_checksum(hw
, NULL
) < 0) {
6625 dev_err(&pdev
->dev
, "The EEPROM Checksum Is Not Valid\n");
6630 memcpy(netdev
->dev_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
6631 memcpy(netdev
->perm_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
6633 if (ixgbe_validate_mac_addr(netdev
->perm_addr
)) {
6634 dev_err(&pdev
->dev
, "invalid MAC address\n");
6639 /* power down the optics */
6640 if (hw
->phy
.multispeed_fiber
)
6641 hw
->mac
.ops
.disable_tx_laser(hw
);
6643 init_timer(&adapter
->watchdog_timer
);
6644 adapter
->watchdog_timer
.function
= &ixgbe_watchdog
;
6645 adapter
->watchdog_timer
.data
= (unsigned long)adapter
;
6647 INIT_WORK(&adapter
->reset_task
, ixgbe_reset_task
);
6648 INIT_WORK(&adapter
->watchdog_task
, ixgbe_watchdog_task
);
6650 err
= ixgbe_init_interrupt_scheme(adapter
);
6654 switch (pdev
->device
) {
6655 case IXGBE_DEV_ID_82599_KX4
:
6656 adapter
->wol
= (IXGBE_WUFC_MAG
| IXGBE_WUFC_EX
|
6657 IXGBE_WUFC_MC
| IXGBE_WUFC_BC
);
6663 device_set_wakeup_enable(&adapter
->pdev
->dev
, adapter
->wol
);
6665 /* pick up the PCI bus settings for reporting later */
6666 hw
->mac
.ops
.get_bus_info(hw
);
6668 /* print bus type/speed/width info */
6669 dev_info(&pdev
->dev
, "(PCI Express:%s:%s) %pM\n",
6670 ((hw
->bus
.speed
== ixgbe_bus_speed_5000
) ? "5.0Gb/s":
6671 (hw
->bus
.speed
== ixgbe_bus_speed_2500
) ? "2.5Gb/s":"Unknown"),
6672 ((hw
->bus
.width
== ixgbe_bus_width_pcie_x8
) ? "Width x8" :
6673 (hw
->bus
.width
== ixgbe_bus_width_pcie_x4
) ? "Width x4" :
6674 (hw
->bus
.width
== ixgbe_bus_width_pcie_x1
) ? "Width x1" :
6677 ixgbe_read_pba_num_generic(hw
, &part_num
);
6678 if (ixgbe_is_sfp(hw
) && hw
->phy
.sfp_type
!= ixgbe_sfp_type_not_present
)
6679 dev_info(&pdev
->dev
, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
6680 hw
->mac
.type
, hw
->phy
.type
, hw
->phy
.sfp_type
,
6681 (part_num
>> 8), (part_num
& 0xff));
6683 dev_info(&pdev
->dev
, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6684 hw
->mac
.type
, hw
->phy
.type
,
6685 (part_num
>> 8), (part_num
& 0xff));
6687 if (hw
->bus
.width
<= ixgbe_bus_width_pcie_x4
) {
6688 dev_warn(&pdev
->dev
, "PCI-Express bandwidth available for "
6689 "this card is not sufficient for optimal "
6691 dev_warn(&pdev
->dev
, "For optimal performance a x8 "
6692 "PCI-Express slot is required.\n");
6695 /* save off EEPROM version number */
6696 hw
->eeprom
.ops
.read(hw
, 0x29, &adapter
->eeprom_version
);
6698 /* reset the hardware with the new settings */
6699 err
= hw
->mac
.ops
.start_hw(hw
);
6701 if (err
== IXGBE_ERR_EEPROM_VERSION
) {
6702 /* We are running on a pre-production device, log a warning */
6703 dev_warn(&pdev
->dev
, "This device is a pre-production "
6704 "adapter/LOM. Please be aware there may be issues "
6705 "associated with your hardware. If you are "
6706 "experiencing problems please contact your Intel or "
6707 "hardware representative who provided you with this "
6710 strcpy(netdev
->name
, "eth%d");
6711 err
= register_netdev(netdev
);
6715 /* carrier off reporting is important to ethtool even BEFORE open */
6716 netif_carrier_off(netdev
);
6718 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
6719 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
6720 INIT_WORK(&adapter
->fdir_reinit_task
, ixgbe_fdir_reinit_task
);
6722 #ifdef CONFIG_IXGBE_DCA
6723 if (dca_add_requester(&pdev
->dev
) == 0) {
6724 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
6725 ixgbe_setup_dca(adapter
);
6728 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
6729 DPRINTK(PROBE
, INFO
, "IOV is enabled with %d VFs\n",
6731 for (i
= 0; i
< adapter
->num_vfs
; i
++)
6732 ixgbe_vf_configuration(pdev
, (i
| 0x10000000));
6735 /* add san mac addr to netdev */
6736 ixgbe_add_sanmac_netdev(netdev
);
6738 dev_info(&pdev
->dev
, "Intel(R) 10 Gigabit Network Connection\n");
6743 ixgbe_release_hw_control(adapter
);
6744 ixgbe_clear_interrupt_scheme(adapter
);
6747 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
6748 ixgbe_disable_sriov(adapter
);
6749 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
6750 del_timer_sync(&adapter
->sfp_timer
);
6751 cancel_work_sync(&adapter
->sfp_task
);
6752 cancel_work_sync(&adapter
->multispeed_fiber_task
);
6753 cancel_work_sync(&adapter
->sfp_config_module_task
);
6754 iounmap(hw
->hw_addr
);
6756 free_netdev(netdev
);
6758 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
6762 pci_disable_device(pdev
);
6767 * ixgbe_remove - Device Removal Routine
6768 * @pdev: PCI device information struct
6770 * ixgbe_remove is called by the PCI subsystem to alert the driver
6771 * that it should release a PCI device. The could be caused by a
6772 * Hot-Plug event, or because the driver is going to be removed from
6775 static void __devexit
ixgbe_remove(struct pci_dev
*pdev
)
6777 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6778 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6780 set_bit(__IXGBE_DOWN
, &adapter
->state
);
6781 /* clear the module not found bit to make sure the worker won't
6784 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
6785 del_timer_sync(&adapter
->watchdog_timer
);
6787 del_timer_sync(&adapter
->sfp_timer
);
6788 cancel_work_sync(&adapter
->watchdog_task
);
6789 cancel_work_sync(&adapter
->sfp_task
);
6790 cancel_work_sync(&adapter
->multispeed_fiber_task
);
6791 cancel_work_sync(&adapter
->sfp_config_module_task
);
6792 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
6793 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
6794 cancel_work_sync(&adapter
->fdir_reinit_task
);
6795 flush_scheduled_work();
6797 #ifdef CONFIG_IXGBE_DCA
6798 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
6799 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
6800 dca_remove_requester(&pdev
->dev
);
6801 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
6806 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
6807 ixgbe_cleanup_fcoe(adapter
);
6809 #endif /* IXGBE_FCOE */
6811 /* remove the added san mac */
6812 ixgbe_del_sanmac_netdev(netdev
);
6814 if (netdev
->reg_state
== NETREG_REGISTERED
)
6815 unregister_netdev(netdev
);
6817 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
6818 ixgbe_disable_sriov(adapter
);
6820 ixgbe_clear_interrupt_scheme(adapter
);
6822 ixgbe_release_hw_control(adapter
);
6824 iounmap(adapter
->hw
.hw_addr
);
6825 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
6828 DPRINTK(PROBE
, INFO
, "complete\n");
6830 free_netdev(netdev
);
6832 pci_disable_pcie_error_reporting(pdev
);
6834 pci_disable_device(pdev
);
6838 * ixgbe_io_error_detected - called when PCI error is detected
6839 * @pdev: Pointer to PCI device
6840 * @state: The current pci connection state
6842 * This function is called after a PCI bus error affecting
6843 * this device has been detected.
6845 static pci_ers_result_t
ixgbe_io_error_detected(struct pci_dev
*pdev
,
6846 pci_channel_state_t state
)
6848 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6849 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6851 netif_device_detach(netdev
);
6853 if (state
== pci_channel_io_perm_failure
)
6854 return PCI_ERS_RESULT_DISCONNECT
;
6856 if (netif_running(netdev
))
6857 ixgbe_down(adapter
);
6858 pci_disable_device(pdev
);
6860 /* Request a slot reset. */
6861 return PCI_ERS_RESULT_NEED_RESET
;
6865 * ixgbe_io_slot_reset - called after the pci bus has been reset.
6866 * @pdev: Pointer to PCI device
6868 * Restart the card from scratch, as if from a cold-boot.
6870 static pci_ers_result_t
ixgbe_io_slot_reset(struct pci_dev
*pdev
)
6872 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6873 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6874 pci_ers_result_t result
;
6877 if (pci_enable_device_mem(pdev
)) {
6879 "Cannot re-enable PCI device after reset.\n");
6880 result
= PCI_ERS_RESULT_DISCONNECT
;
6882 pci_set_master(pdev
);
6883 pci_restore_state(pdev
);
6884 pci_save_state(pdev
);
6886 pci_wake_from_d3(pdev
, false);
6888 ixgbe_reset(adapter
);
6889 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
6890 result
= PCI_ERS_RESULT_RECOVERED
;
6893 err
= pci_cleanup_aer_uncorrect_error_status(pdev
);
6896 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err
);
6897 /* non-fatal, continue */
6904 * ixgbe_io_resume - called when traffic can start flowing again.
6905 * @pdev: Pointer to PCI device
6907 * This callback is called when the error recovery driver tells us that
6908 * its OK to resume normal operation.
6910 static void ixgbe_io_resume(struct pci_dev
*pdev
)
6912 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6913 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6915 if (netif_running(netdev
)) {
6916 if (ixgbe_up(adapter
)) {
6917 DPRINTK(PROBE
, INFO
, "ixgbe_up failed after reset\n");
6922 netif_device_attach(netdev
);
6925 static struct pci_error_handlers ixgbe_err_handler
= {
6926 .error_detected
= ixgbe_io_error_detected
,
6927 .slot_reset
= ixgbe_io_slot_reset
,
6928 .resume
= ixgbe_io_resume
,
6931 static struct pci_driver ixgbe_driver
= {
6932 .name
= ixgbe_driver_name
,
6933 .id_table
= ixgbe_pci_tbl
,
6934 .probe
= ixgbe_probe
,
6935 .remove
= __devexit_p(ixgbe_remove
),
6937 .suspend
= ixgbe_suspend
,
6938 .resume
= ixgbe_resume
,
6940 .shutdown
= ixgbe_shutdown
,
6941 .err_handler
= &ixgbe_err_handler
6945 * ixgbe_init_module - Driver Registration Routine
6947 * ixgbe_init_module is the first routine called when the driver is
6948 * loaded. All it does is register with the PCI subsystem.
6950 static int __init
ixgbe_init_module(void)
6953 printk(KERN_INFO
"%s: %s - version %s\n", ixgbe_driver_name
,
6954 ixgbe_driver_string
, ixgbe_driver_version
);
6956 printk(KERN_INFO
"%s: %s\n", ixgbe_driver_name
, ixgbe_copyright
);
6958 #ifdef CONFIG_IXGBE_DCA
6959 dca_register_notify(&dca_notifier
);
6962 ret
= pci_register_driver(&ixgbe_driver
);
6966 module_init(ixgbe_init_module
);
6969 * ixgbe_exit_module - Driver Exit Cleanup Routine
6971 * ixgbe_exit_module is called just before the driver is removed
6974 static void __exit
ixgbe_exit_module(void)
6976 #ifdef CONFIG_IXGBE_DCA
6977 dca_unregister_notify(&dca_notifier
);
6979 pci_unregister_driver(&ixgbe_driver
);
6982 #ifdef CONFIG_IXGBE_DCA
6983 static int ixgbe_notify_dca(struct notifier_block
*nb
, unsigned long event
,
6988 ret_val
= driver_for_each_device(&ixgbe_driver
.driver
, NULL
, &event
,
6989 __ixgbe_notify_dca
);
6991 return ret_val
? NOTIFY_BAD
: NOTIFY_DONE
;
6994 #endif /* CONFIG_IXGBE_DCA */
6997 * ixgbe_get_hw_dev_name - return device name string
6998 * used by hardware layer to print debugging information
7000 char *ixgbe_get_hw_dev_name(struct ixgbe_hw
*hw
)
7002 struct ixgbe_adapter
*adapter
= hw
->back
;
7003 return adapter
->netdev
->name
;
7007 module_exit(ixgbe_exit_module
);