1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <linux/slab.h>
40 #include <net/checksum.h>
41 #include <net/ip6_checksum.h>
42 #include <linux/ethtool.h>
43 #include <linux/if_vlan.h>
44 #include <scsi/fc/fc_fcoe.h>
47 #include "ixgbe_common.h"
48 #include "ixgbe_dcb_82599.h"
49 #include "ixgbe_sriov.h"
51 char ixgbe_driver_name
[] = "ixgbe";
52 static const char ixgbe_driver_string
[] =
53 "Intel(R) 10 Gigabit PCI Express Network Driver";
55 #define DRV_VERSION "2.0.84-k2"
56 const char ixgbe_driver_version
[] = DRV_VERSION
;
57 static char ixgbe_copyright
[] = "Copyright (c) 1999-2010 Intel Corporation.";
59 static const struct ixgbe_info
*ixgbe_info_tbl
[] = {
60 [board_82598
] = &ixgbe_82598_info
,
61 [board_82599
] = &ixgbe_82599_info
,
64 /* ixgbe_pci_tbl - PCI Device ID Table
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl
) = {
73 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598
),
75 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_DUAL_PORT
),
77 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_SINGLE_PORT
),
79 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT
),
81 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT2
),
83 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_CX4
),
85 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_CX4_DUAL_PORT
),
87 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_DA_DUAL_PORT
),
89 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM
),
91 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_XF_LR
),
93 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_SFP_LOM
),
95 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_BX
),
97 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4
),
99 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_XAUI_LOM
),
101 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KR
),
103 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP
),
105 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP_EM
),
107 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4_MEZZ
),
109 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_CX4
),
111 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_T3_LOM
),
113 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_COMBO_BACKPLANE
),
116 /* required last entry */
119 MODULE_DEVICE_TABLE(pci
, ixgbe_pci_tbl
);
121 #ifdef CONFIG_IXGBE_DCA
122 static int ixgbe_notify_dca(struct notifier_block
*, unsigned long event
,
124 static struct notifier_block dca_notifier
= {
125 .notifier_call
= ixgbe_notify_dca
,
131 #ifdef CONFIG_PCI_IOV
132 static unsigned int max_vfs
;
133 module_param(max_vfs
, uint
, 0);
134 MODULE_PARM_DESC(max_vfs
, "Maximum number of virtual functions to allocate "
135 "per physical function");
136 #endif /* CONFIG_PCI_IOV */
138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
140 MODULE_LICENSE("GPL");
141 MODULE_VERSION(DRV_VERSION
);
143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter
*adapter
)
147 struct ixgbe_hw
*hw
= &adapter
->hw
;
152 #ifdef CONFIG_PCI_IOV
153 /* disable iov and allow time for transactions to clear */
154 pci_disable_sriov(adapter
->pdev
);
157 /* turn off device IOV mode */
158 gcr
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
159 gcr
&= ~(IXGBE_GCR_EXT_SRIOV
);
160 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, gcr
);
161 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
162 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
163 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
165 /* set default pool back to 0 */
166 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
167 vmdctl
&= ~IXGBE_VT_CTL_POOL_MASK
;
168 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
);
170 /* take a breather then clean up driver data */
173 kfree(adapter
->vfinfo
);
174 adapter
->vfinfo
= NULL
;
176 adapter
->num_vfs
= 0;
177 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
180 struct ixgbe_reg_info
{
185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl
[] = {
187 /* General Registers */
188 {IXGBE_CTRL
, "CTRL"},
189 {IXGBE_STATUS
, "STATUS"},
190 {IXGBE_CTRL_EXT
, "CTRL_EXT"},
192 /* Interrupt Registers */
193 {IXGBE_EICR
, "EICR"},
196 {IXGBE_SRRCTL(0), "SRRCTL"},
197 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
198 {IXGBE_RDLEN(0), "RDLEN"},
199 {IXGBE_RDH(0), "RDH"},
200 {IXGBE_RDT(0), "RDT"},
201 {IXGBE_RXDCTL(0), "RXDCTL"},
202 {IXGBE_RDBAL(0), "RDBAL"},
203 {IXGBE_RDBAH(0), "RDBAH"},
206 {IXGBE_TDBAL(0), "TDBAL"},
207 {IXGBE_TDBAH(0), "TDBAH"},
208 {IXGBE_TDLEN(0), "TDLEN"},
209 {IXGBE_TDH(0), "TDH"},
210 {IXGBE_TDT(0), "TDT"},
211 {IXGBE_TXDCTL(0), "TXDCTL"},
213 /* List Terminator */
219 * ixgbe_regdump - register printout routine
221 static void ixgbe_regdump(struct ixgbe_hw
*hw
, struct ixgbe_reg_info
*reginfo
)
227 switch (reginfo
->ofs
) {
228 case IXGBE_SRRCTL(0):
229 for (i
= 0; i
< 64; i
++)
230 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_SRRCTL(i
));
232 case IXGBE_DCA_RXCTRL(0):
233 for (i
= 0; i
< 64; i
++)
234 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_DCA_RXCTRL(i
));
237 for (i
= 0; i
< 64; i
++)
238 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDLEN(i
));
241 for (i
= 0; i
< 64; i
++)
242 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDH(i
));
245 for (i
= 0; i
< 64; i
++)
246 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDT(i
));
248 case IXGBE_RXDCTL(0):
249 for (i
= 0; i
< 64; i
++)
250 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RXDCTL(i
));
253 for (i
= 0; i
< 64; i
++)
254 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDBAL(i
));
257 for (i
= 0; i
< 64; i
++)
258 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDBAH(i
));
261 for (i
= 0; i
< 64; i
++)
262 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDBAL(i
));
265 for (i
= 0; i
< 64; i
++)
266 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDBAH(i
));
269 for (i
= 0; i
< 64; i
++)
270 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDLEN(i
));
273 for (i
= 0; i
< 64; i
++)
274 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDH(i
));
277 for (i
= 0; i
< 64; i
++)
278 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDT(i
));
280 case IXGBE_TXDCTL(0):
281 for (i
= 0; i
< 64; i
++)
282 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TXDCTL(i
));
285 printk(KERN_INFO
"%-15s %08x\n", reginfo
->name
,
286 IXGBE_READ_REG(hw
, reginfo
->ofs
));
290 for (i
= 0; i
< 8; i
++) {
291 snprintf(rname
, 16, "%s[%d-%d]", reginfo
->name
, i
*8, i
*8+7);
292 printk(KERN_ERR
"%-15s ", rname
);
293 for (j
= 0; j
< 8; j
++)
294 printk(KERN_CONT
"%08x ", regs
[i
*8+j
]);
295 printk(KERN_CONT
"\n");
301 * ixgbe_dump - Print registers, tx-rings and rx-rings
303 static void ixgbe_dump(struct ixgbe_adapter
*adapter
)
305 struct net_device
*netdev
= adapter
->netdev
;
306 struct ixgbe_hw
*hw
= &adapter
->hw
;
307 struct ixgbe_reg_info
*reginfo
;
309 struct ixgbe_ring
*tx_ring
;
310 struct ixgbe_tx_buffer
*tx_buffer_info
;
311 union ixgbe_adv_tx_desc
*tx_desc
;
312 struct my_u0
{ u64 a
; u64 b
; } *u0
;
313 struct ixgbe_ring
*rx_ring
;
314 union ixgbe_adv_rx_desc
*rx_desc
;
315 struct ixgbe_rx_buffer
*rx_buffer_info
;
319 if (!netif_msg_hw(adapter
))
322 /* Print netdevice Info */
324 dev_info(&adapter
->pdev
->dev
, "Net device Info\n");
325 printk(KERN_INFO
"Device Name state "
326 "trans_start last_rx\n");
327 printk(KERN_INFO
"%-15s %016lX %016lX %016lX\n",
334 /* Print Registers */
335 dev_info(&adapter
->pdev
->dev
, "Register Dump\n");
336 printk(KERN_INFO
" Register Name Value\n");
337 for (reginfo
= (struct ixgbe_reg_info
*)ixgbe_reg_info_tbl
;
338 reginfo
->name
; reginfo
++) {
339 ixgbe_regdump(hw
, reginfo
);
342 /* Print TX Ring Summary */
343 if (!netdev
|| !netif_running(netdev
))
346 dev_info(&adapter
->pdev
->dev
, "TX Rings Summary\n");
347 printk(KERN_INFO
"Queue [NTU] [NTC] [bi(ntc)->dma ] "
348 "leng ntw timestamp\n");
349 for (n
= 0; n
< adapter
->num_tx_queues
; n
++) {
350 tx_ring
= adapter
->tx_ring
[n
];
352 &tx_ring
->tx_buffer_info
[tx_ring
->next_to_clean
];
353 printk(KERN_INFO
" %5d %5X %5X %016llX %04X %3X %016llX\n",
354 n
, tx_ring
->next_to_use
, tx_ring
->next_to_clean
,
355 (u64
)tx_buffer_info
->dma
,
356 tx_buffer_info
->length
,
357 tx_buffer_info
->next_to_watch
,
358 (u64
)tx_buffer_info
->time_stamp
);
362 if (!netif_msg_tx_done(adapter
))
363 goto rx_ring_summary
;
365 dev_info(&adapter
->pdev
->dev
, "TX Rings Dump\n");
367 /* Transmit Descriptor Formats
369 * Advanced Transmit Descriptor
370 * +--------------------------------------------------------------+
371 * 0 | Buffer Address [63:0] |
372 * +--------------------------------------------------------------+
373 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
374 * +--------------------------------------------------------------+
375 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
378 for (n
= 0; n
< adapter
->num_tx_queues
; n
++) {
379 tx_ring
= adapter
->tx_ring
[n
];
380 printk(KERN_INFO
"------------------------------------\n");
381 printk(KERN_INFO
"TX QUEUE INDEX = %d\n", tx_ring
->queue_index
);
382 printk(KERN_INFO
"------------------------------------\n");
383 printk(KERN_INFO
"T [desc] [address 63:0 ] "
384 "[PlPOIdStDDt Ln] [bi->dma ] "
385 "leng ntw timestamp bi->skb\n");
387 for (i
= 0; tx_ring
->desc
&& (i
< tx_ring
->count
); i
++) {
388 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, i
);
389 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
390 u0
= (struct my_u0
*)tx_desc
;
391 printk(KERN_INFO
"T [0x%03X] %016llX %016llX %016llX"
392 " %04X %3X %016llX %p", i
,
395 (u64
)tx_buffer_info
->dma
,
396 tx_buffer_info
->length
,
397 tx_buffer_info
->next_to_watch
,
398 (u64
)tx_buffer_info
->time_stamp
,
399 tx_buffer_info
->skb
);
400 if (i
== tx_ring
->next_to_use
&&
401 i
== tx_ring
->next_to_clean
)
402 printk(KERN_CONT
" NTC/U\n");
403 else if (i
== tx_ring
->next_to_use
)
404 printk(KERN_CONT
" NTU\n");
405 else if (i
== tx_ring
->next_to_clean
)
406 printk(KERN_CONT
" NTC\n");
408 printk(KERN_CONT
"\n");
410 if (netif_msg_pktdata(adapter
) &&
411 tx_buffer_info
->dma
!= 0)
412 print_hex_dump(KERN_INFO
, "",
413 DUMP_PREFIX_ADDRESS
, 16, 1,
414 phys_to_virt(tx_buffer_info
->dma
),
415 tx_buffer_info
->length
, true);
419 /* Print RX Rings Summary */
421 dev_info(&adapter
->pdev
->dev
, "RX Rings Summary\n");
422 printk(KERN_INFO
"Queue [NTU] [NTC]\n");
423 for (n
= 0; n
< adapter
->num_rx_queues
; n
++) {
424 rx_ring
= adapter
->rx_ring
[n
];
425 printk(KERN_INFO
"%5d %5X %5X\n", n
,
426 rx_ring
->next_to_use
, rx_ring
->next_to_clean
);
430 if (!netif_msg_rx_status(adapter
))
433 dev_info(&adapter
->pdev
->dev
, "RX Rings Dump\n");
435 /* Advanced Receive Descriptor (Read) Format
437 * +-----------------------------------------------------+
438 * 0 | Packet Buffer Address [63:1] |A0/NSE|
439 * +----------------------------------------------+------+
440 * 8 | Header Buffer Address [63:1] | DD |
441 * +-----------------------------------------------------+
444 * Advanced Receive Descriptor (Write-Back) Format
446 * 63 48 47 32 31 30 21 20 16 15 4 3 0
447 * +------------------------------------------------------+
448 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
449 * | Checksum Ident | | | | Type | Type |
450 * +------------------------------------------------------+
451 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
452 * +------------------------------------------------------+
453 * 63 48 47 32 31 20 19 0
455 for (n
= 0; n
< adapter
->num_rx_queues
; n
++) {
456 rx_ring
= adapter
->rx_ring
[n
];
457 printk(KERN_INFO
"------------------------------------\n");
458 printk(KERN_INFO
"RX QUEUE INDEX = %d\n", rx_ring
->queue_index
);
459 printk(KERN_INFO
"------------------------------------\n");
460 printk(KERN_INFO
"R [desc] [ PktBuf A0] "
461 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
462 "<-- Adv Rx Read format\n");
463 printk(KERN_INFO
"RWB[desc] [PcsmIpSHl PtRs] "
464 "[vl er S cks ln] ---------------- [bi->skb] "
465 "<-- Adv Rx Write-Back format\n");
467 for (i
= 0; i
< rx_ring
->count
; i
++) {
468 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
469 rx_desc
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
470 u0
= (struct my_u0
*)rx_desc
;
471 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
472 if (staterr
& IXGBE_RXD_STAT_DD
) {
473 /* Descriptor Done */
474 printk(KERN_INFO
"RWB[0x%03X] %016llX "
475 "%016llX ---------------- %p", i
,
478 rx_buffer_info
->skb
);
480 printk(KERN_INFO
"R [0x%03X] %016llX "
481 "%016llX %016llX %p", i
,
484 (u64
)rx_buffer_info
->dma
,
485 rx_buffer_info
->skb
);
487 if (netif_msg_pktdata(adapter
)) {
488 print_hex_dump(KERN_INFO
, "",
489 DUMP_PREFIX_ADDRESS
, 16, 1,
490 phys_to_virt(rx_buffer_info
->dma
),
491 rx_ring
->rx_buf_len
, true);
493 if (rx_ring
->rx_buf_len
494 < IXGBE_RXBUFFER_2048
)
495 print_hex_dump(KERN_INFO
, "",
496 DUMP_PREFIX_ADDRESS
, 16, 1,
498 rx_buffer_info
->page_dma
+
499 rx_buffer_info
->page_offset
505 if (i
== rx_ring
->next_to_use
)
506 printk(KERN_CONT
" NTU\n");
507 else if (i
== rx_ring
->next_to_clean
)
508 printk(KERN_CONT
" NTC\n");
510 printk(KERN_CONT
"\n");
519 static void ixgbe_release_hw_control(struct ixgbe_adapter
*adapter
)
523 /* Let firmware take over control of h/w */
524 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
525 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
526 ctrl_ext
& ~IXGBE_CTRL_EXT_DRV_LOAD
);
529 static void ixgbe_get_hw_control(struct ixgbe_adapter
*adapter
)
533 /* Let firmware know the driver has taken over */
534 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
535 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
536 ctrl_ext
| IXGBE_CTRL_EXT_DRV_LOAD
);
540 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
541 * @adapter: pointer to adapter struct
542 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
543 * @queue: queue to map the corresponding interrupt to
544 * @msix_vector: the vector to map to the corresponding queue
547 static void ixgbe_set_ivar(struct ixgbe_adapter
*adapter
, s8 direction
,
548 u8 queue
, u8 msix_vector
)
551 struct ixgbe_hw
*hw
= &adapter
->hw
;
552 switch (hw
->mac
.type
) {
553 case ixgbe_mac_82598EB
:
554 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
557 index
= (((direction
* 64) + queue
) >> 2) & 0x1F;
558 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(index
));
559 ivar
&= ~(0xFF << (8 * (queue
& 0x3)));
560 ivar
|= (msix_vector
<< (8 * (queue
& 0x3)));
561 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(index
), ivar
);
563 case ixgbe_mac_82599EB
:
564 if (direction
== -1) {
566 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
567 index
= ((queue
& 1) * 8);
568 ivar
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_IVAR_MISC
);
569 ivar
&= ~(0xFF << index
);
570 ivar
|= (msix_vector
<< index
);
571 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_IVAR_MISC
, ivar
);
574 /* tx or rx causes */
575 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
576 index
= ((16 * (queue
& 1)) + (8 * direction
));
577 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(queue
>> 1));
578 ivar
&= ~(0xFF << index
);
579 ivar
|= (msix_vector
<< index
);
580 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(queue
>> 1), ivar
);
588 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter
*adapter
,
593 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
594 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
595 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS
, mask
);
597 mask
= (qmask
& 0xFFFFFFFF);
598 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(0), mask
);
599 mask
= (qmask
>> 32);
600 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(1), mask
);
604 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter
*adapter
,
605 struct ixgbe_tx_buffer
608 if (tx_buffer_info
->dma
) {
609 if (tx_buffer_info
->mapped_as_page
)
610 dma_unmap_page(&adapter
->pdev
->dev
,
612 tx_buffer_info
->length
,
615 dma_unmap_single(&adapter
->pdev
->dev
,
617 tx_buffer_info
->length
,
619 tx_buffer_info
->dma
= 0;
621 if (tx_buffer_info
->skb
) {
622 dev_kfree_skb_any(tx_buffer_info
->skb
);
623 tx_buffer_info
->skb
= NULL
;
625 tx_buffer_info
->time_stamp
= 0;
626 /* tx_buffer_info must be completely set up in the transmit path */
630 * ixgbe_tx_xon_state - check the tx ring xon state
631 * @adapter: the ixgbe adapter
632 * @tx_ring: the corresponding tx_ring
634 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
635 * corresponding TC of this tx_ring when checking TFCS.
637 * Returns : true if in xon state (currently not paused)
639 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter
*adapter
,
640 struct ixgbe_ring
*tx_ring
)
642 u32 txoff
= IXGBE_TFCS_TXOFF
;
644 #ifdef CONFIG_IXGBE_DCB
645 if (adapter
->dcb_cfg
.pfc_mode_enable
) {
647 int reg_idx
= tx_ring
->reg_idx
;
648 int dcb_i
= adapter
->ring_feature
[RING_F_DCB
].indices
;
650 switch (adapter
->hw
.mac
.type
) {
651 case ixgbe_mac_82598EB
:
653 txoff
= IXGBE_TFCS_TXOFF0
;
655 case ixgbe_mac_82599EB
:
657 txoff
= IXGBE_TFCS_TXOFF
;
661 if (tc
== 2) /* TC2, TC3 */
662 tc
+= (reg_idx
- 64) >> 4;
663 else if (tc
== 3) /* TC4, TC5, TC6, TC7 */
664 tc
+= 1 + ((reg_idx
- 96) >> 3);
665 } else if (dcb_i
== 4) {
669 tc
+= (reg_idx
- 64) >> 5;
670 if (tc
== 2) /* TC2, TC3 */
671 tc
+= (reg_idx
- 96) >> 4;
681 return IXGBE_READ_REG(&adapter
->hw
, IXGBE_TFCS
) & txoff
;
684 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter
*adapter
,
685 struct ixgbe_ring
*tx_ring
,
688 struct ixgbe_hw
*hw
= &adapter
->hw
;
690 /* Detect a transmit hang in hardware, this serializes the
691 * check with the clearing of time_stamp and movement of eop */
692 adapter
->detect_tx_hung
= false;
693 if (tx_ring
->tx_buffer_info
[eop
].time_stamp
&&
694 time_after(jiffies
, tx_ring
->tx_buffer_info
[eop
].time_stamp
+ HZ
) &&
695 ixgbe_tx_xon_state(adapter
, tx_ring
)) {
696 /* detected Tx unit hang */
697 union ixgbe_adv_tx_desc
*tx_desc
;
698 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, eop
);
699 e_err(drv
, "Detected Tx Unit Hang\n"
701 " TDH, TDT <%x>, <%x>\n"
702 " next_to_use <%x>\n"
703 " next_to_clean <%x>\n"
704 "tx_buffer_info[next_to_clean]\n"
705 " time_stamp <%lx>\n"
707 tx_ring
->queue_index
,
708 IXGBE_READ_REG(hw
, tx_ring
->head
),
709 IXGBE_READ_REG(hw
, tx_ring
->tail
),
710 tx_ring
->next_to_use
, eop
,
711 tx_ring
->tx_buffer_info
[eop
].time_stamp
, jiffies
);
718 #define IXGBE_MAX_TXD_PWR 14
719 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
721 /* Tx Descriptors needed, worst case */
722 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
723 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
724 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
725 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
727 static void ixgbe_tx_timeout(struct net_device
*netdev
);
730 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
731 * @q_vector: structure containing interrupt and ring information
732 * @tx_ring: tx ring to clean
734 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector
*q_vector
,
735 struct ixgbe_ring
*tx_ring
)
737 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
738 struct net_device
*netdev
= adapter
->netdev
;
739 union ixgbe_adv_tx_desc
*tx_desc
, *eop_desc
;
740 struct ixgbe_tx_buffer
*tx_buffer_info
;
741 unsigned int i
, eop
, count
= 0;
742 unsigned int total_bytes
= 0, total_packets
= 0;
744 i
= tx_ring
->next_to_clean
;
745 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
746 eop_desc
= IXGBE_TX_DESC_ADV(tx_ring
, eop
);
748 while ((eop_desc
->wb
.status
& cpu_to_le32(IXGBE_TXD_STAT_DD
)) &&
749 (count
< tx_ring
->work_limit
)) {
750 bool cleaned
= false;
751 rmb(); /* read buffer_info after eop_desc */
752 for ( ; !cleaned
; count
++) {
754 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, i
);
755 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
756 cleaned
= (i
== eop
);
757 skb
= tx_buffer_info
->skb
;
759 if (cleaned
&& skb
) {
760 unsigned int segs
, bytecount
;
761 unsigned int hlen
= skb_headlen(skb
);
763 /* gso_segs is currently only valid for tcp */
764 segs
= skb_shinfo(skb
)->gso_segs
?: 1;
766 /* adjust for FCoE Sequence Offload */
767 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
768 && (skb
->protocol
== htons(ETH_P_FCOE
)) &&
770 hlen
= skb_transport_offset(skb
) +
771 sizeof(struct fc_frame_header
) +
772 sizeof(struct fcoe_crc_eof
);
773 segs
= DIV_ROUND_UP(skb
->len
- hlen
,
774 skb_shinfo(skb
)->gso_size
);
776 #endif /* IXGBE_FCOE */
777 /* multiply data chunks by size of headers */
778 bytecount
= ((segs
- 1) * hlen
) + skb
->len
;
779 total_packets
+= segs
;
780 total_bytes
+= bytecount
;
783 ixgbe_unmap_and_free_tx_resource(adapter
,
786 tx_desc
->wb
.status
= 0;
789 if (i
== tx_ring
->count
)
793 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
794 eop_desc
= IXGBE_TX_DESC_ADV(tx_ring
, eop
);
797 tx_ring
->next_to_clean
= i
;
799 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
800 if (unlikely(count
&& netif_carrier_ok(netdev
) &&
801 (IXGBE_DESC_UNUSED(tx_ring
) >= TX_WAKE_THRESHOLD
))) {
802 /* Make sure that anybody stopping the queue after this
803 * sees the new next_to_clean.
806 if (__netif_subqueue_stopped(netdev
, tx_ring
->queue_index
) &&
807 !test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
808 netif_wake_subqueue(netdev
, tx_ring
->queue_index
);
809 ++tx_ring
->restart_queue
;
813 if (adapter
->detect_tx_hung
) {
814 if (ixgbe_check_tx_hang(adapter
, tx_ring
, i
)) {
815 /* schedule immediate reset if we believe we hung */
816 e_info(probe
, "tx hang %d detected, resetting "
817 "adapter\n", adapter
->tx_timeout_count
+ 1);
818 ixgbe_tx_timeout(adapter
->netdev
);
822 /* re-arm the interrupt */
823 if (count
>= tx_ring
->work_limit
)
824 ixgbe_irq_rearm_queues(adapter
, ((u64
)1 << q_vector
->v_idx
));
826 tx_ring
->total_bytes
+= total_bytes
;
827 tx_ring
->total_packets
+= total_packets
;
828 tx_ring
->stats
.packets
+= total_packets
;
829 tx_ring
->stats
.bytes
+= total_bytes
;
830 return (count
< tx_ring
->work_limit
);
833 #ifdef CONFIG_IXGBE_DCA
834 static void ixgbe_update_rx_dca(struct ixgbe_adapter
*adapter
,
835 struct ixgbe_ring
*rx_ring
)
839 int q
= rx_ring
->reg_idx
;
841 if (rx_ring
->cpu
!= cpu
) {
842 rxctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_DCA_RXCTRL(q
));
843 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
844 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK
;
845 rxctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
846 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
847 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599
;
848 rxctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
849 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599
);
851 rxctrl
|= IXGBE_DCA_RXCTRL_DESC_DCA_EN
;
852 rxctrl
|= IXGBE_DCA_RXCTRL_HEAD_DCA_EN
;
853 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN
);
854 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN
|
855 IXGBE_DCA_RXCTRL_DESC_HSRO_EN
);
856 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_RXCTRL(q
), rxctrl
);
862 static void ixgbe_update_tx_dca(struct ixgbe_adapter
*adapter
,
863 struct ixgbe_ring
*tx_ring
)
867 int q
= tx_ring
->reg_idx
;
868 struct ixgbe_hw
*hw
= &adapter
->hw
;
870 if (tx_ring
->cpu
!= cpu
) {
871 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
872 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL(q
));
873 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK
;
874 txctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
875 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
876 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL(q
), txctrl
);
877 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
878 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL_82599(q
));
879 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599
;
880 txctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
881 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599
);
882 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
883 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL_82599(q
), txctrl
);
890 static void ixgbe_setup_dca(struct ixgbe_adapter
*adapter
)
894 if (!(adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
))
897 /* always use CB2 mode, difference is masked in the CB driver */
898 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 2);
900 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
901 adapter
->tx_ring
[i
]->cpu
= -1;
902 ixgbe_update_tx_dca(adapter
, adapter
->tx_ring
[i
]);
904 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
905 adapter
->rx_ring
[i
]->cpu
= -1;
906 ixgbe_update_rx_dca(adapter
, adapter
->rx_ring
[i
]);
910 static int __ixgbe_notify_dca(struct device
*dev
, void *data
)
912 struct net_device
*netdev
= dev_get_drvdata(dev
);
913 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
914 unsigned long event
= *(unsigned long *)data
;
917 case DCA_PROVIDER_ADD
:
918 /* if we're already enabled, don't do it again */
919 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
921 if (dca_add_requester(dev
) == 0) {
922 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
923 ixgbe_setup_dca(adapter
);
926 /* Fall Through since DCA is disabled. */
927 case DCA_PROVIDER_REMOVE
:
928 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
929 dca_remove_requester(dev
);
930 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
931 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
939 #endif /* CONFIG_IXGBE_DCA */
941 * ixgbe_receive_skb - Send a completed packet up the stack
942 * @adapter: board private structure
943 * @skb: packet to send up
944 * @status: hardware indication of status of receive
945 * @rx_ring: rx descriptor ring (for a specific queue) to setup
946 * @rx_desc: rx descriptor
948 static void ixgbe_receive_skb(struct ixgbe_q_vector
*q_vector
,
949 struct sk_buff
*skb
, u8 status
,
950 struct ixgbe_ring
*ring
,
951 union ixgbe_adv_rx_desc
*rx_desc
)
953 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
954 struct napi_struct
*napi
= &q_vector
->napi
;
955 bool is_vlan
= (status
& IXGBE_RXD_STAT_VP
);
956 u16 tag
= le16_to_cpu(rx_desc
->wb
.upper
.vlan
);
958 if (!(adapter
->flags
& IXGBE_FLAG_IN_NETPOLL
)) {
959 if (adapter
->vlgrp
&& is_vlan
&& (tag
& VLAN_VID_MASK
))
960 vlan_gro_receive(napi
, adapter
->vlgrp
, tag
, skb
);
962 napi_gro_receive(napi
, skb
);
964 if (adapter
->vlgrp
&& is_vlan
&& (tag
& VLAN_VID_MASK
))
965 vlan_hwaccel_rx(skb
, adapter
->vlgrp
, tag
);
972 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
973 * @adapter: address of board private structure
974 * @status_err: hardware indication of status of receive
975 * @skb: skb currently being received and modified
977 static inline void ixgbe_rx_checksum(struct ixgbe_adapter
*adapter
,
978 union ixgbe_adv_rx_desc
*rx_desc
,
981 u32 status_err
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
983 skb
->ip_summed
= CHECKSUM_NONE
;
985 /* Rx csum disabled */
986 if (!(adapter
->flags
& IXGBE_FLAG_RX_CSUM_ENABLED
))
989 /* if IP and error */
990 if ((status_err
& IXGBE_RXD_STAT_IPCS
) &&
991 (status_err
& IXGBE_RXDADV_ERR_IPE
)) {
992 adapter
->hw_csum_rx_error
++;
996 if (!(status_err
& IXGBE_RXD_STAT_L4CS
))
999 if (status_err
& IXGBE_RXDADV_ERR_TCPE
) {
1000 u16 pkt_info
= rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
1003 * 82599 errata, UDP frames with a 0 checksum can be marked as
1006 if ((pkt_info
& IXGBE_RXDADV_PKTTYPE_UDP
) &&
1007 (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
))
1010 adapter
->hw_csum_rx_error
++;
1014 /* It must be a TCP or UDP packet with a valid checksum */
1015 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1018 static inline void ixgbe_release_rx_desc(struct ixgbe_hw
*hw
,
1019 struct ixgbe_ring
*rx_ring
, u32 val
)
1022 * Force memory writes to complete before letting h/w
1023 * know there are new descriptors to fetch. (Only
1024 * applicable for weak-ordered memory model archs,
1028 IXGBE_WRITE_REG(hw
, IXGBE_RDT(rx_ring
->reg_idx
), val
);
1032 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1033 * @adapter: address of board private structure
1035 void ixgbe_alloc_rx_buffers(struct ixgbe_adapter
*adapter
,
1036 struct ixgbe_ring
*rx_ring
,
1039 struct net_device
*netdev
= adapter
->netdev
;
1040 struct pci_dev
*pdev
= adapter
->pdev
;
1041 union ixgbe_adv_rx_desc
*rx_desc
;
1042 struct ixgbe_rx_buffer
*bi
;
1044 unsigned int bufsz
= rx_ring
->rx_buf_len
;
1046 i
= rx_ring
->next_to_use
;
1047 bi
= &rx_ring
->rx_buffer_info
[i
];
1049 while (cleaned_count
--) {
1050 rx_desc
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
1052 if (!bi
->page_dma
&&
1053 (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
)) {
1055 bi
->page
= netdev_alloc_page(netdev
);
1057 adapter
->alloc_rx_page_failed
++;
1060 bi
->page_offset
= 0;
1062 /* use a half page if we're re-using */
1063 bi
->page_offset
^= (PAGE_SIZE
/ 2);
1066 bi
->page_dma
= dma_map_page(&pdev
->dev
, bi
->page
,
1073 struct sk_buff
*skb
= netdev_alloc_skb_ip_align(netdev
,
1078 adapter
->alloc_rx_buff_failed
++;
1081 /* initialize queue mapping */
1082 skb_record_rx_queue(skb
, rx_ring
->queue_index
);
1086 bi
->dma
= dma_map_single(&pdev
->dev
,
1088 rx_ring
->rx_buf_len
,
1091 /* Refresh the desc even if buffer_addrs didn't change because
1092 * each write-back erases this info. */
1093 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
1094 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->page_dma
);
1095 rx_desc
->read
.hdr_addr
= cpu_to_le64(bi
->dma
);
1097 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->dma
);
1098 rx_desc
->read
.hdr_addr
= 0;
1102 if (i
== rx_ring
->count
)
1104 bi
= &rx_ring
->rx_buffer_info
[i
];
1108 if (rx_ring
->next_to_use
!= i
) {
1109 rx_ring
->next_to_use
= i
;
1111 i
= (rx_ring
->count
- 1);
1113 ixgbe_release_rx_desc(&adapter
->hw
, rx_ring
, i
);
1117 static inline u16
ixgbe_get_hdr_info(union ixgbe_adv_rx_desc
*rx_desc
)
1119 return rx_desc
->wb
.lower
.lo_dword
.hs_rss
.hdr_info
;
1122 static inline u16
ixgbe_get_pkt_info(union ixgbe_adv_rx_desc
*rx_desc
)
1124 return rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
1127 static inline u32
ixgbe_get_rsc_count(union ixgbe_adv_rx_desc
*rx_desc
)
1129 return (le32_to_cpu(rx_desc
->wb
.lower
.lo_dword
.data
) &
1130 IXGBE_RXDADV_RSCCNT_MASK
) >>
1131 IXGBE_RXDADV_RSCCNT_SHIFT
;
1135 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1136 * @skb: pointer to the last skb in the rsc queue
1137 * @count: pointer to number of packets coalesced in this context
1139 * This function changes a queue full of hw rsc buffers into a completed
1140 * packet. It uses the ->prev pointers to find the first packet and then
1141 * turns it into the frag list owner.
1143 static inline struct sk_buff
*ixgbe_transform_rsc_queue(struct sk_buff
*skb
,
1146 unsigned int frag_list_size
= 0;
1149 struct sk_buff
*prev
= skb
->prev
;
1150 frag_list_size
+= skb
->len
;
1156 skb_shinfo(skb
)->frag_list
= skb
->next
;
1158 skb
->len
+= frag_list_size
;
1159 skb
->data_len
+= frag_list_size
;
1160 skb
->truesize
+= frag_list_size
;
1164 struct ixgbe_rsc_cb
{
1169 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1171 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector
*q_vector
,
1172 struct ixgbe_ring
*rx_ring
,
1173 int *work_done
, int work_to_do
)
1175 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1176 struct net_device
*netdev
= adapter
->netdev
;
1177 struct pci_dev
*pdev
= adapter
->pdev
;
1178 union ixgbe_adv_rx_desc
*rx_desc
, *next_rxd
;
1179 struct ixgbe_rx_buffer
*rx_buffer_info
, *next_buffer
;
1180 struct sk_buff
*skb
;
1181 unsigned int i
, rsc_count
= 0;
1184 bool cleaned
= false;
1185 int cleaned_count
= 0;
1186 unsigned int total_rx_bytes
= 0, total_rx_packets
= 0;
1189 #endif /* IXGBE_FCOE */
1191 i
= rx_ring
->next_to_clean
;
1192 rx_desc
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
1193 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1194 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
1196 while (staterr
& IXGBE_RXD_STAT_DD
) {
1198 if (*work_done
>= work_to_do
)
1202 rmb(); /* read descriptor and rx_buffer_info after status DD */
1203 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
1204 hdr_info
= le16_to_cpu(ixgbe_get_hdr_info(rx_desc
));
1205 len
= (hdr_info
& IXGBE_RXDADV_HDRBUFLEN_MASK
) >>
1206 IXGBE_RXDADV_HDRBUFLEN_SHIFT
;
1207 upper_len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1208 if ((len
> IXGBE_RX_HDR_SIZE
) ||
1209 (upper_len
&& !(hdr_info
& IXGBE_RXDADV_SPH
)))
1210 len
= IXGBE_RX_HDR_SIZE
;
1212 len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1216 skb
= rx_buffer_info
->skb
;
1217 prefetch(skb
->data
);
1218 rx_buffer_info
->skb
= NULL
;
1220 if (rx_buffer_info
->dma
) {
1221 if ((adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) &&
1222 (!(staterr
& IXGBE_RXD_STAT_EOP
)) &&
1225 * When HWRSC is enabled, delay unmapping
1226 * of the first packet. It carries the
1227 * header information, HW may still
1228 * access the header after the writeback.
1229 * Only unmap it when EOP is reached
1231 IXGBE_RSC_CB(skb
)->delay_unmap
= true;
1232 IXGBE_RSC_CB(skb
)->dma
= rx_buffer_info
->dma
;
1234 dma_unmap_single(&pdev
->dev
,
1235 rx_buffer_info
->dma
,
1236 rx_ring
->rx_buf_len
,
1239 rx_buffer_info
->dma
= 0;
1244 dma_unmap_page(&pdev
->dev
, rx_buffer_info
->page_dma
,
1245 PAGE_SIZE
/ 2, DMA_FROM_DEVICE
);
1246 rx_buffer_info
->page_dma
= 0;
1247 skb_fill_page_desc(skb
, skb_shinfo(skb
)->nr_frags
,
1248 rx_buffer_info
->page
,
1249 rx_buffer_info
->page_offset
,
1252 if ((rx_ring
->rx_buf_len
> (PAGE_SIZE
/ 2)) ||
1253 (page_count(rx_buffer_info
->page
) != 1))
1254 rx_buffer_info
->page
= NULL
;
1256 get_page(rx_buffer_info
->page
);
1258 skb
->len
+= upper_len
;
1259 skb
->data_len
+= upper_len
;
1260 skb
->truesize
+= upper_len
;
1264 if (i
== rx_ring
->count
)
1267 next_rxd
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
1271 if (adapter
->flags2
& IXGBE_FLAG2_RSC_CAPABLE
)
1272 rsc_count
= ixgbe_get_rsc_count(rx_desc
);
1275 u32 nextp
= (staterr
& IXGBE_RXDADV_NEXTP_MASK
) >>
1276 IXGBE_RXDADV_NEXTP_SHIFT
;
1277 next_buffer
= &rx_ring
->rx_buffer_info
[nextp
];
1279 next_buffer
= &rx_ring
->rx_buffer_info
[i
];
1282 if (staterr
& IXGBE_RXD_STAT_EOP
) {
1284 skb
= ixgbe_transform_rsc_queue(skb
, &(rx_ring
->rsc_count
));
1285 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
1286 if (IXGBE_RSC_CB(skb
)->delay_unmap
) {
1287 dma_unmap_single(&pdev
->dev
,
1288 IXGBE_RSC_CB(skb
)->dma
,
1289 rx_ring
->rx_buf_len
,
1291 IXGBE_RSC_CB(skb
)->dma
= 0;
1292 IXGBE_RSC_CB(skb
)->delay_unmap
= false;
1294 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
)
1295 rx_ring
->rsc_count
+= skb_shinfo(skb
)->nr_frags
;
1297 rx_ring
->rsc_count
++;
1298 rx_ring
->rsc_flush
++;
1300 rx_ring
->stats
.packets
++;
1301 rx_ring
->stats
.bytes
+= skb
->len
;
1303 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
1304 rx_buffer_info
->skb
= next_buffer
->skb
;
1305 rx_buffer_info
->dma
= next_buffer
->dma
;
1306 next_buffer
->skb
= skb
;
1307 next_buffer
->dma
= 0;
1309 skb
->next
= next_buffer
->skb
;
1310 skb
->next
->prev
= skb
;
1312 rx_ring
->non_eop_descs
++;
1316 if (staterr
& IXGBE_RXDADV_ERR_FRAME_ERR_MASK
) {
1317 dev_kfree_skb_irq(skb
);
1321 ixgbe_rx_checksum(adapter
, rx_desc
, skb
);
1323 /* probably a little skewed due to removing CRC */
1324 total_rx_bytes
+= skb
->len
;
1327 skb
->protocol
= eth_type_trans(skb
, adapter
->netdev
);
1329 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1330 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
1331 ddp_bytes
= ixgbe_fcoe_ddp(adapter
, rx_desc
, skb
);
1335 #endif /* IXGBE_FCOE */
1336 ixgbe_receive_skb(q_vector
, skb
, staterr
, rx_ring
, rx_desc
);
1339 rx_desc
->wb
.upper
.status_error
= 0;
1341 /* return some buffers to hardware, one at a time is too slow */
1342 if (cleaned_count
>= IXGBE_RX_BUFFER_WRITE
) {
1343 ixgbe_alloc_rx_buffers(adapter
, rx_ring
, cleaned_count
);
1347 /* use prefetched values */
1349 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
1351 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1354 rx_ring
->next_to_clean
= i
;
1355 cleaned_count
= IXGBE_DESC_UNUSED(rx_ring
);
1358 ixgbe_alloc_rx_buffers(adapter
, rx_ring
, cleaned_count
);
1361 /* include DDPed FCoE data */
1362 if (ddp_bytes
> 0) {
1365 mss
= adapter
->netdev
->mtu
- sizeof(struct fcoe_hdr
) -
1366 sizeof(struct fc_frame_header
) -
1367 sizeof(struct fcoe_crc_eof
);
1370 total_rx_bytes
+= ddp_bytes
;
1371 total_rx_packets
+= DIV_ROUND_UP(ddp_bytes
, mss
);
1373 #endif /* IXGBE_FCOE */
1375 rx_ring
->total_packets
+= total_rx_packets
;
1376 rx_ring
->total_bytes
+= total_rx_bytes
;
1377 netdev
->stats
.rx_bytes
+= total_rx_bytes
;
1378 netdev
->stats
.rx_packets
+= total_rx_packets
;
1383 static int ixgbe_clean_rxonly(struct napi_struct
*, int);
1385 * ixgbe_configure_msix - Configure MSI-X hardware
1386 * @adapter: board private structure
1388 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1391 static void ixgbe_configure_msix(struct ixgbe_adapter
*adapter
)
1393 struct ixgbe_q_vector
*q_vector
;
1394 int i
, j
, q_vectors
, v_idx
, r_idx
;
1397 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1400 * Populate the IVAR table and set the ITR values to the
1401 * corresponding register.
1403 for (v_idx
= 0; v_idx
< q_vectors
; v_idx
++) {
1404 q_vector
= adapter
->q_vector
[v_idx
];
1405 /* XXX for_each_set_bit(...) */
1406 r_idx
= find_first_bit(q_vector
->rxr_idx
,
1407 adapter
->num_rx_queues
);
1409 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1410 j
= adapter
->rx_ring
[r_idx
]->reg_idx
;
1411 ixgbe_set_ivar(adapter
, 0, j
, v_idx
);
1412 r_idx
= find_next_bit(q_vector
->rxr_idx
,
1413 adapter
->num_rx_queues
,
1416 r_idx
= find_first_bit(q_vector
->txr_idx
,
1417 adapter
->num_tx_queues
);
1419 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1420 j
= adapter
->tx_ring
[r_idx
]->reg_idx
;
1421 ixgbe_set_ivar(adapter
, 1, j
, v_idx
);
1422 r_idx
= find_next_bit(q_vector
->txr_idx
,
1423 adapter
->num_tx_queues
,
1427 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
1429 q_vector
->eitr
= adapter
->tx_eitr_param
;
1430 else if (q_vector
->rxr_count
)
1432 q_vector
->eitr
= adapter
->rx_eitr_param
;
1434 ixgbe_write_eitr(q_vector
);
1437 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
1438 ixgbe_set_ivar(adapter
, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX
,
1440 else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
1441 ixgbe_set_ivar(adapter
, -1, 1, v_idx
);
1442 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITR(v_idx
), 1950);
1444 /* set up to autoclear timer, and the vectors */
1445 mask
= IXGBE_EIMS_ENABLE_MASK
;
1446 if (adapter
->num_vfs
)
1447 mask
&= ~(IXGBE_EIMS_OTHER
|
1448 IXGBE_EIMS_MAILBOX
|
1451 mask
&= ~(IXGBE_EIMS_OTHER
| IXGBE_EIMS_LSC
);
1452 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIAC
, mask
);
1455 enum latency_range
{
1459 latency_invalid
= 255
1463 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1464 * @adapter: pointer to adapter
1465 * @eitr: eitr setting (ints per sec) to give last timeslice
1466 * @itr_setting: current throttle rate in ints/second
1467 * @packets: the number of packets during this measurement interval
1468 * @bytes: the number of bytes during this measurement interval
1470 * Stores a new ITR value based on packets and byte
1471 * counts during the last interrupt. The advantage of per interrupt
1472 * computation is faster updates and more accurate ITR for the current
1473 * traffic pattern. Constants in this function were computed
1474 * based on theoretical maximum wire speed and thresholds were set based
1475 * on testing data as well as attempting to minimize response time
1476 * while increasing bulk throughput.
1477 * this functionality is controlled by the InterruptThrottleRate module
1478 * parameter (see ixgbe_param.c)
1480 static u8
ixgbe_update_itr(struct ixgbe_adapter
*adapter
,
1481 u32 eitr
, u8 itr_setting
,
1482 int packets
, int bytes
)
1484 unsigned int retval
= itr_setting
;
1489 goto update_itr_done
;
1492 /* simple throttlerate management
1493 * 0-20MB/s lowest (100000 ints/s)
1494 * 20-100MB/s low (20000 ints/s)
1495 * 100-1249MB/s bulk (8000 ints/s)
1497 /* what was last interrupt timeslice? */
1498 timepassed_us
= 1000000/eitr
;
1499 bytes_perint
= bytes
/ timepassed_us
; /* bytes/usec */
1501 switch (itr_setting
) {
1502 case lowest_latency
:
1503 if (bytes_perint
> adapter
->eitr_low
)
1504 retval
= low_latency
;
1507 if (bytes_perint
> adapter
->eitr_high
)
1508 retval
= bulk_latency
;
1509 else if (bytes_perint
<= adapter
->eitr_low
)
1510 retval
= lowest_latency
;
1513 if (bytes_perint
<= adapter
->eitr_high
)
1514 retval
= low_latency
;
1523 * ixgbe_write_eitr - write EITR register in hardware specific way
1524 * @q_vector: structure containing interrupt and ring information
1526 * This function is made to be called by ethtool and by the driver
1527 * when it needs to update EITR registers at runtime. Hardware
1528 * specific quirks/differences are taken care of here.
1530 void ixgbe_write_eitr(struct ixgbe_q_vector
*q_vector
)
1532 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1533 struct ixgbe_hw
*hw
= &adapter
->hw
;
1534 int v_idx
= q_vector
->v_idx
;
1535 u32 itr_reg
= EITR_INTS_PER_SEC_TO_REG(q_vector
->eitr
);
1537 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1538 /* must write high and low 16 bits to reset counter */
1539 itr_reg
|= (itr_reg
<< 16);
1540 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
1542 * 82599 can support a value of zero, so allow it for
1543 * max interrupt rate, but there is an errata where it can
1544 * not be zero with RSC
1547 !(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
))
1551 * set the WDIS bit to not clear the timer bits and cause an
1552 * immediate assertion of the interrupt
1554 itr_reg
|= IXGBE_EITR_CNT_WDIS
;
1556 IXGBE_WRITE_REG(hw
, IXGBE_EITR(v_idx
), itr_reg
);
1559 static void ixgbe_set_itr_msix(struct ixgbe_q_vector
*q_vector
)
1561 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1563 u8 current_itr
, ret_itr
;
1565 struct ixgbe_ring
*rx_ring
, *tx_ring
;
1567 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1568 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1569 tx_ring
= adapter
->tx_ring
[r_idx
];
1570 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1572 tx_ring
->total_packets
,
1573 tx_ring
->total_bytes
);
1574 /* if the result for this queue would decrease interrupt
1575 * rate for this vector then use that result */
1576 q_vector
->tx_itr
= ((q_vector
->tx_itr
> ret_itr
) ?
1577 q_vector
->tx_itr
- 1 : ret_itr
);
1578 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1582 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1583 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1584 rx_ring
= adapter
->rx_ring
[r_idx
];
1585 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1587 rx_ring
->total_packets
,
1588 rx_ring
->total_bytes
);
1589 /* if the result for this queue would decrease interrupt
1590 * rate for this vector then use that result */
1591 q_vector
->rx_itr
= ((q_vector
->rx_itr
> ret_itr
) ?
1592 q_vector
->rx_itr
- 1 : ret_itr
);
1593 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1597 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
1599 switch (current_itr
) {
1600 /* counts and packets in update_itr are dependent on these numbers */
1601 case lowest_latency
:
1605 new_itr
= 20000; /* aka hwitr = ~200 */
1613 if (new_itr
!= q_vector
->eitr
) {
1614 /* do an exponential smoothing */
1615 new_itr
= ((q_vector
->eitr
* 90)/100) + ((new_itr
* 10)/100);
1617 /* save the algorithm value here, not the smoothed one */
1618 q_vector
->eitr
= new_itr
;
1620 ixgbe_write_eitr(q_vector
);
1625 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1626 * @work: pointer to work_struct containing our data
1628 static void ixgbe_check_overtemp_task(struct work_struct
*work
)
1630 struct ixgbe_adapter
*adapter
= container_of(work
,
1631 struct ixgbe_adapter
,
1632 check_overtemp_task
);
1633 struct ixgbe_hw
*hw
= &adapter
->hw
;
1634 u32 eicr
= adapter
->interrupt_event
;
1636 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) {
1637 switch (hw
->device_id
) {
1638 case IXGBE_DEV_ID_82599_T3_LOM
: {
1640 bool link_up
= false;
1642 if (hw
->mac
.ops
.check_link
)
1643 hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
1645 if (((eicr
& IXGBE_EICR_GPI_SDP0
) && (!link_up
)) ||
1646 (eicr
& IXGBE_EICR_LSC
))
1647 /* Check if this is due to overtemp */
1648 if (hw
->phy
.ops
.check_overtemp(hw
) == IXGBE_ERR_OVERTEMP
)
1653 if (!(eicr
& IXGBE_EICR_GPI_SDP0
))
1657 e_crit(drv
, "Network adapter has been stopped because it has "
1658 "over heated. Restart the computer. If the problem "
1659 "persists, power off the system and replace the "
1661 /* write to clear the interrupt */
1662 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP0
);
1666 static void ixgbe_check_fan_failure(struct ixgbe_adapter
*adapter
, u32 eicr
)
1668 struct ixgbe_hw
*hw
= &adapter
->hw
;
1670 if ((adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) &&
1671 (eicr
& IXGBE_EICR_GPI_SDP1
)) {
1672 e_crit(probe
, "Fan has stopped, replace the adapter\n");
1673 /* write to clear the interrupt */
1674 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1678 static void ixgbe_check_sfp_event(struct ixgbe_adapter
*adapter
, u32 eicr
)
1680 struct ixgbe_hw
*hw
= &adapter
->hw
;
1682 if (eicr
& IXGBE_EICR_GPI_SDP1
) {
1683 /* Clear the interrupt */
1684 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1685 schedule_work(&adapter
->multispeed_fiber_task
);
1686 } else if (eicr
& IXGBE_EICR_GPI_SDP2
) {
1687 /* Clear the interrupt */
1688 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP2
);
1689 schedule_work(&adapter
->sfp_config_module_task
);
1691 /* Interrupt isn't for us... */
1696 static void ixgbe_check_lsc(struct ixgbe_adapter
*adapter
)
1698 struct ixgbe_hw
*hw
= &adapter
->hw
;
1701 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
1702 adapter
->link_check_timeout
= jiffies
;
1703 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1704 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_EIMC_LSC
);
1705 IXGBE_WRITE_FLUSH(hw
);
1706 schedule_work(&adapter
->watchdog_task
);
1710 static irqreturn_t
ixgbe_msix_lsc(int irq
, void *data
)
1712 struct net_device
*netdev
= data
;
1713 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
1714 struct ixgbe_hw
*hw
= &adapter
->hw
;
1718 * Workaround for Silicon errata. Use clear-by-write instead
1719 * of clear-by-read. Reading with EICS will return the
1720 * interrupt causes without clearing, which later be done
1721 * with the write to EICR.
1723 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICS
);
1724 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, eicr
);
1726 if (eicr
& IXGBE_EICR_LSC
)
1727 ixgbe_check_lsc(adapter
);
1729 if (eicr
& IXGBE_EICR_MAILBOX
)
1730 ixgbe_msg_task(adapter
);
1732 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
1733 ixgbe_check_fan_failure(adapter
, eicr
);
1735 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
1736 ixgbe_check_sfp_event(adapter
, eicr
);
1737 adapter
->interrupt_event
= eicr
;
1738 if ((adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) &&
1739 ((eicr
& IXGBE_EICR_GPI_SDP0
) || (eicr
& IXGBE_EICR_LSC
)))
1740 schedule_work(&adapter
->check_overtemp_task
);
1742 /* Handle Flow Director Full threshold interrupt */
1743 if (eicr
& IXGBE_EICR_FLOW_DIR
) {
1745 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_FLOW_DIR
);
1746 /* Disable transmits before FDIR Re-initialization */
1747 netif_tx_stop_all_queues(netdev
);
1748 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
1749 struct ixgbe_ring
*tx_ring
=
1750 adapter
->tx_ring
[i
];
1751 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE
,
1752 &tx_ring
->reinit_state
))
1753 schedule_work(&adapter
->fdir_reinit_task
);
1757 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1758 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMS_OTHER
);
1763 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter
*adapter
,
1768 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1769 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1770 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
1772 mask
= (qmask
& 0xFFFFFFFF);
1773 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS_EX(0), mask
);
1774 mask
= (qmask
>> 32);
1775 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS_EX(1), mask
);
1777 /* skip the flush */
1780 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter
*adapter
,
1785 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1786 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1787 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, mask
);
1789 mask
= (qmask
& 0xFFFFFFFF);
1790 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), mask
);
1791 mask
= (qmask
>> 32);
1792 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1), mask
);
1794 /* skip the flush */
1797 static irqreturn_t
ixgbe_msix_clean_tx(int irq
, void *data
)
1799 struct ixgbe_q_vector
*q_vector
= data
;
1800 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1801 struct ixgbe_ring
*tx_ring
;
1804 if (!q_vector
->txr_count
)
1807 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1808 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1809 tx_ring
= adapter
->tx_ring
[r_idx
];
1810 tx_ring
->total_bytes
= 0;
1811 tx_ring
->total_packets
= 0;
1812 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1816 /* EIAM disabled interrupts (on this vector) for us */
1817 napi_schedule(&q_vector
->napi
);
1823 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1825 * @data: pointer to our q_vector struct for this interrupt vector
1827 static irqreturn_t
ixgbe_msix_clean_rx(int irq
, void *data
)
1829 struct ixgbe_q_vector
*q_vector
= data
;
1830 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1831 struct ixgbe_ring
*rx_ring
;
1835 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1836 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1837 rx_ring
= adapter
->rx_ring
[r_idx
];
1838 rx_ring
->total_bytes
= 0;
1839 rx_ring
->total_packets
= 0;
1840 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1844 if (!q_vector
->rxr_count
)
1847 /* disable interrupts on this vector only */
1848 /* EIAM disabled interrupts (on this vector) for us */
1849 napi_schedule(&q_vector
->napi
);
1854 static irqreturn_t
ixgbe_msix_clean_many(int irq
, void *data
)
1856 struct ixgbe_q_vector
*q_vector
= data
;
1857 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1858 struct ixgbe_ring
*ring
;
1862 if (!q_vector
->txr_count
&& !q_vector
->rxr_count
)
1865 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1866 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1867 ring
= adapter
->tx_ring
[r_idx
];
1868 ring
->total_bytes
= 0;
1869 ring
->total_packets
= 0;
1870 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1874 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1875 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1876 ring
= adapter
->rx_ring
[r_idx
];
1877 ring
->total_bytes
= 0;
1878 ring
->total_packets
= 0;
1879 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1883 /* EIAM disabled interrupts (on this vector) for us */
1884 napi_schedule(&q_vector
->napi
);
1890 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1891 * @napi: napi struct with our devices info in it
1892 * @budget: amount of work driver is allowed to do this pass, in packets
1894 * This function is optimized for cleaning one queue only on a single
1897 static int ixgbe_clean_rxonly(struct napi_struct
*napi
, int budget
)
1899 struct ixgbe_q_vector
*q_vector
=
1900 container_of(napi
, struct ixgbe_q_vector
, napi
);
1901 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1902 struct ixgbe_ring
*rx_ring
= NULL
;
1906 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1907 rx_ring
= adapter
->rx_ring
[r_idx
];
1908 #ifdef CONFIG_IXGBE_DCA
1909 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1910 ixgbe_update_rx_dca(adapter
, rx_ring
);
1913 ixgbe_clean_rx_irq(q_vector
, rx_ring
, &work_done
, budget
);
1915 /* If all Rx work done, exit the polling mode */
1916 if (work_done
< budget
) {
1917 napi_complete(napi
);
1918 if (adapter
->rx_itr_setting
& 1)
1919 ixgbe_set_itr_msix(q_vector
);
1920 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1921 ixgbe_irq_enable_queues(adapter
,
1922 ((u64
)1 << q_vector
->v_idx
));
1929 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1930 * @napi: napi struct with our devices info in it
1931 * @budget: amount of work driver is allowed to do this pass, in packets
1933 * This function will clean more than one rx queue associated with a
1936 static int ixgbe_clean_rxtx_many(struct napi_struct
*napi
, int budget
)
1938 struct ixgbe_q_vector
*q_vector
=
1939 container_of(napi
, struct ixgbe_q_vector
, napi
);
1940 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1941 struct ixgbe_ring
*ring
= NULL
;
1942 int work_done
= 0, i
;
1944 bool tx_clean_complete
= true;
1946 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1947 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1948 ring
= adapter
->tx_ring
[r_idx
];
1949 #ifdef CONFIG_IXGBE_DCA
1950 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1951 ixgbe_update_tx_dca(adapter
, ring
);
1953 tx_clean_complete
&= ixgbe_clean_tx_irq(q_vector
, ring
);
1954 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1958 /* attempt to distribute budget to each queue fairly, but don't allow
1959 * the budget to go below 1 because we'll exit polling */
1960 budget
/= (q_vector
->rxr_count
?: 1);
1961 budget
= max(budget
, 1);
1962 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1963 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1964 ring
= adapter
->rx_ring
[r_idx
];
1965 #ifdef CONFIG_IXGBE_DCA
1966 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1967 ixgbe_update_rx_dca(adapter
, ring
);
1969 ixgbe_clean_rx_irq(q_vector
, ring
, &work_done
, budget
);
1970 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1974 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1975 ring
= adapter
->rx_ring
[r_idx
];
1976 /* If all Rx work done, exit the polling mode */
1977 if (work_done
< budget
) {
1978 napi_complete(napi
);
1979 if (adapter
->rx_itr_setting
& 1)
1980 ixgbe_set_itr_msix(q_vector
);
1981 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1982 ixgbe_irq_enable_queues(adapter
,
1983 ((u64
)1 << q_vector
->v_idx
));
1991 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1992 * @napi: napi struct with our devices info in it
1993 * @budget: amount of work driver is allowed to do this pass, in packets
1995 * This function is optimized for cleaning one queue only on a single
1998 static int ixgbe_clean_txonly(struct napi_struct
*napi
, int budget
)
2000 struct ixgbe_q_vector
*q_vector
=
2001 container_of(napi
, struct ixgbe_q_vector
, napi
);
2002 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2003 struct ixgbe_ring
*tx_ring
= NULL
;
2007 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
2008 tx_ring
= adapter
->tx_ring
[r_idx
];
2009 #ifdef CONFIG_IXGBE_DCA
2010 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
2011 ixgbe_update_tx_dca(adapter
, tx_ring
);
2014 if (!ixgbe_clean_tx_irq(q_vector
, tx_ring
))
2017 /* If all Tx work done, exit the polling mode */
2018 if (work_done
< budget
) {
2019 napi_complete(napi
);
2020 if (adapter
->tx_itr_setting
& 1)
2021 ixgbe_set_itr_msix(q_vector
);
2022 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2023 ixgbe_irq_enable_queues(adapter
, ((u64
)1 << q_vector
->v_idx
));
2029 static inline void map_vector_to_rxq(struct ixgbe_adapter
*a
, int v_idx
,
2032 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
2034 set_bit(r_idx
, q_vector
->rxr_idx
);
2035 q_vector
->rxr_count
++;
2038 static inline void map_vector_to_txq(struct ixgbe_adapter
*a
, int v_idx
,
2041 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
2043 set_bit(t_idx
, q_vector
->txr_idx
);
2044 q_vector
->txr_count
++;
2048 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2049 * @adapter: board private structure to initialize
2050 * @vectors: allotted vector count for descriptor rings
2052 * This function maps descriptor rings to the queue-specific vectors
2053 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2054 * one vector per ring/queue, but on a constrained vector budget, we
2055 * group the rings as "efficiently" as possible. You would add new
2056 * mapping configurations in here.
2058 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter
*adapter
,
2062 int rxr_idx
= 0, txr_idx
= 0;
2063 int rxr_remaining
= adapter
->num_rx_queues
;
2064 int txr_remaining
= adapter
->num_tx_queues
;
2069 /* No mapping required if MSI-X is disabled. */
2070 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
2074 * The ideal configuration...
2075 * We have enough vectors to map one per queue.
2077 if (vectors
== adapter
->num_rx_queues
+ adapter
->num_tx_queues
) {
2078 for (; rxr_idx
< rxr_remaining
; v_start
++, rxr_idx
++)
2079 map_vector_to_rxq(adapter
, v_start
, rxr_idx
);
2081 for (; txr_idx
< txr_remaining
; v_start
++, txr_idx
++)
2082 map_vector_to_txq(adapter
, v_start
, txr_idx
);
2088 * If we don't have enough vectors for a 1-to-1
2089 * mapping, we'll have to group them so there are
2090 * multiple queues per vector.
2092 /* Re-adjusting *qpv takes care of the remainder. */
2093 for (i
= v_start
; i
< vectors
; i
++) {
2094 rqpv
= DIV_ROUND_UP(rxr_remaining
, vectors
- i
);
2095 for (j
= 0; j
< rqpv
; j
++) {
2096 map_vector_to_rxq(adapter
, i
, rxr_idx
);
2101 for (i
= v_start
; i
< vectors
; i
++) {
2102 tqpv
= DIV_ROUND_UP(txr_remaining
, vectors
- i
);
2103 for (j
= 0; j
< tqpv
; j
++) {
2104 map_vector_to_txq(adapter
, i
, txr_idx
);
2115 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2116 * @adapter: board private structure
2118 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2119 * interrupts from the kernel.
2121 static int ixgbe_request_msix_irqs(struct ixgbe_adapter
*adapter
)
2123 struct net_device
*netdev
= adapter
->netdev
;
2124 irqreturn_t (*handler
)(int, void *);
2125 int i
, vector
, q_vectors
, err
;
2128 /* Decrement for Other and TCP Timer vectors */
2129 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2131 /* Map the Tx/Rx rings to the vectors we were allotted. */
2132 err
= ixgbe_map_rings_to_vectors(adapter
, q_vectors
);
2136 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2137 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2138 &ixgbe_msix_clean_many)
2139 for (vector
= 0; vector
< q_vectors
; vector
++) {
2140 handler
= SET_HANDLER(adapter
->q_vector
[vector
]);
2142 if(handler
== &ixgbe_msix_clean_rx
) {
2143 sprintf(adapter
->name
[vector
], "%s-%s-%d",
2144 netdev
->name
, "rx", ri
++);
2146 else if(handler
== &ixgbe_msix_clean_tx
) {
2147 sprintf(adapter
->name
[vector
], "%s-%s-%d",
2148 netdev
->name
, "tx", ti
++);
2151 sprintf(adapter
->name
[vector
], "%s-%s-%d",
2152 netdev
->name
, "TxRx", vector
);
2154 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
2155 handler
, 0, adapter
->name
[vector
],
2156 adapter
->q_vector
[vector
]);
2158 e_err(probe
, "request_irq failed for MSIX interrupt "
2159 "Error: %d\n", err
);
2160 goto free_queue_irqs
;
2164 sprintf(adapter
->name
[vector
], "%s:lsc", netdev
->name
);
2165 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
2166 ixgbe_msix_lsc
, 0, adapter
->name
[vector
], netdev
);
2168 e_err(probe
, "request_irq for msix_lsc failed: %d\n", err
);
2169 goto free_queue_irqs
;
2175 for (i
= vector
- 1; i
>= 0; i
--)
2176 free_irq(adapter
->msix_entries
[--vector
].vector
,
2177 adapter
->q_vector
[i
]);
2178 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
2179 pci_disable_msix(adapter
->pdev
);
2180 kfree(adapter
->msix_entries
);
2181 adapter
->msix_entries
= NULL
;
2186 static void ixgbe_set_itr(struct ixgbe_adapter
*adapter
)
2188 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
2190 u32 new_itr
= q_vector
->eitr
;
2191 struct ixgbe_ring
*rx_ring
= adapter
->rx_ring
[0];
2192 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[0];
2194 q_vector
->tx_itr
= ixgbe_update_itr(adapter
, new_itr
,
2196 tx_ring
->total_packets
,
2197 tx_ring
->total_bytes
);
2198 q_vector
->rx_itr
= ixgbe_update_itr(adapter
, new_itr
,
2200 rx_ring
->total_packets
,
2201 rx_ring
->total_bytes
);
2203 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
2205 switch (current_itr
) {
2206 /* counts and packets in update_itr are dependent on these numbers */
2207 case lowest_latency
:
2211 new_itr
= 20000; /* aka hwitr = ~200 */
2220 if (new_itr
!= q_vector
->eitr
) {
2221 /* do an exponential smoothing */
2222 new_itr
= ((q_vector
->eitr
* 90)/100) + ((new_itr
* 10)/100);
2224 /* save the algorithm value here, not the smoothed one */
2225 q_vector
->eitr
= new_itr
;
2227 ixgbe_write_eitr(q_vector
);
2232 * ixgbe_irq_enable - Enable default interrupt generation settings
2233 * @adapter: board private structure
2235 static inline void ixgbe_irq_enable(struct ixgbe_adapter
*adapter
)
2239 mask
= (IXGBE_EIMS_ENABLE_MASK
& ~IXGBE_EIMS_RTX_QUEUE
);
2240 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
)
2241 mask
|= IXGBE_EIMS_GPI_SDP0
;
2242 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
)
2243 mask
|= IXGBE_EIMS_GPI_SDP1
;
2244 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
2245 mask
|= IXGBE_EIMS_ECC
;
2246 mask
|= IXGBE_EIMS_GPI_SDP1
;
2247 mask
|= IXGBE_EIMS_GPI_SDP2
;
2248 if (adapter
->num_vfs
)
2249 mask
|= IXGBE_EIMS_MAILBOX
;
2251 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
2252 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
2253 mask
|= IXGBE_EIMS_FLOW_DIR
;
2255 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
2256 ixgbe_irq_enable_queues(adapter
, ~0);
2257 IXGBE_WRITE_FLUSH(&adapter
->hw
);
2259 if (adapter
->num_vfs
> 32) {
2260 u32 eitrsel
= (1 << (adapter
->num_vfs
- 32)) - 1;
2261 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, eitrsel
);
2266 * ixgbe_intr - legacy mode Interrupt Handler
2267 * @irq: interrupt number
2268 * @data: pointer to a network interface device structure
2270 static irqreturn_t
ixgbe_intr(int irq
, void *data
)
2272 struct net_device
*netdev
= data
;
2273 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2274 struct ixgbe_hw
*hw
= &adapter
->hw
;
2275 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
2279 * Workaround for silicon errata. Mask the interrupts
2280 * before the read of EICR.
2282 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_IRQ_CLEAR_MASK
);
2284 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2285 * therefore no explict interrupt disable is necessary */
2286 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICR
);
2288 /* shared interrupt alert!
2289 * make sure interrupts are enabled because the read will
2290 * have disabled interrupts due to EIAM */
2291 ixgbe_irq_enable(adapter
);
2292 return IRQ_NONE
; /* Not our interrupt */
2295 if (eicr
& IXGBE_EICR_LSC
)
2296 ixgbe_check_lsc(adapter
);
2298 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
2299 ixgbe_check_sfp_event(adapter
, eicr
);
2301 ixgbe_check_fan_failure(adapter
, eicr
);
2302 if ((adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) &&
2303 ((eicr
& IXGBE_EICR_GPI_SDP0
) || (eicr
& IXGBE_EICR_LSC
)))
2304 schedule_work(&adapter
->check_overtemp_task
);
2306 if (napi_schedule_prep(&(q_vector
->napi
))) {
2307 adapter
->tx_ring
[0]->total_packets
= 0;
2308 adapter
->tx_ring
[0]->total_bytes
= 0;
2309 adapter
->rx_ring
[0]->total_packets
= 0;
2310 adapter
->rx_ring
[0]->total_bytes
= 0;
2311 /* would disable interrupts here but EIAM disabled it */
2312 __napi_schedule(&(q_vector
->napi
));
2318 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter
*adapter
)
2320 int i
, q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2322 for (i
= 0; i
< q_vectors
; i
++) {
2323 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
2324 bitmap_zero(q_vector
->rxr_idx
, MAX_RX_QUEUES
);
2325 bitmap_zero(q_vector
->txr_idx
, MAX_TX_QUEUES
);
2326 q_vector
->rxr_count
= 0;
2327 q_vector
->txr_count
= 0;
2332 * ixgbe_request_irq - initialize interrupts
2333 * @adapter: board private structure
2335 * Attempts to configure interrupts using the best available
2336 * capabilities of the hardware and kernel.
2338 static int ixgbe_request_irq(struct ixgbe_adapter
*adapter
)
2340 struct net_device
*netdev
= adapter
->netdev
;
2343 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2344 err
= ixgbe_request_msix_irqs(adapter
);
2345 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
2346 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, 0,
2347 netdev
->name
, netdev
);
2349 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, IRQF_SHARED
,
2350 netdev
->name
, netdev
);
2354 e_err(probe
, "request_irq failed, Error %d\n", err
);
2359 static void ixgbe_free_irq(struct ixgbe_adapter
*adapter
)
2361 struct net_device
*netdev
= adapter
->netdev
;
2363 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2366 q_vectors
= adapter
->num_msix_vectors
;
2369 free_irq(adapter
->msix_entries
[i
].vector
, netdev
);
2372 for (; i
>= 0; i
--) {
2373 free_irq(adapter
->msix_entries
[i
].vector
,
2374 adapter
->q_vector
[i
]);
2377 ixgbe_reset_q_vectors(adapter
);
2379 free_irq(adapter
->pdev
->irq
, netdev
);
2384 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2385 * @adapter: board private structure
2387 static inline void ixgbe_irq_disable(struct ixgbe_adapter
*adapter
)
2389 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
2390 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, ~0);
2392 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, 0xFFFF0000);
2393 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), ~0);
2394 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1), ~0);
2395 if (adapter
->num_vfs
> 32)
2396 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, 0);
2398 IXGBE_WRITE_FLUSH(&adapter
->hw
);
2399 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2401 for (i
= 0; i
< adapter
->num_msix_vectors
; i
++)
2402 synchronize_irq(adapter
->msix_entries
[i
].vector
);
2404 synchronize_irq(adapter
->pdev
->irq
);
2409 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2412 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter
*adapter
)
2414 struct ixgbe_hw
*hw
= &adapter
->hw
;
2416 IXGBE_WRITE_REG(hw
, IXGBE_EITR(0),
2417 EITR_INTS_PER_SEC_TO_REG(adapter
->rx_eitr_param
));
2419 ixgbe_set_ivar(adapter
, 0, 0, 0);
2420 ixgbe_set_ivar(adapter
, 1, 0, 0);
2422 map_vector_to_rxq(adapter
, 0, 0);
2423 map_vector_to_txq(adapter
, 0, 0);
2425 e_info(hw
, "Legacy interrupt IVAR setup done\n");
2429 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2430 * @adapter: board private structure
2431 * @ring: structure containing ring specific data
2433 * Configure the Tx descriptor ring after a reset.
2435 void ixgbe_configure_tx_ring(struct ixgbe_adapter
*adapter
,
2436 struct ixgbe_ring
*ring
)
2438 struct ixgbe_hw
*hw
= &adapter
->hw
;
2439 u64 tdba
= ring
->dma
;
2442 u16 reg_idx
= ring
->reg_idx
;
2444 /* disable queue to avoid issues while updating state */
2445 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(reg_idx
));
2446 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(reg_idx
),
2447 txdctl
& ~IXGBE_TXDCTL_ENABLE
);
2448 IXGBE_WRITE_FLUSH(hw
);
2450 IXGBE_WRITE_REG(hw
, IXGBE_TDBAL(reg_idx
),
2451 (tdba
& DMA_BIT_MASK(32)));
2452 IXGBE_WRITE_REG(hw
, IXGBE_TDBAH(reg_idx
), (tdba
>> 32));
2453 IXGBE_WRITE_REG(hw
, IXGBE_TDLEN(reg_idx
),
2454 ring
->count
* sizeof(union ixgbe_adv_tx_desc
));
2455 IXGBE_WRITE_REG(hw
, IXGBE_TDH(reg_idx
), 0);
2456 IXGBE_WRITE_REG(hw
, IXGBE_TDT(reg_idx
), 0);
2457 ring
->head
= IXGBE_TDH(reg_idx
);
2458 ring
->tail
= IXGBE_TDT(reg_idx
);
2460 /* configure fetching thresholds */
2461 if (adapter
->rx_itr_setting
== 0) {
2462 /* cannot set wthresh when itr==0 */
2463 txdctl
&= ~0x007F0000;
2465 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2466 txdctl
|= (8 << 16);
2468 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
2469 /* PThresh workaround for Tx hang with DFP enabled. */
2473 /* reinitialize flowdirector state */
2474 set_bit(__IXGBE_FDIR_INIT_DONE
, &ring
->reinit_state
);
2477 txdctl
|= IXGBE_TXDCTL_ENABLE
;
2478 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(reg_idx
), txdctl
);
2480 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2481 if (hw
->mac
.type
== ixgbe_mac_82598EB
&&
2482 !(IXGBE_READ_REG(hw
, IXGBE_LINKS
) & IXGBE_LINKS_UP
))
2485 /* poll to verify queue is enabled */
2488 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(reg_idx
));
2489 } while (--wait_loop
&& !(txdctl
& IXGBE_TXDCTL_ENABLE
));
2491 e_err(drv
, "Could not enable Tx Queue %d\n", reg_idx
);
2494 static void ixgbe_setup_mtqc(struct ixgbe_adapter
*adapter
)
2496 struct ixgbe_hw
*hw
= &adapter
->hw
;
2500 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2503 /* disable the arbiter while setting MTQC */
2504 rttdcs
= IXGBE_READ_REG(hw
, IXGBE_RTTDCS
);
2505 rttdcs
|= IXGBE_RTTDCS_ARBDIS
;
2506 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2508 /* set transmit pool layout */
2509 mask
= (IXGBE_FLAG_SRIOV_ENABLED
| IXGBE_FLAG_DCB_ENABLED
);
2510 switch (adapter
->flags
& mask
) {
2512 case (IXGBE_FLAG_SRIOV_ENABLED
):
2513 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
,
2514 (IXGBE_MTQC_VT_ENA
| IXGBE_MTQC_64VF
));
2517 case (IXGBE_FLAG_DCB_ENABLED
):
2518 /* We enable 8 traffic classes, DCB only */
2519 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
,
2520 (IXGBE_MTQC_RT_ENA
| IXGBE_MTQC_8TC_8TQ
));
2524 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
, IXGBE_MTQC_64Q_1PB
);
2528 /* re-enable the arbiter */
2529 rttdcs
&= ~IXGBE_RTTDCS_ARBDIS
;
2530 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2534 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2535 * @adapter: board private structure
2537 * Configure the Tx unit of the MAC after a reset.
2539 static void ixgbe_configure_tx(struct ixgbe_adapter
*adapter
)
2541 struct ixgbe_hw
*hw
= &adapter
->hw
;
2545 ixgbe_setup_mtqc(adapter
);
2547 if (hw
->mac
.type
!= ixgbe_mac_82598EB
) {
2548 /* DMATXCTL.EN must be before Tx queues are enabled */
2549 dmatxctl
= IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
);
2550 dmatxctl
|= IXGBE_DMATXCTL_TE
;
2551 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
, dmatxctl
);
2554 /* Setup the HW Tx Head and Tail descriptor pointers */
2555 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
2556 ixgbe_configure_tx_ring(adapter
, adapter
->tx_ring
[i
]);
2559 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2561 static void ixgbe_configure_srrctl(struct ixgbe_adapter
*adapter
,
2562 struct ixgbe_ring
*rx_ring
)
2566 struct ixgbe_ring_feature
*feature
= adapter
->ring_feature
;
2568 index
= rx_ring
->reg_idx
;
2569 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
2571 mask
= (unsigned long) feature
[RING_F_RSS
].mask
;
2572 index
= index
& mask
;
2574 srrctl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_SRRCTL(index
));
2576 srrctl
&= ~IXGBE_SRRCTL_BSIZEHDR_MASK
;
2577 srrctl
&= ~IXGBE_SRRCTL_BSIZEPKT_MASK
;
2578 if (adapter
->num_vfs
)
2579 srrctl
|= IXGBE_SRRCTL_DROP_EN
;
2581 srrctl
|= (IXGBE_RX_HDR_SIZE
<< IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT
) &
2582 IXGBE_SRRCTL_BSIZEHDR_MASK
;
2584 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
2585 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2586 srrctl
|= IXGBE_MAX_RXBUFFER
>> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2588 srrctl
|= (PAGE_SIZE
/ 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2590 srrctl
|= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS
;
2592 srrctl
|= ALIGN(rx_ring
->rx_buf_len
, 1024) >>
2593 IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2594 srrctl
|= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF
;
2597 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_SRRCTL(index
), srrctl
);
2600 static void ixgbe_setup_mrqc(struct ixgbe_adapter
*adapter
)
2602 struct ixgbe_hw
*hw
= &adapter
->hw
;
2603 static const u32 seed
[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2604 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2605 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2606 u32 mrqc
= 0, reta
= 0;
2611 /* Fill out hash function seeds */
2612 for (i
= 0; i
< 10; i
++)
2613 IXGBE_WRITE_REG(hw
, IXGBE_RSSRK(i
), seed
[i
]);
2615 /* Fill out redirection table */
2616 for (i
= 0, j
= 0; i
< 128; i
++, j
++) {
2617 if (j
== adapter
->ring_feature
[RING_F_RSS
].indices
)
2619 /* reta = 4-byte sliding window of
2620 * 0x00..(indices-1)(indices-1)00..etc. */
2621 reta
= (reta
<< 8) | (j
* 0x11);
2623 IXGBE_WRITE_REG(hw
, IXGBE_RETA(i
>> 2), reta
);
2626 /* Disable indicating checksum in descriptor, enables RSS hash */
2627 rxcsum
= IXGBE_READ_REG(hw
, IXGBE_RXCSUM
);
2628 rxcsum
|= IXGBE_RXCSUM_PCSD
;
2629 IXGBE_WRITE_REG(hw
, IXGBE_RXCSUM
, rxcsum
);
2631 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
2632 mask
= adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
;
2634 mask
= adapter
->flags
& (IXGBE_FLAG_RSS_ENABLED
2635 #ifdef CONFIG_IXGBE_DCB
2636 | IXGBE_FLAG_DCB_ENABLED
2638 | IXGBE_FLAG_SRIOV_ENABLED
2642 case (IXGBE_FLAG_RSS_ENABLED
):
2643 mrqc
= IXGBE_MRQC_RSSEN
;
2645 case (IXGBE_FLAG_SRIOV_ENABLED
):
2646 mrqc
= IXGBE_MRQC_VMDQEN
;
2648 #ifdef CONFIG_IXGBE_DCB
2649 case (IXGBE_FLAG_DCB_ENABLED
):
2650 mrqc
= IXGBE_MRQC_RT8TCEN
;
2652 #endif /* CONFIG_IXGBE_DCB */
2657 /* Perform hash on these packet types */
2658 mrqc
|= IXGBE_MRQC_RSS_FIELD_IPV4
2659 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2660 | IXGBE_MRQC_RSS_FIELD_IPV6
2661 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
;
2663 IXGBE_WRITE_REG(hw
, IXGBE_MRQC
, mrqc
);
2667 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2668 * @adapter: address of board private structure
2669 * @index: index of ring to set
2671 static void ixgbe_configure_rscctl(struct ixgbe_adapter
*adapter
,
2672 struct ixgbe_ring
*ring
)
2674 struct ixgbe_hw
*hw
= &adapter
->hw
;
2677 u16 reg_idx
= ring
->reg_idx
;
2679 if (!(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
))
2682 rx_buf_len
= ring
->rx_buf_len
;
2683 rscctrl
= IXGBE_READ_REG(hw
, IXGBE_RSCCTL(reg_idx
));
2684 rscctrl
|= IXGBE_RSCCTL_RSCEN
;
2686 * we must limit the number of descriptors so that the
2687 * total size of max desc * buf_len is not greater
2690 if (ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
2691 #if (MAX_SKB_FRAGS > 16)
2692 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2693 #elif (MAX_SKB_FRAGS > 8)
2694 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2695 #elif (MAX_SKB_FRAGS > 4)
2696 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2698 rscctrl
|= IXGBE_RSCCTL_MAXDESC_1
;
2701 if (rx_buf_len
< IXGBE_RXBUFFER_4096
)
2702 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2703 else if (rx_buf_len
< IXGBE_RXBUFFER_8192
)
2704 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2706 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2708 IXGBE_WRITE_REG(hw
, IXGBE_RSCCTL(reg_idx
), rscctrl
);
2712 * ixgbe_set_uta - Set unicast filter table address
2713 * @adapter: board private structure
2715 * The unicast table address is a register array of 32-bit registers.
2716 * The table is meant to be used in a way similar to how the MTA is used
2717 * however due to certain limitations in the hardware it is necessary to
2718 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2719 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2721 static void ixgbe_set_uta(struct ixgbe_adapter
*adapter
)
2723 struct ixgbe_hw
*hw
= &adapter
->hw
;
2726 /* The UTA table only exists on 82599 hardware and newer */
2727 if (hw
->mac
.type
< ixgbe_mac_82599EB
)
2730 /* we only need to do this if VMDq is enabled */
2731 if (!(adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
))
2734 for (i
= 0; i
< 128; i
++)
2735 IXGBE_WRITE_REG(hw
, IXGBE_UTA(i
), ~0);
2738 #define IXGBE_MAX_RX_DESC_POLL 10
2739 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter
*adapter
,
2740 struct ixgbe_ring
*ring
)
2742 struct ixgbe_hw
*hw
= &adapter
->hw
;
2743 int reg_idx
= ring
->reg_idx
;
2744 int wait_loop
= IXGBE_MAX_RX_DESC_POLL
;
2747 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2748 if (hw
->mac
.type
== ixgbe_mac_82598EB
&&
2749 !(IXGBE_READ_REG(hw
, IXGBE_LINKS
) & IXGBE_LINKS_UP
))
2754 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
2755 } while (--wait_loop
&& !(rxdctl
& IXGBE_RXDCTL_ENABLE
));
2758 e_err(drv
, "RXDCTL.ENABLE on Rx queue %d not set within "
2759 "the polling period\n", reg_idx
);
2763 void ixgbe_configure_rx_ring(struct ixgbe_adapter
*adapter
,
2764 struct ixgbe_ring
*ring
)
2766 struct ixgbe_hw
*hw
= &adapter
->hw
;
2767 u64 rdba
= ring
->dma
;
2769 u16 reg_idx
= ring
->reg_idx
;
2771 /* disable queue to avoid issues while updating state */
2772 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
2773 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(reg_idx
),
2774 rxdctl
& ~IXGBE_RXDCTL_ENABLE
);
2775 IXGBE_WRITE_FLUSH(hw
);
2777 IXGBE_WRITE_REG(hw
, IXGBE_RDBAL(reg_idx
), (rdba
& DMA_BIT_MASK(32)));
2778 IXGBE_WRITE_REG(hw
, IXGBE_RDBAH(reg_idx
), (rdba
>> 32));
2779 IXGBE_WRITE_REG(hw
, IXGBE_RDLEN(reg_idx
),
2780 ring
->count
* sizeof(union ixgbe_adv_rx_desc
));
2781 IXGBE_WRITE_REG(hw
, IXGBE_RDH(reg_idx
), 0);
2782 IXGBE_WRITE_REG(hw
, IXGBE_RDT(reg_idx
), 0);
2783 ring
->head
= IXGBE_RDH(reg_idx
);
2784 ring
->tail
= IXGBE_RDT(reg_idx
);
2786 ixgbe_configure_srrctl(adapter
, ring
);
2787 ixgbe_configure_rscctl(adapter
, ring
);
2789 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
2791 * enable cache line friendly hardware writes:
2792 * PTHRESH=32 descriptors (half the internal cache),
2793 * this also removes ugly rx_no_buffer_count increment
2794 * HTHRESH=4 descriptors (to minimize latency on fetch)
2795 * WTHRESH=8 burst writeback up to two cache lines
2797 rxdctl
&= ~0x3FFFFF;
2801 /* enable receive descriptor ring */
2802 rxdctl
|= IXGBE_RXDCTL_ENABLE
;
2803 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(reg_idx
), rxdctl
);
2805 ixgbe_rx_desc_queue_enable(adapter
, ring
);
2806 ixgbe_alloc_rx_buffers(adapter
, ring
, IXGBE_DESC_UNUSED(ring
));
2809 static void ixgbe_setup_psrtype(struct ixgbe_adapter
*adapter
)
2811 struct ixgbe_hw
*hw
= &adapter
->hw
;
2814 /* PSRTYPE must be initialized in non 82598 adapters */
2815 u32 psrtype
= IXGBE_PSRTYPE_TCPHDR
|
2816 IXGBE_PSRTYPE_UDPHDR
|
2817 IXGBE_PSRTYPE_IPV4HDR
|
2818 IXGBE_PSRTYPE_L2HDR
|
2819 IXGBE_PSRTYPE_IPV6HDR
;
2821 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2824 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
)
2825 psrtype
|= (adapter
->num_rx_queues_per_pool
<< 29);
2827 for (p
= 0; p
< adapter
->num_rx_pools
; p
++)
2828 IXGBE_WRITE_REG(hw
, IXGBE_PSRTYPE(adapter
->num_vfs
+ p
),
2832 static void ixgbe_configure_virtualization(struct ixgbe_adapter
*adapter
)
2834 struct ixgbe_hw
*hw
= &adapter
->hw
;
2837 u32 reg_offset
, vf_shift
;
2840 if (!(adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
))
2843 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
2844 vt_reg_bits
= IXGBE_VMD_CTL_VMDQ_EN
| IXGBE_VT_CTL_REPLEN
;
2845 vt_reg_bits
|= (adapter
->num_vfs
<< IXGBE_VT_CTL_POOL_SHIFT
);
2846 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
| vt_reg_bits
);
2848 vf_shift
= adapter
->num_vfs
% 32;
2849 reg_offset
= (adapter
->num_vfs
> 32) ? 1 : 0;
2851 /* Enable only the PF's pool for Tx/Rx */
2852 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(reg_offset
), (1 << vf_shift
));
2853 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(reg_offset
^ 1), 0);
2854 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(reg_offset
), (1 << vf_shift
));
2855 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(reg_offset
^ 1), 0);
2856 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, IXGBE_PFDTXGSWC_VT_LBEN
);
2858 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2859 hw
->mac
.ops
.set_vmdq(hw
, 0, adapter
->num_vfs
);
2862 * Set up VF register offsets for selected VT Mode,
2863 * i.e. 32 or 64 VFs for SR-IOV
2865 gcr_ext
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
2866 gcr_ext
|= IXGBE_GCR_EXT_MSIX_EN
;
2867 gcr_ext
|= IXGBE_GCR_EXT_VT_MODE_64
;
2868 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, gcr_ext
);
2870 /* enable Tx loopback for VF/PF communication */
2871 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, IXGBE_PFDTXGSWC_VT_LBEN
);
2874 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter
*adapter
)
2876 struct ixgbe_hw
*hw
= &adapter
->hw
;
2877 struct net_device
*netdev
= adapter
->netdev
;
2878 int max_frame
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
2880 struct ixgbe_ring
*rx_ring
;
2884 /* Decide whether to use packet split mode or not */
2885 /* Do not use packet split if we're in SR-IOV Mode */
2886 if (!adapter
->num_vfs
)
2887 adapter
->flags
|= IXGBE_FLAG_RX_PS_ENABLED
;
2889 /* Set the RX buffer length according to the mode */
2890 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
) {
2891 rx_buf_len
= IXGBE_RX_HDR_SIZE
;
2893 if (!(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) &&
2894 (netdev
->mtu
<= ETH_DATA_LEN
))
2895 rx_buf_len
= MAXIMUM_ETHERNET_VLAN_SIZE
;
2897 rx_buf_len
= ALIGN(max_frame
+ VLAN_HLEN
, 1024);
2901 /* adjust max frame to be able to do baby jumbo for FCoE */
2902 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) &&
2903 (max_frame
< IXGBE_FCOE_JUMBO_FRAME_SIZE
))
2904 max_frame
= IXGBE_FCOE_JUMBO_FRAME_SIZE
;
2906 #endif /* IXGBE_FCOE */
2907 mhadd
= IXGBE_READ_REG(hw
, IXGBE_MHADD
);
2908 if (max_frame
!= (mhadd
>> IXGBE_MHADD_MFS_SHIFT
)) {
2909 mhadd
&= ~IXGBE_MHADD_MFS_MASK
;
2910 mhadd
|= max_frame
<< IXGBE_MHADD_MFS_SHIFT
;
2912 IXGBE_WRITE_REG(hw
, IXGBE_MHADD
, mhadd
);
2915 hlreg0
= IXGBE_READ_REG(hw
, IXGBE_HLREG0
);
2916 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2917 hlreg0
|= IXGBE_HLREG0_JUMBOEN
;
2918 IXGBE_WRITE_REG(hw
, IXGBE_HLREG0
, hlreg0
);
2921 * Setup the HW Rx Head and Tail Descriptor Pointers and
2922 * the Base and Length of the Rx Descriptor Ring
2924 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2925 rx_ring
= adapter
->rx_ring
[i
];
2926 rx_ring
->rx_buf_len
= rx_buf_len
;
2928 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
)
2929 rx_ring
->flags
|= IXGBE_RING_RX_PS_ENABLED
;
2931 rx_ring
->flags
&= ~IXGBE_RING_RX_PS_ENABLED
;
2934 if (netdev
->features
& NETIF_F_FCOE_MTU
)
2936 struct ixgbe_ring_feature
*f
;
2937 f
= &adapter
->ring_feature
[RING_F_FCOE
];
2938 if ((i
>= f
->mask
) && (i
< f
->mask
+ f
->indices
)) {
2939 rx_ring
->flags
&= ~IXGBE_RING_RX_PS_ENABLED
;
2940 if (rx_buf_len
< IXGBE_FCOE_JUMBO_FRAME_SIZE
)
2941 rx_ring
->rx_buf_len
=
2942 IXGBE_FCOE_JUMBO_FRAME_SIZE
;
2945 #endif /* IXGBE_FCOE */
2950 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter
*adapter
)
2952 struct ixgbe_hw
*hw
= &adapter
->hw
;
2953 u32 rdrxctl
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
2955 switch (hw
->mac
.type
) {
2956 case ixgbe_mac_82598EB
:
2958 * For VMDq support of different descriptor types or
2959 * buffer sizes through the use of multiple SRRCTL
2960 * registers, RDRXCTL.MVMEN must be set to 1
2962 * also, the manual doesn't mention it clearly but DCA hints
2963 * will only use queue 0's tags unless this bit is set. Side
2964 * effects of setting this bit are only that SRRCTL must be
2965 * fully programmed [0..15]
2967 rdrxctl
|= IXGBE_RDRXCTL_MVMEN
;
2969 case ixgbe_mac_82599EB
:
2970 /* Disable RSC for ACK packets */
2971 IXGBE_WRITE_REG(hw
, IXGBE_RSCDBU
,
2972 (IXGBE_RSCDBU_RSCACKDIS
| IXGBE_READ_REG(hw
, IXGBE_RSCDBU
)));
2973 rdrxctl
&= ~IXGBE_RDRXCTL_RSCFRSTSIZE
;
2974 /* hardware requires some bits to be set by default */
2975 rdrxctl
|= (IXGBE_RDRXCTL_RSCACKC
| IXGBE_RDRXCTL_FCOE_WRFIX
);
2976 rdrxctl
|= IXGBE_RDRXCTL_CRCSTRIP
;
2979 /* We should do nothing since we don't know this hardware */
2983 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, rdrxctl
);
2987 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2988 * @adapter: board private structure
2990 * Configure the Rx unit of the MAC after a reset.
2992 static void ixgbe_configure_rx(struct ixgbe_adapter
*adapter
)
2994 struct ixgbe_hw
*hw
= &adapter
->hw
;
2998 /* disable receives while setting up the descriptors */
2999 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
3000 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
3002 ixgbe_setup_psrtype(adapter
);
3003 ixgbe_setup_rdrxctl(adapter
);
3005 /* Program registers for the distribution of queues */
3006 ixgbe_setup_mrqc(adapter
);
3007 ixgbe_configure_virtualization(adapter
);
3009 ixgbe_set_uta(adapter
);
3011 /* set_rx_buffer_len must be called before ring initialization */
3012 ixgbe_set_rx_buffer_len(adapter
);
3015 * Setup the HW Rx Head and Tail Descriptor Pointers and
3016 * the Base and Length of the Rx Descriptor Ring
3018 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3019 ixgbe_configure_rx_ring(adapter
, adapter
->rx_ring
[i
]);
3021 /* disable drop enable for 82598 parts */
3022 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3023 rxctrl
|= IXGBE_RXCTRL_DMBYPS
;
3025 /* enable all receives */
3026 rxctrl
|= IXGBE_RXCTRL_RXEN
;
3027 hw
->mac
.ops
.enable_rx_dma(hw
, rxctrl
);
3030 static void ixgbe_vlan_rx_add_vid(struct net_device
*netdev
, u16 vid
)
3032 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3033 struct ixgbe_hw
*hw
= &adapter
->hw
;
3034 int pool_ndx
= adapter
->num_vfs
;
3036 /* add VID to filter table */
3037 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, true);
3040 static void ixgbe_vlan_rx_kill_vid(struct net_device
*netdev
, u16 vid
)
3042 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3043 struct ixgbe_hw
*hw
= &adapter
->hw
;
3044 int pool_ndx
= adapter
->num_vfs
;
3046 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
3047 ixgbe_irq_disable(adapter
);
3049 vlan_group_set_device(adapter
->vlgrp
, vid
, NULL
);
3051 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
3052 ixgbe_irq_enable(adapter
);
3054 /* remove VID from filter table */
3055 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, false);
3059 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3060 * @adapter: driver data
3062 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter
*adapter
)
3064 struct ixgbe_hw
*hw
= &adapter
->hw
;
3065 u32 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3068 switch (hw
->mac
.type
) {
3069 case ixgbe_mac_82598EB
:
3070 vlnctrl
&= ~IXGBE_VLNCTRL_VFE
;
3071 #ifdef CONFIG_IXGBE_DCB
3072 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
))
3073 vlnctrl
&= ~IXGBE_VLNCTRL_VME
;
3075 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
3076 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3078 case ixgbe_mac_82599EB
:
3079 vlnctrl
&= ~IXGBE_VLNCTRL_VFE
;
3080 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
3081 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3082 #ifdef CONFIG_IXGBE_DCB
3083 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)
3086 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3087 j
= adapter
->rx_ring
[i
]->reg_idx
;
3088 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
3089 vlnctrl
&= ~IXGBE_RXDCTL_VME
;
3090 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
3099 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3100 * @adapter: driver data
3102 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter
*adapter
)
3104 struct ixgbe_hw
*hw
= &adapter
->hw
;
3105 u32 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3108 switch (hw
->mac
.type
) {
3109 case ixgbe_mac_82598EB
:
3110 vlnctrl
|= IXGBE_VLNCTRL_VME
| IXGBE_VLNCTRL_VFE
;
3111 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
3112 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3114 case ixgbe_mac_82599EB
:
3115 vlnctrl
|= IXGBE_VLNCTRL_VFE
;
3116 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
3117 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3118 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3119 j
= adapter
->rx_ring
[i
]->reg_idx
;
3120 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
3121 vlnctrl
|= IXGBE_RXDCTL_VME
;
3122 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
3130 static void ixgbe_vlan_rx_register(struct net_device
*netdev
,
3131 struct vlan_group
*grp
)
3133 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3135 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
3136 ixgbe_irq_disable(adapter
);
3137 adapter
->vlgrp
= grp
;
3140 * For a DCB driver, always enable VLAN tag stripping so we can
3141 * still receive traffic from a DCB-enabled host even if we're
3144 ixgbe_vlan_filter_enable(adapter
);
3146 ixgbe_vlan_rx_add_vid(netdev
, 0);
3148 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
3149 ixgbe_irq_enable(adapter
);
3152 static void ixgbe_restore_vlan(struct ixgbe_adapter
*adapter
)
3154 ixgbe_vlan_rx_register(adapter
->netdev
, adapter
->vlgrp
);
3156 if (adapter
->vlgrp
) {
3158 for (vid
= 0; vid
< VLAN_GROUP_ARRAY_LEN
; vid
++) {
3159 if (!vlan_group_get_device(adapter
->vlgrp
, vid
))
3161 ixgbe_vlan_rx_add_vid(adapter
->netdev
, vid
);
3167 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3168 * @netdev: network interface device structure
3170 * Writes unicast address list to the RAR table.
3171 * Returns: -ENOMEM on failure/insufficient address space
3172 * 0 on no addresses written
3173 * X on writing X addresses to the RAR table
3175 static int ixgbe_write_uc_addr_list(struct net_device
*netdev
)
3177 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3178 struct ixgbe_hw
*hw
= &adapter
->hw
;
3179 unsigned int vfn
= adapter
->num_vfs
;
3180 unsigned int rar_entries
= hw
->mac
.num_rar_entries
- (vfn
+ 1);
3183 /* return ENOMEM indicating insufficient memory for addresses */
3184 if (netdev_uc_count(netdev
) > rar_entries
)
3187 if (!netdev_uc_empty(netdev
) && rar_entries
) {
3188 struct netdev_hw_addr
*ha
;
3189 /* return error if we do not support writing to RAR table */
3190 if (!hw
->mac
.ops
.set_rar
)
3193 netdev_for_each_uc_addr(ha
, netdev
) {
3196 hw
->mac
.ops
.set_rar(hw
, rar_entries
--, ha
->addr
,
3201 /* write the addresses in reverse order to avoid write combining */
3202 for (; rar_entries
> 0 ; rar_entries
--)
3203 hw
->mac
.ops
.clear_rar(hw
, rar_entries
);
3209 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3210 * @netdev: network interface device structure
3212 * The set_rx_method entry point is called whenever the unicast/multicast
3213 * address list or the network interface flags are updated. This routine is
3214 * responsible for configuring the hardware for proper unicast, multicast and
3217 void ixgbe_set_rx_mode(struct net_device
*netdev
)
3219 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3220 struct ixgbe_hw
*hw
= &adapter
->hw
;
3221 u32 fctrl
, vmolr
= IXGBE_VMOLR_BAM
| IXGBE_VMOLR_AUPE
;
3224 /* Check for Promiscuous and All Multicast modes */
3226 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
3228 /* set all bits that we expect to always be set */
3229 fctrl
|= IXGBE_FCTRL_BAM
;
3230 fctrl
|= IXGBE_FCTRL_DPF
; /* discard pause frames when FC enabled */
3231 fctrl
|= IXGBE_FCTRL_PMCF
;
3233 /* clear the bits we are changing the status of */
3234 fctrl
&= ~(IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
3236 if (netdev
->flags
& IFF_PROMISC
) {
3237 hw
->addr_ctrl
.user_set_promisc
= true;
3238 fctrl
|= (IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
3239 vmolr
|= (IXGBE_VMOLR_ROPE
| IXGBE_VMOLR_MPE
);
3240 /* don't hardware filter vlans in promisc mode */
3241 ixgbe_vlan_filter_disable(adapter
);
3243 if (netdev
->flags
& IFF_ALLMULTI
) {
3244 fctrl
|= IXGBE_FCTRL_MPE
;
3245 vmolr
|= IXGBE_VMOLR_MPE
;
3248 * Write addresses to the MTA, if the attempt fails
3249 * then we should just turn on promiscous mode so
3250 * that we can at least receive multicast traffic
3252 hw
->mac
.ops
.update_mc_addr_list(hw
, netdev
);
3253 vmolr
|= IXGBE_VMOLR_ROMPE
;
3255 ixgbe_vlan_filter_enable(adapter
);
3256 hw
->addr_ctrl
.user_set_promisc
= false;
3258 * Write addresses to available RAR registers, if there is not
3259 * sufficient space to store all the addresses then enable
3260 * unicast promiscous mode
3262 count
= ixgbe_write_uc_addr_list(netdev
);
3264 fctrl
|= IXGBE_FCTRL_UPE
;
3265 vmolr
|= IXGBE_VMOLR_ROPE
;
3269 if (adapter
->num_vfs
) {
3270 ixgbe_restore_vf_multicasts(adapter
);
3271 vmolr
|= IXGBE_READ_REG(hw
, IXGBE_VMOLR(adapter
->num_vfs
)) &
3272 ~(IXGBE_VMOLR_MPE
| IXGBE_VMOLR_ROMPE
|
3274 IXGBE_WRITE_REG(hw
, IXGBE_VMOLR(adapter
->num_vfs
), vmolr
);
3277 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
3280 static void ixgbe_napi_enable_all(struct ixgbe_adapter
*adapter
)
3283 struct ixgbe_q_vector
*q_vector
;
3284 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3286 /* legacy and MSI only use one vector */
3287 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
3290 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
3291 struct napi_struct
*napi
;
3292 q_vector
= adapter
->q_vector
[q_idx
];
3293 napi
= &q_vector
->napi
;
3294 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3295 if (!q_vector
->rxr_count
|| !q_vector
->txr_count
) {
3296 if (q_vector
->txr_count
== 1)
3297 napi
->poll
= &ixgbe_clean_txonly
;
3298 else if (q_vector
->rxr_count
== 1)
3299 napi
->poll
= &ixgbe_clean_rxonly
;
3307 static void ixgbe_napi_disable_all(struct ixgbe_adapter
*adapter
)
3310 struct ixgbe_q_vector
*q_vector
;
3311 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3313 /* legacy and MSI only use one vector */
3314 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
3317 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
3318 q_vector
= adapter
->q_vector
[q_idx
];
3319 napi_disable(&q_vector
->napi
);
3323 #ifdef CONFIG_IXGBE_DCB
3325 * ixgbe_configure_dcb - Configure DCB hardware
3326 * @adapter: ixgbe adapter struct
3328 * This is called by the driver on open to configure the DCB hardware.
3329 * This is also called by the gennetlink interface when reconfiguring
3332 static void ixgbe_configure_dcb(struct ixgbe_adapter
*adapter
)
3334 struct ixgbe_hw
*hw
= &adapter
->hw
;
3338 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)) {
3339 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3340 netif_set_gso_max_size(adapter
->netdev
, 65536);
3344 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3345 netif_set_gso_max_size(adapter
->netdev
, 32768);
3347 ixgbe_dcb_check_config(&adapter
->dcb_cfg
);
3348 ixgbe_dcb_calculate_tc_credits(&adapter
->dcb_cfg
, DCB_TX_CONFIG
);
3349 ixgbe_dcb_calculate_tc_credits(&adapter
->dcb_cfg
, DCB_RX_CONFIG
);
3351 /* reconfigure the hardware */
3352 ixgbe_dcb_hw_config(&adapter
->hw
, &adapter
->dcb_cfg
);
3354 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
3355 j
= adapter
->tx_ring
[i
]->reg_idx
;
3356 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
3357 /* PThresh workaround for Tx hang with DFP enabled. */
3359 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
), txdctl
);
3361 /* Enable VLAN tag insert/strip */
3362 ixgbe_vlan_filter_enable(adapter
);
3364 hw
->mac
.ops
.set_vfta(&adapter
->hw
, 0, 0, true);
3368 static void ixgbe_configure(struct ixgbe_adapter
*adapter
)
3370 struct net_device
*netdev
= adapter
->netdev
;
3371 struct ixgbe_hw
*hw
= &adapter
->hw
;
3374 ixgbe_set_rx_mode(netdev
);
3376 ixgbe_restore_vlan(adapter
);
3377 #ifdef CONFIG_IXGBE_DCB
3378 ixgbe_configure_dcb(adapter
);
3382 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
3383 ixgbe_configure_fcoe(adapter
);
3385 #endif /* IXGBE_FCOE */
3386 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
3387 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3388 adapter
->tx_ring
[i
]->atr_sample_rate
=
3389 adapter
->atr_sample_rate
;
3390 ixgbe_init_fdir_signature_82599(hw
, adapter
->fdir_pballoc
);
3391 } else if (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
) {
3392 ixgbe_init_fdir_perfect_82599(hw
, adapter
->fdir_pballoc
);
3395 ixgbe_configure_tx(adapter
);
3396 ixgbe_configure_rx(adapter
);
3399 static inline bool ixgbe_is_sfp(struct ixgbe_hw
*hw
)
3401 switch (hw
->phy
.type
) {
3402 case ixgbe_phy_sfp_avago
:
3403 case ixgbe_phy_sfp_ftl
:
3404 case ixgbe_phy_sfp_intel
:
3405 case ixgbe_phy_sfp_unknown
:
3406 case ixgbe_phy_sfp_passive_tyco
:
3407 case ixgbe_phy_sfp_passive_unknown
:
3408 case ixgbe_phy_sfp_active_unknown
:
3409 case ixgbe_phy_sfp_ftl_active
:
3417 * ixgbe_sfp_link_config - set up SFP+ link
3418 * @adapter: pointer to private adapter struct
3420 static void ixgbe_sfp_link_config(struct ixgbe_adapter
*adapter
)
3422 struct ixgbe_hw
*hw
= &adapter
->hw
;
3424 if (hw
->phy
.multispeed_fiber
) {
3426 * In multispeed fiber setups, the device may not have
3427 * had a physical connection when the driver loaded.
3428 * If that's the case, the initial link configuration
3429 * couldn't get the MAC into 10G or 1G mode, so we'll
3430 * never have a link status change interrupt fire.
3431 * We need to try and force an autonegotiation
3432 * session, then bring up link.
3434 hw
->mac
.ops
.setup_sfp(hw
);
3435 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_LINK_TASK
))
3436 schedule_work(&adapter
->multispeed_fiber_task
);
3439 * Direct Attach Cu and non-multispeed fiber modules
3440 * still need to be configured properly prior to
3443 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_MOD_TASK
))
3444 schedule_work(&adapter
->sfp_config_module_task
);
3449 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3450 * @hw: pointer to private hardware struct
3452 * Returns 0 on success, negative on failure
3454 static int ixgbe_non_sfp_link_config(struct ixgbe_hw
*hw
)
3457 bool negotiation
, link_up
= false;
3458 u32 ret
= IXGBE_ERR_LINK_SETUP
;
3460 if (hw
->mac
.ops
.check_link
)
3461 ret
= hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
3466 if (hw
->mac
.ops
.get_link_capabilities
)
3467 ret
= hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
, &negotiation
);
3471 if (hw
->mac
.ops
.setup_link
)
3472 ret
= hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, link_up
);
3477 static void ixgbe_setup_gpie(struct ixgbe_adapter
*adapter
)
3479 struct ixgbe_hw
*hw
= &adapter
->hw
;
3482 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3483 gpie
= IXGBE_GPIE_MSIX_MODE
| IXGBE_GPIE_PBA_SUPPORT
|
3485 gpie
|= IXGBE_GPIE_EIAME
;
3487 * use EIAM to auto-mask when MSI-X interrupt is asserted
3488 * this saves a register write for every interrupt
3490 switch (hw
->mac
.type
) {
3491 case ixgbe_mac_82598EB
:
3492 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
3495 case ixgbe_mac_82599EB
:
3496 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3497 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3501 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3502 * specifically only auto mask tx and rx interrupts */
3503 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
3506 /* XXX: to interrupt immediately for EICS writes, enable this */
3507 /* gpie |= IXGBE_GPIE_EIMEN; */
3509 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
3510 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
3511 gpie
|= IXGBE_GPIE_VTMODE_64
;
3514 /* Enable fan failure interrupt */
3515 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
)
3516 gpie
|= IXGBE_SDP1_GPIEN
;
3518 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
3519 gpie
|= IXGBE_SDP1_GPIEN
;
3520 gpie
|= IXGBE_SDP2_GPIEN
;
3522 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
3525 static int ixgbe_up_complete(struct ixgbe_adapter
*adapter
)
3527 struct ixgbe_hw
*hw
= &adapter
->hw
;
3531 ixgbe_get_hw_control(adapter
);
3532 ixgbe_setup_gpie(adapter
);
3534 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
3535 ixgbe_configure_msix(adapter
);
3537 ixgbe_configure_msi_and_legacy(adapter
);
3539 /* enable the optics */
3540 if (hw
->phy
.multispeed_fiber
)
3541 hw
->mac
.ops
.enable_tx_laser(hw
);
3543 clear_bit(__IXGBE_DOWN
, &adapter
->state
);
3544 ixgbe_napi_enable_all(adapter
);
3546 /* clear any pending interrupts, may auto mask */
3547 IXGBE_READ_REG(hw
, IXGBE_EICR
);
3548 ixgbe_irq_enable(adapter
);
3551 * If this adapter has a fan, check to see if we had a failure
3552 * before we enabled the interrupt.
3554 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
3555 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
3556 if (esdp
& IXGBE_ESDP_SDP1
)
3557 e_crit(drv
, "Fan has stopped, replace the adapter\n");
3561 * For hot-pluggable SFP+ devices, a new SFP+ module may have
3562 * arrived before interrupts were enabled but after probe. Such
3563 * devices wouldn't have their type identified yet. We need to
3564 * kick off the SFP+ module setup first, then try to bring up link.
3565 * If we're not hot-pluggable SFP+, we just need to configure link
3568 if (hw
->phy
.type
== ixgbe_phy_unknown
) {
3569 err
= hw
->phy
.ops
.identify(hw
);
3570 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
3572 * Take the device down and schedule the sfp tasklet
3573 * which will unregister_netdev and log it.
3575 ixgbe_down(adapter
);
3576 schedule_work(&adapter
->sfp_config_module_task
);
3581 if (ixgbe_is_sfp(hw
)) {
3582 ixgbe_sfp_link_config(adapter
);
3584 err
= ixgbe_non_sfp_link_config(hw
);
3586 e_err(probe
, "link_config FAILED %d\n", err
);
3589 /* enable transmits */
3590 netif_tx_start_all_queues(adapter
->netdev
);
3592 /* bring the link up in the watchdog, this could race with our first
3593 * link up interrupt but shouldn't be a problem */
3594 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
3595 adapter
->link_check_timeout
= jiffies
;
3596 mod_timer(&adapter
->watchdog_timer
, jiffies
);
3598 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3599 ctrl_ext
= IXGBE_READ_REG(hw
, IXGBE_CTRL_EXT
);
3600 ctrl_ext
|= IXGBE_CTRL_EXT_PFRSTD
;
3601 IXGBE_WRITE_REG(hw
, IXGBE_CTRL_EXT
, ctrl_ext
);
3606 void ixgbe_reinit_locked(struct ixgbe_adapter
*adapter
)
3608 WARN_ON(in_interrupt());
3609 while (test_and_set_bit(__IXGBE_RESETTING
, &adapter
->state
))
3611 ixgbe_down(adapter
);
3613 * If SR-IOV enabled then wait a bit before bringing the adapter
3614 * back up to give the VFs time to respond to the reset. The
3615 * two second wait is based upon the watchdog timer cycle in
3618 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
3621 clear_bit(__IXGBE_RESETTING
, &adapter
->state
);
3624 int ixgbe_up(struct ixgbe_adapter
*adapter
)
3626 /* hardware has been reset, we need to reload some things */
3627 ixgbe_configure(adapter
);
3629 return ixgbe_up_complete(adapter
);
3632 void ixgbe_reset(struct ixgbe_adapter
*adapter
)
3634 struct ixgbe_hw
*hw
= &adapter
->hw
;
3637 err
= hw
->mac
.ops
.init_hw(hw
);
3640 case IXGBE_ERR_SFP_NOT_PRESENT
:
3642 case IXGBE_ERR_MASTER_REQUESTS_PENDING
:
3643 e_dev_err("master disable timed out\n");
3645 case IXGBE_ERR_EEPROM_VERSION
:
3646 /* We are running on a pre-production device, log a warning */
3647 e_dev_warn("This device is a pre-production adapter/LOM. "
3648 "Please be aware there may be issuesassociated with "
3649 "your hardware. If you are experiencing problems "
3650 "please contact your Intel or hardware "
3651 "representative who provided you with this "
3655 e_dev_err("Hardware Error: %d\n", err
);
3658 /* reprogram the RAR[0] in case user changed it. */
3659 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
3664 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3665 * @adapter: board private structure
3666 * @rx_ring: ring to free buffers from
3668 static void ixgbe_clean_rx_ring(struct ixgbe_adapter
*adapter
,
3669 struct ixgbe_ring
*rx_ring
)
3671 struct pci_dev
*pdev
= adapter
->pdev
;
3675 /* ring already cleared, nothing to do */
3676 if (!rx_ring
->rx_buffer_info
)
3679 /* Free all the Rx ring sk_buffs */
3680 for (i
= 0; i
< rx_ring
->count
; i
++) {
3681 struct ixgbe_rx_buffer
*rx_buffer_info
;
3683 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
3684 if (rx_buffer_info
->dma
) {
3685 dma_unmap_single(&pdev
->dev
, rx_buffer_info
->dma
,
3686 rx_ring
->rx_buf_len
,
3688 rx_buffer_info
->dma
= 0;
3690 if (rx_buffer_info
->skb
) {
3691 struct sk_buff
*skb
= rx_buffer_info
->skb
;
3692 rx_buffer_info
->skb
= NULL
;
3694 struct sk_buff
*this = skb
;
3695 if (IXGBE_RSC_CB(this)->delay_unmap
) {
3696 dma_unmap_single(&pdev
->dev
,
3697 IXGBE_RSC_CB(this)->dma
,
3698 rx_ring
->rx_buf_len
,
3700 IXGBE_RSC_CB(this)->dma
= 0;
3701 IXGBE_RSC_CB(skb
)->delay_unmap
= false;
3704 dev_kfree_skb(this);
3707 if (!rx_buffer_info
->page
)
3709 if (rx_buffer_info
->page_dma
) {
3710 dma_unmap_page(&pdev
->dev
, rx_buffer_info
->page_dma
,
3711 PAGE_SIZE
/ 2, DMA_FROM_DEVICE
);
3712 rx_buffer_info
->page_dma
= 0;
3714 put_page(rx_buffer_info
->page
);
3715 rx_buffer_info
->page
= NULL
;
3716 rx_buffer_info
->page_offset
= 0;
3719 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
3720 memset(rx_ring
->rx_buffer_info
, 0, size
);
3722 /* Zero out the descriptor ring */
3723 memset(rx_ring
->desc
, 0, rx_ring
->size
);
3725 rx_ring
->next_to_clean
= 0;
3726 rx_ring
->next_to_use
= 0;
3729 writel(0, adapter
->hw
.hw_addr
+ rx_ring
->head
);
3731 writel(0, adapter
->hw
.hw_addr
+ rx_ring
->tail
);
3735 * ixgbe_clean_tx_ring - Free Tx Buffers
3736 * @adapter: board private structure
3737 * @tx_ring: ring to be cleaned
3739 static void ixgbe_clean_tx_ring(struct ixgbe_adapter
*adapter
,
3740 struct ixgbe_ring
*tx_ring
)
3742 struct ixgbe_tx_buffer
*tx_buffer_info
;
3746 /* ring already cleared, nothing to do */
3747 if (!tx_ring
->tx_buffer_info
)
3750 /* Free all the Tx ring sk_buffs */
3751 for (i
= 0; i
< tx_ring
->count
; i
++) {
3752 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
3753 ixgbe_unmap_and_free_tx_resource(adapter
, tx_buffer_info
);
3756 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
3757 memset(tx_ring
->tx_buffer_info
, 0, size
);
3759 /* Zero out the descriptor ring */
3760 memset(tx_ring
->desc
, 0, tx_ring
->size
);
3762 tx_ring
->next_to_use
= 0;
3763 tx_ring
->next_to_clean
= 0;
3766 writel(0, adapter
->hw
.hw_addr
+ tx_ring
->head
);
3768 writel(0, adapter
->hw
.hw_addr
+ tx_ring
->tail
);
3772 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3773 * @adapter: board private structure
3775 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter
*adapter
)
3779 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3780 ixgbe_clean_rx_ring(adapter
, adapter
->rx_ring
[i
]);
3784 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3785 * @adapter: board private structure
3787 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter
*adapter
)
3791 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3792 ixgbe_clean_tx_ring(adapter
, adapter
->tx_ring
[i
]);
3795 void ixgbe_down(struct ixgbe_adapter
*adapter
)
3797 struct net_device
*netdev
= adapter
->netdev
;
3798 struct ixgbe_hw
*hw
= &adapter
->hw
;
3803 /* signal that we are down to the interrupt handler */
3804 set_bit(__IXGBE_DOWN
, &adapter
->state
);
3806 /* disable receive for all VFs and wait one second */
3807 if (adapter
->num_vfs
) {
3808 /* ping all the active vfs to let them know we are going down */
3809 ixgbe_ping_all_vfs(adapter
);
3811 /* Disable all VFTE/VFRE TX/RX */
3812 ixgbe_disable_tx_rx(adapter
);
3814 /* Mark all the VFs as inactive */
3815 for (i
= 0 ; i
< adapter
->num_vfs
; i
++)
3816 adapter
->vfinfo
[i
].clear_to_send
= 0;
3819 /* disable receives */
3820 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
3821 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
3823 IXGBE_WRITE_FLUSH(hw
);
3826 netif_tx_stop_all_queues(netdev
);
3828 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
3829 del_timer_sync(&adapter
->sfp_timer
);
3830 del_timer_sync(&adapter
->watchdog_timer
);
3831 cancel_work_sync(&adapter
->watchdog_task
);
3833 netif_carrier_off(netdev
);
3834 netif_tx_disable(netdev
);
3836 ixgbe_irq_disable(adapter
);
3838 ixgbe_napi_disable_all(adapter
);
3840 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
3841 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
3842 cancel_work_sync(&adapter
->fdir_reinit_task
);
3844 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
)
3845 cancel_work_sync(&adapter
->check_overtemp_task
);
3847 /* disable transmits in the hardware now that interrupts are off */
3848 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
3849 j
= adapter
->tx_ring
[i
]->reg_idx
;
3850 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
3851 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
),
3852 (txdctl
& ~IXGBE_TXDCTL_ENABLE
));
3854 /* Disable the Tx DMA engine on 82599 */
3855 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
3856 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
,
3857 (IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
) &
3858 ~IXGBE_DMATXCTL_TE
));
3860 /* power down the optics */
3861 if (hw
->phy
.multispeed_fiber
)
3862 hw
->mac
.ops
.disable_tx_laser(hw
);
3864 /* clear n-tuple filters that are cached */
3865 ethtool_ntuple_flush(netdev
);
3867 if (!pci_channel_offline(adapter
->pdev
))
3868 ixgbe_reset(adapter
);
3869 ixgbe_clean_all_tx_rings(adapter
);
3870 ixgbe_clean_all_rx_rings(adapter
);
3872 #ifdef CONFIG_IXGBE_DCA
3873 /* since we reset the hardware DCA settings were cleared */
3874 ixgbe_setup_dca(adapter
);
3879 * ixgbe_poll - NAPI Rx polling callback
3880 * @napi: structure for representing this polling device
3881 * @budget: how many packets driver is allowed to clean
3883 * This function is used for legacy and MSI, NAPI mode
3885 static int ixgbe_poll(struct napi_struct
*napi
, int budget
)
3887 struct ixgbe_q_vector
*q_vector
=
3888 container_of(napi
, struct ixgbe_q_vector
, napi
);
3889 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
3890 int tx_clean_complete
, work_done
= 0;
3892 #ifdef CONFIG_IXGBE_DCA
3893 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
3894 ixgbe_update_tx_dca(adapter
, adapter
->tx_ring
[0]);
3895 ixgbe_update_rx_dca(adapter
, adapter
->rx_ring
[0]);
3899 tx_clean_complete
= ixgbe_clean_tx_irq(q_vector
, adapter
->tx_ring
[0]);
3900 ixgbe_clean_rx_irq(q_vector
, adapter
->rx_ring
[0], &work_done
, budget
);
3902 if (!tx_clean_complete
)
3905 /* If budget not fully consumed, exit the polling mode */
3906 if (work_done
< budget
) {
3907 napi_complete(napi
);
3908 if (adapter
->rx_itr_setting
& 1)
3909 ixgbe_set_itr(adapter
);
3910 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
3911 ixgbe_irq_enable_queues(adapter
, IXGBE_EIMS_RTX_QUEUE
);
3917 * ixgbe_tx_timeout - Respond to a Tx Hang
3918 * @netdev: network interface device structure
3920 static void ixgbe_tx_timeout(struct net_device
*netdev
)
3922 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3924 /* Do the reset outside of interrupt context */
3925 schedule_work(&adapter
->reset_task
);
3928 static void ixgbe_reset_task(struct work_struct
*work
)
3930 struct ixgbe_adapter
*adapter
;
3931 adapter
= container_of(work
, struct ixgbe_adapter
, reset_task
);
3933 /* If we're already down or resetting, just bail */
3934 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
3935 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
3938 adapter
->tx_timeout_count
++;
3940 ixgbe_dump(adapter
);
3941 netdev_err(adapter
->netdev
, "Reset adapter\n");
3942 ixgbe_reinit_locked(adapter
);
3945 #ifdef CONFIG_IXGBE_DCB
3946 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter
*adapter
)
3949 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_DCB
];
3951 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
))
3955 adapter
->num_rx_queues
= f
->indices
;
3956 adapter
->num_tx_queues
= f
->indices
;
3964 * ixgbe_set_rss_queues: Allocate queues for RSS
3965 * @adapter: board private structure to initialize
3967 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3968 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3971 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter
*adapter
)
3974 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_RSS
];
3976 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3978 adapter
->num_rx_queues
= f
->indices
;
3979 adapter
->num_tx_queues
= f
->indices
;
3989 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3990 * @adapter: board private structure to initialize
3992 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3993 * to the original CPU that initiated the Tx session. This runs in addition
3994 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3995 * Rx load across CPUs using RSS.
3998 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter
*adapter
)
4001 struct ixgbe_ring_feature
*f_fdir
= &adapter
->ring_feature
[RING_F_FDIR
];
4003 f_fdir
->indices
= min((int)num_online_cpus(), f_fdir
->indices
);
4006 /* Flow Director must have RSS enabled */
4007 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
&&
4008 ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
4009 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)))) {
4010 adapter
->num_tx_queues
= f_fdir
->indices
;
4011 adapter
->num_rx_queues
= f_fdir
->indices
;
4014 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4015 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
4022 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4023 * @adapter: board private structure to initialize
4025 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4026 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4027 * rx queues out of the max number of rx queues, instead, it is used as the
4028 * index of the first rx queue used by FCoE.
4031 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter
*adapter
)
4034 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
4036 f
->indices
= min((int)num_online_cpus(), f
->indices
);
4037 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
4038 adapter
->num_rx_queues
= 1;
4039 adapter
->num_tx_queues
= 1;
4040 #ifdef CONFIG_IXGBE_DCB
4041 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
4042 e_info(probe
, "FCoE enabled with DCB\n");
4043 ixgbe_set_dcb_queues(adapter
);
4046 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4047 e_info(probe
, "FCoE enabled with RSS\n");
4048 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
4049 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))
4050 ixgbe_set_fdir_queues(adapter
);
4052 ixgbe_set_rss_queues(adapter
);
4054 /* adding FCoE rx rings to the end */
4055 f
->mask
= adapter
->num_rx_queues
;
4056 adapter
->num_rx_queues
+= f
->indices
;
4057 adapter
->num_tx_queues
+= f
->indices
;
4065 #endif /* IXGBE_FCOE */
4067 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4068 * @adapter: board private structure to initialize
4070 * IOV doesn't actually use anything, so just NAK the
4071 * request for now and let the other queue routines
4072 * figure out what to do.
4074 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter
*adapter
)
4080 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4081 * @adapter: board private structure to initialize
4083 * This is the top level queue allocation routine. The order here is very
4084 * important, starting with the "most" number of features turned on at once,
4085 * and ending with the smallest set of features. This way large combinations
4086 * can be allocated if they're turned on, and smaller combinations are the
4087 * fallthrough conditions.
4090 static void ixgbe_set_num_queues(struct ixgbe_adapter
*adapter
)
4092 /* Start with base case */
4093 adapter
->num_rx_queues
= 1;
4094 adapter
->num_tx_queues
= 1;
4095 adapter
->num_rx_pools
= adapter
->num_rx_queues
;
4096 adapter
->num_rx_queues_per_pool
= 1;
4098 if (ixgbe_set_sriov_queues(adapter
))
4102 if (ixgbe_set_fcoe_queues(adapter
))
4105 #endif /* IXGBE_FCOE */
4106 #ifdef CONFIG_IXGBE_DCB
4107 if (ixgbe_set_dcb_queues(adapter
))
4111 if (ixgbe_set_fdir_queues(adapter
))
4114 if (ixgbe_set_rss_queues(adapter
))
4117 /* fallback to base case */
4118 adapter
->num_rx_queues
= 1;
4119 adapter
->num_tx_queues
= 1;
4122 /* Notify the stack of the (possibly) reduced Tx Queue count. */
4123 netif_set_real_num_tx_queues(adapter
->netdev
, adapter
->num_tx_queues
);
4126 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter
*adapter
,
4129 int err
, vector_threshold
;
4131 /* We'll want at least 3 (vector_threshold):
4134 * 3) Other (Link Status Change, etc.)
4135 * 4) TCP Timer (optional)
4137 vector_threshold
= MIN_MSIX_COUNT
;
4139 /* The more we get, the more we will assign to Tx/Rx Cleanup
4140 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4141 * Right now, we simply care about how many we'll get; we'll
4142 * set them up later while requesting irq's.
4144 while (vectors
>= vector_threshold
) {
4145 err
= pci_enable_msix(adapter
->pdev
, adapter
->msix_entries
,
4147 if (!err
) /* Success in acquiring all requested vectors. */
4150 vectors
= 0; /* Nasty failure, quit now */
4151 else /* err == number of vectors we should try again with */
4155 if (vectors
< vector_threshold
) {
4156 /* Can't allocate enough MSI-X interrupts? Oh well.
4157 * This just means we'll go with either a single MSI
4158 * vector or fall back to legacy interrupts.
4160 netif_printk(adapter
, hw
, KERN_DEBUG
, adapter
->netdev
,
4161 "Unable to allocate MSI-X interrupts\n");
4162 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
4163 kfree(adapter
->msix_entries
);
4164 adapter
->msix_entries
= NULL
;
4166 adapter
->flags
|= IXGBE_FLAG_MSIX_ENABLED
; /* Woot! */
4168 * Adjust for only the vectors we'll use, which is minimum
4169 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4170 * vectors we were allocated.
4172 adapter
->num_msix_vectors
= min(vectors
,
4173 adapter
->max_msix_q_vectors
+ NON_Q_VECTORS
);
4178 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4179 * @adapter: board private structure to initialize
4181 * Cache the descriptor ring offsets for RSS to the assigned rings.
4184 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter
*adapter
)
4189 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4190 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4191 adapter
->rx_ring
[i
]->reg_idx
= i
;
4192 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4193 adapter
->tx_ring
[i
]->reg_idx
= i
;
4202 #ifdef CONFIG_IXGBE_DCB
4204 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4205 * @adapter: board private structure to initialize
4207 * Cache the descriptor ring offsets for DCB to the assigned rings.
4210 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter
*adapter
)
4214 int dcb_i
= adapter
->ring_feature
[RING_F_DCB
].indices
;
4216 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
4217 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
4218 /* the number of queues is assumed to be symmetric */
4219 for (i
= 0; i
< dcb_i
; i
++) {
4220 adapter
->rx_ring
[i
]->reg_idx
= i
<< 3;
4221 adapter
->tx_ring
[i
]->reg_idx
= i
<< 2;
4224 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
4227 * Tx TC0 starts at: descriptor queue 0
4228 * Tx TC1 starts at: descriptor queue 32
4229 * Tx TC2 starts at: descriptor queue 64
4230 * Tx TC3 starts at: descriptor queue 80
4231 * Tx TC4 starts at: descriptor queue 96
4232 * Tx TC5 starts at: descriptor queue 104
4233 * Tx TC6 starts at: descriptor queue 112
4234 * Tx TC7 starts at: descriptor queue 120
4236 * Rx TC0-TC7 are offset by 16 queues each
4238 for (i
= 0; i
< 3; i
++) {
4239 adapter
->tx_ring
[i
]->reg_idx
= i
<< 5;
4240 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
4242 for ( ; i
< 5; i
++) {
4243 adapter
->tx_ring
[i
]->reg_idx
=
4245 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
4247 for ( ; i
< dcb_i
; i
++) {
4248 adapter
->tx_ring
[i
]->reg_idx
=
4250 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
4254 } else if (dcb_i
== 4) {
4256 * Tx TC0 starts at: descriptor queue 0
4257 * Tx TC1 starts at: descriptor queue 64
4258 * Tx TC2 starts at: descriptor queue 96
4259 * Tx TC3 starts at: descriptor queue 112
4261 * Rx TC0-TC3 are offset by 32 queues each
4263 adapter
->tx_ring
[0]->reg_idx
= 0;
4264 adapter
->tx_ring
[1]->reg_idx
= 64;
4265 adapter
->tx_ring
[2]->reg_idx
= 96;
4266 adapter
->tx_ring
[3]->reg_idx
= 112;
4267 for (i
= 0 ; i
< dcb_i
; i
++)
4268 adapter
->rx_ring
[i
]->reg_idx
= i
<< 5;
4286 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4287 * @adapter: board private structure to initialize
4289 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4292 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter
*adapter
)
4297 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
&&
4298 ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
4299 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))) {
4300 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4301 adapter
->rx_ring
[i
]->reg_idx
= i
;
4302 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4303 adapter
->tx_ring
[i
]->reg_idx
= i
;
4312 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4313 * @adapter: board private structure to initialize
4315 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4318 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter
*adapter
)
4320 int i
, fcoe_rx_i
= 0, fcoe_tx_i
= 0;
4322 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
4324 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
4325 #ifdef CONFIG_IXGBE_DCB
4326 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
4327 struct ixgbe_fcoe
*fcoe
= &adapter
->fcoe
;
4329 ixgbe_cache_ring_dcb(adapter
);
4330 /* find out queues in TC for FCoE */
4331 fcoe_rx_i
= adapter
->rx_ring
[fcoe
->tc
]->reg_idx
+ 1;
4332 fcoe_tx_i
= adapter
->tx_ring
[fcoe
->tc
]->reg_idx
+ 1;
4334 * In 82599, the number of Tx queues for each traffic
4335 * class for both 8-TC and 4-TC modes are:
4336 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4337 * 8 TCs: 32 32 16 16 8 8 8 8
4338 * 4 TCs: 64 64 32 32
4339 * We have max 8 queues for FCoE, where 8 the is
4340 * FCoE redirection table size. If TC for FCoE is
4341 * less than or equal to TC3, we have enough queues
4342 * to add max of 8 queues for FCoE, so we start FCoE
4343 * tx descriptor from the next one, i.e., reg_idx + 1.
4344 * If TC for FCoE is above TC3, implying 8 TC mode,
4345 * and we need 8 for FCoE, we have to take all queues
4346 * in that traffic class for FCoE.
4348 if ((f
->indices
== IXGBE_FCRETA_SIZE
) && (fcoe
->tc
> 3))
4351 #endif /* CONFIG_IXGBE_DCB */
4352 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4353 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
4354 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))
4355 ixgbe_cache_ring_fdir(adapter
);
4357 ixgbe_cache_ring_rss(adapter
);
4359 fcoe_rx_i
= f
->mask
;
4360 fcoe_tx_i
= f
->mask
;
4362 for (i
= 0; i
< f
->indices
; i
++, fcoe_rx_i
++, fcoe_tx_i
++) {
4363 adapter
->rx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_rx_i
;
4364 adapter
->tx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_tx_i
;
4371 #endif /* IXGBE_FCOE */
4373 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4374 * @adapter: board private structure to initialize
4376 * SR-IOV doesn't use any descriptor rings but changes the default if
4377 * no other mapping is used.
4380 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter
*adapter
)
4382 adapter
->rx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
4383 adapter
->tx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
4384 if (adapter
->num_vfs
)
4391 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4392 * @adapter: board private structure to initialize
4394 * Once we know the feature-set enabled for the device, we'll cache
4395 * the register offset the descriptor ring is assigned to.
4397 * Note, the order the various feature calls is important. It must start with
4398 * the "most" features enabled at the same time, then trickle down to the
4399 * least amount of features turned on at once.
4401 static void ixgbe_cache_ring_register(struct ixgbe_adapter
*adapter
)
4403 /* start with default case */
4404 adapter
->rx_ring
[0]->reg_idx
= 0;
4405 adapter
->tx_ring
[0]->reg_idx
= 0;
4407 if (ixgbe_cache_ring_sriov(adapter
))
4411 if (ixgbe_cache_ring_fcoe(adapter
))
4414 #endif /* IXGBE_FCOE */
4415 #ifdef CONFIG_IXGBE_DCB
4416 if (ixgbe_cache_ring_dcb(adapter
))
4420 if (ixgbe_cache_ring_fdir(adapter
))
4423 if (ixgbe_cache_ring_rss(adapter
))
4428 * ixgbe_alloc_queues - Allocate memory for all rings
4429 * @adapter: board private structure to initialize
4431 * We allocate one ring per queue at run-time since we don't know the
4432 * number of queues at compile-time. The polling_netdev array is
4433 * intended for Multiqueue, but should work fine with a single queue.
4435 static int ixgbe_alloc_queues(struct ixgbe_adapter
*adapter
)
4438 int orig_node
= adapter
->node
;
4440 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4441 struct ixgbe_ring
*ring
= adapter
->tx_ring
[i
];
4442 if (orig_node
== -1) {
4443 int cur_node
= next_online_node(adapter
->node
);
4444 if (cur_node
== MAX_NUMNODES
)
4445 cur_node
= first_online_node
;
4446 adapter
->node
= cur_node
;
4448 ring
= kzalloc_node(sizeof(struct ixgbe_ring
), GFP_KERNEL
,
4451 ring
= kzalloc(sizeof(struct ixgbe_ring
), GFP_KERNEL
);
4453 goto err_tx_ring_allocation
;
4454 ring
->count
= adapter
->tx_ring_count
;
4455 ring
->queue_index
= i
;
4456 ring
->numa_node
= adapter
->node
;
4458 adapter
->tx_ring
[i
] = ring
;
4461 /* Restore the adapter's original node */
4462 adapter
->node
= orig_node
;
4464 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
4465 struct ixgbe_ring
*ring
= adapter
->rx_ring
[i
];
4466 if (orig_node
== -1) {
4467 int cur_node
= next_online_node(adapter
->node
);
4468 if (cur_node
== MAX_NUMNODES
)
4469 cur_node
= first_online_node
;
4470 adapter
->node
= cur_node
;
4472 ring
= kzalloc_node(sizeof(struct ixgbe_ring
), GFP_KERNEL
,
4475 ring
= kzalloc(sizeof(struct ixgbe_ring
), GFP_KERNEL
);
4477 goto err_rx_ring_allocation
;
4478 ring
->count
= adapter
->rx_ring_count
;
4479 ring
->queue_index
= i
;
4480 ring
->numa_node
= adapter
->node
;
4482 adapter
->rx_ring
[i
] = ring
;
4485 /* Restore the adapter's original node */
4486 adapter
->node
= orig_node
;
4488 ixgbe_cache_ring_register(adapter
);
4492 err_rx_ring_allocation
:
4493 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4494 kfree(adapter
->tx_ring
[i
]);
4495 err_tx_ring_allocation
:
4500 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4501 * @adapter: board private structure to initialize
4503 * Attempt to configure the interrupts using the best available
4504 * capabilities of the hardware and the kernel.
4506 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter
*adapter
)
4508 struct ixgbe_hw
*hw
= &adapter
->hw
;
4510 int vector
, v_budget
;
4513 * It's easy to be greedy for MSI-X vectors, but it really
4514 * doesn't do us much good if we have a lot more vectors
4515 * than CPU's. So let's be conservative and only ask for
4516 * (roughly) the same number of vectors as there are CPU's.
4518 v_budget
= min(adapter
->num_rx_queues
+ adapter
->num_tx_queues
,
4519 (int)num_online_cpus()) + NON_Q_VECTORS
;
4522 * At the same time, hardware can only support a maximum of
4523 * hw.mac->max_msix_vectors vectors. With features
4524 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4525 * descriptor queues supported by our device. Thus, we cap it off in
4526 * those rare cases where the cpu count also exceeds our vector limit.
4528 v_budget
= min(v_budget
, (int)hw
->mac
.max_msix_vectors
);
4530 /* A failure in MSI-X entry allocation isn't fatal, but it does
4531 * mean we disable MSI-X capabilities of the adapter. */
4532 adapter
->msix_entries
= kcalloc(v_budget
,
4533 sizeof(struct msix_entry
), GFP_KERNEL
);
4534 if (adapter
->msix_entries
) {
4535 for (vector
= 0; vector
< v_budget
; vector
++)
4536 adapter
->msix_entries
[vector
].entry
= vector
;
4538 ixgbe_acquire_msix_vectors(adapter
, v_budget
);
4540 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
4544 adapter
->flags
&= ~IXGBE_FLAG_DCB_ENABLED
;
4545 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
4546 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4547 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
4548 adapter
->atr_sample_rate
= 0;
4549 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
4550 ixgbe_disable_sriov(adapter
);
4552 ixgbe_set_num_queues(adapter
);
4554 err
= pci_enable_msi(adapter
->pdev
);
4556 adapter
->flags
|= IXGBE_FLAG_MSI_ENABLED
;
4558 netif_printk(adapter
, hw
, KERN_DEBUG
, adapter
->netdev
,
4559 "Unable to allocate MSI interrupt, "
4560 "falling back to legacy. Error: %d\n", err
);
4570 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4571 * @adapter: board private structure to initialize
4573 * We allocate one q_vector per queue interrupt. If allocation fails we
4576 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter
*adapter
)
4578 int q_idx
, num_q_vectors
;
4579 struct ixgbe_q_vector
*q_vector
;
4581 int (*poll
)(struct napi_struct
*, int);
4583 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4584 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4585 napi_vectors
= adapter
->num_rx_queues
;
4586 poll
= &ixgbe_clean_rxtx_many
;
4593 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
4594 q_vector
= kzalloc_node(sizeof(struct ixgbe_q_vector
),
4595 GFP_KERNEL
, adapter
->node
);
4597 q_vector
= kzalloc(sizeof(struct ixgbe_q_vector
),
4601 q_vector
->adapter
= adapter
;
4602 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
4603 q_vector
->eitr
= adapter
->tx_eitr_param
;
4605 q_vector
->eitr
= adapter
->rx_eitr_param
;
4606 q_vector
->v_idx
= q_idx
;
4607 netif_napi_add(adapter
->netdev
, &q_vector
->napi
, (*poll
), 64);
4608 adapter
->q_vector
[q_idx
] = q_vector
;
4616 q_vector
= adapter
->q_vector
[q_idx
];
4617 netif_napi_del(&q_vector
->napi
);
4619 adapter
->q_vector
[q_idx
] = NULL
;
4625 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4626 * @adapter: board private structure to initialize
4628 * This function frees the memory allocated to the q_vectors. In addition if
4629 * NAPI is enabled it will delete any references to the NAPI struct prior
4630 * to freeing the q_vector.
4632 static void ixgbe_free_q_vectors(struct ixgbe_adapter
*adapter
)
4634 int q_idx
, num_q_vectors
;
4636 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
4637 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4641 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
4642 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[q_idx
];
4643 adapter
->q_vector
[q_idx
] = NULL
;
4644 netif_napi_del(&q_vector
->napi
);
4649 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter
*adapter
)
4651 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4652 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
4653 pci_disable_msix(adapter
->pdev
);
4654 kfree(adapter
->msix_entries
);
4655 adapter
->msix_entries
= NULL
;
4656 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
4657 adapter
->flags
&= ~IXGBE_FLAG_MSI_ENABLED
;
4658 pci_disable_msi(adapter
->pdev
);
4663 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4664 * @adapter: board private structure to initialize
4666 * We determine which interrupt scheme to use based on...
4667 * - Kernel support (MSI, MSI-X)
4668 * - which can be user-defined (via MODULE_PARAM)
4669 * - Hardware queue count (num_*_queues)
4670 * - defined by miscellaneous hardware support/features (RSS, etc.)
4672 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter
*adapter
)
4676 /* Number of supported queues */
4677 ixgbe_set_num_queues(adapter
);
4679 err
= ixgbe_set_interrupt_capability(adapter
);
4681 e_dev_err("Unable to setup interrupt capabilities\n");
4682 goto err_set_interrupt
;
4685 err
= ixgbe_alloc_q_vectors(adapter
);
4687 e_dev_err("Unable to allocate memory for queue vectors\n");
4688 goto err_alloc_q_vectors
;
4691 err
= ixgbe_alloc_queues(adapter
);
4693 e_dev_err("Unable to allocate memory for queues\n");
4694 goto err_alloc_queues
;
4697 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4698 (adapter
->num_rx_queues
> 1) ? "Enabled" : "Disabled",
4699 adapter
->num_rx_queues
, adapter
->num_tx_queues
);
4701 set_bit(__IXGBE_DOWN
, &adapter
->state
);
4706 ixgbe_free_q_vectors(adapter
);
4707 err_alloc_q_vectors
:
4708 ixgbe_reset_interrupt_capability(adapter
);
4714 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4715 * @adapter: board private structure to clear interrupt scheme on
4717 * We go through and clear interrupt specific resources and reset the structure
4718 * to pre-load conditions
4720 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter
*adapter
)
4724 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4725 kfree(adapter
->tx_ring
[i
]);
4726 adapter
->tx_ring
[i
] = NULL
;
4728 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
4729 kfree(adapter
->rx_ring
[i
]);
4730 adapter
->rx_ring
[i
] = NULL
;
4733 ixgbe_free_q_vectors(adapter
);
4734 ixgbe_reset_interrupt_capability(adapter
);
4738 * ixgbe_sfp_timer - worker thread to find a missing module
4739 * @data: pointer to our adapter struct
4741 static void ixgbe_sfp_timer(unsigned long data
)
4743 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
4746 * Do the sfp_timer outside of interrupt context due to the
4747 * delays that sfp+ detection requires
4749 schedule_work(&adapter
->sfp_task
);
4753 * ixgbe_sfp_task - worker thread to find a missing module
4754 * @work: pointer to work_struct containing our data
4756 static void ixgbe_sfp_task(struct work_struct
*work
)
4758 struct ixgbe_adapter
*adapter
= container_of(work
,
4759 struct ixgbe_adapter
,
4761 struct ixgbe_hw
*hw
= &adapter
->hw
;
4763 if ((hw
->phy
.type
== ixgbe_phy_nl
) &&
4764 (hw
->phy
.sfp_type
== ixgbe_sfp_type_not_present
)) {
4765 s32 ret
= hw
->phy
.ops
.identify_sfp(hw
);
4766 if (ret
== IXGBE_ERR_SFP_NOT_PRESENT
)
4768 ret
= hw
->phy
.ops
.reset(hw
);
4769 if (ret
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
4770 e_dev_err("failed to initialize because an unsupported "
4771 "SFP+ module type was detected.\n");
4772 e_dev_err("Reload the driver after installing a "
4773 "supported module.\n");
4774 unregister_netdev(adapter
->netdev
);
4776 e_info(probe
, "detected SFP+: %d\n", hw
->phy
.sfp_type
);
4778 /* don't need this routine any more */
4779 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
4783 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
))
4784 mod_timer(&adapter
->sfp_timer
,
4785 round_jiffies(jiffies
+ (2 * HZ
)));
4789 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4790 * @adapter: board private structure to initialize
4792 * ixgbe_sw_init initializes the Adapter private data structure.
4793 * Fields are initialized based on PCI device information and
4794 * OS network device settings (MTU size).
4796 static int __devinit
ixgbe_sw_init(struct ixgbe_adapter
*adapter
)
4798 struct ixgbe_hw
*hw
= &adapter
->hw
;
4799 struct pci_dev
*pdev
= adapter
->pdev
;
4800 struct net_device
*dev
= adapter
->netdev
;
4802 #ifdef CONFIG_IXGBE_DCB
4804 struct tc_configuration
*tc
;
4807 /* PCI config space info */
4809 hw
->vendor_id
= pdev
->vendor
;
4810 hw
->device_id
= pdev
->device
;
4811 hw
->revision_id
= pdev
->revision
;
4812 hw
->subsystem_vendor_id
= pdev
->subsystem_vendor
;
4813 hw
->subsystem_device_id
= pdev
->subsystem_device
;
4815 /* Set capability flags */
4816 rss
= min(IXGBE_MAX_RSS_INDICES
, (int)num_online_cpus());
4817 adapter
->ring_feature
[RING_F_RSS
].indices
= rss
;
4818 adapter
->flags
|= IXGBE_FLAG_RSS_ENABLED
;
4819 adapter
->ring_feature
[RING_F_DCB
].indices
= IXGBE_MAX_DCB_INDICES
;
4820 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
4821 if (hw
->device_id
== IXGBE_DEV_ID_82598AT
)
4822 adapter
->flags
|= IXGBE_FLAG_FAN_FAIL_CAPABLE
;
4823 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82598
;
4824 } else if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
4825 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82599
;
4826 adapter
->flags2
|= IXGBE_FLAG2_RSC_CAPABLE
;
4827 adapter
->flags2
|= IXGBE_FLAG2_RSC_ENABLED
;
4828 if (hw
->device_id
== IXGBE_DEV_ID_82599_T3_LOM
)
4829 adapter
->flags2
|= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
;
4830 if (dev
->features
& NETIF_F_NTUPLE
) {
4831 /* Flow Director perfect filter enabled */
4832 adapter
->flags
|= IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
4833 adapter
->atr_sample_rate
= 0;
4834 spin_lock_init(&adapter
->fdir_perfect_lock
);
4836 /* Flow Director hash filters enabled */
4837 adapter
->flags
|= IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4838 adapter
->atr_sample_rate
= 20;
4840 adapter
->ring_feature
[RING_F_FDIR
].indices
=
4841 IXGBE_MAX_FDIR_INDICES
;
4842 adapter
->fdir_pballoc
= 0;
4844 adapter
->flags
|= IXGBE_FLAG_FCOE_CAPABLE
;
4845 adapter
->flags
&= ~IXGBE_FLAG_FCOE_ENABLED
;
4846 adapter
->ring_feature
[RING_F_FCOE
].indices
= 0;
4847 #ifdef CONFIG_IXGBE_DCB
4848 /* Default traffic class to use for FCoE */
4849 adapter
->fcoe
.tc
= IXGBE_FCOE_DEFTC
;
4850 adapter
->fcoe
.up
= IXGBE_FCOE_DEFTC
;
4852 #endif /* IXGBE_FCOE */
4855 #ifdef CONFIG_IXGBE_DCB
4856 /* Configure DCB traffic classes */
4857 for (j
= 0; j
< MAX_TRAFFIC_CLASS
; j
++) {
4858 tc
= &adapter
->dcb_cfg
.tc_config
[j
];
4859 tc
->path
[DCB_TX_CONFIG
].bwg_id
= 0;
4860 tc
->path
[DCB_TX_CONFIG
].bwg_percent
= 12 + (j
& 1);
4861 tc
->path
[DCB_RX_CONFIG
].bwg_id
= 0;
4862 tc
->path
[DCB_RX_CONFIG
].bwg_percent
= 12 + (j
& 1);
4863 tc
->dcb_pfc
= pfc_disabled
;
4865 adapter
->dcb_cfg
.bw_percentage
[DCB_TX_CONFIG
][0] = 100;
4866 adapter
->dcb_cfg
.bw_percentage
[DCB_RX_CONFIG
][0] = 100;
4867 adapter
->dcb_cfg
.rx_pba_cfg
= pba_equal
;
4868 adapter
->dcb_cfg
.pfc_mode_enable
= false;
4869 adapter
->dcb_cfg
.round_robin_enable
= false;
4870 adapter
->dcb_set_bitmap
= 0x00;
4871 ixgbe_copy_dcb_cfg(&adapter
->dcb_cfg
, &adapter
->temp_dcb_cfg
,
4872 adapter
->ring_feature
[RING_F_DCB
].indices
);
4876 /* default flow control settings */
4877 hw
->fc
.requested_mode
= ixgbe_fc_full
;
4878 hw
->fc
.current_mode
= ixgbe_fc_full
; /* init for ethtool output */
4880 adapter
->last_lfc_mode
= hw
->fc
.current_mode
;
4882 hw
->fc
.high_water
= IXGBE_DEFAULT_FCRTH
;
4883 hw
->fc
.low_water
= IXGBE_DEFAULT_FCRTL
;
4884 hw
->fc
.pause_time
= IXGBE_DEFAULT_FCPAUSE
;
4885 hw
->fc
.send_xon
= true;
4886 hw
->fc
.disable_fc_autoneg
= false;
4888 /* enable itr by default in dynamic mode */
4889 adapter
->rx_itr_setting
= 1;
4890 adapter
->rx_eitr_param
= 20000;
4891 adapter
->tx_itr_setting
= 1;
4892 adapter
->tx_eitr_param
= 10000;
4894 /* set defaults for eitr in MegaBytes */
4895 adapter
->eitr_low
= 10;
4896 adapter
->eitr_high
= 20;
4898 /* set default ring sizes */
4899 adapter
->tx_ring_count
= IXGBE_DEFAULT_TXD
;
4900 adapter
->rx_ring_count
= IXGBE_DEFAULT_RXD
;
4902 /* initialize eeprom parameters */
4903 if (ixgbe_init_eeprom_params_generic(hw
)) {
4904 e_dev_err("EEPROM initialization failed\n");
4908 /* enable rx csum by default */
4909 adapter
->flags
|= IXGBE_FLAG_RX_CSUM_ENABLED
;
4911 /* get assigned NUMA node */
4912 adapter
->node
= dev_to_node(&pdev
->dev
);
4914 set_bit(__IXGBE_DOWN
, &adapter
->state
);
4920 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4921 * @adapter: board private structure
4922 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4924 * Return 0 on success, negative on failure
4926 int ixgbe_setup_tx_resources(struct ixgbe_adapter
*adapter
,
4927 struct ixgbe_ring
*tx_ring
)
4929 struct pci_dev
*pdev
= adapter
->pdev
;
4932 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
4933 tx_ring
->tx_buffer_info
= vmalloc_node(size
, tx_ring
->numa_node
);
4934 if (!tx_ring
->tx_buffer_info
)
4935 tx_ring
->tx_buffer_info
= vmalloc(size
);
4936 if (!tx_ring
->tx_buffer_info
)
4938 memset(tx_ring
->tx_buffer_info
, 0, size
);
4940 /* round up to nearest 4K */
4941 tx_ring
->size
= tx_ring
->count
* sizeof(union ixgbe_adv_tx_desc
);
4942 tx_ring
->size
= ALIGN(tx_ring
->size
, 4096);
4944 tx_ring
->desc
= dma_alloc_coherent(&pdev
->dev
, tx_ring
->size
,
4945 &tx_ring
->dma
, GFP_KERNEL
);
4949 tx_ring
->next_to_use
= 0;
4950 tx_ring
->next_to_clean
= 0;
4951 tx_ring
->work_limit
= tx_ring
->count
;
4955 vfree(tx_ring
->tx_buffer_info
);
4956 tx_ring
->tx_buffer_info
= NULL
;
4957 e_err(probe
, "Unable to allocate memory for the Tx descriptor ring\n");
4962 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4963 * @adapter: board private structure
4965 * If this function returns with an error, then it's possible one or
4966 * more of the rings is populated (while the rest are not). It is the
4967 * callers duty to clean those orphaned rings.
4969 * Return 0 on success, negative on failure
4971 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter
*adapter
)
4975 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4976 err
= ixgbe_setup_tx_resources(adapter
, adapter
->tx_ring
[i
]);
4979 e_err(probe
, "Allocation for Tx Queue %u failed\n", i
);
4987 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4988 * @adapter: board private structure
4989 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4991 * Returns 0 on success, negative on failure
4993 int ixgbe_setup_rx_resources(struct ixgbe_adapter
*adapter
,
4994 struct ixgbe_ring
*rx_ring
)
4996 struct pci_dev
*pdev
= adapter
->pdev
;
4999 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
5000 rx_ring
->rx_buffer_info
= vmalloc_node(size
, adapter
->node
);
5001 if (!rx_ring
->rx_buffer_info
)
5002 rx_ring
->rx_buffer_info
= vmalloc(size
);
5003 if (!rx_ring
->rx_buffer_info
) {
5004 e_err(probe
, "vmalloc allocation failed for the Rx "
5005 "descriptor ring\n");
5008 memset(rx_ring
->rx_buffer_info
, 0, size
);
5010 /* Round up to nearest 4K */
5011 rx_ring
->size
= rx_ring
->count
* sizeof(union ixgbe_adv_rx_desc
);
5012 rx_ring
->size
= ALIGN(rx_ring
->size
, 4096);
5014 rx_ring
->desc
= dma_alloc_coherent(&pdev
->dev
, rx_ring
->size
,
5015 &rx_ring
->dma
, GFP_KERNEL
);
5017 if (!rx_ring
->desc
) {
5018 e_err(probe
, "Memory allocation failed for the Rx "
5019 "descriptor ring\n");
5020 vfree(rx_ring
->rx_buffer_info
);
5024 rx_ring
->next_to_clean
= 0;
5025 rx_ring
->next_to_use
= 0;
5034 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5035 * @adapter: board private structure
5037 * If this function returns with an error, then it's possible one or
5038 * more of the rings is populated (while the rest are not). It is the
5039 * callers duty to clean those orphaned rings.
5041 * Return 0 on success, negative on failure
5044 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter
*adapter
)
5048 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5049 err
= ixgbe_setup_rx_resources(adapter
, adapter
->rx_ring
[i
]);
5052 e_err(probe
, "Allocation for Rx Queue %u failed\n", i
);
5060 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5061 * @adapter: board private structure
5062 * @tx_ring: Tx descriptor ring for a specific queue
5064 * Free all transmit software resources
5066 void ixgbe_free_tx_resources(struct ixgbe_adapter
*adapter
,
5067 struct ixgbe_ring
*tx_ring
)
5069 struct pci_dev
*pdev
= adapter
->pdev
;
5071 ixgbe_clean_tx_ring(adapter
, tx_ring
);
5073 vfree(tx_ring
->tx_buffer_info
);
5074 tx_ring
->tx_buffer_info
= NULL
;
5076 dma_free_coherent(&pdev
->dev
, tx_ring
->size
, tx_ring
->desc
,
5079 tx_ring
->desc
= NULL
;
5083 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5084 * @adapter: board private structure
5086 * Free all transmit software resources
5088 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter
*adapter
)
5092 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5093 if (adapter
->tx_ring
[i
]->desc
)
5094 ixgbe_free_tx_resources(adapter
, adapter
->tx_ring
[i
]);
5098 * ixgbe_free_rx_resources - Free Rx Resources
5099 * @adapter: board private structure
5100 * @rx_ring: ring to clean the resources from
5102 * Free all receive software resources
5104 void ixgbe_free_rx_resources(struct ixgbe_adapter
*adapter
,
5105 struct ixgbe_ring
*rx_ring
)
5107 struct pci_dev
*pdev
= adapter
->pdev
;
5109 ixgbe_clean_rx_ring(adapter
, rx_ring
);
5111 vfree(rx_ring
->rx_buffer_info
);
5112 rx_ring
->rx_buffer_info
= NULL
;
5114 dma_free_coherent(&pdev
->dev
, rx_ring
->size
, rx_ring
->desc
,
5117 rx_ring
->desc
= NULL
;
5121 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5122 * @adapter: board private structure
5124 * Free all receive software resources
5126 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter
*adapter
)
5130 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
5131 if (adapter
->rx_ring
[i
]->desc
)
5132 ixgbe_free_rx_resources(adapter
, adapter
->rx_ring
[i
]);
5136 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5137 * @netdev: network interface device structure
5138 * @new_mtu: new value for maximum frame size
5140 * Returns 0 on success, negative on failure
5142 static int ixgbe_change_mtu(struct net_device
*netdev
, int new_mtu
)
5144 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5145 int max_frame
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
5147 /* MTU < 68 is an error and causes problems on some kernels */
5148 if ((new_mtu
< 68) || (max_frame
> IXGBE_MAX_JUMBO_FRAME_SIZE
))
5151 e_info(probe
, "changing MTU from %d to %d\n", netdev
->mtu
, new_mtu
);
5152 /* must set new MTU before calling down or up */
5153 netdev
->mtu
= new_mtu
;
5155 if (netif_running(netdev
))
5156 ixgbe_reinit_locked(adapter
);
5162 * ixgbe_open - Called when a network interface is made active
5163 * @netdev: network interface device structure
5165 * Returns 0 on success, negative value on failure
5167 * The open entry point is called when a network interface is made
5168 * active by the system (IFF_UP). At this point all resources needed
5169 * for transmit and receive operations are allocated, the interrupt
5170 * handler is registered with the OS, the watchdog timer is started,
5171 * and the stack is notified that the interface is ready.
5173 static int ixgbe_open(struct net_device
*netdev
)
5175 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5178 /* disallow open during test */
5179 if (test_bit(__IXGBE_TESTING
, &adapter
->state
))
5182 netif_carrier_off(netdev
);
5184 /* allocate transmit descriptors */
5185 err
= ixgbe_setup_all_tx_resources(adapter
);
5189 /* allocate receive descriptors */
5190 err
= ixgbe_setup_all_rx_resources(adapter
);
5194 ixgbe_configure(adapter
);
5196 err
= ixgbe_request_irq(adapter
);
5200 err
= ixgbe_up_complete(adapter
);
5204 netif_tx_start_all_queues(netdev
);
5209 ixgbe_release_hw_control(adapter
);
5210 ixgbe_free_irq(adapter
);
5213 ixgbe_free_all_rx_resources(adapter
);
5215 ixgbe_free_all_tx_resources(adapter
);
5216 ixgbe_reset(adapter
);
5222 * ixgbe_close - Disables a network interface
5223 * @netdev: network interface device structure
5225 * Returns 0, this is not allowed to fail
5227 * The close entry point is called when an interface is de-activated
5228 * by the OS. The hardware is still under the drivers control, but
5229 * needs to be disabled. A global MAC reset is issued to stop the
5230 * hardware, and all transmit and receive resources are freed.
5232 static int ixgbe_close(struct net_device
*netdev
)
5234 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5236 ixgbe_down(adapter
);
5237 ixgbe_free_irq(adapter
);
5239 ixgbe_free_all_tx_resources(adapter
);
5240 ixgbe_free_all_rx_resources(adapter
);
5242 ixgbe_release_hw_control(adapter
);
5248 static int ixgbe_resume(struct pci_dev
*pdev
)
5250 struct net_device
*netdev
= pci_get_drvdata(pdev
);
5251 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5254 pci_set_power_state(pdev
, PCI_D0
);
5255 pci_restore_state(pdev
);
5257 * pci_restore_state clears dev->state_saved so call
5258 * pci_save_state to restore it.
5260 pci_save_state(pdev
);
5262 err
= pci_enable_device_mem(pdev
);
5264 e_dev_err("Cannot enable PCI device from suspend\n");
5267 pci_set_master(pdev
);
5269 pci_wake_from_d3(pdev
, false);
5271 err
= ixgbe_init_interrupt_scheme(adapter
);
5273 e_dev_err("Cannot initialize interrupts for device\n");
5277 ixgbe_reset(adapter
);
5279 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
5281 if (netif_running(netdev
)) {
5282 err
= ixgbe_open(adapter
->netdev
);
5287 netif_device_attach(netdev
);
5291 #endif /* CONFIG_PM */
5293 static int __ixgbe_shutdown(struct pci_dev
*pdev
, bool *enable_wake
)
5295 struct net_device
*netdev
= pci_get_drvdata(pdev
);
5296 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5297 struct ixgbe_hw
*hw
= &adapter
->hw
;
5299 u32 wufc
= adapter
->wol
;
5304 netif_device_detach(netdev
);
5306 if (netif_running(netdev
)) {
5307 ixgbe_down(adapter
);
5308 ixgbe_free_irq(adapter
);
5309 ixgbe_free_all_tx_resources(adapter
);
5310 ixgbe_free_all_rx_resources(adapter
);
5314 retval
= pci_save_state(pdev
);
5320 ixgbe_set_rx_mode(netdev
);
5322 /* turn on all-multi mode if wake on multicast is enabled */
5323 if (wufc
& IXGBE_WUFC_MC
) {
5324 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
5325 fctrl
|= IXGBE_FCTRL_MPE
;
5326 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
5329 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
5330 ctrl
|= IXGBE_CTRL_GIO_DIS
;
5331 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, ctrl
);
5333 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, wufc
);
5335 IXGBE_WRITE_REG(hw
, IXGBE_WUC
, 0);
5336 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, 0);
5339 if (wufc
&& hw
->mac
.type
== ixgbe_mac_82599EB
)
5340 pci_wake_from_d3(pdev
, true);
5342 pci_wake_from_d3(pdev
, false);
5344 *enable_wake
= !!wufc
;
5346 ixgbe_clear_interrupt_scheme(adapter
);
5348 ixgbe_release_hw_control(adapter
);
5350 pci_disable_device(pdev
);
5356 static int ixgbe_suspend(struct pci_dev
*pdev
, pm_message_t state
)
5361 retval
= __ixgbe_shutdown(pdev
, &wake
);
5366 pci_prepare_to_sleep(pdev
);
5368 pci_wake_from_d3(pdev
, false);
5369 pci_set_power_state(pdev
, PCI_D3hot
);
5374 #endif /* CONFIG_PM */
5376 static void ixgbe_shutdown(struct pci_dev
*pdev
)
5380 __ixgbe_shutdown(pdev
, &wake
);
5382 if (system_state
== SYSTEM_POWER_OFF
) {
5383 pci_wake_from_d3(pdev
, wake
);
5384 pci_set_power_state(pdev
, PCI_D3hot
);
5389 * ixgbe_update_stats - Update the board statistics counters.
5390 * @adapter: board private structure
5392 void ixgbe_update_stats(struct ixgbe_adapter
*adapter
)
5394 struct net_device
*netdev
= adapter
->netdev
;
5395 struct ixgbe_hw
*hw
= &adapter
->hw
;
5397 u32 i
, missed_rx
= 0, mpc
, bprc
, lxon
, lxoff
, xon_off_tot
;
5398 u64 non_eop_descs
= 0, restart_queue
= 0;
5400 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
5401 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
5404 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
5407 for (i
= 0; i
< 16; i
++)
5408 adapter
->hw_rx_no_dma_resources
+=
5409 IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
5410 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5411 rsc_count
+= adapter
->rx_ring
[i
]->rsc_count
;
5412 rsc_flush
+= adapter
->rx_ring
[i
]->rsc_flush
;
5414 adapter
->rsc_total_count
= rsc_count
;
5415 adapter
->rsc_total_flush
= rsc_flush
;
5418 /* gather some stats to the adapter struct that are per queue */
5419 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5420 restart_queue
+= adapter
->tx_ring
[i
]->restart_queue
;
5421 adapter
->restart_queue
= restart_queue
;
5423 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
5424 non_eop_descs
+= adapter
->rx_ring
[i
]->non_eop_descs
;
5425 adapter
->non_eop_descs
= non_eop_descs
;
5427 adapter
->stats
.crcerrs
+= IXGBE_READ_REG(hw
, IXGBE_CRCERRS
);
5428 for (i
= 0; i
< 8; i
++) {
5429 /* for packet buffers not used, the register should read 0 */
5430 mpc
= IXGBE_READ_REG(hw
, IXGBE_MPC(i
));
5432 adapter
->stats
.mpc
[i
] += mpc
;
5433 total_mpc
+= adapter
->stats
.mpc
[i
];
5434 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
5435 adapter
->stats
.rnbc
[i
] += IXGBE_READ_REG(hw
, IXGBE_RNBC(i
));
5436 adapter
->stats
.qptc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPTC(i
));
5437 adapter
->stats
.qbtc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBTC(i
));
5438 adapter
->stats
.qprc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRC(i
));
5439 adapter
->stats
.qbrc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBRC(i
));
5440 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
5441 adapter
->stats
.pxonrxc
[i
] += IXGBE_READ_REG(hw
,
5442 IXGBE_PXONRXCNT(i
));
5443 adapter
->stats
.pxoffrxc
[i
] += IXGBE_READ_REG(hw
,
5444 IXGBE_PXOFFRXCNT(i
));
5445 adapter
->stats
.qprdc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
5447 adapter
->stats
.pxonrxc
[i
] += IXGBE_READ_REG(hw
,
5449 adapter
->stats
.pxoffrxc
[i
] += IXGBE_READ_REG(hw
,
5452 adapter
->stats
.pxontxc
[i
] += IXGBE_READ_REG(hw
,
5454 adapter
->stats
.pxofftxc
[i
] += IXGBE_READ_REG(hw
,
5457 adapter
->stats
.gprc
+= IXGBE_READ_REG(hw
, IXGBE_GPRC
);
5458 /* work around hardware counting issue */
5459 adapter
->stats
.gprc
-= missed_rx
;
5461 /* 82598 hardware only has a 32 bit counter in the high register */
5462 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
5464 adapter
->stats
.gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCL
);
5465 tmp
= IXGBE_READ_REG(hw
, IXGBE_GORCH
) & 0xF; /* 4 high bits of GORC */
5466 adapter
->stats
.gorc
+= (tmp
<< 32);
5467 adapter
->stats
.gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCL
);
5468 tmp
= IXGBE_READ_REG(hw
, IXGBE_GOTCH
) & 0xF; /* 4 high bits of GOTC */
5469 adapter
->stats
.gotc
+= (tmp
<< 32);
5470 adapter
->stats
.tor
+= IXGBE_READ_REG(hw
, IXGBE_TORL
);
5471 IXGBE_READ_REG(hw
, IXGBE_TORH
); /* to clear */
5472 adapter
->stats
.lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXCNT
);
5473 adapter
->stats
.lxoffrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXCNT
);
5474 adapter
->stats
.fdirmatch
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMATCH
);
5475 adapter
->stats
.fdirmiss
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMISS
);
5477 adapter
->stats
.fccrc
+= IXGBE_READ_REG(hw
, IXGBE_FCCRC
);
5478 adapter
->stats
.fcoerpdc
+= IXGBE_READ_REG(hw
, IXGBE_FCOERPDC
);
5479 adapter
->stats
.fcoeprc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPRC
);
5480 adapter
->stats
.fcoeptc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPTC
);
5481 adapter
->stats
.fcoedwrc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWRC
);
5482 adapter
->stats
.fcoedwtc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWTC
);
5483 #endif /* IXGBE_FCOE */
5485 adapter
->stats
.lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXC
);
5486 adapter
->stats
.lxoffrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXC
);
5487 adapter
->stats
.gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCH
);
5488 adapter
->stats
.gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCH
);
5489 adapter
->stats
.tor
+= IXGBE_READ_REG(hw
, IXGBE_TORH
);
5491 bprc
= IXGBE_READ_REG(hw
, IXGBE_BPRC
);
5492 adapter
->stats
.bprc
+= bprc
;
5493 adapter
->stats
.mprc
+= IXGBE_READ_REG(hw
, IXGBE_MPRC
);
5494 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
5495 adapter
->stats
.mprc
-= bprc
;
5496 adapter
->stats
.roc
+= IXGBE_READ_REG(hw
, IXGBE_ROC
);
5497 adapter
->stats
.prc64
+= IXGBE_READ_REG(hw
, IXGBE_PRC64
);
5498 adapter
->stats
.prc127
+= IXGBE_READ_REG(hw
, IXGBE_PRC127
);
5499 adapter
->stats
.prc255
+= IXGBE_READ_REG(hw
, IXGBE_PRC255
);
5500 adapter
->stats
.prc511
+= IXGBE_READ_REG(hw
, IXGBE_PRC511
);
5501 adapter
->stats
.prc1023
+= IXGBE_READ_REG(hw
, IXGBE_PRC1023
);
5502 adapter
->stats
.prc1522
+= IXGBE_READ_REG(hw
, IXGBE_PRC1522
);
5503 adapter
->stats
.rlec
+= IXGBE_READ_REG(hw
, IXGBE_RLEC
);
5504 lxon
= IXGBE_READ_REG(hw
, IXGBE_LXONTXC
);
5505 adapter
->stats
.lxontxc
+= lxon
;
5506 lxoff
= IXGBE_READ_REG(hw
, IXGBE_LXOFFTXC
);
5507 adapter
->stats
.lxofftxc
+= lxoff
;
5508 adapter
->stats
.ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
5509 adapter
->stats
.gptc
+= IXGBE_READ_REG(hw
, IXGBE_GPTC
);
5510 adapter
->stats
.mptc
+= IXGBE_READ_REG(hw
, IXGBE_MPTC
);
5512 * 82598 errata - tx of flow control packets is included in tx counters
5514 xon_off_tot
= lxon
+ lxoff
;
5515 adapter
->stats
.gptc
-= xon_off_tot
;
5516 adapter
->stats
.mptc
-= xon_off_tot
;
5517 adapter
->stats
.gotc
-= (xon_off_tot
* (ETH_ZLEN
+ ETH_FCS_LEN
));
5518 adapter
->stats
.ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
5519 adapter
->stats
.rfc
+= IXGBE_READ_REG(hw
, IXGBE_RFC
);
5520 adapter
->stats
.rjc
+= IXGBE_READ_REG(hw
, IXGBE_RJC
);
5521 adapter
->stats
.tpr
+= IXGBE_READ_REG(hw
, IXGBE_TPR
);
5522 adapter
->stats
.ptc64
+= IXGBE_READ_REG(hw
, IXGBE_PTC64
);
5523 adapter
->stats
.ptc64
-= xon_off_tot
;
5524 adapter
->stats
.ptc127
+= IXGBE_READ_REG(hw
, IXGBE_PTC127
);
5525 adapter
->stats
.ptc255
+= IXGBE_READ_REG(hw
, IXGBE_PTC255
);
5526 adapter
->stats
.ptc511
+= IXGBE_READ_REG(hw
, IXGBE_PTC511
);
5527 adapter
->stats
.ptc1023
+= IXGBE_READ_REG(hw
, IXGBE_PTC1023
);
5528 adapter
->stats
.ptc1522
+= IXGBE_READ_REG(hw
, IXGBE_PTC1522
);
5529 adapter
->stats
.bptc
+= IXGBE_READ_REG(hw
, IXGBE_BPTC
);
5531 /* Fill out the OS statistics structure */
5532 netdev
->stats
.multicast
= adapter
->stats
.mprc
;
5535 netdev
->stats
.rx_errors
= adapter
->stats
.crcerrs
+
5536 adapter
->stats
.rlec
;
5537 netdev
->stats
.rx_dropped
= 0;
5538 netdev
->stats
.rx_length_errors
= adapter
->stats
.rlec
;
5539 netdev
->stats
.rx_crc_errors
= adapter
->stats
.crcerrs
;
5540 netdev
->stats
.rx_missed_errors
= total_mpc
;
5544 * ixgbe_watchdog - Timer Call-back
5545 * @data: pointer to adapter cast into an unsigned long
5547 static void ixgbe_watchdog(unsigned long data
)
5549 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
5550 struct ixgbe_hw
*hw
= &adapter
->hw
;
5555 * Do the watchdog outside of interrupt context due to the lovely
5556 * delays that some of the newer hardware requires
5559 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
5560 goto watchdog_short_circuit
;
5562 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)) {
5564 * for legacy and MSI interrupts don't set any bits
5565 * that are enabled for EIAM, because this operation
5566 * would set *both* EIMS and EICS for any bit in EIAM
5568 IXGBE_WRITE_REG(hw
, IXGBE_EICS
,
5569 (IXGBE_EICS_TCP_TIMER
| IXGBE_EICS_OTHER
));
5570 goto watchdog_reschedule
;
5573 /* get one bit for every active tx/rx interrupt vector */
5574 for (i
= 0; i
< adapter
->num_msix_vectors
- NON_Q_VECTORS
; i
++) {
5575 struct ixgbe_q_vector
*qv
= adapter
->q_vector
[i
];
5576 if (qv
->rxr_count
|| qv
->txr_count
)
5577 eics
|= ((u64
)1 << i
);
5580 /* Cause software interrupt to ensure rx rings are cleaned */
5581 ixgbe_irq_rearm_queues(adapter
, eics
);
5583 watchdog_reschedule
:
5584 /* Reset the timer */
5585 mod_timer(&adapter
->watchdog_timer
, round_jiffies(jiffies
+ 2 * HZ
));
5587 watchdog_short_circuit
:
5588 schedule_work(&adapter
->watchdog_task
);
5592 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5593 * @work: pointer to work_struct containing our data
5595 static void ixgbe_multispeed_fiber_task(struct work_struct
*work
)
5597 struct ixgbe_adapter
*adapter
= container_of(work
,
5598 struct ixgbe_adapter
,
5599 multispeed_fiber_task
);
5600 struct ixgbe_hw
*hw
= &adapter
->hw
;
5604 adapter
->flags
|= IXGBE_FLAG_IN_SFP_LINK_TASK
;
5605 autoneg
= hw
->phy
.autoneg_advertised
;
5606 if ((!autoneg
) && (hw
->mac
.ops
.get_link_capabilities
))
5607 hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
, &negotiation
);
5608 hw
->mac
.autotry_restart
= false;
5609 if (hw
->mac
.ops
.setup_link
)
5610 hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, true);
5611 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
5612 adapter
->flags
&= ~IXGBE_FLAG_IN_SFP_LINK_TASK
;
5616 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5617 * @work: pointer to work_struct containing our data
5619 static void ixgbe_sfp_config_module_task(struct work_struct
*work
)
5621 struct ixgbe_adapter
*adapter
= container_of(work
,
5622 struct ixgbe_adapter
,
5623 sfp_config_module_task
);
5624 struct ixgbe_hw
*hw
= &adapter
->hw
;
5627 adapter
->flags
|= IXGBE_FLAG_IN_SFP_MOD_TASK
;
5629 /* Time for electrical oscillations to settle down */
5631 err
= hw
->phy
.ops
.identify_sfp(hw
);
5633 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
5634 e_dev_err("failed to initialize because an unsupported SFP+ "
5635 "module type was detected.\n");
5636 e_dev_err("Reload the driver after installing a supported "
5638 unregister_netdev(adapter
->netdev
);
5641 hw
->mac
.ops
.setup_sfp(hw
);
5643 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_LINK_TASK
))
5644 /* This will also work for DA Twinax connections */
5645 schedule_work(&adapter
->multispeed_fiber_task
);
5646 adapter
->flags
&= ~IXGBE_FLAG_IN_SFP_MOD_TASK
;
5650 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5651 * @work: pointer to work_struct containing our data
5653 static void ixgbe_fdir_reinit_task(struct work_struct
*work
)
5655 struct ixgbe_adapter
*adapter
= container_of(work
,
5656 struct ixgbe_adapter
,
5658 struct ixgbe_hw
*hw
= &adapter
->hw
;
5661 if (ixgbe_reinit_fdir_tables_82599(hw
) == 0) {
5662 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5663 set_bit(__IXGBE_FDIR_INIT_DONE
,
5664 &(adapter
->tx_ring
[i
]->reinit_state
));
5666 e_err(probe
, "failed to finish FDIR re-initialization, "
5667 "ignored adding FDIR ATR filters\n");
5669 /* Done FDIR Re-initialization, enable transmits */
5670 netif_tx_start_all_queues(adapter
->netdev
);
5673 static DEFINE_MUTEX(ixgbe_watchdog_lock
);
5676 * ixgbe_watchdog_task - worker thread to bring link up
5677 * @work: pointer to work_struct containing our data
5679 static void ixgbe_watchdog_task(struct work_struct
*work
)
5681 struct ixgbe_adapter
*adapter
= container_of(work
,
5682 struct ixgbe_adapter
,
5684 struct net_device
*netdev
= adapter
->netdev
;
5685 struct ixgbe_hw
*hw
= &adapter
->hw
;
5689 struct ixgbe_ring
*tx_ring
;
5690 int some_tx_pending
= 0;
5692 mutex_lock(&ixgbe_watchdog_lock
);
5694 link_up
= adapter
->link_up
;
5695 link_speed
= adapter
->link_speed
;
5697 if (adapter
->flags
& IXGBE_FLAG_NEED_LINK_UPDATE
) {
5698 hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
, false);
5701 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
5702 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++)
5703 hw
->mac
.ops
.fc_enable(hw
, i
);
5705 hw
->mac
.ops
.fc_enable(hw
, 0);
5708 hw
->mac
.ops
.fc_enable(hw
, 0);
5713 time_after(jiffies
, (adapter
->link_check_timeout
+
5714 IXGBE_TRY_LINK_TIMEOUT
))) {
5715 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_UPDATE
;
5716 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMC_LSC
);
5718 adapter
->link_up
= link_up
;
5719 adapter
->link_speed
= link_speed
;
5723 if (!netif_carrier_ok(netdev
)) {
5724 bool flow_rx
, flow_tx
;
5726 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
5727 u32 mflcn
= IXGBE_READ_REG(hw
, IXGBE_MFLCN
);
5728 u32 fccfg
= IXGBE_READ_REG(hw
, IXGBE_FCCFG
);
5729 flow_rx
= !!(mflcn
& IXGBE_MFLCN_RFCE
);
5730 flow_tx
= !!(fccfg
& IXGBE_FCCFG_TFCE_802_3X
);
5732 u32 frctl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
5733 u32 rmcs
= IXGBE_READ_REG(hw
, IXGBE_RMCS
);
5734 flow_rx
= !!(frctl
& IXGBE_FCTRL_RFCE
);
5735 flow_tx
= !!(rmcs
& IXGBE_RMCS_TFCE_802_3X
);
5738 e_info(drv
, "NIC Link is Up %s, Flow Control: %s\n",
5739 (link_speed
== IXGBE_LINK_SPEED_10GB_FULL
?
5741 (link_speed
== IXGBE_LINK_SPEED_1GB_FULL
?
5742 "1 Gbps" : "unknown speed")),
5743 ((flow_rx
&& flow_tx
) ? "RX/TX" :
5745 (flow_tx
? "TX" : "None"))));
5747 netif_carrier_on(netdev
);
5749 /* Force detection of hung controller */
5750 adapter
->detect_tx_hung
= true;
5753 adapter
->link_up
= false;
5754 adapter
->link_speed
= 0;
5755 if (netif_carrier_ok(netdev
)) {
5756 e_info(drv
, "NIC Link is Down\n");
5757 netif_carrier_off(netdev
);
5761 if (!netif_carrier_ok(netdev
)) {
5762 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5763 tx_ring
= adapter
->tx_ring
[i
];
5764 if (tx_ring
->next_to_use
!= tx_ring
->next_to_clean
) {
5765 some_tx_pending
= 1;
5770 if (some_tx_pending
) {
5771 /* We've lost link, so the controller stops DMA,
5772 * but we've got queued Tx work that's never going
5773 * to get done, so reset controller to flush Tx.
5774 * (Do the reset outside of interrupt context).
5776 schedule_work(&adapter
->reset_task
);
5780 ixgbe_update_stats(adapter
);
5781 mutex_unlock(&ixgbe_watchdog_lock
);
5784 static int ixgbe_tso(struct ixgbe_adapter
*adapter
,
5785 struct ixgbe_ring
*tx_ring
, struct sk_buff
*skb
,
5786 u32 tx_flags
, u8
*hdr_len
)
5788 struct ixgbe_adv_tx_context_desc
*context_desc
;
5791 struct ixgbe_tx_buffer
*tx_buffer_info
;
5792 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
;
5793 u32 mss_l4len_idx
, l4len
;
5795 if (skb_is_gso(skb
)) {
5796 if (skb_header_cloned(skb
)) {
5797 err
= pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
);
5801 l4len
= tcp_hdrlen(skb
);
5804 if (skb
->protocol
== htons(ETH_P_IP
)) {
5805 struct iphdr
*iph
= ip_hdr(skb
);
5808 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
5812 } else if (skb_is_gso_v6(skb
)) {
5813 ipv6_hdr(skb
)->payload_len
= 0;
5814 tcp_hdr(skb
)->check
=
5815 ~csum_ipv6_magic(&ipv6_hdr(skb
)->saddr
,
5816 &ipv6_hdr(skb
)->daddr
,
5820 i
= tx_ring
->next_to_use
;
5822 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5823 context_desc
= IXGBE_TX_CTXTDESC_ADV(tx_ring
, i
);
5825 /* VLAN MACLEN IPLEN */
5826 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
5828 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
5829 vlan_macip_lens
|= ((skb_network_offset(skb
)) <<
5830 IXGBE_ADVTXD_MACLEN_SHIFT
);
5831 *hdr_len
+= skb_network_offset(skb
);
5833 (skb_transport_header(skb
) - skb_network_header(skb
));
5835 (skb_transport_header(skb
) - skb_network_header(skb
));
5836 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
5837 context_desc
->seqnum_seed
= 0;
5839 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5840 type_tucmd_mlhl
= (IXGBE_TXD_CMD_DEXT
|
5841 IXGBE_ADVTXD_DTYP_CTXT
);
5843 if (skb
->protocol
== htons(ETH_P_IP
))
5844 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_IPV4
;
5845 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
5846 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
5850 (skb_shinfo(skb
)->gso_size
<< IXGBE_ADVTXD_MSS_SHIFT
);
5851 mss_l4len_idx
|= (l4len
<< IXGBE_ADVTXD_L4LEN_SHIFT
);
5852 /* use index 1 for TSO */
5853 mss_l4len_idx
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
5854 context_desc
->mss_l4len_idx
= cpu_to_le32(mss_l4len_idx
);
5856 tx_buffer_info
->time_stamp
= jiffies
;
5857 tx_buffer_info
->next_to_watch
= i
;
5860 if (i
== tx_ring
->count
)
5862 tx_ring
->next_to_use
= i
;
5869 static bool ixgbe_tx_csum(struct ixgbe_adapter
*adapter
,
5870 struct ixgbe_ring
*tx_ring
,
5871 struct sk_buff
*skb
, u32 tx_flags
)
5873 struct ixgbe_adv_tx_context_desc
*context_desc
;
5875 struct ixgbe_tx_buffer
*tx_buffer_info
;
5876 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
= 0;
5878 if (skb
->ip_summed
== CHECKSUM_PARTIAL
||
5879 (tx_flags
& IXGBE_TX_FLAGS_VLAN
)) {
5880 i
= tx_ring
->next_to_use
;
5881 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5882 context_desc
= IXGBE_TX_CTXTDESC_ADV(tx_ring
, i
);
5884 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
5886 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
5887 vlan_macip_lens
|= (skb_network_offset(skb
) <<
5888 IXGBE_ADVTXD_MACLEN_SHIFT
);
5889 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
5890 vlan_macip_lens
|= (skb_transport_header(skb
) -
5891 skb_network_header(skb
));
5893 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
5894 context_desc
->seqnum_seed
= 0;
5896 type_tucmd_mlhl
|= (IXGBE_TXD_CMD_DEXT
|
5897 IXGBE_ADVTXD_DTYP_CTXT
);
5899 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5902 if (skb
->protocol
== cpu_to_be16(ETH_P_8021Q
)) {
5903 const struct vlan_ethhdr
*vhdr
=
5904 (const struct vlan_ethhdr
*)skb
->data
;
5906 protocol
= vhdr
->h_vlan_encapsulated_proto
;
5908 protocol
= skb
->protocol
;
5912 case cpu_to_be16(ETH_P_IP
):
5913 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_IPV4
;
5914 if (ip_hdr(skb
)->protocol
== IPPROTO_TCP
)
5916 IXGBE_ADVTXD_TUCMD_L4T_TCP
;
5917 else if (ip_hdr(skb
)->protocol
== IPPROTO_SCTP
)
5919 IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
5921 case cpu_to_be16(ETH_P_IPV6
):
5922 /* XXX what about other V6 headers?? */
5923 if (ipv6_hdr(skb
)->nexthdr
== IPPROTO_TCP
)
5925 IXGBE_ADVTXD_TUCMD_L4T_TCP
;
5926 else if (ipv6_hdr(skb
)->nexthdr
== IPPROTO_SCTP
)
5928 IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
5931 if (unlikely(net_ratelimit())) {
5932 e_warn(probe
, "partial checksum "
5940 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
5941 /* use index zero for tx checksum offload */
5942 context_desc
->mss_l4len_idx
= 0;
5944 tx_buffer_info
->time_stamp
= jiffies
;
5945 tx_buffer_info
->next_to_watch
= i
;
5948 if (i
== tx_ring
->count
)
5950 tx_ring
->next_to_use
= i
;
5958 static int ixgbe_tx_map(struct ixgbe_adapter
*adapter
,
5959 struct ixgbe_ring
*tx_ring
,
5960 struct sk_buff
*skb
, u32 tx_flags
,
5963 struct pci_dev
*pdev
= adapter
->pdev
;
5964 struct ixgbe_tx_buffer
*tx_buffer_info
;
5966 unsigned int total
= skb
->len
;
5967 unsigned int offset
= 0, size
, count
= 0, i
;
5968 unsigned int nr_frags
= skb_shinfo(skb
)->nr_frags
;
5971 i
= tx_ring
->next_to_use
;
5973 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
)
5974 /* excluding fcoe_crc_eof for FCoE */
5975 total
-= sizeof(struct fcoe_crc_eof
);
5977 len
= min(skb_headlen(skb
), total
);
5979 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5980 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
5982 tx_buffer_info
->length
= size
;
5983 tx_buffer_info
->mapped_as_page
= false;
5984 tx_buffer_info
->dma
= dma_map_single(&pdev
->dev
,
5986 size
, DMA_TO_DEVICE
);
5987 if (dma_mapping_error(&pdev
->dev
, tx_buffer_info
->dma
))
5989 tx_buffer_info
->time_stamp
= jiffies
;
5990 tx_buffer_info
->next_to_watch
= i
;
5999 if (i
== tx_ring
->count
)
6004 for (f
= 0; f
< nr_frags
; f
++) {
6005 struct skb_frag_struct
*frag
;
6007 frag
= &skb_shinfo(skb
)->frags
[f
];
6008 len
= min((unsigned int)frag
->size
, total
);
6009 offset
= frag
->page_offset
;
6013 if (i
== tx_ring
->count
)
6016 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6017 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
6019 tx_buffer_info
->length
= size
;
6020 tx_buffer_info
->dma
= dma_map_page(&adapter
->pdev
->dev
,
6024 tx_buffer_info
->mapped_as_page
= true;
6025 if (dma_mapping_error(&pdev
->dev
, tx_buffer_info
->dma
))
6027 tx_buffer_info
->time_stamp
= jiffies
;
6028 tx_buffer_info
->next_to_watch
= i
;
6039 tx_ring
->tx_buffer_info
[i
].skb
= skb
;
6040 tx_ring
->tx_buffer_info
[first
].next_to_watch
= i
;
6045 e_dev_err("TX DMA map failed\n");
6047 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6048 tx_buffer_info
->dma
= 0;
6049 tx_buffer_info
->time_stamp
= 0;
6050 tx_buffer_info
->next_to_watch
= 0;
6054 /* clear timestamp and dma mappings for remaining portion of packet */
6057 i
+= tx_ring
->count
;
6059 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6060 ixgbe_unmap_and_free_tx_resource(adapter
, tx_buffer_info
);
6066 static void ixgbe_tx_queue(struct ixgbe_adapter
*adapter
,
6067 struct ixgbe_ring
*tx_ring
,
6068 int tx_flags
, int count
, u32 paylen
, u8 hdr_len
)
6070 union ixgbe_adv_tx_desc
*tx_desc
= NULL
;
6071 struct ixgbe_tx_buffer
*tx_buffer_info
;
6072 u32 olinfo_status
= 0, cmd_type_len
= 0;
6074 u32 txd_cmd
= IXGBE_TXD_CMD_EOP
| IXGBE_TXD_CMD_RS
| IXGBE_TXD_CMD_IFCS
;
6076 cmd_type_len
|= IXGBE_ADVTXD_DTYP_DATA
;
6078 cmd_type_len
|= IXGBE_ADVTXD_DCMD_IFCS
| IXGBE_ADVTXD_DCMD_DEXT
;
6080 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
6081 cmd_type_len
|= IXGBE_ADVTXD_DCMD_VLE
;
6083 if (tx_flags
& IXGBE_TX_FLAGS_TSO
) {
6084 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
6086 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
6087 IXGBE_ADVTXD_POPTS_SHIFT
;
6089 /* use index 1 context for tso */
6090 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
6091 if (tx_flags
& IXGBE_TX_FLAGS_IPV4
)
6092 olinfo_status
|= IXGBE_TXD_POPTS_IXSM
<<
6093 IXGBE_ADVTXD_POPTS_SHIFT
;
6095 } else if (tx_flags
& IXGBE_TX_FLAGS_CSUM
)
6096 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
6097 IXGBE_ADVTXD_POPTS_SHIFT
;
6099 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
6100 olinfo_status
|= IXGBE_ADVTXD_CC
;
6101 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
6102 if (tx_flags
& IXGBE_TX_FLAGS_FSO
)
6103 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
6106 olinfo_status
|= ((paylen
- hdr_len
) << IXGBE_ADVTXD_PAYLEN_SHIFT
);
6108 i
= tx_ring
->next_to_use
;
6110 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6111 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, i
);
6112 tx_desc
->read
.buffer_addr
= cpu_to_le64(tx_buffer_info
->dma
);
6113 tx_desc
->read
.cmd_type_len
=
6114 cpu_to_le32(cmd_type_len
| tx_buffer_info
->length
);
6115 tx_desc
->read
.olinfo_status
= cpu_to_le32(olinfo_status
);
6117 if (i
== tx_ring
->count
)
6121 tx_desc
->read
.cmd_type_len
|= cpu_to_le32(txd_cmd
);
6124 * Force memory writes to complete before letting h/w
6125 * know there are new descriptors to fetch. (Only
6126 * applicable for weak-ordered memory model archs,
6131 tx_ring
->next_to_use
= i
;
6132 writel(i
, adapter
->hw
.hw_addr
+ tx_ring
->tail
);
6135 static void ixgbe_atr(struct ixgbe_adapter
*adapter
, struct sk_buff
*skb
,
6136 int queue
, u32 tx_flags
)
6138 struct ixgbe_atr_input atr_input
;
6140 struct iphdr
*iph
= ip_hdr(skb
);
6141 struct ethhdr
*eth
= (struct ethhdr
*)skb
->data
;
6142 u16 vlan_id
, src_port
, dst_port
, flex_bytes
;
6143 u32 src_ipv4_addr
, dst_ipv4_addr
;
6146 /* Right now, we support IPv4 only */
6147 if (skb
->protocol
!= htons(ETH_P_IP
))
6149 /* check if we're UDP or TCP */
6150 if (iph
->protocol
== IPPROTO_TCP
) {
6152 src_port
= th
->source
;
6153 dst_port
= th
->dest
;
6154 l4type
|= IXGBE_ATR_L4TYPE_TCP
;
6155 /* l4type IPv4 type is 0, no need to assign */
6157 /* Unsupported L4 header, just bail here */
6161 memset(&atr_input
, 0, sizeof(struct ixgbe_atr_input
));
6163 vlan_id
= (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
) >>
6164 IXGBE_TX_FLAGS_VLAN_SHIFT
;
6165 src_ipv4_addr
= iph
->saddr
;
6166 dst_ipv4_addr
= iph
->daddr
;
6167 flex_bytes
= eth
->h_proto
;
6169 ixgbe_atr_set_vlan_id_82599(&atr_input
, vlan_id
);
6170 ixgbe_atr_set_src_port_82599(&atr_input
, dst_port
);
6171 ixgbe_atr_set_dst_port_82599(&atr_input
, src_port
);
6172 ixgbe_atr_set_flex_byte_82599(&atr_input
, flex_bytes
);
6173 ixgbe_atr_set_l4type_82599(&atr_input
, l4type
);
6174 /* src and dst are inverted, think how the receiver sees them */
6175 ixgbe_atr_set_src_ipv4_82599(&atr_input
, dst_ipv4_addr
);
6176 ixgbe_atr_set_dst_ipv4_82599(&atr_input
, src_ipv4_addr
);
6178 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6179 ixgbe_fdir_add_signature_filter_82599(&adapter
->hw
, &atr_input
, queue
);
6182 static int __ixgbe_maybe_stop_tx(struct net_device
*netdev
,
6183 struct ixgbe_ring
*tx_ring
, int size
)
6185 netif_stop_subqueue(netdev
, tx_ring
->queue_index
);
6186 /* Herbert's original patch had:
6187 * smp_mb__after_netif_stop_queue();
6188 * but since that doesn't exist yet, just open code it. */
6191 /* We need to check again in a case another CPU has just
6192 * made room available. */
6193 if (likely(IXGBE_DESC_UNUSED(tx_ring
) < size
))
6196 /* A reprieve! - use start_queue because it doesn't call schedule */
6197 netif_start_subqueue(netdev
, tx_ring
->queue_index
);
6198 ++tx_ring
->restart_queue
;
6202 static int ixgbe_maybe_stop_tx(struct net_device
*netdev
,
6203 struct ixgbe_ring
*tx_ring
, int size
)
6205 if (likely(IXGBE_DESC_UNUSED(tx_ring
) >= size
))
6207 return __ixgbe_maybe_stop_tx(netdev
, tx_ring
, size
);
6210 static u16
ixgbe_select_queue(struct net_device
*dev
, struct sk_buff
*skb
)
6212 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6213 int txq
= smp_processor_id();
6216 if ((skb
->protocol
== htons(ETH_P_FCOE
)) ||
6217 (skb
->protocol
== htons(ETH_P_FIP
))) {
6218 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
6219 txq
&= (adapter
->ring_feature
[RING_F_FCOE
].indices
- 1);
6220 txq
+= adapter
->ring_feature
[RING_F_FCOE
].mask
;
6222 #ifdef CONFIG_IXGBE_DCB
6223 } else if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6224 txq
= adapter
->fcoe
.up
;
6231 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
6232 while (unlikely(txq
>= dev
->real_num_tx_queues
))
6233 txq
-= dev
->real_num_tx_queues
;
6237 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6238 if (skb
->priority
== TC_PRIO_CONTROL
)
6239 txq
= adapter
->ring_feature
[RING_F_DCB
].indices
-1;
6241 txq
= (skb
->vlan_tci
& IXGBE_TX_FLAGS_VLAN_PRIO_MASK
)
6246 return skb_tx_hash(dev
, skb
);
6249 netdev_tx_t
ixgbe_xmit_frame_ring(struct sk_buff
*skb
, struct net_device
*netdev
,
6250 struct ixgbe_adapter
*adapter
,
6251 struct ixgbe_ring
*tx_ring
)
6253 struct netdev_queue
*txq
;
6255 unsigned int tx_flags
= 0;
6261 if (adapter
->vlgrp
&& vlan_tx_tag_present(skb
)) {
6262 tx_flags
|= vlan_tx_tag_get(skb
);
6263 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6264 tx_flags
&= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK
;
6265 tx_flags
|= ((skb
->queue_mapping
& 0x7) << 13);
6267 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
6268 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
6269 } else if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
&&
6270 skb
->priority
!= TC_PRIO_CONTROL
) {
6271 tx_flags
|= ((skb
->queue_mapping
& 0x7) << 13);
6272 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
6273 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
6277 /* for FCoE with DCB, we force the priority to what
6278 * was specified by the switch */
6279 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
&&
6280 (skb
->protocol
== htons(ETH_P_FCOE
) ||
6281 skb
->protocol
== htons(ETH_P_FIP
))) {
6282 #ifdef CONFIG_IXGBE_DCB
6283 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6284 tx_flags
&= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6285 << IXGBE_TX_FLAGS_VLAN_SHIFT
);
6286 tx_flags
|= ((adapter
->fcoe
.up
<< 13)
6287 << IXGBE_TX_FLAGS_VLAN_SHIFT
);
6290 /* flag for FCoE offloads */
6291 if (skb
->protocol
== htons(ETH_P_FCOE
))
6292 tx_flags
|= IXGBE_TX_FLAGS_FCOE
;
6296 /* four things can cause us to need a context descriptor */
6297 if (skb_is_gso(skb
) ||
6298 (skb
->ip_summed
== CHECKSUM_PARTIAL
) ||
6299 (tx_flags
& IXGBE_TX_FLAGS_VLAN
) ||
6300 (tx_flags
& IXGBE_TX_FLAGS_FCOE
))
6303 count
+= TXD_USE_COUNT(skb_headlen(skb
));
6304 for (f
= 0; f
< skb_shinfo(skb
)->nr_frags
; f
++)
6305 count
+= TXD_USE_COUNT(skb_shinfo(skb
)->frags
[f
].size
);
6307 if (ixgbe_maybe_stop_tx(netdev
, tx_ring
, count
)) {
6309 return NETDEV_TX_BUSY
;
6312 first
= tx_ring
->next_to_use
;
6313 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
6315 /* setup tx offload for FCoE */
6316 tso
= ixgbe_fso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
);
6318 dev_kfree_skb_any(skb
);
6319 return NETDEV_TX_OK
;
6322 tx_flags
|= IXGBE_TX_FLAGS_FSO
;
6323 #endif /* IXGBE_FCOE */
6325 if (skb
->protocol
== htons(ETH_P_IP
))
6326 tx_flags
|= IXGBE_TX_FLAGS_IPV4
;
6327 tso
= ixgbe_tso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
);
6329 dev_kfree_skb_any(skb
);
6330 return NETDEV_TX_OK
;
6334 tx_flags
|= IXGBE_TX_FLAGS_TSO
;
6335 else if (ixgbe_tx_csum(adapter
, tx_ring
, skb
, tx_flags
) &&
6336 (skb
->ip_summed
== CHECKSUM_PARTIAL
))
6337 tx_flags
|= IXGBE_TX_FLAGS_CSUM
;
6340 count
= ixgbe_tx_map(adapter
, tx_ring
, skb
, tx_flags
, first
);
6342 /* add the ATR filter if ATR is on */
6343 if (tx_ring
->atr_sample_rate
) {
6344 ++tx_ring
->atr_count
;
6345 if ((tx_ring
->atr_count
>= tx_ring
->atr_sample_rate
) &&
6346 test_bit(__IXGBE_FDIR_INIT_DONE
,
6347 &tx_ring
->reinit_state
)) {
6348 ixgbe_atr(adapter
, skb
, tx_ring
->queue_index
,
6350 tx_ring
->atr_count
= 0;
6353 txq
= netdev_get_tx_queue(netdev
, tx_ring
->queue_index
);
6354 txq
->tx_bytes
+= skb
->len
;
6356 ixgbe_tx_queue(adapter
, tx_ring
, tx_flags
, count
, skb
->len
,
6358 ixgbe_maybe_stop_tx(netdev
, tx_ring
, DESC_NEEDED
);
6361 dev_kfree_skb_any(skb
);
6362 tx_ring
->tx_buffer_info
[first
].time_stamp
= 0;
6363 tx_ring
->next_to_use
= first
;
6366 return NETDEV_TX_OK
;
6369 static netdev_tx_t
ixgbe_xmit_frame(struct sk_buff
*skb
, struct net_device
*netdev
)
6371 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6372 struct ixgbe_ring
*tx_ring
;
6374 tx_ring
= adapter
->tx_ring
[skb
->queue_mapping
];
6375 return ixgbe_xmit_frame_ring(skb
, netdev
, adapter
, tx_ring
);
6379 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6380 * @netdev: network interface device structure
6381 * @p: pointer to an address structure
6383 * Returns 0 on success, negative on failure
6385 static int ixgbe_set_mac(struct net_device
*netdev
, void *p
)
6387 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6388 struct ixgbe_hw
*hw
= &adapter
->hw
;
6389 struct sockaddr
*addr
= p
;
6391 if (!is_valid_ether_addr(addr
->sa_data
))
6392 return -EADDRNOTAVAIL
;
6394 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
6395 memcpy(hw
->mac
.addr
, addr
->sa_data
, netdev
->addr_len
);
6397 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
6404 ixgbe_mdio_read(struct net_device
*netdev
, int prtad
, int devad
, u16 addr
)
6406 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6407 struct ixgbe_hw
*hw
= &adapter
->hw
;
6411 if (prtad
!= hw
->phy
.mdio
.prtad
)
6413 rc
= hw
->phy
.ops
.read_reg(hw
, addr
, devad
, &value
);
6419 static int ixgbe_mdio_write(struct net_device
*netdev
, int prtad
, int devad
,
6420 u16 addr
, u16 value
)
6422 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6423 struct ixgbe_hw
*hw
= &adapter
->hw
;
6425 if (prtad
!= hw
->phy
.mdio
.prtad
)
6427 return hw
->phy
.ops
.write_reg(hw
, addr
, devad
, value
);
6430 static int ixgbe_ioctl(struct net_device
*netdev
, struct ifreq
*req
, int cmd
)
6432 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6434 return mdio_mii_ioctl(&adapter
->hw
.phy
.mdio
, if_mii(req
), cmd
);
6438 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6440 * @netdev: network interface device structure
6442 * Returns non-zero on failure
6444 static int ixgbe_add_sanmac_netdev(struct net_device
*dev
)
6447 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6448 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
6450 if (is_valid_ether_addr(mac
->san_addr
)) {
6452 err
= dev_addr_add(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
6459 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6461 * @netdev: network interface device structure
6463 * Returns non-zero on failure
6465 static int ixgbe_del_sanmac_netdev(struct net_device
*dev
)
6468 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6469 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
6471 if (is_valid_ether_addr(mac
->san_addr
)) {
6473 err
= dev_addr_del(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
6479 #ifdef CONFIG_NET_POLL_CONTROLLER
6481 * Polling 'interrupt' - used by things like netconsole to send skbs
6482 * without having to re-enable interrupts. It's not called while
6483 * the interrupt routine is executing.
6485 static void ixgbe_netpoll(struct net_device
*netdev
)
6487 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6490 /* if interface is down do nothing */
6491 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
6494 adapter
->flags
|= IXGBE_FLAG_IN_NETPOLL
;
6495 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
6496 int num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
6497 for (i
= 0; i
< num_q_vectors
; i
++) {
6498 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
6499 ixgbe_msix_clean_many(0, q_vector
);
6502 ixgbe_intr(adapter
->pdev
->irq
, netdev
);
6504 adapter
->flags
&= ~IXGBE_FLAG_IN_NETPOLL
;
6508 static const struct net_device_ops ixgbe_netdev_ops
= {
6509 .ndo_open
= ixgbe_open
,
6510 .ndo_stop
= ixgbe_close
,
6511 .ndo_start_xmit
= ixgbe_xmit_frame
,
6512 .ndo_select_queue
= ixgbe_select_queue
,
6513 .ndo_set_rx_mode
= ixgbe_set_rx_mode
,
6514 .ndo_set_multicast_list
= ixgbe_set_rx_mode
,
6515 .ndo_validate_addr
= eth_validate_addr
,
6516 .ndo_set_mac_address
= ixgbe_set_mac
,
6517 .ndo_change_mtu
= ixgbe_change_mtu
,
6518 .ndo_tx_timeout
= ixgbe_tx_timeout
,
6519 .ndo_vlan_rx_register
= ixgbe_vlan_rx_register
,
6520 .ndo_vlan_rx_add_vid
= ixgbe_vlan_rx_add_vid
,
6521 .ndo_vlan_rx_kill_vid
= ixgbe_vlan_rx_kill_vid
,
6522 .ndo_do_ioctl
= ixgbe_ioctl
,
6523 .ndo_set_vf_mac
= ixgbe_ndo_set_vf_mac
,
6524 .ndo_set_vf_vlan
= ixgbe_ndo_set_vf_vlan
,
6525 .ndo_set_vf_tx_rate
= ixgbe_ndo_set_vf_bw
,
6526 .ndo_get_vf_config
= ixgbe_ndo_get_vf_config
,
6527 #ifdef CONFIG_NET_POLL_CONTROLLER
6528 .ndo_poll_controller
= ixgbe_netpoll
,
6531 .ndo_fcoe_ddp_setup
= ixgbe_fcoe_ddp_get
,
6532 .ndo_fcoe_ddp_done
= ixgbe_fcoe_ddp_put
,
6533 .ndo_fcoe_enable
= ixgbe_fcoe_enable
,
6534 .ndo_fcoe_disable
= ixgbe_fcoe_disable
,
6535 .ndo_fcoe_get_wwn
= ixgbe_fcoe_get_wwn
,
6536 #endif /* IXGBE_FCOE */
6539 static void __devinit
ixgbe_probe_vf(struct ixgbe_adapter
*adapter
,
6540 const struct ixgbe_info
*ii
)
6542 #ifdef CONFIG_PCI_IOV
6543 struct ixgbe_hw
*hw
= &adapter
->hw
;
6546 if (hw
->mac
.type
!= ixgbe_mac_82599EB
|| !max_vfs
)
6549 /* The 82599 supports up to 64 VFs per physical function
6550 * but this implementation limits allocation to 63 so that
6551 * basic networking resources are still available to the
6554 adapter
->num_vfs
= (max_vfs
> 63) ? 63 : max_vfs
;
6555 adapter
->flags
|= IXGBE_FLAG_SRIOV_ENABLED
;
6556 err
= pci_enable_sriov(adapter
->pdev
, adapter
->num_vfs
);
6558 e_err(probe
, "Failed to enable PCI sriov: %d\n", err
);
6561 /* If call to enable VFs succeeded then allocate memory
6562 * for per VF control structures.
6565 kcalloc(adapter
->num_vfs
,
6566 sizeof(struct vf_data_storage
), GFP_KERNEL
);
6567 if (adapter
->vfinfo
) {
6568 /* Now that we're sure SR-IOV is enabled
6569 * and memory allocated set up the mailbox parameters
6571 ixgbe_init_mbx_params_pf(hw
);
6572 memcpy(&hw
->mbx
.ops
, ii
->mbx_ops
,
6573 sizeof(hw
->mbx
.ops
));
6575 /* Disable RSC when in SR-IOV mode */
6576 adapter
->flags2
&= ~(IXGBE_FLAG2_RSC_CAPABLE
|
6577 IXGBE_FLAG2_RSC_ENABLED
);
6582 e_err(probe
, "Unable to allocate memory for VF Data Storage - "
6583 "SRIOV disabled\n");
6584 pci_disable_sriov(adapter
->pdev
);
6587 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
6588 adapter
->num_vfs
= 0;
6589 #endif /* CONFIG_PCI_IOV */
6593 * ixgbe_probe - Device Initialization Routine
6594 * @pdev: PCI device information struct
6595 * @ent: entry in ixgbe_pci_tbl
6597 * Returns 0 on success, negative on failure
6599 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6600 * The OS initialization, configuring of the adapter private structure,
6601 * and a hardware reset occur.
6603 static int __devinit
ixgbe_probe(struct pci_dev
*pdev
,
6604 const struct pci_device_id
*ent
)
6606 struct net_device
*netdev
;
6607 struct ixgbe_adapter
*adapter
= NULL
;
6608 struct ixgbe_hw
*hw
;
6609 const struct ixgbe_info
*ii
= ixgbe_info_tbl
[ent
->driver_data
];
6610 static int cards_found
;
6611 int i
, err
, pci_using_dac
;
6612 unsigned int indices
= num_possible_cpus();
6618 /* Catch broken hardware that put the wrong VF device ID in
6619 * the PCIe SR-IOV capability.
6621 if (pdev
->is_virtfn
) {
6622 WARN(1, KERN_ERR
"%s (%hx:%hx) should not be a VF!\n",
6623 pci_name(pdev
), pdev
->vendor
, pdev
->device
);
6627 err
= pci_enable_device_mem(pdev
);
6631 if (!dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(64)) &&
6632 !dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(64))) {
6635 err
= dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(32));
6637 err
= dma_set_coherent_mask(&pdev
->dev
,
6641 "No usable DMA configuration, aborting\n");
6648 err
= pci_request_selected_regions(pdev
, pci_select_bars(pdev
,
6649 IORESOURCE_MEM
), ixgbe_driver_name
);
6652 "pci_request_selected_regions failed 0x%x\n", err
);
6656 pci_enable_pcie_error_reporting(pdev
);
6658 pci_set_master(pdev
);
6659 pci_save_state(pdev
);
6661 if (ii
->mac
== ixgbe_mac_82598EB
)
6662 indices
= min_t(unsigned int, indices
, IXGBE_MAX_RSS_INDICES
);
6664 indices
= min_t(unsigned int, indices
, IXGBE_MAX_FDIR_INDICES
);
6666 indices
= max_t(unsigned int, indices
, IXGBE_MAX_DCB_INDICES
);
6668 indices
+= min_t(unsigned int, num_possible_cpus(),
6669 IXGBE_MAX_FCOE_INDICES
);
6671 netdev
= alloc_etherdev_mq(sizeof(struct ixgbe_adapter
), indices
);
6674 goto err_alloc_etherdev
;
6677 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
6679 pci_set_drvdata(pdev
, netdev
);
6680 adapter
= netdev_priv(netdev
);
6682 adapter
->netdev
= netdev
;
6683 adapter
->pdev
= pdev
;
6686 adapter
->msg_enable
= (1 << DEFAULT_DEBUG_LEVEL_SHIFT
) - 1;
6688 hw
->hw_addr
= ioremap(pci_resource_start(pdev
, 0),
6689 pci_resource_len(pdev
, 0));
6695 for (i
= 1; i
<= 5; i
++) {
6696 if (pci_resource_len(pdev
, i
) == 0)
6700 netdev
->netdev_ops
= &ixgbe_netdev_ops
;
6701 ixgbe_set_ethtool_ops(netdev
);
6702 netdev
->watchdog_timeo
= 5 * HZ
;
6703 strcpy(netdev
->name
, pci_name(pdev
));
6705 adapter
->bd_number
= cards_found
;
6708 memcpy(&hw
->mac
.ops
, ii
->mac_ops
, sizeof(hw
->mac
.ops
));
6709 hw
->mac
.type
= ii
->mac
;
6712 memcpy(&hw
->eeprom
.ops
, ii
->eeprom_ops
, sizeof(hw
->eeprom
.ops
));
6713 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
6714 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6715 if (!(eec
& (1 << 8)))
6716 hw
->eeprom
.ops
.read
= &ixgbe_read_eeprom_bit_bang_generic
;
6719 memcpy(&hw
->phy
.ops
, ii
->phy_ops
, sizeof(hw
->phy
.ops
));
6720 hw
->phy
.sfp_type
= ixgbe_sfp_type_unknown
;
6721 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6722 hw
->phy
.mdio
.prtad
= MDIO_PRTAD_NONE
;
6723 hw
->phy
.mdio
.mmds
= 0;
6724 hw
->phy
.mdio
.mode_support
= MDIO_SUPPORTS_C45
| MDIO_EMULATE_C22
;
6725 hw
->phy
.mdio
.dev
= netdev
;
6726 hw
->phy
.mdio
.mdio_read
= ixgbe_mdio_read
;
6727 hw
->phy
.mdio
.mdio_write
= ixgbe_mdio_write
;
6729 /* set up this timer and work struct before calling get_invariants
6730 * which might start the timer
6732 init_timer(&adapter
->sfp_timer
);
6733 adapter
->sfp_timer
.function
= &ixgbe_sfp_timer
;
6734 adapter
->sfp_timer
.data
= (unsigned long) adapter
;
6736 INIT_WORK(&adapter
->sfp_task
, ixgbe_sfp_task
);
6738 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6739 INIT_WORK(&adapter
->multispeed_fiber_task
, ixgbe_multispeed_fiber_task
);
6741 /* a new SFP+ module arrival, called from GPI SDP2 context */
6742 INIT_WORK(&adapter
->sfp_config_module_task
,
6743 ixgbe_sfp_config_module_task
);
6745 ii
->get_invariants(hw
);
6747 /* setup the private structure */
6748 err
= ixgbe_sw_init(adapter
);
6752 /* Make it possible the adapter to be woken up via WOL */
6753 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
6754 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
6757 * If there is a fan on this device and it has failed log the
6760 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
6761 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
6762 if (esdp
& IXGBE_ESDP_SDP1
)
6763 e_crit(probe
, "Fan has stopped, replace the adapter\n");
6766 /* reset_hw fills in the perm_addr as well */
6767 hw
->phy
.reset_if_overtemp
= true;
6768 err
= hw
->mac
.ops
.reset_hw(hw
);
6769 hw
->phy
.reset_if_overtemp
= false;
6770 if (err
== IXGBE_ERR_SFP_NOT_PRESENT
&&
6771 hw
->mac
.type
== ixgbe_mac_82598EB
) {
6773 * Start a kernel thread to watch for a module to arrive.
6774 * Only do this for 82598, since 82599 will generate
6775 * interrupts on module arrival.
6777 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
6778 mod_timer(&adapter
->sfp_timer
,
6779 round_jiffies(jiffies
+ (2 * HZ
)));
6781 } else if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
6782 e_dev_err("failed to initialize because an unsupported SFP+ "
6783 "module type was detected.\n");
6784 e_dev_err("Reload the driver after installing a supported "
6788 e_dev_err("HW Init failed: %d\n", err
);
6792 ixgbe_probe_vf(adapter
, ii
);
6794 netdev
->features
= NETIF_F_SG
|
6796 NETIF_F_HW_VLAN_TX
|
6797 NETIF_F_HW_VLAN_RX
|
6798 NETIF_F_HW_VLAN_FILTER
;
6800 netdev
->features
|= NETIF_F_IPV6_CSUM
;
6801 netdev
->features
|= NETIF_F_TSO
;
6802 netdev
->features
|= NETIF_F_TSO6
;
6803 netdev
->features
|= NETIF_F_GRO
;
6805 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
6806 netdev
->features
|= NETIF_F_SCTP_CSUM
;
6808 netdev
->vlan_features
|= NETIF_F_TSO
;
6809 netdev
->vlan_features
|= NETIF_F_TSO6
;
6810 netdev
->vlan_features
|= NETIF_F_IP_CSUM
;
6811 netdev
->vlan_features
|= NETIF_F_IPV6_CSUM
;
6812 netdev
->vlan_features
|= NETIF_F_SG
;
6814 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
6815 adapter
->flags
&= ~(IXGBE_FLAG_RSS_ENABLED
|
6816 IXGBE_FLAG_DCB_ENABLED
);
6817 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)
6818 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
6820 #ifdef CONFIG_IXGBE_DCB
6821 netdev
->dcbnl_ops
= &dcbnl_ops
;
6825 if (adapter
->flags
& IXGBE_FLAG_FCOE_CAPABLE
) {
6826 if (hw
->mac
.ops
.get_device_caps
) {
6827 hw
->mac
.ops
.get_device_caps(hw
, &device_caps
);
6828 if (device_caps
& IXGBE_DEVICE_CAPS_FCOE_OFFLOADS
)
6829 adapter
->flags
&= ~IXGBE_FLAG_FCOE_CAPABLE
;
6832 if (adapter
->flags
& IXGBE_FLAG_FCOE_CAPABLE
) {
6833 netdev
->vlan_features
|= NETIF_F_FCOE_CRC
;
6834 netdev
->vlan_features
|= NETIF_F_FSO
;
6835 netdev
->vlan_features
|= NETIF_F_FCOE_MTU
;
6837 #endif /* IXGBE_FCOE */
6839 netdev
->features
|= NETIF_F_HIGHDMA
;
6841 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
)
6842 netdev
->features
|= NETIF_F_LRO
;
6844 /* make sure the EEPROM is good */
6845 if (hw
->eeprom
.ops
.validate_checksum(hw
, NULL
) < 0) {
6846 e_dev_err("The EEPROM Checksum Is Not Valid\n");
6851 memcpy(netdev
->dev_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
6852 memcpy(netdev
->perm_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
6854 if (ixgbe_validate_mac_addr(netdev
->perm_addr
)) {
6855 e_dev_err("invalid MAC address\n");
6860 /* power down the optics */
6861 if (hw
->phy
.multispeed_fiber
)
6862 hw
->mac
.ops
.disable_tx_laser(hw
);
6864 init_timer(&adapter
->watchdog_timer
);
6865 adapter
->watchdog_timer
.function
= &ixgbe_watchdog
;
6866 adapter
->watchdog_timer
.data
= (unsigned long)adapter
;
6868 INIT_WORK(&adapter
->reset_task
, ixgbe_reset_task
);
6869 INIT_WORK(&adapter
->watchdog_task
, ixgbe_watchdog_task
);
6871 err
= ixgbe_init_interrupt_scheme(adapter
);
6875 switch (pdev
->device
) {
6876 case IXGBE_DEV_ID_82599_KX4
:
6877 adapter
->wol
= (IXGBE_WUFC_MAG
| IXGBE_WUFC_EX
|
6878 IXGBE_WUFC_MC
| IXGBE_WUFC_BC
);
6884 device_set_wakeup_enable(&adapter
->pdev
->dev
, adapter
->wol
);
6886 /* pick up the PCI bus settings for reporting later */
6887 hw
->mac
.ops
.get_bus_info(hw
);
6889 /* print bus type/speed/width info */
6890 e_dev_info("(PCI Express:%s:%s) %pM\n",
6891 ((hw
->bus
.speed
== ixgbe_bus_speed_5000
) ? "5.0Gb/s":
6892 (hw
->bus
.speed
== ixgbe_bus_speed_2500
) ? "2.5Gb/s":"Unknown"),
6893 ((hw
->bus
.width
== ixgbe_bus_width_pcie_x8
) ? "Width x8" :
6894 (hw
->bus
.width
== ixgbe_bus_width_pcie_x4
) ? "Width x4" :
6895 (hw
->bus
.width
== ixgbe_bus_width_pcie_x1
) ? "Width x1" :
6898 ixgbe_read_pba_num_generic(hw
, &part_num
);
6899 if (ixgbe_is_sfp(hw
) && hw
->phy
.sfp_type
!= ixgbe_sfp_type_not_present
)
6900 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
6901 "PBA No: %06x-%03x\n",
6902 hw
->mac
.type
, hw
->phy
.type
, hw
->phy
.sfp_type
,
6903 (part_num
>> 8), (part_num
& 0xff));
6905 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6906 hw
->mac
.type
, hw
->phy
.type
,
6907 (part_num
>> 8), (part_num
& 0xff));
6909 if (hw
->bus
.width
<= ixgbe_bus_width_pcie_x4
) {
6910 e_dev_warn("PCI-Express bandwidth available for this card is "
6911 "not sufficient for optimal performance.\n");
6912 e_dev_warn("For optimal performance a x8 PCI-Express slot "
6916 /* save off EEPROM version number */
6917 hw
->eeprom
.ops
.read(hw
, 0x29, &adapter
->eeprom_version
);
6919 /* reset the hardware with the new settings */
6920 err
= hw
->mac
.ops
.start_hw(hw
);
6922 if (err
== IXGBE_ERR_EEPROM_VERSION
) {
6923 /* We are running on a pre-production device, log a warning */
6924 e_dev_warn("This device is a pre-production adapter/LOM. "
6925 "Please be aware there may be issues associated "
6926 "with your hardware. If you are experiencing "
6927 "problems please contact your Intel or hardware "
6928 "representative who provided you with this "
6931 strcpy(netdev
->name
, "eth%d");
6932 err
= register_netdev(netdev
);
6936 /* carrier off reporting is important to ethtool even BEFORE open */
6937 netif_carrier_off(netdev
);
6939 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
6940 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
6941 INIT_WORK(&adapter
->fdir_reinit_task
, ixgbe_fdir_reinit_task
);
6943 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
)
6944 INIT_WORK(&adapter
->check_overtemp_task
, ixgbe_check_overtemp_task
);
6945 #ifdef CONFIG_IXGBE_DCA
6946 if (dca_add_requester(&pdev
->dev
) == 0) {
6947 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
6948 ixgbe_setup_dca(adapter
);
6951 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
6952 e_info(probe
, "IOV is enabled with %d VFs\n", adapter
->num_vfs
);
6953 for (i
= 0; i
< adapter
->num_vfs
; i
++)
6954 ixgbe_vf_configuration(pdev
, (i
| 0x10000000));
6957 /* add san mac addr to netdev */
6958 ixgbe_add_sanmac_netdev(netdev
);
6960 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
6965 ixgbe_release_hw_control(adapter
);
6966 ixgbe_clear_interrupt_scheme(adapter
);
6969 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
6970 ixgbe_disable_sriov(adapter
);
6971 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
6972 del_timer_sync(&adapter
->sfp_timer
);
6973 cancel_work_sync(&adapter
->sfp_task
);
6974 cancel_work_sync(&adapter
->multispeed_fiber_task
);
6975 cancel_work_sync(&adapter
->sfp_config_module_task
);
6976 iounmap(hw
->hw_addr
);
6978 free_netdev(netdev
);
6980 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
6984 pci_disable_device(pdev
);
6989 * ixgbe_remove - Device Removal Routine
6990 * @pdev: PCI device information struct
6992 * ixgbe_remove is called by the PCI subsystem to alert the driver
6993 * that it should release a PCI device. The could be caused by a
6994 * Hot-Plug event, or because the driver is going to be removed from
6997 static void __devexit
ixgbe_remove(struct pci_dev
*pdev
)
6999 struct net_device
*netdev
= pci_get_drvdata(pdev
);
7000 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
7002 set_bit(__IXGBE_DOWN
, &adapter
->state
);
7003 /* clear the module not found bit to make sure the worker won't
7006 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
7007 del_timer_sync(&adapter
->watchdog_timer
);
7009 del_timer_sync(&adapter
->sfp_timer
);
7010 cancel_work_sync(&adapter
->watchdog_task
);
7011 cancel_work_sync(&adapter
->sfp_task
);
7012 cancel_work_sync(&adapter
->multispeed_fiber_task
);
7013 cancel_work_sync(&adapter
->sfp_config_module_task
);
7014 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
7015 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
7016 cancel_work_sync(&adapter
->fdir_reinit_task
);
7017 flush_scheduled_work();
7019 #ifdef CONFIG_IXGBE_DCA
7020 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
7021 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
7022 dca_remove_requester(&pdev
->dev
);
7023 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
7028 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
7029 ixgbe_cleanup_fcoe(adapter
);
7031 #endif /* IXGBE_FCOE */
7033 /* remove the added san mac */
7034 ixgbe_del_sanmac_netdev(netdev
);
7036 if (netdev
->reg_state
== NETREG_REGISTERED
)
7037 unregister_netdev(netdev
);
7039 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
7040 ixgbe_disable_sriov(adapter
);
7042 ixgbe_clear_interrupt_scheme(adapter
);
7044 ixgbe_release_hw_control(adapter
);
7046 iounmap(adapter
->hw
.hw_addr
);
7047 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
7050 e_dev_info("complete\n");
7052 free_netdev(netdev
);
7054 pci_disable_pcie_error_reporting(pdev
);
7056 pci_disable_device(pdev
);
7060 * ixgbe_io_error_detected - called when PCI error is detected
7061 * @pdev: Pointer to PCI device
7062 * @state: The current pci connection state
7064 * This function is called after a PCI bus error affecting
7065 * this device has been detected.
7067 static pci_ers_result_t
ixgbe_io_error_detected(struct pci_dev
*pdev
,
7068 pci_channel_state_t state
)
7070 struct net_device
*netdev
= pci_get_drvdata(pdev
);
7071 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
7073 netif_device_detach(netdev
);
7075 if (state
== pci_channel_io_perm_failure
)
7076 return PCI_ERS_RESULT_DISCONNECT
;
7078 if (netif_running(netdev
))
7079 ixgbe_down(adapter
);
7080 pci_disable_device(pdev
);
7082 /* Request a slot reset. */
7083 return PCI_ERS_RESULT_NEED_RESET
;
7087 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7088 * @pdev: Pointer to PCI device
7090 * Restart the card from scratch, as if from a cold-boot.
7092 static pci_ers_result_t
ixgbe_io_slot_reset(struct pci_dev
*pdev
)
7094 struct net_device
*netdev
= pci_get_drvdata(pdev
);
7095 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
7096 pci_ers_result_t result
;
7099 if (pci_enable_device_mem(pdev
)) {
7100 e_err(probe
, "Cannot re-enable PCI device after reset.\n");
7101 result
= PCI_ERS_RESULT_DISCONNECT
;
7103 pci_set_master(pdev
);
7104 pci_restore_state(pdev
);
7105 pci_save_state(pdev
);
7107 pci_wake_from_d3(pdev
, false);
7109 ixgbe_reset(adapter
);
7110 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
7111 result
= PCI_ERS_RESULT_RECOVERED
;
7114 err
= pci_cleanup_aer_uncorrect_error_status(pdev
);
7116 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7117 "failed 0x%0x\n", err
);
7118 /* non-fatal, continue */
7125 * ixgbe_io_resume - called when traffic can start flowing again.
7126 * @pdev: Pointer to PCI device
7128 * This callback is called when the error recovery driver tells us that
7129 * its OK to resume normal operation.
7131 static void ixgbe_io_resume(struct pci_dev
*pdev
)
7133 struct net_device
*netdev
= pci_get_drvdata(pdev
);
7134 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
7136 if (netif_running(netdev
)) {
7137 if (ixgbe_up(adapter
)) {
7138 e_info(probe
, "ixgbe_up failed after reset\n");
7143 netif_device_attach(netdev
);
7146 static struct pci_error_handlers ixgbe_err_handler
= {
7147 .error_detected
= ixgbe_io_error_detected
,
7148 .slot_reset
= ixgbe_io_slot_reset
,
7149 .resume
= ixgbe_io_resume
,
7152 static struct pci_driver ixgbe_driver
= {
7153 .name
= ixgbe_driver_name
,
7154 .id_table
= ixgbe_pci_tbl
,
7155 .probe
= ixgbe_probe
,
7156 .remove
= __devexit_p(ixgbe_remove
),
7158 .suspend
= ixgbe_suspend
,
7159 .resume
= ixgbe_resume
,
7161 .shutdown
= ixgbe_shutdown
,
7162 .err_handler
= &ixgbe_err_handler
7166 * ixgbe_init_module - Driver Registration Routine
7168 * ixgbe_init_module is the first routine called when the driver is
7169 * loaded. All it does is register with the PCI subsystem.
7171 static int __init
ixgbe_init_module(void)
7174 pr_info("%s - version %s\n", ixgbe_driver_string
,
7175 ixgbe_driver_version
);
7176 pr_info("%s\n", ixgbe_copyright
);
7178 #ifdef CONFIG_IXGBE_DCA
7179 dca_register_notify(&dca_notifier
);
7182 ret
= pci_register_driver(&ixgbe_driver
);
7186 module_init(ixgbe_init_module
);
7189 * ixgbe_exit_module - Driver Exit Cleanup Routine
7191 * ixgbe_exit_module is called just before the driver is removed
7194 static void __exit
ixgbe_exit_module(void)
7196 #ifdef CONFIG_IXGBE_DCA
7197 dca_unregister_notify(&dca_notifier
);
7199 pci_unregister_driver(&ixgbe_driver
);
7202 #ifdef CONFIG_IXGBE_DCA
7203 static int ixgbe_notify_dca(struct notifier_block
*nb
, unsigned long event
,
7208 ret_val
= driver_for_each_device(&ixgbe_driver
.driver
, NULL
, &event
,
7209 __ixgbe_notify_dca
);
7211 return ret_val
? NOTIFY_BAD
: NOTIFY_DONE
;
7214 #endif /* CONFIG_IXGBE_DCA */
7217 * ixgbe_get_hw_dev return device
7218 * used by hardware layer to print debugging information
7220 struct net_device
*ixgbe_get_hw_dev(struct ixgbe_hw
*hw
)
7222 struct ixgbe_adapter
*adapter
= hw
->back
;
7223 return adapter
->netdev
;
7226 module_exit(ixgbe_exit_module
);