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ixgbe: DCB, implement capabilities flags
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <linux/slab.h>
40 #include <net/checksum.h>
41 #include <net/ip6_checksum.h>
42 #include <linux/ethtool.h>
43 #include <linux/if_vlan.h>
44 #include <scsi/fc/fc_fcoe.h>
45
46 #include "ixgbe.h"
47 #include "ixgbe_common.h"
48 #include "ixgbe_dcb_82599.h"
49 #include "ixgbe_sriov.h"
50
51 char ixgbe_driver_name[] = "ixgbe";
52 static const char ixgbe_driver_string[] =
53 "Intel(R) 10 Gigabit PCI Express Network Driver";
54
55 #define DRV_VERSION "3.2.9-k2"
56 const char ixgbe_driver_version[] = DRV_VERSION;
57 static const char ixgbe_copyright[] =
58 "Copyright (c) 1999-2011 Intel Corporation.";
59
60 static const struct ixgbe_info *ixgbe_info_tbl[] = {
61 [board_82598] = &ixgbe_82598_info,
62 [board_82599] = &ixgbe_82599_info,
63 [board_X540] = &ixgbe_X540_info,
64 };
65
66 /* ixgbe_pci_tbl - PCI Device ID Table
67 *
68 * Wildcard entries (PCI_ANY_ID) should come last
69 * Last entry must be all 0s
70 *
71 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
72 * Class, Class Mask, private data (not used) }
73 */
74 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
76 board_82598 },
77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
78 board_82598 },
79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
80 board_82598 },
81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
82 board_82598 },
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
84 board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
86 board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
88 board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
90 board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
92 board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
94 board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
96 board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
98 board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
100 board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
102 board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
104 board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
106 board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
108 board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
110 board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
112 board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
114 board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
116 board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
118 board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
120 board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
122 board_X540 },
123
124 /* required last entry */
125 {0, }
126 };
127 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
128
129 #ifdef CONFIG_IXGBE_DCA
130 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
131 void *p);
132 static struct notifier_block dca_notifier = {
133 .notifier_call = ixgbe_notify_dca,
134 .next = NULL,
135 .priority = 0
136 };
137 #endif
138
139 #ifdef CONFIG_PCI_IOV
140 static unsigned int max_vfs;
141 module_param(max_vfs, uint, 0);
142 MODULE_PARM_DESC(max_vfs,
143 "Maximum number of virtual functions to allocate per physical function");
144 #endif /* CONFIG_PCI_IOV */
145
146 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
147 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
148 MODULE_LICENSE("GPL");
149 MODULE_VERSION(DRV_VERSION);
150
151 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
152
153 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
154 {
155 struct ixgbe_hw *hw = &adapter->hw;
156 u32 gcr;
157 u32 gpie;
158 u32 vmdctl;
159
160 #ifdef CONFIG_PCI_IOV
161 /* disable iov and allow time for transactions to clear */
162 pci_disable_sriov(adapter->pdev);
163 #endif
164
165 /* turn off device IOV mode */
166 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
167 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
168 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
169 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
170 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
171 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
172
173 /* set default pool back to 0 */
174 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
175 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
176 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
177
178 /* take a breather then clean up driver data */
179 msleep(100);
180
181 kfree(adapter->vfinfo);
182 adapter->vfinfo = NULL;
183
184 adapter->num_vfs = 0;
185 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
186 }
187
188 struct ixgbe_reg_info {
189 u32 ofs;
190 char *name;
191 };
192
193 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
194
195 /* General Registers */
196 {IXGBE_CTRL, "CTRL"},
197 {IXGBE_STATUS, "STATUS"},
198 {IXGBE_CTRL_EXT, "CTRL_EXT"},
199
200 /* Interrupt Registers */
201 {IXGBE_EICR, "EICR"},
202
203 /* RX Registers */
204 {IXGBE_SRRCTL(0), "SRRCTL"},
205 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
206 {IXGBE_RDLEN(0), "RDLEN"},
207 {IXGBE_RDH(0), "RDH"},
208 {IXGBE_RDT(0), "RDT"},
209 {IXGBE_RXDCTL(0), "RXDCTL"},
210 {IXGBE_RDBAL(0), "RDBAL"},
211 {IXGBE_RDBAH(0), "RDBAH"},
212
213 /* TX Registers */
214 {IXGBE_TDBAL(0), "TDBAL"},
215 {IXGBE_TDBAH(0), "TDBAH"},
216 {IXGBE_TDLEN(0), "TDLEN"},
217 {IXGBE_TDH(0), "TDH"},
218 {IXGBE_TDT(0), "TDT"},
219 {IXGBE_TXDCTL(0), "TXDCTL"},
220
221 /* List Terminator */
222 {}
223 };
224
225
226 /*
227 * ixgbe_regdump - register printout routine
228 */
229 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
230 {
231 int i = 0, j = 0;
232 char rname[16];
233 u32 regs[64];
234
235 switch (reginfo->ofs) {
236 case IXGBE_SRRCTL(0):
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
239 break;
240 case IXGBE_DCA_RXCTRL(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
243 break;
244 case IXGBE_RDLEN(0):
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
247 break;
248 case IXGBE_RDH(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
251 break;
252 case IXGBE_RDT(0):
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
255 break;
256 case IXGBE_RXDCTL(0):
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
259 break;
260 case IXGBE_RDBAL(0):
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
263 break;
264 case IXGBE_RDBAH(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
267 break;
268 case IXGBE_TDBAL(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
271 break;
272 case IXGBE_TDBAH(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
275 break;
276 case IXGBE_TDLEN(0):
277 for (i = 0; i < 64; i++)
278 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
279 break;
280 case IXGBE_TDH(0):
281 for (i = 0; i < 64; i++)
282 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
283 break;
284 case IXGBE_TDT(0):
285 for (i = 0; i < 64; i++)
286 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
287 break;
288 case IXGBE_TXDCTL(0):
289 for (i = 0; i < 64; i++)
290 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
291 break;
292 default:
293 pr_info("%-15s %08x\n", reginfo->name,
294 IXGBE_READ_REG(hw, reginfo->ofs));
295 return;
296 }
297
298 for (i = 0; i < 8; i++) {
299 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
300 pr_err("%-15s", rname);
301 for (j = 0; j < 8; j++)
302 pr_cont(" %08x", regs[i*8+j]);
303 pr_cont("\n");
304 }
305
306 }
307
308 /*
309 * ixgbe_dump - Print registers, tx-rings and rx-rings
310 */
311 static void ixgbe_dump(struct ixgbe_adapter *adapter)
312 {
313 struct net_device *netdev = adapter->netdev;
314 struct ixgbe_hw *hw = &adapter->hw;
315 struct ixgbe_reg_info *reginfo;
316 int n = 0;
317 struct ixgbe_ring *tx_ring;
318 struct ixgbe_tx_buffer *tx_buffer_info;
319 union ixgbe_adv_tx_desc *tx_desc;
320 struct my_u0 { u64 a; u64 b; } *u0;
321 struct ixgbe_ring *rx_ring;
322 union ixgbe_adv_rx_desc *rx_desc;
323 struct ixgbe_rx_buffer *rx_buffer_info;
324 u32 staterr;
325 int i = 0;
326
327 if (!netif_msg_hw(adapter))
328 return;
329
330 /* Print netdevice Info */
331 if (netdev) {
332 dev_info(&adapter->pdev->dev, "Net device Info\n");
333 pr_info("Device Name state "
334 "trans_start last_rx\n");
335 pr_info("%-15s %016lX %016lX %016lX\n",
336 netdev->name,
337 netdev->state,
338 netdev->trans_start,
339 netdev->last_rx);
340 }
341
342 /* Print Registers */
343 dev_info(&adapter->pdev->dev, "Register Dump\n");
344 pr_info(" Register Name Value\n");
345 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
346 reginfo->name; reginfo++) {
347 ixgbe_regdump(hw, reginfo);
348 }
349
350 /* Print TX Ring Summary */
351 if (!netdev || !netif_running(netdev))
352 goto exit;
353
354 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
355 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
356 for (n = 0; n < adapter->num_tx_queues; n++) {
357 tx_ring = adapter->tx_ring[n];
358 tx_buffer_info =
359 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
360 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
361 n, tx_ring->next_to_use, tx_ring->next_to_clean,
362 (u64)tx_buffer_info->dma,
363 tx_buffer_info->length,
364 tx_buffer_info->next_to_watch,
365 (u64)tx_buffer_info->time_stamp);
366 }
367
368 /* Print TX Rings */
369 if (!netif_msg_tx_done(adapter))
370 goto rx_ring_summary;
371
372 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
373
374 /* Transmit Descriptor Formats
375 *
376 * Advanced Transmit Descriptor
377 * +--------------------------------------------------------------+
378 * 0 | Buffer Address [63:0] |
379 * +--------------------------------------------------------------+
380 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
381 * +--------------------------------------------------------------+
382 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
383 */
384
385 for (n = 0; n < adapter->num_tx_queues; n++) {
386 tx_ring = adapter->tx_ring[n];
387 pr_info("------------------------------------\n");
388 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
389 pr_info("------------------------------------\n");
390 pr_info("T [desc] [address 63:0 ] "
391 "[PlPOIdStDDt Ln] [bi->dma ] "
392 "leng ntw timestamp bi->skb\n");
393
394 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
395 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
396 tx_buffer_info = &tx_ring->tx_buffer_info[i];
397 u0 = (struct my_u0 *)tx_desc;
398 pr_info("T [0x%03X] %016llX %016llX %016llX"
399 " %04X %3X %016llX %p", i,
400 le64_to_cpu(u0->a),
401 le64_to_cpu(u0->b),
402 (u64)tx_buffer_info->dma,
403 tx_buffer_info->length,
404 tx_buffer_info->next_to_watch,
405 (u64)tx_buffer_info->time_stamp,
406 tx_buffer_info->skb);
407 if (i == tx_ring->next_to_use &&
408 i == tx_ring->next_to_clean)
409 pr_cont(" NTC/U\n");
410 else if (i == tx_ring->next_to_use)
411 pr_cont(" NTU\n");
412 else if (i == tx_ring->next_to_clean)
413 pr_cont(" NTC\n");
414 else
415 pr_cont("\n");
416
417 if (netif_msg_pktdata(adapter) &&
418 tx_buffer_info->dma != 0)
419 print_hex_dump(KERN_INFO, "",
420 DUMP_PREFIX_ADDRESS, 16, 1,
421 phys_to_virt(tx_buffer_info->dma),
422 tx_buffer_info->length, true);
423 }
424 }
425
426 /* Print RX Rings Summary */
427 rx_ring_summary:
428 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
429 pr_info("Queue [NTU] [NTC]\n");
430 for (n = 0; n < adapter->num_rx_queues; n++) {
431 rx_ring = adapter->rx_ring[n];
432 pr_info("%5d %5X %5X\n",
433 n, rx_ring->next_to_use, rx_ring->next_to_clean);
434 }
435
436 /* Print RX Rings */
437 if (!netif_msg_rx_status(adapter))
438 goto exit;
439
440 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
441
442 /* Advanced Receive Descriptor (Read) Format
443 * 63 1 0
444 * +-----------------------------------------------------+
445 * 0 | Packet Buffer Address [63:1] |A0/NSE|
446 * +----------------------------------------------+------+
447 * 8 | Header Buffer Address [63:1] | DD |
448 * +-----------------------------------------------------+
449 *
450 *
451 * Advanced Receive Descriptor (Write-Back) Format
452 *
453 * 63 48 47 32 31 30 21 20 16 15 4 3 0
454 * +------------------------------------------------------+
455 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
456 * | Checksum Ident | | | | Type | Type |
457 * +------------------------------------------------------+
458 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
459 * +------------------------------------------------------+
460 * 63 48 47 32 31 20 19 0
461 */
462 for (n = 0; n < adapter->num_rx_queues; n++) {
463 rx_ring = adapter->rx_ring[n];
464 pr_info("------------------------------------\n");
465 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
466 pr_info("------------------------------------\n");
467 pr_info("R [desc] [ PktBuf A0] "
468 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
469 "<-- Adv Rx Read format\n");
470 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
471 "[vl er S cks ln] ---------------- [bi->skb] "
472 "<-- Adv Rx Write-Back format\n");
473
474 for (i = 0; i < rx_ring->count; i++) {
475 rx_buffer_info = &rx_ring->rx_buffer_info[i];
476 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
477 u0 = (struct my_u0 *)rx_desc;
478 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
479 if (staterr & IXGBE_RXD_STAT_DD) {
480 /* Descriptor Done */
481 pr_info("RWB[0x%03X] %016llX "
482 "%016llX ---------------- %p", i,
483 le64_to_cpu(u0->a),
484 le64_to_cpu(u0->b),
485 rx_buffer_info->skb);
486 } else {
487 pr_info("R [0x%03X] %016llX "
488 "%016llX %016llX %p", i,
489 le64_to_cpu(u0->a),
490 le64_to_cpu(u0->b),
491 (u64)rx_buffer_info->dma,
492 rx_buffer_info->skb);
493
494 if (netif_msg_pktdata(adapter)) {
495 print_hex_dump(KERN_INFO, "",
496 DUMP_PREFIX_ADDRESS, 16, 1,
497 phys_to_virt(rx_buffer_info->dma),
498 rx_ring->rx_buf_len, true);
499
500 if (rx_ring->rx_buf_len
501 < IXGBE_RXBUFFER_2048)
502 print_hex_dump(KERN_INFO, "",
503 DUMP_PREFIX_ADDRESS, 16, 1,
504 phys_to_virt(
505 rx_buffer_info->page_dma +
506 rx_buffer_info->page_offset
507 ),
508 PAGE_SIZE/2, true);
509 }
510 }
511
512 if (i == rx_ring->next_to_use)
513 pr_cont(" NTU\n");
514 else if (i == rx_ring->next_to_clean)
515 pr_cont(" NTC\n");
516 else
517 pr_cont("\n");
518
519 }
520 }
521
522 exit:
523 return;
524 }
525
526 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
527 {
528 u32 ctrl_ext;
529
530 /* Let firmware take over control of h/w */
531 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
532 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
533 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
534 }
535
536 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
537 {
538 u32 ctrl_ext;
539
540 /* Let firmware know the driver has taken over */
541 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
542 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
543 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
544 }
545
546 /*
547 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
548 * @adapter: pointer to adapter struct
549 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
550 * @queue: queue to map the corresponding interrupt to
551 * @msix_vector: the vector to map to the corresponding queue
552 *
553 */
554 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
555 u8 queue, u8 msix_vector)
556 {
557 u32 ivar, index;
558 struct ixgbe_hw *hw = &adapter->hw;
559 switch (hw->mac.type) {
560 case ixgbe_mac_82598EB:
561 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
562 if (direction == -1)
563 direction = 0;
564 index = (((direction * 64) + queue) >> 2) & 0x1F;
565 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
566 ivar &= ~(0xFF << (8 * (queue & 0x3)));
567 ivar |= (msix_vector << (8 * (queue & 0x3)));
568 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
569 break;
570 case ixgbe_mac_82599EB:
571 case ixgbe_mac_X540:
572 if (direction == -1) {
573 /* other causes */
574 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
575 index = ((queue & 1) * 8);
576 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
577 ivar &= ~(0xFF << index);
578 ivar |= (msix_vector << index);
579 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
580 break;
581 } else {
582 /* tx or rx causes */
583 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
584 index = ((16 * (queue & 1)) + (8 * direction));
585 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
586 ivar &= ~(0xFF << index);
587 ivar |= (msix_vector << index);
588 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
589 break;
590 }
591 default:
592 break;
593 }
594 }
595
596 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
597 u64 qmask)
598 {
599 u32 mask;
600
601 switch (adapter->hw.mac.type) {
602 case ixgbe_mac_82598EB:
603 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
604 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
605 break;
606 case ixgbe_mac_82599EB:
607 case ixgbe_mac_X540:
608 mask = (qmask & 0xFFFFFFFF);
609 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
610 mask = (qmask >> 32);
611 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
612 break;
613 default:
614 break;
615 }
616 }
617
618 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
619 struct ixgbe_tx_buffer *tx_buffer_info)
620 {
621 if (tx_buffer_info->dma) {
622 if (tx_buffer_info->mapped_as_page)
623 dma_unmap_page(tx_ring->dev,
624 tx_buffer_info->dma,
625 tx_buffer_info->length,
626 DMA_TO_DEVICE);
627 else
628 dma_unmap_single(tx_ring->dev,
629 tx_buffer_info->dma,
630 tx_buffer_info->length,
631 DMA_TO_DEVICE);
632 tx_buffer_info->dma = 0;
633 }
634 if (tx_buffer_info->skb) {
635 dev_kfree_skb_any(tx_buffer_info->skb);
636 tx_buffer_info->skb = NULL;
637 }
638 tx_buffer_info->time_stamp = 0;
639 /* tx_buffer_info must be completely set up in the transmit path */
640 }
641
642 /**
643 * ixgbe_dcb_txq_to_tc - convert a reg index to a traffic class
644 * @adapter: driver private struct
645 * @index: reg idx of queue to query (0-127)
646 *
647 * Helper function to determine the traffic index for a paticular
648 * register index.
649 *
650 * Returns : a tc index for use in range 0-7, or 0-3
651 */
652 static u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx)
653 {
654 int tc = -1;
655 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
656
657 /* if DCB is not enabled the queues have no TC */
658 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
659 return tc;
660
661 /* check valid range */
662 if (reg_idx >= adapter->hw.mac.max_tx_queues)
663 return tc;
664
665 switch (adapter->hw.mac.type) {
666 case ixgbe_mac_82598EB:
667 tc = reg_idx >> 2;
668 break;
669 default:
670 if (dcb_i != 4 && dcb_i != 8)
671 break;
672
673 /* if VMDq is enabled the lowest order bits determine TC */
674 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
675 IXGBE_FLAG_VMDQ_ENABLED)) {
676 tc = reg_idx & (dcb_i - 1);
677 break;
678 }
679
680 /*
681 * Convert the reg_idx into the correct TC. This bitmask
682 * targets the last full 32 ring traffic class and assigns
683 * it a value of 1. From there the rest of the rings are
684 * based on shifting the mask further up to include the
685 * reg_idx / 16 and then reg_idx / 8. It assumes dcB_i
686 * will only ever be 8 or 4 and that reg_idx will never
687 * be greater then 128. The code without the power of 2
688 * optimizations would be:
689 * (((reg_idx % 32) + 32) * dcb_i) >> (9 - reg_idx / 32)
690 */
691 tc = ((reg_idx & 0X1F) + 0x20) * dcb_i;
692 tc >>= 9 - (reg_idx >> 5);
693 }
694
695 return tc;
696 }
697
698 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
699 {
700 struct ixgbe_hw *hw = &adapter->hw;
701 struct ixgbe_hw_stats *hwstats = &adapter->stats;
702 u32 data = 0;
703 u32 xoff[8] = {0};
704 int i;
705
706 if ((hw->fc.current_mode == ixgbe_fc_full) ||
707 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
708 switch (hw->mac.type) {
709 case ixgbe_mac_82598EB:
710 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
711 break;
712 default:
713 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
714 }
715 hwstats->lxoffrxc += data;
716
717 /* refill credits (no tx hang) if we received xoff */
718 if (!data)
719 return;
720
721 for (i = 0; i < adapter->num_tx_queues; i++)
722 clear_bit(__IXGBE_HANG_CHECK_ARMED,
723 &adapter->tx_ring[i]->state);
724 return;
725 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
726 return;
727
728 /* update stats for each tc, only valid with PFC enabled */
729 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
730 switch (hw->mac.type) {
731 case ixgbe_mac_82598EB:
732 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
733 break;
734 default:
735 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
736 }
737 hwstats->pxoffrxc[i] += xoff[i];
738 }
739
740 /* disarm tx queues that have received xoff frames */
741 for (i = 0; i < adapter->num_tx_queues; i++) {
742 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
743 u32 tc = ixgbe_dcb_txq_to_tc(adapter, tx_ring->reg_idx);
744
745 if (xoff[tc])
746 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
747 }
748 }
749
750 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
751 {
752 return ring->tx_stats.completed;
753 }
754
755 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
756 {
757 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
758 struct ixgbe_hw *hw = &adapter->hw;
759
760 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
761 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
762
763 if (head != tail)
764 return (head < tail) ?
765 tail - head : (tail + ring->count - head);
766
767 return 0;
768 }
769
770 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
771 {
772 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
773 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
774 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
775 bool ret = false;
776
777 clear_check_for_tx_hang(tx_ring);
778
779 /*
780 * Check for a hung queue, but be thorough. This verifies
781 * that a transmit has been completed since the previous
782 * check AND there is at least one packet pending. The
783 * ARMED bit is set to indicate a potential hang. The
784 * bit is cleared if a pause frame is received to remove
785 * false hang detection due to PFC or 802.3x frames. By
786 * requiring this to fail twice we avoid races with
787 * pfc clearing the ARMED bit and conditions where we
788 * run the check_tx_hang logic with a transmit completion
789 * pending but without time to complete it yet.
790 */
791 if ((tx_done_old == tx_done) && tx_pending) {
792 /* make sure it is true for two checks in a row */
793 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
794 &tx_ring->state);
795 } else {
796 /* update completed stats and continue */
797 tx_ring->tx_stats.tx_done_old = tx_done;
798 /* reset the countdown */
799 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
800 }
801
802 return ret;
803 }
804
805 #define IXGBE_MAX_TXD_PWR 14
806 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
807
808 /* Tx Descriptors needed, worst case */
809 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
810 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
811 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
812 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
813
814 static void ixgbe_tx_timeout(struct net_device *netdev);
815
816 /**
817 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
818 * @q_vector: structure containing interrupt and ring information
819 * @tx_ring: tx ring to clean
820 **/
821 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
822 struct ixgbe_ring *tx_ring)
823 {
824 struct ixgbe_adapter *adapter = q_vector->adapter;
825 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
826 struct ixgbe_tx_buffer *tx_buffer_info;
827 unsigned int total_bytes = 0, total_packets = 0;
828 u16 i, eop, count = 0;
829
830 i = tx_ring->next_to_clean;
831 eop = tx_ring->tx_buffer_info[i].next_to_watch;
832 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
833
834 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
835 (count < tx_ring->work_limit)) {
836 bool cleaned = false;
837 rmb(); /* read buffer_info after eop_desc */
838 for ( ; !cleaned; count++) {
839 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
840 tx_buffer_info = &tx_ring->tx_buffer_info[i];
841
842 tx_desc->wb.status = 0;
843 cleaned = (i == eop);
844
845 i++;
846 if (i == tx_ring->count)
847 i = 0;
848
849 if (cleaned && tx_buffer_info->skb) {
850 total_bytes += tx_buffer_info->bytecount;
851 total_packets += tx_buffer_info->gso_segs;
852 }
853
854 ixgbe_unmap_and_free_tx_resource(tx_ring,
855 tx_buffer_info);
856 }
857
858 tx_ring->tx_stats.completed++;
859 eop = tx_ring->tx_buffer_info[i].next_to_watch;
860 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
861 }
862
863 tx_ring->next_to_clean = i;
864 tx_ring->total_bytes += total_bytes;
865 tx_ring->total_packets += total_packets;
866 u64_stats_update_begin(&tx_ring->syncp);
867 tx_ring->stats.packets += total_packets;
868 tx_ring->stats.bytes += total_bytes;
869 u64_stats_update_end(&tx_ring->syncp);
870
871 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
872 /* schedule immediate reset if we believe we hung */
873 struct ixgbe_hw *hw = &adapter->hw;
874 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
875 e_err(drv, "Detected Tx Unit Hang\n"
876 " Tx Queue <%d>\n"
877 " TDH, TDT <%x>, <%x>\n"
878 " next_to_use <%x>\n"
879 " next_to_clean <%x>\n"
880 "tx_buffer_info[next_to_clean]\n"
881 " time_stamp <%lx>\n"
882 " jiffies <%lx>\n",
883 tx_ring->queue_index,
884 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
885 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
886 tx_ring->next_to_use, eop,
887 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
888
889 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
890
891 e_info(probe,
892 "tx hang %d detected on queue %d, resetting adapter\n",
893 adapter->tx_timeout_count + 1, tx_ring->queue_index);
894
895 /* schedule immediate reset if we believe we hung */
896 ixgbe_tx_timeout(adapter->netdev);
897
898 /* the adapter is about to reset, no point in enabling stuff */
899 return true;
900 }
901
902 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
903 if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
904 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
905 /* Make sure that anybody stopping the queue after this
906 * sees the new next_to_clean.
907 */
908 smp_mb();
909 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
910 !test_bit(__IXGBE_DOWN, &adapter->state)) {
911 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
912 ++tx_ring->tx_stats.restart_queue;
913 }
914 }
915
916 return count < tx_ring->work_limit;
917 }
918
919 #ifdef CONFIG_IXGBE_DCA
920 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
921 struct ixgbe_ring *rx_ring,
922 int cpu)
923 {
924 struct ixgbe_hw *hw = &adapter->hw;
925 u32 rxctrl;
926 u8 reg_idx = rx_ring->reg_idx;
927
928 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
929 switch (hw->mac.type) {
930 case ixgbe_mac_82598EB:
931 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
932 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
933 break;
934 case ixgbe_mac_82599EB:
935 case ixgbe_mac_X540:
936 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
937 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
938 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
939 break;
940 default:
941 break;
942 }
943 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
944 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
945 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
946 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
947 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
948 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
949 }
950
951 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
952 struct ixgbe_ring *tx_ring,
953 int cpu)
954 {
955 struct ixgbe_hw *hw = &adapter->hw;
956 u32 txctrl;
957 u8 reg_idx = tx_ring->reg_idx;
958
959 switch (hw->mac.type) {
960 case ixgbe_mac_82598EB:
961 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
962 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
963 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
964 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
965 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
966 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
967 break;
968 case ixgbe_mac_82599EB:
969 case ixgbe_mac_X540:
970 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
971 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
972 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
973 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
974 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
975 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
976 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
977 break;
978 default:
979 break;
980 }
981 }
982
983 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
984 {
985 struct ixgbe_adapter *adapter = q_vector->adapter;
986 int cpu = get_cpu();
987 long r_idx;
988 int i;
989
990 if (q_vector->cpu == cpu)
991 goto out_no_update;
992
993 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
994 for (i = 0; i < q_vector->txr_count; i++) {
995 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
996 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
997 r_idx + 1);
998 }
999
1000 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1001 for (i = 0; i < q_vector->rxr_count; i++) {
1002 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
1003 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1004 r_idx + 1);
1005 }
1006
1007 q_vector->cpu = cpu;
1008 out_no_update:
1009 put_cpu();
1010 }
1011
1012 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1013 {
1014 int num_q_vectors;
1015 int i;
1016
1017 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1018 return;
1019
1020 /* always use CB2 mode, difference is masked in the CB driver */
1021 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1022
1023 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1024 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1025 else
1026 num_q_vectors = 1;
1027
1028 for (i = 0; i < num_q_vectors; i++) {
1029 adapter->q_vector[i]->cpu = -1;
1030 ixgbe_update_dca(adapter->q_vector[i]);
1031 }
1032 }
1033
1034 static int __ixgbe_notify_dca(struct device *dev, void *data)
1035 {
1036 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1037 unsigned long event = *(unsigned long *)data;
1038
1039 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1040 return 0;
1041
1042 switch (event) {
1043 case DCA_PROVIDER_ADD:
1044 /* if we're already enabled, don't do it again */
1045 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1046 break;
1047 if (dca_add_requester(dev) == 0) {
1048 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1049 ixgbe_setup_dca(adapter);
1050 break;
1051 }
1052 /* Fall Through since DCA is disabled. */
1053 case DCA_PROVIDER_REMOVE:
1054 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1055 dca_remove_requester(dev);
1056 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1057 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1058 }
1059 break;
1060 }
1061
1062 return 0;
1063 }
1064
1065 #endif /* CONFIG_IXGBE_DCA */
1066 /**
1067 * ixgbe_receive_skb - Send a completed packet up the stack
1068 * @adapter: board private structure
1069 * @skb: packet to send up
1070 * @status: hardware indication of status of receive
1071 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1072 * @rx_desc: rx descriptor
1073 **/
1074 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1075 struct sk_buff *skb, u8 status,
1076 struct ixgbe_ring *ring,
1077 union ixgbe_adv_rx_desc *rx_desc)
1078 {
1079 struct ixgbe_adapter *adapter = q_vector->adapter;
1080 struct napi_struct *napi = &q_vector->napi;
1081 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1082 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1083
1084 if (is_vlan && (tag & VLAN_VID_MASK))
1085 __vlan_hwaccel_put_tag(skb, tag);
1086
1087 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1088 napi_gro_receive(napi, skb);
1089 else
1090 netif_rx(skb);
1091 }
1092
1093 /**
1094 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1095 * @adapter: address of board private structure
1096 * @status_err: hardware indication of status of receive
1097 * @skb: skb currently being received and modified
1098 **/
1099 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1100 union ixgbe_adv_rx_desc *rx_desc,
1101 struct sk_buff *skb)
1102 {
1103 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
1104
1105 skb_checksum_none_assert(skb);
1106
1107 /* Rx csum disabled */
1108 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1109 return;
1110
1111 /* if IP and error */
1112 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1113 (status_err & IXGBE_RXDADV_ERR_IPE)) {
1114 adapter->hw_csum_rx_error++;
1115 return;
1116 }
1117
1118 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1119 return;
1120
1121 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1122 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1123
1124 /*
1125 * 82599 errata, UDP frames with a 0 checksum can be marked as
1126 * checksum errors.
1127 */
1128 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1129 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1130 return;
1131
1132 adapter->hw_csum_rx_error++;
1133 return;
1134 }
1135
1136 /* It must be a TCP or UDP packet with a valid checksum */
1137 skb->ip_summed = CHECKSUM_UNNECESSARY;
1138 }
1139
1140 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1141 {
1142 /*
1143 * Force memory writes to complete before letting h/w
1144 * know there are new descriptors to fetch. (Only
1145 * applicable for weak-ordered memory model archs,
1146 * such as IA-64).
1147 */
1148 wmb();
1149 writel(val, rx_ring->tail);
1150 }
1151
1152 /**
1153 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1154 * @rx_ring: ring to place buffers on
1155 * @cleaned_count: number of buffers to replace
1156 **/
1157 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1158 {
1159 union ixgbe_adv_rx_desc *rx_desc;
1160 struct ixgbe_rx_buffer *bi;
1161 struct sk_buff *skb;
1162 u16 i = rx_ring->next_to_use;
1163
1164 /* do nothing if no valid netdev defined */
1165 if (!rx_ring->netdev)
1166 return;
1167
1168 while (cleaned_count--) {
1169 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1170 bi = &rx_ring->rx_buffer_info[i];
1171 skb = bi->skb;
1172
1173 if (!skb) {
1174 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1175 rx_ring->rx_buf_len);
1176 if (!skb) {
1177 rx_ring->rx_stats.alloc_rx_buff_failed++;
1178 goto no_buffers;
1179 }
1180 /* initialize queue mapping */
1181 skb_record_rx_queue(skb, rx_ring->queue_index);
1182 bi->skb = skb;
1183 }
1184
1185 if (!bi->dma) {
1186 bi->dma = dma_map_single(rx_ring->dev,
1187 skb->data,
1188 rx_ring->rx_buf_len,
1189 DMA_FROM_DEVICE);
1190 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1191 rx_ring->rx_stats.alloc_rx_buff_failed++;
1192 bi->dma = 0;
1193 goto no_buffers;
1194 }
1195 }
1196
1197 if (ring_is_ps_enabled(rx_ring)) {
1198 if (!bi->page) {
1199 bi->page = netdev_alloc_page(rx_ring->netdev);
1200 if (!bi->page) {
1201 rx_ring->rx_stats.alloc_rx_page_failed++;
1202 goto no_buffers;
1203 }
1204 }
1205
1206 if (!bi->page_dma) {
1207 /* use a half page if we're re-using */
1208 bi->page_offset ^= PAGE_SIZE / 2;
1209 bi->page_dma = dma_map_page(rx_ring->dev,
1210 bi->page,
1211 bi->page_offset,
1212 PAGE_SIZE / 2,
1213 DMA_FROM_DEVICE);
1214 if (dma_mapping_error(rx_ring->dev,
1215 bi->page_dma)) {
1216 rx_ring->rx_stats.alloc_rx_page_failed++;
1217 bi->page_dma = 0;
1218 goto no_buffers;
1219 }
1220 }
1221
1222 /* Refresh the desc even if buffer_addrs didn't change
1223 * because each write-back erases this info. */
1224 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1225 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1226 } else {
1227 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1228 rx_desc->read.hdr_addr = 0;
1229 }
1230
1231 i++;
1232 if (i == rx_ring->count)
1233 i = 0;
1234 }
1235
1236 no_buffers:
1237 if (rx_ring->next_to_use != i) {
1238 rx_ring->next_to_use = i;
1239 ixgbe_release_rx_desc(rx_ring, i);
1240 }
1241 }
1242
1243 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1244 {
1245 /* HW will not DMA in data larger than the given buffer, even if it
1246 * parses the (NFS, of course) header to be larger. In that case, it
1247 * fills the header buffer and spills the rest into the page.
1248 */
1249 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1250 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1251 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1252 if (hlen > IXGBE_RX_HDR_SIZE)
1253 hlen = IXGBE_RX_HDR_SIZE;
1254 return hlen;
1255 }
1256
1257 /**
1258 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1259 * @skb: pointer to the last skb in the rsc queue
1260 *
1261 * This function changes a queue full of hw rsc buffers into a completed
1262 * packet. It uses the ->prev pointers to find the first packet and then
1263 * turns it into the frag list owner.
1264 **/
1265 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1266 {
1267 unsigned int frag_list_size = 0;
1268 unsigned int skb_cnt = 1;
1269
1270 while (skb->prev) {
1271 struct sk_buff *prev = skb->prev;
1272 frag_list_size += skb->len;
1273 skb->prev = NULL;
1274 skb = prev;
1275 skb_cnt++;
1276 }
1277
1278 skb_shinfo(skb)->frag_list = skb->next;
1279 skb->next = NULL;
1280 skb->len += frag_list_size;
1281 skb->data_len += frag_list_size;
1282 skb->truesize += frag_list_size;
1283 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1284
1285 return skb;
1286 }
1287
1288 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1289 {
1290 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1291 IXGBE_RXDADV_RSCCNT_MASK);
1292 }
1293
1294 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1295 struct ixgbe_ring *rx_ring,
1296 int *work_done, int work_to_do)
1297 {
1298 struct ixgbe_adapter *adapter = q_vector->adapter;
1299 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1300 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1301 struct sk_buff *skb;
1302 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1303 const int current_node = numa_node_id();
1304 #ifdef IXGBE_FCOE
1305 int ddp_bytes = 0;
1306 #endif /* IXGBE_FCOE */
1307 u32 staterr;
1308 u16 i;
1309 u16 cleaned_count = 0;
1310 bool pkt_is_rsc = false;
1311
1312 i = rx_ring->next_to_clean;
1313 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1314 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1315
1316 while (staterr & IXGBE_RXD_STAT_DD) {
1317 u32 upper_len = 0;
1318
1319 rmb(); /* read descriptor and rx_buffer_info after status DD */
1320
1321 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1322
1323 skb = rx_buffer_info->skb;
1324 rx_buffer_info->skb = NULL;
1325 prefetch(skb->data);
1326
1327 if (ring_is_rsc_enabled(rx_ring))
1328 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1329
1330 /* if this is a skb from previous receive DMA will be 0 */
1331 if (rx_buffer_info->dma) {
1332 u16 hlen;
1333 if (pkt_is_rsc &&
1334 !(staterr & IXGBE_RXD_STAT_EOP) &&
1335 !skb->prev) {
1336 /*
1337 * When HWRSC is enabled, delay unmapping
1338 * of the first packet. It carries the
1339 * header information, HW may still
1340 * access the header after the writeback.
1341 * Only unmap it when EOP is reached
1342 */
1343 IXGBE_RSC_CB(skb)->delay_unmap = true;
1344 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1345 } else {
1346 dma_unmap_single(rx_ring->dev,
1347 rx_buffer_info->dma,
1348 rx_ring->rx_buf_len,
1349 DMA_FROM_DEVICE);
1350 }
1351 rx_buffer_info->dma = 0;
1352
1353 if (ring_is_ps_enabled(rx_ring)) {
1354 hlen = ixgbe_get_hlen(rx_desc);
1355 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1356 } else {
1357 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1358 }
1359
1360 skb_put(skb, hlen);
1361 } else {
1362 /* assume packet split since header is unmapped */
1363 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1364 }
1365
1366 if (upper_len) {
1367 dma_unmap_page(rx_ring->dev,
1368 rx_buffer_info->page_dma,
1369 PAGE_SIZE / 2,
1370 DMA_FROM_DEVICE);
1371 rx_buffer_info->page_dma = 0;
1372 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1373 rx_buffer_info->page,
1374 rx_buffer_info->page_offset,
1375 upper_len);
1376
1377 if ((page_count(rx_buffer_info->page) == 1) &&
1378 (page_to_nid(rx_buffer_info->page) == current_node))
1379 get_page(rx_buffer_info->page);
1380 else
1381 rx_buffer_info->page = NULL;
1382
1383 skb->len += upper_len;
1384 skb->data_len += upper_len;
1385 skb->truesize += upper_len;
1386 }
1387
1388 i++;
1389 if (i == rx_ring->count)
1390 i = 0;
1391
1392 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1393 prefetch(next_rxd);
1394 cleaned_count++;
1395
1396 if (pkt_is_rsc) {
1397 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1398 IXGBE_RXDADV_NEXTP_SHIFT;
1399 next_buffer = &rx_ring->rx_buffer_info[nextp];
1400 } else {
1401 next_buffer = &rx_ring->rx_buffer_info[i];
1402 }
1403
1404 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1405 if (ring_is_ps_enabled(rx_ring)) {
1406 rx_buffer_info->skb = next_buffer->skb;
1407 rx_buffer_info->dma = next_buffer->dma;
1408 next_buffer->skb = skb;
1409 next_buffer->dma = 0;
1410 } else {
1411 skb->next = next_buffer->skb;
1412 skb->next->prev = skb;
1413 }
1414 rx_ring->rx_stats.non_eop_descs++;
1415 goto next_desc;
1416 }
1417
1418 if (skb->prev) {
1419 skb = ixgbe_transform_rsc_queue(skb);
1420 /* if we got here without RSC the packet is invalid */
1421 if (!pkt_is_rsc) {
1422 __pskb_trim(skb, 0);
1423 rx_buffer_info->skb = skb;
1424 goto next_desc;
1425 }
1426 }
1427
1428 if (ring_is_rsc_enabled(rx_ring)) {
1429 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1430 dma_unmap_single(rx_ring->dev,
1431 IXGBE_RSC_CB(skb)->dma,
1432 rx_ring->rx_buf_len,
1433 DMA_FROM_DEVICE);
1434 IXGBE_RSC_CB(skb)->dma = 0;
1435 IXGBE_RSC_CB(skb)->delay_unmap = false;
1436 }
1437 }
1438 if (pkt_is_rsc) {
1439 if (ring_is_ps_enabled(rx_ring))
1440 rx_ring->rx_stats.rsc_count +=
1441 skb_shinfo(skb)->nr_frags;
1442 else
1443 rx_ring->rx_stats.rsc_count +=
1444 IXGBE_RSC_CB(skb)->skb_cnt;
1445 rx_ring->rx_stats.rsc_flush++;
1446 }
1447
1448 /* ERR_MASK will only have valid bits if EOP set */
1449 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1450 /* trim packet back to size 0 and recycle it */
1451 __pskb_trim(skb, 0);
1452 rx_buffer_info->skb = skb;
1453 goto next_desc;
1454 }
1455
1456 ixgbe_rx_checksum(adapter, rx_desc, skb);
1457
1458 /* probably a little skewed due to removing CRC */
1459 total_rx_bytes += skb->len;
1460 total_rx_packets++;
1461
1462 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1463 #ifdef IXGBE_FCOE
1464 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1465 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1466 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1467 if (!ddp_bytes)
1468 goto next_desc;
1469 }
1470 #endif /* IXGBE_FCOE */
1471 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1472
1473 next_desc:
1474 rx_desc->wb.upper.status_error = 0;
1475
1476 (*work_done)++;
1477 if (*work_done >= work_to_do)
1478 break;
1479
1480 /* return some buffers to hardware, one at a time is too slow */
1481 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1482 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1483 cleaned_count = 0;
1484 }
1485
1486 /* use prefetched values */
1487 rx_desc = next_rxd;
1488 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1489 }
1490
1491 rx_ring->next_to_clean = i;
1492 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1493
1494 if (cleaned_count)
1495 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1496
1497 #ifdef IXGBE_FCOE
1498 /* include DDPed FCoE data */
1499 if (ddp_bytes > 0) {
1500 unsigned int mss;
1501
1502 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1503 sizeof(struct fc_frame_header) -
1504 sizeof(struct fcoe_crc_eof);
1505 if (mss > 512)
1506 mss &= ~511;
1507 total_rx_bytes += ddp_bytes;
1508 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1509 }
1510 #endif /* IXGBE_FCOE */
1511
1512 rx_ring->total_packets += total_rx_packets;
1513 rx_ring->total_bytes += total_rx_bytes;
1514 u64_stats_update_begin(&rx_ring->syncp);
1515 rx_ring->stats.packets += total_rx_packets;
1516 rx_ring->stats.bytes += total_rx_bytes;
1517 u64_stats_update_end(&rx_ring->syncp);
1518 }
1519
1520 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1521 /**
1522 * ixgbe_configure_msix - Configure MSI-X hardware
1523 * @adapter: board private structure
1524 *
1525 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1526 * interrupts.
1527 **/
1528 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1529 {
1530 struct ixgbe_q_vector *q_vector;
1531 int i, q_vectors, v_idx, r_idx;
1532 u32 mask;
1533
1534 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1535
1536 /*
1537 * Populate the IVAR table and set the ITR values to the
1538 * corresponding register.
1539 */
1540 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1541 q_vector = adapter->q_vector[v_idx];
1542 /* XXX for_each_set_bit(...) */
1543 r_idx = find_first_bit(q_vector->rxr_idx,
1544 adapter->num_rx_queues);
1545
1546 for (i = 0; i < q_vector->rxr_count; i++) {
1547 u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1548 ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
1549 r_idx = find_next_bit(q_vector->rxr_idx,
1550 adapter->num_rx_queues,
1551 r_idx + 1);
1552 }
1553 r_idx = find_first_bit(q_vector->txr_idx,
1554 adapter->num_tx_queues);
1555
1556 for (i = 0; i < q_vector->txr_count; i++) {
1557 u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1558 ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
1559 r_idx = find_next_bit(q_vector->txr_idx,
1560 adapter->num_tx_queues,
1561 r_idx + 1);
1562 }
1563
1564 if (q_vector->txr_count && !q_vector->rxr_count)
1565 /* tx only */
1566 q_vector->eitr = adapter->tx_eitr_param;
1567 else if (q_vector->rxr_count)
1568 /* rx or mixed */
1569 q_vector->eitr = adapter->rx_eitr_param;
1570
1571 ixgbe_write_eitr(q_vector);
1572 /* If Flow Director is enabled, set interrupt affinity */
1573 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1574 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1575 /*
1576 * Allocate the affinity_hint cpumask, assign the mask
1577 * for this vector, and set our affinity_hint for
1578 * this irq.
1579 */
1580 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1581 GFP_KERNEL))
1582 return;
1583 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1584 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1585 q_vector->affinity_mask);
1586 }
1587 }
1588
1589 switch (adapter->hw.mac.type) {
1590 case ixgbe_mac_82598EB:
1591 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1592 v_idx);
1593 break;
1594 case ixgbe_mac_82599EB:
1595 case ixgbe_mac_X540:
1596 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1597 break;
1598
1599 default:
1600 break;
1601 }
1602 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1603
1604 /* set up to autoclear timer, and the vectors */
1605 mask = IXGBE_EIMS_ENABLE_MASK;
1606 if (adapter->num_vfs)
1607 mask &= ~(IXGBE_EIMS_OTHER |
1608 IXGBE_EIMS_MAILBOX |
1609 IXGBE_EIMS_LSC);
1610 else
1611 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1612 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1613 }
1614
1615 enum latency_range {
1616 lowest_latency = 0,
1617 low_latency = 1,
1618 bulk_latency = 2,
1619 latency_invalid = 255
1620 };
1621
1622 /**
1623 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1624 * @adapter: pointer to adapter
1625 * @eitr: eitr setting (ints per sec) to give last timeslice
1626 * @itr_setting: current throttle rate in ints/second
1627 * @packets: the number of packets during this measurement interval
1628 * @bytes: the number of bytes during this measurement interval
1629 *
1630 * Stores a new ITR value based on packets and byte
1631 * counts during the last interrupt. The advantage of per interrupt
1632 * computation is faster updates and more accurate ITR for the current
1633 * traffic pattern. Constants in this function were computed
1634 * based on theoretical maximum wire speed and thresholds were set based
1635 * on testing data as well as attempting to minimize response time
1636 * while increasing bulk throughput.
1637 * this functionality is controlled by the InterruptThrottleRate module
1638 * parameter (see ixgbe_param.c)
1639 **/
1640 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1641 u32 eitr, u8 itr_setting,
1642 int packets, int bytes)
1643 {
1644 unsigned int retval = itr_setting;
1645 u32 timepassed_us;
1646 u64 bytes_perint;
1647
1648 if (packets == 0)
1649 goto update_itr_done;
1650
1651
1652 /* simple throttlerate management
1653 * 0-20MB/s lowest (100000 ints/s)
1654 * 20-100MB/s low (20000 ints/s)
1655 * 100-1249MB/s bulk (8000 ints/s)
1656 */
1657 /* what was last interrupt timeslice? */
1658 timepassed_us = 1000000/eitr;
1659 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1660
1661 switch (itr_setting) {
1662 case lowest_latency:
1663 if (bytes_perint > adapter->eitr_low)
1664 retval = low_latency;
1665 break;
1666 case low_latency:
1667 if (bytes_perint > adapter->eitr_high)
1668 retval = bulk_latency;
1669 else if (bytes_perint <= adapter->eitr_low)
1670 retval = lowest_latency;
1671 break;
1672 case bulk_latency:
1673 if (bytes_perint <= adapter->eitr_high)
1674 retval = low_latency;
1675 break;
1676 }
1677
1678 update_itr_done:
1679 return retval;
1680 }
1681
1682 /**
1683 * ixgbe_write_eitr - write EITR register in hardware specific way
1684 * @q_vector: structure containing interrupt and ring information
1685 *
1686 * This function is made to be called by ethtool and by the driver
1687 * when it needs to update EITR registers at runtime. Hardware
1688 * specific quirks/differences are taken care of here.
1689 */
1690 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1691 {
1692 struct ixgbe_adapter *adapter = q_vector->adapter;
1693 struct ixgbe_hw *hw = &adapter->hw;
1694 int v_idx = q_vector->v_idx;
1695 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1696
1697 switch (adapter->hw.mac.type) {
1698 case ixgbe_mac_82598EB:
1699 /* must write high and low 16 bits to reset counter */
1700 itr_reg |= (itr_reg << 16);
1701 break;
1702 case ixgbe_mac_82599EB:
1703 case ixgbe_mac_X540:
1704 /*
1705 * 82599 and X540 can support a value of zero, so allow it for
1706 * max interrupt rate, but there is an errata where it can
1707 * not be zero with RSC
1708 */
1709 if (itr_reg == 8 &&
1710 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1711 itr_reg = 0;
1712
1713 /*
1714 * set the WDIS bit to not clear the timer bits and cause an
1715 * immediate assertion of the interrupt
1716 */
1717 itr_reg |= IXGBE_EITR_CNT_WDIS;
1718 break;
1719 default:
1720 break;
1721 }
1722 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1723 }
1724
1725 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1726 {
1727 struct ixgbe_adapter *adapter = q_vector->adapter;
1728 int i, r_idx;
1729 u32 new_itr;
1730 u8 current_itr, ret_itr;
1731
1732 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1733 for (i = 0; i < q_vector->txr_count; i++) {
1734 struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
1735 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1736 q_vector->tx_itr,
1737 tx_ring->total_packets,
1738 tx_ring->total_bytes);
1739 /* if the result for this queue would decrease interrupt
1740 * rate for this vector then use that result */
1741 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1742 q_vector->tx_itr - 1 : ret_itr);
1743 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1744 r_idx + 1);
1745 }
1746
1747 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1748 for (i = 0; i < q_vector->rxr_count; i++) {
1749 struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
1750 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1751 q_vector->rx_itr,
1752 rx_ring->total_packets,
1753 rx_ring->total_bytes);
1754 /* if the result for this queue would decrease interrupt
1755 * rate for this vector then use that result */
1756 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1757 q_vector->rx_itr - 1 : ret_itr);
1758 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1759 r_idx + 1);
1760 }
1761
1762 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1763
1764 switch (current_itr) {
1765 /* counts and packets in update_itr are dependent on these numbers */
1766 case lowest_latency:
1767 new_itr = 100000;
1768 break;
1769 case low_latency:
1770 new_itr = 20000; /* aka hwitr = ~200 */
1771 break;
1772 case bulk_latency:
1773 default:
1774 new_itr = 8000;
1775 break;
1776 }
1777
1778 if (new_itr != q_vector->eitr) {
1779 /* do an exponential smoothing */
1780 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1781
1782 /* save the algorithm value here, not the smoothed one */
1783 q_vector->eitr = new_itr;
1784
1785 ixgbe_write_eitr(q_vector);
1786 }
1787 }
1788
1789 /**
1790 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1791 * @work: pointer to work_struct containing our data
1792 **/
1793 static void ixgbe_check_overtemp_task(struct work_struct *work)
1794 {
1795 struct ixgbe_adapter *adapter = container_of(work,
1796 struct ixgbe_adapter,
1797 check_overtemp_task);
1798 struct ixgbe_hw *hw = &adapter->hw;
1799 u32 eicr = adapter->interrupt_event;
1800
1801 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1802 return;
1803
1804 switch (hw->device_id) {
1805 case IXGBE_DEV_ID_82599_T3_LOM: {
1806 u32 autoneg;
1807 bool link_up = false;
1808
1809 if (hw->mac.ops.check_link)
1810 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1811
1812 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1813 (eicr & IXGBE_EICR_LSC))
1814 /* Check if this is due to overtemp */
1815 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1816 break;
1817 return;
1818 }
1819 default:
1820 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1821 return;
1822 break;
1823 }
1824 e_crit(drv,
1825 "Network adapter has been stopped because it has over heated. "
1826 "Restart the computer. If the problem persists, "
1827 "power off the system and replace the adapter\n");
1828 /* write to clear the interrupt */
1829 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1830 }
1831
1832 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1833 {
1834 struct ixgbe_hw *hw = &adapter->hw;
1835
1836 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1837 (eicr & IXGBE_EICR_GPI_SDP1)) {
1838 e_crit(probe, "Fan has stopped, replace the adapter\n");
1839 /* write to clear the interrupt */
1840 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1841 }
1842 }
1843
1844 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1845 {
1846 struct ixgbe_hw *hw = &adapter->hw;
1847
1848 if (eicr & IXGBE_EICR_GPI_SDP2) {
1849 /* Clear the interrupt */
1850 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1851 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1852 schedule_work(&adapter->sfp_config_module_task);
1853 }
1854
1855 if (eicr & IXGBE_EICR_GPI_SDP1) {
1856 /* Clear the interrupt */
1857 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1858 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1859 schedule_work(&adapter->multispeed_fiber_task);
1860 }
1861 }
1862
1863 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1864 {
1865 struct ixgbe_hw *hw = &adapter->hw;
1866
1867 adapter->lsc_int++;
1868 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1869 adapter->link_check_timeout = jiffies;
1870 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1871 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1872 IXGBE_WRITE_FLUSH(hw);
1873 schedule_work(&adapter->watchdog_task);
1874 }
1875 }
1876
1877 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1878 {
1879 struct net_device *netdev = data;
1880 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1881 struct ixgbe_hw *hw = &adapter->hw;
1882 u32 eicr;
1883
1884 /*
1885 * Workaround for Silicon errata. Use clear-by-write instead
1886 * of clear-by-read. Reading with EICS will return the
1887 * interrupt causes without clearing, which later be done
1888 * with the write to EICR.
1889 */
1890 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1891 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1892
1893 if (eicr & IXGBE_EICR_LSC)
1894 ixgbe_check_lsc(adapter);
1895
1896 if (eicr & IXGBE_EICR_MAILBOX)
1897 ixgbe_msg_task(adapter);
1898
1899 switch (hw->mac.type) {
1900 case ixgbe_mac_82599EB:
1901 ixgbe_check_sfp_event(adapter, eicr);
1902 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1903 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1904 adapter->interrupt_event = eicr;
1905 schedule_work(&adapter->check_overtemp_task);
1906 }
1907 /* now fallthrough to handle Flow Director */
1908 case ixgbe_mac_X540:
1909 /* Handle Flow Director Full threshold interrupt */
1910 if (eicr & IXGBE_EICR_FLOW_DIR) {
1911 int i;
1912 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1913 /* Disable transmits before FDIR Re-initialization */
1914 netif_tx_stop_all_queues(netdev);
1915 for (i = 0; i < adapter->num_tx_queues; i++) {
1916 struct ixgbe_ring *tx_ring =
1917 adapter->tx_ring[i];
1918 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1919 &tx_ring->state))
1920 schedule_work(&adapter->fdir_reinit_task);
1921 }
1922 }
1923 break;
1924 default:
1925 break;
1926 }
1927
1928 ixgbe_check_fan_failure(adapter, eicr);
1929
1930 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1931 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1932
1933 return IRQ_HANDLED;
1934 }
1935
1936 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1937 u64 qmask)
1938 {
1939 u32 mask;
1940 struct ixgbe_hw *hw = &adapter->hw;
1941
1942 switch (hw->mac.type) {
1943 case ixgbe_mac_82598EB:
1944 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1945 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1946 break;
1947 case ixgbe_mac_82599EB:
1948 case ixgbe_mac_X540:
1949 mask = (qmask & 0xFFFFFFFF);
1950 if (mask)
1951 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1952 mask = (qmask >> 32);
1953 if (mask)
1954 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1955 break;
1956 default:
1957 break;
1958 }
1959 /* skip the flush */
1960 }
1961
1962 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1963 u64 qmask)
1964 {
1965 u32 mask;
1966 struct ixgbe_hw *hw = &adapter->hw;
1967
1968 switch (hw->mac.type) {
1969 case ixgbe_mac_82598EB:
1970 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1971 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1972 break;
1973 case ixgbe_mac_82599EB:
1974 case ixgbe_mac_X540:
1975 mask = (qmask & 0xFFFFFFFF);
1976 if (mask)
1977 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1978 mask = (qmask >> 32);
1979 if (mask)
1980 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1981 break;
1982 default:
1983 break;
1984 }
1985 /* skip the flush */
1986 }
1987
1988 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1989 {
1990 struct ixgbe_q_vector *q_vector = data;
1991 struct ixgbe_adapter *adapter = q_vector->adapter;
1992 struct ixgbe_ring *tx_ring;
1993 int i, r_idx;
1994
1995 if (!q_vector->txr_count)
1996 return IRQ_HANDLED;
1997
1998 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1999 for (i = 0; i < q_vector->txr_count; i++) {
2000 tx_ring = adapter->tx_ring[r_idx];
2001 tx_ring->total_bytes = 0;
2002 tx_ring->total_packets = 0;
2003 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2004 r_idx + 1);
2005 }
2006
2007 /* EIAM disabled interrupts (on this vector) for us */
2008 napi_schedule(&q_vector->napi);
2009
2010 return IRQ_HANDLED;
2011 }
2012
2013 /**
2014 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2015 * @irq: unused
2016 * @data: pointer to our q_vector struct for this interrupt vector
2017 **/
2018 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2019 {
2020 struct ixgbe_q_vector *q_vector = data;
2021 struct ixgbe_adapter *adapter = q_vector->adapter;
2022 struct ixgbe_ring *rx_ring;
2023 int r_idx;
2024 int i;
2025
2026 #ifdef CONFIG_IXGBE_DCA
2027 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2028 ixgbe_update_dca(q_vector);
2029 #endif
2030
2031 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2032 for (i = 0; i < q_vector->rxr_count; i++) {
2033 rx_ring = adapter->rx_ring[r_idx];
2034 rx_ring->total_bytes = 0;
2035 rx_ring->total_packets = 0;
2036 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2037 r_idx + 1);
2038 }
2039
2040 if (!q_vector->rxr_count)
2041 return IRQ_HANDLED;
2042
2043 /* EIAM disabled interrupts (on this vector) for us */
2044 napi_schedule(&q_vector->napi);
2045
2046 return IRQ_HANDLED;
2047 }
2048
2049 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2050 {
2051 struct ixgbe_q_vector *q_vector = data;
2052 struct ixgbe_adapter *adapter = q_vector->adapter;
2053 struct ixgbe_ring *ring;
2054 int r_idx;
2055 int i;
2056
2057 if (!q_vector->txr_count && !q_vector->rxr_count)
2058 return IRQ_HANDLED;
2059
2060 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2061 for (i = 0; i < q_vector->txr_count; i++) {
2062 ring = adapter->tx_ring[r_idx];
2063 ring->total_bytes = 0;
2064 ring->total_packets = 0;
2065 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2066 r_idx + 1);
2067 }
2068
2069 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2070 for (i = 0; i < q_vector->rxr_count; i++) {
2071 ring = adapter->rx_ring[r_idx];
2072 ring->total_bytes = 0;
2073 ring->total_packets = 0;
2074 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2075 r_idx + 1);
2076 }
2077
2078 /* EIAM disabled interrupts (on this vector) for us */
2079 napi_schedule(&q_vector->napi);
2080
2081 return IRQ_HANDLED;
2082 }
2083
2084 /**
2085 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2086 * @napi: napi struct with our devices info in it
2087 * @budget: amount of work driver is allowed to do this pass, in packets
2088 *
2089 * This function is optimized for cleaning one queue only on a single
2090 * q_vector!!!
2091 **/
2092 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2093 {
2094 struct ixgbe_q_vector *q_vector =
2095 container_of(napi, struct ixgbe_q_vector, napi);
2096 struct ixgbe_adapter *adapter = q_vector->adapter;
2097 struct ixgbe_ring *rx_ring = NULL;
2098 int work_done = 0;
2099 long r_idx;
2100
2101 #ifdef CONFIG_IXGBE_DCA
2102 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2103 ixgbe_update_dca(q_vector);
2104 #endif
2105
2106 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2107 rx_ring = adapter->rx_ring[r_idx];
2108
2109 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
2110
2111 /* If all Rx work done, exit the polling mode */
2112 if (work_done < budget) {
2113 napi_complete(napi);
2114 if (adapter->rx_itr_setting & 1)
2115 ixgbe_set_itr_msix(q_vector);
2116 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2117 ixgbe_irq_enable_queues(adapter,
2118 ((u64)1 << q_vector->v_idx));
2119 }
2120
2121 return work_done;
2122 }
2123
2124 /**
2125 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2126 * @napi: napi struct with our devices info in it
2127 * @budget: amount of work driver is allowed to do this pass, in packets
2128 *
2129 * This function will clean more than one rx queue associated with a
2130 * q_vector.
2131 **/
2132 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
2133 {
2134 struct ixgbe_q_vector *q_vector =
2135 container_of(napi, struct ixgbe_q_vector, napi);
2136 struct ixgbe_adapter *adapter = q_vector->adapter;
2137 struct ixgbe_ring *ring = NULL;
2138 int work_done = 0, i;
2139 long r_idx;
2140 bool tx_clean_complete = true;
2141
2142 #ifdef CONFIG_IXGBE_DCA
2143 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2144 ixgbe_update_dca(q_vector);
2145 #endif
2146
2147 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2148 for (i = 0; i < q_vector->txr_count; i++) {
2149 ring = adapter->tx_ring[r_idx];
2150 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2151 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2152 r_idx + 1);
2153 }
2154
2155 /* attempt to distribute budget to each queue fairly, but don't allow
2156 * the budget to go below 1 because we'll exit polling */
2157 budget /= (q_vector->rxr_count ?: 1);
2158 budget = max(budget, 1);
2159 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2160 for (i = 0; i < q_vector->rxr_count; i++) {
2161 ring = adapter->rx_ring[r_idx];
2162 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2163 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2164 r_idx + 1);
2165 }
2166
2167 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2168 ring = adapter->rx_ring[r_idx];
2169 /* If all Rx work done, exit the polling mode */
2170 if (work_done < budget) {
2171 napi_complete(napi);
2172 if (adapter->rx_itr_setting & 1)
2173 ixgbe_set_itr_msix(q_vector);
2174 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2175 ixgbe_irq_enable_queues(adapter,
2176 ((u64)1 << q_vector->v_idx));
2177 return 0;
2178 }
2179
2180 return work_done;
2181 }
2182
2183 /**
2184 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2185 * @napi: napi struct with our devices info in it
2186 * @budget: amount of work driver is allowed to do this pass, in packets
2187 *
2188 * This function is optimized for cleaning one queue only on a single
2189 * q_vector!!!
2190 **/
2191 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2192 {
2193 struct ixgbe_q_vector *q_vector =
2194 container_of(napi, struct ixgbe_q_vector, napi);
2195 struct ixgbe_adapter *adapter = q_vector->adapter;
2196 struct ixgbe_ring *tx_ring = NULL;
2197 int work_done = 0;
2198 long r_idx;
2199
2200 #ifdef CONFIG_IXGBE_DCA
2201 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2202 ixgbe_update_dca(q_vector);
2203 #endif
2204
2205 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2206 tx_ring = adapter->tx_ring[r_idx];
2207
2208 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2209 work_done = budget;
2210
2211 /* If all Tx work done, exit the polling mode */
2212 if (work_done < budget) {
2213 napi_complete(napi);
2214 if (adapter->tx_itr_setting & 1)
2215 ixgbe_set_itr_msix(q_vector);
2216 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2217 ixgbe_irq_enable_queues(adapter,
2218 ((u64)1 << q_vector->v_idx));
2219 }
2220
2221 return work_done;
2222 }
2223
2224 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2225 int r_idx)
2226 {
2227 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2228 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2229
2230 set_bit(r_idx, q_vector->rxr_idx);
2231 q_vector->rxr_count++;
2232 rx_ring->q_vector = q_vector;
2233 }
2234
2235 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2236 int t_idx)
2237 {
2238 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2239 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2240
2241 set_bit(t_idx, q_vector->txr_idx);
2242 q_vector->txr_count++;
2243 tx_ring->q_vector = q_vector;
2244 }
2245
2246 /**
2247 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2248 * @adapter: board private structure to initialize
2249 *
2250 * This function maps descriptor rings to the queue-specific vectors
2251 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2252 * one vector per ring/queue, but on a constrained vector budget, we
2253 * group the rings as "efficiently" as possible. You would add new
2254 * mapping configurations in here.
2255 **/
2256 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2257 {
2258 int q_vectors;
2259 int v_start = 0;
2260 int rxr_idx = 0, txr_idx = 0;
2261 int rxr_remaining = adapter->num_rx_queues;
2262 int txr_remaining = adapter->num_tx_queues;
2263 int i, j;
2264 int rqpv, tqpv;
2265 int err = 0;
2266
2267 /* No mapping required if MSI-X is disabled. */
2268 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2269 goto out;
2270
2271 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2272
2273 /*
2274 * The ideal configuration...
2275 * We have enough vectors to map one per queue.
2276 */
2277 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2278 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2279 map_vector_to_rxq(adapter, v_start, rxr_idx);
2280
2281 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2282 map_vector_to_txq(adapter, v_start, txr_idx);
2283
2284 goto out;
2285 }
2286
2287 /*
2288 * If we don't have enough vectors for a 1-to-1
2289 * mapping, we'll have to group them so there are
2290 * multiple queues per vector.
2291 */
2292 /* Re-adjusting *qpv takes care of the remainder. */
2293 for (i = v_start; i < q_vectors; i++) {
2294 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
2295 for (j = 0; j < rqpv; j++) {
2296 map_vector_to_rxq(adapter, i, rxr_idx);
2297 rxr_idx++;
2298 rxr_remaining--;
2299 }
2300 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
2301 for (j = 0; j < tqpv; j++) {
2302 map_vector_to_txq(adapter, i, txr_idx);
2303 txr_idx++;
2304 txr_remaining--;
2305 }
2306 }
2307 out:
2308 return err;
2309 }
2310
2311 /**
2312 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2313 * @adapter: board private structure
2314 *
2315 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2316 * interrupts from the kernel.
2317 **/
2318 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2319 {
2320 struct net_device *netdev = adapter->netdev;
2321 irqreturn_t (*handler)(int, void *);
2322 int i, vector, q_vectors, err;
2323 int ri = 0, ti = 0;
2324
2325 /* Decrement for Other and TCP Timer vectors */
2326 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2327
2328 err = ixgbe_map_rings_to_vectors(adapter);
2329 if (err)
2330 return err;
2331
2332 #define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \
2333 ? &ixgbe_msix_clean_many : \
2334 (_v)->rxr_count ? &ixgbe_msix_clean_rx : \
2335 (_v)->txr_count ? &ixgbe_msix_clean_tx : \
2336 NULL)
2337 for (vector = 0; vector < q_vectors; vector++) {
2338 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2339 handler = SET_HANDLER(q_vector);
2340
2341 if (handler == &ixgbe_msix_clean_rx) {
2342 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2343 "%s-%s-%d", netdev->name, "rx", ri++);
2344 } else if (handler == &ixgbe_msix_clean_tx) {
2345 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2346 "%s-%s-%d", netdev->name, "tx", ti++);
2347 } else if (handler == &ixgbe_msix_clean_many) {
2348 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2349 "%s-%s-%d", netdev->name, "TxRx", ri++);
2350 ti++;
2351 } else {
2352 /* skip this unused q_vector */
2353 continue;
2354 }
2355 err = request_irq(adapter->msix_entries[vector].vector,
2356 handler, 0, q_vector->name,
2357 q_vector);
2358 if (err) {
2359 e_err(probe, "request_irq failed for MSIX interrupt "
2360 "Error: %d\n", err);
2361 goto free_queue_irqs;
2362 }
2363 }
2364
2365 sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
2366 err = request_irq(adapter->msix_entries[vector].vector,
2367 ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev);
2368 if (err) {
2369 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2370 goto free_queue_irqs;
2371 }
2372
2373 return 0;
2374
2375 free_queue_irqs:
2376 for (i = vector - 1; i >= 0; i--)
2377 free_irq(adapter->msix_entries[--vector].vector,
2378 adapter->q_vector[i]);
2379 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2380 pci_disable_msix(adapter->pdev);
2381 kfree(adapter->msix_entries);
2382 adapter->msix_entries = NULL;
2383 return err;
2384 }
2385
2386 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2387 {
2388 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2389 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2390 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2391 u32 new_itr = q_vector->eitr;
2392 u8 current_itr;
2393
2394 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2395 q_vector->tx_itr,
2396 tx_ring->total_packets,
2397 tx_ring->total_bytes);
2398 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2399 q_vector->rx_itr,
2400 rx_ring->total_packets,
2401 rx_ring->total_bytes);
2402
2403 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2404
2405 switch (current_itr) {
2406 /* counts and packets in update_itr are dependent on these numbers */
2407 case lowest_latency:
2408 new_itr = 100000;
2409 break;
2410 case low_latency:
2411 new_itr = 20000; /* aka hwitr = ~200 */
2412 break;
2413 case bulk_latency:
2414 new_itr = 8000;
2415 break;
2416 default:
2417 break;
2418 }
2419
2420 if (new_itr != q_vector->eitr) {
2421 /* do an exponential smoothing */
2422 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
2423
2424 /* save the algorithm value here */
2425 q_vector->eitr = new_itr;
2426
2427 ixgbe_write_eitr(q_vector);
2428 }
2429 }
2430
2431 /**
2432 * ixgbe_irq_enable - Enable default interrupt generation settings
2433 * @adapter: board private structure
2434 **/
2435 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2436 bool flush)
2437 {
2438 u32 mask;
2439
2440 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2441 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2442 mask |= IXGBE_EIMS_GPI_SDP0;
2443 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2444 mask |= IXGBE_EIMS_GPI_SDP1;
2445 switch (adapter->hw.mac.type) {
2446 case ixgbe_mac_82599EB:
2447 case ixgbe_mac_X540:
2448 mask |= IXGBE_EIMS_ECC;
2449 mask |= IXGBE_EIMS_GPI_SDP1;
2450 mask |= IXGBE_EIMS_GPI_SDP2;
2451 if (adapter->num_vfs)
2452 mask |= IXGBE_EIMS_MAILBOX;
2453 break;
2454 default:
2455 break;
2456 }
2457 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2458 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2459 mask |= IXGBE_EIMS_FLOW_DIR;
2460
2461 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2462 if (queues)
2463 ixgbe_irq_enable_queues(adapter, ~0);
2464 if (flush)
2465 IXGBE_WRITE_FLUSH(&adapter->hw);
2466
2467 if (adapter->num_vfs > 32) {
2468 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2469 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2470 }
2471 }
2472
2473 /**
2474 * ixgbe_intr - legacy mode Interrupt Handler
2475 * @irq: interrupt number
2476 * @data: pointer to a network interface device structure
2477 **/
2478 static irqreturn_t ixgbe_intr(int irq, void *data)
2479 {
2480 struct net_device *netdev = data;
2481 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2482 struct ixgbe_hw *hw = &adapter->hw;
2483 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2484 u32 eicr;
2485
2486 /*
2487 * Workaround for silicon errata on 82598. Mask the interrupts
2488 * before the read of EICR.
2489 */
2490 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2491
2492 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2493 * therefore no explict interrupt disable is necessary */
2494 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2495 if (!eicr) {
2496 /*
2497 * shared interrupt alert!
2498 * make sure interrupts are enabled because the read will
2499 * have disabled interrupts due to EIAM
2500 * finish the workaround of silicon errata on 82598. Unmask
2501 * the interrupt that we masked before the EICR read.
2502 */
2503 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2504 ixgbe_irq_enable(adapter, true, true);
2505 return IRQ_NONE; /* Not our interrupt */
2506 }
2507
2508 if (eicr & IXGBE_EICR_LSC)
2509 ixgbe_check_lsc(adapter);
2510
2511 switch (hw->mac.type) {
2512 case ixgbe_mac_82599EB:
2513 ixgbe_check_sfp_event(adapter, eicr);
2514 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2515 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2516 adapter->interrupt_event = eicr;
2517 schedule_work(&adapter->check_overtemp_task);
2518 }
2519 break;
2520 default:
2521 break;
2522 }
2523
2524 ixgbe_check_fan_failure(adapter, eicr);
2525
2526 if (napi_schedule_prep(&(q_vector->napi))) {
2527 adapter->tx_ring[0]->total_packets = 0;
2528 adapter->tx_ring[0]->total_bytes = 0;
2529 adapter->rx_ring[0]->total_packets = 0;
2530 adapter->rx_ring[0]->total_bytes = 0;
2531 /* would disable interrupts here but EIAM disabled it */
2532 __napi_schedule(&(q_vector->napi));
2533 }
2534
2535 /*
2536 * re-enable link(maybe) and non-queue interrupts, no flush.
2537 * ixgbe_poll will re-enable the queue interrupts
2538 */
2539
2540 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2541 ixgbe_irq_enable(adapter, false, false);
2542
2543 return IRQ_HANDLED;
2544 }
2545
2546 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2547 {
2548 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2549
2550 for (i = 0; i < q_vectors; i++) {
2551 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2552 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2553 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2554 q_vector->rxr_count = 0;
2555 q_vector->txr_count = 0;
2556 }
2557 }
2558
2559 /**
2560 * ixgbe_request_irq - initialize interrupts
2561 * @adapter: board private structure
2562 *
2563 * Attempts to configure interrupts using the best available
2564 * capabilities of the hardware and kernel.
2565 **/
2566 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2567 {
2568 struct net_device *netdev = adapter->netdev;
2569 int err;
2570
2571 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2572 err = ixgbe_request_msix_irqs(adapter);
2573 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2574 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2575 netdev->name, netdev);
2576 } else {
2577 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2578 netdev->name, netdev);
2579 }
2580
2581 if (err)
2582 e_err(probe, "request_irq failed, Error %d\n", err);
2583
2584 return err;
2585 }
2586
2587 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2588 {
2589 struct net_device *netdev = adapter->netdev;
2590
2591 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2592 int i, q_vectors;
2593
2594 q_vectors = adapter->num_msix_vectors;
2595
2596 i = q_vectors - 1;
2597 free_irq(adapter->msix_entries[i].vector, netdev);
2598
2599 i--;
2600 for (; i >= 0; i--) {
2601 /* free only the irqs that were actually requested */
2602 if (!adapter->q_vector[i]->rxr_count &&
2603 !adapter->q_vector[i]->txr_count)
2604 continue;
2605
2606 free_irq(adapter->msix_entries[i].vector,
2607 adapter->q_vector[i]);
2608 }
2609
2610 ixgbe_reset_q_vectors(adapter);
2611 } else {
2612 free_irq(adapter->pdev->irq, netdev);
2613 }
2614 }
2615
2616 /**
2617 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2618 * @adapter: board private structure
2619 **/
2620 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2621 {
2622 switch (adapter->hw.mac.type) {
2623 case ixgbe_mac_82598EB:
2624 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2625 break;
2626 case ixgbe_mac_82599EB:
2627 case ixgbe_mac_X540:
2628 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2629 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2630 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2631 if (adapter->num_vfs > 32)
2632 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2633 break;
2634 default:
2635 break;
2636 }
2637 IXGBE_WRITE_FLUSH(&adapter->hw);
2638 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2639 int i;
2640 for (i = 0; i < adapter->num_msix_vectors; i++)
2641 synchronize_irq(adapter->msix_entries[i].vector);
2642 } else {
2643 synchronize_irq(adapter->pdev->irq);
2644 }
2645 }
2646
2647 /**
2648 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2649 *
2650 **/
2651 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2652 {
2653 struct ixgbe_hw *hw = &adapter->hw;
2654
2655 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2656 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2657
2658 ixgbe_set_ivar(adapter, 0, 0, 0);
2659 ixgbe_set_ivar(adapter, 1, 0, 0);
2660
2661 map_vector_to_rxq(adapter, 0, 0);
2662 map_vector_to_txq(adapter, 0, 0);
2663
2664 e_info(hw, "Legacy interrupt IVAR setup done\n");
2665 }
2666
2667 /**
2668 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2669 * @adapter: board private structure
2670 * @ring: structure containing ring specific data
2671 *
2672 * Configure the Tx descriptor ring after a reset.
2673 **/
2674 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2675 struct ixgbe_ring *ring)
2676 {
2677 struct ixgbe_hw *hw = &adapter->hw;
2678 u64 tdba = ring->dma;
2679 int wait_loop = 10;
2680 u32 txdctl;
2681 u8 reg_idx = ring->reg_idx;
2682
2683 /* disable queue to avoid issues while updating state */
2684 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2685 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2686 txdctl & ~IXGBE_TXDCTL_ENABLE);
2687 IXGBE_WRITE_FLUSH(hw);
2688
2689 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2690 (tdba & DMA_BIT_MASK(32)));
2691 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2692 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2693 ring->count * sizeof(union ixgbe_adv_tx_desc));
2694 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2695 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2696 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2697
2698 /* configure fetching thresholds */
2699 if (adapter->rx_itr_setting == 0) {
2700 /* cannot set wthresh when itr==0 */
2701 txdctl &= ~0x007F0000;
2702 } else {
2703 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2704 txdctl |= (8 << 16);
2705 }
2706 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2707 /* PThresh workaround for Tx hang with DFP enabled. */
2708 txdctl |= 32;
2709 }
2710
2711 /* reinitialize flowdirector state */
2712 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2713 adapter->atr_sample_rate) {
2714 ring->atr_sample_rate = adapter->atr_sample_rate;
2715 ring->atr_count = 0;
2716 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2717 } else {
2718 ring->atr_sample_rate = 0;
2719 }
2720
2721 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2722
2723 /* enable queue */
2724 txdctl |= IXGBE_TXDCTL_ENABLE;
2725 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2726
2727 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2728 if (hw->mac.type == ixgbe_mac_82598EB &&
2729 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2730 return;
2731
2732 /* poll to verify queue is enabled */
2733 do {
2734 msleep(1);
2735 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2736 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2737 if (!wait_loop)
2738 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2739 }
2740
2741 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2742 {
2743 struct ixgbe_hw *hw = &adapter->hw;
2744 u32 rttdcs;
2745 u32 mask;
2746
2747 if (hw->mac.type == ixgbe_mac_82598EB)
2748 return;
2749
2750 /* disable the arbiter while setting MTQC */
2751 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2752 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2753 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2754
2755 /* set transmit pool layout */
2756 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2757 switch (adapter->flags & mask) {
2758
2759 case (IXGBE_FLAG_SRIOV_ENABLED):
2760 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2761 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2762 break;
2763
2764 case (IXGBE_FLAG_DCB_ENABLED):
2765 /* We enable 8 traffic classes, DCB only */
2766 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2767 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2768 break;
2769
2770 default:
2771 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2772 break;
2773 }
2774
2775 /* re-enable the arbiter */
2776 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2777 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2778 }
2779
2780 /**
2781 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2782 * @adapter: board private structure
2783 *
2784 * Configure the Tx unit of the MAC after a reset.
2785 **/
2786 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2787 {
2788 struct ixgbe_hw *hw = &adapter->hw;
2789 u32 dmatxctl;
2790 u32 i;
2791
2792 ixgbe_setup_mtqc(adapter);
2793
2794 if (hw->mac.type != ixgbe_mac_82598EB) {
2795 /* DMATXCTL.EN must be before Tx queues are enabled */
2796 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2797 dmatxctl |= IXGBE_DMATXCTL_TE;
2798 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2799 }
2800
2801 /* Setup the HW Tx Head and Tail descriptor pointers */
2802 for (i = 0; i < adapter->num_tx_queues; i++)
2803 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2804 }
2805
2806 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2807
2808 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2809 struct ixgbe_ring *rx_ring)
2810 {
2811 u32 srrctl;
2812 u8 reg_idx = rx_ring->reg_idx;
2813
2814 switch (adapter->hw.mac.type) {
2815 case ixgbe_mac_82598EB: {
2816 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2817 const int mask = feature[RING_F_RSS].mask;
2818 reg_idx = reg_idx & mask;
2819 }
2820 break;
2821 case ixgbe_mac_82599EB:
2822 case ixgbe_mac_X540:
2823 default:
2824 break;
2825 }
2826
2827 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2828
2829 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2830 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2831 if (adapter->num_vfs)
2832 srrctl |= IXGBE_SRRCTL_DROP_EN;
2833
2834 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2835 IXGBE_SRRCTL_BSIZEHDR_MASK;
2836
2837 if (ring_is_ps_enabled(rx_ring)) {
2838 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2839 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2840 #else
2841 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2842 #endif
2843 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2844 } else {
2845 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2846 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2847 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2848 }
2849
2850 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2851 }
2852
2853 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2854 {
2855 struct ixgbe_hw *hw = &adapter->hw;
2856 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2857 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2858 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2859 u32 mrqc = 0, reta = 0;
2860 u32 rxcsum;
2861 int i, j;
2862 int mask;
2863
2864 /* Fill out hash function seeds */
2865 for (i = 0; i < 10; i++)
2866 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2867
2868 /* Fill out redirection table */
2869 for (i = 0, j = 0; i < 128; i++, j++) {
2870 if (j == adapter->ring_feature[RING_F_RSS].indices)
2871 j = 0;
2872 /* reta = 4-byte sliding window of
2873 * 0x00..(indices-1)(indices-1)00..etc. */
2874 reta = (reta << 8) | (j * 0x11);
2875 if ((i & 3) == 3)
2876 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2877 }
2878
2879 /* Disable indicating checksum in descriptor, enables RSS hash */
2880 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2881 rxcsum |= IXGBE_RXCSUM_PCSD;
2882 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2883
2884 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2885 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2886 else
2887 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2888 #ifdef CONFIG_IXGBE_DCB
2889 | IXGBE_FLAG_DCB_ENABLED
2890 #endif
2891 | IXGBE_FLAG_SRIOV_ENABLED
2892 );
2893
2894 switch (mask) {
2895 case (IXGBE_FLAG_RSS_ENABLED):
2896 mrqc = IXGBE_MRQC_RSSEN;
2897 break;
2898 case (IXGBE_FLAG_SRIOV_ENABLED):
2899 mrqc = IXGBE_MRQC_VMDQEN;
2900 break;
2901 #ifdef CONFIG_IXGBE_DCB
2902 case (IXGBE_FLAG_DCB_ENABLED):
2903 mrqc = IXGBE_MRQC_RT8TCEN;
2904 break;
2905 #endif /* CONFIG_IXGBE_DCB */
2906 default:
2907 break;
2908 }
2909
2910 /* Perform hash on these packet types */
2911 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2912 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2913 | IXGBE_MRQC_RSS_FIELD_IPV6
2914 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2915
2916 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2917 }
2918
2919 /**
2920 * ixgbe_clear_rscctl - disable RSC for the indicated ring
2921 * @adapter: address of board private structure
2922 * @ring: structure containing ring specific data
2923 **/
2924 void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
2925 struct ixgbe_ring *ring)
2926 {
2927 struct ixgbe_hw *hw = &adapter->hw;
2928 u32 rscctrl;
2929 u8 reg_idx = ring->reg_idx;
2930
2931 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2932 rscctrl &= ~IXGBE_RSCCTL_RSCEN;
2933 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2934 }
2935
2936 /**
2937 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2938 * @adapter: address of board private structure
2939 * @index: index of ring to set
2940 **/
2941 void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2942 struct ixgbe_ring *ring)
2943 {
2944 struct ixgbe_hw *hw = &adapter->hw;
2945 u32 rscctrl;
2946 int rx_buf_len;
2947 u8 reg_idx = ring->reg_idx;
2948
2949 if (!ring_is_rsc_enabled(ring))
2950 return;
2951
2952 rx_buf_len = ring->rx_buf_len;
2953 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2954 rscctrl |= IXGBE_RSCCTL_RSCEN;
2955 /*
2956 * we must limit the number of descriptors so that the
2957 * total size of max desc * buf_len is not greater
2958 * than 65535
2959 */
2960 if (ring_is_ps_enabled(ring)) {
2961 #if (MAX_SKB_FRAGS > 16)
2962 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2963 #elif (MAX_SKB_FRAGS > 8)
2964 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2965 #elif (MAX_SKB_FRAGS > 4)
2966 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2967 #else
2968 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2969 #endif
2970 } else {
2971 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2972 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2973 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2974 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2975 else
2976 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2977 }
2978 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2979 }
2980
2981 /**
2982 * ixgbe_set_uta - Set unicast filter table address
2983 * @adapter: board private structure
2984 *
2985 * The unicast table address is a register array of 32-bit registers.
2986 * The table is meant to be used in a way similar to how the MTA is used
2987 * however due to certain limitations in the hardware it is necessary to
2988 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2989 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2990 **/
2991 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2992 {
2993 struct ixgbe_hw *hw = &adapter->hw;
2994 int i;
2995
2996 /* The UTA table only exists on 82599 hardware and newer */
2997 if (hw->mac.type < ixgbe_mac_82599EB)
2998 return;
2999
3000 /* we only need to do this if VMDq is enabled */
3001 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3002 return;
3003
3004 for (i = 0; i < 128; i++)
3005 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3006 }
3007
3008 #define IXGBE_MAX_RX_DESC_POLL 10
3009 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3010 struct ixgbe_ring *ring)
3011 {
3012 struct ixgbe_hw *hw = &adapter->hw;
3013 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3014 u32 rxdctl;
3015 u8 reg_idx = ring->reg_idx;
3016
3017 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3018 if (hw->mac.type == ixgbe_mac_82598EB &&
3019 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3020 return;
3021
3022 do {
3023 msleep(1);
3024 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3025 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3026
3027 if (!wait_loop) {
3028 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3029 "the polling period\n", reg_idx);
3030 }
3031 }
3032
3033 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3034 struct ixgbe_ring *ring)
3035 {
3036 struct ixgbe_hw *hw = &adapter->hw;
3037 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3038 u32 rxdctl;
3039 u8 reg_idx = ring->reg_idx;
3040
3041 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3042 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3043
3044 /* write value back with RXDCTL.ENABLE bit cleared */
3045 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3046
3047 if (hw->mac.type == ixgbe_mac_82598EB &&
3048 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3049 return;
3050
3051 /* the hardware may take up to 100us to really disable the rx queue */
3052 do {
3053 udelay(10);
3054 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3055 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3056
3057 if (!wait_loop) {
3058 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3059 "the polling period\n", reg_idx);
3060 }
3061 }
3062
3063 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3064 struct ixgbe_ring *ring)
3065 {
3066 struct ixgbe_hw *hw = &adapter->hw;
3067 u64 rdba = ring->dma;
3068 u32 rxdctl;
3069 u8 reg_idx = ring->reg_idx;
3070
3071 /* disable queue to avoid issues while updating state */
3072 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3073 ixgbe_disable_rx_queue(adapter, ring);
3074
3075 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3076 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3077 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3078 ring->count * sizeof(union ixgbe_adv_rx_desc));
3079 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3080 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3081 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3082
3083 ixgbe_configure_srrctl(adapter, ring);
3084 ixgbe_configure_rscctl(adapter, ring);
3085
3086 /* If operating in IOV mode set RLPML for X540 */
3087 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3088 hw->mac.type == ixgbe_mac_X540) {
3089 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3090 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3091 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3092 }
3093
3094 if (hw->mac.type == ixgbe_mac_82598EB) {
3095 /*
3096 * enable cache line friendly hardware writes:
3097 * PTHRESH=32 descriptors (half the internal cache),
3098 * this also removes ugly rx_no_buffer_count increment
3099 * HTHRESH=4 descriptors (to minimize latency on fetch)
3100 * WTHRESH=8 burst writeback up to two cache lines
3101 */
3102 rxdctl &= ~0x3FFFFF;
3103 rxdctl |= 0x080420;
3104 }
3105
3106 /* enable receive descriptor ring */
3107 rxdctl |= IXGBE_RXDCTL_ENABLE;
3108 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3109
3110 ixgbe_rx_desc_queue_enable(adapter, ring);
3111 ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
3112 }
3113
3114 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3115 {
3116 struct ixgbe_hw *hw = &adapter->hw;
3117 int p;
3118
3119 /* PSRTYPE must be initialized in non 82598 adapters */
3120 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3121 IXGBE_PSRTYPE_UDPHDR |
3122 IXGBE_PSRTYPE_IPV4HDR |
3123 IXGBE_PSRTYPE_L2HDR |
3124 IXGBE_PSRTYPE_IPV6HDR;
3125
3126 if (hw->mac.type == ixgbe_mac_82598EB)
3127 return;
3128
3129 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3130 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3131
3132 for (p = 0; p < adapter->num_rx_pools; p++)
3133 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3134 psrtype);
3135 }
3136
3137 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3138 {
3139 struct ixgbe_hw *hw = &adapter->hw;
3140 u32 gcr_ext;
3141 u32 vt_reg_bits;
3142 u32 reg_offset, vf_shift;
3143 u32 vmdctl;
3144
3145 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3146 return;
3147
3148 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3149 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3150 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3151 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3152
3153 vf_shift = adapter->num_vfs % 32;
3154 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3155
3156 /* Enable only the PF's pool for Tx/Rx */
3157 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3158 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3159 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3160 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3161 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3162
3163 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3164 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3165
3166 /*
3167 * Set up VF register offsets for selected VT Mode,
3168 * i.e. 32 or 64 VFs for SR-IOV
3169 */
3170 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3171 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3172 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3173 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3174
3175 /* enable Tx loopback for VF/PF communication */
3176 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3177 /* Enable MAC Anti-Spoofing */
3178 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3179 adapter->num_vfs);
3180 }
3181
3182 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3183 {
3184 struct ixgbe_hw *hw = &adapter->hw;
3185 struct net_device *netdev = adapter->netdev;
3186 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3187 int rx_buf_len;
3188 struct ixgbe_ring *rx_ring;
3189 int i;
3190 u32 mhadd, hlreg0;
3191
3192 /* Decide whether to use packet split mode or not */
3193 /* On by default */
3194 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3195
3196 /* Do not use packet split if we're in SR-IOV Mode */
3197 if (adapter->num_vfs)
3198 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3199
3200 /* Disable packet split due to 82599 erratum #45 */
3201 if (hw->mac.type == ixgbe_mac_82599EB)
3202 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3203
3204 /* Set the RX buffer length according to the mode */
3205 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3206 rx_buf_len = IXGBE_RX_HDR_SIZE;
3207 } else {
3208 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3209 (netdev->mtu <= ETH_DATA_LEN))
3210 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3211 else
3212 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
3213 }
3214
3215 #ifdef IXGBE_FCOE
3216 /* adjust max frame to be able to do baby jumbo for FCoE */
3217 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3218 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3219 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3220
3221 #endif /* IXGBE_FCOE */
3222 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3223 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3224 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3225 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3226
3227 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3228 }
3229
3230 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3231 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3232 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3233 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3234
3235 /*
3236 * Setup the HW Rx Head and Tail Descriptor Pointers and
3237 * the Base and Length of the Rx Descriptor Ring
3238 */
3239 for (i = 0; i < adapter->num_rx_queues; i++) {
3240 rx_ring = adapter->rx_ring[i];
3241 rx_ring->rx_buf_len = rx_buf_len;
3242
3243 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
3244 set_ring_ps_enabled(rx_ring);
3245 else
3246 clear_ring_ps_enabled(rx_ring);
3247
3248 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3249 set_ring_rsc_enabled(rx_ring);
3250 else
3251 clear_ring_rsc_enabled(rx_ring);
3252
3253 #ifdef IXGBE_FCOE
3254 if (netdev->features & NETIF_F_FCOE_MTU) {
3255 struct ixgbe_ring_feature *f;
3256 f = &adapter->ring_feature[RING_F_FCOE];
3257 if ((i >= f->mask) && (i < f->mask + f->indices)) {
3258 clear_ring_ps_enabled(rx_ring);
3259 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3260 rx_ring->rx_buf_len =
3261 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3262 } else if (!ring_is_rsc_enabled(rx_ring) &&
3263 !ring_is_ps_enabled(rx_ring)) {
3264 rx_ring->rx_buf_len =
3265 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3266 }
3267 }
3268 #endif /* IXGBE_FCOE */
3269 }
3270 }
3271
3272 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3273 {
3274 struct ixgbe_hw *hw = &adapter->hw;
3275 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3276
3277 switch (hw->mac.type) {
3278 case ixgbe_mac_82598EB:
3279 /*
3280 * For VMDq support of different descriptor types or
3281 * buffer sizes through the use of multiple SRRCTL
3282 * registers, RDRXCTL.MVMEN must be set to 1
3283 *
3284 * also, the manual doesn't mention it clearly but DCA hints
3285 * will only use queue 0's tags unless this bit is set. Side
3286 * effects of setting this bit are only that SRRCTL must be
3287 * fully programmed [0..15]
3288 */
3289 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3290 break;
3291 case ixgbe_mac_82599EB:
3292 case ixgbe_mac_X540:
3293 /* Disable RSC for ACK packets */
3294 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3295 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3296 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3297 /* hardware requires some bits to be set by default */
3298 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3299 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3300 break;
3301 default:
3302 /* We should do nothing since we don't know this hardware */
3303 return;
3304 }
3305
3306 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3307 }
3308
3309 /**
3310 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3311 * @adapter: board private structure
3312 *
3313 * Configure the Rx unit of the MAC after a reset.
3314 **/
3315 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3316 {
3317 struct ixgbe_hw *hw = &adapter->hw;
3318 int i;
3319 u32 rxctrl;
3320
3321 /* disable receives while setting up the descriptors */
3322 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3323 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3324
3325 ixgbe_setup_psrtype(adapter);
3326 ixgbe_setup_rdrxctl(adapter);
3327
3328 /* Program registers for the distribution of queues */
3329 ixgbe_setup_mrqc(adapter);
3330
3331 ixgbe_set_uta(adapter);
3332
3333 /* set_rx_buffer_len must be called before ring initialization */
3334 ixgbe_set_rx_buffer_len(adapter);
3335
3336 /*
3337 * Setup the HW Rx Head and Tail Descriptor Pointers and
3338 * the Base and Length of the Rx Descriptor Ring
3339 */
3340 for (i = 0; i < adapter->num_rx_queues; i++)
3341 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3342
3343 /* disable drop enable for 82598 parts */
3344 if (hw->mac.type == ixgbe_mac_82598EB)
3345 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3346
3347 /* enable all receives */
3348 rxctrl |= IXGBE_RXCTRL_RXEN;
3349 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3350 }
3351
3352 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3353 {
3354 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3355 struct ixgbe_hw *hw = &adapter->hw;
3356 int pool_ndx = adapter->num_vfs;
3357
3358 /* add VID to filter table */
3359 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3360 set_bit(vid, adapter->active_vlans);
3361 }
3362
3363 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3364 {
3365 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3366 struct ixgbe_hw *hw = &adapter->hw;
3367 int pool_ndx = adapter->num_vfs;
3368
3369 /* remove VID from filter table */
3370 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3371 clear_bit(vid, adapter->active_vlans);
3372 }
3373
3374 /**
3375 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3376 * @adapter: driver data
3377 */
3378 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3379 {
3380 struct ixgbe_hw *hw = &adapter->hw;
3381 u32 vlnctrl;
3382
3383 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3384 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3385 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3386 }
3387
3388 /**
3389 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3390 * @adapter: driver data
3391 */
3392 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3393 {
3394 struct ixgbe_hw *hw = &adapter->hw;
3395 u32 vlnctrl;
3396
3397 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3398 vlnctrl |= IXGBE_VLNCTRL_VFE;
3399 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3400 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3401 }
3402
3403 /**
3404 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3405 * @adapter: driver data
3406 */
3407 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3408 {
3409 struct ixgbe_hw *hw = &adapter->hw;
3410 u32 vlnctrl;
3411 int i, j;
3412
3413 switch (hw->mac.type) {
3414 case ixgbe_mac_82598EB:
3415 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3416 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3417 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3418 break;
3419 case ixgbe_mac_82599EB:
3420 case ixgbe_mac_X540:
3421 for (i = 0; i < adapter->num_rx_queues; i++) {
3422 j = adapter->rx_ring[i]->reg_idx;
3423 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3424 vlnctrl &= ~IXGBE_RXDCTL_VME;
3425 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3426 }
3427 break;
3428 default:
3429 break;
3430 }
3431 }
3432
3433 /**
3434 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3435 * @adapter: driver data
3436 */
3437 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3438 {
3439 struct ixgbe_hw *hw = &adapter->hw;
3440 u32 vlnctrl;
3441 int i, j;
3442
3443 switch (hw->mac.type) {
3444 case ixgbe_mac_82598EB:
3445 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3446 vlnctrl |= IXGBE_VLNCTRL_VME;
3447 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3448 break;
3449 case ixgbe_mac_82599EB:
3450 case ixgbe_mac_X540:
3451 for (i = 0; i < adapter->num_rx_queues; i++) {
3452 j = adapter->rx_ring[i]->reg_idx;
3453 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3454 vlnctrl |= IXGBE_RXDCTL_VME;
3455 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3456 }
3457 break;
3458 default:
3459 break;
3460 }
3461 }
3462
3463 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3464 {
3465 u16 vid;
3466
3467 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3468
3469 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3470 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3471 }
3472
3473 /**
3474 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3475 * @netdev: network interface device structure
3476 *
3477 * Writes unicast address list to the RAR table.
3478 * Returns: -ENOMEM on failure/insufficient address space
3479 * 0 on no addresses written
3480 * X on writing X addresses to the RAR table
3481 **/
3482 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3483 {
3484 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3485 struct ixgbe_hw *hw = &adapter->hw;
3486 unsigned int vfn = adapter->num_vfs;
3487 unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3488 int count = 0;
3489
3490 /* return ENOMEM indicating insufficient memory for addresses */
3491 if (netdev_uc_count(netdev) > rar_entries)
3492 return -ENOMEM;
3493
3494 if (!netdev_uc_empty(netdev) && rar_entries) {
3495 struct netdev_hw_addr *ha;
3496 /* return error if we do not support writing to RAR table */
3497 if (!hw->mac.ops.set_rar)
3498 return -ENOMEM;
3499
3500 netdev_for_each_uc_addr(ha, netdev) {
3501 if (!rar_entries)
3502 break;
3503 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3504 vfn, IXGBE_RAH_AV);
3505 count++;
3506 }
3507 }
3508 /* write the addresses in reverse order to avoid write combining */
3509 for (; rar_entries > 0 ; rar_entries--)
3510 hw->mac.ops.clear_rar(hw, rar_entries);
3511
3512 return count;
3513 }
3514
3515 /**
3516 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3517 * @netdev: network interface device structure
3518 *
3519 * The set_rx_method entry point is called whenever the unicast/multicast
3520 * address list or the network interface flags are updated. This routine is
3521 * responsible for configuring the hardware for proper unicast, multicast and
3522 * promiscuous mode.
3523 **/
3524 void ixgbe_set_rx_mode(struct net_device *netdev)
3525 {
3526 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3527 struct ixgbe_hw *hw = &adapter->hw;
3528 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3529 int count;
3530
3531 /* Check for Promiscuous and All Multicast modes */
3532
3533 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3534
3535 /* set all bits that we expect to always be set */
3536 fctrl |= IXGBE_FCTRL_BAM;
3537 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3538 fctrl |= IXGBE_FCTRL_PMCF;
3539
3540 /* clear the bits we are changing the status of */
3541 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3542
3543 if (netdev->flags & IFF_PROMISC) {
3544 hw->addr_ctrl.user_set_promisc = true;
3545 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3546 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3547 /* don't hardware filter vlans in promisc mode */
3548 ixgbe_vlan_filter_disable(adapter);
3549 } else {
3550 if (netdev->flags & IFF_ALLMULTI) {
3551 fctrl |= IXGBE_FCTRL_MPE;
3552 vmolr |= IXGBE_VMOLR_MPE;
3553 } else {
3554 /*
3555 * Write addresses to the MTA, if the attempt fails
3556 * then we should just turn on promiscous mode so
3557 * that we can at least receive multicast traffic
3558 */
3559 hw->mac.ops.update_mc_addr_list(hw, netdev);
3560 vmolr |= IXGBE_VMOLR_ROMPE;
3561 }
3562 ixgbe_vlan_filter_enable(adapter);
3563 hw->addr_ctrl.user_set_promisc = false;
3564 /*
3565 * Write addresses to available RAR registers, if there is not
3566 * sufficient space to store all the addresses then enable
3567 * unicast promiscous mode
3568 */
3569 count = ixgbe_write_uc_addr_list(netdev);
3570 if (count < 0) {
3571 fctrl |= IXGBE_FCTRL_UPE;
3572 vmolr |= IXGBE_VMOLR_ROPE;
3573 }
3574 }
3575
3576 if (adapter->num_vfs) {
3577 ixgbe_restore_vf_multicasts(adapter);
3578 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3579 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3580 IXGBE_VMOLR_ROPE);
3581 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3582 }
3583
3584 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3585
3586 if (netdev->features & NETIF_F_HW_VLAN_RX)
3587 ixgbe_vlan_strip_enable(adapter);
3588 else
3589 ixgbe_vlan_strip_disable(adapter);
3590 }
3591
3592 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3593 {
3594 int q_idx;
3595 struct ixgbe_q_vector *q_vector;
3596 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3597
3598 /* legacy and MSI only use one vector */
3599 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3600 q_vectors = 1;
3601
3602 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3603 struct napi_struct *napi;
3604 q_vector = adapter->q_vector[q_idx];
3605 napi = &q_vector->napi;
3606 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3607 if (!q_vector->rxr_count || !q_vector->txr_count) {
3608 if (q_vector->txr_count == 1)
3609 napi->poll = &ixgbe_clean_txonly;
3610 else if (q_vector->rxr_count == 1)
3611 napi->poll = &ixgbe_clean_rxonly;
3612 }
3613 }
3614
3615 napi_enable(napi);
3616 }
3617 }
3618
3619 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3620 {
3621 int q_idx;
3622 struct ixgbe_q_vector *q_vector;
3623 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3624
3625 /* legacy and MSI only use one vector */
3626 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3627 q_vectors = 1;
3628
3629 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3630 q_vector = adapter->q_vector[q_idx];
3631 napi_disable(&q_vector->napi);
3632 }
3633 }
3634
3635 #ifdef CONFIG_IXGBE_DCB
3636 /*
3637 * ixgbe_configure_dcb - Configure DCB hardware
3638 * @adapter: ixgbe adapter struct
3639 *
3640 * This is called by the driver on open to configure the DCB hardware.
3641 * This is also called by the gennetlink interface when reconfiguring
3642 * the DCB state.
3643 */
3644 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3645 {
3646 struct ixgbe_hw *hw = &adapter->hw;
3647 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3648
3649 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3650 if (hw->mac.type == ixgbe_mac_82598EB)
3651 netif_set_gso_max_size(adapter->netdev, 65536);
3652 return;
3653 }
3654
3655 if (hw->mac.type == ixgbe_mac_82598EB)
3656 netif_set_gso_max_size(adapter->netdev, 32768);
3657
3658 #ifdef CONFIG_FCOE
3659 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3660 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3661 #endif
3662
3663 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3664 DCB_TX_CONFIG);
3665 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3666 DCB_RX_CONFIG);
3667
3668 /* Enable VLAN tag insert/strip */
3669 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3670
3671 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3672
3673 /* reconfigure the hardware */
3674 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3675 }
3676
3677 #endif
3678 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3679 {
3680 struct net_device *netdev = adapter->netdev;
3681 struct ixgbe_hw *hw = &adapter->hw;
3682 int i;
3683
3684 #ifdef CONFIG_IXGBE_DCB
3685 ixgbe_configure_dcb(adapter);
3686 #endif
3687
3688 ixgbe_set_rx_mode(netdev);
3689 ixgbe_restore_vlan(adapter);
3690
3691 #ifdef IXGBE_FCOE
3692 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3693 ixgbe_configure_fcoe(adapter);
3694
3695 #endif /* IXGBE_FCOE */
3696 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3697 for (i = 0; i < adapter->num_tx_queues; i++)
3698 adapter->tx_ring[i]->atr_sample_rate =
3699 adapter->atr_sample_rate;
3700 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3701 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3702 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3703 }
3704 ixgbe_configure_virtualization(adapter);
3705
3706 ixgbe_configure_tx(adapter);
3707 ixgbe_configure_rx(adapter);
3708 }
3709
3710 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3711 {
3712 switch (hw->phy.type) {
3713 case ixgbe_phy_sfp_avago:
3714 case ixgbe_phy_sfp_ftl:
3715 case ixgbe_phy_sfp_intel:
3716 case ixgbe_phy_sfp_unknown:
3717 case ixgbe_phy_sfp_passive_tyco:
3718 case ixgbe_phy_sfp_passive_unknown:
3719 case ixgbe_phy_sfp_active_unknown:
3720 case ixgbe_phy_sfp_ftl_active:
3721 return true;
3722 default:
3723 return false;
3724 }
3725 }
3726
3727 /**
3728 * ixgbe_sfp_link_config - set up SFP+ link
3729 * @adapter: pointer to private adapter struct
3730 **/
3731 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3732 {
3733 struct ixgbe_hw *hw = &adapter->hw;
3734
3735 if (hw->phy.multispeed_fiber) {
3736 /*
3737 * In multispeed fiber setups, the device may not have
3738 * had a physical connection when the driver loaded.
3739 * If that's the case, the initial link configuration
3740 * couldn't get the MAC into 10G or 1G mode, so we'll
3741 * never have a link status change interrupt fire.
3742 * We need to try and force an autonegotiation
3743 * session, then bring up link.
3744 */
3745 if (hw->mac.ops.setup_sfp)
3746 hw->mac.ops.setup_sfp(hw);
3747 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3748 schedule_work(&adapter->multispeed_fiber_task);
3749 } else {
3750 /*
3751 * Direct Attach Cu and non-multispeed fiber modules
3752 * still need to be configured properly prior to
3753 * attempting link.
3754 */
3755 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3756 schedule_work(&adapter->sfp_config_module_task);
3757 }
3758 }
3759
3760 /**
3761 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3762 * @hw: pointer to private hardware struct
3763 *
3764 * Returns 0 on success, negative on failure
3765 **/
3766 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3767 {
3768 u32 autoneg;
3769 bool negotiation, link_up = false;
3770 u32 ret = IXGBE_ERR_LINK_SETUP;
3771
3772 if (hw->mac.ops.check_link)
3773 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3774
3775 if (ret)
3776 goto link_cfg_out;
3777
3778 autoneg = hw->phy.autoneg_advertised;
3779 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3780 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3781 &negotiation);
3782 if (ret)
3783 goto link_cfg_out;
3784
3785 if (hw->mac.ops.setup_link)
3786 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3787 link_cfg_out:
3788 return ret;
3789 }
3790
3791 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3792 {
3793 struct ixgbe_hw *hw = &adapter->hw;
3794 u32 gpie = 0;
3795
3796 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3797 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3798 IXGBE_GPIE_OCD;
3799 gpie |= IXGBE_GPIE_EIAME;
3800 /*
3801 * use EIAM to auto-mask when MSI-X interrupt is asserted
3802 * this saves a register write for every interrupt
3803 */
3804 switch (hw->mac.type) {
3805 case ixgbe_mac_82598EB:
3806 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3807 break;
3808 case ixgbe_mac_82599EB:
3809 case ixgbe_mac_X540:
3810 default:
3811 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3812 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3813 break;
3814 }
3815 } else {
3816 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3817 * specifically only auto mask tx and rx interrupts */
3818 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3819 }
3820
3821 /* XXX: to interrupt immediately for EICS writes, enable this */
3822 /* gpie |= IXGBE_GPIE_EIMEN; */
3823
3824 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3825 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3826 gpie |= IXGBE_GPIE_VTMODE_64;
3827 }
3828
3829 /* Enable fan failure interrupt */
3830 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3831 gpie |= IXGBE_SDP1_GPIEN;
3832
3833 if (hw->mac.type == ixgbe_mac_82599EB)
3834 gpie |= IXGBE_SDP1_GPIEN;
3835 gpie |= IXGBE_SDP2_GPIEN;
3836
3837 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3838 }
3839
3840 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3841 {
3842 struct ixgbe_hw *hw = &adapter->hw;
3843 int err;
3844 u32 ctrl_ext;
3845
3846 ixgbe_get_hw_control(adapter);
3847 ixgbe_setup_gpie(adapter);
3848
3849 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3850 ixgbe_configure_msix(adapter);
3851 else
3852 ixgbe_configure_msi_and_legacy(adapter);
3853
3854 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3855 if (hw->mac.ops.enable_tx_laser &&
3856 ((hw->phy.multispeed_fiber) ||
3857 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3858 (hw->mac.type == ixgbe_mac_82599EB))))
3859 hw->mac.ops.enable_tx_laser(hw);
3860
3861 clear_bit(__IXGBE_DOWN, &adapter->state);
3862 ixgbe_napi_enable_all(adapter);
3863
3864 if (ixgbe_is_sfp(hw)) {
3865 ixgbe_sfp_link_config(adapter);
3866 } else {
3867 err = ixgbe_non_sfp_link_config(hw);
3868 if (err)
3869 e_err(probe, "link_config FAILED %d\n", err);
3870 }
3871
3872 /* clear any pending interrupts, may auto mask */
3873 IXGBE_READ_REG(hw, IXGBE_EICR);
3874 ixgbe_irq_enable(adapter, true, true);
3875
3876 /*
3877 * If this adapter has a fan, check to see if we had a failure
3878 * before we enabled the interrupt.
3879 */
3880 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3881 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3882 if (esdp & IXGBE_ESDP_SDP1)
3883 e_crit(drv, "Fan has stopped, replace the adapter\n");
3884 }
3885
3886 /*
3887 * For hot-pluggable SFP+ devices, a new SFP+ module may have
3888 * arrived before interrupts were enabled but after probe. Such
3889 * devices wouldn't have their type identified yet. We need to
3890 * kick off the SFP+ module setup first, then try to bring up link.
3891 * If we're not hot-pluggable SFP+, we just need to configure link
3892 * and bring it up.
3893 */
3894 if (hw->phy.type == ixgbe_phy_none)
3895 schedule_work(&adapter->sfp_config_module_task);
3896
3897 /* enable transmits */
3898 netif_tx_start_all_queues(adapter->netdev);
3899
3900 /* bring the link up in the watchdog, this could race with our first
3901 * link up interrupt but shouldn't be a problem */
3902 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3903 adapter->link_check_timeout = jiffies;
3904 mod_timer(&adapter->watchdog_timer, jiffies);
3905
3906 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3907 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3908 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3909 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3910
3911 return 0;
3912 }
3913
3914 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3915 {
3916 WARN_ON(in_interrupt());
3917 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3918 msleep(1);
3919 ixgbe_down(adapter);
3920 /*
3921 * If SR-IOV enabled then wait a bit before bringing the adapter
3922 * back up to give the VFs time to respond to the reset. The
3923 * two second wait is based upon the watchdog timer cycle in
3924 * the VF driver.
3925 */
3926 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3927 msleep(2000);
3928 ixgbe_up(adapter);
3929 clear_bit(__IXGBE_RESETTING, &adapter->state);
3930 }
3931
3932 int ixgbe_up(struct ixgbe_adapter *adapter)
3933 {
3934 /* hardware has been reset, we need to reload some things */
3935 ixgbe_configure(adapter);
3936
3937 return ixgbe_up_complete(adapter);
3938 }
3939
3940 void ixgbe_reset(struct ixgbe_adapter *adapter)
3941 {
3942 struct ixgbe_hw *hw = &adapter->hw;
3943 int err;
3944
3945 err = hw->mac.ops.init_hw(hw);
3946 switch (err) {
3947 case 0:
3948 case IXGBE_ERR_SFP_NOT_PRESENT:
3949 break;
3950 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3951 e_dev_err("master disable timed out\n");
3952 break;
3953 case IXGBE_ERR_EEPROM_VERSION:
3954 /* We are running on a pre-production device, log a warning */
3955 e_dev_warn("This device is a pre-production adapter/LOM. "
3956 "Please be aware there may be issuesassociated with "
3957 "your hardware. If you are experiencing problems "
3958 "please contact your Intel or hardware "
3959 "representative who provided you with this "
3960 "hardware.\n");
3961 break;
3962 default:
3963 e_dev_err("Hardware Error: %d\n", err);
3964 }
3965
3966 /* reprogram the RAR[0] in case user changed it. */
3967 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3968 IXGBE_RAH_AV);
3969 }
3970
3971 /**
3972 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3973 * @rx_ring: ring to free buffers from
3974 **/
3975 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3976 {
3977 struct device *dev = rx_ring->dev;
3978 unsigned long size;
3979 u16 i;
3980
3981 /* ring already cleared, nothing to do */
3982 if (!rx_ring->rx_buffer_info)
3983 return;
3984
3985 /* Free all the Rx ring sk_buffs */
3986 for (i = 0; i < rx_ring->count; i++) {
3987 struct ixgbe_rx_buffer *rx_buffer_info;
3988
3989 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3990 if (rx_buffer_info->dma) {
3991 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3992 rx_ring->rx_buf_len,
3993 DMA_FROM_DEVICE);
3994 rx_buffer_info->dma = 0;
3995 }
3996 if (rx_buffer_info->skb) {
3997 struct sk_buff *skb = rx_buffer_info->skb;
3998 rx_buffer_info->skb = NULL;
3999 do {
4000 struct sk_buff *this = skb;
4001 if (IXGBE_RSC_CB(this)->delay_unmap) {
4002 dma_unmap_single(dev,
4003 IXGBE_RSC_CB(this)->dma,
4004 rx_ring->rx_buf_len,
4005 DMA_FROM_DEVICE);
4006 IXGBE_RSC_CB(this)->dma = 0;
4007 IXGBE_RSC_CB(skb)->delay_unmap = false;
4008 }
4009 skb = skb->prev;
4010 dev_kfree_skb(this);
4011 } while (skb);
4012 }
4013 if (!rx_buffer_info->page)
4014 continue;
4015 if (rx_buffer_info->page_dma) {
4016 dma_unmap_page(dev, rx_buffer_info->page_dma,
4017 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4018 rx_buffer_info->page_dma = 0;
4019 }
4020 put_page(rx_buffer_info->page);
4021 rx_buffer_info->page = NULL;
4022 rx_buffer_info->page_offset = 0;
4023 }
4024
4025 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4026 memset(rx_ring->rx_buffer_info, 0, size);
4027
4028 /* Zero out the descriptor ring */
4029 memset(rx_ring->desc, 0, rx_ring->size);
4030
4031 rx_ring->next_to_clean = 0;
4032 rx_ring->next_to_use = 0;
4033 }
4034
4035 /**
4036 * ixgbe_clean_tx_ring - Free Tx Buffers
4037 * @tx_ring: ring to be cleaned
4038 **/
4039 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4040 {
4041 struct ixgbe_tx_buffer *tx_buffer_info;
4042 unsigned long size;
4043 u16 i;
4044
4045 /* ring already cleared, nothing to do */
4046 if (!tx_ring->tx_buffer_info)
4047 return;
4048
4049 /* Free all the Tx ring sk_buffs */
4050 for (i = 0; i < tx_ring->count; i++) {
4051 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4052 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4053 }
4054
4055 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4056 memset(tx_ring->tx_buffer_info, 0, size);
4057
4058 /* Zero out the descriptor ring */
4059 memset(tx_ring->desc, 0, tx_ring->size);
4060
4061 tx_ring->next_to_use = 0;
4062 tx_ring->next_to_clean = 0;
4063 }
4064
4065 /**
4066 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4067 * @adapter: board private structure
4068 **/
4069 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4070 {
4071 int i;
4072
4073 for (i = 0; i < adapter->num_rx_queues; i++)
4074 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4075 }
4076
4077 /**
4078 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4079 * @adapter: board private structure
4080 **/
4081 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4082 {
4083 int i;
4084
4085 for (i = 0; i < adapter->num_tx_queues; i++)
4086 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4087 }
4088
4089 void ixgbe_down(struct ixgbe_adapter *adapter)
4090 {
4091 struct net_device *netdev = adapter->netdev;
4092 struct ixgbe_hw *hw = &adapter->hw;
4093 u32 rxctrl;
4094 u32 txdctl;
4095 int i;
4096 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4097
4098 /* signal that we are down to the interrupt handler */
4099 set_bit(__IXGBE_DOWN, &adapter->state);
4100
4101 /* disable receive for all VFs and wait one second */
4102 if (adapter->num_vfs) {
4103 /* ping all the active vfs to let them know we are going down */
4104 ixgbe_ping_all_vfs(adapter);
4105
4106 /* Disable all VFTE/VFRE TX/RX */
4107 ixgbe_disable_tx_rx(adapter);
4108
4109 /* Mark all the VFs as inactive */
4110 for (i = 0 ; i < adapter->num_vfs; i++)
4111 adapter->vfinfo[i].clear_to_send = 0;
4112 }
4113
4114 /* disable receives */
4115 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4116 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4117
4118 /* disable all enabled rx queues */
4119 for (i = 0; i < adapter->num_rx_queues; i++)
4120 /* this call also flushes the previous write */
4121 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4122
4123 msleep(10);
4124
4125 netif_tx_stop_all_queues(netdev);
4126
4127 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4128 del_timer_sync(&adapter->sfp_timer);
4129 del_timer_sync(&adapter->watchdog_timer);
4130 cancel_work_sync(&adapter->watchdog_task);
4131
4132 netif_carrier_off(netdev);
4133 netif_tx_disable(netdev);
4134
4135 ixgbe_irq_disable(adapter);
4136
4137 ixgbe_napi_disable_all(adapter);
4138
4139 /* Cleanup the affinity_hint CPU mask memory and callback */
4140 for (i = 0; i < num_q_vectors; i++) {
4141 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4142 /* clear the affinity_mask in the IRQ descriptor */
4143 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4144 /* release the CPU mask memory */
4145 free_cpumask_var(q_vector->affinity_mask);
4146 }
4147
4148 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4149 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4150 cancel_work_sync(&adapter->fdir_reinit_task);
4151
4152 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4153 cancel_work_sync(&adapter->check_overtemp_task);
4154
4155 /* disable transmits in the hardware now that interrupts are off */
4156 for (i = 0; i < adapter->num_tx_queues; i++) {
4157 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4158 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
4159 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
4160 (txdctl & ~IXGBE_TXDCTL_ENABLE));
4161 }
4162 /* Disable the Tx DMA engine on 82599 */
4163 switch (hw->mac.type) {
4164 case ixgbe_mac_82599EB:
4165 case ixgbe_mac_X540:
4166 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4167 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4168 ~IXGBE_DMATXCTL_TE));
4169 break;
4170 default:
4171 break;
4172 }
4173
4174 /* clear n-tuple filters that are cached */
4175 ethtool_ntuple_flush(netdev);
4176
4177 if (!pci_channel_offline(adapter->pdev))
4178 ixgbe_reset(adapter);
4179
4180 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4181 if (hw->mac.ops.disable_tx_laser &&
4182 ((hw->phy.multispeed_fiber) ||
4183 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4184 (hw->mac.type == ixgbe_mac_82599EB))))
4185 hw->mac.ops.disable_tx_laser(hw);
4186
4187 ixgbe_clean_all_tx_rings(adapter);
4188 ixgbe_clean_all_rx_rings(adapter);
4189
4190 #ifdef CONFIG_IXGBE_DCA
4191 /* since we reset the hardware DCA settings were cleared */
4192 ixgbe_setup_dca(adapter);
4193 #endif
4194 }
4195
4196 /**
4197 * ixgbe_poll - NAPI Rx polling callback
4198 * @napi: structure for representing this polling device
4199 * @budget: how many packets driver is allowed to clean
4200 *
4201 * This function is used for legacy and MSI, NAPI mode
4202 **/
4203 static int ixgbe_poll(struct napi_struct *napi, int budget)
4204 {
4205 struct ixgbe_q_vector *q_vector =
4206 container_of(napi, struct ixgbe_q_vector, napi);
4207 struct ixgbe_adapter *adapter = q_vector->adapter;
4208 int tx_clean_complete, work_done = 0;
4209
4210 #ifdef CONFIG_IXGBE_DCA
4211 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4212 ixgbe_update_dca(q_vector);
4213 #endif
4214
4215 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4216 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
4217
4218 if (!tx_clean_complete)
4219 work_done = budget;
4220
4221 /* If budget not fully consumed, exit the polling mode */
4222 if (work_done < budget) {
4223 napi_complete(napi);
4224 if (adapter->rx_itr_setting & 1)
4225 ixgbe_set_itr(adapter);
4226 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4227 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
4228 }
4229 return work_done;
4230 }
4231
4232 /**
4233 * ixgbe_tx_timeout - Respond to a Tx Hang
4234 * @netdev: network interface device structure
4235 **/
4236 static void ixgbe_tx_timeout(struct net_device *netdev)
4237 {
4238 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4239
4240 adapter->tx_timeout_count++;
4241
4242 /* Do the reset outside of interrupt context */
4243 schedule_work(&adapter->reset_task);
4244 }
4245
4246 static void ixgbe_reset_task(struct work_struct *work)
4247 {
4248 struct ixgbe_adapter *adapter;
4249 adapter = container_of(work, struct ixgbe_adapter, reset_task);
4250
4251 /* If we're already down or resetting, just bail */
4252 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
4253 test_bit(__IXGBE_RESETTING, &adapter->state))
4254 return;
4255
4256 ixgbe_dump(adapter);
4257 netdev_err(adapter->netdev, "Reset adapter\n");
4258 ixgbe_reinit_locked(adapter);
4259 }
4260
4261 #ifdef CONFIG_IXGBE_DCB
4262 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4263 {
4264 bool ret = false;
4265 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
4266
4267 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4268 return ret;
4269
4270 f->mask = 0x7 << 3;
4271 adapter->num_rx_queues = f->indices;
4272 adapter->num_tx_queues = f->indices;
4273 ret = true;
4274
4275 return ret;
4276 }
4277 #endif
4278
4279 /**
4280 * ixgbe_set_rss_queues: Allocate queues for RSS
4281 * @adapter: board private structure to initialize
4282 *
4283 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4284 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4285 *
4286 **/
4287 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4288 {
4289 bool ret = false;
4290 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4291
4292 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4293 f->mask = 0xF;
4294 adapter->num_rx_queues = f->indices;
4295 adapter->num_tx_queues = f->indices;
4296 ret = true;
4297 } else {
4298 ret = false;
4299 }
4300
4301 return ret;
4302 }
4303
4304 /**
4305 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4306 * @adapter: board private structure to initialize
4307 *
4308 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4309 * to the original CPU that initiated the Tx session. This runs in addition
4310 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4311 * Rx load across CPUs using RSS.
4312 *
4313 **/
4314 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4315 {
4316 bool ret = false;
4317 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4318
4319 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4320 f_fdir->mask = 0;
4321
4322 /* Flow Director must have RSS enabled */
4323 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4324 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4325 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4326 adapter->num_tx_queues = f_fdir->indices;
4327 adapter->num_rx_queues = f_fdir->indices;
4328 ret = true;
4329 } else {
4330 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4331 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4332 }
4333 return ret;
4334 }
4335
4336 #ifdef IXGBE_FCOE
4337 /**
4338 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4339 * @adapter: board private structure to initialize
4340 *
4341 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4342 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4343 * rx queues out of the max number of rx queues, instead, it is used as the
4344 * index of the first rx queue used by FCoE.
4345 *
4346 **/
4347 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4348 {
4349 bool ret = false;
4350 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4351
4352 f->indices = min((int)num_online_cpus(), f->indices);
4353 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4354 adapter->num_rx_queues = 1;
4355 adapter->num_tx_queues = 1;
4356 #ifdef CONFIG_IXGBE_DCB
4357 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4358 e_info(probe, "FCoE enabled with DCB\n");
4359 ixgbe_set_dcb_queues(adapter);
4360 }
4361 #endif
4362 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4363 e_info(probe, "FCoE enabled with RSS\n");
4364 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4365 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4366 ixgbe_set_fdir_queues(adapter);
4367 else
4368 ixgbe_set_rss_queues(adapter);
4369 }
4370 /* adding FCoE rx rings to the end */
4371 f->mask = adapter->num_rx_queues;
4372 adapter->num_rx_queues += f->indices;
4373 adapter->num_tx_queues += f->indices;
4374
4375 ret = true;
4376 }
4377
4378 return ret;
4379 }
4380
4381 #endif /* IXGBE_FCOE */
4382 /**
4383 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4384 * @adapter: board private structure to initialize
4385 *
4386 * IOV doesn't actually use anything, so just NAK the
4387 * request for now and let the other queue routines
4388 * figure out what to do.
4389 */
4390 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4391 {
4392 return false;
4393 }
4394
4395 /*
4396 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4397 * @adapter: board private structure to initialize
4398 *
4399 * This is the top level queue allocation routine. The order here is very
4400 * important, starting with the "most" number of features turned on at once,
4401 * and ending with the smallest set of features. This way large combinations
4402 * can be allocated if they're turned on, and smaller combinations are the
4403 * fallthrough conditions.
4404 *
4405 **/
4406 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4407 {
4408 /* Start with base case */
4409 adapter->num_rx_queues = 1;
4410 adapter->num_tx_queues = 1;
4411 adapter->num_rx_pools = adapter->num_rx_queues;
4412 adapter->num_rx_queues_per_pool = 1;
4413
4414 if (ixgbe_set_sriov_queues(adapter))
4415 goto done;
4416
4417 #ifdef IXGBE_FCOE
4418 if (ixgbe_set_fcoe_queues(adapter))
4419 goto done;
4420
4421 #endif /* IXGBE_FCOE */
4422 #ifdef CONFIG_IXGBE_DCB
4423 if (ixgbe_set_dcb_queues(adapter))
4424 goto done;
4425
4426 #endif
4427 if (ixgbe_set_fdir_queues(adapter))
4428 goto done;
4429
4430 if (ixgbe_set_rss_queues(adapter))
4431 goto done;
4432
4433 /* fallback to base case */
4434 adapter->num_rx_queues = 1;
4435 adapter->num_tx_queues = 1;
4436
4437 done:
4438 /* Notify the stack of the (possibly) reduced queue counts. */
4439 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4440 return netif_set_real_num_rx_queues(adapter->netdev,
4441 adapter->num_rx_queues);
4442 }
4443
4444 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4445 int vectors)
4446 {
4447 int err, vector_threshold;
4448
4449 /* We'll want at least 3 (vector_threshold):
4450 * 1) TxQ[0] Cleanup
4451 * 2) RxQ[0] Cleanup
4452 * 3) Other (Link Status Change, etc.)
4453 * 4) TCP Timer (optional)
4454 */
4455 vector_threshold = MIN_MSIX_COUNT;
4456
4457 /* The more we get, the more we will assign to Tx/Rx Cleanup
4458 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4459 * Right now, we simply care about how many we'll get; we'll
4460 * set them up later while requesting irq's.
4461 */
4462 while (vectors >= vector_threshold) {
4463 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4464 vectors);
4465 if (!err) /* Success in acquiring all requested vectors. */
4466 break;
4467 else if (err < 0)
4468 vectors = 0; /* Nasty failure, quit now */
4469 else /* err == number of vectors we should try again with */
4470 vectors = err;
4471 }
4472
4473 if (vectors < vector_threshold) {
4474 /* Can't allocate enough MSI-X interrupts? Oh well.
4475 * This just means we'll go with either a single MSI
4476 * vector or fall back to legacy interrupts.
4477 */
4478 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4479 "Unable to allocate MSI-X interrupts\n");
4480 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4481 kfree(adapter->msix_entries);
4482 adapter->msix_entries = NULL;
4483 } else {
4484 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4485 /*
4486 * Adjust for only the vectors we'll use, which is minimum
4487 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4488 * vectors we were allocated.
4489 */
4490 adapter->num_msix_vectors = min(vectors,
4491 adapter->max_msix_q_vectors + NON_Q_VECTORS);
4492 }
4493 }
4494
4495 /**
4496 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4497 * @adapter: board private structure to initialize
4498 *
4499 * Cache the descriptor ring offsets for RSS to the assigned rings.
4500 *
4501 **/
4502 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4503 {
4504 int i;
4505
4506 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4507 return false;
4508
4509 for (i = 0; i < adapter->num_rx_queues; i++)
4510 adapter->rx_ring[i]->reg_idx = i;
4511 for (i = 0; i < adapter->num_tx_queues; i++)
4512 adapter->tx_ring[i]->reg_idx = i;
4513
4514 return true;
4515 }
4516
4517 #ifdef CONFIG_IXGBE_DCB
4518 /**
4519 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4520 * @adapter: board private structure to initialize
4521 *
4522 * Cache the descriptor ring offsets for DCB to the assigned rings.
4523 *
4524 **/
4525 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4526 {
4527 int i;
4528 bool ret = false;
4529 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4530
4531 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4532 return false;
4533
4534 /* the number of queues is assumed to be symmetric */
4535 switch (adapter->hw.mac.type) {
4536 case ixgbe_mac_82598EB:
4537 for (i = 0; i < dcb_i; i++) {
4538 adapter->rx_ring[i]->reg_idx = i << 3;
4539 adapter->tx_ring[i]->reg_idx = i << 2;
4540 }
4541 ret = true;
4542 break;
4543 case ixgbe_mac_82599EB:
4544 case ixgbe_mac_X540:
4545 if (dcb_i == 8) {
4546 /*
4547 * Tx TC0 starts at: descriptor queue 0
4548 * Tx TC1 starts at: descriptor queue 32
4549 * Tx TC2 starts at: descriptor queue 64
4550 * Tx TC3 starts at: descriptor queue 80
4551 * Tx TC4 starts at: descriptor queue 96
4552 * Tx TC5 starts at: descriptor queue 104
4553 * Tx TC6 starts at: descriptor queue 112
4554 * Tx TC7 starts at: descriptor queue 120
4555 *
4556 * Rx TC0-TC7 are offset by 16 queues each
4557 */
4558 for (i = 0; i < 3; i++) {
4559 adapter->tx_ring[i]->reg_idx = i << 5;
4560 adapter->rx_ring[i]->reg_idx = i << 4;
4561 }
4562 for ( ; i < 5; i++) {
4563 adapter->tx_ring[i]->reg_idx = ((i + 2) << 4);
4564 adapter->rx_ring[i]->reg_idx = i << 4;
4565 }
4566 for ( ; i < dcb_i; i++) {
4567 adapter->tx_ring[i]->reg_idx = ((i + 8) << 3);
4568 adapter->rx_ring[i]->reg_idx = i << 4;
4569 }
4570 ret = true;
4571 } else if (dcb_i == 4) {
4572 /*
4573 * Tx TC0 starts at: descriptor queue 0
4574 * Tx TC1 starts at: descriptor queue 64
4575 * Tx TC2 starts at: descriptor queue 96
4576 * Tx TC3 starts at: descriptor queue 112
4577 *
4578 * Rx TC0-TC3 are offset by 32 queues each
4579 */
4580 adapter->tx_ring[0]->reg_idx = 0;
4581 adapter->tx_ring[1]->reg_idx = 64;
4582 adapter->tx_ring[2]->reg_idx = 96;
4583 adapter->tx_ring[3]->reg_idx = 112;
4584 for (i = 0 ; i < dcb_i; i++)
4585 adapter->rx_ring[i]->reg_idx = i << 5;
4586 ret = true;
4587 }
4588 break;
4589 default:
4590 break;
4591 }
4592 return ret;
4593 }
4594 #endif
4595
4596 /**
4597 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4598 * @adapter: board private structure to initialize
4599 *
4600 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4601 *
4602 **/
4603 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4604 {
4605 int i;
4606 bool ret = false;
4607
4608 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4609 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4610 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4611 for (i = 0; i < adapter->num_rx_queues; i++)
4612 adapter->rx_ring[i]->reg_idx = i;
4613 for (i = 0; i < adapter->num_tx_queues; i++)
4614 adapter->tx_ring[i]->reg_idx = i;
4615 ret = true;
4616 }
4617
4618 return ret;
4619 }
4620
4621 #ifdef IXGBE_FCOE
4622 /**
4623 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4624 * @adapter: board private structure to initialize
4625 *
4626 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4627 *
4628 */
4629 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4630 {
4631 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4632 int i;
4633 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4634
4635 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4636 return false;
4637
4638 #ifdef CONFIG_IXGBE_DCB
4639 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4640 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4641
4642 ixgbe_cache_ring_dcb(adapter);
4643 /* find out queues in TC for FCoE */
4644 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4645 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4646 /*
4647 * In 82599, the number of Tx queues for each traffic
4648 * class for both 8-TC and 4-TC modes are:
4649 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4650 * 8 TCs: 32 32 16 16 8 8 8 8
4651 * 4 TCs: 64 64 32 32
4652 * We have max 8 queues for FCoE, where 8 the is
4653 * FCoE redirection table size. If TC for FCoE is
4654 * less than or equal to TC3, we have enough queues
4655 * to add max of 8 queues for FCoE, so we start FCoE
4656 * Tx queue from the next one, i.e., reg_idx + 1.
4657 * If TC for FCoE is above TC3, implying 8 TC mode,
4658 * and we need 8 for FCoE, we have to take all queues
4659 * in that traffic class for FCoE.
4660 */
4661 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4662 fcoe_tx_i--;
4663 }
4664 #endif /* CONFIG_IXGBE_DCB */
4665 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4666 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4667 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4668 ixgbe_cache_ring_fdir(adapter);
4669 else
4670 ixgbe_cache_ring_rss(adapter);
4671
4672 fcoe_rx_i = f->mask;
4673 fcoe_tx_i = f->mask;
4674 }
4675 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4676 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4677 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4678 }
4679 return true;
4680 }
4681
4682 #endif /* IXGBE_FCOE */
4683 /**
4684 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4685 * @adapter: board private structure to initialize
4686 *
4687 * SR-IOV doesn't use any descriptor rings but changes the default if
4688 * no other mapping is used.
4689 *
4690 */
4691 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4692 {
4693 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4694 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4695 if (adapter->num_vfs)
4696 return true;
4697 else
4698 return false;
4699 }
4700
4701 /**
4702 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4703 * @adapter: board private structure to initialize
4704 *
4705 * Once we know the feature-set enabled for the device, we'll cache
4706 * the register offset the descriptor ring is assigned to.
4707 *
4708 * Note, the order the various feature calls is important. It must start with
4709 * the "most" features enabled at the same time, then trickle down to the
4710 * least amount of features turned on at once.
4711 **/
4712 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4713 {
4714 /* start with default case */
4715 adapter->rx_ring[0]->reg_idx = 0;
4716 adapter->tx_ring[0]->reg_idx = 0;
4717
4718 if (ixgbe_cache_ring_sriov(adapter))
4719 return;
4720
4721 #ifdef IXGBE_FCOE
4722 if (ixgbe_cache_ring_fcoe(adapter))
4723 return;
4724
4725 #endif /* IXGBE_FCOE */
4726 #ifdef CONFIG_IXGBE_DCB
4727 if (ixgbe_cache_ring_dcb(adapter))
4728 return;
4729
4730 #endif
4731 if (ixgbe_cache_ring_fdir(adapter))
4732 return;
4733
4734 if (ixgbe_cache_ring_rss(adapter))
4735 return;
4736 }
4737
4738 /**
4739 * ixgbe_alloc_queues - Allocate memory for all rings
4740 * @adapter: board private structure to initialize
4741 *
4742 * We allocate one ring per queue at run-time since we don't know the
4743 * number of queues at compile-time. The polling_netdev array is
4744 * intended for Multiqueue, but should work fine with a single queue.
4745 **/
4746 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4747 {
4748 int rx = 0, tx = 0, nid = adapter->node;
4749
4750 if (nid < 0 || !node_online(nid))
4751 nid = first_online_node;
4752
4753 for (; tx < adapter->num_tx_queues; tx++) {
4754 struct ixgbe_ring *ring;
4755
4756 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4757 if (!ring)
4758 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4759 if (!ring)
4760 goto err_allocation;
4761 ring->count = adapter->tx_ring_count;
4762 ring->queue_index = tx;
4763 ring->numa_node = nid;
4764 ring->dev = &adapter->pdev->dev;
4765 ring->netdev = adapter->netdev;
4766
4767 adapter->tx_ring[tx] = ring;
4768 }
4769
4770 for (; rx < adapter->num_rx_queues; rx++) {
4771 struct ixgbe_ring *ring;
4772
4773 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4774 if (!ring)
4775 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4776 if (!ring)
4777 goto err_allocation;
4778 ring->count = adapter->rx_ring_count;
4779 ring->queue_index = rx;
4780 ring->numa_node = nid;
4781 ring->dev = &adapter->pdev->dev;
4782 ring->netdev = adapter->netdev;
4783
4784 adapter->rx_ring[rx] = ring;
4785 }
4786
4787 ixgbe_cache_ring_register(adapter);
4788
4789 return 0;
4790
4791 err_allocation:
4792 while (tx)
4793 kfree(adapter->tx_ring[--tx]);
4794
4795 while (rx)
4796 kfree(adapter->rx_ring[--rx]);
4797 return -ENOMEM;
4798 }
4799
4800 /**
4801 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4802 * @adapter: board private structure to initialize
4803 *
4804 * Attempt to configure the interrupts using the best available
4805 * capabilities of the hardware and the kernel.
4806 **/
4807 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4808 {
4809 struct ixgbe_hw *hw = &adapter->hw;
4810 int err = 0;
4811 int vector, v_budget;
4812
4813 /*
4814 * It's easy to be greedy for MSI-X vectors, but it really
4815 * doesn't do us much good if we have a lot more vectors
4816 * than CPU's. So let's be conservative and only ask for
4817 * (roughly) the same number of vectors as there are CPU's.
4818 */
4819 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4820 (int)num_online_cpus()) + NON_Q_VECTORS;
4821
4822 /*
4823 * At the same time, hardware can only support a maximum of
4824 * hw.mac->max_msix_vectors vectors. With features
4825 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4826 * descriptor queues supported by our device. Thus, we cap it off in
4827 * those rare cases where the cpu count also exceeds our vector limit.
4828 */
4829 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4830
4831 /* A failure in MSI-X entry allocation isn't fatal, but it does
4832 * mean we disable MSI-X capabilities of the adapter. */
4833 adapter->msix_entries = kcalloc(v_budget,
4834 sizeof(struct msix_entry), GFP_KERNEL);
4835 if (adapter->msix_entries) {
4836 for (vector = 0; vector < v_budget; vector++)
4837 adapter->msix_entries[vector].entry = vector;
4838
4839 ixgbe_acquire_msix_vectors(adapter, v_budget);
4840
4841 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4842 goto out;
4843 }
4844
4845 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4846 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4847 if (adapter->flags & (IXGBE_FLAG_FDIR_HASH_CAPABLE |
4848 IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
4849 e_err(probe,
4850 "Flow Director is not supported while multiple "
4851 "queues are disabled. Disabling Flow Director\n");
4852 }
4853 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4854 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4855 adapter->atr_sample_rate = 0;
4856 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4857 ixgbe_disable_sriov(adapter);
4858
4859 err = ixgbe_set_num_queues(adapter);
4860 if (err)
4861 return err;
4862
4863 err = pci_enable_msi(adapter->pdev);
4864 if (!err) {
4865 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4866 } else {
4867 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4868 "Unable to allocate MSI interrupt, "
4869 "falling back to legacy. Error: %d\n", err);
4870 /* reset err */
4871 err = 0;
4872 }
4873
4874 out:
4875 return err;
4876 }
4877
4878 /**
4879 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4880 * @adapter: board private structure to initialize
4881 *
4882 * We allocate one q_vector per queue interrupt. If allocation fails we
4883 * return -ENOMEM.
4884 **/
4885 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4886 {
4887 int q_idx, num_q_vectors;
4888 struct ixgbe_q_vector *q_vector;
4889 int (*poll)(struct napi_struct *, int);
4890
4891 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4892 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4893 poll = &ixgbe_clean_rxtx_many;
4894 } else {
4895 num_q_vectors = 1;
4896 poll = &ixgbe_poll;
4897 }
4898
4899 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4900 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4901 GFP_KERNEL, adapter->node);
4902 if (!q_vector)
4903 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4904 GFP_KERNEL);
4905 if (!q_vector)
4906 goto err_out;
4907 q_vector->adapter = adapter;
4908 if (q_vector->txr_count && !q_vector->rxr_count)
4909 q_vector->eitr = adapter->tx_eitr_param;
4910 else
4911 q_vector->eitr = adapter->rx_eitr_param;
4912 q_vector->v_idx = q_idx;
4913 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4914 adapter->q_vector[q_idx] = q_vector;
4915 }
4916
4917 return 0;
4918
4919 err_out:
4920 while (q_idx) {
4921 q_idx--;
4922 q_vector = adapter->q_vector[q_idx];
4923 netif_napi_del(&q_vector->napi);
4924 kfree(q_vector);
4925 adapter->q_vector[q_idx] = NULL;
4926 }
4927 return -ENOMEM;
4928 }
4929
4930 /**
4931 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4932 * @adapter: board private structure to initialize
4933 *
4934 * This function frees the memory allocated to the q_vectors. In addition if
4935 * NAPI is enabled it will delete any references to the NAPI struct prior
4936 * to freeing the q_vector.
4937 **/
4938 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4939 {
4940 int q_idx, num_q_vectors;
4941
4942 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4943 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4944 else
4945 num_q_vectors = 1;
4946
4947 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4948 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4949 adapter->q_vector[q_idx] = NULL;
4950 netif_napi_del(&q_vector->napi);
4951 kfree(q_vector);
4952 }
4953 }
4954
4955 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4956 {
4957 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4958 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4959 pci_disable_msix(adapter->pdev);
4960 kfree(adapter->msix_entries);
4961 adapter->msix_entries = NULL;
4962 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4963 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4964 pci_disable_msi(adapter->pdev);
4965 }
4966 }
4967
4968 /**
4969 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4970 * @adapter: board private structure to initialize
4971 *
4972 * We determine which interrupt scheme to use based on...
4973 * - Kernel support (MSI, MSI-X)
4974 * - which can be user-defined (via MODULE_PARAM)
4975 * - Hardware queue count (num_*_queues)
4976 * - defined by miscellaneous hardware support/features (RSS, etc.)
4977 **/
4978 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4979 {
4980 int err;
4981
4982 /* Number of supported queues */
4983 err = ixgbe_set_num_queues(adapter);
4984 if (err)
4985 return err;
4986
4987 err = ixgbe_set_interrupt_capability(adapter);
4988 if (err) {
4989 e_dev_err("Unable to setup interrupt capabilities\n");
4990 goto err_set_interrupt;
4991 }
4992
4993 err = ixgbe_alloc_q_vectors(adapter);
4994 if (err) {
4995 e_dev_err("Unable to allocate memory for queue vectors\n");
4996 goto err_alloc_q_vectors;
4997 }
4998
4999 err = ixgbe_alloc_queues(adapter);
5000 if (err) {
5001 e_dev_err("Unable to allocate memory for queues\n");
5002 goto err_alloc_queues;
5003 }
5004
5005 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
5006 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5007 adapter->num_rx_queues, adapter->num_tx_queues);
5008
5009 set_bit(__IXGBE_DOWN, &adapter->state);
5010
5011 return 0;
5012
5013 err_alloc_queues:
5014 ixgbe_free_q_vectors(adapter);
5015 err_alloc_q_vectors:
5016 ixgbe_reset_interrupt_capability(adapter);
5017 err_set_interrupt:
5018 return err;
5019 }
5020
5021 static void ring_free_rcu(struct rcu_head *head)
5022 {
5023 kfree(container_of(head, struct ixgbe_ring, rcu));
5024 }
5025
5026 /**
5027 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5028 * @adapter: board private structure to clear interrupt scheme on
5029 *
5030 * We go through and clear interrupt specific resources and reset the structure
5031 * to pre-load conditions
5032 **/
5033 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5034 {
5035 int i;
5036
5037 for (i = 0; i < adapter->num_tx_queues; i++) {
5038 kfree(adapter->tx_ring[i]);
5039 adapter->tx_ring[i] = NULL;
5040 }
5041 for (i = 0; i < adapter->num_rx_queues; i++) {
5042 struct ixgbe_ring *ring = adapter->rx_ring[i];
5043
5044 /* ixgbe_get_stats64() might access this ring, we must wait
5045 * a grace period before freeing it.
5046 */
5047 call_rcu(&ring->rcu, ring_free_rcu);
5048 adapter->rx_ring[i] = NULL;
5049 }
5050
5051 adapter->num_tx_queues = 0;
5052 adapter->num_rx_queues = 0;
5053
5054 ixgbe_free_q_vectors(adapter);
5055 ixgbe_reset_interrupt_capability(adapter);
5056 }
5057
5058 /**
5059 * ixgbe_sfp_timer - worker thread to find a missing module
5060 * @data: pointer to our adapter struct
5061 **/
5062 static void ixgbe_sfp_timer(unsigned long data)
5063 {
5064 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5065
5066 /*
5067 * Do the sfp_timer outside of interrupt context due to the
5068 * delays that sfp+ detection requires
5069 */
5070 schedule_work(&adapter->sfp_task);
5071 }
5072
5073 /**
5074 * ixgbe_sfp_task - worker thread to find a missing module
5075 * @work: pointer to work_struct containing our data
5076 **/
5077 static void ixgbe_sfp_task(struct work_struct *work)
5078 {
5079 struct ixgbe_adapter *adapter = container_of(work,
5080 struct ixgbe_adapter,
5081 sfp_task);
5082 struct ixgbe_hw *hw = &adapter->hw;
5083
5084 if ((hw->phy.type == ixgbe_phy_nl) &&
5085 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
5086 s32 ret = hw->phy.ops.identify_sfp(hw);
5087 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
5088 goto reschedule;
5089 ret = hw->phy.ops.reset(hw);
5090 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5091 e_dev_err("failed to initialize because an unsupported "
5092 "SFP+ module type was detected.\n");
5093 e_dev_err("Reload the driver after installing a "
5094 "supported module.\n");
5095 unregister_netdev(adapter->netdev);
5096 } else {
5097 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5098 }
5099 /* don't need this routine any more */
5100 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5101 }
5102 return;
5103 reschedule:
5104 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
5105 mod_timer(&adapter->sfp_timer,
5106 round_jiffies(jiffies + (2 * HZ)));
5107 }
5108
5109 /**
5110 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5111 * @adapter: board private structure to initialize
5112 *
5113 * ixgbe_sw_init initializes the Adapter private data structure.
5114 * Fields are initialized based on PCI device information and
5115 * OS network device settings (MTU size).
5116 **/
5117 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5118 {
5119 struct ixgbe_hw *hw = &adapter->hw;
5120 struct pci_dev *pdev = adapter->pdev;
5121 struct net_device *dev = adapter->netdev;
5122 unsigned int rss;
5123 #ifdef CONFIG_IXGBE_DCB
5124 int j;
5125 struct tc_configuration *tc;
5126 #endif
5127 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5128
5129 /* PCI config space info */
5130
5131 hw->vendor_id = pdev->vendor;
5132 hw->device_id = pdev->device;
5133 hw->revision_id = pdev->revision;
5134 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5135 hw->subsystem_device_id = pdev->subsystem_device;
5136
5137 /* Set capability flags */
5138 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5139 adapter->ring_feature[RING_F_RSS].indices = rss;
5140 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
5141 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
5142 switch (hw->mac.type) {
5143 case ixgbe_mac_82598EB:
5144 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5145 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5146 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
5147 break;
5148 case ixgbe_mac_82599EB:
5149 case ixgbe_mac_X540:
5150 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
5151 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5152 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5153 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5154 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5155 /* n-tuple support exists, always init our spinlock */
5156 spin_lock_init(&adapter->fdir_perfect_lock);
5157 /* Flow Director hash filters enabled */
5158 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5159 adapter->atr_sample_rate = 20;
5160 adapter->ring_feature[RING_F_FDIR].indices =
5161 IXGBE_MAX_FDIR_INDICES;
5162 adapter->fdir_pballoc = 0;
5163 #ifdef IXGBE_FCOE
5164 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5165 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5166 adapter->ring_feature[RING_F_FCOE].indices = 0;
5167 #ifdef CONFIG_IXGBE_DCB
5168 /* Default traffic class to use for FCoE */
5169 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
5170 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5171 #endif
5172 #endif /* IXGBE_FCOE */
5173 break;
5174 default:
5175 break;
5176 }
5177
5178 #ifdef CONFIG_IXGBE_DCB
5179 /* Configure DCB traffic classes */
5180 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5181 tc = &adapter->dcb_cfg.tc_config[j];
5182 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5183 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5184 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5185 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5186 tc->dcb_pfc = pfc_disabled;
5187 }
5188 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5189 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5190 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
5191 adapter->dcb_cfg.pfc_mode_enable = false;
5192 adapter->dcb_set_bitmap = 0x00;
5193 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5194 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5195 adapter->ring_feature[RING_F_DCB].indices);
5196
5197 #endif
5198
5199 /* default flow control settings */
5200 hw->fc.requested_mode = ixgbe_fc_full;
5201 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
5202 #ifdef CONFIG_DCB
5203 adapter->last_lfc_mode = hw->fc.current_mode;
5204 #endif
5205 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5206 hw->fc.low_water = FC_LOW_WATER(max_frame);
5207 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5208 hw->fc.send_xon = true;
5209 hw->fc.disable_fc_autoneg = false;
5210
5211 /* enable itr by default in dynamic mode */
5212 adapter->rx_itr_setting = 1;
5213 adapter->rx_eitr_param = 20000;
5214 adapter->tx_itr_setting = 1;
5215 adapter->tx_eitr_param = 10000;
5216
5217 /* set defaults for eitr in MegaBytes */
5218 adapter->eitr_low = 10;
5219 adapter->eitr_high = 20;
5220
5221 /* set default ring sizes */
5222 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5223 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5224
5225 /* initialize eeprom parameters */
5226 if (ixgbe_init_eeprom_params_generic(hw)) {
5227 e_dev_err("EEPROM initialization failed\n");
5228 return -EIO;
5229 }
5230
5231 /* enable rx csum by default */
5232 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5233
5234 /* get assigned NUMA node */
5235 adapter->node = dev_to_node(&pdev->dev);
5236
5237 set_bit(__IXGBE_DOWN, &adapter->state);
5238
5239 return 0;
5240 }
5241
5242 /**
5243 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5244 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5245 *
5246 * Return 0 on success, negative on failure
5247 **/
5248 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5249 {
5250 struct device *dev = tx_ring->dev;
5251 int size;
5252
5253 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5254 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
5255 if (!tx_ring->tx_buffer_info)
5256 tx_ring->tx_buffer_info = vzalloc(size);
5257 if (!tx_ring->tx_buffer_info)
5258 goto err;
5259
5260 /* round up to nearest 4K */
5261 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5262 tx_ring->size = ALIGN(tx_ring->size, 4096);
5263
5264 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5265 &tx_ring->dma, GFP_KERNEL);
5266 if (!tx_ring->desc)
5267 goto err;
5268
5269 tx_ring->next_to_use = 0;
5270 tx_ring->next_to_clean = 0;
5271 tx_ring->work_limit = tx_ring->count;
5272 return 0;
5273
5274 err:
5275 vfree(tx_ring->tx_buffer_info);
5276 tx_ring->tx_buffer_info = NULL;
5277 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5278 return -ENOMEM;
5279 }
5280
5281 /**
5282 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5283 * @adapter: board private structure
5284 *
5285 * If this function returns with an error, then it's possible one or
5286 * more of the rings is populated (while the rest are not). It is the
5287 * callers duty to clean those orphaned rings.
5288 *
5289 * Return 0 on success, negative on failure
5290 **/
5291 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5292 {
5293 int i, err = 0;
5294
5295 for (i = 0; i < adapter->num_tx_queues; i++) {
5296 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5297 if (!err)
5298 continue;
5299 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5300 break;
5301 }
5302
5303 return err;
5304 }
5305
5306 /**
5307 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5308 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5309 *
5310 * Returns 0 on success, negative on failure
5311 **/
5312 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5313 {
5314 struct device *dev = rx_ring->dev;
5315 int size;
5316
5317 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5318 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5319 if (!rx_ring->rx_buffer_info)
5320 rx_ring->rx_buffer_info = vzalloc(size);
5321 if (!rx_ring->rx_buffer_info)
5322 goto err;
5323
5324 /* Round up to nearest 4K */
5325 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5326 rx_ring->size = ALIGN(rx_ring->size, 4096);
5327
5328 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5329 &rx_ring->dma, GFP_KERNEL);
5330
5331 if (!rx_ring->desc)
5332 goto err;
5333
5334 rx_ring->next_to_clean = 0;
5335 rx_ring->next_to_use = 0;
5336
5337 return 0;
5338 err:
5339 vfree(rx_ring->rx_buffer_info);
5340 rx_ring->rx_buffer_info = NULL;
5341 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5342 return -ENOMEM;
5343 }
5344
5345 /**
5346 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5347 * @adapter: board private structure
5348 *
5349 * If this function returns with an error, then it's possible one or
5350 * more of the rings is populated (while the rest are not). It is the
5351 * callers duty to clean those orphaned rings.
5352 *
5353 * Return 0 on success, negative on failure
5354 **/
5355 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5356 {
5357 int i, err = 0;
5358
5359 for (i = 0; i < adapter->num_rx_queues; i++) {
5360 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5361 if (!err)
5362 continue;
5363 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5364 break;
5365 }
5366
5367 return err;
5368 }
5369
5370 /**
5371 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5372 * @tx_ring: Tx descriptor ring for a specific queue
5373 *
5374 * Free all transmit software resources
5375 **/
5376 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5377 {
5378 ixgbe_clean_tx_ring(tx_ring);
5379
5380 vfree(tx_ring->tx_buffer_info);
5381 tx_ring->tx_buffer_info = NULL;
5382
5383 /* if not set, then don't free */
5384 if (!tx_ring->desc)
5385 return;
5386
5387 dma_free_coherent(tx_ring->dev, tx_ring->size,
5388 tx_ring->desc, tx_ring->dma);
5389
5390 tx_ring->desc = NULL;
5391 }
5392
5393 /**
5394 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5395 * @adapter: board private structure
5396 *
5397 * Free all transmit software resources
5398 **/
5399 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5400 {
5401 int i;
5402
5403 for (i = 0; i < adapter->num_tx_queues; i++)
5404 if (adapter->tx_ring[i]->desc)
5405 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5406 }
5407
5408 /**
5409 * ixgbe_free_rx_resources - Free Rx Resources
5410 * @rx_ring: ring to clean the resources from
5411 *
5412 * Free all receive software resources
5413 **/
5414 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5415 {
5416 ixgbe_clean_rx_ring(rx_ring);
5417
5418 vfree(rx_ring->rx_buffer_info);
5419 rx_ring->rx_buffer_info = NULL;
5420
5421 /* if not set, then don't free */
5422 if (!rx_ring->desc)
5423 return;
5424
5425 dma_free_coherent(rx_ring->dev, rx_ring->size,
5426 rx_ring->desc, rx_ring->dma);
5427
5428 rx_ring->desc = NULL;
5429 }
5430
5431 /**
5432 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5433 * @adapter: board private structure
5434 *
5435 * Free all receive software resources
5436 **/
5437 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5438 {
5439 int i;
5440
5441 for (i = 0; i < adapter->num_rx_queues; i++)
5442 if (adapter->rx_ring[i]->desc)
5443 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5444 }
5445
5446 /**
5447 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5448 * @netdev: network interface device structure
5449 * @new_mtu: new value for maximum frame size
5450 *
5451 * Returns 0 on success, negative on failure
5452 **/
5453 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5454 {
5455 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5456 struct ixgbe_hw *hw = &adapter->hw;
5457 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5458
5459 /* MTU < 68 is an error and causes problems on some kernels */
5460 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5461 hw->mac.type != ixgbe_mac_X540) {
5462 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5463 return -EINVAL;
5464 } else {
5465 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5466 return -EINVAL;
5467 }
5468
5469 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5470 /* must set new MTU before calling down or up */
5471 netdev->mtu = new_mtu;
5472
5473 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5474 hw->fc.low_water = FC_LOW_WATER(max_frame);
5475
5476 if (netif_running(netdev))
5477 ixgbe_reinit_locked(adapter);
5478
5479 return 0;
5480 }
5481
5482 /**
5483 * ixgbe_open - Called when a network interface is made active
5484 * @netdev: network interface device structure
5485 *
5486 * Returns 0 on success, negative value on failure
5487 *
5488 * The open entry point is called when a network interface is made
5489 * active by the system (IFF_UP). At this point all resources needed
5490 * for transmit and receive operations are allocated, the interrupt
5491 * handler is registered with the OS, the watchdog timer is started,
5492 * and the stack is notified that the interface is ready.
5493 **/
5494 static int ixgbe_open(struct net_device *netdev)
5495 {
5496 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5497 int err;
5498
5499 /* disallow open during test */
5500 if (test_bit(__IXGBE_TESTING, &adapter->state))
5501 return -EBUSY;
5502
5503 netif_carrier_off(netdev);
5504
5505 /* allocate transmit descriptors */
5506 err = ixgbe_setup_all_tx_resources(adapter);
5507 if (err)
5508 goto err_setup_tx;
5509
5510 /* allocate receive descriptors */
5511 err = ixgbe_setup_all_rx_resources(adapter);
5512 if (err)
5513 goto err_setup_rx;
5514
5515 ixgbe_configure(adapter);
5516
5517 err = ixgbe_request_irq(adapter);
5518 if (err)
5519 goto err_req_irq;
5520
5521 err = ixgbe_up_complete(adapter);
5522 if (err)
5523 goto err_up;
5524
5525 netif_tx_start_all_queues(netdev);
5526
5527 return 0;
5528
5529 err_up:
5530 ixgbe_release_hw_control(adapter);
5531 ixgbe_free_irq(adapter);
5532 err_req_irq:
5533 err_setup_rx:
5534 ixgbe_free_all_rx_resources(adapter);
5535 err_setup_tx:
5536 ixgbe_free_all_tx_resources(adapter);
5537 ixgbe_reset(adapter);
5538
5539 return err;
5540 }
5541
5542 /**
5543 * ixgbe_close - Disables a network interface
5544 * @netdev: network interface device structure
5545 *
5546 * Returns 0, this is not allowed to fail
5547 *
5548 * The close entry point is called when an interface is de-activated
5549 * by the OS. The hardware is still under the drivers control, but
5550 * needs to be disabled. A global MAC reset is issued to stop the
5551 * hardware, and all transmit and receive resources are freed.
5552 **/
5553 static int ixgbe_close(struct net_device *netdev)
5554 {
5555 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5556
5557 ixgbe_down(adapter);
5558 ixgbe_free_irq(adapter);
5559
5560 ixgbe_free_all_tx_resources(adapter);
5561 ixgbe_free_all_rx_resources(adapter);
5562
5563 ixgbe_release_hw_control(adapter);
5564
5565 return 0;
5566 }
5567
5568 #ifdef CONFIG_PM
5569 static int ixgbe_resume(struct pci_dev *pdev)
5570 {
5571 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5572 struct net_device *netdev = adapter->netdev;
5573 u32 err;
5574
5575 pci_set_power_state(pdev, PCI_D0);
5576 pci_restore_state(pdev);
5577 /*
5578 * pci_restore_state clears dev->state_saved so call
5579 * pci_save_state to restore it.
5580 */
5581 pci_save_state(pdev);
5582
5583 err = pci_enable_device_mem(pdev);
5584 if (err) {
5585 e_dev_err("Cannot enable PCI device from suspend\n");
5586 return err;
5587 }
5588 pci_set_master(pdev);
5589
5590 pci_wake_from_d3(pdev, false);
5591
5592 err = ixgbe_init_interrupt_scheme(adapter);
5593 if (err) {
5594 e_dev_err("Cannot initialize interrupts for device\n");
5595 return err;
5596 }
5597
5598 ixgbe_reset(adapter);
5599
5600 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5601
5602 if (netif_running(netdev)) {
5603 err = ixgbe_open(netdev);
5604 if (err)
5605 return err;
5606 }
5607
5608 netif_device_attach(netdev);
5609
5610 return 0;
5611 }
5612 #endif /* CONFIG_PM */
5613
5614 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5615 {
5616 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5617 struct net_device *netdev = adapter->netdev;
5618 struct ixgbe_hw *hw = &adapter->hw;
5619 u32 ctrl, fctrl;
5620 u32 wufc = adapter->wol;
5621 #ifdef CONFIG_PM
5622 int retval = 0;
5623 #endif
5624
5625 netif_device_detach(netdev);
5626
5627 if (netif_running(netdev)) {
5628 ixgbe_down(adapter);
5629 ixgbe_free_irq(adapter);
5630 ixgbe_free_all_tx_resources(adapter);
5631 ixgbe_free_all_rx_resources(adapter);
5632 }
5633
5634 ixgbe_clear_interrupt_scheme(adapter);
5635 #ifdef CONFIG_DCB
5636 kfree(adapter->ixgbe_ieee_pfc);
5637 kfree(adapter->ixgbe_ieee_ets);
5638 #endif
5639
5640 #ifdef CONFIG_PM
5641 retval = pci_save_state(pdev);
5642 if (retval)
5643 return retval;
5644
5645 #endif
5646 if (wufc) {
5647 ixgbe_set_rx_mode(netdev);
5648
5649 /* turn on all-multi mode if wake on multicast is enabled */
5650 if (wufc & IXGBE_WUFC_MC) {
5651 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5652 fctrl |= IXGBE_FCTRL_MPE;
5653 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5654 }
5655
5656 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5657 ctrl |= IXGBE_CTRL_GIO_DIS;
5658 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5659
5660 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5661 } else {
5662 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5663 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5664 }
5665
5666 switch (hw->mac.type) {
5667 case ixgbe_mac_82598EB:
5668 pci_wake_from_d3(pdev, false);
5669 break;
5670 case ixgbe_mac_82599EB:
5671 case ixgbe_mac_X540:
5672 pci_wake_from_d3(pdev, !!wufc);
5673 break;
5674 default:
5675 break;
5676 }
5677
5678 *enable_wake = !!wufc;
5679
5680 ixgbe_release_hw_control(adapter);
5681
5682 pci_disable_device(pdev);
5683
5684 return 0;
5685 }
5686
5687 #ifdef CONFIG_PM
5688 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5689 {
5690 int retval;
5691 bool wake;
5692
5693 retval = __ixgbe_shutdown(pdev, &wake);
5694 if (retval)
5695 return retval;
5696
5697 if (wake) {
5698 pci_prepare_to_sleep(pdev);
5699 } else {
5700 pci_wake_from_d3(pdev, false);
5701 pci_set_power_state(pdev, PCI_D3hot);
5702 }
5703
5704 return 0;
5705 }
5706 #endif /* CONFIG_PM */
5707
5708 static void ixgbe_shutdown(struct pci_dev *pdev)
5709 {
5710 bool wake;
5711
5712 __ixgbe_shutdown(pdev, &wake);
5713
5714 if (system_state == SYSTEM_POWER_OFF) {
5715 pci_wake_from_d3(pdev, wake);
5716 pci_set_power_state(pdev, PCI_D3hot);
5717 }
5718 }
5719
5720 /**
5721 * ixgbe_update_stats - Update the board statistics counters.
5722 * @adapter: board private structure
5723 **/
5724 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5725 {
5726 struct net_device *netdev = adapter->netdev;
5727 struct ixgbe_hw *hw = &adapter->hw;
5728 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5729 u64 total_mpc = 0;
5730 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5731 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5732 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5733 u64 bytes = 0, packets = 0;
5734
5735 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5736 test_bit(__IXGBE_RESETTING, &adapter->state))
5737 return;
5738
5739 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5740 u64 rsc_count = 0;
5741 u64 rsc_flush = 0;
5742 for (i = 0; i < 16; i++)
5743 adapter->hw_rx_no_dma_resources +=
5744 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5745 for (i = 0; i < adapter->num_rx_queues; i++) {
5746 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5747 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5748 }
5749 adapter->rsc_total_count = rsc_count;
5750 adapter->rsc_total_flush = rsc_flush;
5751 }
5752
5753 for (i = 0; i < adapter->num_rx_queues; i++) {
5754 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5755 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5756 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5757 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5758 bytes += rx_ring->stats.bytes;
5759 packets += rx_ring->stats.packets;
5760 }
5761 adapter->non_eop_descs = non_eop_descs;
5762 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5763 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5764 netdev->stats.rx_bytes = bytes;
5765 netdev->stats.rx_packets = packets;
5766
5767 bytes = 0;
5768 packets = 0;
5769 /* gather some stats to the adapter struct that are per queue */
5770 for (i = 0; i < adapter->num_tx_queues; i++) {
5771 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5772 restart_queue += tx_ring->tx_stats.restart_queue;
5773 tx_busy += tx_ring->tx_stats.tx_busy;
5774 bytes += tx_ring->stats.bytes;
5775 packets += tx_ring->stats.packets;
5776 }
5777 adapter->restart_queue = restart_queue;
5778 adapter->tx_busy = tx_busy;
5779 netdev->stats.tx_bytes = bytes;
5780 netdev->stats.tx_packets = packets;
5781
5782 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5783 for (i = 0; i < 8; i++) {
5784 /* for packet buffers not used, the register should read 0 */
5785 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5786 missed_rx += mpc;
5787 hwstats->mpc[i] += mpc;
5788 total_mpc += hwstats->mpc[i];
5789 if (hw->mac.type == ixgbe_mac_82598EB)
5790 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5791 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5792 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5793 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5794 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5795 switch (hw->mac.type) {
5796 case ixgbe_mac_82598EB:
5797 hwstats->pxonrxc[i] +=
5798 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5799 break;
5800 case ixgbe_mac_82599EB:
5801 case ixgbe_mac_X540:
5802 hwstats->pxonrxc[i] +=
5803 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5804 break;
5805 default:
5806 break;
5807 }
5808 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5809 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5810 }
5811 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5812 /* work around hardware counting issue */
5813 hwstats->gprc -= missed_rx;
5814
5815 ixgbe_update_xoff_received(adapter);
5816
5817 /* 82598 hardware only has a 32 bit counter in the high register */
5818 switch (hw->mac.type) {
5819 case ixgbe_mac_82598EB:
5820 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5821 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5822 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5823 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5824 break;
5825 case ixgbe_mac_82599EB:
5826 case ixgbe_mac_X540:
5827 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5828 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5829 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5830 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5831 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5832 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5833 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5834 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5835 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5836 #ifdef IXGBE_FCOE
5837 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5838 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5839 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5840 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5841 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5842 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5843 #endif /* IXGBE_FCOE */
5844 break;
5845 default:
5846 break;
5847 }
5848 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5849 hwstats->bprc += bprc;
5850 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5851 if (hw->mac.type == ixgbe_mac_82598EB)
5852 hwstats->mprc -= bprc;
5853 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5854 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5855 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5856 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5857 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5858 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5859 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5860 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5861 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5862 hwstats->lxontxc += lxon;
5863 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5864 hwstats->lxofftxc += lxoff;
5865 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5866 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5867 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5868 /*
5869 * 82598 errata - tx of flow control packets is included in tx counters
5870 */
5871 xon_off_tot = lxon + lxoff;
5872 hwstats->gptc -= xon_off_tot;
5873 hwstats->mptc -= xon_off_tot;
5874 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5875 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5876 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5877 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5878 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5879 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5880 hwstats->ptc64 -= xon_off_tot;
5881 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5882 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5883 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5884 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5885 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5886 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5887
5888 /* Fill out the OS statistics structure */
5889 netdev->stats.multicast = hwstats->mprc;
5890
5891 /* Rx Errors */
5892 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5893 netdev->stats.rx_dropped = 0;
5894 netdev->stats.rx_length_errors = hwstats->rlec;
5895 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5896 netdev->stats.rx_missed_errors = total_mpc;
5897 }
5898
5899 /**
5900 * ixgbe_watchdog - Timer Call-back
5901 * @data: pointer to adapter cast into an unsigned long
5902 **/
5903 static void ixgbe_watchdog(unsigned long data)
5904 {
5905 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5906 struct ixgbe_hw *hw = &adapter->hw;
5907 u64 eics = 0;
5908 int i;
5909
5910 /*
5911 * Do the watchdog outside of interrupt context due to the lovely
5912 * delays that some of the newer hardware requires
5913 */
5914
5915 if (test_bit(__IXGBE_DOWN, &adapter->state))
5916 goto watchdog_short_circuit;
5917
5918 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5919 /*
5920 * for legacy and MSI interrupts don't set any bits
5921 * that are enabled for EIAM, because this operation
5922 * would set *both* EIMS and EICS for any bit in EIAM
5923 */
5924 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5925 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5926 goto watchdog_reschedule;
5927 }
5928
5929 /* get one bit for every active tx/rx interrupt vector */
5930 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5931 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5932 if (qv->rxr_count || qv->txr_count)
5933 eics |= ((u64)1 << i);
5934 }
5935
5936 /* Cause software interrupt to ensure rx rings are cleaned */
5937 ixgbe_irq_rearm_queues(adapter, eics);
5938
5939 watchdog_reschedule:
5940 /* Reset the timer */
5941 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5942
5943 watchdog_short_circuit:
5944 schedule_work(&adapter->watchdog_task);
5945 }
5946
5947 /**
5948 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5949 * @work: pointer to work_struct containing our data
5950 **/
5951 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5952 {
5953 struct ixgbe_adapter *adapter = container_of(work,
5954 struct ixgbe_adapter,
5955 multispeed_fiber_task);
5956 struct ixgbe_hw *hw = &adapter->hw;
5957 u32 autoneg;
5958 bool negotiation;
5959
5960 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5961 autoneg = hw->phy.autoneg_advertised;
5962 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5963 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5964 hw->mac.autotry_restart = false;
5965 if (hw->mac.ops.setup_link)
5966 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5967 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5968 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5969 }
5970
5971 /**
5972 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5973 * @work: pointer to work_struct containing our data
5974 **/
5975 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5976 {
5977 struct ixgbe_adapter *adapter = container_of(work,
5978 struct ixgbe_adapter,
5979 sfp_config_module_task);
5980 struct ixgbe_hw *hw = &adapter->hw;
5981 u32 err;
5982
5983 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5984
5985 /* Time for electrical oscillations to settle down */
5986 msleep(100);
5987 err = hw->phy.ops.identify_sfp(hw);
5988
5989 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5990 e_dev_err("failed to initialize because an unsupported SFP+ "
5991 "module type was detected.\n");
5992 e_dev_err("Reload the driver after installing a supported "
5993 "module.\n");
5994 unregister_netdev(adapter->netdev);
5995 return;
5996 }
5997 if (hw->mac.ops.setup_sfp)
5998 hw->mac.ops.setup_sfp(hw);
5999
6000 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
6001 /* This will also work for DA Twinax connections */
6002 schedule_work(&adapter->multispeed_fiber_task);
6003 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
6004 }
6005
6006 /**
6007 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
6008 * @work: pointer to work_struct containing our data
6009 **/
6010 static void ixgbe_fdir_reinit_task(struct work_struct *work)
6011 {
6012 struct ixgbe_adapter *adapter = container_of(work,
6013 struct ixgbe_adapter,
6014 fdir_reinit_task);
6015 struct ixgbe_hw *hw = &adapter->hw;
6016 int i;
6017
6018 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6019 for (i = 0; i < adapter->num_tx_queues; i++)
6020 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
6021 &(adapter->tx_ring[i]->state));
6022 } else {
6023 e_err(probe, "failed to finish FDIR re-initialization, "
6024 "ignored adding FDIR ATR filters\n");
6025 }
6026 /* Done FDIR Re-initialization, enable transmits */
6027 netif_tx_start_all_queues(adapter->netdev);
6028 }
6029
6030 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6031 {
6032 u32 ssvpc;
6033
6034 /* Do not perform spoof check for 82598 */
6035 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6036 return;
6037
6038 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6039
6040 /*
6041 * ssvpc register is cleared on read, if zero then no
6042 * spoofed packets in the last interval.
6043 */
6044 if (!ssvpc)
6045 return;
6046
6047 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6048 }
6049
6050 static DEFINE_MUTEX(ixgbe_watchdog_lock);
6051
6052 /**
6053 * ixgbe_watchdog_task - worker thread to bring link up
6054 * @work: pointer to work_struct containing our data
6055 **/
6056 static void ixgbe_watchdog_task(struct work_struct *work)
6057 {
6058 struct ixgbe_adapter *adapter = container_of(work,
6059 struct ixgbe_adapter,
6060 watchdog_task);
6061 struct net_device *netdev = adapter->netdev;
6062 struct ixgbe_hw *hw = &adapter->hw;
6063 u32 link_speed;
6064 bool link_up;
6065 int i;
6066 struct ixgbe_ring *tx_ring;
6067 int some_tx_pending = 0;
6068
6069 mutex_lock(&ixgbe_watchdog_lock);
6070
6071 link_up = adapter->link_up;
6072 link_speed = adapter->link_speed;
6073
6074 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
6075 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
6076 if (link_up) {
6077 #ifdef CONFIG_DCB
6078 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6079 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
6080 hw->mac.ops.fc_enable(hw, i);
6081 } else {
6082 hw->mac.ops.fc_enable(hw, 0);
6083 }
6084 #else
6085 hw->mac.ops.fc_enable(hw, 0);
6086 #endif
6087 }
6088
6089 if (link_up ||
6090 time_after(jiffies, (adapter->link_check_timeout +
6091 IXGBE_TRY_LINK_TIMEOUT))) {
6092 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6093 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6094 }
6095 adapter->link_up = link_up;
6096 adapter->link_speed = link_speed;
6097 }
6098
6099 if (link_up) {
6100 if (!netif_carrier_ok(netdev)) {
6101 bool flow_rx, flow_tx;
6102
6103 switch (hw->mac.type) {
6104 case ixgbe_mac_82598EB: {
6105 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6106 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6107 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6108 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6109 }
6110 break;
6111 case ixgbe_mac_82599EB:
6112 case ixgbe_mac_X540: {
6113 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6114 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6115 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6116 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6117 }
6118 break;
6119 default:
6120 flow_tx = false;
6121 flow_rx = false;
6122 break;
6123 }
6124
6125 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6126 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6127 "10 Gbps" :
6128 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6129 "1 Gbps" :
6130 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6131 "100 Mbps" :
6132 "unknown speed"))),
6133 ((flow_rx && flow_tx) ? "RX/TX" :
6134 (flow_rx ? "RX" :
6135 (flow_tx ? "TX" : "None"))));
6136
6137 netif_carrier_on(netdev);
6138 } else {
6139 /* Force detection of hung controller */
6140 for (i = 0; i < adapter->num_tx_queues; i++) {
6141 tx_ring = adapter->tx_ring[i];
6142 set_check_for_tx_hang(tx_ring);
6143 }
6144 }
6145 } else {
6146 adapter->link_up = false;
6147 adapter->link_speed = 0;
6148 if (netif_carrier_ok(netdev)) {
6149 e_info(drv, "NIC Link is Down\n");
6150 netif_carrier_off(netdev);
6151 }
6152 }
6153
6154 if (!netif_carrier_ok(netdev)) {
6155 for (i = 0; i < adapter->num_tx_queues; i++) {
6156 tx_ring = adapter->tx_ring[i];
6157 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6158 some_tx_pending = 1;
6159 break;
6160 }
6161 }
6162
6163 if (some_tx_pending) {
6164 /* We've lost link, so the controller stops DMA,
6165 * but we've got queued Tx work that's never going
6166 * to get done, so reset controller to flush Tx.
6167 * (Do the reset outside of interrupt context).
6168 */
6169 schedule_work(&adapter->reset_task);
6170 }
6171 }
6172
6173 ixgbe_spoof_check(adapter);
6174 ixgbe_update_stats(adapter);
6175 mutex_unlock(&ixgbe_watchdog_lock);
6176 }
6177
6178 static int ixgbe_tso(struct ixgbe_adapter *adapter,
6179 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6180 u32 tx_flags, u8 *hdr_len, __be16 protocol)
6181 {
6182 struct ixgbe_adv_tx_context_desc *context_desc;
6183 unsigned int i;
6184 int err;
6185 struct ixgbe_tx_buffer *tx_buffer_info;
6186 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
6187 u32 mss_l4len_idx, l4len;
6188
6189 if (skb_is_gso(skb)) {
6190 if (skb_header_cloned(skb)) {
6191 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6192 if (err)
6193 return err;
6194 }
6195 l4len = tcp_hdrlen(skb);
6196 *hdr_len += l4len;
6197
6198 if (protocol == htons(ETH_P_IP)) {
6199 struct iphdr *iph = ip_hdr(skb);
6200 iph->tot_len = 0;
6201 iph->check = 0;
6202 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6203 iph->daddr, 0,
6204 IPPROTO_TCP,
6205 0);
6206 } else if (skb_is_gso_v6(skb)) {
6207 ipv6_hdr(skb)->payload_len = 0;
6208 tcp_hdr(skb)->check =
6209 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6210 &ipv6_hdr(skb)->daddr,
6211 0, IPPROTO_TCP, 0);
6212 }
6213
6214 i = tx_ring->next_to_use;
6215
6216 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6217 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6218
6219 /* VLAN MACLEN IPLEN */
6220 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6221 vlan_macip_lens |=
6222 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6223 vlan_macip_lens |= ((skb_network_offset(skb)) <<
6224 IXGBE_ADVTXD_MACLEN_SHIFT);
6225 *hdr_len += skb_network_offset(skb);
6226 vlan_macip_lens |=
6227 (skb_transport_header(skb) - skb_network_header(skb));
6228 *hdr_len +=
6229 (skb_transport_header(skb) - skb_network_header(skb));
6230 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6231 context_desc->seqnum_seed = 0;
6232
6233 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6234 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
6235 IXGBE_ADVTXD_DTYP_CTXT);
6236
6237 if (protocol == htons(ETH_P_IP))
6238 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
6239 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6240 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6241
6242 /* MSS L4LEN IDX */
6243 mss_l4len_idx =
6244 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
6245 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
6246 /* use index 1 for TSO */
6247 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6248 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6249
6250 tx_buffer_info->time_stamp = jiffies;
6251 tx_buffer_info->next_to_watch = i;
6252
6253 i++;
6254 if (i == tx_ring->count)
6255 i = 0;
6256 tx_ring->next_to_use = i;
6257
6258 return true;
6259 }
6260 return false;
6261 }
6262
6263 static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6264 __be16 protocol)
6265 {
6266 u32 rtn = 0;
6267
6268 switch (protocol) {
6269 case cpu_to_be16(ETH_P_IP):
6270 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
6271 switch (ip_hdr(skb)->protocol) {
6272 case IPPROTO_TCP:
6273 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6274 break;
6275 case IPPROTO_SCTP:
6276 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6277 break;
6278 }
6279 break;
6280 case cpu_to_be16(ETH_P_IPV6):
6281 /* XXX what about other V6 headers?? */
6282 switch (ipv6_hdr(skb)->nexthdr) {
6283 case IPPROTO_TCP:
6284 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6285 break;
6286 case IPPROTO_SCTP:
6287 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6288 break;
6289 }
6290 break;
6291 default:
6292 if (unlikely(net_ratelimit()))
6293 e_warn(probe, "partial checksum but proto=%x!\n",
6294 protocol);
6295 break;
6296 }
6297
6298 return rtn;
6299 }
6300
6301 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
6302 struct ixgbe_ring *tx_ring,
6303 struct sk_buff *skb, u32 tx_flags,
6304 __be16 protocol)
6305 {
6306 struct ixgbe_adv_tx_context_desc *context_desc;
6307 unsigned int i;
6308 struct ixgbe_tx_buffer *tx_buffer_info;
6309 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6310
6311 if (skb->ip_summed == CHECKSUM_PARTIAL ||
6312 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6313 i = tx_ring->next_to_use;
6314 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6315 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6316
6317 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6318 vlan_macip_lens |=
6319 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6320 vlan_macip_lens |= (skb_network_offset(skb) <<
6321 IXGBE_ADVTXD_MACLEN_SHIFT);
6322 if (skb->ip_summed == CHECKSUM_PARTIAL)
6323 vlan_macip_lens |= (skb_transport_header(skb) -
6324 skb_network_header(skb));
6325
6326 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6327 context_desc->seqnum_seed = 0;
6328
6329 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
6330 IXGBE_ADVTXD_DTYP_CTXT);
6331
6332 if (skb->ip_summed == CHECKSUM_PARTIAL)
6333 type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
6334
6335 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6336 /* use index zero for tx checksum offload */
6337 context_desc->mss_l4len_idx = 0;
6338
6339 tx_buffer_info->time_stamp = jiffies;
6340 tx_buffer_info->next_to_watch = i;
6341
6342 i++;
6343 if (i == tx_ring->count)
6344 i = 0;
6345 tx_ring->next_to_use = i;
6346
6347 return true;
6348 }
6349
6350 return false;
6351 }
6352
6353 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6354 struct ixgbe_ring *tx_ring,
6355 struct sk_buff *skb, u32 tx_flags,
6356 unsigned int first, const u8 hdr_len)
6357 {
6358 struct device *dev = tx_ring->dev;
6359 struct ixgbe_tx_buffer *tx_buffer_info;
6360 unsigned int len;
6361 unsigned int total = skb->len;
6362 unsigned int offset = 0, size, count = 0, i;
6363 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6364 unsigned int f;
6365 unsigned int bytecount = skb->len;
6366 u16 gso_segs = 1;
6367
6368 i = tx_ring->next_to_use;
6369
6370 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6371 /* excluding fcoe_crc_eof for FCoE */
6372 total -= sizeof(struct fcoe_crc_eof);
6373
6374 len = min(skb_headlen(skb), total);
6375 while (len) {
6376 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6377 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6378
6379 tx_buffer_info->length = size;
6380 tx_buffer_info->mapped_as_page = false;
6381 tx_buffer_info->dma = dma_map_single(dev,
6382 skb->data + offset,
6383 size, DMA_TO_DEVICE);
6384 if (dma_mapping_error(dev, tx_buffer_info->dma))
6385 goto dma_error;
6386 tx_buffer_info->time_stamp = jiffies;
6387 tx_buffer_info->next_to_watch = i;
6388
6389 len -= size;
6390 total -= size;
6391 offset += size;
6392 count++;
6393
6394 if (len) {
6395 i++;
6396 if (i == tx_ring->count)
6397 i = 0;
6398 }
6399 }
6400
6401 for (f = 0; f < nr_frags; f++) {
6402 struct skb_frag_struct *frag;
6403
6404 frag = &skb_shinfo(skb)->frags[f];
6405 len = min((unsigned int)frag->size, total);
6406 offset = frag->page_offset;
6407
6408 while (len) {
6409 i++;
6410 if (i == tx_ring->count)
6411 i = 0;
6412
6413 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6414 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6415
6416 tx_buffer_info->length = size;
6417 tx_buffer_info->dma = dma_map_page(dev,
6418 frag->page,
6419 offset, size,
6420 DMA_TO_DEVICE);
6421 tx_buffer_info->mapped_as_page = true;
6422 if (dma_mapping_error(dev, tx_buffer_info->dma))
6423 goto dma_error;
6424 tx_buffer_info->time_stamp = jiffies;
6425 tx_buffer_info->next_to_watch = i;
6426
6427 len -= size;
6428 total -= size;
6429 offset += size;
6430 count++;
6431 }
6432 if (total == 0)
6433 break;
6434 }
6435
6436 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6437 gso_segs = skb_shinfo(skb)->gso_segs;
6438 #ifdef IXGBE_FCOE
6439 /* adjust for FCoE Sequence Offload */
6440 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6441 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6442 skb_shinfo(skb)->gso_size);
6443 #endif /* IXGBE_FCOE */
6444 bytecount += (gso_segs - 1) * hdr_len;
6445
6446 /* multiply data chunks by size of headers */
6447 tx_ring->tx_buffer_info[i].bytecount = bytecount;
6448 tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6449 tx_ring->tx_buffer_info[i].skb = skb;
6450 tx_ring->tx_buffer_info[first].next_to_watch = i;
6451
6452 return count;
6453
6454 dma_error:
6455 e_dev_err("TX DMA map failed\n");
6456
6457 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6458 tx_buffer_info->dma = 0;
6459 tx_buffer_info->time_stamp = 0;
6460 tx_buffer_info->next_to_watch = 0;
6461 if (count)
6462 count--;
6463
6464 /* clear timestamp and dma mappings for remaining portion of packet */
6465 while (count--) {
6466 if (i == 0)
6467 i += tx_ring->count;
6468 i--;
6469 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6470 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6471 }
6472
6473 return 0;
6474 }
6475
6476 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6477 int tx_flags, int count, u32 paylen, u8 hdr_len)
6478 {
6479 union ixgbe_adv_tx_desc *tx_desc = NULL;
6480 struct ixgbe_tx_buffer *tx_buffer_info;
6481 u32 olinfo_status = 0, cmd_type_len = 0;
6482 unsigned int i;
6483 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6484
6485 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6486
6487 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6488
6489 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6490 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6491
6492 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6493 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6494
6495 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6496 IXGBE_ADVTXD_POPTS_SHIFT;
6497
6498 /* use index 1 context for tso */
6499 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6500 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6501 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6502 IXGBE_ADVTXD_POPTS_SHIFT;
6503
6504 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6505 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6506 IXGBE_ADVTXD_POPTS_SHIFT;
6507
6508 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6509 olinfo_status |= IXGBE_ADVTXD_CC;
6510 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6511 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6512 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6513 }
6514
6515 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6516
6517 i = tx_ring->next_to_use;
6518 while (count--) {
6519 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6520 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6521 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6522 tx_desc->read.cmd_type_len =
6523 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6524 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6525 i++;
6526 if (i == tx_ring->count)
6527 i = 0;
6528 }
6529
6530 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6531
6532 /*
6533 * Force memory writes to complete before letting h/w
6534 * know there are new descriptors to fetch. (Only
6535 * applicable for weak-ordered memory model archs,
6536 * such as IA-64).
6537 */
6538 wmb();
6539
6540 tx_ring->next_to_use = i;
6541 writel(i, tx_ring->tail);
6542 }
6543
6544 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6545 u32 tx_flags, __be16 protocol)
6546 {
6547 struct ixgbe_q_vector *q_vector = ring->q_vector;
6548 union ixgbe_atr_hash_dword input = { .dword = 0 };
6549 union ixgbe_atr_hash_dword common = { .dword = 0 };
6550 union {
6551 unsigned char *network;
6552 struct iphdr *ipv4;
6553 struct ipv6hdr *ipv6;
6554 } hdr;
6555 struct tcphdr *th;
6556 __be16 vlan_id;
6557
6558 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6559 if (!q_vector)
6560 return;
6561
6562 /* do nothing if sampling is disabled */
6563 if (!ring->atr_sample_rate)
6564 return;
6565
6566 ring->atr_count++;
6567
6568 /* snag network header to get L4 type and address */
6569 hdr.network = skb_network_header(skb);
6570
6571 /* Currently only IPv4/IPv6 with TCP is supported */
6572 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6573 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6574 (protocol != __constant_htons(ETH_P_IP) ||
6575 hdr.ipv4->protocol != IPPROTO_TCP))
6576 return;
6577
6578 th = tcp_hdr(skb);
6579
6580 /* skip this packet since the socket is closing */
6581 if (th->fin)
6582 return;
6583
6584 /* sample on all syn packets or once every atr sample count */
6585 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6586 return;
6587
6588 /* reset sample count */
6589 ring->atr_count = 0;
6590
6591 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6592
6593 /*
6594 * src and dst are inverted, think how the receiver sees them
6595 *
6596 * The input is broken into two sections, a non-compressed section
6597 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6598 * is XORed together and stored in the compressed dword.
6599 */
6600 input.formatted.vlan_id = vlan_id;
6601
6602 /*
6603 * since src port and flex bytes occupy the same word XOR them together
6604 * and write the value to source port portion of compressed dword
6605 */
6606 if (vlan_id)
6607 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6608 else
6609 common.port.src ^= th->dest ^ protocol;
6610 common.port.dst ^= th->source;
6611
6612 if (protocol == __constant_htons(ETH_P_IP)) {
6613 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6614 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6615 } else {
6616 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6617 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6618 hdr.ipv6->saddr.s6_addr32[1] ^
6619 hdr.ipv6->saddr.s6_addr32[2] ^
6620 hdr.ipv6->saddr.s6_addr32[3] ^
6621 hdr.ipv6->daddr.s6_addr32[0] ^
6622 hdr.ipv6->daddr.s6_addr32[1] ^
6623 hdr.ipv6->daddr.s6_addr32[2] ^
6624 hdr.ipv6->daddr.s6_addr32[3];
6625 }
6626
6627 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6628 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6629 input, common, ring->queue_index);
6630 }
6631
6632 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6633 {
6634 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6635 /* Herbert's original patch had:
6636 * smp_mb__after_netif_stop_queue();
6637 * but since that doesn't exist yet, just open code it. */
6638 smp_mb();
6639
6640 /* We need to check again in a case another CPU has just
6641 * made room available. */
6642 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6643 return -EBUSY;
6644
6645 /* A reprieve! - use start_queue because it doesn't call schedule */
6646 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6647 ++tx_ring->tx_stats.restart_queue;
6648 return 0;
6649 }
6650
6651 static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6652 {
6653 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6654 return 0;
6655 return __ixgbe_maybe_stop_tx(tx_ring, size);
6656 }
6657
6658 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6659 {
6660 struct ixgbe_adapter *adapter = netdev_priv(dev);
6661 int txq = smp_processor_id();
6662 #ifdef IXGBE_FCOE
6663 __be16 protocol;
6664
6665 protocol = vlan_get_protocol(skb);
6666
6667 if ((protocol == htons(ETH_P_FCOE)) ||
6668 (protocol == htons(ETH_P_FIP))) {
6669 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6670 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6671 txq += adapter->ring_feature[RING_F_FCOE].mask;
6672 return txq;
6673 #ifdef CONFIG_IXGBE_DCB
6674 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6675 txq = adapter->fcoe.up;
6676 return txq;
6677 #endif
6678 }
6679 }
6680 #endif
6681
6682 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6683 while (unlikely(txq >= dev->real_num_tx_queues))
6684 txq -= dev->real_num_tx_queues;
6685 return txq;
6686 }
6687
6688 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6689 if (skb->priority == TC_PRIO_CONTROL)
6690 txq = adapter->ring_feature[RING_F_DCB].indices-1;
6691 else
6692 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6693 >> 13;
6694 return txq;
6695 }
6696
6697 return skb_tx_hash(dev, skb);
6698 }
6699
6700 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6701 struct ixgbe_adapter *adapter,
6702 struct ixgbe_ring *tx_ring)
6703 {
6704 unsigned int first;
6705 unsigned int tx_flags = 0;
6706 u8 hdr_len = 0;
6707 int tso;
6708 int count = 0;
6709 unsigned int f;
6710 __be16 protocol;
6711
6712 protocol = vlan_get_protocol(skb);
6713
6714 if (vlan_tx_tag_present(skb)) {
6715 tx_flags |= vlan_tx_tag_get(skb);
6716 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6717 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6718 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6719 }
6720 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6721 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6722 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6723 skb->priority != TC_PRIO_CONTROL) {
6724 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6725 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6726 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6727 }
6728
6729 #ifdef IXGBE_FCOE
6730 /* for FCoE with DCB, we force the priority to what
6731 * was specified by the switch */
6732 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6733 (protocol == htons(ETH_P_FCOE) ||
6734 protocol == htons(ETH_P_FIP))) {
6735 #ifdef CONFIG_IXGBE_DCB
6736 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6737 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6738 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6739 tx_flags |= ((adapter->fcoe.up << 13)
6740 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6741 }
6742 #endif
6743 /* flag for FCoE offloads */
6744 if (protocol == htons(ETH_P_FCOE))
6745 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6746 }
6747 #endif
6748
6749 /* four things can cause us to need a context descriptor */
6750 if (skb_is_gso(skb) ||
6751 (skb->ip_summed == CHECKSUM_PARTIAL) ||
6752 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6753 (tx_flags & IXGBE_TX_FLAGS_FCOE))
6754 count++;
6755
6756 count += TXD_USE_COUNT(skb_headlen(skb));
6757 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6758 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6759
6760 if (ixgbe_maybe_stop_tx(tx_ring, count)) {
6761 tx_ring->tx_stats.tx_busy++;
6762 return NETDEV_TX_BUSY;
6763 }
6764
6765 first = tx_ring->next_to_use;
6766 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6767 #ifdef IXGBE_FCOE
6768 /* setup tx offload for FCoE */
6769 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6770 if (tso < 0) {
6771 dev_kfree_skb_any(skb);
6772 return NETDEV_TX_OK;
6773 }
6774 if (tso)
6775 tx_flags |= IXGBE_TX_FLAGS_FSO;
6776 #endif /* IXGBE_FCOE */
6777 } else {
6778 if (protocol == htons(ETH_P_IP))
6779 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6780 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6781 protocol);
6782 if (tso < 0) {
6783 dev_kfree_skb_any(skb);
6784 return NETDEV_TX_OK;
6785 }
6786
6787 if (tso)
6788 tx_flags |= IXGBE_TX_FLAGS_TSO;
6789 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6790 protocol) &&
6791 (skb->ip_summed == CHECKSUM_PARTIAL))
6792 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6793 }
6794
6795 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6796 if (count) {
6797 /* add the ATR filter if ATR is on */
6798 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6799 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6800 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
6801 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6802
6803 } else {
6804 dev_kfree_skb_any(skb);
6805 tx_ring->tx_buffer_info[first].time_stamp = 0;
6806 tx_ring->next_to_use = first;
6807 }
6808
6809 return NETDEV_TX_OK;
6810 }
6811
6812 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6813 {
6814 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6815 struct ixgbe_ring *tx_ring;
6816
6817 tx_ring = adapter->tx_ring[skb->queue_mapping];
6818 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6819 }
6820
6821 /**
6822 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6823 * @netdev: network interface device structure
6824 * @p: pointer to an address structure
6825 *
6826 * Returns 0 on success, negative on failure
6827 **/
6828 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6829 {
6830 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6831 struct ixgbe_hw *hw = &adapter->hw;
6832 struct sockaddr *addr = p;
6833
6834 if (!is_valid_ether_addr(addr->sa_data))
6835 return -EADDRNOTAVAIL;
6836
6837 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6838 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6839
6840 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6841 IXGBE_RAH_AV);
6842
6843 return 0;
6844 }
6845
6846 static int
6847 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6848 {
6849 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6850 struct ixgbe_hw *hw = &adapter->hw;
6851 u16 value;
6852 int rc;
6853
6854 if (prtad != hw->phy.mdio.prtad)
6855 return -EINVAL;
6856 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6857 if (!rc)
6858 rc = value;
6859 return rc;
6860 }
6861
6862 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6863 u16 addr, u16 value)
6864 {
6865 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6866 struct ixgbe_hw *hw = &adapter->hw;
6867
6868 if (prtad != hw->phy.mdio.prtad)
6869 return -EINVAL;
6870 return hw->phy.ops.write_reg(hw, addr, devad, value);
6871 }
6872
6873 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6874 {
6875 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6876
6877 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6878 }
6879
6880 /**
6881 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6882 * netdev->dev_addrs
6883 * @netdev: network interface device structure
6884 *
6885 * Returns non-zero on failure
6886 **/
6887 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6888 {
6889 int err = 0;
6890 struct ixgbe_adapter *adapter = netdev_priv(dev);
6891 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6892
6893 if (is_valid_ether_addr(mac->san_addr)) {
6894 rtnl_lock();
6895 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6896 rtnl_unlock();
6897 }
6898 return err;
6899 }
6900
6901 /**
6902 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6903 * netdev->dev_addrs
6904 * @netdev: network interface device structure
6905 *
6906 * Returns non-zero on failure
6907 **/
6908 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6909 {
6910 int err = 0;
6911 struct ixgbe_adapter *adapter = netdev_priv(dev);
6912 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6913
6914 if (is_valid_ether_addr(mac->san_addr)) {
6915 rtnl_lock();
6916 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6917 rtnl_unlock();
6918 }
6919 return err;
6920 }
6921
6922 #ifdef CONFIG_NET_POLL_CONTROLLER
6923 /*
6924 * Polling 'interrupt' - used by things like netconsole to send skbs
6925 * without having to re-enable interrupts. It's not called while
6926 * the interrupt routine is executing.
6927 */
6928 static void ixgbe_netpoll(struct net_device *netdev)
6929 {
6930 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6931 int i;
6932
6933 /* if interface is down do nothing */
6934 if (test_bit(__IXGBE_DOWN, &adapter->state))
6935 return;
6936
6937 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6938 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6939 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6940 for (i = 0; i < num_q_vectors; i++) {
6941 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6942 ixgbe_msix_clean_many(0, q_vector);
6943 }
6944 } else {
6945 ixgbe_intr(adapter->pdev->irq, netdev);
6946 }
6947 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6948 }
6949 #endif
6950
6951 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6952 struct rtnl_link_stats64 *stats)
6953 {
6954 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6955 int i;
6956
6957 rcu_read_lock();
6958 for (i = 0; i < adapter->num_rx_queues; i++) {
6959 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6960 u64 bytes, packets;
6961 unsigned int start;
6962
6963 if (ring) {
6964 do {
6965 start = u64_stats_fetch_begin_bh(&ring->syncp);
6966 packets = ring->stats.packets;
6967 bytes = ring->stats.bytes;
6968 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6969 stats->rx_packets += packets;
6970 stats->rx_bytes += bytes;
6971 }
6972 }
6973
6974 for (i = 0; i < adapter->num_tx_queues; i++) {
6975 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6976 u64 bytes, packets;
6977 unsigned int start;
6978
6979 if (ring) {
6980 do {
6981 start = u64_stats_fetch_begin_bh(&ring->syncp);
6982 packets = ring->stats.packets;
6983 bytes = ring->stats.bytes;
6984 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6985 stats->tx_packets += packets;
6986 stats->tx_bytes += bytes;
6987 }
6988 }
6989 rcu_read_unlock();
6990 /* following stats updated by ixgbe_watchdog_task() */
6991 stats->multicast = netdev->stats.multicast;
6992 stats->rx_errors = netdev->stats.rx_errors;
6993 stats->rx_length_errors = netdev->stats.rx_length_errors;
6994 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6995 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6996 return stats;
6997 }
6998
6999
7000 static const struct net_device_ops ixgbe_netdev_ops = {
7001 .ndo_open = ixgbe_open,
7002 .ndo_stop = ixgbe_close,
7003 .ndo_start_xmit = ixgbe_xmit_frame,
7004 .ndo_select_queue = ixgbe_select_queue,
7005 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7006 .ndo_set_multicast_list = ixgbe_set_rx_mode,
7007 .ndo_validate_addr = eth_validate_addr,
7008 .ndo_set_mac_address = ixgbe_set_mac,
7009 .ndo_change_mtu = ixgbe_change_mtu,
7010 .ndo_tx_timeout = ixgbe_tx_timeout,
7011 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7012 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7013 .ndo_do_ioctl = ixgbe_ioctl,
7014 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7015 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7016 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7017 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7018 .ndo_get_stats64 = ixgbe_get_stats64,
7019 #ifdef CONFIG_NET_POLL_CONTROLLER
7020 .ndo_poll_controller = ixgbe_netpoll,
7021 #endif
7022 #ifdef IXGBE_FCOE
7023 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7024 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7025 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7026 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7027 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7028 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7029 #endif /* IXGBE_FCOE */
7030 };
7031
7032 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7033 const struct ixgbe_info *ii)
7034 {
7035 #ifdef CONFIG_PCI_IOV
7036 struct ixgbe_hw *hw = &adapter->hw;
7037 int err;
7038
7039 if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
7040 return;
7041
7042 /* The 82599 supports up to 64 VFs per physical function
7043 * but this implementation limits allocation to 63 so that
7044 * basic networking resources are still available to the
7045 * physical function
7046 */
7047 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7048 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7049 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7050 if (err) {
7051 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
7052 goto err_novfs;
7053 }
7054 /* If call to enable VFs succeeded then allocate memory
7055 * for per VF control structures.
7056 */
7057 adapter->vfinfo =
7058 kcalloc(adapter->num_vfs,
7059 sizeof(struct vf_data_storage), GFP_KERNEL);
7060 if (adapter->vfinfo) {
7061 /* Now that we're sure SR-IOV is enabled
7062 * and memory allocated set up the mailbox parameters
7063 */
7064 ixgbe_init_mbx_params_pf(hw);
7065 memcpy(&hw->mbx.ops, ii->mbx_ops,
7066 sizeof(hw->mbx.ops));
7067
7068 /* Disable RSC when in SR-IOV mode */
7069 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7070 IXGBE_FLAG2_RSC_ENABLED);
7071 return;
7072 }
7073
7074 /* Oh oh */
7075 e_err(probe, "Unable to allocate memory for VF Data Storage - "
7076 "SRIOV disabled\n");
7077 pci_disable_sriov(adapter->pdev);
7078
7079 err_novfs:
7080 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7081 adapter->num_vfs = 0;
7082 #endif /* CONFIG_PCI_IOV */
7083 }
7084
7085 /**
7086 * ixgbe_probe - Device Initialization Routine
7087 * @pdev: PCI device information struct
7088 * @ent: entry in ixgbe_pci_tbl
7089 *
7090 * Returns 0 on success, negative on failure
7091 *
7092 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7093 * The OS initialization, configuring of the adapter private structure,
7094 * and a hardware reset occur.
7095 **/
7096 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7097 const struct pci_device_id *ent)
7098 {
7099 struct net_device *netdev;
7100 struct ixgbe_adapter *adapter = NULL;
7101 struct ixgbe_hw *hw;
7102 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7103 static int cards_found;
7104 int i, err, pci_using_dac;
7105 u8 part_str[IXGBE_PBANUM_LENGTH];
7106 unsigned int indices = num_possible_cpus();
7107 #ifdef IXGBE_FCOE
7108 u16 device_caps;
7109 #endif
7110 u32 eec;
7111
7112 /* Catch broken hardware that put the wrong VF device ID in
7113 * the PCIe SR-IOV capability.
7114 */
7115 if (pdev->is_virtfn) {
7116 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7117 pci_name(pdev), pdev->vendor, pdev->device);
7118 return -EINVAL;
7119 }
7120
7121 err = pci_enable_device_mem(pdev);
7122 if (err)
7123 return err;
7124
7125 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7126 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7127 pci_using_dac = 1;
7128 } else {
7129 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7130 if (err) {
7131 err = dma_set_coherent_mask(&pdev->dev,
7132 DMA_BIT_MASK(32));
7133 if (err) {
7134 dev_err(&pdev->dev,
7135 "No usable DMA configuration, aborting\n");
7136 goto err_dma;
7137 }
7138 }
7139 pci_using_dac = 0;
7140 }
7141
7142 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7143 IORESOURCE_MEM), ixgbe_driver_name);
7144 if (err) {
7145 dev_err(&pdev->dev,
7146 "pci_request_selected_regions failed 0x%x\n", err);
7147 goto err_pci_reg;
7148 }
7149
7150 pci_enable_pcie_error_reporting(pdev);
7151
7152 pci_set_master(pdev);
7153 pci_save_state(pdev);
7154
7155 if (ii->mac == ixgbe_mac_82598EB)
7156 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7157 else
7158 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7159
7160 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
7161 #ifdef IXGBE_FCOE
7162 indices += min_t(unsigned int, num_possible_cpus(),
7163 IXGBE_MAX_FCOE_INDICES);
7164 #endif
7165 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7166 if (!netdev) {
7167 err = -ENOMEM;
7168 goto err_alloc_etherdev;
7169 }
7170
7171 SET_NETDEV_DEV(netdev, &pdev->dev);
7172
7173 adapter = netdev_priv(netdev);
7174 pci_set_drvdata(pdev, adapter);
7175
7176 adapter->netdev = netdev;
7177 adapter->pdev = pdev;
7178 hw = &adapter->hw;
7179 hw->back = adapter;
7180 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7181
7182 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7183 pci_resource_len(pdev, 0));
7184 if (!hw->hw_addr) {
7185 err = -EIO;
7186 goto err_ioremap;
7187 }
7188
7189 for (i = 1; i <= 5; i++) {
7190 if (pci_resource_len(pdev, i) == 0)
7191 continue;
7192 }
7193
7194 netdev->netdev_ops = &ixgbe_netdev_ops;
7195 ixgbe_set_ethtool_ops(netdev);
7196 netdev->watchdog_timeo = 5 * HZ;
7197 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7198
7199 adapter->bd_number = cards_found;
7200
7201 /* Setup hw api */
7202 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7203 hw->mac.type = ii->mac;
7204
7205 /* EEPROM */
7206 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7207 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7208 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7209 if (!(eec & (1 << 8)))
7210 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7211
7212 /* PHY */
7213 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7214 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7215 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7216 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7217 hw->phy.mdio.mmds = 0;
7218 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7219 hw->phy.mdio.dev = netdev;
7220 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7221 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7222
7223 /* set up this timer and work struct before calling get_invariants
7224 * which might start the timer
7225 */
7226 init_timer(&adapter->sfp_timer);
7227 adapter->sfp_timer.function = ixgbe_sfp_timer;
7228 adapter->sfp_timer.data = (unsigned long) adapter;
7229
7230 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
7231
7232 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
7233 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
7234
7235 /* a new SFP+ module arrival, called from GPI SDP2 context */
7236 INIT_WORK(&adapter->sfp_config_module_task,
7237 ixgbe_sfp_config_module_task);
7238
7239 ii->get_invariants(hw);
7240
7241 /* setup the private structure */
7242 err = ixgbe_sw_init(adapter);
7243 if (err)
7244 goto err_sw_init;
7245
7246 /* Make it possible the adapter to be woken up via WOL */
7247 switch (adapter->hw.mac.type) {
7248 case ixgbe_mac_82599EB:
7249 case ixgbe_mac_X540:
7250 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7251 break;
7252 default:
7253 break;
7254 }
7255
7256 /*
7257 * If there is a fan on this device and it has failed log the
7258 * failure.
7259 */
7260 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7261 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7262 if (esdp & IXGBE_ESDP_SDP1)
7263 e_crit(probe, "Fan has stopped, replace the adapter\n");
7264 }
7265
7266 /* reset_hw fills in the perm_addr as well */
7267 hw->phy.reset_if_overtemp = true;
7268 err = hw->mac.ops.reset_hw(hw);
7269 hw->phy.reset_if_overtemp = false;
7270 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7271 hw->mac.type == ixgbe_mac_82598EB) {
7272 /*
7273 * Start a kernel thread to watch for a module to arrive.
7274 * Only do this for 82598, since 82599 will generate
7275 * interrupts on module arrival.
7276 */
7277 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7278 mod_timer(&adapter->sfp_timer,
7279 round_jiffies(jiffies + (2 * HZ)));
7280 err = 0;
7281 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7282 e_dev_err("failed to initialize because an unsupported SFP+ "
7283 "module type was detected.\n");
7284 e_dev_err("Reload the driver after installing a supported "
7285 "module.\n");
7286 goto err_sw_init;
7287 } else if (err) {
7288 e_dev_err("HW Init failed: %d\n", err);
7289 goto err_sw_init;
7290 }
7291
7292 ixgbe_probe_vf(adapter, ii);
7293
7294 netdev->features = NETIF_F_SG |
7295 NETIF_F_IP_CSUM |
7296 NETIF_F_HW_VLAN_TX |
7297 NETIF_F_HW_VLAN_RX |
7298 NETIF_F_HW_VLAN_FILTER;
7299
7300 netdev->features |= NETIF_F_IPV6_CSUM;
7301 netdev->features |= NETIF_F_TSO;
7302 netdev->features |= NETIF_F_TSO6;
7303 netdev->features |= NETIF_F_GRO;
7304
7305 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
7306 netdev->features |= NETIF_F_SCTP_CSUM;
7307
7308 netdev->vlan_features |= NETIF_F_TSO;
7309 netdev->vlan_features |= NETIF_F_TSO6;
7310 netdev->vlan_features |= NETIF_F_IP_CSUM;
7311 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7312 netdev->vlan_features |= NETIF_F_SG;
7313
7314 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7315 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7316 IXGBE_FLAG_DCB_ENABLED);
7317 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7318 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
7319
7320 #ifdef CONFIG_IXGBE_DCB
7321 netdev->dcbnl_ops = &dcbnl_ops;
7322 #endif
7323
7324 #ifdef IXGBE_FCOE
7325 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7326 if (hw->mac.ops.get_device_caps) {
7327 hw->mac.ops.get_device_caps(hw, &device_caps);
7328 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7329 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7330 }
7331 }
7332 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7333 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7334 netdev->vlan_features |= NETIF_F_FSO;
7335 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7336 }
7337 #endif /* IXGBE_FCOE */
7338 if (pci_using_dac) {
7339 netdev->features |= NETIF_F_HIGHDMA;
7340 netdev->vlan_features |= NETIF_F_HIGHDMA;
7341 }
7342
7343 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7344 netdev->features |= NETIF_F_LRO;
7345
7346 /* make sure the EEPROM is good */
7347 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7348 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7349 err = -EIO;
7350 goto err_eeprom;
7351 }
7352
7353 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7354 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7355
7356 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7357 e_dev_err("invalid MAC address\n");
7358 err = -EIO;
7359 goto err_eeprom;
7360 }
7361
7362 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7363 if (hw->mac.ops.disable_tx_laser &&
7364 ((hw->phy.multispeed_fiber) ||
7365 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7366 (hw->mac.type == ixgbe_mac_82599EB))))
7367 hw->mac.ops.disable_tx_laser(hw);
7368
7369 init_timer(&adapter->watchdog_timer);
7370 adapter->watchdog_timer.function = ixgbe_watchdog;
7371 adapter->watchdog_timer.data = (unsigned long)adapter;
7372
7373 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
7374 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
7375
7376 err = ixgbe_init_interrupt_scheme(adapter);
7377 if (err)
7378 goto err_sw_init;
7379
7380 switch (pdev->device) {
7381 case IXGBE_DEV_ID_82599_SFP:
7382 /* Only this subdevice supports WOL */
7383 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7384 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7385 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7386 break;
7387 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7388 /* All except this subdevice support WOL */
7389 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7390 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7391 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7392 break;
7393 case IXGBE_DEV_ID_82599_KX4:
7394 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7395 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7396 break;
7397 default:
7398 adapter->wol = 0;
7399 break;
7400 }
7401 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7402
7403 /* pick up the PCI bus settings for reporting later */
7404 hw->mac.ops.get_bus_info(hw);
7405
7406 /* print bus type/speed/width info */
7407 e_dev_info("(PCI Express:%s:%s) %pM\n",
7408 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
7409 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
7410 "Unknown"),
7411 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7412 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7413 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7414 "Unknown"),
7415 netdev->dev_addr);
7416
7417 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7418 if (err)
7419 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7420 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7421 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7422 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7423 part_str);
7424 else
7425 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7426 hw->mac.type, hw->phy.type, part_str);
7427
7428 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7429 e_dev_warn("PCI-Express bandwidth available for this card is "
7430 "not sufficient for optimal performance.\n");
7431 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7432 "is required.\n");
7433 }
7434
7435 /* save off EEPROM version number */
7436 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7437
7438 /* reset the hardware with the new settings */
7439 err = hw->mac.ops.start_hw(hw);
7440
7441 if (err == IXGBE_ERR_EEPROM_VERSION) {
7442 /* We are running on a pre-production device, log a warning */
7443 e_dev_warn("This device is a pre-production adapter/LOM. "
7444 "Please be aware there may be issues associated "
7445 "with your hardware. If you are experiencing "
7446 "problems please contact your Intel or hardware "
7447 "representative who provided you with this "
7448 "hardware.\n");
7449 }
7450 strcpy(netdev->name, "eth%d");
7451 err = register_netdev(netdev);
7452 if (err)
7453 goto err_register;
7454
7455 /* carrier off reporting is important to ethtool even BEFORE open */
7456 netif_carrier_off(netdev);
7457
7458 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7459 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7460 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7461
7462 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7463 INIT_WORK(&adapter->check_overtemp_task,
7464 ixgbe_check_overtemp_task);
7465 #ifdef CONFIG_IXGBE_DCA
7466 if (dca_add_requester(&pdev->dev) == 0) {
7467 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7468 ixgbe_setup_dca(adapter);
7469 }
7470 #endif
7471 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7472 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7473 for (i = 0; i < adapter->num_vfs; i++)
7474 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7475 }
7476
7477 /* add san mac addr to netdev */
7478 ixgbe_add_sanmac_netdev(netdev);
7479
7480 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7481 cards_found++;
7482 return 0;
7483
7484 err_register:
7485 ixgbe_release_hw_control(adapter);
7486 ixgbe_clear_interrupt_scheme(adapter);
7487 err_sw_init:
7488 err_eeprom:
7489 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7490 ixgbe_disable_sriov(adapter);
7491 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7492 del_timer_sync(&adapter->sfp_timer);
7493 cancel_work_sync(&adapter->sfp_task);
7494 cancel_work_sync(&adapter->multispeed_fiber_task);
7495 cancel_work_sync(&adapter->sfp_config_module_task);
7496 iounmap(hw->hw_addr);
7497 err_ioremap:
7498 free_netdev(netdev);
7499 err_alloc_etherdev:
7500 pci_release_selected_regions(pdev,
7501 pci_select_bars(pdev, IORESOURCE_MEM));
7502 err_pci_reg:
7503 err_dma:
7504 pci_disable_device(pdev);
7505 return err;
7506 }
7507
7508 /**
7509 * ixgbe_remove - Device Removal Routine
7510 * @pdev: PCI device information struct
7511 *
7512 * ixgbe_remove is called by the PCI subsystem to alert the driver
7513 * that it should release a PCI device. The could be caused by a
7514 * Hot-Plug event, or because the driver is going to be removed from
7515 * memory.
7516 **/
7517 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7518 {
7519 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7520 struct net_device *netdev = adapter->netdev;
7521
7522 set_bit(__IXGBE_DOWN, &adapter->state);
7523
7524 /*
7525 * The timers may be rescheduled, so explicitly disable them
7526 * from being rescheduled.
7527 */
7528 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7529 del_timer_sync(&adapter->watchdog_timer);
7530 del_timer_sync(&adapter->sfp_timer);
7531
7532 cancel_work_sync(&adapter->watchdog_task);
7533 cancel_work_sync(&adapter->sfp_task);
7534 cancel_work_sync(&adapter->multispeed_fiber_task);
7535 cancel_work_sync(&adapter->sfp_config_module_task);
7536 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7537 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7538 cancel_work_sync(&adapter->fdir_reinit_task);
7539 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7540 cancel_work_sync(&adapter->check_overtemp_task);
7541
7542 #ifdef CONFIG_IXGBE_DCA
7543 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7544 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7545 dca_remove_requester(&pdev->dev);
7546 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7547 }
7548
7549 #endif
7550 #ifdef IXGBE_FCOE
7551 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7552 ixgbe_cleanup_fcoe(adapter);
7553
7554 #endif /* IXGBE_FCOE */
7555
7556 /* remove the added san mac */
7557 ixgbe_del_sanmac_netdev(netdev);
7558
7559 if (netdev->reg_state == NETREG_REGISTERED)
7560 unregister_netdev(netdev);
7561
7562 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7563 ixgbe_disable_sriov(adapter);
7564
7565 ixgbe_clear_interrupt_scheme(adapter);
7566
7567 ixgbe_release_hw_control(adapter);
7568
7569 iounmap(adapter->hw.hw_addr);
7570 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7571 IORESOURCE_MEM));
7572
7573 e_dev_info("complete\n");
7574
7575 free_netdev(netdev);
7576
7577 pci_disable_pcie_error_reporting(pdev);
7578
7579 pci_disable_device(pdev);
7580 }
7581
7582 /**
7583 * ixgbe_io_error_detected - called when PCI error is detected
7584 * @pdev: Pointer to PCI device
7585 * @state: The current pci connection state
7586 *
7587 * This function is called after a PCI bus error affecting
7588 * this device has been detected.
7589 */
7590 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7591 pci_channel_state_t state)
7592 {
7593 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7594 struct net_device *netdev = adapter->netdev;
7595
7596 netif_device_detach(netdev);
7597
7598 if (state == pci_channel_io_perm_failure)
7599 return PCI_ERS_RESULT_DISCONNECT;
7600
7601 if (netif_running(netdev))
7602 ixgbe_down(adapter);
7603 pci_disable_device(pdev);
7604
7605 /* Request a slot reset. */
7606 return PCI_ERS_RESULT_NEED_RESET;
7607 }
7608
7609 /**
7610 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7611 * @pdev: Pointer to PCI device
7612 *
7613 * Restart the card from scratch, as if from a cold-boot.
7614 */
7615 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7616 {
7617 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7618 pci_ers_result_t result;
7619 int err;
7620
7621 if (pci_enable_device_mem(pdev)) {
7622 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7623 result = PCI_ERS_RESULT_DISCONNECT;
7624 } else {
7625 pci_set_master(pdev);
7626 pci_restore_state(pdev);
7627 pci_save_state(pdev);
7628
7629 pci_wake_from_d3(pdev, false);
7630
7631 ixgbe_reset(adapter);
7632 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7633 result = PCI_ERS_RESULT_RECOVERED;
7634 }
7635
7636 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7637 if (err) {
7638 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7639 "failed 0x%0x\n", err);
7640 /* non-fatal, continue */
7641 }
7642
7643 return result;
7644 }
7645
7646 /**
7647 * ixgbe_io_resume - called when traffic can start flowing again.
7648 * @pdev: Pointer to PCI device
7649 *
7650 * This callback is called when the error recovery driver tells us that
7651 * its OK to resume normal operation.
7652 */
7653 static void ixgbe_io_resume(struct pci_dev *pdev)
7654 {
7655 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7656 struct net_device *netdev = adapter->netdev;
7657
7658 if (netif_running(netdev)) {
7659 if (ixgbe_up(adapter)) {
7660 e_info(probe, "ixgbe_up failed after reset\n");
7661 return;
7662 }
7663 }
7664
7665 netif_device_attach(netdev);
7666 }
7667
7668 static struct pci_error_handlers ixgbe_err_handler = {
7669 .error_detected = ixgbe_io_error_detected,
7670 .slot_reset = ixgbe_io_slot_reset,
7671 .resume = ixgbe_io_resume,
7672 };
7673
7674 static struct pci_driver ixgbe_driver = {
7675 .name = ixgbe_driver_name,
7676 .id_table = ixgbe_pci_tbl,
7677 .probe = ixgbe_probe,
7678 .remove = __devexit_p(ixgbe_remove),
7679 #ifdef CONFIG_PM
7680 .suspend = ixgbe_suspend,
7681 .resume = ixgbe_resume,
7682 #endif
7683 .shutdown = ixgbe_shutdown,
7684 .err_handler = &ixgbe_err_handler
7685 };
7686
7687 /**
7688 * ixgbe_init_module - Driver Registration Routine
7689 *
7690 * ixgbe_init_module is the first routine called when the driver is
7691 * loaded. All it does is register with the PCI subsystem.
7692 **/
7693 static int __init ixgbe_init_module(void)
7694 {
7695 int ret;
7696 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7697 pr_info("%s\n", ixgbe_copyright);
7698
7699 #ifdef CONFIG_IXGBE_DCA
7700 dca_register_notify(&dca_notifier);
7701 #endif
7702
7703 ret = pci_register_driver(&ixgbe_driver);
7704 return ret;
7705 }
7706
7707 module_init(ixgbe_init_module);
7708
7709 /**
7710 * ixgbe_exit_module - Driver Exit Cleanup Routine
7711 *
7712 * ixgbe_exit_module is called just before the driver is removed
7713 * from memory.
7714 **/
7715 static void __exit ixgbe_exit_module(void)
7716 {
7717 #ifdef CONFIG_IXGBE_DCA
7718 dca_unregister_notify(&dca_notifier);
7719 #endif
7720 pci_unregister_driver(&ixgbe_driver);
7721 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7722 }
7723
7724 #ifdef CONFIG_IXGBE_DCA
7725 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7726 void *p)
7727 {
7728 int ret_val;
7729
7730 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7731 __ixgbe_notify_dca);
7732
7733 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7734 }
7735
7736 #endif /* CONFIG_IXGBE_DCA */
7737
7738 module_exit(ixgbe_exit_module);
7739
7740 /* ixgbe_main.c */
Linux kernel - Deliverables
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