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ixgbe: add support to FCoE DDP in target mode
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <linux/slab.h>
40 #include <net/checksum.h>
41 #include <net/ip6_checksum.h>
42 #include <linux/ethtool.h>
43 #include <linux/if_vlan.h>
44 #include <scsi/fc/fc_fcoe.h>
45
46 #include "ixgbe.h"
47 #include "ixgbe_common.h"
48 #include "ixgbe_dcb_82599.h"
49 #include "ixgbe_sriov.h"
50
51 char ixgbe_driver_name[] = "ixgbe";
52 static const char ixgbe_driver_string[] =
53 "Intel(R) 10 Gigabit PCI Express Network Driver";
54
55 #define DRV_VERSION "3.2.9-k2"
56 const char ixgbe_driver_version[] = DRV_VERSION;
57 static const char ixgbe_copyright[] =
58 "Copyright (c) 1999-2011 Intel Corporation.";
59
60 static const struct ixgbe_info *ixgbe_info_tbl[] = {
61 [board_82598] = &ixgbe_82598_info,
62 [board_82599] = &ixgbe_82599_info,
63 [board_X540] = &ixgbe_X540_info,
64 };
65
66 /* ixgbe_pci_tbl - PCI Device ID Table
67 *
68 * Wildcard entries (PCI_ANY_ID) should come last
69 * Last entry must be all 0s
70 *
71 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
72 * Class, Class Mask, private data (not used) }
73 */
74 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
76 board_82598 },
77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
78 board_82598 },
79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
80 board_82598 },
81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
82 board_82598 },
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
84 board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
86 board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
88 board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
90 board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
92 board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
94 board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
96 board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
98 board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
100 board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
102 board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
104 board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
106 board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
108 board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
110 board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
112 board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
114 board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
116 board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
118 board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
120 board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
122 board_X540 },
123
124 /* required last entry */
125 {0, }
126 };
127 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
128
129 #ifdef CONFIG_IXGBE_DCA
130 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
131 void *p);
132 static struct notifier_block dca_notifier = {
133 .notifier_call = ixgbe_notify_dca,
134 .next = NULL,
135 .priority = 0
136 };
137 #endif
138
139 #ifdef CONFIG_PCI_IOV
140 static unsigned int max_vfs;
141 module_param(max_vfs, uint, 0);
142 MODULE_PARM_DESC(max_vfs,
143 "Maximum number of virtual functions to allocate per physical function");
144 #endif /* CONFIG_PCI_IOV */
145
146 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
147 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
148 MODULE_LICENSE("GPL");
149 MODULE_VERSION(DRV_VERSION);
150
151 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
152
153 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
154 {
155 struct ixgbe_hw *hw = &adapter->hw;
156 u32 gcr;
157 u32 gpie;
158 u32 vmdctl;
159
160 #ifdef CONFIG_PCI_IOV
161 /* disable iov and allow time for transactions to clear */
162 pci_disable_sriov(adapter->pdev);
163 #endif
164
165 /* turn off device IOV mode */
166 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
167 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
168 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
169 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
170 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
171 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
172
173 /* set default pool back to 0 */
174 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
175 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
176 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
177
178 /* take a breather then clean up driver data */
179 msleep(100);
180
181 kfree(adapter->vfinfo);
182 adapter->vfinfo = NULL;
183
184 adapter->num_vfs = 0;
185 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
186 }
187
188 struct ixgbe_reg_info {
189 u32 ofs;
190 char *name;
191 };
192
193 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
194
195 /* General Registers */
196 {IXGBE_CTRL, "CTRL"},
197 {IXGBE_STATUS, "STATUS"},
198 {IXGBE_CTRL_EXT, "CTRL_EXT"},
199
200 /* Interrupt Registers */
201 {IXGBE_EICR, "EICR"},
202
203 /* RX Registers */
204 {IXGBE_SRRCTL(0), "SRRCTL"},
205 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
206 {IXGBE_RDLEN(0), "RDLEN"},
207 {IXGBE_RDH(0), "RDH"},
208 {IXGBE_RDT(0), "RDT"},
209 {IXGBE_RXDCTL(0), "RXDCTL"},
210 {IXGBE_RDBAL(0), "RDBAL"},
211 {IXGBE_RDBAH(0), "RDBAH"},
212
213 /* TX Registers */
214 {IXGBE_TDBAL(0), "TDBAL"},
215 {IXGBE_TDBAH(0), "TDBAH"},
216 {IXGBE_TDLEN(0), "TDLEN"},
217 {IXGBE_TDH(0), "TDH"},
218 {IXGBE_TDT(0), "TDT"},
219 {IXGBE_TXDCTL(0), "TXDCTL"},
220
221 /* List Terminator */
222 {}
223 };
224
225
226 /*
227 * ixgbe_regdump - register printout routine
228 */
229 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
230 {
231 int i = 0, j = 0;
232 char rname[16];
233 u32 regs[64];
234
235 switch (reginfo->ofs) {
236 case IXGBE_SRRCTL(0):
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
239 break;
240 case IXGBE_DCA_RXCTRL(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
243 break;
244 case IXGBE_RDLEN(0):
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
247 break;
248 case IXGBE_RDH(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
251 break;
252 case IXGBE_RDT(0):
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
255 break;
256 case IXGBE_RXDCTL(0):
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
259 break;
260 case IXGBE_RDBAL(0):
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
263 break;
264 case IXGBE_RDBAH(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
267 break;
268 case IXGBE_TDBAL(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
271 break;
272 case IXGBE_TDBAH(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
275 break;
276 case IXGBE_TDLEN(0):
277 for (i = 0; i < 64; i++)
278 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
279 break;
280 case IXGBE_TDH(0):
281 for (i = 0; i < 64; i++)
282 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
283 break;
284 case IXGBE_TDT(0):
285 for (i = 0; i < 64; i++)
286 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
287 break;
288 case IXGBE_TXDCTL(0):
289 for (i = 0; i < 64; i++)
290 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
291 break;
292 default:
293 pr_info("%-15s %08x\n", reginfo->name,
294 IXGBE_READ_REG(hw, reginfo->ofs));
295 return;
296 }
297
298 for (i = 0; i < 8; i++) {
299 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
300 pr_err("%-15s", rname);
301 for (j = 0; j < 8; j++)
302 pr_cont(" %08x", regs[i*8+j]);
303 pr_cont("\n");
304 }
305
306 }
307
308 /*
309 * ixgbe_dump - Print registers, tx-rings and rx-rings
310 */
311 static void ixgbe_dump(struct ixgbe_adapter *adapter)
312 {
313 struct net_device *netdev = adapter->netdev;
314 struct ixgbe_hw *hw = &adapter->hw;
315 struct ixgbe_reg_info *reginfo;
316 int n = 0;
317 struct ixgbe_ring *tx_ring;
318 struct ixgbe_tx_buffer *tx_buffer_info;
319 union ixgbe_adv_tx_desc *tx_desc;
320 struct my_u0 { u64 a; u64 b; } *u0;
321 struct ixgbe_ring *rx_ring;
322 union ixgbe_adv_rx_desc *rx_desc;
323 struct ixgbe_rx_buffer *rx_buffer_info;
324 u32 staterr;
325 int i = 0;
326
327 if (!netif_msg_hw(adapter))
328 return;
329
330 /* Print netdevice Info */
331 if (netdev) {
332 dev_info(&adapter->pdev->dev, "Net device Info\n");
333 pr_info("Device Name state "
334 "trans_start last_rx\n");
335 pr_info("%-15s %016lX %016lX %016lX\n",
336 netdev->name,
337 netdev->state,
338 netdev->trans_start,
339 netdev->last_rx);
340 }
341
342 /* Print Registers */
343 dev_info(&adapter->pdev->dev, "Register Dump\n");
344 pr_info(" Register Name Value\n");
345 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
346 reginfo->name; reginfo++) {
347 ixgbe_regdump(hw, reginfo);
348 }
349
350 /* Print TX Ring Summary */
351 if (!netdev || !netif_running(netdev))
352 goto exit;
353
354 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
355 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
356 for (n = 0; n < adapter->num_tx_queues; n++) {
357 tx_ring = adapter->tx_ring[n];
358 tx_buffer_info =
359 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
360 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
361 n, tx_ring->next_to_use, tx_ring->next_to_clean,
362 (u64)tx_buffer_info->dma,
363 tx_buffer_info->length,
364 tx_buffer_info->next_to_watch,
365 (u64)tx_buffer_info->time_stamp);
366 }
367
368 /* Print TX Rings */
369 if (!netif_msg_tx_done(adapter))
370 goto rx_ring_summary;
371
372 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
373
374 /* Transmit Descriptor Formats
375 *
376 * Advanced Transmit Descriptor
377 * +--------------------------------------------------------------+
378 * 0 | Buffer Address [63:0] |
379 * +--------------------------------------------------------------+
380 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
381 * +--------------------------------------------------------------+
382 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
383 */
384
385 for (n = 0; n < adapter->num_tx_queues; n++) {
386 tx_ring = adapter->tx_ring[n];
387 pr_info("------------------------------------\n");
388 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
389 pr_info("------------------------------------\n");
390 pr_info("T [desc] [address 63:0 ] "
391 "[PlPOIdStDDt Ln] [bi->dma ] "
392 "leng ntw timestamp bi->skb\n");
393
394 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
395 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
396 tx_buffer_info = &tx_ring->tx_buffer_info[i];
397 u0 = (struct my_u0 *)tx_desc;
398 pr_info("T [0x%03X] %016llX %016llX %016llX"
399 " %04X %3X %016llX %p", i,
400 le64_to_cpu(u0->a),
401 le64_to_cpu(u0->b),
402 (u64)tx_buffer_info->dma,
403 tx_buffer_info->length,
404 tx_buffer_info->next_to_watch,
405 (u64)tx_buffer_info->time_stamp,
406 tx_buffer_info->skb);
407 if (i == tx_ring->next_to_use &&
408 i == tx_ring->next_to_clean)
409 pr_cont(" NTC/U\n");
410 else if (i == tx_ring->next_to_use)
411 pr_cont(" NTU\n");
412 else if (i == tx_ring->next_to_clean)
413 pr_cont(" NTC\n");
414 else
415 pr_cont("\n");
416
417 if (netif_msg_pktdata(adapter) &&
418 tx_buffer_info->dma != 0)
419 print_hex_dump(KERN_INFO, "",
420 DUMP_PREFIX_ADDRESS, 16, 1,
421 phys_to_virt(tx_buffer_info->dma),
422 tx_buffer_info->length, true);
423 }
424 }
425
426 /* Print RX Rings Summary */
427 rx_ring_summary:
428 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
429 pr_info("Queue [NTU] [NTC]\n");
430 for (n = 0; n < adapter->num_rx_queues; n++) {
431 rx_ring = adapter->rx_ring[n];
432 pr_info("%5d %5X %5X\n",
433 n, rx_ring->next_to_use, rx_ring->next_to_clean);
434 }
435
436 /* Print RX Rings */
437 if (!netif_msg_rx_status(adapter))
438 goto exit;
439
440 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
441
442 /* Advanced Receive Descriptor (Read) Format
443 * 63 1 0
444 * +-----------------------------------------------------+
445 * 0 | Packet Buffer Address [63:1] |A0/NSE|
446 * +----------------------------------------------+------+
447 * 8 | Header Buffer Address [63:1] | DD |
448 * +-----------------------------------------------------+
449 *
450 *
451 * Advanced Receive Descriptor (Write-Back) Format
452 *
453 * 63 48 47 32 31 30 21 20 16 15 4 3 0
454 * +------------------------------------------------------+
455 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
456 * | Checksum Ident | | | | Type | Type |
457 * +------------------------------------------------------+
458 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
459 * +------------------------------------------------------+
460 * 63 48 47 32 31 20 19 0
461 */
462 for (n = 0; n < adapter->num_rx_queues; n++) {
463 rx_ring = adapter->rx_ring[n];
464 pr_info("------------------------------------\n");
465 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
466 pr_info("------------------------------------\n");
467 pr_info("R [desc] [ PktBuf A0] "
468 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
469 "<-- Adv Rx Read format\n");
470 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
471 "[vl er S cks ln] ---------------- [bi->skb] "
472 "<-- Adv Rx Write-Back format\n");
473
474 for (i = 0; i < rx_ring->count; i++) {
475 rx_buffer_info = &rx_ring->rx_buffer_info[i];
476 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
477 u0 = (struct my_u0 *)rx_desc;
478 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
479 if (staterr & IXGBE_RXD_STAT_DD) {
480 /* Descriptor Done */
481 pr_info("RWB[0x%03X] %016llX "
482 "%016llX ---------------- %p", i,
483 le64_to_cpu(u0->a),
484 le64_to_cpu(u0->b),
485 rx_buffer_info->skb);
486 } else {
487 pr_info("R [0x%03X] %016llX "
488 "%016llX %016llX %p", i,
489 le64_to_cpu(u0->a),
490 le64_to_cpu(u0->b),
491 (u64)rx_buffer_info->dma,
492 rx_buffer_info->skb);
493
494 if (netif_msg_pktdata(adapter)) {
495 print_hex_dump(KERN_INFO, "",
496 DUMP_PREFIX_ADDRESS, 16, 1,
497 phys_to_virt(rx_buffer_info->dma),
498 rx_ring->rx_buf_len, true);
499
500 if (rx_ring->rx_buf_len
501 < IXGBE_RXBUFFER_2048)
502 print_hex_dump(KERN_INFO, "",
503 DUMP_PREFIX_ADDRESS, 16, 1,
504 phys_to_virt(
505 rx_buffer_info->page_dma +
506 rx_buffer_info->page_offset
507 ),
508 PAGE_SIZE/2, true);
509 }
510 }
511
512 if (i == rx_ring->next_to_use)
513 pr_cont(" NTU\n");
514 else if (i == rx_ring->next_to_clean)
515 pr_cont(" NTC\n");
516 else
517 pr_cont("\n");
518
519 }
520 }
521
522 exit:
523 return;
524 }
525
526 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
527 {
528 u32 ctrl_ext;
529
530 /* Let firmware take over control of h/w */
531 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
532 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
533 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
534 }
535
536 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
537 {
538 u32 ctrl_ext;
539
540 /* Let firmware know the driver has taken over */
541 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
542 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
543 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
544 }
545
546 /*
547 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
548 * @adapter: pointer to adapter struct
549 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
550 * @queue: queue to map the corresponding interrupt to
551 * @msix_vector: the vector to map to the corresponding queue
552 *
553 */
554 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
555 u8 queue, u8 msix_vector)
556 {
557 u32 ivar, index;
558 struct ixgbe_hw *hw = &adapter->hw;
559 switch (hw->mac.type) {
560 case ixgbe_mac_82598EB:
561 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
562 if (direction == -1)
563 direction = 0;
564 index = (((direction * 64) + queue) >> 2) & 0x1F;
565 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
566 ivar &= ~(0xFF << (8 * (queue & 0x3)));
567 ivar |= (msix_vector << (8 * (queue & 0x3)));
568 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
569 break;
570 case ixgbe_mac_82599EB:
571 case ixgbe_mac_X540:
572 if (direction == -1) {
573 /* other causes */
574 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
575 index = ((queue & 1) * 8);
576 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
577 ivar &= ~(0xFF << index);
578 ivar |= (msix_vector << index);
579 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
580 break;
581 } else {
582 /* tx or rx causes */
583 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
584 index = ((16 * (queue & 1)) + (8 * direction));
585 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
586 ivar &= ~(0xFF << index);
587 ivar |= (msix_vector << index);
588 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
589 break;
590 }
591 default:
592 break;
593 }
594 }
595
596 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
597 u64 qmask)
598 {
599 u32 mask;
600
601 switch (adapter->hw.mac.type) {
602 case ixgbe_mac_82598EB:
603 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
604 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
605 break;
606 case ixgbe_mac_82599EB:
607 case ixgbe_mac_X540:
608 mask = (qmask & 0xFFFFFFFF);
609 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
610 mask = (qmask >> 32);
611 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
612 break;
613 default:
614 break;
615 }
616 }
617
618 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
619 struct ixgbe_tx_buffer *tx_buffer_info)
620 {
621 if (tx_buffer_info->dma) {
622 if (tx_buffer_info->mapped_as_page)
623 dma_unmap_page(tx_ring->dev,
624 tx_buffer_info->dma,
625 tx_buffer_info->length,
626 DMA_TO_DEVICE);
627 else
628 dma_unmap_single(tx_ring->dev,
629 tx_buffer_info->dma,
630 tx_buffer_info->length,
631 DMA_TO_DEVICE);
632 tx_buffer_info->dma = 0;
633 }
634 if (tx_buffer_info->skb) {
635 dev_kfree_skb_any(tx_buffer_info->skb);
636 tx_buffer_info->skb = NULL;
637 }
638 tx_buffer_info->time_stamp = 0;
639 /* tx_buffer_info must be completely set up in the transmit path */
640 }
641
642 /**
643 * ixgbe_dcb_txq_to_tc - convert a reg index to a traffic class
644 * @adapter: driver private struct
645 * @index: reg idx of queue to query (0-127)
646 *
647 * Helper function to determine the traffic index for a paticular
648 * register index.
649 *
650 * Returns : a tc index for use in range 0-7, or 0-3
651 */
652 static u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx)
653 {
654 int tc = -1;
655 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
656
657 /* if DCB is not enabled the queues have no TC */
658 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
659 return tc;
660
661 /* check valid range */
662 if (reg_idx >= adapter->hw.mac.max_tx_queues)
663 return tc;
664
665 switch (adapter->hw.mac.type) {
666 case ixgbe_mac_82598EB:
667 tc = reg_idx >> 2;
668 break;
669 default:
670 if (dcb_i != 4 && dcb_i != 8)
671 break;
672
673 /* if VMDq is enabled the lowest order bits determine TC */
674 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
675 IXGBE_FLAG_VMDQ_ENABLED)) {
676 tc = reg_idx & (dcb_i - 1);
677 break;
678 }
679
680 /*
681 * Convert the reg_idx into the correct TC. This bitmask
682 * targets the last full 32 ring traffic class and assigns
683 * it a value of 1. From there the rest of the rings are
684 * based on shifting the mask further up to include the
685 * reg_idx / 16 and then reg_idx / 8. It assumes dcB_i
686 * will only ever be 8 or 4 and that reg_idx will never
687 * be greater then 128. The code without the power of 2
688 * optimizations would be:
689 * (((reg_idx % 32) + 32) * dcb_i) >> (9 - reg_idx / 32)
690 */
691 tc = ((reg_idx & 0X1F) + 0x20) * dcb_i;
692 tc >>= 9 - (reg_idx >> 5);
693 }
694
695 return tc;
696 }
697
698 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
699 {
700 struct ixgbe_hw *hw = &adapter->hw;
701 struct ixgbe_hw_stats *hwstats = &adapter->stats;
702 u32 data = 0;
703 u32 xoff[8] = {0};
704 int i;
705
706 if ((hw->fc.current_mode == ixgbe_fc_full) ||
707 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
708 switch (hw->mac.type) {
709 case ixgbe_mac_82598EB:
710 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
711 break;
712 default:
713 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
714 }
715 hwstats->lxoffrxc += data;
716
717 /* refill credits (no tx hang) if we received xoff */
718 if (!data)
719 return;
720
721 for (i = 0; i < adapter->num_tx_queues; i++)
722 clear_bit(__IXGBE_HANG_CHECK_ARMED,
723 &adapter->tx_ring[i]->state);
724 return;
725 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
726 return;
727
728 /* update stats for each tc, only valid with PFC enabled */
729 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
730 switch (hw->mac.type) {
731 case ixgbe_mac_82598EB:
732 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
733 break;
734 default:
735 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
736 }
737 hwstats->pxoffrxc[i] += xoff[i];
738 }
739
740 /* disarm tx queues that have received xoff frames */
741 for (i = 0; i < adapter->num_tx_queues; i++) {
742 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
743 u32 tc = ixgbe_dcb_txq_to_tc(adapter, tx_ring->reg_idx);
744
745 if (xoff[tc])
746 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
747 }
748 }
749
750 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
751 {
752 return ring->tx_stats.completed;
753 }
754
755 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
756 {
757 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
758 struct ixgbe_hw *hw = &adapter->hw;
759
760 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
761 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
762
763 if (head != tail)
764 return (head < tail) ?
765 tail - head : (tail + ring->count - head);
766
767 return 0;
768 }
769
770 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
771 {
772 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
773 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
774 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
775 bool ret = false;
776
777 clear_check_for_tx_hang(tx_ring);
778
779 /*
780 * Check for a hung queue, but be thorough. This verifies
781 * that a transmit has been completed since the previous
782 * check AND there is at least one packet pending. The
783 * ARMED bit is set to indicate a potential hang. The
784 * bit is cleared if a pause frame is received to remove
785 * false hang detection due to PFC or 802.3x frames. By
786 * requiring this to fail twice we avoid races with
787 * pfc clearing the ARMED bit and conditions where we
788 * run the check_tx_hang logic with a transmit completion
789 * pending but without time to complete it yet.
790 */
791 if ((tx_done_old == tx_done) && tx_pending) {
792 /* make sure it is true for two checks in a row */
793 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
794 &tx_ring->state);
795 } else {
796 /* update completed stats and continue */
797 tx_ring->tx_stats.tx_done_old = tx_done;
798 /* reset the countdown */
799 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
800 }
801
802 return ret;
803 }
804
805 #define IXGBE_MAX_TXD_PWR 14
806 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
807
808 /* Tx Descriptors needed, worst case */
809 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
810 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
811 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
812 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
813
814 static void ixgbe_tx_timeout(struct net_device *netdev);
815
816 /**
817 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
818 * @q_vector: structure containing interrupt and ring information
819 * @tx_ring: tx ring to clean
820 **/
821 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
822 struct ixgbe_ring *tx_ring)
823 {
824 struct ixgbe_adapter *adapter = q_vector->adapter;
825 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
826 struct ixgbe_tx_buffer *tx_buffer_info;
827 unsigned int total_bytes = 0, total_packets = 0;
828 u16 i, eop, count = 0;
829
830 i = tx_ring->next_to_clean;
831 eop = tx_ring->tx_buffer_info[i].next_to_watch;
832 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
833
834 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
835 (count < tx_ring->work_limit)) {
836 bool cleaned = false;
837 rmb(); /* read buffer_info after eop_desc */
838 for ( ; !cleaned; count++) {
839 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
840 tx_buffer_info = &tx_ring->tx_buffer_info[i];
841
842 tx_desc->wb.status = 0;
843 cleaned = (i == eop);
844
845 i++;
846 if (i == tx_ring->count)
847 i = 0;
848
849 if (cleaned && tx_buffer_info->skb) {
850 total_bytes += tx_buffer_info->bytecount;
851 total_packets += tx_buffer_info->gso_segs;
852 }
853
854 ixgbe_unmap_and_free_tx_resource(tx_ring,
855 tx_buffer_info);
856 }
857
858 tx_ring->tx_stats.completed++;
859 eop = tx_ring->tx_buffer_info[i].next_to_watch;
860 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
861 }
862
863 tx_ring->next_to_clean = i;
864 tx_ring->total_bytes += total_bytes;
865 tx_ring->total_packets += total_packets;
866 u64_stats_update_begin(&tx_ring->syncp);
867 tx_ring->stats.packets += total_packets;
868 tx_ring->stats.bytes += total_bytes;
869 u64_stats_update_end(&tx_ring->syncp);
870
871 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
872 /* schedule immediate reset if we believe we hung */
873 struct ixgbe_hw *hw = &adapter->hw;
874 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
875 e_err(drv, "Detected Tx Unit Hang\n"
876 " Tx Queue <%d>\n"
877 " TDH, TDT <%x>, <%x>\n"
878 " next_to_use <%x>\n"
879 " next_to_clean <%x>\n"
880 "tx_buffer_info[next_to_clean]\n"
881 " time_stamp <%lx>\n"
882 " jiffies <%lx>\n",
883 tx_ring->queue_index,
884 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
885 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
886 tx_ring->next_to_use, eop,
887 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
888
889 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
890
891 e_info(probe,
892 "tx hang %d detected on queue %d, resetting adapter\n",
893 adapter->tx_timeout_count + 1, tx_ring->queue_index);
894
895 /* schedule immediate reset if we believe we hung */
896 ixgbe_tx_timeout(adapter->netdev);
897
898 /* the adapter is about to reset, no point in enabling stuff */
899 return true;
900 }
901
902 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
903 if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
904 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
905 /* Make sure that anybody stopping the queue after this
906 * sees the new next_to_clean.
907 */
908 smp_mb();
909 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
910 !test_bit(__IXGBE_DOWN, &adapter->state)) {
911 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
912 ++tx_ring->tx_stats.restart_queue;
913 }
914 }
915
916 return count < tx_ring->work_limit;
917 }
918
919 #ifdef CONFIG_IXGBE_DCA
920 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
921 struct ixgbe_ring *rx_ring,
922 int cpu)
923 {
924 struct ixgbe_hw *hw = &adapter->hw;
925 u32 rxctrl;
926 u8 reg_idx = rx_ring->reg_idx;
927
928 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
929 switch (hw->mac.type) {
930 case ixgbe_mac_82598EB:
931 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
932 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
933 break;
934 case ixgbe_mac_82599EB:
935 case ixgbe_mac_X540:
936 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
937 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
938 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
939 break;
940 default:
941 break;
942 }
943 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
944 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
945 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
946 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
947 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
948 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
949 }
950
951 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
952 struct ixgbe_ring *tx_ring,
953 int cpu)
954 {
955 struct ixgbe_hw *hw = &adapter->hw;
956 u32 txctrl;
957 u8 reg_idx = tx_ring->reg_idx;
958
959 switch (hw->mac.type) {
960 case ixgbe_mac_82598EB:
961 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
962 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
963 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
964 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
965 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
966 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
967 break;
968 case ixgbe_mac_82599EB:
969 case ixgbe_mac_X540:
970 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
971 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
972 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
973 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
974 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
975 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
976 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
977 break;
978 default:
979 break;
980 }
981 }
982
983 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
984 {
985 struct ixgbe_adapter *adapter = q_vector->adapter;
986 int cpu = get_cpu();
987 long r_idx;
988 int i;
989
990 if (q_vector->cpu == cpu)
991 goto out_no_update;
992
993 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
994 for (i = 0; i < q_vector->txr_count; i++) {
995 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
996 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
997 r_idx + 1);
998 }
999
1000 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1001 for (i = 0; i < q_vector->rxr_count; i++) {
1002 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
1003 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1004 r_idx + 1);
1005 }
1006
1007 q_vector->cpu = cpu;
1008 out_no_update:
1009 put_cpu();
1010 }
1011
1012 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1013 {
1014 int num_q_vectors;
1015 int i;
1016
1017 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1018 return;
1019
1020 /* always use CB2 mode, difference is masked in the CB driver */
1021 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1022
1023 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1024 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1025 else
1026 num_q_vectors = 1;
1027
1028 for (i = 0; i < num_q_vectors; i++) {
1029 adapter->q_vector[i]->cpu = -1;
1030 ixgbe_update_dca(adapter->q_vector[i]);
1031 }
1032 }
1033
1034 static int __ixgbe_notify_dca(struct device *dev, void *data)
1035 {
1036 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1037 unsigned long event = *(unsigned long *)data;
1038
1039 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1040 return 0;
1041
1042 switch (event) {
1043 case DCA_PROVIDER_ADD:
1044 /* if we're already enabled, don't do it again */
1045 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1046 break;
1047 if (dca_add_requester(dev) == 0) {
1048 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1049 ixgbe_setup_dca(adapter);
1050 break;
1051 }
1052 /* Fall Through since DCA is disabled. */
1053 case DCA_PROVIDER_REMOVE:
1054 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1055 dca_remove_requester(dev);
1056 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1057 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1058 }
1059 break;
1060 }
1061
1062 return 0;
1063 }
1064
1065 #endif /* CONFIG_IXGBE_DCA */
1066 /**
1067 * ixgbe_receive_skb - Send a completed packet up the stack
1068 * @adapter: board private structure
1069 * @skb: packet to send up
1070 * @status: hardware indication of status of receive
1071 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1072 * @rx_desc: rx descriptor
1073 **/
1074 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1075 struct sk_buff *skb, u8 status,
1076 struct ixgbe_ring *ring,
1077 union ixgbe_adv_rx_desc *rx_desc)
1078 {
1079 struct ixgbe_adapter *adapter = q_vector->adapter;
1080 struct napi_struct *napi = &q_vector->napi;
1081 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1082 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1083
1084 if (is_vlan && (tag & VLAN_VID_MASK))
1085 __vlan_hwaccel_put_tag(skb, tag);
1086
1087 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1088 napi_gro_receive(napi, skb);
1089 else
1090 netif_rx(skb);
1091 }
1092
1093 /**
1094 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1095 * @adapter: address of board private structure
1096 * @status_err: hardware indication of status of receive
1097 * @skb: skb currently being received and modified
1098 **/
1099 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1100 union ixgbe_adv_rx_desc *rx_desc,
1101 struct sk_buff *skb)
1102 {
1103 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
1104
1105 skb_checksum_none_assert(skb);
1106
1107 /* Rx csum disabled */
1108 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1109 return;
1110
1111 /* if IP and error */
1112 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1113 (status_err & IXGBE_RXDADV_ERR_IPE)) {
1114 adapter->hw_csum_rx_error++;
1115 return;
1116 }
1117
1118 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1119 return;
1120
1121 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1122 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1123
1124 /*
1125 * 82599 errata, UDP frames with a 0 checksum can be marked as
1126 * checksum errors.
1127 */
1128 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1129 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1130 return;
1131
1132 adapter->hw_csum_rx_error++;
1133 return;
1134 }
1135
1136 /* It must be a TCP or UDP packet with a valid checksum */
1137 skb->ip_summed = CHECKSUM_UNNECESSARY;
1138 }
1139
1140 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1141 {
1142 /*
1143 * Force memory writes to complete before letting h/w
1144 * know there are new descriptors to fetch. (Only
1145 * applicable for weak-ordered memory model archs,
1146 * such as IA-64).
1147 */
1148 wmb();
1149 writel(val, rx_ring->tail);
1150 }
1151
1152 /**
1153 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1154 * @rx_ring: ring to place buffers on
1155 * @cleaned_count: number of buffers to replace
1156 **/
1157 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1158 {
1159 union ixgbe_adv_rx_desc *rx_desc;
1160 struct ixgbe_rx_buffer *bi;
1161 struct sk_buff *skb;
1162 u16 i = rx_ring->next_to_use;
1163
1164 /* do nothing if no valid netdev defined */
1165 if (!rx_ring->netdev)
1166 return;
1167
1168 while (cleaned_count--) {
1169 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1170 bi = &rx_ring->rx_buffer_info[i];
1171 skb = bi->skb;
1172
1173 if (!skb) {
1174 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1175 rx_ring->rx_buf_len);
1176 if (!skb) {
1177 rx_ring->rx_stats.alloc_rx_buff_failed++;
1178 goto no_buffers;
1179 }
1180 /* initialize queue mapping */
1181 skb_record_rx_queue(skb, rx_ring->queue_index);
1182 bi->skb = skb;
1183 }
1184
1185 if (!bi->dma) {
1186 bi->dma = dma_map_single(rx_ring->dev,
1187 skb->data,
1188 rx_ring->rx_buf_len,
1189 DMA_FROM_DEVICE);
1190 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1191 rx_ring->rx_stats.alloc_rx_buff_failed++;
1192 bi->dma = 0;
1193 goto no_buffers;
1194 }
1195 }
1196
1197 if (ring_is_ps_enabled(rx_ring)) {
1198 if (!bi->page) {
1199 bi->page = netdev_alloc_page(rx_ring->netdev);
1200 if (!bi->page) {
1201 rx_ring->rx_stats.alloc_rx_page_failed++;
1202 goto no_buffers;
1203 }
1204 }
1205
1206 if (!bi->page_dma) {
1207 /* use a half page if we're re-using */
1208 bi->page_offset ^= PAGE_SIZE / 2;
1209 bi->page_dma = dma_map_page(rx_ring->dev,
1210 bi->page,
1211 bi->page_offset,
1212 PAGE_SIZE / 2,
1213 DMA_FROM_DEVICE);
1214 if (dma_mapping_error(rx_ring->dev,
1215 bi->page_dma)) {
1216 rx_ring->rx_stats.alloc_rx_page_failed++;
1217 bi->page_dma = 0;
1218 goto no_buffers;
1219 }
1220 }
1221
1222 /* Refresh the desc even if buffer_addrs didn't change
1223 * because each write-back erases this info. */
1224 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1225 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1226 } else {
1227 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1228 rx_desc->read.hdr_addr = 0;
1229 }
1230
1231 i++;
1232 if (i == rx_ring->count)
1233 i = 0;
1234 }
1235
1236 no_buffers:
1237 if (rx_ring->next_to_use != i) {
1238 rx_ring->next_to_use = i;
1239 ixgbe_release_rx_desc(rx_ring, i);
1240 }
1241 }
1242
1243 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1244 {
1245 /* HW will not DMA in data larger than the given buffer, even if it
1246 * parses the (NFS, of course) header to be larger. In that case, it
1247 * fills the header buffer and spills the rest into the page.
1248 */
1249 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1250 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1251 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1252 if (hlen > IXGBE_RX_HDR_SIZE)
1253 hlen = IXGBE_RX_HDR_SIZE;
1254 return hlen;
1255 }
1256
1257 /**
1258 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1259 * @skb: pointer to the last skb in the rsc queue
1260 *
1261 * This function changes a queue full of hw rsc buffers into a completed
1262 * packet. It uses the ->prev pointers to find the first packet and then
1263 * turns it into the frag list owner.
1264 **/
1265 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1266 {
1267 unsigned int frag_list_size = 0;
1268 unsigned int skb_cnt = 1;
1269
1270 while (skb->prev) {
1271 struct sk_buff *prev = skb->prev;
1272 frag_list_size += skb->len;
1273 skb->prev = NULL;
1274 skb = prev;
1275 skb_cnt++;
1276 }
1277
1278 skb_shinfo(skb)->frag_list = skb->next;
1279 skb->next = NULL;
1280 skb->len += frag_list_size;
1281 skb->data_len += frag_list_size;
1282 skb->truesize += frag_list_size;
1283 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1284
1285 return skb;
1286 }
1287
1288 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1289 {
1290 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1291 IXGBE_RXDADV_RSCCNT_MASK);
1292 }
1293
1294 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1295 struct ixgbe_ring *rx_ring,
1296 int *work_done, int work_to_do)
1297 {
1298 struct ixgbe_adapter *adapter = q_vector->adapter;
1299 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1300 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1301 struct sk_buff *skb;
1302 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1303 const int current_node = numa_node_id();
1304 #ifdef IXGBE_FCOE
1305 int ddp_bytes = 0;
1306 #endif /* IXGBE_FCOE */
1307 u32 staterr;
1308 u16 i;
1309 u16 cleaned_count = 0;
1310 bool pkt_is_rsc = false;
1311
1312 i = rx_ring->next_to_clean;
1313 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1314 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1315
1316 while (staterr & IXGBE_RXD_STAT_DD) {
1317 u32 upper_len = 0;
1318
1319 rmb(); /* read descriptor and rx_buffer_info after status DD */
1320
1321 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1322
1323 skb = rx_buffer_info->skb;
1324 rx_buffer_info->skb = NULL;
1325 prefetch(skb->data);
1326
1327 if (ring_is_rsc_enabled(rx_ring))
1328 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1329
1330 /* if this is a skb from previous receive DMA will be 0 */
1331 if (rx_buffer_info->dma) {
1332 u16 hlen;
1333 if (pkt_is_rsc &&
1334 !(staterr & IXGBE_RXD_STAT_EOP) &&
1335 !skb->prev) {
1336 /*
1337 * When HWRSC is enabled, delay unmapping
1338 * of the first packet. It carries the
1339 * header information, HW may still
1340 * access the header after the writeback.
1341 * Only unmap it when EOP is reached
1342 */
1343 IXGBE_RSC_CB(skb)->delay_unmap = true;
1344 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1345 } else {
1346 dma_unmap_single(rx_ring->dev,
1347 rx_buffer_info->dma,
1348 rx_ring->rx_buf_len,
1349 DMA_FROM_DEVICE);
1350 }
1351 rx_buffer_info->dma = 0;
1352
1353 if (ring_is_ps_enabled(rx_ring)) {
1354 hlen = ixgbe_get_hlen(rx_desc);
1355 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1356 } else {
1357 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1358 }
1359
1360 skb_put(skb, hlen);
1361 } else {
1362 /* assume packet split since header is unmapped */
1363 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1364 }
1365
1366 if (upper_len) {
1367 dma_unmap_page(rx_ring->dev,
1368 rx_buffer_info->page_dma,
1369 PAGE_SIZE / 2,
1370 DMA_FROM_DEVICE);
1371 rx_buffer_info->page_dma = 0;
1372 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1373 rx_buffer_info->page,
1374 rx_buffer_info->page_offset,
1375 upper_len);
1376
1377 if ((page_count(rx_buffer_info->page) == 1) &&
1378 (page_to_nid(rx_buffer_info->page) == current_node))
1379 get_page(rx_buffer_info->page);
1380 else
1381 rx_buffer_info->page = NULL;
1382
1383 skb->len += upper_len;
1384 skb->data_len += upper_len;
1385 skb->truesize += upper_len;
1386 }
1387
1388 i++;
1389 if (i == rx_ring->count)
1390 i = 0;
1391
1392 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1393 prefetch(next_rxd);
1394 cleaned_count++;
1395
1396 if (pkt_is_rsc) {
1397 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1398 IXGBE_RXDADV_NEXTP_SHIFT;
1399 next_buffer = &rx_ring->rx_buffer_info[nextp];
1400 } else {
1401 next_buffer = &rx_ring->rx_buffer_info[i];
1402 }
1403
1404 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1405 if (ring_is_ps_enabled(rx_ring)) {
1406 rx_buffer_info->skb = next_buffer->skb;
1407 rx_buffer_info->dma = next_buffer->dma;
1408 next_buffer->skb = skb;
1409 next_buffer->dma = 0;
1410 } else {
1411 skb->next = next_buffer->skb;
1412 skb->next->prev = skb;
1413 }
1414 rx_ring->rx_stats.non_eop_descs++;
1415 goto next_desc;
1416 }
1417
1418 if (skb->prev) {
1419 skb = ixgbe_transform_rsc_queue(skb);
1420 /* if we got here without RSC the packet is invalid */
1421 if (!pkt_is_rsc) {
1422 __pskb_trim(skb, 0);
1423 rx_buffer_info->skb = skb;
1424 goto next_desc;
1425 }
1426 }
1427
1428 if (ring_is_rsc_enabled(rx_ring)) {
1429 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1430 dma_unmap_single(rx_ring->dev,
1431 IXGBE_RSC_CB(skb)->dma,
1432 rx_ring->rx_buf_len,
1433 DMA_FROM_DEVICE);
1434 IXGBE_RSC_CB(skb)->dma = 0;
1435 IXGBE_RSC_CB(skb)->delay_unmap = false;
1436 }
1437 }
1438 if (pkt_is_rsc) {
1439 if (ring_is_ps_enabled(rx_ring))
1440 rx_ring->rx_stats.rsc_count +=
1441 skb_shinfo(skb)->nr_frags;
1442 else
1443 rx_ring->rx_stats.rsc_count +=
1444 IXGBE_RSC_CB(skb)->skb_cnt;
1445 rx_ring->rx_stats.rsc_flush++;
1446 }
1447
1448 /* ERR_MASK will only have valid bits if EOP set */
1449 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1450 /* trim packet back to size 0 and recycle it */
1451 __pskb_trim(skb, 0);
1452 rx_buffer_info->skb = skb;
1453 goto next_desc;
1454 }
1455
1456 ixgbe_rx_checksum(adapter, rx_desc, skb);
1457
1458 /* probably a little skewed due to removing CRC */
1459 total_rx_bytes += skb->len;
1460 total_rx_packets++;
1461
1462 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1463 #ifdef IXGBE_FCOE
1464 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1465 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1466 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1467 if (!ddp_bytes)
1468 goto next_desc;
1469 }
1470 #endif /* IXGBE_FCOE */
1471 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1472
1473 next_desc:
1474 rx_desc->wb.upper.status_error = 0;
1475
1476 (*work_done)++;
1477 if (*work_done >= work_to_do)
1478 break;
1479
1480 /* return some buffers to hardware, one at a time is too slow */
1481 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1482 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1483 cleaned_count = 0;
1484 }
1485
1486 /* use prefetched values */
1487 rx_desc = next_rxd;
1488 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1489 }
1490
1491 rx_ring->next_to_clean = i;
1492 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1493
1494 if (cleaned_count)
1495 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1496
1497 #ifdef IXGBE_FCOE
1498 /* include DDPed FCoE data */
1499 if (ddp_bytes > 0) {
1500 unsigned int mss;
1501
1502 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1503 sizeof(struct fc_frame_header) -
1504 sizeof(struct fcoe_crc_eof);
1505 if (mss > 512)
1506 mss &= ~511;
1507 total_rx_bytes += ddp_bytes;
1508 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1509 }
1510 #endif /* IXGBE_FCOE */
1511
1512 rx_ring->total_packets += total_rx_packets;
1513 rx_ring->total_bytes += total_rx_bytes;
1514 u64_stats_update_begin(&rx_ring->syncp);
1515 rx_ring->stats.packets += total_rx_packets;
1516 rx_ring->stats.bytes += total_rx_bytes;
1517 u64_stats_update_end(&rx_ring->syncp);
1518 }
1519
1520 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1521 /**
1522 * ixgbe_configure_msix - Configure MSI-X hardware
1523 * @adapter: board private structure
1524 *
1525 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1526 * interrupts.
1527 **/
1528 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1529 {
1530 struct ixgbe_q_vector *q_vector;
1531 int i, q_vectors, v_idx, r_idx;
1532 u32 mask;
1533
1534 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1535
1536 /*
1537 * Populate the IVAR table and set the ITR values to the
1538 * corresponding register.
1539 */
1540 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1541 q_vector = adapter->q_vector[v_idx];
1542 /* XXX for_each_set_bit(...) */
1543 r_idx = find_first_bit(q_vector->rxr_idx,
1544 adapter->num_rx_queues);
1545
1546 for (i = 0; i < q_vector->rxr_count; i++) {
1547 u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1548 ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
1549 r_idx = find_next_bit(q_vector->rxr_idx,
1550 adapter->num_rx_queues,
1551 r_idx + 1);
1552 }
1553 r_idx = find_first_bit(q_vector->txr_idx,
1554 adapter->num_tx_queues);
1555
1556 for (i = 0; i < q_vector->txr_count; i++) {
1557 u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1558 ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
1559 r_idx = find_next_bit(q_vector->txr_idx,
1560 adapter->num_tx_queues,
1561 r_idx + 1);
1562 }
1563
1564 if (q_vector->txr_count && !q_vector->rxr_count)
1565 /* tx only */
1566 q_vector->eitr = adapter->tx_eitr_param;
1567 else if (q_vector->rxr_count)
1568 /* rx or mixed */
1569 q_vector->eitr = adapter->rx_eitr_param;
1570
1571 ixgbe_write_eitr(q_vector);
1572 /* If Flow Director is enabled, set interrupt affinity */
1573 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1574 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1575 /*
1576 * Allocate the affinity_hint cpumask, assign the mask
1577 * for this vector, and set our affinity_hint for
1578 * this irq.
1579 */
1580 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1581 GFP_KERNEL))
1582 return;
1583 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1584 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1585 q_vector->affinity_mask);
1586 }
1587 }
1588
1589 switch (adapter->hw.mac.type) {
1590 case ixgbe_mac_82598EB:
1591 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1592 v_idx);
1593 break;
1594 case ixgbe_mac_82599EB:
1595 case ixgbe_mac_X540:
1596 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1597 break;
1598
1599 default:
1600 break;
1601 }
1602 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1603
1604 /* set up to autoclear timer, and the vectors */
1605 mask = IXGBE_EIMS_ENABLE_MASK;
1606 if (adapter->num_vfs)
1607 mask &= ~(IXGBE_EIMS_OTHER |
1608 IXGBE_EIMS_MAILBOX |
1609 IXGBE_EIMS_LSC);
1610 else
1611 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1612 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1613 }
1614
1615 enum latency_range {
1616 lowest_latency = 0,
1617 low_latency = 1,
1618 bulk_latency = 2,
1619 latency_invalid = 255
1620 };
1621
1622 /**
1623 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1624 * @adapter: pointer to adapter
1625 * @eitr: eitr setting (ints per sec) to give last timeslice
1626 * @itr_setting: current throttle rate in ints/second
1627 * @packets: the number of packets during this measurement interval
1628 * @bytes: the number of bytes during this measurement interval
1629 *
1630 * Stores a new ITR value based on packets and byte
1631 * counts during the last interrupt. The advantage of per interrupt
1632 * computation is faster updates and more accurate ITR for the current
1633 * traffic pattern. Constants in this function were computed
1634 * based on theoretical maximum wire speed and thresholds were set based
1635 * on testing data as well as attempting to minimize response time
1636 * while increasing bulk throughput.
1637 * this functionality is controlled by the InterruptThrottleRate module
1638 * parameter (see ixgbe_param.c)
1639 **/
1640 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1641 u32 eitr, u8 itr_setting,
1642 int packets, int bytes)
1643 {
1644 unsigned int retval = itr_setting;
1645 u32 timepassed_us;
1646 u64 bytes_perint;
1647
1648 if (packets == 0)
1649 goto update_itr_done;
1650
1651
1652 /* simple throttlerate management
1653 * 0-20MB/s lowest (100000 ints/s)
1654 * 20-100MB/s low (20000 ints/s)
1655 * 100-1249MB/s bulk (8000 ints/s)
1656 */
1657 /* what was last interrupt timeslice? */
1658 timepassed_us = 1000000/eitr;
1659 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1660
1661 switch (itr_setting) {
1662 case lowest_latency:
1663 if (bytes_perint > adapter->eitr_low)
1664 retval = low_latency;
1665 break;
1666 case low_latency:
1667 if (bytes_perint > adapter->eitr_high)
1668 retval = bulk_latency;
1669 else if (bytes_perint <= adapter->eitr_low)
1670 retval = lowest_latency;
1671 break;
1672 case bulk_latency:
1673 if (bytes_perint <= adapter->eitr_high)
1674 retval = low_latency;
1675 break;
1676 }
1677
1678 update_itr_done:
1679 return retval;
1680 }
1681
1682 /**
1683 * ixgbe_write_eitr - write EITR register in hardware specific way
1684 * @q_vector: structure containing interrupt and ring information
1685 *
1686 * This function is made to be called by ethtool and by the driver
1687 * when it needs to update EITR registers at runtime. Hardware
1688 * specific quirks/differences are taken care of here.
1689 */
1690 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1691 {
1692 struct ixgbe_adapter *adapter = q_vector->adapter;
1693 struct ixgbe_hw *hw = &adapter->hw;
1694 int v_idx = q_vector->v_idx;
1695 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1696
1697 switch (adapter->hw.mac.type) {
1698 case ixgbe_mac_82598EB:
1699 /* must write high and low 16 bits to reset counter */
1700 itr_reg |= (itr_reg << 16);
1701 break;
1702 case ixgbe_mac_82599EB:
1703 case ixgbe_mac_X540:
1704 /*
1705 * 82599 and X540 can support a value of zero, so allow it for
1706 * max interrupt rate, but there is an errata where it can
1707 * not be zero with RSC
1708 */
1709 if (itr_reg == 8 &&
1710 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1711 itr_reg = 0;
1712
1713 /*
1714 * set the WDIS bit to not clear the timer bits and cause an
1715 * immediate assertion of the interrupt
1716 */
1717 itr_reg |= IXGBE_EITR_CNT_WDIS;
1718 break;
1719 default:
1720 break;
1721 }
1722 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1723 }
1724
1725 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1726 {
1727 struct ixgbe_adapter *adapter = q_vector->adapter;
1728 int i, r_idx;
1729 u32 new_itr;
1730 u8 current_itr, ret_itr;
1731
1732 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1733 for (i = 0; i < q_vector->txr_count; i++) {
1734 struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
1735 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1736 q_vector->tx_itr,
1737 tx_ring->total_packets,
1738 tx_ring->total_bytes);
1739 /* if the result for this queue would decrease interrupt
1740 * rate for this vector then use that result */
1741 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1742 q_vector->tx_itr - 1 : ret_itr);
1743 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1744 r_idx + 1);
1745 }
1746
1747 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1748 for (i = 0; i < q_vector->rxr_count; i++) {
1749 struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
1750 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1751 q_vector->rx_itr,
1752 rx_ring->total_packets,
1753 rx_ring->total_bytes);
1754 /* if the result for this queue would decrease interrupt
1755 * rate for this vector then use that result */
1756 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1757 q_vector->rx_itr - 1 : ret_itr);
1758 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1759 r_idx + 1);
1760 }
1761
1762 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1763
1764 switch (current_itr) {
1765 /* counts and packets in update_itr are dependent on these numbers */
1766 case lowest_latency:
1767 new_itr = 100000;
1768 break;
1769 case low_latency:
1770 new_itr = 20000; /* aka hwitr = ~200 */
1771 break;
1772 case bulk_latency:
1773 default:
1774 new_itr = 8000;
1775 break;
1776 }
1777
1778 if (new_itr != q_vector->eitr) {
1779 /* do an exponential smoothing */
1780 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1781
1782 /* save the algorithm value here, not the smoothed one */
1783 q_vector->eitr = new_itr;
1784
1785 ixgbe_write_eitr(q_vector);
1786 }
1787 }
1788
1789 /**
1790 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1791 * @work: pointer to work_struct containing our data
1792 **/
1793 static void ixgbe_check_overtemp_task(struct work_struct *work)
1794 {
1795 struct ixgbe_adapter *adapter = container_of(work,
1796 struct ixgbe_adapter,
1797 check_overtemp_task);
1798 struct ixgbe_hw *hw = &adapter->hw;
1799 u32 eicr = adapter->interrupt_event;
1800
1801 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1802 return;
1803
1804 switch (hw->device_id) {
1805 case IXGBE_DEV_ID_82599_T3_LOM: {
1806 u32 autoneg;
1807 bool link_up = false;
1808
1809 if (hw->mac.ops.check_link)
1810 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1811
1812 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1813 (eicr & IXGBE_EICR_LSC))
1814 /* Check if this is due to overtemp */
1815 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1816 break;
1817 return;
1818 }
1819 default:
1820 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1821 return;
1822 break;
1823 }
1824 e_crit(drv,
1825 "Network adapter has been stopped because it has over heated. "
1826 "Restart the computer. If the problem persists, "
1827 "power off the system and replace the adapter\n");
1828 /* write to clear the interrupt */
1829 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1830 }
1831
1832 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1833 {
1834 struct ixgbe_hw *hw = &adapter->hw;
1835
1836 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1837 (eicr & IXGBE_EICR_GPI_SDP1)) {
1838 e_crit(probe, "Fan has stopped, replace the adapter\n");
1839 /* write to clear the interrupt */
1840 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1841 }
1842 }
1843
1844 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1845 {
1846 struct ixgbe_hw *hw = &adapter->hw;
1847
1848 if (eicr & IXGBE_EICR_GPI_SDP2) {
1849 /* Clear the interrupt */
1850 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1851 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1852 schedule_work(&adapter->sfp_config_module_task);
1853 }
1854
1855 if (eicr & IXGBE_EICR_GPI_SDP1) {
1856 /* Clear the interrupt */
1857 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1858 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1859 schedule_work(&adapter->multispeed_fiber_task);
1860 }
1861 }
1862
1863 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1864 {
1865 struct ixgbe_hw *hw = &adapter->hw;
1866
1867 adapter->lsc_int++;
1868 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1869 adapter->link_check_timeout = jiffies;
1870 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1871 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1872 IXGBE_WRITE_FLUSH(hw);
1873 schedule_work(&adapter->watchdog_task);
1874 }
1875 }
1876
1877 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1878 {
1879 struct net_device *netdev = data;
1880 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1881 struct ixgbe_hw *hw = &adapter->hw;
1882 u32 eicr;
1883
1884 /*
1885 * Workaround for Silicon errata. Use clear-by-write instead
1886 * of clear-by-read. Reading with EICS will return the
1887 * interrupt causes without clearing, which later be done
1888 * with the write to EICR.
1889 */
1890 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1891 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1892
1893 if (eicr & IXGBE_EICR_LSC)
1894 ixgbe_check_lsc(adapter);
1895
1896 if (eicr & IXGBE_EICR_MAILBOX)
1897 ixgbe_msg_task(adapter);
1898
1899 switch (hw->mac.type) {
1900 case ixgbe_mac_82599EB:
1901 ixgbe_check_sfp_event(adapter, eicr);
1902 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1903 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1904 adapter->interrupt_event = eicr;
1905 schedule_work(&adapter->check_overtemp_task);
1906 }
1907 /* now fallthrough to handle Flow Director */
1908 case ixgbe_mac_X540:
1909 /* Handle Flow Director Full threshold interrupt */
1910 if (eicr & IXGBE_EICR_FLOW_DIR) {
1911 int i;
1912 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1913 /* Disable transmits before FDIR Re-initialization */
1914 netif_tx_stop_all_queues(netdev);
1915 for (i = 0; i < adapter->num_tx_queues; i++) {
1916 struct ixgbe_ring *tx_ring =
1917 adapter->tx_ring[i];
1918 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1919 &tx_ring->state))
1920 schedule_work(&adapter->fdir_reinit_task);
1921 }
1922 }
1923 break;
1924 default:
1925 break;
1926 }
1927
1928 ixgbe_check_fan_failure(adapter, eicr);
1929
1930 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1931 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1932
1933 return IRQ_HANDLED;
1934 }
1935
1936 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1937 u64 qmask)
1938 {
1939 u32 mask;
1940 struct ixgbe_hw *hw = &adapter->hw;
1941
1942 switch (hw->mac.type) {
1943 case ixgbe_mac_82598EB:
1944 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1945 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1946 break;
1947 case ixgbe_mac_82599EB:
1948 case ixgbe_mac_X540:
1949 mask = (qmask & 0xFFFFFFFF);
1950 if (mask)
1951 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1952 mask = (qmask >> 32);
1953 if (mask)
1954 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1955 break;
1956 default:
1957 break;
1958 }
1959 /* skip the flush */
1960 }
1961
1962 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1963 u64 qmask)
1964 {
1965 u32 mask;
1966 struct ixgbe_hw *hw = &adapter->hw;
1967
1968 switch (hw->mac.type) {
1969 case ixgbe_mac_82598EB:
1970 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1971 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1972 break;
1973 case ixgbe_mac_82599EB:
1974 case ixgbe_mac_X540:
1975 mask = (qmask & 0xFFFFFFFF);
1976 if (mask)
1977 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1978 mask = (qmask >> 32);
1979 if (mask)
1980 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1981 break;
1982 default:
1983 break;
1984 }
1985 /* skip the flush */
1986 }
1987
1988 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1989 {
1990 struct ixgbe_q_vector *q_vector = data;
1991 struct ixgbe_adapter *adapter = q_vector->adapter;
1992 struct ixgbe_ring *tx_ring;
1993 int i, r_idx;
1994
1995 if (!q_vector->txr_count)
1996 return IRQ_HANDLED;
1997
1998 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1999 for (i = 0; i < q_vector->txr_count; i++) {
2000 tx_ring = adapter->tx_ring[r_idx];
2001 tx_ring->total_bytes = 0;
2002 tx_ring->total_packets = 0;
2003 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2004 r_idx + 1);
2005 }
2006
2007 /* EIAM disabled interrupts (on this vector) for us */
2008 napi_schedule(&q_vector->napi);
2009
2010 return IRQ_HANDLED;
2011 }
2012
2013 /**
2014 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2015 * @irq: unused
2016 * @data: pointer to our q_vector struct for this interrupt vector
2017 **/
2018 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2019 {
2020 struct ixgbe_q_vector *q_vector = data;
2021 struct ixgbe_adapter *adapter = q_vector->adapter;
2022 struct ixgbe_ring *rx_ring;
2023 int r_idx;
2024 int i;
2025
2026 #ifdef CONFIG_IXGBE_DCA
2027 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2028 ixgbe_update_dca(q_vector);
2029 #endif
2030
2031 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2032 for (i = 0; i < q_vector->rxr_count; i++) {
2033 rx_ring = adapter->rx_ring[r_idx];
2034 rx_ring->total_bytes = 0;
2035 rx_ring->total_packets = 0;
2036 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2037 r_idx + 1);
2038 }
2039
2040 if (!q_vector->rxr_count)
2041 return IRQ_HANDLED;
2042
2043 /* EIAM disabled interrupts (on this vector) for us */
2044 napi_schedule(&q_vector->napi);
2045
2046 return IRQ_HANDLED;
2047 }
2048
2049 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2050 {
2051 struct ixgbe_q_vector *q_vector = data;
2052 struct ixgbe_adapter *adapter = q_vector->adapter;
2053 struct ixgbe_ring *ring;
2054 int r_idx;
2055 int i;
2056
2057 if (!q_vector->txr_count && !q_vector->rxr_count)
2058 return IRQ_HANDLED;
2059
2060 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2061 for (i = 0; i < q_vector->txr_count; i++) {
2062 ring = adapter->tx_ring[r_idx];
2063 ring->total_bytes = 0;
2064 ring->total_packets = 0;
2065 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2066 r_idx + 1);
2067 }
2068
2069 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2070 for (i = 0; i < q_vector->rxr_count; i++) {
2071 ring = adapter->rx_ring[r_idx];
2072 ring->total_bytes = 0;
2073 ring->total_packets = 0;
2074 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2075 r_idx + 1);
2076 }
2077
2078 /* EIAM disabled interrupts (on this vector) for us */
2079 napi_schedule(&q_vector->napi);
2080
2081 return IRQ_HANDLED;
2082 }
2083
2084 /**
2085 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2086 * @napi: napi struct with our devices info in it
2087 * @budget: amount of work driver is allowed to do this pass, in packets
2088 *
2089 * This function is optimized for cleaning one queue only on a single
2090 * q_vector!!!
2091 **/
2092 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2093 {
2094 struct ixgbe_q_vector *q_vector =
2095 container_of(napi, struct ixgbe_q_vector, napi);
2096 struct ixgbe_adapter *adapter = q_vector->adapter;
2097 struct ixgbe_ring *rx_ring = NULL;
2098 int work_done = 0;
2099 long r_idx;
2100
2101 #ifdef CONFIG_IXGBE_DCA
2102 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2103 ixgbe_update_dca(q_vector);
2104 #endif
2105
2106 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2107 rx_ring = adapter->rx_ring[r_idx];
2108
2109 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
2110
2111 /* If all Rx work done, exit the polling mode */
2112 if (work_done < budget) {
2113 napi_complete(napi);
2114 if (adapter->rx_itr_setting & 1)
2115 ixgbe_set_itr_msix(q_vector);
2116 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2117 ixgbe_irq_enable_queues(adapter,
2118 ((u64)1 << q_vector->v_idx));
2119 }
2120
2121 return work_done;
2122 }
2123
2124 /**
2125 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2126 * @napi: napi struct with our devices info in it
2127 * @budget: amount of work driver is allowed to do this pass, in packets
2128 *
2129 * This function will clean more than one rx queue associated with a
2130 * q_vector.
2131 **/
2132 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
2133 {
2134 struct ixgbe_q_vector *q_vector =
2135 container_of(napi, struct ixgbe_q_vector, napi);
2136 struct ixgbe_adapter *adapter = q_vector->adapter;
2137 struct ixgbe_ring *ring = NULL;
2138 int work_done = 0, i;
2139 long r_idx;
2140 bool tx_clean_complete = true;
2141
2142 #ifdef CONFIG_IXGBE_DCA
2143 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2144 ixgbe_update_dca(q_vector);
2145 #endif
2146
2147 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2148 for (i = 0; i < q_vector->txr_count; i++) {
2149 ring = adapter->tx_ring[r_idx];
2150 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2151 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2152 r_idx + 1);
2153 }
2154
2155 /* attempt to distribute budget to each queue fairly, but don't allow
2156 * the budget to go below 1 because we'll exit polling */
2157 budget /= (q_vector->rxr_count ?: 1);
2158 budget = max(budget, 1);
2159 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2160 for (i = 0; i < q_vector->rxr_count; i++) {
2161 ring = adapter->rx_ring[r_idx];
2162 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2163 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2164 r_idx + 1);
2165 }
2166
2167 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2168 ring = adapter->rx_ring[r_idx];
2169 /* If all Rx work done, exit the polling mode */
2170 if (work_done < budget) {
2171 napi_complete(napi);
2172 if (adapter->rx_itr_setting & 1)
2173 ixgbe_set_itr_msix(q_vector);
2174 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2175 ixgbe_irq_enable_queues(adapter,
2176 ((u64)1 << q_vector->v_idx));
2177 return 0;
2178 }
2179
2180 return work_done;
2181 }
2182
2183 /**
2184 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2185 * @napi: napi struct with our devices info in it
2186 * @budget: amount of work driver is allowed to do this pass, in packets
2187 *
2188 * This function is optimized for cleaning one queue only on a single
2189 * q_vector!!!
2190 **/
2191 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2192 {
2193 struct ixgbe_q_vector *q_vector =
2194 container_of(napi, struct ixgbe_q_vector, napi);
2195 struct ixgbe_adapter *adapter = q_vector->adapter;
2196 struct ixgbe_ring *tx_ring = NULL;
2197 int work_done = 0;
2198 long r_idx;
2199
2200 #ifdef CONFIG_IXGBE_DCA
2201 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2202 ixgbe_update_dca(q_vector);
2203 #endif
2204
2205 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2206 tx_ring = adapter->tx_ring[r_idx];
2207
2208 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2209 work_done = budget;
2210
2211 /* If all Tx work done, exit the polling mode */
2212 if (work_done < budget) {
2213 napi_complete(napi);
2214 if (adapter->tx_itr_setting & 1)
2215 ixgbe_set_itr_msix(q_vector);
2216 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2217 ixgbe_irq_enable_queues(adapter,
2218 ((u64)1 << q_vector->v_idx));
2219 }
2220
2221 return work_done;
2222 }
2223
2224 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2225 int r_idx)
2226 {
2227 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2228 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2229
2230 set_bit(r_idx, q_vector->rxr_idx);
2231 q_vector->rxr_count++;
2232 rx_ring->q_vector = q_vector;
2233 }
2234
2235 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2236 int t_idx)
2237 {
2238 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2239 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2240
2241 set_bit(t_idx, q_vector->txr_idx);
2242 q_vector->txr_count++;
2243 tx_ring->q_vector = q_vector;
2244 }
2245
2246 /**
2247 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2248 * @adapter: board private structure to initialize
2249 *
2250 * This function maps descriptor rings to the queue-specific vectors
2251 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2252 * one vector per ring/queue, but on a constrained vector budget, we
2253 * group the rings as "efficiently" as possible. You would add new
2254 * mapping configurations in here.
2255 **/
2256 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2257 {
2258 int q_vectors;
2259 int v_start = 0;
2260 int rxr_idx = 0, txr_idx = 0;
2261 int rxr_remaining = adapter->num_rx_queues;
2262 int txr_remaining = adapter->num_tx_queues;
2263 int i, j;
2264 int rqpv, tqpv;
2265 int err = 0;
2266
2267 /* No mapping required if MSI-X is disabled. */
2268 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2269 goto out;
2270
2271 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2272
2273 /*
2274 * The ideal configuration...
2275 * We have enough vectors to map one per queue.
2276 */
2277 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2278 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2279 map_vector_to_rxq(adapter, v_start, rxr_idx);
2280
2281 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2282 map_vector_to_txq(adapter, v_start, txr_idx);
2283
2284 goto out;
2285 }
2286
2287 /*
2288 * If we don't have enough vectors for a 1-to-1
2289 * mapping, we'll have to group them so there are
2290 * multiple queues per vector.
2291 */
2292 /* Re-adjusting *qpv takes care of the remainder. */
2293 for (i = v_start; i < q_vectors; i++) {
2294 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
2295 for (j = 0; j < rqpv; j++) {
2296 map_vector_to_rxq(adapter, i, rxr_idx);
2297 rxr_idx++;
2298 rxr_remaining--;
2299 }
2300 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
2301 for (j = 0; j < tqpv; j++) {
2302 map_vector_to_txq(adapter, i, txr_idx);
2303 txr_idx++;
2304 txr_remaining--;
2305 }
2306 }
2307 out:
2308 return err;
2309 }
2310
2311 /**
2312 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2313 * @adapter: board private structure
2314 *
2315 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2316 * interrupts from the kernel.
2317 **/
2318 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2319 {
2320 struct net_device *netdev = adapter->netdev;
2321 irqreturn_t (*handler)(int, void *);
2322 int i, vector, q_vectors, err;
2323 int ri = 0, ti = 0;
2324
2325 /* Decrement for Other and TCP Timer vectors */
2326 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2327
2328 err = ixgbe_map_rings_to_vectors(adapter);
2329 if (err)
2330 return err;
2331
2332 #define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \
2333 ? &ixgbe_msix_clean_many : \
2334 (_v)->rxr_count ? &ixgbe_msix_clean_rx : \
2335 (_v)->txr_count ? &ixgbe_msix_clean_tx : \
2336 NULL)
2337 for (vector = 0; vector < q_vectors; vector++) {
2338 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2339 handler = SET_HANDLER(q_vector);
2340
2341 if (handler == &ixgbe_msix_clean_rx) {
2342 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2343 "%s-%s-%d", netdev->name, "rx", ri++);
2344 } else if (handler == &ixgbe_msix_clean_tx) {
2345 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2346 "%s-%s-%d", netdev->name, "tx", ti++);
2347 } else if (handler == &ixgbe_msix_clean_many) {
2348 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2349 "%s-%s-%d", netdev->name, "TxRx", ri++);
2350 ti++;
2351 } else {
2352 /* skip this unused q_vector */
2353 continue;
2354 }
2355 err = request_irq(adapter->msix_entries[vector].vector,
2356 handler, 0, q_vector->name,
2357 q_vector);
2358 if (err) {
2359 e_err(probe, "request_irq failed for MSIX interrupt "
2360 "Error: %d\n", err);
2361 goto free_queue_irqs;
2362 }
2363 }
2364
2365 sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
2366 err = request_irq(adapter->msix_entries[vector].vector,
2367 ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev);
2368 if (err) {
2369 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2370 goto free_queue_irqs;
2371 }
2372
2373 return 0;
2374
2375 free_queue_irqs:
2376 for (i = vector - 1; i >= 0; i--)
2377 free_irq(adapter->msix_entries[--vector].vector,
2378 adapter->q_vector[i]);
2379 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2380 pci_disable_msix(adapter->pdev);
2381 kfree(adapter->msix_entries);
2382 adapter->msix_entries = NULL;
2383 return err;
2384 }
2385
2386 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2387 {
2388 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2389 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2390 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2391 u32 new_itr = q_vector->eitr;
2392 u8 current_itr;
2393
2394 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2395 q_vector->tx_itr,
2396 tx_ring->total_packets,
2397 tx_ring->total_bytes);
2398 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2399 q_vector->rx_itr,
2400 rx_ring->total_packets,
2401 rx_ring->total_bytes);
2402
2403 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2404
2405 switch (current_itr) {
2406 /* counts and packets in update_itr are dependent on these numbers */
2407 case lowest_latency:
2408 new_itr = 100000;
2409 break;
2410 case low_latency:
2411 new_itr = 20000; /* aka hwitr = ~200 */
2412 break;
2413 case bulk_latency:
2414 new_itr = 8000;
2415 break;
2416 default:
2417 break;
2418 }
2419
2420 if (new_itr != q_vector->eitr) {
2421 /* do an exponential smoothing */
2422 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
2423
2424 /* save the algorithm value here */
2425 q_vector->eitr = new_itr;
2426
2427 ixgbe_write_eitr(q_vector);
2428 }
2429 }
2430
2431 /**
2432 * ixgbe_irq_enable - Enable default interrupt generation settings
2433 * @adapter: board private structure
2434 **/
2435 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2436 bool flush)
2437 {
2438 u32 mask;
2439
2440 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2441 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2442 mask |= IXGBE_EIMS_GPI_SDP0;
2443 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2444 mask |= IXGBE_EIMS_GPI_SDP1;
2445 switch (adapter->hw.mac.type) {
2446 case ixgbe_mac_82599EB:
2447 case ixgbe_mac_X540:
2448 mask |= IXGBE_EIMS_ECC;
2449 mask |= IXGBE_EIMS_GPI_SDP1;
2450 mask |= IXGBE_EIMS_GPI_SDP2;
2451 if (adapter->num_vfs)
2452 mask |= IXGBE_EIMS_MAILBOX;
2453 break;
2454 default:
2455 break;
2456 }
2457 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2458 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2459 mask |= IXGBE_EIMS_FLOW_DIR;
2460
2461 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2462 if (queues)
2463 ixgbe_irq_enable_queues(adapter, ~0);
2464 if (flush)
2465 IXGBE_WRITE_FLUSH(&adapter->hw);
2466
2467 if (adapter->num_vfs > 32) {
2468 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2469 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2470 }
2471 }
2472
2473 /**
2474 * ixgbe_intr - legacy mode Interrupt Handler
2475 * @irq: interrupt number
2476 * @data: pointer to a network interface device structure
2477 **/
2478 static irqreturn_t ixgbe_intr(int irq, void *data)
2479 {
2480 struct net_device *netdev = data;
2481 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2482 struct ixgbe_hw *hw = &adapter->hw;
2483 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2484 u32 eicr;
2485
2486 /*
2487 * Workaround for silicon errata on 82598. Mask the interrupts
2488 * before the read of EICR.
2489 */
2490 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2491
2492 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2493 * therefore no explict interrupt disable is necessary */
2494 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2495 if (!eicr) {
2496 /*
2497 * shared interrupt alert!
2498 * make sure interrupts are enabled because the read will
2499 * have disabled interrupts due to EIAM
2500 * finish the workaround of silicon errata on 82598. Unmask
2501 * the interrupt that we masked before the EICR read.
2502 */
2503 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2504 ixgbe_irq_enable(adapter, true, true);
2505 return IRQ_NONE; /* Not our interrupt */
2506 }
2507
2508 if (eicr & IXGBE_EICR_LSC)
2509 ixgbe_check_lsc(adapter);
2510
2511 switch (hw->mac.type) {
2512 case ixgbe_mac_82599EB:
2513 ixgbe_check_sfp_event(adapter, eicr);
2514 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2515 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2516 adapter->interrupt_event = eicr;
2517 schedule_work(&adapter->check_overtemp_task);
2518 }
2519 break;
2520 default:
2521 break;
2522 }
2523
2524 ixgbe_check_fan_failure(adapter, eicr);
2525
2526 if (napi_schedule_prep(&(q_vector->napi))) {
2527 adapter->tx_ring[0]->total_packets = 0;
2528 adapter->tx_ring[0]->total_bytes = 0;
2529 adapter->rx_ring[0]->total_packets = 0;
2530 adapter->rx_ring[0]->total_bytes = 0;
2531 /* would disable interrupts here but EIAM disabled it */
2532 __napi_schedule(&(q_vector->napi));
2533 }
2534
2535 /*
2536 * re-enable link(maybe) and non-queue interrupts, no flush.
2537 * ixgbe_poll will re-enable the queue interrupts
2538 */
2539
2540 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2541 ixgbe_irq_enable(adapter, false, false);
2542
2543 return IRQ_HANDLED;
2544 }
2545
2546 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2547 {
2548 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2549
2550 for (i = 0; i < q_vectors; i++) {
2551 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2552 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2553 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2554 q_vector->rxr_count = 0;
2555 q_vector->txr_count = 0;
2556 }
2557 }
2558
2559 /**
2560 * ixgbe_request_irq - initialize interrupts
2561 * @adapter: board private structure
2562 *
2563 * Attempts to configure interrupts using the best available
2564 * capabilities of the hardware and kernel.
2565 **/
2566 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2567 {
2568 struct net_device *netdev = adapter->netdev;
2569 int err;
2570
2571 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2572 err = ixgbe_request_msix_irqs(adapter);
2573 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2574 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2575 netdev->name, netdev);
2576 } else {
2577 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2578 netdev->name, netdev);
2579 }
2580
2581 if (err)
2582 e_err(probe, "request_irq failed, Error %d\n", err);
2583
2584 return err;
2585 }
2586
2587 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2588 {
2589 struct net_device *netdev = adapter->netdev;
2590
2591 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2592 int i, q_vectors;
2593
2594 q_vectors = adapter->num_msix_vectors;
2595
2596 i = q_vectors - 1;
2597 free_irq(adapter->msix_entries[i].vector, netdev);
2598
2599 i--;
2600 for (; i >= 0; i--) {
2601 /* free only the irqs that were actually requested */
2602 if (!adapter->q_vector[i]->rxr_count &&
2603 !adapter->q_vector[i]->txr_count)
2604 continue;
2605
2606 free_irq(adapter->msix_entries[i].vector,
2607 adapter->q_vector[i]);
2608 }
2609
2610 ixgbe_reset_q_vectors(adapter);
2611 } else {
2612 free_irq(adapter->pdev->irq, netdev);
2613 }
2614 }
2615
2616 /**
2617 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2618 * @adapter: board private structure
2619 **/
2620 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2621 {
2622 switch (adapter->hw.mac.type) {
2623 case ixgbe_mac_82598EB:
2624 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2625 break;
2626 case ixgbe_mac_82599EB:
2627 case ixgbe_mac_X540:
2628 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2629 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2630 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2631 if (adapter->num_vfs > 32)
2632 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2633 break;
2634 default:
2635 break;
2636 }
2637 IXGBE_WRITE_FLUSH(&adapter->hw);
2638 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2639 int i;
2640 for (i = 0; i < adapter->num_msix_vectors; i++)
2641 synchronize_irq(adapter->msix_entries[i].vector);
2642 } else {
2643 synchronize_irq(adapter->pdev->irq);
2644 }
2645 }
2646
2647 /**
2648 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2649 *
2650 **/
2651 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2652 {
2653 struct ixgbe_hw *hw = &adapter->hw;
2654
2655 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2656 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2657
2658 ixgbe_set_ivar(adapter, 0, 0, 0);
2659 ixgbe_set_ivar(adapter, 1, 0, 0);
2660
2661 map_vector_to_rxq(adapter, 0, 0);
2662 map_vector_to_txq(adapter, 0, 0);
2663
2664 e_info(hw, "Legacy interrupt IVAR setup done\n");
2665 }
2666
2667 /**
2668 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2669 * @adapter: board private structure
2670 * @ring: structure containing ring specific data
2671 *
2672 * Configure the Tx descriptor ring after a reset.
2673 **/
2674 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2675 struct ixgbe_ring *ring)
2676 {
2677 struct ixgbe_hw *hw = &adapter->hw;
2678 u64 tdba = ring->dma;
2679 int wait_loop = 10;
2680 u32 txdctl;
2681 u8 reg_idx = ring->reg_idx;
2682
2683 /* disable queue to avoid issues while updating state */
2684 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2685 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2686 txdctl & ~IXGBE_TXDCTL_ENABLE);
2687 IXGBE_WRITE_FLUSH(hw);
2688
2689 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2690 (tdba & DMA_BIT_MASK(32)));
2691 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2692 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2693 ring->count * sizeof(union ixgbe_adv_tx_desc));
2694 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2695 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2696 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2697
2698 /* configure fetching thresholds */
2699 if (adapter->rx_itr_setting == 0) {
2700 /* cannot set wthresh when itr==0 */
2701 txdctl &= ~0x007F0000;
2702 } else {
2703 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2704 txdctl |= (8 << 16);
2705 }
2706 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2707 /* PThresh workaround for Tx hang with DFP enabled. */
2708 txdctl |= 32;
2709 }
2710
2711 /* reinitialize flowdirector state */
2712 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2713 adapter->atr_sample_rate) {
2714 ring->atr_sample_rate = adapter->atr_sample_rate;
2715 ring->atr_count = 0;
2716 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2717 } else {
2718 ring->atr_sample_rate = 0;
2719 }
2720
2721 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2722
2723 /* enable queue */
2724 txdctl |= IXGBE_TXDCTL_ENABLE;
2725 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2726
2727 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2728 if (hw->mac.type == ixgbe_mac_82598EB &&
2729 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2730 return;
2731
2732 /* poll to verify queue is enabled */
2733 do {
2734 msleep(1);
2735 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2736 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2737 if (!wait_loop)
2738 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2739 }
2740
2741 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2742 {
2743 struct ixgbe_hw *hw = &adapter->hw;
2744 u32 rttdcs;
2745 u32 mask;
2746
2747 if (hw->mac.type == ixgbe_mac_82598EB)
2748 return;
2749
2750 /* disable the arbiter while setting MTQC */
2751 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2752 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2753 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2754
2755 /* set transmit pool layout */
2756 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2757 switch (adapter->flags & mask) {
2758
2759 case (IXGBE_FLAG_SRIOV_ENABLED):
2760 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2761 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2762 break;
2763
2764 case (IXGBE_FLAG_DCB_ENABLED):
2765 /* We enable 8 traffic classes, DCB only */
2766 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2767 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2768 break;
2769
2770 default:
2771 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2772 break;
2773 }
2774
2775 /* re-enable the arbiter */
2776 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2777 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2778 }
2779
2780 /**
2781 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2782 * @adapter: board private structure
2783 *
2784 * Configure the Tx unit of the MAC after a reset.
2785 **/
2786 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2787 {
2788 struct ixgbe_hw *hw = &adapter->hw;
2789 u32 dmatxctl;
2790 u32 i;
2791
2792 ixgbe_setup_mtqc(adapter);
2793
2794 if (hw->mac.type != ixgbe_mac_82598EB) {
2795 /* DMATXCTL.EN must be before Tx queues are enabled */
2796 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2797 dmatxctl |= IXGBE_DMATXCTL_TE;
2798 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2799 }
2800
2801 /* Setup the HW Tx Head and Tail descriptor pointers */
2802 for (i = 0; i < adapter->num_tx_queues; i++)
2803 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2804 }
2805
2806 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2807
2808 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2809 struct ixgbe_ring *rx_ring)
2810 {
2811 u32 srrctl;
2812 u8 reg_idx = rx_ring->reg_idx;
2813
2814 switch (adapter->hw.mac.type) {
2815 case ixgbe_mac_82598EB: {
2816 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2817 const int mask = feature[RING_F_RSS].mask;
2818 reg_idx = reg_idx & mask;
2819 }
2820 break;
2821 case ixgbe_mac_82599EB:
2822 case ixgbe_mac_X540:
2823 default:
2824 break;
2825 }
2826
2827 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2828
2829 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2830 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2831 if (adapter->num_vfs)
2832 srrctl |= IXGBE_SRRCTL_DROP_EN;
2833
2834 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2835 IXGBE_SRRCTL_BSIZEHDR_MASK;
2836
2837 if (ring_is_ps_enabled(rx_ring)) {
2838 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2839 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2840 #else
2841 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2842 #endif
2843 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2844 } else {
2845 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2846 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2847 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2848 }
2849
2850 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2851 }
2852
2853 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2854 {
2855 struct ixgbe_hw *hw = &adapter->hw;
2856 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2857 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2858 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2859 u32 mrqc = 0, reta = 0;
2860 u32 rxcsum;
2861 int i, j;
2862 int mask;
2863
2864 /* Fill out hash function seeds */
2865 for (i = 0; i < 10; i++)
2866 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2867
2868 /* Fill out redirection table */
2869 for (i = 0, j = 0; i < 128; i++, j++) {
2870 if (j == adapter->ring_feature[RING_F_RSS].indices)
2871 j = 0;
2872 /* reta = 4-byte sliding window of
2873 * 0x00..(indices-1)(indices-1)00..etc. */
2874 reta = (reta << 8) | (j * 0x11);
2875 if ((i & 3) == 3)
2876 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2877 }
2878
2879 /* Disable indicating checksum in descriptor, enables RSS hash */
2880 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2881 rxcsum |= IXGBE_RXCSUM_PCSD;
2882 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2883
2884 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2885 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2886 else
2887 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2888 #ifdef CONFIG_IXGBE_DCB
2889 | IXGBE_FLAG_DCB_ENABLED
2890 #endif
2891 | IXGBE_FLAG_SRIOV_ENABLED
2892 );
2893
2894 switch (mask) {
2895 case (IXGBE_FLAG_RSS_ENABLED):
2896 mrqc = IXGBE_MRQC_RSSEN;
2897 break;
2898 case (IXGBE_FLAG_SRIOV_ENABLED):
2899 mrqc = IXGBE_MRQC_VMDQEN;
2900 break;
2901 #ifdef CONFIG_IXGBE_DCB
2902 case (IXGBE_FLAG_DCB_ENABLED):
2903 mrqc = IXGBE_MRQC_RT8TCEN;
2904 break;
2905 #endif /* CONFIG_IXGBE_DCB */
2906 default:
2907 break;
2908 }
2909
2910 /* Perform hash on these packet types */
2911 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2912 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2913 | IXGBE_MRQC_RSS_FIELD_IPV6
2914 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2915
2916 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2917 }
2918
2919 /**
2920 * ixgbe_clear_rscctl - disable RSC for the indicated ring
2921 * @adapter: address of board private structure
2922 * @ring: structure containing ring specific data
2923 **/
2924 void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
2925 struct ixgbe_ring *ring)
2926 {
2927 struct ixgbe_hw *hw = &adapter->hw;
2928 u32 rscctrl;
2929 u8 reg_idx = ring->reg_idx;
2930
2931 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2932 rscctrl &= ~IXGBE_RSCCTL_RSCEN;
2933 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2934 }
2935
2936 /**
2937 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2938 * @adapter: address of board private structure
2939 * @index: index of ring to set
2940 **/
2941 void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2942 struct ixgbe_ring *ring)
2943 {
2944 struct ixgbe_hw *hw = &adapter->hw;
2945 u32 rscctrl;
2946 int rx_buf_len;
2947 u8 reg_idx = ring->reg_idx;
2948
2949 if (!ring_is_rsc_enabled(ring))
2950 return;
2951
2952 rx_buf_len = ring->rx_buf_len;
2953 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2954 rscctrl |= IXGBE_RSCCTL_RSCEN;
2955 /*
2956 * we must limit the number of descriptors so that the
2957 * total size of max desc * buf_len is not greater
2958 * than 65535
2959 */
2960 if (ring_is_ps_enabled(ring)) {
2961 #if (MAX_SKB_FRAGS > 16)
2962 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2963 #elif (MAX_SKB_FRAGS > 8)
2964 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2965 #elif (MAX_SKB_FRAGS > 4)
2966 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2967 #else
2968 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2969 #endif
2970 } else {
2971 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2972 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2973 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2974 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2975 else
2976 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2977 }
2978 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2979 }
2980
2981 /**
2982 * ixgbe_set_uta - Set unicast filter table address
2983 * @adapter: board private structure
2984 *
2985 * The unicast table address is a register array of 32-bit registers.
2986 * The table is meant to be used in a way similar to how the MTA is used
2987 * however due to certain limitations in the hardware it is necessary to
2988 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2989 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2990 **/
2991 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2992 {
2993 struct ixgbe_hw *hw = &adapter->hw;
2994 int i;
2995
2996 /* The UTA table only exists on 82599 hardware and newer */
2997 if (hw->mac.type < ixgbe_mac_82599EB)
2998 return;
2999
3000 /* we only need to do this if VMDq is enabled */
3001 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3002 return;
3003
3004 for (i = 0; i < 128; i++)
3005 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3006 }
3007
3008 #define IXGBE_MAX_RX_DESC_POLL 10
3009 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3010 struct ixgbe_ring *ring)
3011 {
3012 struct ixgbe_hw *hw = &adapter->hw;
3013 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3014 u32 rxdctl;
3015 u8 reg_idx = ring->reg_idx;
3016
3017 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3018 if (hw->mac.type == ixgbe_mac_82598EB &&
3019 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3020 return;
3021
3022 do {
3023 msleep(1);
3024 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3025 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3026
3027 if (!wait_loop) {
3028 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3029 "the polling period\n", reg_idx);
3030 }
3031 }
3032
3033 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3034 struct ixgbe_ring *ring)
3035 {
3036 struct ixgbe_hw *hw = &adapter->hw;
3037 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3038 u32 rxdctl;
3039 u8 reg_idx = ring->reg_idx;
3040
3041 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3042 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3043
3044 /* write value back with RXDCTL.ENABLE bit cleared */
3045 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3046
3047 if (hw->mac.type == ixgbe_mac_82598EB &&
3048 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3049 return;
3050
3051 /* the hardware may take up to 100us to really disable the rx queue */
3052 do {
3053 udelay(10);
3054 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3055 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3056
3057 if (!wait_loop) {
3058 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3059 "the polling period\n", reg_idx);
3060 }
3061 }
3062
3063 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3064 struct ixgbe_ring *ring)
3065 {
3066 struct ixgbe_hw *hw = &adapter->hw;
3067 u64 rdba = ring->dma;
3068 u32 rxdctl;
3069 u8 reg_idx = ring->reg_idx;
3070
3071 /* disable queue to avoid issues while updating state */
3072 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3073 ixgbe_disable_rx_queue(adapter, ring);
3074
3075 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3076 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3077 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3078 ring->count * sizeof(union ixgbe_adv_rx_desc));
3079 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3080 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3081 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3082
3083 ixgbe_configure_srrctl(adapter, ring);
3084 ixgbe_configure_rscctl(adapter, ring);
3085
3086 /* If operating in IOV mode set RLPML for X540 */
3087 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3088 hw->mac.type == ixgbe_mac_X540) {
3089 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3090 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3091 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3092 }
3093
3094 if (hw->mac.type == ixgbe_mac_82598EB) {
3095 /*
3096 * enable cache line friendly hardware writes:
3097 * PTHRESH=32 descriptors (half the internal cache),
3098 * this also removes ugly rx_no_buffer_count increment
3099 * HTHRESH=4 descriptors (to minimize latency on fetch)
3100 * WTHRESH=8 burst writeback up to two cache lines
3101 */
3102 rxdctl &= ~0x3FFFFF;
3103 rxdctl |= 0x080420;
3104 }
3105
3106 /* enable receive descriptor ring */
3107 rxdctl |= IXGBE_RXDCTL_ENABLE;
3108 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3109
3110 ixgbe_rx_desc_queue_enable(adapter, ring);
3111 ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
3112 }
3113
3114 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3115 {
3116 struct ixgbe_hw *hw = &adapter->hw;
3117 int p;
3118
3119 /* PSRTYPE must be initialized in non 82598 adapters */
3120 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3121 IXGBE_PSRTYPE_UDPHDR |
3122 IXGBE_PSRTYPE_IPV4HDR |
3123 IXGBE_PSRTYPE_L2HDR |
3124 IXGBE_PSRTYPE_IPV6HDR;
3125
3126 if (hw->mac.type == ixgbe_mac_82598EB)
3127 return;
3128
3129 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3130 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3131
3132 for (p = 0; p < adapter->num_rx_pools; p++)
3133 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3134 psrtype);
3135 }
3136
3137 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3138 {
3139 struct ixgbe_hw *hw = &adapter->hw;
3140 u32 gcr_ext;
3141 u32 vt_reg_bits;
3142 u32 reg_offset, vf_shift;
3143 u32 vmdctl;
3144
3145 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3146 return;
3147
3148 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3149 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3150 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3151 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3152
3153 vf_shift = adapter->num_vfs % 32;
3154 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3155
3156 /* Enable only the PF's pool for Tx/Rx */
3157 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3158 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3159 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3160 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3161 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3162
3163 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3164 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3165
3166 /*
3167 * Set up VF register offsets for selected VT Mode,
3168 * i.e. 32 or 64 VFs for SR-IOV
3169 */
3170 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3171 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3172 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3173 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3174
3175 /* enable Tx loopback for VF/PF communication */
3176 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3177 /* Enable MAC Anti-Spoofing */
3178 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3179 adapter->num_vfs);
3180 }
3181
3182 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3183 {
3184 struct ixgbe_hw *hw = &adapter->hw;
3185 struct net_device *netdev = adapter->netdev;
3186 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3187 int rx_buf_len;
3188 struct ixgbe_ring *rx_ring;
3189 int i;
3190 u32 mhadd, hlreg0;
3191
3192 /* Decide whether to use packet split mode or not */
3193 /* On by default */
3194 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3195
3196 /* Do not use packet split if we're in SR-IOV Mode */
3197 if (adapter->num_vfs)
3198 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3199
3200 /* Disable packet split due to 82599 erratum #45 */
3201 if (hw->mac.type == ixgbe_mac_82599EB)
3202 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3203
3204 /* Set the RX buffer length according to the mode */
3205 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3206 rx_buf_len = IXGBE_RX_HDR_SIZE;
3207 } else {
3208 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3209 (netdev->mtu <= ETH_DATA_LEN))
3210 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3211 else
3212 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
3213 }
3214
3215 #ifdef IXGBE_FCOE
3216 /* adjust max frame to be able to do baby jumbo for FCoE */
3217 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3218 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3219 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3220
3221 #endif /* IXGBE_FCOE */
3222 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3223 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3224 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3225 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3226
3227 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3228 }
3229
3230 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3231 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3232 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3233 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3234
3235 /*
3236 * Setup the HW Rx Head and Tail Descriptor Pointers and
3237 * the Base and Length of the Rx Descriptor Ring
3238 */
3239 for (i = 0; i < adapter->num_rx_queues; i++) {
3240 rx_ring = adapter->rx_ring[i];
3241 rx_ring->rx_buf_len = rx_buf_len;
3242
3243 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
3244 set_ring_ps_enabled(rx_ring);
3245 else
3246 clear_ring_ps_enabled(rx_ring);
3247
3248 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3249 set_ring_rsc_enabled(rx_ring);
3250 else
3251 clear_ring_rsc_enabled(rx_ring);
3252
3253 #ifdef IXGBE_FCOE
3254 if (netdev->features & NETIF_F_FCOE_MTU) {
3255 struct ixgbe_ring_feature *f;
3256 f = &adapter->ring_feature[RING_F_FCOE];
3257 if ((i >= f->mask) && (i < f->mask + f->indices)) {
3258 clear_ring_ps_enabled(rx_ring);
3259 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3260 rx_ring->rx_buf_len =
3261 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3262 } else if (!ring_is_rsc_enabled(rx_ring) &&
3263 !ring_is_ps_enabled(rx_ring)) {
3264 rx_ring->rx_buf_len =
3265 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3266 }
3267 }
3268 #endif /* IXGBE_FCOE */
3269 }
3270 }
3271
3272 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3273 {
3274 struct ixgbe_hw *hw = &adapter->hw;
3275 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3276
3277 switch (hw->mac.type) {
3278 case ixgbe_mac_82598EB:
3279 /*
3280 * For VMDq support of different descriptor types or
3281 * buffer sizes through the use of multiple SRRCTL
3282 * registers, RDRXCTL.MVMEN must be set to 1
3283 *
3284 * also, the manual doesn't mention it clearly but DCA hints
3285 * will only use queue 0's tags unless this bit is set. Side
3286 * effects of setting this bit are only that SRRCTL must be
3287 * fully programmed [0..15]
3288 */
3289 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3290 break;
3291 case ixgbe_mac_82599EB:
3292 case ixgbe_mac_X540:
3293 /* Disable RSC for ACK packets */
3294 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3295 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3296 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3297 /* hardware requires some bits to be set by default */
3298 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3299 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3300 break;
3301 default:
3302 /* We should do nothing since we don't know this hardware */
3303 return;
3304 }
3305
3306 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3307 }
3308
3309 /**
3310 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3311 * @adapter: board private structure
3312 *
3313 * Configure the Rx unit of the MAC after a reset.
3314 **/
3315 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3316 {
3317 struct ixgbe_hw *hw = &adapter->hw;
3318 int i;
3319 u32 rxctrl;
3320
3321 /* disable receives while setting up the descriptors */
3322 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3323 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3324
3325 ixgbe_setup_psrtype(adapter);
3326 ixgbe_setup_rdrxctl(adapter);
3327
3328 /* Program registers for the distribution of queues */
3329 ixgbe_setup_mrqc(adapter);
3330
3331 ixgbe_set_uta(adapter);
3332
3333 /* set_rx_buffer_len must be called before ring initialization */
3334 ixgbe_set_rx_buffer_len(adapter);
3335
3336 /*
3337 * Setup the HW Rx Head and Tail Descriptor Pointers and
3338 * the Base and Length of the Rx Descriptor Ring
3339 */
3340 for (i = 0; i < adapter->num_rx_queues; i++)
3341 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3342
3343 /* disable drop enable for 82598 parts */
3344 if (hw->mac.type == ixgbe_mac_82598EB)
3345 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3346
3347 /* enable all receives */
3348 rxctrl |= IXGBE_RXCTRL_RXEN;
3349 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3350 }
3351
3352 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3353 {
3354 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3355 struct ixgbe_hw *hw = &adapter->hw;
3356 int pool_ndx = adapter->num_vfs;
3357
3358 /* add VID to filter table */
3359 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3360 set_bit(vid, adapter->active_vlans);
3361 }
3362
3363 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3364 {
3365 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3366 struct ixgbe_hw *hw = &adapter->hw;
3367 int pool_ndx = adapter->num_vfs;
3368
3369 /* remove VID from filter table */
3370 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3371 clear_bit(vid, adapter->active_vlans);
3372 }
3373
3374 /**
3375 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3376 * @adapter: driver data
3377 */
3378 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3379 {
3380 struct ixgbe_hw *hw = &adapter->hw;
3381 u32 vlnctrl;
3382
3383 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3384 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3385 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3386 }
3387
3388 /**
3389 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3390 * @adapter: driver data
3391 */
3392 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3393 {
3394 struct ixgbe_hw *hw = &adapter->hw;
3395 u32 vlnctrl;
3396
3397 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3398 vlnctrl |= IXGBE_VLNCTRL_VFE;
3399 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3400 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3401 }
3402
3403 /**
3404 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3405 * @adapter: driver data
3406 */
3407 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3408 {
3409 struct ixgbe_hw *hw = &adapter->hw;
3410 u32 vlnctrl;
3411 int i, j;
3412
3413 switch (hw->mac.type) {
3414 case ixgbe_mac_82598EB:
3415 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3416 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3417 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3418 break;
3419 case ixgbe_mac_82599EB:
3420 case ixgbe_mac_X540:
3421 for (i = 0; i < adapter->num_rx_queues; i++) {
3422 j = adapter->rx_ring[i]->reg_idx;
3423 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3424 vlnctrl &= ~IXGBE_RXDCTL_VME;
3425 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3426 }
3427 break;
3428 default:
3429 break;
3430 }
3431 }
3432
3433 /**
3434 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3435 * @adapter: driver data
3436 */
3437 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3438 {
3439 struct ixgbe_hw *hw = &adapter->hw;
3440 u32 vlnctrl;
3441 int i, j;
3442
3443 switch (hw->mac.type) {
3444 case ixgbe_mac_82598EB:
3445 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3446 vlnctrl |= IXGBE_VLNCTRL_VME;
3447 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3448 break;
3449 case ixgbe_mac_82599EB:
3450 case ixgbe_mac_X540:
3451 for (i = 0; i < adapter->num_rx_queues; i++) {
3452 j = adapter->rx_ring[i]->reg_idx;
3453 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3454 vlnctrl |= IXGBE_RXDCTL_VME;
3455 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3456 }
3457 break;
3458 default:
3459 break;
3460 }
3461 }
3462
3463 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3464 {
3465 u16 vid;
3466
3467 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3468
3469 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3470 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3471 }
3472
3473 /**
3474 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3475 * @netdev: network interface device structure
3476 *
3477 * Writes unicast address list to the RAR table.
3478 * Returns: -ENOMEM on failure/insufficient address space
3479 * 0 on no addresses written
3480 * X on writing X addresses to the RAR table
3481 **/
3482 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3483 {
3484 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3485 struct ixgbe_hw *hw = &adapter->hw;
3486 unsigned int vfn = adapter->num_vfs;
3487 unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3488 int count = 0;
3489
3490 /* return ENOMEM indicating insufficient memory for addresses */
3491 if (netdev_uc_count(netdev) > rar_entries)
3492 return -ENOMEM;
3493
3494 if (!netdev_uc_empty(netdev) && rar_entries) {
3495 struct netdev_hw_addr *ha;
3496 /* return error if we do not support writing to RAR table */
3497 if (!hw->mac.ops.set_rar)
3498 return -ENOMEM;
3499
3500 netdev_for_each_uc_addr(ha, netdev) {
3501 if (!rar_entries)
3502 break;
3503 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3504 vfn, IXGBE_RAH_AV);
3505 count++;
3506 }
3507 }
3508 /* write the addresses in reverse order to avoid write combining */
3509 for (; rar_entries > 0 ; rar_entries--)
3510 hw->mac.ops.clear_rar(hw, rar_entries);
3511
3512 return count;
3513 }
3514
3515 /**
3516 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3517 * @netdev: network interface device structure
3518 *
3519 * The set_rx_method entry point is called whenever the unicast/multicast
3520 * address list or the network interface flags are updated. This routine is
3521 * responsible for configuring the hardware for proper unicast, multicast and
3522 * promiscuous mode.
3523 **/
3524 void ixgbe_set_rx_mode(struct net_device *netdev)
3525 {
3526 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3527 struct ixgbe_hw *hw = &adapter->hw;
3528 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3529 int count;
3530
3531 /* Check for Promiscuous and All Multicast modes */
3532
3533 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3534
3535 /* set all bits that we expect to always be set */
3536 fctrl |= IXGBE_FCTRL_BAM;
3537 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3538 fctrl |= IXGBE_FCTRL_PMCF;
3539
3540 /* clear the bits we are changing the status of */
3541 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3542
3543 if (netdev->flags & IFF_PROMISC) {
3544 hw->addr_ctrl.user_set_promisc = true;
3545 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3546 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3547 /* don't hardware filter vlans in promisc mode */
3548 ixgbe_vlan_filter_disable(adapter);
3549 } else {
3550 if (netdev->flags & IFF_ALLMULTI) {
3551 fctrl |= IXGBE_FCTRL_MPE;
3552 vmolr |= IXGBE_VMOLR_MPE;
3553 } else {
3554 /*
3555 * Write addresses to the MTA, if the attempt fails
3556 * then we should just turn on promiscous mode so
3557 * that we can at least receive multicast traffic
3558 */
3559 hw->mac.ops.update_mc_addr_list(hw, netdev);
3560 vmolr |= IXGBE_VMOLR_ROMPE;
3561 }
3562 ixgbe_vlan_filter_enable(adapter);
3563 hw->addr_ctrl.user_set_promisc = false;
3564 /*
3565 * Write addresses to available RAR registers, if there is not
3566 * sufficient space to store all the addresses then enable
3567 * unicast promiscous mode
3568 */
3569 count = ixgbe_write_uc_addr_list(netdev);
3570 if (count < 0) {
3571 fctrl |= IXGBE_FCTRL_UPE;
3572 vmolr |= IXGBE_VMOLR_ROPE;
3573 }
3574 }
3575
3576 if (adapter->num_vfs) {
3577 ixgbe_restore_vf_multicasts(adapter);
3578 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3579 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3580 IXGBE_VMOLR_ROPE);
3581 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3582 }
3583
3584 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3585
3586 if (netdev->features & NETIF_F_HW_VLAN_RX)
3587 ixgbe_vlan_strip_enable(adapter);
3588 else
3589 ixgbe_vlan_strip_disable(adapter);
3590 }
3591
3592 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3593 {
3594 int q_idx;
3595 struct ixgbe_q_vector *q_vector;
3596 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3597
3598 /* legacy and MSI only use one vector */
3599 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3600 q_vectors = 1;
3601
3602 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3603 struct napi_struct *napi;
3604 q_vector = adapter->q_vector[q_idx];
3605 napi = &q_vector->napi;
3606 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3607 if (!q_vector->rxr_count || !q_vector->txr_count) {
3608 if (q_vector->txr_count == 1)
3609 napi->poll = &ixgbe_clean_txonly;
3610 else if (q_vector->rxr_count == 1)
3611 napi->poll = &ixgbe_clean_rxonly;
3612 }
3613 }
3614
3615 napi_enable(napi);
3616 }
3617 }
3618
3619 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3620 {
3621 int q_idx;
3622 struct ixgbe_q_vector *q_vector;
3623 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3624
3625 /* legacy and MSI only use one vector */
3626 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3627 q_vectors = 1;
3628
3629 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3630 q_vector = adapter->q_vector[q_idx];
3631 napi_disable(&q_vector->napi);
3632 }
3633 }
3634
3635 #ifdef CONFIG_IXGBE_DCB
3636 /*
3637 * ixgbe_configure_dcb - Configure DCB hardware
3638 * @adapter: ixgbe adapter struct
3639 *
3640 * This is called by the driver on open to configure the DCB hardware.
3641 * This is also called by the gennetlink interface when reconfiguring
3642 * the DCB state.
3643 */
3644 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3645 {
3646 struct ixgbe_hw *hw = &adapter->hw;
3647 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3648
3649 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3650 if (hw->mac.type == ixgbe_mac_82598EB)
3651 netif_set_gso_max_size(adapter->netdev, 65536);
3652 return;
3653 }
3654
3655 if (hw->mac.type == ixgbe_mac_82598EB)
3656 netif_set_gso_max_size(adapter->netdev, 32768);
3657
3658 #ifdef CONFIG_FCOE
3659 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3660 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3661 #endif
3662
3663 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3664 DCB_TX_CONFIG);
3665 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3666 DCB_RX_CONFIG);
3667
3668 /* Enable VLAN tag insert/strip */
3669 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3670
3671 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3672
3673 /* reconfigure the hardware */
3674 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3675 }
3676
3677 #endif
3678 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3679 {
3680 struct net_device *netdev = adapter->netdev;
3681 struct ixgbe_hw *hw = &adapter->hw;
3682 int i;
3683
3684 #ifdef CONFIG_IXGBE_DCB
3685 ixgbe_configure_dcb(adapter);
3686 #endif
3687
3688 ixgbe_set_rx_mode(netdev);
3689 ixgbe_restore_vlan(adapter);
3690
3691 #ifdef IXGBE_FCOE
3692 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3693 ixgbe_configure_fcoe(adapter);
3694
3695 #endif /* IXGBE_FCOE */
3696 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3697 for (i = 0; i < adapter->num_tx_queues; i++)
3698 adapter->tx_ring[i]->atr_sample_rate =
3699 adapter->atr_sample_rate;
3700 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3701 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3702 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3703 }
3704 ixgbe_configure_virtualization(adapter);
3705
3706 ixgbe_configure_tx(adapter);
3707 ixgbe_configure_rx(adapter);
3708 }
3709
3710 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3711 {
3712 switch (hw->phy.type) {
3713 case ixgbe_phy_sfp_avago:
3714 case ixgbe_phy_sfp_ftl:
3715 case ixgbe_phy_sfp_intel:
3716 case ixgbe_phy_sfp_unknown:
3717 case ixgbe_phy_sfp_passive_tyco:
3718 case ixgbe_phy_sfp_passive_unknown:
3719 case ixgbe_phy_sfp_active_unknown:
3720 case ixgbe_phy_sfp_ftl_active:
3721 return true;
3722 default:
3723 return false;
3724 }
3725 }
3726
3727 /**
3728 * ixgbe_sfp_link_config - set up SFP+ link
3729 * @adapter: pointer to private adapter struct
3730 **/
3731 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3732 {
3733 struct ixgbe_hw *hw = &adapter->hw;
3734
3735 if (hw->phy.multispeed_fiber) {
3736 /*
3737 * In multispeed fiber setups, the device may not have
3738 * had a physical connection when the driver loaded.
3739 * If that's the case, the initial link configuration
3740 * couldn't get the MAC into 10G or 1G mode, so we'll
3741 * never have a link status change interrupt fire.
3742 * We need to try and force an autonegotiation
3743 * session, then bring up link.
3744 */
3745 if (hw->mac.ops.setup_sfp)
3746 hw->mac.ops.setup_sfp(hw);
3747 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3748 schedule_work(&adapter->multispeed_fiber_task);
3749 } else {
3750 /*
3751 * Direct Attach Cu and non-multispeed fiber modules
3752 * still need to be configured properly prior to
3753 * attempting link.
3754 */
3755 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3756 schedule_work(&adapter->sfp_config_module_task);
3757 }
3758 }
3759
3760 /**
3761 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3762 * @hw: pointer to private hardware struct
3763 *
3764 * Returns 0 on success, negative on failure
3765 **/
3766 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3767 {
3768 u32 autoneg;
3769 bool negotiation, link_up = false;
3770 u32 ret = IXGBE_ERR_LINK_SETUP;
3771
3772 if (hw->mac.ops.check_link)
3773 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3774
3775 if (ret)
3776 goto link_cfg_out;
3777
3778 if (hw->mac.ops.get_link_capabilities)
3779 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3780 &negotiation);
3781 if (ret)
3782 goto link_cfg_out;
3783
3784 if (hw->mac.ops.setup_link)
3785 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3786 link_cfg_out:
3787 return ret;
3788 }
3789
3790 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3791 {
3792 struct ixgbe_hw *hw = &adapter->hw;
3793 u32 gpie = 0;
3794
3795 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3796 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3797 IXGBE_GPIE_OCD;
3798 gpie |= IXGBE_GPIE_EIAME;
3799 /*
3800 * use EIAM to auto-mask when MSI-X interrupt is asserted
3801 * this saves a register write for every interrupt
3802 */
3803 switch (hw->mac.type) {
3804 case ixgbe_mac_82598EB:
3805 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3806 break;
3807 case ixgbe_mac_82599EB:
3808 case ixgbe_mac_X540:
3809 default:
3810 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3811 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3812 break;
3813 }
3814 } else {
3815 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3816 * specifically only auto mask tx and rx interrupts */
3817 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3818 }
3819
3820 /* XXX: to interrupt immediately for EICS writes, enable this */
3821 /* gpie |= IXGBE_GPIE_EIMEN; */
3822
3823 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3824 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3825 gpie |= IXGBE_GPIE_VTMODE_64;
3826 }
3827
3828 /* Enable fan failure interrupt */
3829 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3830 gpie |= IXGBE_SDP1_GPIEN;
3831
3832 if (hw->mac.type == ixgbe_mac_82599EB)
3833 gpie |= IXGBE_SDP1_GPIEN;
3834 gpie |= IXGBE_SDP2_GPIEN;
3835
3836 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3837 }
3838
3839 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3840 {
3841 struct ixgbe_hw *hw = &adapter->hw;
3842 int err;
3843 u32 ctrl_ext;
3844
3845 ixgbe_get_hw_control(adapter);
3846 ixgbe_setup_gpie(adapter);
3847
3848 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3849 ixgbe_configure_msix(adapter);
3850 else
3851 ixgbe_configure_msi_and_legacy(adapter);
3852
3853 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3854 if (hw->mac.ops.enable_tx_laser &&
3855 ((hw->phy.multispeed_fiber) ||
3856 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3857 (hw->mac.type == ixgbe_mac_82599EB))))
3858 hw->mac.ops.enable_tx_laser(hw);
3859
3860 clear_bit(__IXGBE_DOWN, &adapter->state);
3861 ixgbe_napi_enable_all(adapter);
3862
3863 if (ixgbe_is_sfp(hw)) {
3864 ixgbe_sfp_link_config(adapter);
3865 } else {
3866 err = ixgbe_non_sfp_link_config(hw);
3867 if (err)
3868 e_err(probe, "link_config FAILED %d\n", err);
3869 }
3870
3871 /* clear any pending interrupts, may auto mask */
3872 IXGBE_READ_REG(hw, IXGBE_EICR);
3873 ixgbe_irq_enable(adapter, true, true);
3874
3875 /*
3876 * If this adapter has a fan, check to see if we had a failure
3877 * before we enabled the interrupt.
3878 */
3879 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3880 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3881 if (esdp & IXGBE_ESDP_SDP1)
3882 e_crit(drv, "Fan has stopped, replace the adapter\n");
3883 }
3884
3885 /*
3886 * For hot-pluggable SFP+ devices, a new SFP+ module may have
3887 * arrived before interrupts were enabled but after probe. Such
3888 * devices wouldn't have their type identified yet. We need to
3889 * kick off the SFP+ module setup first, then try to bring up link.
3890 * If we're not hot-pluggable SFP+, we just need to configure link
3891 * and bring it up.
3892 */
3893 if (hw->phy.type == ixgbe_phy_none)
3894 schedule_work(&adapter->sfp_config_module_task);
3895
3896 /* enable transmits */
3897 netif_tx_start_all_queues(adapter->netdev);
3898
3899 /* bring the link up in the watchdog, this could race with our first
3900 * link up interrupt but shouldn't be a problem */
3901 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3902 adapter->link_check_timeout = jiffies;
3903 mod_timer(&adapter->watchdog_timer, jiffies);
3904
3905 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3906 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3907 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3908 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3909
3910 return 0;
3911 }
3912
3913 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3914 {
3915 WARN_ON(in_interrupt());
3916 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3917 msleep(1);
3918 ixgbe_down(adapter);
3919 /*
3920 * If SR-IOV enabled then wait a bit before bringing the adapter
3921 * back up to give the VFs time to respond to the reset. The
3922 * two second wait is based upon the watchdog timer cycle in
3923 * the VF driver.
3924 */
3925 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3926 msleep(2000);
3927 ixgbe_up(adapter);
3928 clear_bit(__IXGBE_RESETTING, &adapter->state);
3929 }
3930
3931 int ixgbe_up(struct ixgbe_adapter *adapter)
3932 {
3933 /* hardware has been reset, we need to reload some things */
3934 ixgbe_configure(adapter);
3935
3936 return ixgbe_up_complete(adapter);
3937 }
3938
3939 void ixgbe_reset(struct ixgbe_adapter *adapter)
3940 {
3941 struct ixgbe_hw *hw = &adapter->hw;
3942 int err;
3943
3944 err = hw->mac.ops.init_hw(hw);
3945 switch (err) {
3946 case 0:
3947 case IXGBE_ERR_SFP_NOT_PRESENT:
3948 break;
3949 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3950 e_dev_err("master disable timed out\n");
3951 break;
3952 case IXGBE_ERR_EEPROM_VERSION:
3953 /* We are running on a pre-production device, log a warning */
3954 e_dev_warn("This device is a pre-production adapter/LOM. "
3955 "Please be aware there may be issuesassociated with "
3956 "your hardware. If you are experiencing problems "
3957 "please contact your Intel or hardware "
3958 "representative who provided you with this "
3959 "hardware.\n");
3960 break;
3961 default:
3962 e_dev_err("Hardware Error: %d\n", err);
3963 }
3964
3965 /* reprogram the RAR[0] in case user changed it. */
3966 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3967 IXGBE_RAH_AV);
3968 }
3969
3970 /**
3971 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3972 * @rx_ring: ring to free buffers from
3973 **/
3974 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3975 {
3976 struct device *dev = rx_ring->dev;
3977 unsigned long size;
3978 u16 i;
3979
3980 /* ring already cleared, nothing to do */
3981 if (!rx_ring->rx_buffer_info)
3982 return;
3983
3984 /* Free all the Rx ring sk_buffs */
3985 for (i = 0; i < rx_ring->count; i++) {
3986 struct ixgbe_rx_buffer *rx_buffer_info;
3987
3988 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3989 if (rx_buffer_info->dma) {
3990 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3991 rx_ring->rx_buf_len,
3992 DMA_FROM_DEVICE);
3993 rx_buffer_info->dma = 0;
3994 }
3995 if (rx_buffer_info->skb) {
3996 struct sk_buff *skb = rx_buffer_info->skb;
3997 rx_buffer_info->skb = NULL;
3998 do {
3999 struct sk_buff *this = skb;
4000 if (IXGBE_RSC_CB(this)->delay_unmap) {
4001 dma_unmap_single(dev,
4002 IXGBE_RSC_CB(this)->dma,
4003 rx_ring->rx_buf_len,
4004 DMA_FROM_DEVICE);
4005 IXGBE_RSC_CB(this)->dma = 0;
4006 IXGBE_RSC_CB(skb)->delay_unmap = false;
4007 }
4008 skb = skb->prev;
4009 dev_kfree_skb(this);
4010 } while (skb);
4011 }
4012 if (!rx_buffer_info->page)
4013 continue;
4014 if (rx_buffer_info->page_dma) {
4015 dma_unmap_page(dev, rx_buffer_info->page_dma,
4016 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4017 rx_buffer_info->page_dma = 0;
4018 }
4019 put_page(rx_buffer_info->page);
4020 rx_buffer_info->page = NULL;
4021 rx_buffer_info->page_offset = 0;
4022 }
4023
4024 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4025 memset(rx_ring->rx_buffer_info, 0, size);
4026
4027 /* Zero out the descriptor ring */
4028 memset(rx_ring->desc, 0, rx_ring->size);
4029
4030 rx_ring->next_to_clean = 0;
4031 rx_ring->next_to_use = 0;
4032 }
4033
4034 /**
4035 * ixgbe_clean_tx_ring - Free Tx Buffers
4036 * @tx_ring: ring to be cleaned
4037 **/
4038 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4039 {
4040 struct ixgbe_tx_buffer *tx_buffer_info;
4041 unsigned long size;
4042 u16 i;
4043
4044 /* ring already cleared, nothing to do */
4045 if (!tx_ring->tx_buffer_info)
4046 return;
4047
4048 /* Free all the Tx ring sk_buffs */
4049 for (i = 0; i < tx_ring->count; i++) {
4050 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4051 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4052 }
4053
4054 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4055 memset(tx_ring->tx_buffer_info, 0, size);
4056
4057 /* Zero out the descriptor ring */
4058 memset(tx_ring->desc, 0, tx_ring->size);
4059
4060 tx_ring->next_to_use = 0;
4061 tx_ring->next_to_clean = 0;
4062 }
4063
4064 /**
4065 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4066 * @adapter: board private structure
4067 **/
4068 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4069 {
4070 int i;
4071
4072 for (i = 0; i < adapter->num_rx_queues; i++)
4073 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4074 }
4075
4076 /**
4077 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4078 * @adapter: board private structure
4079 **/
4080 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4081 {
4082 int i;
4083
4084 for (i = 0; i < adapter->num_tx_queues; i++)
4085 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4086 }
4087
4088 void ixgbe_down(struct ixgbe_adapter *adapter)
4089 {
4090 struct net_device *netdev = adapter->netdev;
4091 struct ixgbe_hw *hw = &adapter->hw;
4092 u32 rxctrl;
4093 u32 txdctl;
4094 int i;
4095 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4096
4097 /* signal that we are down to the interrupt handler */
4098 set_bit(__IXGBE_DOWN, &adapter->state);
4099
4100 /* disable receive for all VFs and wait one second */
4101 if (adapter->num_vfs) {
4102 /* ping all the active vfs to let them know we are going down */
4103 ixgbe_ping_all_vfs(adapter);
4104
4105 /* Disable all VFTE/VFRE TX/RX */
4106 ixgbe_disable_tx_rx(adapter);
4107
4108 /* Mark all the VFs as inactive */
4109 for (i = 0 ; i < adapter->num_vfs; i++)
4110 adapter->vfinfo[i].clear_to_send = 0;
4111 }
4112
4113 /* disable receives */
4114 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4115 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4116
4117 /* disable all enabled rx queues */
4118 for (i = 0; i < adapter->num_rx_queues; i++)
4119 /* this call also flushes the previous write */
4120 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4121
4122 msleep(10);
4123
4124 netif_tx_stop_all_queues(netdev);
4125
4126 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4127 del_timer_sync(&adapter->sfp_timer);
4128 del_timer_sync(&adapter->watchdog_timer);
4129 cancel_work_sync(&adapter->watchdog_task);
4130
4131 netif_carrier_off(netdev);
4132 netif_tx_disable(netdev);
4133
4134 ixgbe_irq_disable(adapter);
4135
4136 ixgbe_napi_disable_all(adapter);
4137
4138 /* Cleanup the affinity_hint CPU mask memory and callback */
4139 for (i = 0; i < num_q_vectors; i++) {
4140 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4141 /* clear the affinity_mask in the IRQ descriptor */
4142 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4143 /* release the CPU mask memory */
4144 free_cpumask_var(q_vector->affinity_mask);
4145 }
4146
4147 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4148 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4149 cancel_work_sync(&adapter->fdir_reinit_task);
4150
4151 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4152 cancel_work_sync(&adapter->check_overtemp_task);
4153
4154 /* disable transmits in the hardware now that interrupts are off */
4155 for (i = 0; i < adapter->num_tx_queues; i++) {
4156 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4157 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
4158 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
4159 (txdctl & ~IXGBE_TXDCTL_ENABLE));
4160 }
4161 /* Disable the Tx DMA engine on 82599 */
4162 switch (hw->mac.type) {
4163 case ixgbe_mac_82599EB:
4164 case ixgbe_mac_X540:
4165 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4166 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4167 ~IXGBE_DMATXCTL_TE));
4168 break;
4169 default:
4170 break;
4171 }
4172
4173 /* clear n-tuple filters that are cached */
4174 ethtool_ntuple_flush(netdev);
4175
4176 if (!pci_channel_offline(adapter->pdev))
4177 ixgbe_reset(adapter);
4178
4179 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4180 if (hw->mac.ops.disable_tx_laser &&
4181 ((hw->phy.multispeed_fiber) ||
4182 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4183 (hw->mac.type == ixgbe_mac_82599EB))))
4184 hw->mac.ops.disable_tx_laser(hw);
4185
4186 ixgbe_clean_all_tx_rings(adapter);
4187 ixgbe_clean_all_rx_rings(adapter);
4188
4189 #ifdef CONFIG_IXGBE_DCA
4190 /* since we reset the hardware DCA settings were cleared */
4191 ixgbe_setup_dca(adapter);
4192 #endif
4193 }
4194
4195 /**
4196 * ixgbe_poll - NAPI Rx polling callback
4197 * @napi: structure for representing this polling device
4198 * @budget: how many packets driver is allowed to clean
4199 *
4200 * This function is used for legacy and MSI, NAPI mode
4201 **/
4202 static int ixgbe_poll(struct napi_struct *napi, int budget)
4203 {
4204 struct ixgbe_q_vector *q_vector =
4205 container_of(napi, struct ixgbe_q_vector, napi);
4206 struct ixgbe_adapter *adapter = q_vector->adapter;
4207 int tx_clean_complete, work_done = 0;
4208
4209 #ifdef CONFIG_IXGBE_DCA
4210 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4211 ixgbe_update_dca(q_vector);
4212 #endif
4213
4214 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4215 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
4216
4217 if (!tx_clean_complete)
4218 work_done = budget;
4219
4220 /* If budget not fully consumed, exit the polling mode */
4221 if (work_done < budget) {
4222 napi_complete(napi);
4223 if (adapter->rx_itr_setting & 1)
4224 ixgbe_set_itr(adapter);
4225 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4226 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
4227 }
4228 return work_done;
4229 }
4230
4231 /**
4232 * ixgbe_tx_timeout - Respond to a Tx Hang
4233 * @netdev: network interface device structure
4234 **/
4235 static void ixgbe_tx_timeout(struct net_device *netdev)
4236 {
4237 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4238
4239 adapter->tx_timeout_count++;
4240
4241 /* Do the reset outside of interrupt context */
4242 schedule_work(&adapter->reset_task);
4243 }
4244
4245 static void ixgbe_reset_task(struct work_struct *work)
4246 {
4247 struct ixgbe_adapter *adapter;
4248 adapter = container_of(work, struct ixgbe_adapter, reset_task);
4249
4250 /* If we're already down or resetting, just bail */
4251 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
4252 test_bit(__IXGBE_RESETTING, &adapter->state))
4253 return;
4254
4255 ixgbe_dump(adapter);
4256 netdev_err(adapter->netdev, "Reset adapter\n");
4257 ixgbe_reinit_locked(adapter);
4258 }
4259
4260 #ifdef CONFIG_IXGBE_DCB
4261 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4262 {
4263 bool ret = false;
4264 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
4265
4266 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4267 return ret;
4268
4269 f->mask = 0x7 << 3;
4270 adapter->num_rx_queues = f->indices;
4271 adapter->num_tx_queues = f->indices;
4272 ret = true;
4273
4274 return ret;
4275 }
4276 #endif
4277
4278 /**
4279 * ixgbe_set_rss_queues: Allocate queues for RSS
4280 * @adapter: board private structure to initialize
4281 *
4282 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4283 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4284 *
4285 **/
4286 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4287 {
4288 bool ret = false;
4289 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4290
4291 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4292 f->mask = 0xF;
4293 adapter->num_rx_queues = f->indices;
4294 adapter->num_tx_queues = f->indices;
4295 ret = true;
4296 } else {
4297 ret = false;
4298 }
4299
4300 return ret;
4301 }
4302
4303 /**
4304 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4305 * @adapter: board private structure to initialize
4306 *
4307 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4308 * to the original CPU that initiated the Tx session. This runs in addition
4309 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4310 * Rx load across CPUs using RSS.
4311 *
4312 **/
4313 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4314 {
4315 bool ret = false;
4316 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4317
4318 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4319 f_fdir->mask = 0;
4320
4321 /* Flow Director must have RSS enabled */
4322 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4323 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4324 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4325 adapter->num_tx_queues = f_fdir->indices;
4326 adapter->num_rx_queues = f_fdir->indices;
4327 ret = true;
4328 } else {
4329 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4330 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4331 }
4332 return ret;
4333 }
4334
4335 #ifdef IXGBE_FCOE
4336 /**
4337 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4338 * @adapter: board private structure to initialize
4339 *
4340 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4341 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4342 * rx queues out of the max number of rx queues, instead, it is used as the
4343 * index of the first rx queue used by FCoE.
4344 *
4345 **/
4346 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4347 {
4348 bool ret = false;
4349 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4350
4351 f->indices = min((int)num_online_cpus(), f->indices);
4352 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4353 adapter->num_rx_queues = 1;
4354 adapter->num_tx_queues = 1;
4355 #ifdef CONFIG_IXGBE_DCB
4356 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4357 e_info(probe, "FCoE enabled with DCB\n");
4358 ixgbe_set_dcb_queues(adapter);
4359 }
4360 #endif
4361 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4362 e_info(probe, "FCoE enabled with RSS\n");
4363 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4364 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4365 ixgbe_set_fdir_queues(adapter);
4366 else
4367 ixgbe_set_rss_queues(adapter);
4368 }
4369 /* adding FCoE rx rings to the end */
4370 f->mask = adapter->num_rx_queues;
4371 adapter->num_rx_queues += f->indices;
4372 adapter->num_tx_queues += f->indices;
4373
4374 ret = true;
4375 }
4376
4377 return ret;
4378 }
4379
4380 #endif /* IXGBE_FCOE */
4381 /**
4382 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4383 * @adapter: board private structure to initialize
4384 *
4385 * IOV doesn't actually use anything, so just NAK the
4386 * request for now and let the other queue routines
4387 * figure out what to do.
4388 */
4389 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4390 {
4391 return false;
4392 }
4393
4394 /*
4395 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4396 * @adapter: board private structure to initialize
4397 *
4398 * This is the top level queue allocation routine. The order here is very
4399 * important, starting with the "most" number of features turned on at once,
4400 * and ending with the smallest set of features. This way large combinations
4401 * can be allocated if they're turned on, and smaller combinations are the
4402 * fallthrough conditions.
4403 *
4404 **/
4405 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4406 {
4407 /* Start with base case */
4408 adapter->num_rx_queues = 1;
4409 adapter->num_tx_queues = 1;
4410 adapter->num_rx_pools = adapter->num_rx_queues;
4411 adapter->num_rx_queues_per_pool = 1;
4412
4413 if (ixgbe_set_sriov_queues(adapter))
4414 goto done;
4415
4416 #ifdef IXGBE_FCOE
4417 if (ixgbe_set_fcoe_queues(adapter))
4418 goto done;
4419
4420 #endif /* IXGBE_FCOE */
4421 #ifdef CONFIG_IXGBE_DCB
4422 if (ixgbe_set_dcb_queues(adapter))
4423 goto done;
4424
4425 #endif
4426 if (ixgbe_set_fdir_queues(adapter))
4427 goto done;
4428
4429 if (ixgbe_set_rss_queues(adapter))
4430 goto done;
4431
4432 /* fallback to base case */
4433 adapter->num_rx_queues = 1;
4434 adapter->num_tx_queues = 1;
4435
4436 done:
4437 /* Notify the stack of the (possibly) reduced queue counts. */
4438 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4439 return netif_set_real_num_rx_queues(adapter->netdev,
4440 adapter->num_rx_queues);
4441 }
4442
4443 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4444 int vectors)
4445 {
4446 int err, vector_threshold;
4447
4448 /* We'll want at least 3 (vector_threshold):
4449 * 1) TxQ[0] Cleanup
4450 * 2) RxQ[0] Cleanup
4451 * 3) Other (Link Status Change, etc.)
4452 * 4) TCP Timer (optional)
4453 */
4454 vector_threshold = MIN_MSIX_COUNT;
4455
4456 /* The more we get, the more we will assign to Tx/Rx Cleanup
4457 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4458 * Right now, we simply care about how many we'll get; we'll
4459 * set them up later while requesting irq's.
4460 */
4461 while (vectors >= vector_threshold) {
4462 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4463 vectors);
4464 if (!err) /* Success in acquiring all requested vectors. */
4465 break;
4466 else if (err < 0)
4467 vectors = 0; /* Nasty failure, quit now */
4468 else /* err == number of vectors we should try again with */
4469 vectors = err;
4470 }
4471
4472 if (vectors < vector_threshold) {
4473 /* Can't allocate enough MSI-X interrupts? Oh well.
4474 * This just means we'll go with either a single MSI
4475 * vector or fall back to legacy interrupts.
4476 */
4477 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4478 "Unable to allocate MSI-X interrupts\n");
4479 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4480 kfree(adapter->msix_entries);
4481 adapter->msix_entries = NULL;
4482 } else {
4483 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4484 /*
4485 * Adjust for only the vectors we'll use, which is minimum
4486 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4487 * vectors we were allocated.
4488 */
4489 adapter->num_msix_vectors = min(vectors,
4490 adapter->max_msix_q_vectors + NON_Q_VECTORS);
4491 }
4492 }
4493
4494 /**
4495 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4496 * @adapter: board private structure to initialize
4497 *
4498 * Cache the descriptor ring offsets for RSS to the assigned rings.
4499 *
4500 **/
4501 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4502 {
4503 int i;
4504
4505 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4506 return false;
4507
4508 for (i = 0; i < adapter->num_rx_queues; i++)
4509 adapter->rx_ring[i]->reg_idx = i;
4510 for (i = 0; i < adapter->num_tx_queues; i++)
4511 adapter->tx_ring[i]->reg_idx = i;
4512
4513 return true;
4514 }
4515
4516 #ifdef CONFIG_IXGBE_DCB
4517 /**
4518 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4519 * @adapter: board private structure to initialize
4520 *
4521 * Cache the descriptor ring offsets for DCB to the assigned rings.
4522 *
4523 **/
4524 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4525 {
4526 int i;
4527 bool ret = false;
4528 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4529
4530 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4531 return false;
4532
4533 /* the number of queues is assumed to be symmetric */
4534 switch (adapter->hw.mac.type) {
4535 case ixgbe_mac_82598EB:
4536 for (i = 0; i < dcb_i; i++) {
4537 adapter->rx_ring[i]->reg_idx = i << 3;
4538 adapter->tx_ring[i]->reg_idx = i << 2;
4539 }
4540 ret = true;
4541 break;
4542 case ixgbe_mac_82599EB:
4543 case ixgbe_mac_X540:
4544 if (dcb_i == 8) {
4545 /*
4546 * Tx TC0 starts at: descriptor queue 0
4547 * Tx TC1 starts at: descriptor queue 32
4548 * Tx TC2 starts at: descriptor queue 64
4549 * Tx TC3 starts at: descriptor queue 80
4550 * Tx TC4 starts at: descriptor queue 96
4551 * Tx TC5 starts at: descriptor queue 104
4552 * Tx TC6 starts at: descriptor queue 112
4553 * Tx TC7 starts at: descriptor queue 120
4554 *
4555 * Rx TC0-TC7 are offset by 16 queues each
4556 */
4557 for (i = 0; i < 3; i++) {
4558 adapter->tx_ring[i]->reg_idx = i << 5;
4559 adapter->rx_ring[i]->reg_idx = i << 4;
4560 }
4561 for ( ; i < 5; i++) {
4562 adapter->tx_ring[i]->reg_idx = ((i + 2) << 4);
4563 adapter->rx_ring[i]->reg_idx = i << 4;
4564 }
4565 for ( ; i < dcb_i; i++) {
4566 adapter->tx_ring[i]->reg_idx = ((i + 8) << 3);
4567 adapter->rx_ring[i]->reg_idx = i << 4;
4568 }
4569 ret = true;
4570 } else if (dcb_i == 4) {
4571 /*
4572 * Tx TC0 starts at: descriptor queue 0
4573 * Tx TC1 starts at: descriptor queue 64
4574 * Tx TC2 starts at: descriptor queue 96
4575 * Tx TC3 starts at: descriptor queue 112
4576 *
4577 * Rx TC0-TC3 are offset by 32 queues each
4578 */
4579 adapter->tx_ring[0]->reg_idx = 0;
4580 adapter->tx_ring[1]->reg_idx = 64;
4581 adapter->tx_ring[2]->reg_idx = 96;
4582 adapter->tx_ring[3]->reg_idx = 112;
4583 for (i = 0 ; i < dcb_i; i++)
4584 adapter->rx_ring[i]->reg_idx = i << 5;
4585 ret = true;
4586 }
4587 break;
4588 default:
4589 break;
4590 }
4591 return ret;
4592 }
4593 #endif
4594
4595 /**
4596 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4597 * @adapter: board private structure to initialize
4598 *
4599 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4600 *
4601 **/
4602 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4603 {
4604 int i;
4605 bool ret = false;
4606
4607 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4608 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4609 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4610 for (i = 0; i < adapter->num_rx_queues; i++)
4611 adapter->rx_ring[i]->reg_idx = i;
4612 for (i = 0; i < adapter->num_tx_queues; i++)
4613 adapter->tx_ring[i]->reg_idx = i;
4614 ret = true;
4615 }
4616
4617 return ret;
4618 }
4619
4620 #ifdef IXGBE_FCOE
4621 /**
4622 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4623 * @adapter: board private structure to initialize
4624 *
4625 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4626 *
4627 */
4628 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4629 {
4630 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4631 int i;
4632 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4633
4634 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4635 return false;
4636
4637 #ifdef CONFIG_IXGBE_DCB
4638 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4639 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4640
4641 ixgbe_cache_ring_dcb(adapter);
4642 /* find out queues in TC for FCoE */
4643 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4644 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4645 /*
4646 * In 82599, the number of Tx queues for each traffic
4647 * class for both 8-TC and 4-TC modes are:
4648 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4649 * 8 TCs: 32 32 16 16 8 8 8 8
4650 * 4 TCs: 64 64 32 32
4651 * We have max 8 queues for FCoE, where 8 the is
4652 * FCoE redirection table size. If TC for FCoE is
4653 * less than or equal to TC3, we have enough queues
4654 * to add max of 8 queues for FCoE, so we start FCoE
4655 * Tx queue from the next one, i.e., reg_idx + 1.
4656 * If TC for FCoE is above TC3, implying 8 TC mode,
4657 * and we need 8 for FCoE, we have to take all queues
4658 * in that traffic class for FCoE.
4659 */
4660 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4661 fcoe_tx_i--;
4662 }
4663 #endif /* CONFIG_IXGBE_DCB */
4664 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4665 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4666 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4667 ixgbe_cache_ring_fdir(adapter);
4668 else
4669 ixgbe_cache_ring_rss(adapter);
4670
4671 fcoe_rx_i = f->mask;
4672 fcoe_tx_i = f->mask;
4673 }
4674 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4675 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4676 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4677 }
4678 return true;
4679 }
4680
4681 #endif /* IXGBE_FCOE */
4682 /**
4683 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4684 * @adapter: board private structure to initialize
4685 *
4686 * SR-IOV doesn't use any descriptor rings but changes the default if
4687 * no other mapping is used.
4688 *
4689 */
4690 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4691 {
4692 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4693 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4694 if (adapter->num_vfs)
4695 return true;
4696 else
4697 return false;
4698 }
4699
4700 /**
4701 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4702 * @adapter: board private structure to initialize
4703 *
4704 * Once we know the feature-set enabled for the device, we'll cache
4705 * the register offset the descriptor ring is assigned to.
4706 *
4707 * Note, the order the various feature calls is important. It must start with
4708 * the "most" features enabled at the same time, then trickle down to the
4709 * least amount of features turned on at once.
4710 **/
4711 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4712 {
4713 /* start with default case */
4714 adapter->rx_ring[0]->reg_idx = 0;
4715 adapter->tx_ring[0]->reg_idx = 0;
4716
4717 if (ixgbe_cache_ring_sriov(adapter))
4718 return;
4719
4720 #ifdef IXGBE_FCOE
4721 if (ixgbe_cache_ring_fcoe(adapter))
4722 return;
4723
4724 #endif /* IXGBE_FCOE */
4725 #ifdef CONFIG_IXGBE_DCB
4726 if (ixgbe_cache_ring_dcb(adapter))
4727 return;
4728
4729 #endif
4730 if (ixgbe_cache_ring_fdir(adapter))
4731 return;
4732
4733 if (ixgbe_cache_ring_rss(adapter))
4734 return;
4735 }
4736
4737 /**
4738 * ixgbe_alloc_queues - Allocate memory for all rings
4739 * @adapter: board private structure to initialize
4740 *
4741 * We allocate one ring per queue at run-time since we don't know the
4742 * number of queues at compile-time. The polling_netdev array is
4743 * intended for Multiqueue, but should work fine with a single queue.
4744 **/
4745 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4746 {
4747 int rx = 0, tx = 0, nid = adapter->node;
4748
4749 if (nid < 0 || !node_online(nid))
4750 nid = first_online_node;
4751
4752 for (; tx < adapter->num_tx_queues; tx++) {
4753 struct ixgbe_ring *ring;
4754
4755 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4756 if (!ring)
4757 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4758 if (!ring)
4759 goto err_allocation;
4760 ring->count = adapter->tx_ring_count;
4761 ring->queue_index = tx;
4762 ring->numa_node = nid;
4763 ring->dev = &adapter->pdev->dev;
4764 ring->netdev = adapter->netdev;
4765
4766 adapter->tx_ring[tx] = ring;
4767 }
4768
4769 for (; rx < adapter->num_rx_queues; rx++) {
4770 struct ixgbe_ring *ring;
4771
4772 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4773 if (!ring)
4774 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4775 if (!ring)
4776 goto err_allocation;
4777 ring->count = adapter->rx_ring_count;
4778 ring->queue_index = rx;
4779 ring->numa_node = nid;
4780 ring->dev = &adapter->pdev->dev;
4781 ring->netdev = adapter->netdev;
4782
4783 adapter->rx_ring[rx] = ring;
4784 }
4785
4786 ixgbe_cache_ring_register(adapter);
4787
4788 return 0;
4789
4790 err_allocation:
4791 while (tx)
4792 kfree(adapter->tx_ring[--tx]);
4793
4794 while (rx)
4795 kfree(adapter->rx_ring[--rx]);
4796 return -ENOMEM;
4797 }
4798
4799 /**
4800 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4801 * @adapter: board private structure to initialize
4802 *
4803 * Attempt to configure the interrupts using the best available
4804 * capabilities of the hardware and the kernel.
4805 **/
4806 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4807 {
4808 struct ixgbe_hw *hw = &adapter->hw;
4809 int err = 0;
4810 int vector, v_budget;
4811
4812 /*
4813 * It's easy to be greedy for MSI-X vectors, but it really
4814 * doesn't do us much good if we have a lot more vectors
4815 * than CPU's. So let's be conservative and only ask for
4816 * (roughly) the same number of vectors as there are CPU's.
4817 */
4818 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4819 (int)num_online_cpus()) + NON_Q_VECTORS;
4820
4821 /*
4822 * At the same time, hardware can only support a maximum of
4823 * hw.mac->max_msix_vectors vectors. With features
4824 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4825 * descriptor queues supported by our device. Thus, we cap it off in
4826 * those rare cases where the cpu count also exceeds our vector limit.
4827 */
4828 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4829
4830 /* A failure in MSI-X entry allocation isn't fatal, but it does
4831 * mean we disable MSI-X capabilities of the adapter. */
4832 adapter->msix_entries = kcalloc(v_budget,
4833 sizeof(struct msix_entry), GFP_KERNEL);
4834 if (adapter->msix_entries) {
4835 for (vector = 0; vector < v_budget; vector++)
4836 adapter->msix_entries[vector].entry = vector;
4837
4838 ixgbe_acquire_msix_vectors(adapter, v_budget);
4839
4840 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4841 goto out;
4842 }
4843
4844 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4845 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4846 if (adapter->flags & (IXGBE_FLAG_FDIR_HASH_CAPABLE |
4847 IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
4848 e_err(probe,
4849 "Flow Director is not supported while multiple "
4850 "queues are disabled. Disabling Flow Director\n");
4851 }
4852 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4853 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4854 adapter->atr_sample_rate = 0;
4855 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4856 ixgbe_disable_sriov(adapter);
4857
4858 err = ixgbe_set_num_queues(adapter);
4859 if (err)
4860 return err;
4861
4862 err = pci_enable_msi(adapter->pdev);
4863 if (!err) {
4864 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4865 } else {
4866 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4867 "Unable to allocate MSI interrupt, "
4868 "falling back to legacy. Error: %d\n", err);
4869 /* reset err */
4870 err = 0;
4871 }
4872
4873 out:
4874 return err;
4875 }
4876
4877 /**
4878 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4879 * @adapter: board private structure to initialize
4880 *
4881 * We allocate one q_vector per queue interrupt. If allocation fails we
4882 * return -ENOMEM.
4883 **/
4884 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4885 {
4886 int q_idx, num_q_vectors;
4887 struct ixgbe_q_vector *q_vector;
4888 int (*poll)(struct napi_struct *, int);
4889
4890 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4891 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4892 poll = &ixgbe_clean_rxtx_many;
4893 } else {
4894 num_q_vectors = 1;
4895 poll = &ixgbe_poll;
4896 }
4897
4898 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4899 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4900 GFP_KERNEL, adapter->node);
4901 if (!q_vector)
4902 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4903 GFP_KERNEL);
4904 if (!q_vector)
4905 goto err_out;
4906 q_vector->adapter = adapter;
4907 if (q_vector->txr_count && !q_vector->rxr_count)
4908 q_vector->eitr = adapter->tx_eitr_param;
4909 else
4910 q_vector->eitr = adapter->rx_eitr_param;
4911 q_vector->v_idx = q_idx;
4912 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4913 adapter->q_vector[q_idx] = q_vector;
4914 }
4915
4916 return 0;
4917
4918 err_out:
4919 while (q_idx) {
4920 q_idx--;
4921 q_vector = adapter->q_vector[q_idx];
4922 netif_napi_del(&q_vector->napi);
4923 kfree(q_vector);
4924 adapter->q_vector[q_idx] = NULL;
4925 }
4926 return -ENOMEM;
4927 }
4928
4929 /**
4930 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4931 * @adapter: board private structure to initialize
4932 *
4933 * This function frees the memory allocated to the q_vectors. In addition if
4934 * NAPI is enabled it will delete any references to the NAPI struct prior
4935 * to freeing the q_vector.
4936 **/
4937 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4938 {
4939 int q_idx, num_q_vectors;
4940
4941 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4942 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4943 else
4944 num_q_vectors = 1;
4945
4946 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4947 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4948 adapter->q_vector[q_idx] = NULL;
4949 netif_napi_del(&q_vector->napi);
4950 kfree(q_vector);
4951 }
4952 }
4953
4954 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4955 {
4956 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4957 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4958 pci_disable_msix(adapter->pdev);
4959 kfree(adapter->msix_entries);
4960 adapter->msix_entries = NULL;
4961 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4962 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4963 pci_disable_msi(adapter->pdev);
4964 }
4965 }
4966
4967 /**
4968 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4969 * @adapter: board private structure to initialize
4970 *
4971 * We determine which interrupt scheme to use based on...
4972 * - Kernel support (MSI, MSI-X)
4973 * - which can be user-defined (via MODULE_PARAM)
4974 * - Hardware queue count (num_*_queues)
4975 * - defined by miscellaneous hardware support/features (RSS, etc.)
4976 **/
4977 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4978 {
4979 int err;
4980
4981 /* Number of supported queues */
4982 err = ixgbe_set_num_queues(adapter);
4983 if (err)
4984 return err;
4985
4986 err = ixgbe_set_interrupt_capability(adapter);
4987 if (err) {
4988 e_dev_err("Unable to setup interrupt capabilities\n");
4989 goto err_set_interrupt;
4990 }
4991
4992 err = ixgbe_alloc_q_vectors(adapter);
4993 if (err) {
4994 e_dev_err("Unable to allocate memory for queue vectors\n");
4995 goto err_alloc_q_vectors;
4996 }
4997
4998 err = ixgbe_alloc_queues(adapter);
4999 if (err) {
5000 e_dev_err("Unable to allocate memory for queues\n");
5001 goto err_alloc_queues;
5002 }
5003
5004 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
5005 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5006 adapter->num_rx_queues, adapter->num_tx_queues);
5007
5008 set_bit(__IXGBE_DOWN, &adapter->state);
5009
5010 return 0;
5011
5012 err_alloc_queues:
5013 ixgbe_free_q_vectors(adapter);
5014 err_alloc_q_vectors:
5015 ixgbe_reset_interrupt_capability(adapter);
5016 err_set_interrupt:
5017 return err;
5018 }
5019
5020 static void ring_free_rcu(struct rcu_head *head)
5021 {
5022 kfree(container_of(head, struct ixgbe_ring, rcu));
5023 }
5024
5025 /**
5026 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5027 * @adapter: board private structure to clear interrupt scheme on
5028 *
5029 * We go through and clear interrupt specific resources and reset the structure
5030 * to pre-load conditions
5031 **/
5032 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5033 {
5034 int i;
5035
5036 for (i = 0; i < adapter->num_tx_queues; i++) {
5037 kfree(adapter->tx_ring[i]);
5038 adapter->tx_ring[i] = NULL;
5039 }
5040 for (i = 0; i < adapter->num_rx_queues; i++) {
5041 struct ixgbe_ring *ring = adapter->rx_ring[i];
5042
5043 /* ixgbe_get_stats64() might access this ring, we must wait
5044 * a grace period before freeing it.
5045 */
5046 call_rcu(&ring->rcu, ring_free_rcu);
5047 adapter->rx_ring[i] = NULL;
5048 }
5049
5050 adapter->num_tx_queues = 0;
5051 adapter->num_rx_queues = 0;
5052
5053 ixgbe_free_q_vectors(adapter);
5054 ixgbe_reset_interrupt_capability(adapter);
5055 }
5056
5057 /**
5058 * ixgbe_sfp_timer - worker thread to find a missing module
5059 * @data: pointer to our adapter struct
5060 **/
5061 static void ixgbe_sfp_timer(unsigned long data)
5062 {
5063 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5064
5065 /*
5066 * Do the sfp_timer outside of interrupt context due to the
5067 * delays that sfp+ detection requires
5068 */
5069 schedule_work(&adapter->sfp_task);
5070 }
5071
5072 /**
5073 * ixgbe_sfp_task - worker thread to find a missing module
5074 * @work: pointer to work_struct containing our data
5075 **/
5076 static void ixgbe_sfp_task(struct work_struct *work)
5077 {
5078 struct ixgbe_adapter *adapter = container_of(work,
5079 struct ixgbe_adapter,
5080 sfp_task);
5081 struct ixgbe_hw *hw = &adapter->hw;
5082
5083 if ((hw->phy.type == ixgbe_phy_nl) &&
5084 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
5085 s32 ret = hw->phy.ops.identify_sfp(hw);
5086 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
5087 goto reschedule;
5088 ret = hw->phy.ops.reset(hw);
5089 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5090 e_dev_err("failed to initialize because an unsupported "
5091 "SFP+ module type was detected.\n");
5092 e_dev_err("Reload the driver after installing a "
5093 "supported module.\n");
5094 unregister_netdev(adapter->netdev);
5095 } else {
5096 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5097 }
5098 /* don't need this routine any more */
5099 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5100 }
5101 return;
5102 reschedule:
5103 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
5104 mod_timer(&adapter->sfp_timer,
5105 round_jiffies(jiffies + (2 * HZ)));
5106 }
5107
5108 /**
5109 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5110 * @adapter: board private structure to initialize
5111 *
5112 * ixgbe_sw_init initializes the Adapter private data structure.
5113 * Fields are initialized based on PCI device information and
5114 * OS network device settings (MTU size).
5115 **/
5116 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5117 {
5118 struct ixgbe_hw *hw = &adapter->hw;
5119 struct pci_dev *pdev = adapter->pdev;
5120 struct net_device *dev = adapter->netdev;
5121 unsigned int rss;
5122 #ifdef CONFIG_IXGBE_DCB
5123 int j;
5124 struct tc_configuration *tc;
5125 #endif
5126 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5127
5128 /* PCI config space info */
5129
5130 hw->vendor_id = pdev->vendor;
5131 hw->device_id = pdev->device;
5132 hw->revision_id = pdev->revision;
5133 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5134 hw->subsystem_device_id = pdev->subsystem_device;
5135
5136 /* Set capability flags */
5137 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5138 adapter->ring_feature[RING_F_RSS].indices = rss;
5139 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
5140 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
5141 switch (hw->mac.type) {
5142 case ixgbe_mac_82598EB:
5143 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5144 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5145 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
5146 break;
5147 case ixgbe_mac_82599EB:
5148 case ixgbe_mac_X540:
5149 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
5150 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5151 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5152 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5153 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5154 /* n-tuple support exists, always init our spinlock */
5155 spin_lock_init(&adapter->fdir_perfect_lock);
5156 /* Flow Director hash filters enabled */
5157 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5158 adapter->atr_sample_rate = 20;
5159 adapter->ring_feature[RING_F_FDIR].indices =
5160 IXGBE_MAX_FDIR_INDICES;
5161 adapter->fdir_pballoc = 0;
5162 #ifdef IXGBE_FCOE
5163 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5164 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5165 adapter->ring_feature[RING_F_FCOE].indices = 0;
5166 #ifdef CONFIG_IXGBE_DCB
5167 /* Default traffic class to use for FCoE */
5168 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
5169 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5170 #endif
5171 #endif /* IXGBE_FCOE */
5172 break;
5173 default:
5174 break;
5175 }
5176
5177 #ifdef CONFIG_IXGBE_DCB
5178 /* Configure DCB traffic classes */
5179 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5180 tc = &adapter->dcb_cfg.tc_config[j];
5181 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5182 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5183 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5184 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5185 tc->dcb_pfc = pfc_disabled;
5186 }
5187 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5188 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5189 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
5190 adapter->dcb_cfg.pfc_mode_enable = false;
5191 adapter->dcb_set_bitmap = 0x00;
5192 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5193 adapter->ring_feature[RING_F_DCB].indices);
5194
5195 #endif
5196
5197 /* default flow control settings */
5198 hw->fc.requested_mode = ixgbe_fc_full;
5199 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
5200 #ifdef CONFIG_DCB
5201 adapter->last_lfc_mode = hw->fc.current_mode;
5202 #endif
5203 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5204 hw->fc.low_water = FC_LOW_WATER(max_frame);
5205 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5206 hw->fc.send_xon = true;
5207 hw->fc.disable_fc_autoneg = false;
5208
5209 /* enable itr by default in dynamic mode */
5210 adapter->rx_itr_setting = 1;
5211 adapter->rx_eitr_param = 20000;
5212 adapter->tx_itr_setting = 1;
5213 adapter->tx_eitr_param = 10000;
5214
5215 /* set defaults for eitr in MegaBytes */
5216 adapter->eitr_low = 10;
5217 adapter->eitr_high = 20;
5218
5219 /* set default ring sizes */
5220 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5221 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5222
5223 /* initialize eeprom parameters */
5224 if (ixgbe_init_eeprom_params_generic(hw)) {
5225 e_dev_err("EEPROM initialization failed\n");
5226 return -EIO;
5227 }
5228
5229 /* enable rx csum by default */
5230 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5231
5232 /* get assigned NUMA node */
5233 adapter->node = dev_to_node(&pdev->dev);
5234
5235 set_bit(__IXGBE_DOWN, &adapter->state);
5236
5237 return 0;
5238 }
5239
5240 /**
5241 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5242 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5243 *
5244 * Return 0 on success, negative on failure
5245 **/
5246 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5247 {
5248 struct device *dev = tx_ring->dev;
5249 int size;
5250
5251 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5252 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
5253 if (!tx_ring->tx_buffer_info)
5254 tx_ring->tx_buffer_info = vzalloc(size);
5255 if (!tx_ring->tx_buffer_info)
5256 goto err;
5257
5258 /* round up to nearest 4K */
5259 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5260 tx_ring->size = ALIGN(tx_ring->size, 4096);
5261
5262 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5263 &tx_ring->dma, GFP_KERNEL);
5264 if (!tx_ring->desc)
5265 goto err;
5266
5267 tx_ring->next_to_use = 0;
5268 tx_ring->next_to_clean = 0;
5269 tx_ring->work_limit = tx_ring->count;
5270 return 0;
5271
5272 err:
5273 vfree(tx_ring->tx_buffer_info);
5274 tx_ring->tx_buffer_info = NULL;
5275 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5276 return -ENOMEM;
5277 }
5278
5279 /**
5280 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5281 * @adapter: board private structure
5282 *
5283 * If this function returns with an error, then it's possible one or
5284 * more of the rings is populated (while the rest are not). It is the
5285 * callers duty to clean those orphaned rings.
5286 *
5287 * Return 0 on success, negative on failure
5288 **/
5289 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5290 {
5291 int i, err = 0;
5292
5293 for (i = 0; i < adapter->num_tx_queues; i++) {
5294 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5295 if (!err)
5296 continue;
5297 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5298 break;
5299 }
5300
5301 return err;
5302 }
5303
5304 /**
5305 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5306 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5307 *
5308 * Returns 0 on success, negative on failure
5309 **/
5310 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5311 {
5312 struct device *dev = rx_ring->dev;
5313 int size;
5314
5315 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5316 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5317 if (!rx_ring->rx_buffer_info)
5318 rx_ring->rx_buffer_info = vzalloc(size);
5319 if (!rx_ring->rx_buffer_info)
5320 goto err;
5321
5322 /* Round up to nearest 4K */
5323 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5324 rx_ring->size = ALIGN(rx_ring->size, 4096);
5325
5326 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5327 &rx_ring->dma, GFP_KERNEL);
5328
5329 if (!rx_ring->desc)
5330 goto err;
5331
5332 rx_ring->next_to_clean = 0;
5333 rx_ring->next_to_use = 0;
5334
5335 return 0;
5336 err:
5337 vfree(rx_ring->rx_buffer_info);
5338 rx_ring->rx_buffer_info = NULL;
5339 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5340 return -ENOMEM;
5341 }
5342
5343 /**
5344 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5345 * @adapter: board private structure
5346 *
5347 * If this function returns with an error, then it's possible one or
5348 * more of the rings is populated (while the rest are not). It is the
5349 * callers duty to clean those orphaned rings.
5350 *
5351 * Return 0 on success, negative on failure
5352 **/
5353 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5354 {
5355 int i, err = 0;
5356
5357 for (i = 0; i < adapter->num_rx_queues; i++) {
5358 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5359 if (!err)
5360 continue;
5361 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5362 break;
5363 }
5364
5365 return err;
5366 }
5367
5368 /**
5369 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5370 * @tx_ring: Tx descriptor ring for a specific queue
5371 *
5372 * Free all transmit software resources
5373 **/
5374 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5375 {
5376 ixgbe_clean_tx_ring(tx_ring);
5377
5378 vfree(tx_ring->tx_buffer_info);
5379 tx_ring->tx_buffer_info = NULL;
5380
5381 /* if not set, then don't free */
5382 if (!tx_ring->desc)
5383 return;
5384
5385 dma_free_coherent(tx_ring->dev, tx_ring->size,
5386 tx_ring->desc, tx_ring->dma);
5387
5388 tx_ring->desc = NULL;
5389 }
5390
5391 /**
5392 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5393 * @adapter: board private structure
5394 *
5395 * Free all transmit software resources
5396 **/
5397 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5398 {
5399 int i;
5400
5401 for (i = 0; i < adapter->num_tx_queues; i++)
5402 if (adapter->tx_ring[i]->desc)
5403 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5404 }
5405
5406 /**
5407 * ixgbe_free_rx_resources - Free Rx Resources
5408 * @rx_ring: ring to clean the resources from
5409 *
5410 * Free all receive software resources
5411 **/
5412 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5413 {
5414 ixgbe_clean_rx_ring(rx_ring);
5415
5416 vfree(rx_ring->rx_buffer_info);
5417 rx_ring->rx_buffer_info = NULL;
5418
5419 /* if not set, then don't free */
5420 if (!rx_ring->desc)
5421 return;
5422
5423 dma_free_coherent(rx_ring->dev, rx_ring->size,
5424 rx_ring->desc, rx_ring->dma);
5425
5426 rx_ring->desc = NULL;
5427 }
5428
5429 /**
5430 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5431 * @adapter: board private structure
5432 *
5433 * Free all receive software resources
5434 **/
5435 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5436 {
5437 int i;
5438
5439 for (i = 0; i < adapter->num_rx_queues; i++)
5440 if (adapter->rx_ring[i]->desc)
5441 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5442 }
5443
5444 /**
5445 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5446 * @netdev: network interface device structure
5447 * @new_mtu: new value for maximum frame size
5448 *
5449 * Returns 0 on success, negative on failure
5450 **/
5451 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5452 {
5453 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5454 struct ixgbe_hw *hw = &adapter->hw;
5455 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5456
5457 /* MTU < 68 is an error and causes problems on some kernels */
5458 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5459 hw->mac.type != ixgbe_mac_X540) {
5460 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5461 return -EINVAL;
5462 } else {
5463 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5464 return -EINVAL;
5465 }
5466
5467 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5468 /* must set new MTU before calling down or up */
5469 netdev->mtu = new_mtu;
5470
5471 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5472 hw->fc.low_water = FC_LOW_WATER(max_frame);
5473
5474 if (netif_running(netdev))
5475 ixgbe_reinit_locked(adapter);
5476
5477 return 0;
5478 }
5479
5480 /**
5481 * ixgbe_open - Called when a network interface is made active
5482 * @netdev: network interface device structure
5483 *
5484 * Returns 0 on success, negative value on failure
5485 *
5486 * The open entry point is called when a network interface is made
5487 * active by the system (IFF_UP). At this point all resources needed
5488 * for transmit and receive operations are allocated, the interrupt
5489 * handler is registered with the OS, the watchdog timer is started,
5490 * and the stack is notified that the interface is ready.
5491 **/
5492 static int ixgbe_open(struct net_device *netdev)
5493 {
5494 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5495 int err;
5496
5497 /* disallow open during test */
5498 if (test_bit(__IXGBE_TESTING, &adapter->state))
5499 return -EBUSY;
5500
5501 netif_carrier_off(netdev);
5502
5503 /* allocate transmit descriptors */
5504 err = ixgbe_setup_all_tx_resources(adapter);
5505 if (err)
5506 goto err_setup_tx;
5507
5508 /* allocate receive descriptors */
5509 err = ixgbe_setup_all_rx_resources(adapter);
5510 if (err)
5511 goto err_setup_rx;
5512
5513 ixgbe_configure(adapter);
5514
5515 err = ixgbe_request_irq(adapter);
5516 if (err)
5517 goto err_req_irq;
5518
5519 err = ixgbe_up_complete(adapter);
5520 if (err)
5521 goto err_up;
5522
5523 netif_tx_start_all_queues(netdev);
5524
5525 return 0;
5526
5527 err_up:
5528 ixgbe_release_hw_control(adapter);
5529 ixgbe_free_irq(adapter);
5530 err_req_irq:
5531 err_setup_rx:
5532 ixgbe_free_all_rx_resources(adapter);
5533 err_setup_tx:
5534 ixgbe_free_all_tx_resources(adapter);
5535 ixgbe_reset(adapter);
5536
5537 return err;
5538 }
5539
5540 /**
5541 * ixgbe_close - Disables a network interface
5542 * @netdev: network interface device structure
5543 *
5544 * Returns 0, this is not allowed to fail
5545 *
5546 * The close entry point is called when an interface is de-activated
5547 * by the OS. The hardware is still under the drivers control, but
5548 * needs to be disabled. A global MAC reset is issued to stop the
5549 * hardware, and all transmit and receive resources are freed.
5550 **/
5551 static int ixgbe_close(struct net_device *netdev)
5552 {
5553 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5554
5555 ixgbe_down(adapter);
5556 ixgbe_free_irq(adapter);
5557
5558 ixgbe_free_all_tx_resources(adapter);
5559 ixgbe_free_all_rx_resources(adapter);
5560
5561 ixgbe_release_hw_control(adapter);
5562
5563 return 0;
5564 }
5565
5566 #ifdef CONFIG_PM
5567 static int ixgbe_resume(struct pci_dev *pdev)
5568 {
5569 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5570 struct net_device *netdev = adapter->netdev;
5571 u32 err;
5572
5573 pci_set_power_state(pdev, PCI_D0);
5574 pci_restore_state(pdev);
5575 /*
5576 * pci_restore_state clears dev->state_saved so call
5577 * pci_save_state to restore it.
5578 */
5579 pci_save_state(pdev);
5580
5581 err = pci_enable_device_mem(pdev);
5582 if (err) {
5583 e_dev_err("Cannot enable PCI device from suspend\n");
5584 return err;
5585 }
5586 pci_set_master(pdev);
5587
5588 pci_wake_from_d3(pdev, false);
5589
5590 err = ixgbe_init_interrupt_scheme(adapter);
5591 if (err) {
5592 e_dev_err("Cannot initialize interrupts for device\n");
5593 return err;
5594 }
5595
5596 ixgbe_reset(adapter);
5597
5598 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5599
5600 if (netif_running(netdev)) {
5601 err = ixgbe_open(netdev);
5602 if (err)
5603 return err;
5604 }
5605
5606 netif_device_attach(netdev);
5607
5608 return 0;
5609 }
5610 #endif /* CONFIG_PM */
5611
5612 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5613 {
5614 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5615 struct net_device *netdev = adapter->netdev;
5616 struct ixgbe_hw *hw = &adapter->hw;
5617 u32 ctrl, fctrl;
5618 u32 wufc = adapter->wol;
5619 #ifdef CONFIG_PM
5620 int retval = 0;
5621 #endif
5622
5623 netif_device_detach(netdev);
5624
5625 if (netif_running(netdev)) {
5626 ixgbe_down(adapter);
5627 ixgbe_free_irq(adapter);
5628 ixgbe_free_all_tx_resources(adapter);
5629 ixgbe_free_all_rx_resources(adapter);
5630 }
5631
5632 ixgbe_clear_interrupt_scheme(adapter);
5633 #ifdef CONFIG_DCB
5634 kfree(adapter->ixgbe_ieee_pfc);
5635 kfree(adapter->ixgbe_ieee_ets);
5636 #endif
5637
5638 #ifdef CONFIG_PM
5639 retval = pci_save_state(pdev);
5640 if (retval)
5641 return retval;
5642
5643 #endif
5644 if (wufc) {
5645 ixgbe_set_rx_mode(netdev);
5646
5647 /* turn on all-multi mode if wake on multicast is enabled */
5648 if (wufc & IXGBE_WUFC_MC) {
5649 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5650 fctrl |= IXGBE_FCTRL_MPE;
5651 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5652 }
5653
5654 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5655 ctrl |= IXGBE_CTRL_GIO_DIS;
5656 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5657
5658 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5659 } else {
5660 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5661 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5662 }
5663
5664 switch (hw->mac.type) {
5665 case ixgbe_mac_82598EB:
5666 pci_wake_from_d3(pdev, false);
5667 break;
5668 case ixgbe_mac_82599EB:
5669 case ixgbe_mac_X540:
5670 pci_wake_from_d3(pdev, !!wufc);
5671 break;
5672 default:
5673 break;
5674 }
5675
5676 *enable_wake = !!wufc;
5677
5678 ixgbe_release_hw_control(adapter);
5679
5680 pci_disable_device(pdev);
5681
5682 return 0;
5683 }
5684
5685 #ifdef CONFIG_PM
5686 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5687 {
5688 int retval;
5689 bool wake;
5690
5691 retval = __ixgbe_shutdown(pdev, &wake);
5692 if (retval)
5693 return retval;
5694
5695 if (wake) {
5696 pci_prepare_to_sleep(pdev);
5697 } else {
5698 pci_wake_from_d3(pdev, false);
5699 pci_set_power_state(pdev, PCI_D3hot);
5700 }
5701
5702 return 0;
5703 }
5704 #endif /* CONFIG_PM */
5705
5706 static void ixgbe_shutdown(struct pci_dev *pdev)
5707 {
5708 bool wake;
5709
5710 __ixgbe_shutdown(pdev, &wake);
5711
5712 if (system_state == SYSTEM_POWER_OFF) {
5713 pci_wake_from_d3(pdev, wake);
5714 pci_set_power_state(pdev, PCI_D3hot);
5715 }
5716 }
5717
5718 /**
5719 * ixgbe_update_stats - Update the board statistics counters.
5720 * @adapter: board private structure
5721 **/
5722 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5723 {
5724 struct net_device *netdev = adapter->netdev;
5725 struct ixgbe_hw *hw = &adapter->hw;
5726 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5727 u64 total_mpc = 0;
5728 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5729 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5730 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5731 u64 bytes = 0, packets = 0;
5732
5733 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5734 test_bit(__IXGBE_RESETTING, &adapter->state))
5735 return;
5736
5737 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5738 u64 rsc_count = 0;
5739 u64 rsc_flush = 0;
5740 for (i = 0; i < 16; i++)
5741 adapter->hw_rx_no_dma_resources +=
5742 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5743 for (i = 0; i < adapter->num_rx_queues; i++) {
5744 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5745 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5746 }
5747 adapter->rsc_total_count = rsc_count;
5748 adapter->rsc_total_flush = rsc_flush;
5749 }
5750
5751 for (i = 0; i < adapter->num_rx_queues; i++) {
5752 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5753 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5754 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5755 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5756 bytes += rx_ring->stats.bytes;
5757 packets += rx_ring->stats.packets;
5758 }
5759 adapter->non_eop_descs = non_eop_descs;
5760 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5761 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5762 netdev->stats.rx_bytes = bytes;
5763 netdev->stats.rx_packets = packets;
5764
5765 bytes = 0;
5766 packets = 0;
5767 /* gather some stats to the adapter struct that are per queue */
5768 for (i = 0; i < adapter->num_tx_queues; i++) {
5769 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5770 restart_queue += tx_ring->tx_stats.restart_queue;
5771 tx_busy += tx_ring->tx_stats.tx_busy;
5772 bytes += tx_ring->stats.bytes;
5773 packets += tx_ring->stats.packets;
5774 }
5775 adapter->restart_queue = restart_queue;
5776 adapter->tx_busy = tx_busy;
5777 netdev->stats.tx_bytes = bytes;
5778 netdev->stats.tx_packets = packets;
5779
5780 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5781 for (i = 0; i < 8; i++) {
5782 /* for packet buffers not used, the register should read 0 */
5783 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5784 missed_rx += mpc;
5785 hwstats->mpc[i] += mpc;
5786 total_mpc += hwstats->mpc[i];
5787 if (hw->mac.type == ixgbe_mac_82598EB)
5788 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5789 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5790 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5791 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5792 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5793 switch (hw->mac.type) {
5794 case ixgbe_mac_82598EB:
5795 hwstats->pxonrxc[i] +=
5796 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5797 break;
5798 case ixgbe_mac_82599EB:
5799 case ixgbe_mac_X540:
5800 hwstats->pxonrxc[i] +=
5801 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5802 break;
5803 default:
5804 break;
5805 }
5806 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5807 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5808 }
5809 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5810 /* work around hardware counting issue */
5811 hwstats->gprc -= missed_rx;
5812
5813 ixgbe_update_xoff_received(adapter);
5814
5815 /* 82598 hardware only has a 32 bit counter in the high register */
5816 switch (hw->mac.type) {
5817 case ixgbe_mac_82598EB:
5818 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5819 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5820 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5821 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5822 break;
5823 case ixgbe_mac_82599EB:
5824 case ixgbe_mac_X540:
5825 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5826 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5827 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5828 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5829 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5830 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5831 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5832 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5833 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5834 #ifdef IXGBE_FCOE
5835 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5836 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5837 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5838 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5839 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5840 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5841 #endif /* IXGBE_FCOE */
5842 break;
5843 default:
5844 break;
5845 }
5846 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5847 hwstats->bprc += bprc;
5848 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5849 if (hw->mac.type == ixgbe_mac_82598EB)
5850 hwstats->mprc -= bprc;
5851 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5852 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5853 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5854 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5855 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5856 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5857 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5858 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5859 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5860 hwstats->lxontxc += lxon;
5861 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5862 hwstats->lxofftxc += lxoff;
5863 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5864 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5865 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5866 /*
5867 * 82598 errata - tx of flow control packets is included in tx counters
5868 */
5869 xon_off_tot = lxon + lxoff;
5870 hwstats->gptc -= xon_off_tot;
5871 hwstats->mptc -= xon_off_tot;
5872 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5873 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5874 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5875 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5876 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5877 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5878 hwstats->ptc64 -= xon_off_tot;
5879 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5880 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5881 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5882 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5883 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5884 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5885
5886 /* Fill out the OS statistics structure */
5887 netdev->stats.multicast = hwstats->mprc;
5888
5889 /* Rx Errors */
5890 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5891 netdev->stats.rx_dropped = 0;
5892 netdev->stats.rx_length_errors = hwstats->rlec;
5893 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5894 netdev->stats.rx_missed_errors = total_mpc;
5895 }
5896
5897 /**
5898 * ixgbe_watchdog - Timer Call-back
5899 * @data: pointer to adapter cast into an unsigned long
5900 **/
5901 static void ixgbe_watchdog(unsigned long data)
5902 {
5903 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5904 struct ixgbe_hw *hw = &adapter->hw;
5905 u64 eics = 0;
5906 int i;
5907
5908 /*
5909 * Do the watchdog outside of interrupt context due to the lovely
5910 * delays that some of the newer hardware requires
5911 */
5912
5913 if (test_bit(__IXGBE_DOWN, &adapter->state))
5914 goto watchdog_short_circuit;
5915
5916 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5917 /*
5918 * for legacy and MSI interrupts don't set any bits
5919 * that are enabled for EIAM, because this operation
5920 * would set *both* EIMS and EICS for any bit in EIAM
5921 */
5922 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5923 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5924 goto watchdog_reschedule;
5925 }
5926
5927 /* get one bit for every active tx/rx interrupt vector */
5928 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5929 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5930 if (qv->rxr_count || qv->txr_count)
5931 eics |= ((u64)1 << i);
5932 }
5933
5934 /* Cause software interrupt to ensure rx rings are cleaned */
5935 ixgbe_irq_rearm_queues(adapter, eics);
5936
5937 watchdog_reschedule:
5938 /* Reset the timer */
5939 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5940
5941 watchdog_short_circuit:
5942 schedule_work(&adapter->watchdog_task);
5943 }
5944
5945 /**
5946 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5947 * @work: pointer to work_struct containing our data
5948 **/
5949 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5950 {
5951 struct ixgbe_adapter *adapter = container_of(work,
5952 struct ixgbe_adapter,
5953 multispeed_fiber_task);
5954 struct ixgbe_hw *hw = &adapter->hw;
5955 u32 autoneg;
5956 bool negotiation;
5957
5958 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5959 autoneg = hw->phy.autoneg_advertised;
5960 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5961 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5962 hw->mac.autotry_restart = false;
5963 if (hw->mac.ops.setup_link)
5964 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5965 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5966 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5967 }
5968
5969 /**
5970 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5971 * @work: pointer to work_struct containing our data
5972 **/
5973 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5974 {
5975 struct ixgbe_adapter *adapter = container_of(work,
5976 struct ixgbe_adapter,
5977 sfp_config_module_task);
5978 struct ixgbe_hw *hw = &adapter->hw;
5979 u32 err;
5980
5981 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5982
5983 /* Time for electrical oscillations to settle down */
5984 msleep(100);
5985 err = hw->phy.ops.identify_sfp(hw);
5986
5987 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5988 e_dev_err("failed to initialize because an unsupported SFP+ "
5989 "module type was detected.\n");
5990 e_dev_err("Reload the driver after installing a supported "
5991 "module.\n");
5992 unregister_netdev(adapter->netdev);
5993 return;
5994 }
5995 if (hw->mac.ops.setup_sfp)
5996 hw->mac.ops.setup_sfp(hw);
5997
5998 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5999 /* This will also work for DA Twinax connections */
6000 schedule_work(&adapter->multispeed_fiber_task);
6001 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
6002 }
6003
6004 /**
6005 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
6006 * @work: pointer to work_struct containing our data
6007 **/
6008 static void ixgbe_fdir_reinit_task(struct work_struct *work)
6009 {
6010 struct ixgbe_adapter *adapter = container_of(work,
6011 struct ixgbe_adapter,
6012 fdir_reinit_task);
6013 struct ixgbe_hw *hw = &adapter->hw;
6014 int i;
6015
6016 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6017 for (i = 0; i < adapter->num_tx_queues; i++)
6018 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
6019 &(adapter->tx_ring[i]->state));
6020 } else {
6021 e_err(probe, "failed to finish FDIR re-initialization, "
6022 "ignored adding FDIR ATR filters\n");
6023 }
6024 /* Done FDIR Re-initialization, enable transmits */
6025 netif_tx_start_all_queues(adapter->netdev);
6026 }
6027
6028 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6029 {
6030 u32 ssvpc;
6031
6032 /* Do not perform spoof check for 82598 */
6033 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6034 return;
6035
6036 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6037
6038 /*
6039 * ssvpc register is cleared on read, if zero then no
6040 * spoofed packets in the last interval.
6041 */
6042 if (!ssvpc)
6043 return;
6044
6045 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6046 }
6047
6048 static DEFINE_MUTEX(ixgbe_watchdog_lock);
6049
6050 /**
6051 * ixgbe_watchdog_task - worker thread to bring link up
6052 * @work: pointer to work_struct containing our data
6053 **/
6054 static void ixgbe_watchdog_task(struct work_struct *work)
6055 {
6056 struct ixgbe_adapter *adapter = container_of(work,
6057 struct ixgbe_adapter,
6058 watchdog_task);
6059 struct net_device *netdev = adapter->netdev;
6060 struct ixgbe_hw *hw = &adapter->hw;
6061 u32 link_speed;
6062 bool link_up;
6063 int i;
6064 struct ixgbe_ring *tx_ring;
6065 int some_tx_pending = 0;
6066
6067 mutex_lock(&ixgbe_watchdog_lock);
6068
6069 link_up = adapter->link_up;
6070 link_speed = adapter->link_speed;
6071
6072 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
6073 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
6074 if (link_up) {
6075 #ifdef CONFIG_DCB
6076 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6077 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
6078 hw->mac.ops.fc_enable(hw, i);
6079 } else {
6080 hw->mac.ops.fc_enable(hw, 0);
6081 }
6082 #else
6083 hw->mac.ops.fc_enable(hw, 0);
6084 #endif
6085 }
6086
6087 if (link_up ||
6088 time_after(jiffies, (adapter->link_check_timeout +
6089 IXGBE_TRY_LINK_TIMEOUT))) {
6090 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6091 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6092 }
6093 adapter->link_up = link_up;
6094 adapter->link_speed = link_speed;
6095 }
6096
6097 if (link_up) {
6098 if (!netif_carrier_ok(netdev)) {
6099 bool flow_rx, flow_tx;
6100
6101 switch (hw->mac.type) {
6102 case ixgbe_mac_82598EB: {
6103 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6104 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6105 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6106 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6107 }
6108 break;
6109 case ixgbe_mac_82599EB:
6110 case ixgbe_mac_X540: {
6111 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6112 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6113 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6114 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6115 }
6116 break;
6117 default:
6118 flow_tx = false;
6119 flow_rx = false;
6120 break;
6121 }
6122
6123 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6124 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6125 "10 Gbps" :
6126 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6127 "1 Gbps" :
6128 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6129 "100 Mbps" :
6130 "unknown speed"))),
6131 ((flow_rx && flow_tx) ? "RX/TX" :
6132 (flow_rx ? "RX" :
6133 (flow_tx ? "TX" : "None"))));
6134
6135 netif_carrier_on(netdev);
6136 } else {
6137 /* Force detection of hung controller */
6138 for (i = 0; i < adapter->num_tx_queues; i++) {
6139 tx_ring = adapter->tx_ring[i];
6140 set_check_for_tx_hang(tx_ring);
6141 }
6142 }
6143 } else {
6144 adapter->link_up = false;
6145 adapter->link_speed = 0;
6146 if (netif_carrier_ok(netdev)) {
6147 e_info(drv, "NIC Link is Down\n");
6148 netif_carrier_off(netdev);
6149 }
6150 }
6151
6152 if (!netif_carrier_ok(netdev)) {
6153 for (i = 0; i < adapter->num_tx_queues; i++) {
6154 tx_ring = adapter->tx_ring[i];
6155 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6156 some_tx_pending = 1;
6157 break;
6158 }
6159 }
6160
6161 if (some_tx_pending) {
6162 /* We've lost link, so the controller stops DMA,
6163 * but we've got queued Tx work that's never going
6164 * to get done, so reset controller to flush Tx.
6165 * (Do the reset outside of interrupt context).
6166 */
6167 schedule_work(&adapter->reset_task);
6168 }
6169 }
6170
6171 ixgbe_spoof_check(adapter);
6172 ixgbe_update_stats(adapter);
6173 mutex_unlock(&ixgbe_watchdog_lock);
6174 }
6175
6176 static int ixgbe_tso(struct ixgbe_adapter *adapter,
6177 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6178 u32 tx_flags, u8 *hdr_len, __be16 protocol)
6179 {
6180 struct ixgbe_adv_tx_context_desc *context_desc;
6181 unsigned int i;
6182 int err;
6183 struct ixgbe_tx_buffer *tx_buffer_info;
6184 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
6185 u32 mss_l4len_idx, l4len;
6186
6187 if (skb_is_gso(skb)) {
6188 if (skb_header_cloned(skb)) {
6189 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6190 if (err)
6191 return err;
6192 }
6193 l4len = tcp_hdrlen(skb);
6194 *hdr_len += l4len;
6195
6196 if (protocol == htons(ETH_P_IP)) {
6197 struct iphdr *iph = ip_hdr(skb);
6198 iph->tot_len = 0;
6199 iph->check = 0;
6200 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6201 iph->daddr, 0,
6202 IPPROTO_TCP,
6203 0);
6204 } else if (skb_is_gso_v6(skb)) {
6205 ipv6_hdr(skb)->payload_len = 0;
6206 tcp_hdr(skb)->check =
6207 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6208 &ipv6_hdr(skb)->daddr,
6209 0, IPPROTO_TCP, 0);
6210 }
6211
6212 i = tx_ring->next_to_use;
6213
6214 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6215 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6216
6217 /* VLAN MACLEN IPLEN */
6218 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6219 vlan_macip_lens |=
6220 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6221 vlan_macip_lens |= ((skb_network_offset(skb)) <<
6222 IXGBE_ADVTXD_MACLEN_SHIFT);
6223 *hdr_len += skb_network_offset(skb);
6224 vlan_macip_lens |=
6225 (skb_transport_header(skb) - skb_network_header(skb));
6226 *hdr_len +=
6227 (skb_transport_header(skb) - skb_network_header(skb));
6228 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6229 context_desc->seqnum_seed = 0;
6230
6231 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6232 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
6233 IXGBE_ADVTXD_DTYP_CTXT);
6234
6235 if (protocol == htons(ETH_P_IP))
6236 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
6237 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6238 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6239
6240 /* MSS L4LEN IDX */
6241 mss_l4len_idx =
6242 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
6243 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
6244 /* use index 1 for TSO */
6245 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6246 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6247
6248 tx_buffer_info->time_stamp = jiffies;
6249 tx_buffer_info->next_to_watch = i;
6250
6251 i++;
6252 if (i == tx_ring->count)
6253 i = 0;
6254 tx_ring->next_to_use = i;
6255
6256 return true;
6257 }
6258 return false;
6259 }
6260
6261 static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6262 __be16 protocol)
6263 {
6264 u32 rtn = 0;
6265
6266 switch (protocol) {
6267 case cpu_to_be16(ETH_P_IP):
6268 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
6269 switch (ip_hdr(skb)->protocol) {
6270 case IPPROTO_TCP:
6271 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6272 break;
6273 case IPPROTO_SCTP:
6274 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6275 break;
6276 }
6277 break;
6278 case cpu_to_be16(ETH_P_IPV6):
6279 /* XXX what about other V6 headers?? */
6280 switch (ipv6_hdr(skb)->nexthdr) {
6281 case IPPROTO_TCP:
6282 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6283 break;
6284 case IPPROTO_SCTP:
6285 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6286 break;
6287 }
6288 break;
6289 default:
6290 if (unlikely(net_ratelimit()))
6291 e_warn(probe, "partial checksum but proto=%x!\n",
6292 protocol);
6293 break;
6294 }
6295
6296 return rtn;
6297 }
6298
6299 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
6300 struct ixgbe_ring *tx_ring,
6301 struct sk_buff *skb, u32 tx_flags,
6302 __be16 protocol)
6303 {
6304 struct ixgbe_adv_tx_context_desc *context_desc;
6305 unsigned int i;
6306 struct ixgbe_tx_buffer *tx_buffer_info;
6307 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6308
6309 if (skb->ip_summed == CHECKSUM_PARTIAL ||
6310 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6311 i = tx_ring->next_to_use;
6312 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6313 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6314
6315 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6316 vlan_macip_lens |=
6317 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6318 vlan_macip_lens |= (skb_network_offset(skb) <<
6319 IXGBE_ADVTXD_MACLEN_SHIFT);
6320 if (skb->ip_summed == CHECKSUM_PARTIAL)
6321 vlan_macip_lens |= (skb_transport_header(skb) -
6322 skb_network_header(skb));
6323
6324 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6325 context_desc->seqnum_seed = 0;
6326
6327 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
6328 IXGBE_ADVTXD_DTYP_CTXT);
6329
6330 if (skb->ip_summed == CHECKSUM_PARTIAL)
6331 type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
6332
6333 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6334 /* use index zero for tx checksum offload */
6335 context_desc->mss_l4len_idx = 0;
6336
6337 tx_buffer_info->time_stamp = jiffies;
6338 tx_buffer_info->next_to_watch = i;
6339
6340 i++;
6341 if (i == tx_ring->count)
6342 i = 0;
6343 tx_ring->next_to_use = i;
6344
6345 return true;
6346 }
6347
6348 return false;
6349 }
6350
6351 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6352 struct ixgbe_ring *tx_ring,
6353 struct sk_buff *skb, u32 tx_flags,
6354 unsigned int first, const u8 hdr_len)
6355 {
6356 struct device *dev = tx_ring->dev;
6357 struct ixgbe_tx_buffer *tx_buffer_info;
6358 unsigned int len;
6359 unsigned int total = skb->len;
6360 unsigned int offset = 0, size, count = 0, i;
6361 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6362 unsigned int f;
6363 unsigned int bytecount = skb->len;
6364 u16 gso_segs = 1;
6365
6366 i = tx_ring->next_to_use;
6367
6368 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6369 /* excluding fcoe_crc_eof for FCoE */
6370 total -= sizeof(struct fcoe_crc_eof);
6371
6372 len = min(skb_headlen(skb), total);
6373 while (len) {
6374 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6375 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6376
6377 tx_buffer_info->length = size;
6378 tx_buffer_info->mapped_as_page = false;
6379 tx_buffer_info->dma = dma_map_single(dev,
6380 skb->data + offset,
6381 size, DMA_TO_DEVICE);
6382 if (dma_mapping_error(dev, tx_buffer_info->dma))
6383 goto dma_error;
6384 tx_buffer_info->time_stamp = jiffies;
6385 tx_buffer_info->next_to_watch = i;
6386
6387 len -= size;
6388 total -= size;
6389 offset += size;
6390 count++;
6391
6392 if (len) {
6393 i++;
6394 if (i == tx_ring->count)
6395 i = 0;
6396 }
6397 }
6398
6399 for (f = 0; f < nr_frags; f++) {
6400 struct skb_frag_struct *frag;
6401
6402 frag = &skb_shinfo(skb)->frags[f];
6403 len = min((unsigned int)frag->size, total);
6404 offset = frag->page_offset;
6405
6406 while (len) {
6407 i++;
6408 if (i == tx_ring->count)
6409 i = 0;
6410
6411 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6412 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6413
6414 tx_buffer_info->length = size;
6415 tx_buffer_info->dma = dma_map_page(dev,
6416 frag->page,
6417 offset, size,
6418 DMA_TO_DEVICE);
6419 tx_buffer_info->mapped_as_page = true;
6420 if (dma_mapping_error(dev, tx_buffer_info->dma))
6421 goto dma_error;
6422 tx_buffer_info->time_stamp = jiffies;
6423 tx_buffer_info->next_to_watch = i;
6424
6425 len -= size;
6426 total -= size;
6427 offset += size;
6428 count++;
6429 }
6430 if (total == 0)
6431 break;
6432 }
6433
6434 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6435 gso_segs = skb_shinfo(skb)->gso_segs;
6436 #ifdef IXGBE_FCOE
6437 /* adjust for FCoE Sequence Offload */
6438 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6439 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6440 skb_shinfo(skb)->gso_size);
6441 #endif /* IXGBE_FCOE */
6442 bytecount += (gso_segs - 1) * hdr_len;
6443
6444 /* multiply data chunks by size of headers */
6445 tx_ring->tx_buffer_info[i].bytecount = bytecount;
6446 tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6447 tx_ring->tx_buffer_info[i].skb = skb;
6448 tx_ring->tx_buffer_info[first].next_to_watch = i;
6449
6450 return count;
6451
6452 dma_error:
6453 e_dev_err("TX DMA map failed\n");
6454
6455 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6456 tx_buffer_info->dma = 0;
6457 tx_buffer_info->time_stamp = 0;
6458 tx_buffer_info->next_to_watch = 0;
6459 if (count)
6460 count--;
6461
6462 /* clear timestamp and dma mappings for remaining portion of packet */
6463 while (count--) {
6464 if (i == 0)
6465 i += tx_ring->count;
6466 i--;
6467 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6468 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6469 }
6470
6471 return 0;
6472 }
6473
6474 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6475 int tx_flags, int count, u32 paylen, u8 hdr_len)
6476 {
6477 union ixgbe_adv_tx_desc *tx_desc = NULL;
6478 struct ixgbe_tx_buffer *tx_buffer_info;
6479 u32 olinfo_status = 0, cmd_type_len = 0;
6480 unsigned int i;
6481 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6482
6483 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6484
6485 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6486
6487 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6488 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6489
6490 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6491 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6492
6493 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6494 IXGBE_ADVTXD_POPTS_SHIFT;
6495
6496 /* use index 1 context for tso */
6497 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6498 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6499 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6500 IXGBE_ADVTXD_POPTS_SHIFT;
6501
6502 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6503 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6504 IXGBE_ADVTXD_POPTS_SHIFT;
6505
6506 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6507 olinfo_status |= IXGBE_ADVTXD_CC;
6508 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6509 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6510 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6511 }
6512
6513 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6514
6515 i = tx_ring->next_to_use;
6516 while (count--) {
6517 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6518 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6519 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6520 tx_desc->read.cmd_type_len =
6521 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6522 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6523 i++;
6524 if (i == tx_ring->count)
6525 i = 0;
6526 }
6527
6528 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6529
6530 /*
6531 * Force memory writes to complete before letting h/w
6532 * know there are new descriptors to fetch. (Only
6533 * applicable for weak-ordered memory model archs,
6534 * such as IA-64).
6535 */
6536 wmb();
6537
6538 tx_ring->next_to_use = i;
6539 writel(i, tx_ring->tail);
6540 }
6541
6542 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6543 u32 tx_flags, __be16 protocol)
6544 {
6545 struct ixgbe_q_vector *q_vector = ring->q_vector;
6546 union ixgbe_atr_hash_dword input = { .dword = 0 };
6547 union ixgbe_atr_hash_dword common = { .dword = 0 };
6548 union {
6549 unsigned char *network;
6550 struct iphdr *ipv4;
6551 struct ipv6hdr *ipv6;
6552 } hdr;
6553 struct tcphdr *th;
6554 __be16 vlan_id;
6555
6556 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6557 if (!q_vector)
6558 return;
6559
6560 /* do nothing if sampling is disabled */
6561 if (!ring->atr_sample_rate)
6562 return;
6563
6564 ring->atr_count++;
6565
6566 /* snag network header to get L4 type and address */
6567 hdr.network = skb_network_header(skb);
6568
6569 /* Currently only IPv4/IPv6 with TCP is supported */
6570 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6571 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6572 (protocol != __constant_htons(ETH_P_IP) ||
6573 hdr.ipv4->protocol != IPPROTO_TCP))
6574 return;
6575
6576 th = tcp_hdr(skb);
6577
6578 /* skip this packet since the socket is closing */
6579 if (th->fin)
6580 return;
6581
6582 /* sample on all syn packets or once every atr sample count */
6583 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6584 return;
6585
6586 /* reset sample count */
6587 ring->atr_count = 0;
6588
6589 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6590
6591 /*
6592 * src and dst are inverted, think how the receiver sees them
6593 *
6594 * The input is broken into two sections, a non-compressed section
6595 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6596 * is XORed together and stored in the compressed dword.
6597 */
6598 input.formatted.vlan_id = vlan_id;
6599
6600 /*
6601 * since src port and flex bytes occupy the same word XOR them together
6602 * and write the value to source port portion of compressed dword
6603 */
6604 if (vlan_id)
6605 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6606 else
6607 common.port.src ^= th->dest ^ protocol;
6608 common.port.dst ^= th->source;
6609
6610 if (protocol == __constant_htons(ETH_P_IP)) {
6611 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6612 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6613 } else {
6614 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6615 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6616 hdr.ipv6->saddr.s6_addr32[1] ^
6617 hdr.ipv6->saddr.s6_addr32[2] ^
6618 hdr.ipv6->saddr.s6_addr32[3] ^
6619 hdr.ipv6->daddr.s6_addr32[0] ^
6620 hdr.ipv6->daddr.s6_addr32[1] ^
6621 hdr.ipv6->daddr.s6_addr32[2] ^
6622 hdr.ipv6->daddr.s6_addr32[3];
6623 }
6624
6625 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6626 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6627 input, common, ring->queue_index);
6628 }
6629
6630 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6631 {
6632 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6633 /* Herbert's original patch had:
6634 * smp_mb__after_netif_stop_queue();
6635 * but since that doesn't exist yet, just open code it. */
6636 smp_mb();
6637
6638 /* We need to check again in a case another CPU has just
6639 * made room available. */
6640 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6641 return -EBUSY;
6642
6643 /* A reprieve! - use start_queue because it doesn't call schedule */
6644 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6645 ++tx_ring->tx_stats.restart_queue;
6646 return 0;
6647 }
6648
6649 static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6650 {
6651 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6652 return 0;
6653 return __ixgbe_maybe_stop_tx(tx_ring, size);
6654 }
6655
6656 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6657 {
6658 struct ixgbe_adapter *adapter = netdev_priv(dev);
6659 int txq = smp_processor_id();
6660 #ifdef IXGBE_FCOE
6661 __be16 protocol;
6662
6663 protocol = vlan_get_protocol(skb);
6664
6665 if ((protocol == htons(ETH_P_FCOE)) ||
6666 (protocol == htons(ETH_P_FIP))) {
6667 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6668 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6669 txq += adapter->ring_feature[RING_F_FCOE].mask;
6670 return txq;
6671 #ifdef CONFIG_IXGBE_DCB
6672 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6673 txq = adapter->fcoe.up;
6674 return txq;
6675 #endif
6676 }
6677 }
6678 #endif
6679
6680 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6681 while (unlikely(txq >= dev->real_num_tx_queues))
6682 txq -= dev->real_num_tx_queues;
6683 return txq;
6684 }
6685
6686 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6687 if (skb->priority == TC_PRIO_CONTROL)
6688 txq = adapter->ring_feature[RING_F_DCB].indices-1;
6689 else
6690 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6691 >> 13;
6692 return txq;
6693 }
6694
6695 return skb_tx_hash(dev, skb);
6696 }
6697
6698 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6699 struct ixgbe_adapter *adapter,
6700 struct ixgbe_ring *tx_ring)
6701 {
6702 unsigned int first;
6703 unsigned int tx_flags = 0;
6704 u8 hdr_len = 0;
6705 int tso;
6706 int count = 0;
6707 unsigned int f;
6708 __be16 protocol;
6709
6710 protocol = vlan_get_protocol(skb);
6711
6712 if (vlan_tx_tag_present(skb)) {
6713 tx_flags |= vlan_tx_tag_get(skb);
6714 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6715 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6716 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6717 }
6718 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6719 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6720 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6721 skb->priority != TC_PRIO_CONTROL) {
6722 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6723 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6724 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6725 }
6726
6727 #ifdef IXGBE_FCOE
6728 /* for FCoE with DCB, we force the priority to what
6729 * was specified by the switch */
6730 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6731 (protocol == htons(ETH_P_FCOE) ||
6732 protocol == htons(ETH_P_FIP))) {
6733 #ifdef CONFIG_IXGBE_DCB
6734 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6735 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6736 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6737 tx_flags |= ((adapter->fcoe.up << 13)
6738 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6739 }
6740 #endif
6741 /* flag for FCoE offloads */
6742 if (protocol == htons(ETH_P_FCOE))
6743 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6744 }
6745 #endif
6746
6747 /* four things can cause us to need a context descriptor */
6748 if (skb_is_gso(skb) ||
6749 (skb->ip_summed == CHECKSUM_PARTIAL) ||
6750 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6751 (tx_flags & IXGBE_TX_FLAGS_FCOE))
6752 count++;
6753
6754 count += TXD_USE_COUNT(skb_headlen(skb));
6755 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6756 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6757
6758 if (ixgbe_maybe_stop_tx(tx_ring, count)) {
6759 tx_ring->tx_stats.tx_busy++;
6760 return NETDEV_TX_BUSY;
6761 }
6762
6763 first = tx_ring->next_to_use;
6764 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6765 #ifdef IXGBE_FCOE
6766 /* setup tx offload for FCoE */
6767 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6768 if (tso < 0) {
6769 dev_kfree_skb_any(skb);
6770 return NETDEV_TX_OK;
6771 }
6772 if (tso)
6773 tx_flags |= IXGBE_TX_FLAGS_FSO;
6774 #endif /* IXGBE_FCOE */
6775 } else {
6776 if (protocol == htons(ETH_P_IP))
6777 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6778 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6779 protocol);
6780 if (tso < 0) {
6781 dev_kfree_skb_any(skb);
6782 return NETDEV_TX_OK;
6783 }
6784
6785 if (tso)
6786 tx_flags |= IXGBE_TX_FLAGS_TSO;
6787 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6788 protocol) &&
6789 (skb->ip_summed == CHECKSUM_PARTIAL))
6790 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6791 }
6792
6793 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6794 if (count) {
6795 /* add the ATR filter if ATR is on */
6796 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6797 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6798 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
6799 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6800
6801 } else {
6802 dev_kfree_skb_any(skb);
6803 tx_ring->tx_buffer_info[first].time_stamp = 0;
6804 tx_ring->next_to_use = first;
6805 }
6806
6807 return NETDEV_TX_OK;
6808 }
6809
6810 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6811 {
6812 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6813 struct ixgbe_ring *tx_ring;
6814
6815 tx_ring = adapter->tx_ring[skb->queue_mapping];
6816 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6817 }
6818
6819 /**
6820 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6821 * @netdev: network interface device structure
6822 * @p: pointer to an address structure
6823 *
6824 * Returns 0 on success, negative on failure
6825 **/
6826 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6827 {
6828 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6829 struct ixgbe_hw *hw = &adapter->hw;
6830 struct sockaddr *addr = p;
6831
6832 if (!is_valid_ether_addr(addr->sa_data))
6833 return -EADDRNOTAVAIL;
6834
6835 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6836 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6837
6838 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6839 IXGBE_RAH_AV);
6840
6841 return 0;
6842 }
6843
6844 static int
6845 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6846 {
6847 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6848 struct ixgbe_hw *hw = &adapter->hw;
6849 u16 value;
6850 int rc;
6851
6852 if (prtad != hw->phy.mdio.prtad)
6853 return -EINVAL;
6854 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6855 if (!rc)
6856 rc = value;
6857 return rc;
6858 }
6859
6860 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6861 u16 addr, u16 value)
6862 {
6863 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6864 struct ixgbe_hw *hw = &adapter->hw;
6865
6866 if (prtad != hw->phy.mdio.prtad)
6867 return -EINVAL;
6868 return hw->phy.ops.write_reg(hw, addr, devad, value);
6869 }
6870
6871 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6872 {
6873 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6874
6875 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6876 }
6877
6878 /**
6879 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6880 * netdev->dev_addrs
6881 * @netdev: network interface device structure
6882 *
6883 * Returns non-zero on failure
6884 **/
6885 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6886 {
6887 int err = 0;
6888 struct ixgbe_adapter *adapter = netdev_priv(dev);
6889 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6890
6891 if (is_valid_ether_addr(mac->san_addr)) {
6892 rtnl_lock();
6893 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6894 rtnl_unlock();
6895 }
6896 return err;
6897 }
6898
6899 /**
6900 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6901 * netdev->dev_addrs
6902 * @netdev: network interface device structure
6903 *
6904 * Returns non-zero on failure
6905 **/
6906 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6907 {
6908 int err = 0;
6909 struct ixgbe_adapter *adapter = netdev_priv(dev);
6910 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6911
6912 if (is_valid_ether_addr(mac->san_addr)) {
6913 rtnl_lock();
6914 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6915 rtnl_unlock();
6916 }
6917 return err;
6918 }
6919
6920 #ifdef CONFIG_NET_POLL_CONTROLLER
6921 /*
6922 * Polling 'interrupt' - used by things like netconsole to send skbs
6923 * without having to re-enable interrupts. It's not called while
6924 * the interrupt routine is executing.
6925 */
6926 static void ixgbe_netpoll(struct net_device *netdev)
6927 {
6928 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6929 int i;
6930
6931 /* if interface is down do nothing */
6932 if (test_bit(__IXGBE_DOWN, &adapter->state))
6933 return;
6934
6935 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6936 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6937 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6938 for (i = 0; i < num_q_vectors; i++) {
6939 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6940 ixgbe_msix_clean_many(0, q_vector);
6941 }
6942 } else {
6943 ixgbe_intr(adapter->pdev->irq, netdev);
6944 }
6945 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6946 }
6947 #endif
6948
6949 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6950 struct rtnl_link_stats64 *stats)
6951 {
6952 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6953 int i;
6954
6955 rcu_read_lock();
6956 for (i = 0; i < adapter->num_rx_queues; i++) {
6957 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6958 u64 bytes, packets;
6959 unsigned int start;
6960
6961 if (ring) {
6962 do {
6963 start = u64_stats_fetch_begin_bh(&ring->syncp);
6964 packets = ring->stats.packets;
6965 bytes = ring->stats.bytes;
6966 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6967 stats->rx_packets += packets;
6968 stats->rx_bytes += bytes;
6969 }
6970 }
6971
6972 for (i = 0; i < adapter->num_tx_queues; i++) {
6973 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6974 u64 bytes, packets;
6975 unsigned int start;
6976
6977 if (ring) {
6978 do {
6979 start = u64_stats_fetch_begin_bh(&ring->syncp);
6980 packets = ring->stats.packets;
6981 bytes = ring->stats.bytes;
6982 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6983 stats->tx_packets += packets;
6984 stats->tx_bytes += bytes;
6985 }
6986 }
6987 rcu_read_unlock();
6988 /* following stats updated by ixgbe_watchdog_task() */
6989 stats->multicast = netdev->stats.multicast;
6990 stats->rx_errors = netdev->stats.rx_errors;
6991 stats->rx_length_errors = netdev->stats.rx_length_errors;
6992 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6993 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6994 return stats;
6995 }
6996
6997
6998 static const struct net_device_ops ixgbe_netdev_ops = {
6999 .ndo_open = ixgbe_open,
7000 .ndo_stop = ixgbe_close,
7001 .ndo_start_xmit = ixgbe_xmit_frame,
7002 .ndo_select_queue = ixgbe_select_queue,
7003 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7004 .ndo_set_multicast_list = ixgbe_set_rx_mode,
7005 .ndo_validate_addr = eth_validate_addr,
7006 .ndo_set_mac_address = ixgbe_set_mac,
7007 .ndo_change_mtu = ixgbe_change_mtu,
7008 .ndo_tx_timeout = ixgbe_tx_timeout,
7009 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7010 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7011 .ndo_do_ioctl = ixgbe_ioctl,
7012 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7013 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7014 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7015 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7016 .ndo_get_stats64 = ixgbe_get_stats64,
7017 #ifdef CONFIG_NET_POLL_CONTROLLER
7018 .ndo_poll_controller = ixgbe_netpoll,
7019 #endif
7020 #ifdef IXGBE_FCOE
7021 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7022 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7023 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7024 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7025 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7026 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7027 #endif /* IXGBE_FCOE */
7028 };
7029
7030 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7031 const struct ixgbe_info *ii)
7032 {
7033 #ifdef CONFIG_PCI_IOV
7034 struct ixgbe_hw *hw = &adapter->hw;
7035 int err;
7036
7037 if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
7038 return;
7039
7040 /* The 82599 supports up to 64 VFs per physical function
7041 * but this implementation limits allocation to 63 so that
7042 * basic networking resources are still available to the
7043 * physical function
7044 */
7045 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7046 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7047 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7048 if (err) {
7049 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
7050 goto err_novfs;
7051 }
7052 /* If call to enable VFs succeeded then allocate memory
7053 * for per VF control structures.
7054 */
7055 adapter->vfinfo =
7056 kcalloc(adapter->num_vfs,
7057 sizeof(struct vf_data_storage), GFP_KERNEL);
7058 if (adapter->vfinfo) {
7059 /* Now that we're sure SR-IOV is enabled
7060 * and memory allocated set up the mailbox parameters
7061 */
7062 ixgbe_init_mbx_params_pf(hw);
7063 memcpy(&hw->mbx.ops, ii->mbx_ops,
7064 sizeof(hw->mbx.ops));
7065
7066 /* Disable RSC when in SR-IOV mode */
7067 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7068 IXGBE_FLAG2_RSC_ENABLED);
7069 return;
7070 }
7071
7072 /* Oh oh */
7073 e_err(probe, "Unable to allocate memory for VF Data Storage - "
7074 "SRIOV disabled\n");
7075 pci_disable_sriov(adapter->pdev);
7076
7077 err_novfs:
7078 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7079 adapter->num_vfs = 0;
7080 #endif /* CONFIG_PCI_IOV */
7081 }
7082
7083 /**
7084 * ixgbe_probe - Device Initialization Routine
7085 * @pdev: PCI device information struct
7086 * @ent: entry in ixgbe_pci_tbl
7087 *
7088 * Returns 0 on success, negative on failure
7089 *
7090 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7091 * The OS initialization, configuring of the adapter private structure,
7092 * and a hardware reset occur.
7093 **/
7094 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7095 const struct pci_device_id *ent)
7096 {
7097 struct net_device *netdev;
7098 struct ixgbe_adapter *adapter = NULL;
7099 struct ixgbe_hw *hw;
7100 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7101 static int cards_found;
7102 int i, err, pci_using_dac;
7103 u8 part_str[IXGBE_PBANUM_LENGTH];
7104 unsigned int indices = num_possible_cpus();
7105 #ifdef IXGBE_FCOE
7106 u16 device_caps;
7107 #endif
7108 u32 eec;
7109
7110 /* Catch broken hardware that put the wrong VF device ID in
7111 * the PCIe SR-IOV capability.
7112 */
7113 if (pdev->is_virtfn) {
7114 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7115 pci_name(pdev), pdev->vendor, pdev->device);
7116 return -EINVAL;
7117 }
7118
7119 err = pci_enable_device_mem(pdev);
7120 if (err)
7121 return err;
7122
7123 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7124 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7125 pci_using_dac = 1;
7126 } else {
7127 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7128 if (err) {
7129 err = dma_set_coherent_mask(&pdev->dev,
7130 DMA_BIT_MASK(32));
7131 if (err) {
7132 dev_err(&pdev->dev,
7133 "No usable DMA configuration, aborting\n");
7134 goto err_dma;
7135 }
7136 }
7137 pci_using_dac = 0;
7138 }
7139
7140 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7141 IORESOURCE_MEM), ixgbe_driver_name);
7142 if (err) {
7143 dev_err(&pdev->dev,
7144 "pci_request_selected_regions failed 0x%x\n", err);
7145 goto err_pci_reg;
7146 }
7147
7148 pci_enable_pcie_error_reporting(pdev);
7149
7150 pci_set_master(pdev);
7151 pci_save_state(pdev);
7152
7153 if (ii->mac == ixgbe_mac_82598EB)
7154 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7155 else
7156 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7157
7158 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
7159 #ifdef IXGBE_FCOE
7160 indices += min_t(unsigned int, num_possible_cpus(),
7161 IXGBE_MAX_FCOE_INDICES);
7162 #endif
7163 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7164 if (!netdev) {
7165 err = -ENOMEM;
7166 goto err_alloc_etherdev;
7167 }
7168
7169 SET_NETDEV_DEV(netdev, &pdev->dev);
7170
7171 adapter = netdev_priv(netdev);
7172 pci_set_drvdata(pdev, adapter);
7173
7174 adapter->netdev = netdev;
7175 adapter->pdev = pdev;
7176 hw = &adapter->hw;
7177 hw->back = adapter;
7178 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7179
7180 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7181 pci_resource_len(pdev, 0));
7182 if (!hw->hw_addr) {
7183 err = -EIO;
7184 goto err_ioremap;
7185 }
7186
7187 for (i = 1; i <= 5; i++) {
7188 if (pci_resource_len(pdev, i) == 0)
7189 continue;
7190 }
7191
7192 netdev->netdev_ops = &ixgbe_netdev_ops;
7193 ixgbe_set_ethtool_ops(netdev);
7194 netdev->watchdog_timeo = 5 * HZ;
7195 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7196
7197 adapter->bd_number = cards_found;
7198
7199 /* Setup hw api */
7200 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7201 hw->mac.type = ii->mac;
7202
7203 /* EEPROM */
7204 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7205 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7206 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7207 if (!(eec & (1 << 8)))
7208 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7209
7210 /* PHY */
7211 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7212 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7213 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7214 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7215 hw->phy.mdio.mmds = 0;
7216 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7217 hw->phy.mdio.dev = netdev;
7218 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7219 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7220
7221 /* set up this timer and work struct before calling get_invariants
7222 * which might start the timer
7223 */
7224 init_timer(&adapter->sfp_timer);
7225 adapter->sfp_timer.function = ixgbe_sfp_timer;
7226 adapter->sfp_timer.data = (unsigned long) adapter;
7227
7228 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
7229
7230 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
7231 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
7232
7233 /* a new SFP+ module arrival, called from GPI SDP2 context */
7234 INIT_WORK(&adapter->sfp_config_module_task,
7235 ixgbe_sfp_config_module_task);
7236
7237 ii->get_invariants(hw);
7238
7239 /* setup the private structure */
7240 err = ixgbe_sw_init(adapter);
7241 if (err)
7242 goto err_sw_init;
7243
7244 /* Make it possible the adapter to be woken up via WOL */
7245 switch (adapter->hw.mac.type) {
7246 case ixgbe_mac_82599EB:
7247 case ixgbe_mac_X540:
7248 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7249 break;
7250 default:
7251 break;
7252 }
7253
7254 /*
7255 * If there is a fan on this device and it has failed log the
7256 * failure.
7257 */
7258 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7259 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7260 if (esdp & IXGBE_ESDP_SDP1)
7261 e_crit(probe, "Fan has stopped, replace the adapter\n");
7262 }
7263
7264 /* reset_hw fills in the perm_addr as well */
7265 hw->phy.reset_if_overtemp = true;
7266 err = hw->mac.ops.reset_hw(hw);
7267 hw->phy.reset_if_overtemp = false;
7268 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7269 hw->mac.type == ixgbe_mac_82598EB) {
7270 /*
7271 * Start a kernel thread to watch for a module to arrive.
7272 * Only do this for 82598, since 82599 will generate
7273 * interrupts on module arrival.
7274 */
7275 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7276 mod_timer(&adapter->sfp_timer,
7277 round_jiffies(jiffies + (2 * HZ)));
7278 err = 0;
7279 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7280 e_dev_err("failed to initialize because an unsupported SFP+ "
7281 "module type was detected.\n");
7282 e_dev_err("Reload the driver after installing a supported "
7283 "module.\n");
7284 goto err_sw_init;
7285 } else if (err) {
7286 e_dev_err("HW Init failed: %d\n", err);
7287 goto err_sw_init;
7288 }
7289
7290 ixgbe_probe_vf(adapter, ii);
7291
7292 netdev->features = NETIF_F_SG |
7293 NETIF_F_IP_CSUM |
7294 NETIF_F_HW_VLAN_TX |
7295 NETIF_F_HW_VLAN_RX |
7296 NETIF_F_HW_VLAN_FILTER;
7297
7298 netdev->features |= NETIF_F_IPV6_CSUM;
7299 netdev->features |= NETIF_F_TSO;
7300 netdev->features |= NETIF_F_TSO6;
7301 netdev->features |= NETIF_F_GRO;
7302
7303 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
7304 netdev->features |= NETIF_F_SCTP_CSUM;
7305
7306 netdev->vlan_features |= NETIF_F_TSO;
7307 netdev->vlan_features |= NETIF_F_TSO6;
7308 netdev->vlan_features |= NETIF_F_IP_CSUM;
7309 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7310 netdev->vlan_features |= NETIF_F_SG;
7311
7312 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7313 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7314 IXGBE_FLAG_DCB_ENABLED);
7315 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7316 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
7317
7318 #ifdef CONFIG_IXGBE_DCB
7319 netdev->dcbnl_ops = &dcbnl_ops;
7320 #endif
7321
7322 #ifdef IXGBE_FCOE
7323 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7324 if (hw->mac.ops.get_device_caps) {
7325 hw->mac.ops.get_device_caps(hw, &device_caps);
7326 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7327 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7328 }
7329 }
7330 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7331 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7332 netdev->vlan_features |= NETIF_F_FSO;
7333 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7334 }
7335 #endif /* IXGBE_FCOE */
7336 if (pci_using_dac) {
7337 netdev->features |= NETIF_F_HIGHDMA;
7338 netdev->vlan_features |= NETIF_F_HIGHDMA;
7339 }
7340
7341 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7342 netdev->features |= NETIF_F_LRO;
7343
7344 /* make sure the EEPROM is good */
7345 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7346 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7347 err = -EIO;
7348 goto err_eeprom;
7349 }
7350
7351 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7352 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7353
7354 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7355 e_dev_err("invalid MAC address\n");
7356 err = -EIO;
7357 goto err_eeprom;
7358 }
7359
7360 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7361 if (hw->mac.ops.disable_tx_laser &&
7362 ((hw->phy.multispeed_fiber) ||
7363 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7364 (hw->mac.type == ixgbe_mac_82599EB))))
7365 hw->mac.ops.disable_tx_laser(hw);
7366
7367 init_timer(&adapter->watchdog_timer);
7368 adapter->watchdog_timer.function = ixgbe_watchdog;
7369 adapter->watchdog_timer.data = (unsigned long)adapter;
7370
7371 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
7372 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
7373
7374 err = ixgbe_init_interrupt_scheme(adapter);
7375 if (err)
7376 goto err_sw_init;
7377
7378 switch (pdev->device) {
7379 case IXGBE_DEV_ID_82599_SFP:
7380 /* Only this subdevice supports WOL */
7381 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7382 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7383 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7384 break;
7385 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7386 /* All except this subdevice support WOL */
7387 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7388 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7389 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7390 break;
7391 case IXGBE_DEV_ID_82599_KX4:
7392 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7393 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7394 break;
7395 default:
7396 adapter->wol = 0;
7397 break;
7398 }
7399 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7400
7401 /* pick up the PCI bus settings for reporting later */
7402 hw->mac.ops.get_bus_info(hw);
7403
7404 /* print bus type/speed/width info */
7405 e_dev_info("(PCI Express:%s:%s) %pM\n",
7406 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
7407 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
7408 "Unknown"),
7409 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7410 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7411 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7412 "Unknown"),
7413 netdev->dev_addr);
7414
7415 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7416 if (err)
7417 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7418 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7419 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7420 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7421 part_str);
7422 else
7423 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7424 hw->mac.type, hw->phy.type, part_str);
7425
7426 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7427 e_dev_warn("PCI-Express bandwidth available for this card is "
7428 "not sufficient for optimal performance.\n");
7429 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7430 "is required.\n");
7431 }
7432
7433 /* save off EEPROM version number */
7434 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7435
7436 /* reset the hardware with the new settings */
7437 err = hw->mac.ops.start_hw(hw);
7438
7439 if (err == IXGBE_ERR_EEPROM_VERSION) {
7440 /* We are running on a pre-production device, log a warning */
7441 e_dev_warn("This device is a pre-production adapter/LOM. "
7442 "Please be aware there may be issues associated "
7443 "with your hardware. If you are experiencing "
7444 "problems please contact your Intel or hardware "
7445 "representative who provided you with this "
7446 "hardware.\n");
7447 }
7448 strcpy(netdev->name, "eth%d");
7449 err = register_netdev(netdev);
7450 if (err)
7451 goto err_register;
7452
7453 /* carrier off reporting is important to ethtool even BEFORE open */
7454 netif_carrier_off(netdev);
7455
7456 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7457 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7458 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7459
7460 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7461 INIT_WORK(&adapter->check_overtemp_task,
7462 ixgbe_check_overtemp_task);
7463 #ifdef CONFIG_IXGBE_DCA
7464 if (dca_add_requester(&pdev->dev) == 0) {
7465 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7466 ixgbe_setup_dca(adapter);
7467 }
7468 #endif
7469 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7470 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7471 for (i = 0; i < adapter->num_vfs; i++)
7472 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7473 }
7474
7475 /* add san mac addr to netdev */
7476 ixgbe_add_sanmac_netdev(netdev);
7477
7478 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7479 cards_found++;
7480 return 0;
7481
7482 err_register:
7483 ixgbe_release_hw_control(adapter);
7484 ixgbe_clear_interrupt_scheme(adapter);
7485 err_sw_init:
7486 err_eeprom:
7487 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7488 ixgbe_disable_sriov(adapter);
7489 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7490 del_timer_sync(&adapter->sfp_timer);
7491 cancel_work_sync(&adapter->sfp_task);
7492 cancel_work_sync(&adapter->multispeed_fiber_task);
7493 cancel_work_sync(&adapter->sfp_config_module_task);
7494 iounmap(hw->hw_addr);
7495 err_ioremap:
7496 free_netdev(netdev);
7497 err_alloc_etherdev:
7498 pci_release_selected_regions(pdev,
7499 pci_select_bars(pdev, IORESOURCE_MEM));
7500 err_pci_reg:
7501 err_dma:
7502 pci_disable_device(pdev);
7503 return err;
7504 }
7505
7506 /**
7507 * ixgbe_remove - Device Removal Routine
7508 * @pdev: PCI device information struct
7509 *
7510 * ixgbe_remove is called by the PCI subsystem to alert the driver
7511 * that it should release a PCI device. The could be caused by a
7512 * Hot-Plug event, or because the driver is going to be removed from
7513 * memory.
7514 **/
7515 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7516 {
7517 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7518 struct net_device *netdev = adapter->netdev;
7519
7520 set_bit(__IXGBE_DOWN, &adapter->state);
7521
7522 /*
7523 * The timers may be rescheduled, so explicitly disable them
7524 * from being rescheduled.
7525 */
7526 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7527 del_timer_sync(&adapter->watchdog_timer);
7528 del_timer_sync(&adapter->sfp_timer);
7529
7530 cancel_work_sync(&adapter->watchdog_task);
7531 cancel_work_sync(&adapter->sfp_task);
7532 cancel_work_sync(&adapter->multispeed_fiber_task);
7533 cancel_work_sync(&adapter->sfp_config_module_task);
7534 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7535 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7536 cancel_work_sync(&adapter->fdir_reinit_task);
7537 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7538 cancel_work_sync(&adapter->check_overtemp_task);
7539
7540 #ifdef CONFIG_IXGBE_DCA
7541 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7542 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7543 dca_remove_requester(&pdev->dev);
7544 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7545 }
7546
7547 #endif
7548 #ifdef IXGBE_FCOE
7549 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7550 ixgbe_cleanup_fcoe(adapter);
7551
7552 #endif /* IXGBE_FCOE */
7553
7554 /* remove the added san mac */
7555 ixgbe_del_sanmac_netdev(netdev);
7556
7557 if (netdev->reg_state == NETREG_REGISTERED)
7558 unregister_netdev(netdev);
7559
7560 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7561 ixgbe_disable_sriov(adapter);
7562
7563 ixgbe_clear_interrupt_scheme(adapter);
7564
7565 ixgbe_release_hw_control(adapter);
7566
7567 iounmap(adapter->hw.hw_addr);
7568 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7569 IORESOURCE_MEM));
7570
7571 e_dev_info("complete\n");
7572
7573 free_netdev(netdev);
7574
7575 pci_disable_pcie_error_reporting(pdev);
7576
7577 pci_disable_device(pdev);
7578 }
7579
7580 /**
7581 * ixgbe_io_error_detected - called when PCI error is detected
7582 * @pdev: Pointer to PCI device
7583 * @state: The current pci connection state
7584 *
7585 * This function is called after a PCI bus error affecting
7586 * this device has been detected.
7587 */
7588 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7589 pci_channel_state_t state)
7590 {
7591 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7592 struct net_device *netdev = adapter->netdev;
7593
7594 netif_device_detach(netdev);
7595
7596 if (state == pci_channel_io_perm_failure)
7597 return PCI_ERS_RESULT_DISCONNECT;
7598
7599 if (netif_running(netdev))
7600 ixgbe_down(adapter);
7601 pci_disable_device(pdev);
7602
7603 /* Request a slot reset. */
7604 return PCI_ERS_RESULT_NEED_RESET;
7605 }
7606
7607 /**
7608 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7609 * @pdev: Pointer to PCI device
7610 *
7611 * Restart the card from scratch, as if from a cold-boot.
7612 */
7613 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7614 {
7615 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7616 pci_ers_result_t result;
7617 int err;
7618
7619 if (pci_enable_device_mem(pdev)) {
7620 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7621 result = PCI_ERS_RESULT_DISCONNECT;
7622 } else {
7623 pci_set_master(pdev);
7624 pci_restore_state(pdev);
7625 pci_save_state(pdev);
7626
7627 pci_wake_from_d3(pdev, false);
7628
7629 ixgbe_reset(adapter);
7630 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7631 result = PCI_ERS_RESULT_RECOVERED;
7632 }
7633
7634 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7635 if (err) {
7636 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7637 "failed 0x%0x\n", err);
7638 /* non-fatal, continue */
7639 }
7640
7641 return result;
7642 }
7643
7644 /**
7645 * ixgbe_io_resume - called when traffic can start flowing again.
7646 * @pdev: Pointer to PCI device
7647 *
7648 * This callback is called when the error recovery driver tells us that
7649 * its OK to resume normal operation.
7650 */
7651 static void ixgbe_io_resume(struct pci_dev *pdev)
7652 {
7653 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7654 struct net_device *netdev = adapter->netdev;
7655
7656 if (netif_running(netdev)) {
7657 if (ixgbe_up(adapter)) {
7658 e_info(probe, "ixgbe_up failed after reset\n");
7659 return;
7660 }
7661 }
7662
7663 netif_device_attach(netdev);
7664 }
7665
7666 static struct pci_error_handlers ixgbe_err_handler = {
7667 .error_detected = ixgbe_io_error_detected,
7668 .slot_reset = ixgbe_io_slot_reset,
7669 .resume = ixgbe_io_resume,
7670 };
7671
7672 static struct pci_driver ixgbe_driver = {
7673 .name = ixgbe_driver_name,
7674 .id_table = ixgbe_pci_tbl,
7675 .probe = ixgbe_probe,
7676 .remove = __devexit_p(ixgbe_remove),
7677 #ifdef CONFIG_PM
7678 .suspend = ixgbe_suspend,
7679 .resume = ixgbe_resume,
7680 #endif
7681 .shutdown = ixgbe_shutdown,
7682 .err_handler = &ixgbe_err_handler
7683 };
7684
7685 /**
7686 * ixgbe_init_module - Driver Registration Routine
7687 *
7688 * ixgbe_init_module is the first routine called when the driver is
7689 * loaded. All it does is register with the PCI subsystem.
7690 **/
7691 static int __init ixgbe_init_module(void)
7692 {
7693 int ret;
7694 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7695 pr_info("%s\n", ixgbe_copyright);
7696
7697 #ifdef CONFIG_IXGBE_DCA
7698 dca_register_notify(&dca_notifier);
7699 #endif
7700
7701 ret = pci_register_driver(&ixgbe_driver);
7702 return ret;
7703 }
7704
7705 module_init(ixgbe_init_module);
7706
7707 /**
7708 * ixgbe_exit_module - Driver Exit Cleanup Routine
7709 *
7710 * ixgbe_exit_module is called just before the driver is removed
7711 * from memory.
7712 **/
7713 static void __exit ixgbe_exit_module(void)
7714 {
7715 #ifdef CONFIG_IXGBE_DCA
7716 dca_unregister_notify(&dca_notifier);
7717 #endif
7718 pci_unregister_driver(&ixgbe_driver);
7719 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7720 }
7721
7722 #ifdef CONFIG_IXGBE_DCA
7723 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7724 void *p)
7725 {
7726 int ret_val;
7727
7728 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7729 __ixgbe_notify_dca);
7730
7731 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7732 }
7733
7734 #endif /* CONFIG_IXGBE_DCA */
7735
7736 module_exit(ixgbe_exit_module);
7737
7738 /* ixgbe_main.c */
Linux kernel - Deliverables
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